/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      d
/*
 * Device Tree file for Marvell Armada 375 evaluation board
 * (DB-88F6720)
 *
 *  Copyright (C) 2014 Marvell
 *
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-375.dtsi"

/ {
	model = "Marvell Armada 375 Development Board";
	compatible = "marvell,a375-db", "marvell,armada375";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x40000000>; /* 1 GB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
			  MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
			  MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;

		internal-regs {
			spi@10600 {
				pinctrl-0 = <&spi0_pins>;
				pinctrl-names = "default";
				/*
				 * SPI conflicts with NAND, so we disable it
				 * here, and select NAND as the enabled device
				 * by default.
				 */
				status = "disabled";

				spi-flash@0 {
					#address-cells = <1>;
					#size-cells = <1>;
					compatible = "n25q128a13", "jedec,spi-nor";
					reg = <0>; /* Chip select 0 */
					spi-max-frequency = <108000000>;
				};
			};

			i2c@11000 {
				status = "okay";
				clock-frequency = <100000>;
				pinctrl-0 = <&i2c0_pins>;
				pinctrl-names = "default";
			};

			i2c@11100 {
				status = "okay";
				clock-frequency = <100000>;
				pinctrl-0 = <&i2c1_pins>;
				pinctrl-names = "default";
			};

			serial@12000 {
				status = "okay";
			};

			pinctrl {
				sdio_st_pins: sdio-st-pins {
					marvell,pins = "mpp44", "mpp45";
					marvell,function = "gpio";
				};
			};

			sata@a0000 {
				status = "okay";
				nr-ports = <2>;
			};

			nand: nand@d0000 {
				pinctrl-0 = <&nand_pins>;
				pinctrl-names = "default";
				status = "okay";
				num-cs = <1>;
				marvell,nand-keep-config;
				marvell,nand-enable-arbiter;
				nand-on-flash-bbt;
				nand-ecc-strength = <4>;
				nand-ecc-step-size = <512>;

				partition@0 {
					label = "U-Boot";
					reg = <0 0x800000>;
				};
				partition@800000 {
					label = "Linux";
					reg = <0x800000 0x800000>;
				};
				partition@1000000 {
					label = "Filesystem";
					reg = <0x1000000 0x3f000000>;
				};
			};

			usb@54000 {
				status = "okay";
			};

			usb3@58000 {
				status = "okay";
			};

			mvsdio@d4000 {
				pinctrl-0 = <&sdio_pins &sdio_st_pins>;
				pinctrl-names = "default";
				status = "okay";
				cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
				wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
			};

			mdio {
				phy0: ethernet-phy@0 {
					reg = <0>;
				};

				phy3: ethernet-phy@3 {
					reg = <3>;
				};
			};

			ethernet@f0000 {
				status = "okay";

				eth0@c4000 {
					status = "okay";
					phy = <&phy0>;
					phy-mode = "rgmii-id";
				};

				eth1@c5000 {
					status = "okay";
					phy = <&phy3>;
					phy-mode = "gmii";
				};
			};
		};

		pcie-controller {
			status = "okay";
			/*
			 * The two PCIe units are accessible through
			 * standard PCIe slots on the board.
			 */
			pcie@1,0 {
				/* Port 0, Lane 0 */
				status = "okay";
			};
			pcie@2,0 {
				/* Port 1, Lane 0 */
				status = "okay";
			};
		};
	};
};