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An Intel MIC X100 device is a PCIe form factor add-in coprocessor
card based on the Intel Many Integrated Core (MIC) architecture
that runs a Linux OS. It is a PCIe endpoint in a platform and therefore
implements the three required standard address spaces i.e. configuration,
memory and I/O. The host OS loads a device driver as is typical for
PCIe devices. The card itself runs a bootstrap after reset that
transfers control to the card OS downloaded from the host driver. The
host driver supports OSPM suspend and resume operations. It shuts down
the card during suspend and reboots the card OS during resume.
The card OS as shipped by Intel is a Linux kernel with modifications
for the X100 devices.

Since it is a PCIe card, it does not have the ability to host hardware
devices for networking, storage and console. We provide these devices
on X100 coprocessors thus enabling a self-bootable equivalent environment
for applications. A key benefit of our solution is that it leverages
the standard virtio framework for network, disk and console devices,
though in our case the virtio framework is used across a PCIe bus.

MIC PCIe card has a dma controller with 8 channels. These channels are
shared between the host s/w and the card s/w. 0 to 3 are used by host
and 4 to 7 by card. As the dma device doesn't show up as PCIe device,
a virtual bus called mic bus is created and virtual dma devices are
created on it by the host/card drivers. On host the channels are private
and used only by the host driver to transfer data for the virtio devices.

Here is a block diagram of the various components described above. The
virtio backends are situated on the host rather than the card given better
single threaded performance for the host compared to MIC, the ability of
the host to initiate DMA's to/from the card using the MIC DMA engine and
the fact that the virtio block storage backend can only be on the host.

                                      |
               +----------+           |             +----------+
               | Card OS  |           |             | Host OS  |
               +----------+           |             +----------+
                                      |
        +-------+ +--------+ +------+ | +---------+  +--------+ +--------+
        | Virtio| |Virtio  | |Virtio| | |Virtio   |  |Virtio  | |Virtio  |
        | Net   | |Console | |Block | | |Net      |  |Console | |Block   |
        | Driver| |Driver  | |Driver| | |backend  |  |backend | |backend |
        +-------+ +--------+ +------+ | +---------+  +--------+ +--------+
            |         |         |     |      |            |         |
            |         |         |     |User  |            |         |
            |         |         |     |------|------------|---------|-------
            +-------------------+     |Kernel +--------------------------+
                      |               |       | Virtio over PCIe IOCTLs  |
                      |               |       +--------------------------+
+-----------+         |               |                   |  +-----------+
| MIC DMA   |         |               |                   |  | MIC DMA   |
| Driver    |         |               |                   |  | Driver    |
+-----------+         |               |                   |  +-----------+
      |               |               |                   |        |
+---------------+     |               |                   |  +----------------+
|MIC virtual Bus|     |               |                   |  |MIC virtual Bus |
+---------------+     |               |                   |  +----------------+
      |               |               |                   |              |
      |   +--------------+            |            +---------------+     |
      |   |Intel MIC     |            |            |Intel MIC      |     |
      +---|Card Driver   |            |            |Host Driver    |     |
          +--------------+            |            +---------------+-----+
                      |               |                   |
             +-------------------------------------------------------------+
             |                                                             |
             |                    PCIe Bus                                 |
             +-------------------------------------------------------------+
ine IOP3XX_ICR_MSTART 0x0001 /* 1=initiate a START */ #define IOP3XX_ISR_BERRD 0x0400 /* 1=BUS ERROR Detected */ #define IOP3XX_ISR_SAD 0x0200 /* 1=Slave ADdress Detected */ #define IOP3XX_ISR_GCAD 0x0100 /* 1=General Call Address Detected */ #define IOP3XX_ISR_RXFULL 0x0080 /* 1=Receive Full */ #define IOP3XX_ISR_TXEMPTY 0x0040 /* 1=Transmit Empty */ #define IOP3XX_ISR_ALD 0x0020 /* 1=Arbitration Loss Detected */ #define IOP3XX_ISR_SSD 0x0010 /* 1=Slave STOP Detected */ #define IOP3XX_ISR_BBUSY 0x0008 /* 1=Bus BUSY */ #define IOP3XX_ISR_UNITBUSY 0x0004 /* 1=Unit Busy */ #define IOP3XX_ISR_NACK 0x0002 /* 1=Unit Rx or Tx a NACK */ #define IOP3XX_ISR_RXREAD 0x0001 /* 1=READ 0=WRITE (R/W bit of slave addr */ #define IOP3XX_ISR_CLEARBITS 0x07f0 #define IOP3XX_ISAR_SAMASK 0x007f #define IOP3XX_IDBR_MASK 0x00ff #define IOP3XX_IBMR_SCL 0x0002 #define IOP3XX_IBMR_SDA 0x0001 #define IOP3XX_GPOD_I2C0 0x00c0 /* clear these bits to enable ch0 */ #define IOP3XX_GPOD_I2C1 0x0030 /* clear these bits to enable ch1 */ #define MYSAR 0 /* default slave address */ #define I2C_ERR 321 #define I2C_ERR_BERR (I2C_ERR+0) #define I2C_ERR_ALD (I2C_ERR+1) #define CR_OFFSET 0 #define SR_OFFSET 0x4 #define SAR_OFFSET 0x8 #define DBR_OFFSET 0xc #define CCR_OFFSET 0x10 #define BMR_OFFSET 0x14 #define IOP3XX_I2C_IO_SIZE 0x18 struct i2c_algo_iop3xx_data { void __iomem *ioaddr; wait_queue_head_t waitq; spinlock_t lock; u32 SR_enabled, SR_received; int id; }; #endif /* I2C_IOP3XX_H */