diff options
Diffstat (limited to 'qemu/roms/u-boot/include/faraday')
| -rw-r--r-- | qemu/roms/u-boot/include/faraday/ftahbc020s.h | 47 | ||||
| -rw-r--r-- | qemu/roms/u-boot/include/faraday/ftpci100.h | 84 | ||||
| -rw-r--r-- | qemu/roms/u-boot/include/faraday/ftpmu010.h | 235 | ||||
| -rw-r--r-- | qemu/roms/u-boot/include/faraday/ftsdc010.h | 246 | ||||
| -rw-r--r-- | qemu/roms/u-boot/include/faraday/ftsdmc020.h | 91 | ||||
| -rw-r--r-- | qemu/roms/u-boot/include/faraday/ftsdmc021.h | 139 | ||||
| -rw-r--r-- | qemu/roms/u-boot/include/faraday/ftsmc020.h | 74 | ||||
| -rw-r--r-- | qemu/roms/u-boot/include/faraday/fttmr010.h | 61 | ||||
| -rw-r--r-- | qemu/roms/u-boot/include/faraday/ftwdt010_wdt.h | 94 |
9 files changed, 0 insertions, 1071 deletions
diff --git a/qemu/roms/u-boot/include/faraday/ftahbc020s.h b/qemu/roms/u-boot/include/faraday/ftahbc020s.h deleted file mode 100644 index ccae39095..000000000 --- a/qemu/roms/u-boot/include/faraday/ftahbc020s.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (C) 2011 Andes Technology Corporation - * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */ -#ifndef __FTAHBC020S_H -#define __FTAHBC202S_H - -/* Registers Offsets */ - -/* - * AHB Slave BSR, offset: n * 4, n=0~31 - */ -#ifndef __ASSEMBLY__ -struct ftahbc02s { - unsigned int s_bsr[32]; /* 0x00-0x7c - Slave n Base/Size Reg */ - unsigned int pcr; /* 0x80 - Priority Ctrl Reg */ - unsigned int tcrg; /* 0x84 - Transfer Ctrl Reg */ - unsigned int cr; /* 0x88 - Ctrl Reg */ -}; -#endif /* __ASSEMBLY__ */ - -/* - * FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register - */ -#define FTAHBC020S_SLAVE_BSR_BASE(x) (((x) & 0xfff) << 20) -#define FTAHBC020S_SLAVE_BSR_SIZE(x) (((x) & 0xf) << 16) -/* The value of b(16:19)SLAVE_BSR_SIZE: 1M-2048M, must be power of 2 */ -#define FTAHBC020S_BSR_SIZE(x) (ffs(x) - 1) /* size of Addr Space */ - -/* - * FTAHBC020S_PCR - Priority Control Register - */ -#define FTAHBC020S_PCR_PLEVEL_(x) (1 << (x)) /* x: 1-15 */ - -/* - * FTAHBC020S_CR - Interrupt Control Register - */ -#define FTAHBC020S_CR_INTSTS (1 << 24) -#define FTAHBC020S_CR_RESP(x) (((x) & 0x3) << 20) -#define FTAHBC020S_CR_INTSMASK (1 << 16) -#define FTAHBC020S_CR_REMAP (1 << 0) - -#endif /* __FTAHBC020S_H */ diff --git a/qemu/roms/u-boot/include/faraday/ftpci100.h b/qemu/roms/u-boot/include/faraday/ftpci100.h deleted file mode 100644 index 43152aae2..000000000 --- a/qemu/roms/u-boot/include/faraday/ftpci100.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation - * - * Copyright (C) 2010 Andes Technology Corporation - * Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com> - * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __FTPCI100_H -#define __FTPCI100_H - -/* AHB Control Registers */ -struct ftpci100_ahbc { - unsigned int iosize; /* 0x00 - I/O Space Size Signal */ - unsigned int prot; /* 0x04 - AHB Protection */ - unsigned int rsved[8]; /* 0x08-0x24 - Reserved */ - unsigned int conf; /* 0x28 - PCI Configuration */ - unsigned int data; /* 0x2c - PCI Configuration DATA */ -}; - -/* - * FTPCI100_IOSIZE_REG's constant definitions - */ -#define FTPCI100_BASE_IO_SIZE(x) (ffs(x) - 1) /* 1M - 2048M */ - -/* - * PCI Configuration Register - */ -#define PCI_INT_MASK 0x4c -#define PCI_MEM_BASE_SIZE1 0x50 -#define PCI_MEM_BASE_SIZE2 0x54 -#define PCI_MEM_BASE_SIZE3 0x58 - -/* - * PCI_INT_MASK's bit definitions - */ -#define PCI_INTA_ENABLE (1 << 22) -#define PCI_INTB_ENABLE (1 << 23) -#define PCI_INTC_ENABLE (1 << 24) -#define PCI_INTD_ENABLE (1 << 25) - -/* - * PCI_MEM_BASE_SIZE1's constant definitions - */ -#define FTPCI100_BASE_ADR_SIZE(x) ((ffs(x) - 1) << 16) /* 1M - 2048M */ - -#define FTPCI100_MAX_FUNCTIONS 20 -#define PCI_IRQ_LINES 4 - -#define MAX_BUS_NUM 256 -#define MAX_DEV_NUM 32 -#define MAX_FUN_NUM 8 - -#define PCI_MAX_BAR_PER_FUNC 6 - -/* - * PCI_MEM_SIZE - */ -#define FTPCI100_MEM_SIZE(x) (ffs(x) << 24) - -/* This definition is used by pci_ftpci_init() */ -#define FTPCI100_BRIDGE_VENDORID 0x159b -#define FTPCI100_BRIDGE_DEVICEID 0x4321 - -void pci_ftpci_init(void); - -struct pcibar { - unsigned int size; - unsigned int addr; -}; - -struct pci_config { - unsigned int bus; - unsigned int dev; /* device */ - unsigned int func; - unsigned int pin; - unsigned short v_id; /* vendor id */ - unsigned short d_id; /* device id */ - struct pcibar bar[PCI_MAX_BAR_PER_FUNC + 1]; -}; - -#endif diff --git a/qemu/roms/u-boot/include/faraday/ftpmu010.h b/qemu/roms/u-boot/include/faraday/ftpmu010.h deleted file mode 100644 index b1131e5ae..000000000 --- a/qemu/roms/u-boot/include/faraday/ftpmu010.h +++ /dev/null @@ -1,235 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Power Management Unit - */ -#ifndef __FTPMU010_H -#define __FTPMU010_H - -#ifndef __ASSEMBLY__ -struct ftpmu010 { - unsigned int IDNMBR0; /* 0x00 */ - unsigned int reserved0; /* 0x04 */ - unsigned int OSCC; /* 0x08 */ - unsigned int PMODE; /* 0x0C */ - unsigned int PMCR; /* 0x10 */ - unsigned int PED; /* 0x14 */ - unsigned int PEDSR; /* 0x18 */ - unsigned int reserved1; /* 0x1C */ - unsigned int PMSR; /* 0x20 */ - unsigned int PGSR; /* 0x24 */ - unsigned int MFPSR; /* 0x28 */ - unsigned int MISC; /* 0x2C */ - unsigned int PDLLCR0; /* 0x30 */ - unsigned int PDLLCR1; /* 0x34 */ - unsigned int AHBMCLKOFF; /* 0x38 */ - unsigned int APBMCLKOFF; /* 0x3C */ - unsigned int DCSRCR0; /* 0x40 */ - unsigned int DCSRCR1; /* 0x44 */ - unsigned int DCSRCR2; /* 0x48 */ - unsigned int SDRAMHTC; /* 0x4C */ - unsigned int PSPR0; /* 0x50 */ - unsigned int PSPR1; /* 0x54 */ - unsigned int PSPR2; /* 0x58 */ - unsigned int PSPR3; /* 0x5C */ - unsigned int PSPR4; /* 0x60 */ - unsigned int PSPR5; /* 0x64 */ - unsigned int PSPR6; /* 0x68 */ - unsigned int PSPR7; /* 0x6C */ - unsigned int PSPR8; /* 0x70 */ - unsigned int PSPR9; /* 0x74 */ - unsigned int PSPR10; /* 0x78 */ - unsigned int PSPR11; /* 0x7C */ - unsigned int PSPR12; /* 0x80 */ - unsigned int PSPR13; /* 0x84 */ - unsigned int PSPR14; /* 0x88 */ - unsigned int PSPR15; /* 0x8C */ - unsigned int AHBDMA_RACCS; /* 0x90 */ - unsigned int reserved2; /* 0x94 */ - unsigned int reserved3; /* 0x98 */ - unsigned int JSS; /* 0x9C */ - unsigned int CFC_RACC; /* 0xA0 */ - unsigned int SSP1_RACC; /* 0xA4 */ - unsigned int UART1TX_RACC; /* 0xA8 */ - unsigned int UART1RX_RACC; /* 0xAC */ - unsigned int UART2TX_RACC; /* 0xB0 */ - unsigned int UART2RX_RACC; /* 0xB4 */ - unsigned int SDC_RACC; /* 0xB8 */ - unsigned int I2SAC97_RACC; /* 0xBC */ - unsigned int IRDATX_RACC; /* 0xC0 */ - unsigned int reserved4; /* 0xC4 */ - unsigned int USBD_RACC; /* 0xC8 */ - unsigned int IRDARX_RACC; /* 0xCC */ - unsigned int IRDA_RACC; /* 0xD0 */ - unsigned int ED0_RACC; /* 0xD4 */ - unsigned int ED1_RACC; /* 0xD8 */ -}; -#endif /* __ASSEMBLY__ */ - -/* - * ID Number 0 Register - */ -#define FTPMU010_ID_A320A 0x03200000 -#define FTPMU010_ID_A320C 0x03200010 -#define FTPMU010_ID_A320D 0x03200030 - -/* - * OSC Control Register - */ -#define FTPMU010_OSCC_OSCH_TRI (1 << 11) -#define FTPMU010_OSCC_OSCH_STABLE (1 << 9) -#define FTPMU010_OSCC_OSCH_OFF (1 << 8) - -#define FTPMU010_OSCC_OSCL_TRI (1 << 3) -#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2) -#define FTPMU010_OSCC_OSCL_STABLE (1 << 1) -#define FTPMU010_OSCC_OSCL_OFF (1 << 0) - -/* - * Power Mode Register - */ -#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4) -#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7) -#define FTPMU010_PMODE_FCS (1 << 2) -#define FTPMU010_PMODE_TURBO (1 << 1) -#define FTPMU010_PMODE_SLEEP (1 << 0) - -/* - * Power Manager Status Register - */ -#define FTPMU010_PMSR_SMR (1 << 10) - -#define FTPMU010_PMSR_RDH (1 << 2) -#define FTPMU010_PMSR_PH (1 << 1) -#define FTPMU010_PMSR_CKEHLOW (1 << 0) - -/* - * Multi-Function Port Setting Register - */ -#define FTPMU010_MFPSR_DEBUGSEL (1 << 17) -#define FTPMU010_MFPSR_DMA0PINSEL (1 << 16) -#define FTPMU010_MFPSR_DMA1PINSEL (1 << 15) -#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) -#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) -#define FTPMU010_MFPSR_PWM1PINSEL (1 << 11) -#define FTPMU010_MFPSR_PWM0PINSEL (1 << 10) -#define FTPMU010_MFPSR_IRDACLKSEL (1 << 9) -#define FTPMU010_MFPSR_UARTCLKSEL (1 << 8) -#define FTPMU010_MFPSR_SSPCLKSEL (1 << 6) -#define FTPMU010_MFPSR_I2SCLKSEL (1 << 5) -#define FTPMU010_MFPSR_AC97CLKSEL (1 << 4) -#define FTPMU010_MFPSR_AC97PINSEL (1 << 3) -#define FTPMU010_MFPSR_TRIAHBDIS (1 << 1) -#define FTPMU010_MFPSR_TRIAHBDBG (1 << 0) - -/* - * PLL/DLL Control Register 0 - * Note: - * 1. FTPMU010_PDLLCR0_HCLKOUTDIS: - * Datasheet indicated it starts at bit #21 which was wrong. - * 2. FTPMU010_PDLLCR0_DLLFRAG: - * Datasheet indicated it has 2 bit which was wrong. - */ -#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20) -#define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19) -#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18) -#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17) -#define FTPMU010_PDLLCR0_DLLDIS (1 << 16) -#define FTPMU010_PDLLCR0_PLL1FRANG(cr0) (((cr0) & 0x3) << 12) -#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) & 0x1ff) << 3) -#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2) -#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1) -#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) - -/* - * SDRAM Signal Hold Time Control Register - */ -#define FTPMU010_SDRAMHTC_RCLK_DLY(x) (((x) & 0xf) << 28) -#define FTPMU010_SDRAMHTC_CTL_WCLK_DLY(x) (((x) & 0xf) << 24) -#define FTPMU010_SDRAMHTC_DAT_WCLK_DLY(x) (((x) & 0xf) << 20) -#define FTPMU010_SDRAMHTC_EBICTRL_DCSR (1 << 18) -#define FTPMU010_SDRAMHTC_EBIDATA_DCSR (1 << 17) -#define FTPMU010_SDRAMHTC_SDRAMCS_DCSR (1 << 16) -#define FTPMU010_SDRAMHTC_SDRAMCTL_DCSR (1 << 15) -#define FTPMU010_SDRAMHTC_CKE_DCSR (1 << 14) -#define FTPMU010_SDRAMHTC_DQM_DCSR (1 << 13) -#define FTPMU010_SDRAMHTC_SDCLK_DCSR (1 << 12) - -#ifndef __ASSEMBLY__ -void ftpmu010_32768osc_enable(void); -void ftpmu010_dlldis_disable(void); -void ftpmu010_mfpsr_diselect_dev(unsigned int dev); -void ftpmu010_mfpsr_select_dev(unsigned int dev); -void ftpmu010_sdram_clk_disable(unsigned int cr0); -void ftpmu010_sdramhtc_set(unsigned int val); -#endif - -#ifdef __ASSEMBLY__ -#define FTPMU010_IDNMBR0 0x00 -#define FTPMU010_reserved0 0x04 -#define FTPMU010_OSCC 0x08 -#define FTPMU010_PMODE 0x0C -#define FTPMU010_PMCR 0x10 -#define FTPMU010_PED 0x14 -#define FTPMU010_PEDSR 0x18 -#define FTPMU010_reserved1 0x1C -#define FTPMU010_PMSR 0x20 -#define FTPMU010_PGSR 0x24 -#define FTPMU010_MFPSR 0x28 -#define FTPMU010_MISC 0x2C -#define FTPMU010_PDLLCR0 0x30 -#define FTPMU010_PDLLCR1 0x34 -#define FTPMU010_AHBMCLKOFF 0x38 -#define FTPMU010_APBMCLKOFF 0x3C -#define FTPMU010_DCSRCR0 0x40 -#define FTPMU010_DCSRCR1 0x44 -#define FTPMU010_DCSRCR2 0x48 -#define FTPMU010_SDRAMHTC 0x4C -#define FTPMU010_PSPR0 0x50 -#define FTPMU010_PSPR1 0x54 -#define FTPMU010_PSPR2 0x58 -#define FTPMU010_PSPR3 0x5C -#define FTPMU010_PSPR4 0x60 -#define FTPMU010_PSPR5 0x64 -#define FTPMU010_PSPR6 0x68 -#define FTPMU010_PSPR7 0x6C -#define FTPMU010_PSPR8 0x70 -#define FTPMU010_PSPR9 0x74 -#define FTPMU010_PSPR10 0x78 -#define FTPMU010_PSPR11 0x7C -#define FTPMU010_PSPR12 0x80 -#define FTPMU010_PSPR13 0x84 -#define FTPMU010_PSPR14 0x88 -#define FTPMU010_PSPR15 0x8C -#define FTPMU010_AHBDMA_RACCS 0x90 -#define FTPMU010_reserved2 0x94 -#define FTPMU010_reserved3 0x98 -#define FTPMU010_JSS 0x9C -#define FTPMU010_CFC_RACC 0xA0 -#define FTPMU010_SSP1_RACC 0xA4 -#define FTPMU010_UART1TX_RACC 0xA8 -#define FTPMU010_UART1RX_RACC 0xAC -#define FTPMU010_UART2TX_RACC 0xB0 -#define FTPMU010_UART2RX_RACC 0xB4 -#define FTPMU010_SDC_RACC 0xB8 -#define FTPMU010_I2SAC97_RACC 0xBC -#define FTPMU010_IRDATX_RACC 0xC0 -#define FTPMU010_reserved4 0xC4 -#define FTPMU010_USBD_RACC 0xC8 -#define FTPMU010_IRDARX_RACC 0xCC -#define FTPMU010_IRDA_RACC 0xD0 -#define FTPMU010_ED0_RACC 0xD4 -#define FTPMU010_ED1_RACC 0xD8 -#endif /* __ASSEMBLY__ */ - -#endif /* __FTPMU010_H */ diff --git a/qemu/roms/u-boot/include/faraday/ftsdc010.h b/qemu/roms/u-boot/include/faraday/ftsdc010.h deleted file mode 100644 index 9bfdef90e..000000000 --- a/qemu/roms/u-boot/include/faraday/ftsdc010.h +++ /dev/null @@ -1,246 +0,0 @@ -/* - * Faraday FTSDC010 Secure Digital Memory Card Host Controller - * - * Copyright (C) 2011 Andes Technology Corporation - * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __FTSDC010_H -#define __FTSDC010_H - -#ifndef __ASSEMBLY__ - -/* sd controller register */ -struct ftsdc010_mmc { - unsigned int cmd; /* 0x00 - command reg */ - unsigned int argu; /* 0x04 - argument reg */ - unsigned int rsp0; /* 0x08 - response reg0 */ - unsigned int rsp1; /* 0x0c - response reg1 */ - unsigned int rsp2; /* 0x10 - response reg2 */ - unsigned int rsp3; /* 0x14 - response reg3 */ - unsigned int rsp_cmd; /* 0x18 - responded cmd reg */ - unsigned int dcr; /* 0x1c - data control reg */ - unsigned int dtr; /* 0x20 - data timer reg */ - unsigned int dlr; /* 0x24 - data length reg */ - unsigned int status; /* 0x28 - status reg */ - unsigned int clr; /* 0x2c - clear reg */ - unsigned int int_mask; /* 0x30 - intrrupt mask reg */ - unsigned int pcr; /* 0x34 - power control reg */ - unsigned int ccr; /* 0x38 - clock contorl reg */ - unsigned int bwr; /* 0x3c - bus width reg */ - unsigned int dwr; /* 0x40 - data window reg */ -#ifndef CONFIG_FTSDC010_SDIO - unsigned int feature; /* 0x44 - feature reg */ - unsigned int rev; /* 0x48 - revision reg */ -#else - unsigned int mmc_intr_time; /* 0x44 - MMC int resp time reg */ - unsigned int gpo; /* 0x48 - gerenal purpose output */ - unsigned int reserved[8]; /* 0x50 - 0x68 reserved */ - unsigned int sdio_ctrl1; /* 0x6c - SDIO control reg 1 */ - unsigned int sdio_ctrl2; /* 0x70 - SDIO control reg 2 */ - unsigned int sdio_status; /* 0x74 - SDIO status regi */ - unsigned int reserved1[9]; /* 0x78 - 0x98 reserved */ - unsigned int feature; /* 0x9c - feature reg */ - unsigned int rev; /* 0xa0 - revision reg */ -#endif /* CONFIG_FTSDC010_SDIO */ -}; - -struct mmc_host { - struct ftsdc010_mmc *reg; - unsigned int version; /* SDHCI spec. version */ - unsigned int clock; /* Current clock (MHz) */ - unsigned int fifo_len; /* bytes */ - unsigned int last_opcode; /* Last OP Code */ - unsigned int card_type; /* Card type */ -}; - -/* functions */ -int ftsdc010_mmc_init(int dev_index); - -#endif /* __ASSEMBLY__ */ - -/* global defines */ -#define FTSDC010_CMD_RETRY 0x100000 -#define FTSDC010_PIO_RETRY 100 /* pio retry times */ -#define FTSDC010_DELAY_UNIT 100 /* 100 us */ - -/* define from Linux kernel - include/linux/mmc/card.h */ -#define MMC_TYPE_SDIO 2 /* SDIO card */ - -/* define for mmc layer */ -#define MMC_DATA_BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ) - -/* this part is strange */ -#define FTSDC010_SDIO_CTRL1_REG 0x0000006C -#define FTSDC010_SDIO_CTRL2_REG 0x0000006C -#define FTSDC010_SDIO_STATUS_REG 0x00000070 - -/* 0x00 - command register */ -#define FTSDC010_CMD_IDX(x) (((x) & 0x3f) << 0) -#define FTSDC010_CMD_NEED_RSP (1 << 6) -#define FTSDC010_CMD_LONG_RSP (1 << 7) -#define FTSDC010_CMD_APP_CMD (1 << 8) -#define FTSDC010_CMD_CMD_EN (1 << 9) -#define FTSDC010_CMD_SDC_RST (1 << 10) -#define FTSDC010_CMD_MMC_INT_STOP (1 << 11) - -/* 0x18 - responded command register */ -#define FTSDC010_RSP_CMD_IDX(x) (((x) >> 0) & 0x3f) -#define FTSDC010_RSP_CMD_APP (1 << 6) - -/* 0x1c - data control register */ -#define FTSDC010_DCR_BLK_SIZE(x) (((x) & 0xf) << 0) -#define FTSDC010_DCR_DATA_WRITE (1 << 4) -#define FTSDC010_DCR_DMA_EN (1 << 5) -#define FTSDC010_DCR_DATA_EN (1 << 6) -#ifdef CONFIG_FTSDC010_SDIO -#define FTSDC010_DCR_FIFOTH (1 << 7) -#define FTSDC010_DCR_DMA_TYPE(x) (((x) & 0x3) << 8) -#define FTSDC010_DCR_FIFO_RST (1 << 10) -#endif /* CONFIG_FTSDC010_SDIO */ - -#define FTSDC010_DCR_DMA_TYPE_1 0x0 /* Single r/w */ -#define FTSDC010_DCR_DMA_TYPE_4 0x1 /* Burst 4 r/w */ -#define FTSDC010_DCR_DMA_TYPE_8 0x2 /* Burst 8 r/w */ - -#define FTSDC010_DCR_BLK_BYTES(x) (ffs(x) - 1) /* 1B - 2048B */ - -/* CPRM related define */ -#define FTSDC010_CPRM_DATA_CHANGE_ENDIAN_EN 0x000008 -#define FTSDC010_CPRM_DATA_SWAP_HL_EN 0x000010 - -/* 0x28 - status register */ -#define FTSDC010_STATUS_RSP_CRC_FAIL (1 << 0) -#define FTSDC010_STATUS_DATA_CRC_FAIL (1 << 1) -#define FTSDC010_STATUS_RSP_TIMEOUT (1 << 2) -#define FTSDC010_STATUS_DATA_TIMEOUT (1 << 3) -#define FTSDC010_STATUS_RSP_CRC_OK (1 << 4) -#define FTSDC010_STATUS_DATA_CRC_OK (1 << 5) -#define FTSDC010_STATUS_CMD_SEND (1 << 6) -#define FTSDC010_STATUS_DATA_END (1 << 7) -#define FTSDC010_STATUS_FIFO_URUN (1 << 8) -#define FTSDC010_STATUS_FIFO_ORUN (1 << 9) -#define FTSDC010_STATUS_CARD_CHANGE (1 << 10) -#define FTSDC010_STATUS_CARD_DETECT (1 << 11) -#define FTSDC010_STATUS_WRITE_PROT (1 << 12) -#ifdef CONFIG_FTSDC010_SDIO -#define FTSDC010_STATUS_CP_READY (1 << 13) /* reserved ? */ -#define FTSDC010_STATUS_CP_BUF_READY (1 << 14) /* reserved ? */ -#define FTSDC010_STATUS_PLAIN_TEXT_READY (1 << 15) /* reserved ? */ -#define FTSDC010_STATUS_SDIO_IRPT (1 << 16) /* SDIO card intr */ -#define FTSDC010_STATUS_DATA0_STATUS (1 << 17) -#endif /* CONFIG_FTSDC010_SDIO */ -#define FTSDC010_STATUS_RSP_ERROR \ - (FTSDC010_STATUS_RSP_CRC_FAIL | FTSDC010_STATUS_RSP_TIMEOUT) -#define FTSDC010_STATUS_RSP_MASK \ - (FTSDC010_STATUS_RSP_ERROR | FTSDC010_STATUS_RSP_CRC_OK) -#define FTSDC010_STATUS_DATA_ERROR \ - (FTSDC010_STATUS_DATA_CRC_FAIL | FTSDC010_STATUS_DATA_TIMEOUT) -#define FTSDC010_STATUS_DATA_MASK \ - (FTSDC010_STATUS_DATA_ERROR | FTSDC010_STATUS_DATA_CRC_OK \ - | FTSDC010_STATUS_DATA_END) - -/* 0x2c - clear register */ -#define FTSDC010_CLR_RSP_CRC_FAIL (1 << 0) -#define FTSDC010_CLR_DATA_CRC_FAIL (1 << 1) -#define FTSDC010_CLR_RSP_TIMEOUT (1 << 2) -#define FTSDC010_CLR_DATA_TIMEOUT (1 << 3) -#define FTSDC010_CLR_RSP_CRC_OK (1 << 4) -#define FTSDC010_CLR_DATA_CRC_OK (1 << 5) -#define FTSDC010_CLR_CMD_SEND (1 << 6) -#define FTSDC010_CLR_DATA_END (1 << 7) -#define FTSDC010_STATUS_FIFO_URUN (1 << 8) /* reserved ? */ -#define FTSDC010_STATUS_FIFO_ORUN (1 << 9) /* reserved ? */ -#define FTSDC010_CLR_CARD_CHANGE (1 << 10) -#ifdef CONFIG_FTSDC010_SDIO -#define FTSDC010_CLR_SDIO_IRPT (1 << 16) -#endif /* CONFIG_FTSDC010_SDIO */ - -/* 0x30 - interrupt mask register */ -#define FTSDC010_INT_MASK_RSP_CRC_FAIL (1 << 0) -#define FTSDC010_INT_MASK_DATA_CRC_FAIL (1 << 1) -#define FTSDC010_INT_MASK_RSP_TIMEOUT (1 << 2) -#define FTSDC010_INT_MASK_DATA_TIMEOUT (1 << 3) -#define FTSDC010_INT_MASK_RSP_CRC_OK (1 << 4) -#define FTSDC010_INT_MASK_DATA_CRC_OK (1 << 5) -#define FTSDC010_INT_MASK_CMD_SEND (1 << 6) -#define FTSDC010_INT_MASK_DATA_END (1 << 7) -#define FTSDC010_INT_MASK_FIFO_URUN (1 << 8) -#define FTSDC010_INT_MASK_FIFO_ORUN (1 << 9) -#define FTSDC010_INT_MASK_CARD_CHANGE (1 << 10) -#ifdef CONFIG_FTSDC010_SDIO -#define FTSDC010_INT_MASK_CP_READY (1 << 13) -#define FTSDC010_INT_MASK_CP_BUF_READY (1 << 14) -#define FTSDC010_INT_MASK_PLAIN_TEXT_READY (1 << 15) -#define FTSDC010_INT_MASK_SDIO_IRPT (1 << 16) -#define FTSDC010_STATUS_DATA0_STATUS (1 << 17) -#endif /* CONFIG_FTSDC010_SDIO */ - -/* ? */ -#define FTSDC010_CARD_INSERT 0x0 -#define FTSDC010_CARD_REMOVE FTSDC010_STATUS_REG_CARD_DETECT - -/* 0x34 - power control register */ -#define FTSDC010_PCR_POWER(x) (((x) & 0xf) << 0) -#define FTSDC010_PCR_POWER_ON (1 << 4) - -/* 0x38 - clock control register */ -#define FTSDC010_CCR_CLK_DIV(x) (((x) & 0x7f) << 0) -#define FTSDC010_CCR_CLK_SD (1 << 7) /* 0: MMC, 1: SD */ -#define FTSDC010_CCR_CLK_DIS (1 << 8) -#define FTSDC010_CCR_CLK_HISPD (1 << 9) /* high speed */ - -/* card type */ -#define FTSDC010_CARD_TYPE_SD FTSDC010_CLOCK_REG_CARD_TYPE -#define FTSDC010_CARD_TYPE_MMC 0x0 - -/* 0x3c - bus width register */ -#define FTSDC010_BWR_MODE_1BIT (1 << 0) /* 1 bit mode enabled */ -#define FTSDC010_BWR_MODE_8BIT (1 << 1) /* 8 bit mode enabled */ -#define FTSDC010_BWR_MODE_4BIT (1 << 2) /* 4 bit mode enabled */ -#define FTSDC010_BWR_MODE_MASK (7 << 0) -#define FTSDC010_BWR_MODE_SHIFT (0) -#define FTSDC010_BWR_CAPS_1BIT (0 << 3) /* 1 bits mode supported */ -#define FTSDC010_BWR_CAPS_4BIT (1 << 3) /* 1,4 bits mode supported */ -#define FTSDC010_BWR_CAPS_8BIT (2 << 3) /* 1,4,8 bits mode supported */ -#define FTSDC010_BWR_CAPS_MASK (3 << 3) -#define FTSDC010_BWR_CAPS_SHIFT (3) -#define FTSDC010_BWR_CARD_DETECT (1 << 5) - -/* 0x44 or 0x9c - feature register */ -#define FTSDC010_FEATURE_FIFO_DEPTH(x) (((x) >> 0) & 0xff) -#define FTSDC010_FEATURE_CPRM_FUNCTION (1 << 8) - -#define FTSDC010_FIFO_DEPTH_4 0x04 -#define FTSDC010_FIFO_DEPTH_8 0x08 -#define FTSDC010_FIFO_DEPTH_16 0x10 - -/* 0x48 or 0xa0 - revision register */ -#define FTSDC010_REV_REVISION(x) (((x) & 0xff) >> 0) -#define FTSDC010_REV_MINOR(x) (((x) & 0xff00) >> 8) -#define FTSDC010_REV_MAJOR(x) (((x) & 0xffff0000) >> 16) - -#ifdef CONFIG_FTSDC010_SDIO -/* 0x44 - general purpose output */ -#define FTSDC010_GPO_PORT(x) (((x) & 0xf) << 0) - -/* 0x6c - sdio control register 1 */ -#define FTSDC010_SDIO_CTRL1_SDIO_BLK_SIZE(x) (((x) & 0xfff) << 0) -#define FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE (1 << 12) -#define FTSDC010_SDIO_CTRL1_READ_WAIT_EN (1 << 13) -#define FTSDC010_SDIO_CTRL1_SDIO_ENABLE (1 << 14) -#define FTSDC010_SDIO_CTRL1_SDIO_BLK_NO(x) (((x) & 0x1ff) << 15) - -/* 0x70 - sdio control register 2 */ -#define FTSDC010_SDIO_CTRL2_SUSP_READ_WAIT (1 << 0) -#define FTSDC010_SDIO_CTRL2_SUSP_CMD_ABORT (1 << 1) - -/* 0x74 - sdio status register */ -#define FTSDC010_SDIO_STATUS_SDIO_BLK_CNT(x) (((x) >> 0) & 0x1ffff) -#define FTSDC010_SDIO_STATUS_FIFO_REMAIN_NO(x) (((x) >> 17) & 0xef) - -#endif /* CONFIG_FTSDC010_SDIO */ - -#endif /* __FTSDC010_H */ diff --git a/qemu/roms/u-boot/include/faraday/ftsdmc020.h b/qemu/roms/u-boot/include/faraday/ftsdmc020.h deleted file mode 100644 index 8e296c056..000000000 --- a/qemu/roms/u-boot/include/faraday/ftsdmc020.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * SDRAM Controller - */ -#ifndef __FTSDMC020_H -#define __FTSDMC020_H - -#define FTSDMC020_OFFSET_TP0 0x00 -#define FTSDMC020_OFFSET_TP1 0x04 -#define FTSDMC020_OFFSET_CR 0x08 -#define FTSDMC020_OFFSET_BANK0_BSR 0x0C -#define FTSDMC020_OFFSET_BANK1_BSR 0x10 -#define FTSDMC020_OFFSET_BANK2_BSR 0x14 -#define FTSDMC020_OFFSET_BANK3_BSR 0x18 -#define FTSDMC020_OFFSET_BANK4_BSR 0x1C -#define FTSDMC020_OFFSET_BANK5_BSR 0x20 -#define FTSDMC020_OFFSET_BANK6_BSR 0x24 -#define FTSDMC020_OFFSET_BANK7_BSR 0x28 -#define FTSDMC020_OFFSET_ACR 0x34 - -/* - * Timing Parametet 0 Register - */ -#define FTSDMC020_TP0_TCL(x) ((x) & 0x3) -#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4) -#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8) -#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12) -#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16) -#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20) - -/* - * Timing Parametet 1 Register - */ -#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff) -#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16) -#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20) - -/* - * Configuration Register - */ -#define FTSDMC020_CR_SREF (1 << 0) -#define FTSDMC020_CR_PWDN (1 << 1) -#define FTSDMC020_CR_ISMR (1 << 2) -#define FTSDMC020_CR_IREF (1 << 3) -#define FTSDMC020_CR_IPREC (1 << 4) -#define FTSDMC020_CR_REFTYPE (1 << 5) - -/* - * SDRAM External Bank Base/Size Register - */ -#define FTSDMC020_BANK_ENABLE (1 << 28) - -#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) - -#define FTSDMC020_BANK_DDW_X4 (0 << 12) -#define FTSDMC020_BANK_DDW_X8 (1 << 12) -#define FTSDMC020_BANK_DDW_X16 (2 << 12) -#define FTSDMC020_BANK_DDW_X32 (3 << 12) - -#define FTSDMC020_BANK_DSZ_16M (0 << 8) -#define FTSDMC020_BANK_DSZ_64M (1 << 8) -#define FTSDMC020_BANK_DSZ_128M (2 << 8) -#define FTSDMC020_BANK_DSZ_256M (3 << 8) - -#define FTSDMC020_BANK_MBW_8 (0 << 4) -#define FTSDMC020_BANK_MBW_16 (1 << 4) -#define FTSDMC020_BANK_MBW_32 (2 << 4) - -#define FTSDMC020_BANK_SIZE_1M 0x0 -#define FTSDMC020_BANK_SIZE_2M 0x1 -#define FTSDMC020_BANK_SIZE_4M 0x2 -#define FTSDMC020_BANK_SIZE_8M 0x3 -#define FTSDMC020_BANK_SIZE_16M 0x4 -#define FTSDMC020_BANK_SIZE_32M 0x5 -#define FTSDMC020_BANK_SIZE_64M 0x6 -#define FTSDMC020_BANK_SIZE_128M 0x7 -#define FTSDMC020_BANK_SIZE_256M 0x8 - -/* - * Arbiter Control Register - */ -#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) -#define FTSDMC020_ACR_TOE (1 << 8) - -#endif /* __FTSDMC020_H */ diff --git a/qemu/roms/u-boot/include/faraday/ftsdmc021.h b/qemu/roms/u-boot/include/faraday/ftsdmc021.h deleted file mode 100644 index b893b5e3e..000000000 --- a/qemu/roms/u-boot/include/faraday/ftsdmc021.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * (C) Copyright 2011 Andes Technology Corp - * Macpaul Lin <macpaul@andestech.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * FTSDMC021 - SDRAM Controller - */ -#ifndef __FTSDMC021_H -#define __FTSDMC021_H - -#ifndef __ASSEMBLY__ -struct ftsdmc021 { - unsigned int tp1; /* 0x00 - SDRAM Timing Parameter 1 */ - unsigned int tp2; /* 0x04 - SDRAM Timing Parameter 2 */ - unsigned int cr1; /* 0x08 - SDRAM Configuration Reg 1 */ - unsigned int cr2; /* 0x0c - SDRAM Configuration Reg 2 */ - unsigned int bank0_bsr; /* 0x10 - Ext. Bank Base/Size Reg 0 */ - unsigned int bank1_bsr; /* 0x14 - Ext. Bank Base/Size Reg 1 */ - unsigned int bank2_bsr; /* 0x18 - Ext. Bank Base/Size Reg 2 */ - unsigned int bank3_bsr; /* 0x1c - Ext. Bank Base/Size Reg 3 */ - unsigned int bank4_bsr; /* 0x20 - Ext. Bank Base/Size Reg 4 */ - unsigned int bank5_bsr; /* 0x24 - Ext. Bank Base/Size Reg 5 */ - unsigned int bank6_bsr; /* 0x28 - Ext. Bank Base/Size Reg 6 */ - unsigned int bank7_bsr; /* 0x2c - Ext. Bank Base/Size Reg 7 */ - unsigned int ragr; /* 0x30 - Read Arbitration Group Reg */ - unsigned int frr; /* 0x34 - Flush Request Register */ - unsigned int ebisr; /* 0x38 - EBI Support Register */ - unsigned int rsved[25]; /* 0x3c-0x9c - Reserved */ - unsigned int crr; /* 0x100 - Controller Revision Reg */ - unsigned int cfr; /* 0x104 - Controller Feature Reg */ -}; -#endif /* __ASSEMBLY__ */ - -/* - * Timing Parameter 1 Register - */ -#define FTSDMC021_TP1_TCL(x) ((x) & 0x3) /* CAS Latency */ -#define FTSDMC021_TP1_TWR(x) (((x) & 0x3) << 4) /* W-Recovery Time */ -#define FTSDMC021_TP1_TRF(x) (((x) & 0xf) << 8) /* Auto-Refresh Cycle */ -#define FTSDMC021_TP1_TRCD(x) (((x) & 0x7) << 12) /* RAS-to-CAS Delay */ -#define FTSDMC021_TP1_TRP(x) (((x) & 0xf) << 16) /* Precharge Cycle */ -#define FTSDMC021_TP1_TRAS(x) (((x) & 0xf) << 20) - -/* - * Timing Parameter 2 Register - */ -#define FTSDMC021_TP2_REF_INTV(x) ((x) & 0xffff) /* Refresh interval */ -/* b(16:19) - Initial Refresh Times */ -#define FTSDMC021_TP2_INI_REFT(x) (((x) & 0xf) << 16) -/* b(20:23) - Initial Pre-Charge Times */ -#define FTSDMC021_TP2_INI_PREC(x) (((x) & 0xf) << 20) - -/* - * SDRAM Configuration Register 1 - */ -#define FTSDMC021_CR1_BNKSIZE(x) ((x) & 0xf) /* Bank Size */ -#define FTSDMC021_CR1_MBW(x) (((x) & 0x3) << 4) /* Bus Width */ -#define FTSDMC021_CR1_DSZ(x) (((x) & 0x7) << 8) /* SDRAM Size */ -#define FTSDMC021_CR1_DDW(x) (((x) & 0x3) << 12) /* Data Width */ -/* b(16) MA2T: Double Memory Address Cycle Enable */ -#define FTSDMC021_CR1_MA2T(x) (1 << 16) -/* The value of b(0:3)CR1: 1M-512M, must be power of 2 */ -#define FTSDMC021_BANK_SIZE(x) (ffs(x) - 1) - -/* - * Configuration Register 2 - */ -#define FTSDMC021_CR2_SREF (1 << 0) /* Self-Refresh Mode */ -#define FTSDMC021_CR2_PWDN (1 << 1) /* Power Down Operation Mode */ -#define FTSDMC021_CR2_ISMR (1 << 2) /* Start Set-Mode-Register */ -#define FTSDMC021_CR2_IREF (1 << 3) /* Init Refresh Start Flag */ -#define FTSDMC021_CR2_IPREC (1 << 4) /* Init Pre-Charge Start Flag */ -#define FTSDMC021_CR2_REFTYPE (1 << 5) - -/* - * SDRAM External Bank Base/Size Register - */ -#define FTSDMC021_BANK_ENABLE (1 << 12) - -/* 12-bit base address of external bank. - * Default value is 0x800. - * The 12-bit equals to the haddr[31:20] of AHB address bus. */ -#define FTSDMC021_BANK_BASE(x) ((x) & 0xfff) - -/* - * Read Arbitration Grant Window Register - */ -#define FTSDMC021_RAGR_CH1GW(x) (((x) & 0xff) << 0) -#define FTSDMC021_RAGR_CH2GW(x) (((x) & 0xff) << 4) -#define FTSDMC021_RAGR_CH3GW(x) (((x) & 0xff) << 8) -#define FTSDMC021_RAGR_CH4GW(x) (((x) & 0xff) << 12) -#define FTSDMC021_RAGR_CH5GW(x) (((x) & 0xff) << 16) -#define FTSDMC021_RAGR_CH6GW(x) (((x) & 0xff) << 20) -#define FTSDMC021_RAGR_CH7GW(x) (((x) & 0xff) << 24) -#define FTSDMC021_RAGR_CH8GW(x) (((x) & 0xff) << 28) - -/* - * Flush Request Register - */ -#define FTSDMC021_FRR_FLUSHCHN(x) (((x) & 0x7) << 0) -#define FTSDMC021_FRR_FLUSHCMPLT (1 << 3) /* Flush Req Flag */ - -/* - * External Bus Interface Support Register (EBISR) - */ -#define FTSDMC021_EBISR_MR(x) ((x) & 0xfff) /* Far-end mode */ -#define FTSDMC021_EBISR_PRSMR (1 << 12) /* Pre-SMR */ -#define FTSDMC021_EBISR_POPREC (1 << 13) -#define FTSDMC021_EBISR_POSMR (1 << 14) /* Post-SMR */ - -/* - * Controller Revision Register (CRR, Read Only) - */ -#define FTSDMC021_CRR_REV_VER (((x) >> 0) & 0xff) -#define FTSDMC021_CRR_MINOR_VER (((x) >> 8) & 0xff) -#define FTSDMC021_CRR_MAJOR_VER (((x) >> 16) & 0xff) - -/* - * Controller Feature Register (CFR, Read Only) - */ -#define FTSDMC021_CFR_EBNK (((x) >> 0) & 0xf) -#define FTSDMC021_CFR_CHN (((x) >> 8) & 0xf) -#define FTSDMC021_CFR_EBI (((x) >> 16) & 0x1) -#define FTSDMC021_CFR_CH1_FDEPTH (((x) >> 24) & 0x1) -#define FTSDMC021_CFR_CH2_FDEPTH (((x) >> 25) & 0x1) -#define FTSDMC021_CFR_CH3_FDEPTH (((x) >> 26) & 0x1) -#define FTSDMC021_CFR_CH4_FDEPTH (((x) >> 27) & 0x1) -#define FTSDMC021_CFR_CH5_FDEPTH (((x) >> 28) & 0x1) -#define FTSDMC021_CFR_CH6_FDEPTH (((x) >> 29) & 0x1) -#define FTSDMC021_CFR_CH7_FDEPTH (((x) >> 30) & 0x1) -#define FTSDMC021_CFR_CH8_FDEPTH (((x) >> 31) & 0x1) - -#endif /* __FTSDMC021_H */ diff --git a/qemu/roms/u-boot/include/faraday/ftsmc020.h b/qemu/roms/u-boot/include/faraday/ftsmc020.h deleted file mode 100644 index 54120ab41..000000000 --- a/qemu/roms/u-boot/include/faraday/ftsmc020.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Static Memory Controller - */ -#ifndef __FTSMC020_H -#define __FTSMC020_H - -#ifndef __ASSEMBLY__ - -struct ftsmc020_bank { - unsigned int cr; - unsigned int tpr; -}; - -struct ftsmc020 { - struct ftsmc020_bank bank[4]; /* 0x00 - 0x1c */ - unsigned int pad[8]; /* 0x20 - 0x3c */ - unsigned int ssr; /* 0x40 */ -}; - -void ftsmc020_init(void); - -#endif /* __ASSEMBLY__ */ - -/* - * Memory Bank Configuration Register - */ -#define FTSMC020_BANK_ENABLE (1 << 28) -#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000) - -#define FTSMC020_BANK_WPROT (1 << 11) - -#define FTSMC020_BANK_TYPE1 (1 << 10) -#define FTSMC020_BANK_TYPE2 (1 << 9) -#define FTSMC020_BANK_TYPE3 (1 << 8) - -#define FTSMC020_BANK_SIZE_32K (0xb << 4) -#define FTSMC020_BANK_SIZE_64K (0xc << 4) -#define FTSMC020_BANK_SIZE_128K (0xd << 4) -#define FTSMC020_BANK_SIZE_256K (0xe << 4) -#define FTSMC020_BANK_SIZE_512K (0xf << 4) -#define FTSMC020_BANK_SIZE_1M (0x0 << 4) -#define FTSMC020_BANK_SIZE_2M (0x1 << 4) -#define FTSMC020_BANK_SIZE_4M (0x2 << 4) -#define FTSMC020_BANK_SIZE_8M (0x3 << 4) -#define FTSMC020_BANK_SIZE_16M (0x4 << 4) -#define FTSMC020_BANK_SIZE_32M (0x5 << 4) -#define FTSMC020_BANK_SIZE_64M (0x6 << 4) - -#define FTSMC020_BANK_MBW_8 (0x0 << 0) -#define FTSMC020_BANK_MBW_16 (0x1 << 0) -#define FTSMC020_BANK_MBW_32 (0x2 << 0) - -/* - * Memory Bank Timing Parameter Register - */ -#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28) -#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24) -#define FTSMC020_TPR_RBE (1 << 20) -#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18) -#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16) -#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12) -#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8) -#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6) -#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4) -#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0) - -#endif /* __FTSMC020_H */ diff --git a/qemu/roms/u-boot/include/faraday/fttmr010.h b/qemu/roms/u-boot/include/faraday/fttmr010.h deleted file mode 100644 index 2ab68d102..000000000 --- a/qemu/roms/u-boot/include/faraday/fttmr010.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Timer - */ -#ifndef __FTTMR010_H -#define __FTTMR010_H - -struct fttmr010 { - unsigned int timer1_counter; /* 0x00 */ - unsigned int timer1_load; /* 0x04 */ - unsigned int timer1_match1; /* 0x08 */ - unsigned int timer1_match2; /* 0x0c */ - unsigned int timer2_counter; /* 0x10 */ - unsigned int timer2_load; /* 0x14 */ - unsigned int timer2_match1; /* 0x18 */ - unsigned int timer2_match2; /* 0x1c */ - unsigned int timer3_counter; /* 0x20 */ - unsigned int timer3_load; /* 0x24 */ - unsigned int timer3_match1; /* 0x28 */ - unsigned int timer3_match2; /* 0x2c */ - unsigned int cr; /* 0x30 */ - unsigned int interrupt_state; /* 0x34 */ - unsigned int interrupt_mask; /* 0x38 */ -}; - -/* - * Timer Control Register - */ -#define FTTMR010_TM3_UPDOWN (1 << 11) -#define FTTMR010_TM2_UPDOWN (1 << 10) -#define FTTMR010_TM1_UPDOWN (1 << 9) -#define FTTMR010_TM3_OFENABLE (1 << 8) -#define FTTMR010_TM3_CLOCK (1 << 7) -#define FTTMR010_TM3_ENABLE (1 << 6) -#define FTTMR010_TM2_OFENABLE (1 << 5) -#define FTTMR010_TM2_CLOCK (1 << 4) -#define FTTMR010_TM2_ENABLE (1 << 3) -#define FTTMR010_TM1_OFENABLE (1 << 2) -#define FTTMR010_TM1_CLOCK (1 << 1) -#define FTTMR010_TM1_ENABLE (1 << 0) - -/* - * Timer Interrupt State & Mask Registers - */ -#define FTTMR010_TM3_OVERFLOW (1 << 8) -#define FTTMR010_TM3_MATCH2 (1 << 7) -#define FTTMR010_TM3_MATCH1 (1 << 6) -#define FTTMR010_TM2_OVERFLOW (1 << 5) -#define FTTMR010_TM2_MATCH2 (1 << 4) -#define FTTMR010_TM2_MATCH1 (1 << 3) -#define FTTMR010_TM1_OVERFLOW (1 << 2) -#define FTTMR010_TM1_MATCH2 (1 << 1) -#define FTTMR010_TM1_MATCH1 (1 << 0) - -#endif /* __FTTMR010_H */ diff --git a/qemu/roms/u-boot/include/faraday/ftwdt010_wdt.h b/qemu/roms/u-boot/include/faraday/ftwdt010_wdt.h deleted file mode 100644 index 2c5a36628..000000000 --- a/qemu/roms/u-boot/include/faraday/ftwdt010_wdt.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Watchdog driver for the FTWDT010 Watch Dog Driver - * - * (c) Copyright 2004 Faraday Technology Corp. (www.faraday-tech.com) - * Based on sa1100_wdt.c by Oleg Drokin <green@crimea.edu> - * Based on SoftDog driver by Alan Cox <alan@redhat.com> - * - * Copyright (C) 2011 Andes Technology Corporation - * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> - * - * SPDX-License-Identifier: GPL-2.0+ - * - * 27/11/2004 Initial release, Faraday. - * 12/01/2011 Port to u-boot, Macpaul Lin. - */ - -#ifndef __FTWDT010_H -#define __FTWDT010_H - -struct ftwdt010_wdt { - unsigned int wdcounter; /* Counter Reg - 0x00 */ - unsigned int wdload; /* Counter Auto Reload Reg - 0x04 */ - unsigned int wdrestart; /* Counter Restart Reg - 0x08 */ - unsigned int wdcr; /* Control Reg - 0x0c */ - unsigned int wdstatus; /* Status Reg - 0x10 */ - unsigned int wdclear; /* Timer Clear - 0x14 */ - unsigned int wdintrlen; /* Interrupt Length - 0x18 */ -}; - -/* - * WDLOAD - Counter Auto Reload Register - * The Auto Reload Register is set to 0x03EF1480 (66Mhz) by default. - * Which means in a 66MHz system, the period of Watch Dog timer reset is - * one second. - */ -#define FTWDT010_WDLOAD(x) ((x) & 0xffffffff) - -/* - * WDRESTART - Watch Dog Timer Counter Restart Register - * If writing 0x5AB9 to WDRESTART register, Watch Dog timer will - * automatically reload WDLOAD to WDCOUNTER and restart counting. - */ -#define FTWDT010_WDRESTART_MAGIC 0x5AB9 - -/* WDCR - Watch Dog Timer Control Register */ -#define FTWDT010_WDCR_ENABLE (1 << 0) -#define FTWDT010_WDCR_RST (1 << 1) -#define FTWDT010_WDCR_INTR (1 << 2) -/* FTWDT010_WDCR_EXT bit: Watch Dog Timer External Signal Enable */ -#define FTWDT010_WDCR_EXT (1 << 3) -/* FTWDT010_WDCR_CLOCK bit: Clock Source: 0: PCLK, 1: EXTCLK. - * The clock source PCLK cannot be gated when system sleeps, even if - * WDCLOCK bit is turned on. - * - * Faraday's Watch Dog timer can be driven by an external clock. The - * programmer just needs to write one to WdCR[WdClock] bit. - * - * Note: There is a limitation between EXTCLK and PCLK: - * EXTCLK cycle time / PCLK cycle time > 2. - * If the system does not need an external clock, - * just keep WdCR[WdClock] bit in its default value. - */ -#define FTWDT010_WDCR_CLOCK (1 << 4) - -/* - * WDSTATUS - Watch Dog Timer Status Register - * This bit is set when the counter reaches Zero - */ -#define FTWDT010_WDSTATUS(x) ((x) & 0x1) - -/* - * WDCLEAR - Watch Dog Timer Clear Register - * Writing one to this register will clear WDSTATUS. - */ -#define FTWDT010_WDCLEAR (1 << 0) - -/* - * WDINTRLEN - Watch Dog Timer Interrupt Length - * This register controls the duration length of wd_rst, wd_intr and wd_ext. - * The default value is 0xFF. - */ -#define FTWDT010_WDINTRLEN(x) ((x) & 0xff) - -/* - * Variable timeout should be set in ms. - * (CONFIG_SYS_CLK_FREQ/1000) equals 1 ms. - * WDLOAD = timeout * TIMEOUT_FACTOR. - */ -#define FTWDT010_TIMEOUT_FACTOR (CONFIG_SYS_CLK_FREQ / 1000) /* 1 ms */ - -void ftwdt010_wdt_reset(void); -void ftwdt010_wdt_disable(void); - -#endif /* __FTWDT010_H */ |