diff options
Diffstat (limited to 'qemu/roms/u-boot/drivers/video')
53 files changed, 23322 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/drivers/video/Makefile b/qemu/roms/u-boot/drivers/video/Makefile new file mode 100644 index 000000000..c52702924 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/Makefile @@ -0,0 +1,42 @@ +# +# (C) Copyright 2000-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o +obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o +obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o +obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o +obj-$(CONFIG_EXYNOS_DP) += exynos_dp.o exynos_dp_lowlevel.o +obj-$(CONFIG_EXYNOS_FB) += exynos_fb.o exynos_fimd.o +obj-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \ + exynos_mipi_dsi_lowlevel.o +obj-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o +obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o +obj-$(CONFIG_L5F31188) += l5f31188.o +obj-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o +obj-$(CONFIG_PXA_LCD) += pxa_lcd.o +obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o +obj-$(CONFIG_S6E8AX0) += s6e8ax0.o +obj-$(CONFIG_S6E63D6) += s6e63d6.o +obj-$(CONFIG_LD9040) += ld9040.o +obj-$(CONFIG_SED156X) += sed156x.o +obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o +obj-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o +obj-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o +obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o +obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o +obj-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o +obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o +obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o +obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o +obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o +obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o +obj-$(CONFIG_VIDEO_SED13806) += sed13806.o +obj-$(CONFIG_VIDEO_SM501) += sm501.o +obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o +obj-$(CONFIG_VIDEO_TEGRA) += tegra.o +obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o +obj-$(CONFIG_FORMIKE) += formike.o diff --git a/qemu/roms/u-boot/drivers/video/ati_ids.h b/qemu/roms/u-boot/drivers/video/ati_ids.h new file mode 100644 index 000000000..3e72a7dd4 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/ati_ids.h @@ -0,0 +1,211 @@ +/* + * ATI PCI IDs from XFree86, kept here to make sync'ing with + * XFree much simpler. Currently, this list is only used by + * radeonfb + */ + +#define PCI_CHIP_RV380_3150 0x3150 +#define PCI_CHIP_RV380_3151 0x3151 +#define PCI_CHIP_RV380_3152 0x3152 +#define PCI_CHIP_RV380_3153 0x3153 +#define PCI_CHIP_RV380_3154 0x3154 +#define PCI_CHIP_RV380_3156 0x3156 +#define PCI_CHIP_RV380_3E50 0x3E50 +#define PCI_CHIP_RV380_3E51 0x3E51 +#define PCI_CHIP_RV380_3E52 0x3E52 +#define PCI_CHIP_RV380_3E53 0x3E53 +#define PCI_CHIP_RV380_3E54 0x3E54 +#define PCI_CHIP_RV380_3E56 0x3E56 +#define PCI_CHIP_RS100_4136 0x4136 +#define PCI_CHIP_RS200_4137 0x4137 +#define PCI_CHIP_R300_AD 0x4144 +#define PCI_CHIP_R300_AE 0x4145 +#define PCI_CHIP_R300_AF 0x4146 +#define PCI_CHIP_R300_AG 0x4147 +#define PCI_CHIP_R350_AH 0x4148 +#define PCI_CHIP_R350_AI 0x4149 +#define PCI_CHIP_R350_AJ 0x414A +#define PCI_CHIP_R350_AK 0x414B +#define PCI_CHIP_RV350_AP 0x4150 +#define PCI_CHIP_RV350_AQ 0x4151 +#define PCI_CHIP_RV360_AR 0x4152 +#define PCI_CHIP_RV350_AS 0x4153 +#define PCI_CHIP_RV350_AT 0x4154 +#define PCI_CHIP_RV350_AV 0x4156 +#define PCI_CHIP_MACH32 0x4158 +#define PCI_CHIP_RS250_4237 0x4237 +#define PCI_CHIP_R200_BB 0x4242 +#define PCI_CHIP_R200_BC 0x4243 +#define PCI_CHIP_RS100_4336 0x4336 +#define PCI_CHIP_RS200_4337 0x4337 +#define PCI_CHIP_MACH64CT 0x4354 +#define PCI_CHIP_MACH64CX 0x4358 +#define PCI_CHIP_RS250_4437 0x4437 +#define PCI_CHIP_MACH64ET 0x4554 +#define PCI_CHIP_MACH64GB 0x4742 +#define PCI_CHIP_MACH64GD 0x4744 +#define PCI_CHIP_MACH64GI 0x4749 +#define PCI_CHIP_MACH64GL 0x474C +#define PCI_CHIP_MACH64GM 0x474D +#define PCI_CHIP_MACH64GN 0x474E +#define PCI_CHIP_MACH64GO 0x474F +#define PCI_CHIP_MACH64GP 0x4750 +#define PCI_CHIP_MACH64GQ 0x4751 +#define PCI_CHIP_MACH64GR 0x4752 +#define PCI_CHIP_MACH64GS 0x4753 +#define PCI_CHIP_MACH64GT 0x4754 +#define PCI_CHIP_MACH64GU 0x4755 +#define PCI_CHIP_MACH64GV 0x4756 +#define PCI_CHIP_MACH64GW 0x4757 +#define PCI_CHIP_MACH64GX 0x4758 +#define PCI_CHIP_MACH64GY 0x4759 +#define PCI_CHIP_MACH64GZ 0x475A +#define PCI_CHIP_RV250_Id 0x4964 +#define PCI_CHIP_RV250_Ie 0x4965 +#define PCI_CHIP_RV250_If 0x4966 +#define PCI_CHIP_RV250_Ig 0x4967 +#define PCI_CHIP_R420_JH 0x4A48 +#define PCI_CHIP_R420_JI 0x4A49 +#define PCI_CHIP_R420_JJ 0x4A4A +#define PCI_CHIP_R420_JK 0x4A4B +#define PCI_CHIP_R420_JL 0x4A4C +#define PCI_CHIP_R420_JM 0x4A4D +#define PCI_CHIP_R420_JN 0x4A4E +#define PCI_CHIP_R420_JP 0x4A50 +#define PCI_CHIP_MACH64LB 0x4C42 +#define PCI_CHIP_MACH64LD 0x4C44 +#define PCI_CHIP_RAGE128LE 0x4C45 +#define PCI_CHIP_RAGE128LF 0x4C46 +#define PCI_CHIP_MACH64LG 0x4C47 +#define PCI_CHIP_MACH64LI 0x4C49 +#define PCI_CHIP_MACH64LM 0x4C4D +#define PCI_CHIP_MACH64LN 0x4C4E +#define PCI_CHIP_MACH64LP 0x4C50 +#define PCI_CHIP_MACH64LQ 0x4C51 +#define PCI_CHIP_MACH64LR 0x4C52 +#define PCI_CHIP_MACH64LS 0x4C53 +#define PCI_CHIP_MACH64LT 0x4C54 +#define PCI_CHIP_RADEON_LW 0x4C57 +#define PCI_CHIP_RADEON_LX 0x4C58 +#define PCI_CHIP_RADEON_LY 0x4C59 +#define PCI_CHIP_RADEON_LZ 0x4C5A +#define PCI_CHIP_RV250_Ld 0x4C64 +#define PCI_CHIP_RV250_Le 0x4C65 +#define PCI_CHIP_RV250_Lf 0x4C66 +#define PCI_CHIP_RV250_Lg 0x4C67 +#define PCI_CHIP_RV250_Ln 0x4C6E +#define PCI_CHIP_RAGE128MF 0x4D46 +#define PCI_CHIP_RAGE128ML 0x4D4C +#define PCI_CHIP_R300_ND 0x4E44 +#define PCI_CHIP_R300_NE 0x4E45 +#define PCI_CHIP_R300_NF 0x4E46 +#define PCI_CHIP_R300_NG 0x4E47 +#define PCI_CHIP_R350_NH 0x4E48 +#define PCI_CHIP_R350_NI 0x4E49 +#define PCI_CHIP_R360_NJ 0x4E4A +#define PCI_CHIP_R350_NK 0x4E4B +#define PCI_CHIP_RV350_NP 0x4E50 +#define PCI_CHIP_RV350_NQ 0x4E51 +#define PCI_CHIP_RV350_NR 0x4E52 +#define PCI_CHIP_RV350_NS 0x4E53 +#define PCI_CHIP_RV350_NT 0x4E54 +#define PCI_CHIP_RV350_NV 0x4E56 +#define PCI_CHIP_RAGE128PA 0x5041 +#define PCI_CHIP_RAGE128PB 0x5042 +#define PCI_CHIP_RAGE128PC 0x5043 +#define PCI_CHIP_RAGE128PD 0x5044 +#define PCI_CHIP_RAGE128PE 0x5045 +#define PCI_CHIP_RAGE128PF 0x5046 +#define PCI_CHIP_RAGE128PG 0x5047 +#define PCI_CHIP_RAGE128PH 0x5048 +#define PCI_CHIP_RAGE128PI 0x5049 +#define PCI_CHIP_RAGE128PJ 0x504A +#define PCI_CHIP_RAGE128PK 0x504B +#define PCI_CHIP_RAGE128PL 0x504C +#define PCI_CHIP_RAGE128PM 0x504D +#define PCI_CHIP_RAGE128PN 0x504E +#define PCI_CHIP_RAGE128PO 0x504F +#define PCI_CHIP_RAGE128PP 0x5050 +#define PCI_CHIP_RAGE128PQ 0x5051 +#define PCI_CHIP_RAGE128PR 0x5052 +#define PCI_CHIP_RAGE128PS 0x5053 +#define PCI_CHIP_RAGE128PT 0x5054 +#define PCI_CHIP_RAGE128PU 0x5055 +#define PCI_CHIP_RAGE128PV 0x5056 +#define PCI_CHIP_RAGE128PW 0x5057 +#define PCI_CHIP_RAGE128PX 0x5058 +#define PCI_CHIP_RADEON_QD 0x5144 +#define PCI_CHIP_RADEON_QE 0x5145 +#define PCI_CHIP_RADEON_QF 0x5146 +#define PCI_CHIP_RADEON_QG 0x5147 +#define PCI_CHIP_R200_QH 0x5148 +#define PCI_CHIP_R200_QI 0x5149 +#define PCI_CHIP_R200_QJ 0x514A +#define PCI_CHIP_R200_QK 0x514B +#define PCI_CHIP_R200_QL 0x514C +#define PCI_CHIP_R200_QM 0x514D +#define PCI_CHIP_R200_QN 0x514E +#define PCI_CHIP_R200_QO 0x514F +#define PCI_CHIP_RV200_QW 0x5157 +#define PCI_CHIP_RV200_QX 0x5158 +#define PCI_CHIP_RV100_QY 0x5159 +#define PCI_CHIP_RV100_QZ 0x515A +#define PCI_CHIP_RN50 0x515E +#define PCI_CHIP_RAGE128RE 0x5245 +#define PCI_CHIP_RAGE128RF 0x5246 +#define PCI_CHIP_RAGE128RG 0x5247 +#define PCI_CHIP_RAGE128RK 0x524B +#define PCI_CHIP_RAGE128RL 0x524C +#define PCI_CHIP_RAGE128SE 0x5345 +#define PCI_CHIP_RAGE128SF 0x5346 +#define PCI_CHIP_RAGE128SG 0x5347 +#define PCI_CHIP_RAGE128SH 0x5348 +#define PCI_CHIP_RAGE128SK 0x534B +#define PCI_CHIP_RAGE128SL 0x534C +#define PCI_CHIP_RAGE128SM 0x534D +#define PCI_CHIP_RAGE128SN 0x534E +#define PCI_CHIP_RAGE128TF 0x5446 +#define PCI_CHIP_RAGE128TL 0x544C +#define PCI_CHIP_RAGE128TR 0x5452 +#define PCI_CHIP_RAGE128TS 0x5453 +#define PCI_CHIP_RAGE128TT 0x5454 +#define PCI_CHIP_RAGE128TU 0x5455 +#define PCI_CHIP_RV370_5460 0x5460 +#define PCI_CHIP_RV370_5461 0x5461 +#define PCI_CHIP_RV370_5462 0x5462 +#define PCI_CHIP_RV370_5463 0x5463 +#define PCI_CHIP_RV370_5464 0x5464 +#define PCI_CHIP_RV370_5465 0x5465 +#define PCI_CHIP_RV370_5466 0x5466 +#define PCI_CHIP_RV370_5467 0x5467 +#define PCI_CHIP_R423_UH 0x5548 +#define PCI_CHIP_R423_UI 0x5549 +#define PCI_CHIP_R423_UJ 0x554A +#define PCI_CHIP_R423_UK 0x554B +#define PCI_CHIP_R423_UQ 0x5551 +#define PCI_CHIP_R423_UR 0x5552 +#define PCI_CHIP_R423_UT 0x5554 +#define PCI_CHIP_MACH64VT 0x5654 +#define PCI_CHIP_MACH64VU 0x5655 +#define PCI_CHIP_MACH64VV 0x5656 +#define PCI_CHIP_RS300_5834 0x5834 +#define PCI_CHIP_RS300_5835 0x5835 +#define PCI_CHIP_RS300_5836 0x5836 +#define PCI_CHIP_RS300_5837 0x5837 +#define PCI_CHIP_RV370_5B60 0x5B60 +#define PCI_CHIP_RV370_5B61 0x5B61 +#define PCI_CHIP_RV370_5B62 0x5B62 +#define PCI_CHIP_RV370_5B63 0x5B63 +#define PCI_CHIP_RV370_5B64 0x5B64 +#define PCI_CHIP_RV370_5B65 0x5B65 +#define PCI_CHIP_RV370_5B66 0x5B66 +#define PCI_CHIP_RV370_5B67 0x5B67 +#define PCI_CHIP_RV280_5960 0x5960 +#define PCI_CHIP_RV280_5961 0x5961 +#define PCI_CHIP_RV280_5962 0x5962 +#define PCI_CHIP_RV280_5964 0x5964 +#define PCI_CHIP_RV280_5C61 0x5C61 +#define PCI_CHIP_RV280_5C63 0x5C63 +#define PCI_CHIP_R423_5D57 0x5D57 +#define PCI_CHIP_RS350_7834 0x7834 +#define PCI_CHIP_RS350_7835 0x7835 diff --git a/qemu/roms/u-boot/drivers/video/ati_radeon_fb.c b/qemu/roms/u-boot/drivers/video/ati_radeon_fb.c new file mode 100644 index 000000000..38d2eb107 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/ati_radeon_fb.c @@ -0,0 +1,764 @@ +/* + * ATI Radeon Video card Framebuffer driver. + * + * Copyright 2007 Freescale Semiconductor, Inc. + * Zhang Wei <wei.zhang@freescale.com> + * Jason Jin <jason.jin@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Some codes of this file is partly ported from Linux kernel + * ATI video framebuffer driver. + * + * Now the driver is tested on below ATI chips: + * 9200 + * X300 + * X700 + */ + +#include <common.h> + +#include <command.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <malloc.h> +#include <video_fb.h> +#include "videomodes.h" + +#include <radeon.h> +#include "ati_ids.h" +#include "ati_radeon_fb.h" + +#undef DEBUG + +#ifdef DEBUG +#define DPRINT(x...) printf(x) +#else +#define DPRINT(x...) do{}while(0) +#endif + +#ifndef min_t +#define min_t(type,x,y) \ + ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) +#endif + +#define MAX_MAPPED_VRAM (2048*2048*4) +#define MIN_MAPPED_VRAM (1024*768*1) + +#define RADEON_BUFFER_ALIGN 0x00000fff +#define SURF_UPPER_BOUND(x,y,bpp) (((((x) * (((y) + 15) & ~15) * (bpp)/8) + RADEON_BUFFER_ALIGN) \ + & ~RADEON_BUFFER_ALIGN) - 1) +#define RADEON_CRT_PITCH(width, bpp) ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) | \ + ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) << 16)) + +#define CRTC_H_TOTAL_DISP_VAL(htotal, hdisp) \ + (((((htotal) / 8) - 1) & 0x3ff) | (((((hdisp) / 8) - 1) & 0x1ff) << 16)) +#define CRTC_HSYNC_STRT_WID_VAL(hsync_srtr, hsync_wid) \ + (((hsync_srtr) & 0x1fff) | (((hsync_wid) & 0x3f) << 16)) +#define CRTC_V_TOTAL_DISP_VAL(vtotal, vdisp) \ + ((((vtotal) - 1) & 0xffff) | (((vdisp) - 1) << 16)) +#define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ + ((((vsync_srtr) - 1) & 0xfff) | (((vsync_wid) & 0x1f) << 16)) + +/*#define PCI_VENDOR_ID_ATI*/ +#define PCI_CHIP_RV280_5960 0x5960 +#define PCI_CHIP_RV280_5961 0x5961 +#define PCI_CHIP_RV280_5962 0x5962 +#define PCI_CHIP_RV280_5964 0x5964 +#define PCI_CHIP_RV280_5C63 0x5C63 +#define PCI_CHIP_RV370_5B60 0x5B60 +#define PCI_CHIP_RV380_5657 0x5657 +#define PCI_CHIP_R420_554d 0x554d + +static struct pci_device_id ati_radeon_pci_ids[] = { + {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5960}, + {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5961}, + {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5962}, + {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5964}, + {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5C63}, + {PCI_VENDOR_ID_ATI, PCI_CHIP_RV370_5B60}, + {PCI_VENDOR_ID_ATI, PCI_CHIP_RV380_5657}, + {PCI_VENDOR_ID_ATI, PCI_CHIP_R420_554d}, + {0, 0} +}; + +static u16 ati_radeon_id_family_table[][2] = { + {PCI_CHIP_RV280_5960, CHIP_FAMILY_RV280}, + {PCI_CHIP_RV280_5961, CHIP_FAMILY_RV280}, + {PCI_CHIP_RV280_5962, CHIP_FAMILY_RV280}, + {PCI_CHIP_RV280_5964, CHIP_FAMILY_RV280}, + {PCI_CHIP_RV280_5C63, CHIP_FAMILY_RV280}, + {PCI_CHIP_RV370_5B60, CHIP_FAMILY_RV380}, + {PCI_CHIP_RV380_5657, CHIP_FAMILY_RV380}, + {PCI_CHIP_R420_554d, CHIP_FAMILY_R420}, + {0, 0} +}; + +u16 get_radeon_id_family(u16 device) +{ + int i; + for (i=0; ati_radeon_id_family_table[0][i]; i+=2) + if (ati_radeon_id_family_table[0][i] == device) + return ati_radeon_id_family_table[0][i + 1]; + return 0; +} + +struct radeonfb_info *rinfo; + +static void radeon_identify_vram(struct radeonfb_info *rinfo) +{ + u32 tmp; + + /* framebuffer size */ + if ((rinfo->family == CHIP_FAMILY_RS100) || + (rinfo->family == CHIP_FAMILY_RS200) || + (rinfo->family == CHIP_FAMILY_RS300)) { + u32 tom = INREG(NB_TOM); + tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); + + radeon_fifo_wait(6); + OUTREG(MC_FB_LOCATION, tom); + OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); + OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); + OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16); + + /* This is supposed to fix the crtc2 noise problem. */ + OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000); + + if ((rinfo->family == CHIP_FAMILY_RS100) || + (rinfo->family == CHIP_FAMILY_RS200)) { + /* This is to workaround the asic bug for RMX, some versions + of BIOS dosen't have this register initialized correctly. + */ + OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN, + ~CRTC_H_CUTOFF_ACTIVE_EN); + } + } else { + tmp = INREG(CONFIG_MEMSIZE); + } + + /* mem size is bits [28:0], mask off the rest */ + rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK; + + /* + * Hack to get around some busted production M6's + * reporting no ram + */ + if (rinfo->video_ram == 0) { + switch (rinfo->pdev.device) { + case PCI_CHIP_RADEON_LY: + case PCI_CHIP_RADEON_LZ: + rinfo->video_ram = 8192 * 1024; + break; + default: + break; + } + } + + /* + * Now try to identify VRAM type + */ + if ((rinfo->family >= CHIP_FAMILY_R300) || + (INREG(MEM_SDRAM_MODE_REG) & (1<<30))) + rinfo->vram_ddr = 1; + else + rinfo->vram_ddr = 0; + + tmp = INREG(MEM_CNTL); + if (IS_R300_VARIANT(rinfo)) { + tmp &= R300_MEM_NUM_CHANNELS_MASK; + switch (tmp) { + case 0: rinfo->vram_width = 64; break; + case 1: rinfo->vram_width = 128; break; + case 2: rinfo->vram_width = 256; break; + default: rinfo->vram_width = 128; break; + } + } else if ((rinfo->family == CHIP_FAMILY_RV100) || + (rinfo->family == CHIP_FAMILY_RS100) || + (rinfo->family == CHIP_FAMILY_RS200)){ + if (tmp & RV100_MEM_HALF_MODE) + rinfo->vram_width = 32; + else + rinfo->vram_width = 64; + } else { + if (tmp & MEM_NUM_CHANNELS_MASK) + rinfo->vram_width = 128; + else + rinfo->vram_width = 64; + } + + /* This may not be correct, as some cards can have half of channel disabled + * ToDo: identify these cases + */ + + DPRINT("radeonfb: Found %dk of %s %d bits wide videoram\n", + rinfo->video_ram / 1024, + rinfo->vram_ddr ? "DDR" : "SDRAM", + rinfo->vram_width); + +} + +static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode) +{ + int i; + + radeon_fifo_wait(20); + +#if 0 + /* Workaround from XFree */ + if (rinfo->is_mobility) { + /* A temporal workaround for the occational blanking on certain laptop + * panels. This appears to related to the PLL divider registers + * (fail to lock?). It occurs even when all dividers are the same + * with their old settings. In this case we really don't need to + * fiddle with PLL registers. By doing this we can avoid the blanking + * problem with some panels. + */ + if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && + (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & + (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) { + /* We still have to force a switch to selected PPLL div thanks to + * an XFree86 driver bug which will switch it away in some cases + * even when using UseFDev */ + OUTREGP(CLOCK_CNTL_INDEX, + mode->clk_cntl_index & PPLL_DIV_SEL_MASK, + ~PPLL_DIV_SEL_MASK); + radeon_pll_errata_after_index(rinfo); + radeon_pll_errata_after_data(rinfo); + return; + } + } +#endif + if(rinfo->pdev.device == PCI_CHIP_RV370_5B60) return; + + /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ + OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); + + /* Reset PPLL & enable atomic update */ + OUTPLLP(PPLL_CNTL, + PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN, + ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); + + /* Switch to selected PPLL divider */ + OUTREGP(CLOCK_CNTL_INDEX, + mode->clk_cntl_index & PPLL_DIV_SEL_MASK, + ~PPLL_DIV_SEL_MASK); + + /* Set PPLL ref. div */ + if (rinfo->family == CHIP_FAMILY_R300 || + rinfo->family == CHIP_FAMILY_RS300 || + rinfo->family == CHIP_FAMILY_R350 || + rinfo->family == CHIP_FAMILY_RV350) { + if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { + /* When restoring console mode, use saved PPLL_REF_DIV + * setting. + */ + OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); + } else { + /* R300 uses ref_div_acc field as real ref divider */ + OUTPLLP(PPLL_REF_DIV, + (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), + ~R300_PPLL_REF_DIV_ACC_MASK); + } + } else + OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); + + /* Set PPLL divider 3 & post divider*/ + OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); + OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); + + /* Write update */ + while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R) + ; + OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W); + + /* Wait read update complete */ + /* FIXME: Certain revisions of R300 can't recover here. Not sure of + the cause yet, but this workaround will mask the problem for now. + Other chips usually will pass at the very first test, so the + workaround shouldn't have any effect on them. */ + for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++) + ; + + OUTPLL(HTOTAL_CNTL, 0); + + /* Clear reset & atomic update */ + OUTPLLP(PPLL_CNTL, 0, + ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); + + /* We may want some locking ... oh well */ + udelay(5000); + + /* Switch back VCLK source to PPLL */ + OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); +} + +typedef struct { + u16 reg; + u32 val; +} reg_val; + +#if 0 /* unused ? -> scheduled for removal */ +/* these common regs are cleared before mode setting so they do not + * interfere with anything + */ +static reg_val common_regs[] = { + { OVR_CLR, 0 }, + { OVR_WID_LEFT_RIGHT, 0 }, + { OVR_WID_TOP_BOTTOM, 0 }, + { OV0_SCALE_CNTL, 0 }, + { SUBPIC_CNTL, 0 }, + { VIPH_CONTROL, 0 }, + { I2C_CNTL_1, 0 }, + { GEN_INT_CNTL, 0 }, + { CAP0_TRIG_CNTL, 0 }, + { CAP1_TRIG_CNTL, 0 }, +}; +#endif /* 0 */ + +void radeon_setmode(void) +{ + struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); + + mode->crtc_gen_cntl = 0x03000200; + mode->crtc_ext_cntl = 0x00008048; + mode->dac_cntl = 0xff002100; + mode->crtc_h_total_disp = 0x4f0063; + mode->crtc_h_sync_strt_wid = 0x8c02a2; + mode->crtc_v_total_disp = 0x01df020c; + mode->crtc_v_sync_strt_wid = 0x8201ea; + mode->crtc_pitch = 0x00500050; + + OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); + OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, + ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); + OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); + OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); + OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); + OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); + OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); + OUTREG(CRTC_OFFSET, 0); + OUTREG(CRTC_OFFSET_CNTL, 0); + OUTREG(CRTC_PITCH, mode->crtc_pitch); + + mode->clk_cntl_index = 0x300; + mode->ppll_ref_div = 0xc; + mode->ppll_div_3 = 0x00030059; + + radeon_write_pll_regs(rinfo, mode); +} + +static void set_pal(void) +{ + int idx, val = 0; + + for (idx = 0; idx < 256; idx++) { + OUTREG8(PALETTE_INDEX, idx); + OUTREG(PALETTE_DATA, val); + val += 0x00010101; + } +} + +void radeon_setmode_9200(int vesa_idx, int bpp) +{ + struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); + + mode->crtc_gen_cntl = CRTC_EN | CRTC_EXT_DISP_EN; + mode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON; + mode->dac_cntl = DAC_MASK_ALL | DAC_VGA_ADR_EN | DAC_8BIT_EN; + mode->crtc_offset_cntl = CRTC_OFFSET_CNTL__CRTC_TILE_EN; + + switch (bpp) { + case 24: + mode->crtc_gen_cntl |= 0x6 << 8; /* x888 */ +#if defined(__BIG_ENDIAN) + mode->surface_cntl = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; + mode->surf_info[0] = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; +#endif + break; + case 16: + mode->crtc_gen_cntl |= 0x4 << 8; /* 565 */ +#if defined(__BIG_ENDIAN) + mode->surface_cntl = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; + mode->surf_info[0] = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; +#endif + break; + default: + mode->crtc_gen_cntl |= 0x2 << 8; /* palette */ + mode->surface_cntl = 0x00000000; + break; + } + + switch (vesa_idx) { + case RES_MODE_1280x1024: + mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1688,1280); + mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(1066,1024); + mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); +#if defined(CONFIG_RADEON_VREFRESH_75HZ) + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1288,18); + mode->ppll_div_3 = 0x00010078; +#else /* default @ 60 Hz */ + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1320,14); + mode->ppll_div_3 = 0x00010060; +#endif + /* + * for this mode pitch expands to the same value for 32, 16 and 8 bpp, + * so we set it here once only. + */ + mode->crtc_pitch = RADEON_CRT_PITCH(1280,32); + switch (bpp) { + case 24: + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 4 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,32); + break; + case 16: + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 2 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,16); + break; + default: /* 8 bpp */ + mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1280 * 1 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,8); + break; + } + break; + case RES_MODE_1024x768: +#if defined(CONFIG_RADEON_VREFRESH_75HZ) + mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1312,1024); + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1032,12); + mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(800,768); + mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); + mode->ppll_div_3 = 0x0002008c; +#else /* @ 60 Hz */ + mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1344,1024); + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1040,17) | CRTC_H_SYNC_POL; + mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(806,768); + mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) | CRTC_V_SYNC_POL; + mode->ppll_div_3 = 0x00020074; +#endif + /* also same pitch value for 32, 16 and 8 bpp */ + mode->crtc_pitch = RADEON_CRT_PITCH(1024,32); + switch (bpp) { + case 24: + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 4 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,32); + break; + case 16: + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 2 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,16); + break; + default: /* 8 bpp */ + mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,8); + break; + } + break; + case RES_MODE_800x600: + mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1056,800); +#if defined(CONFIG_RADEON_VREFRESH_75HZ) + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(808,10); + mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(625,600); + mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); + mode->ppll_div_3 = 0x000300b0; +#else /* @ 60 Hz */ + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(832,16); + mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(628,600); + mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); + mode->ppll_div_3 = 0x0003008e; +#endif + switch (bpp) { + case 24: + mode->crtc_pitch = RADEON_CRT_PITCH(832,32); + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (832 * 4 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(832,600,32); + break; + case 16: + mode->crtc_pitch = RADEON_CRT_PITCH(896,16); + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (896 * 2 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(896,600,16); + break; + default: /* 8 bpp */ + mode->crtc_pitch = RADEON_CRT_PITCH(1024,8); + mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,600,8); + break; + } + break; + default: /* RES_MODE_640x480 */ +#if defined(CONFIG_RADEON_VREFRESH_75HZ) + mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(840,640); + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(648,8) | CRTC_H_SYNC_POL; + mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(500,480); + mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) | CRTC_V_SYNC_POL; + mode->ppll_div_3 = 0x00030070; +#else /* @ 60 Hz */ + mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(800,640); + mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(674,12) | CRTC_H_SYNC_POL; + mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(525,480); + mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) | CRTC_V_SYNC_POL; + mode->ppll_div_3 = 0x00030059; +#endif + /* also same pitch value for 32, 16 and 8 bpp */ + mode->crtc_pitch = RADEON_CRT_PITCH(640,32); + switch (bpp) { + case 24: + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 4 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,32); + break; + case 16: + mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 2 / 16); + mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,16); + break; + default: /* 8 bpp */ + mode->crtc_offset_cntl = 0x00000000; + break; + } + break; + } + + OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl | CRTC_DISP_REQ_EN_B); + OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, + (CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); + OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); + OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); + OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); + OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); + OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); + OUTREG(CRTC_OFFSET, 0); + OUTREG(CRTC_OFFSET_CNTL, mode->crtc_offset_cntl); + OUTREG(CRTC_PITCH, mode->crtc_pitch); + OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); + + mode->clk_cntl_index = 0x300; + mode->ppll_ref_div = 0xc; + + radeon_write_pll_regs(rinfo, mode); + + OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, + ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); + OUTREG(SURFACE0_INFO, mode->surf_info[0]); + OUTREG(SURFACE0_LOWER_BOUND, 0); + OUTREG(SURFACE0_UPPER_BOUND, mode->surf_upper_bound[0]); + OUTREG(SURFACE_CNTL, mode->surface_cntl); + + if (bpp > 8) + set_pal(); + + free(mode); +} + +#include "../bios_emulator/include/biosemu.h" +extern int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp); + +int radeon_probe(struct radeonfb_info *rinfo) +{ + pci_dev_t pdev; + u16 did; + + pdev = pci_find_devices(ati_radeon_pci_ids, 0); + + if (pdev != -1) { + pci_read_config_word(pdev, PCI_DEVICE_ID, &did); + printf("ATI Radeon video card (%04x, %04x) found @(%d:%d:%d)\n", + PCI_VENDOR_ID_ATI, did, (pdev >> 16) & 0xff, + (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); + + strcpy(rinfo->name, "ATI Radeon"); + rinfo->pdev.vendor = PCI_VENDOR_ID_ATI; + rinfo->pdev.device = did; + rinfo->family = get_radeon_id_family(rinfo->pdev.device); + pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, + &rinfo->fb_base_bus); + pci_read_config_dword(pdev, PCI_BASE_ADDRESS_2, + &rinfo->mmio_base_bus); + rinfo->fb_base_bus &= 0xfffff000; + rinfo->mmio_base_bus &= ~0x04; + + rinfo->mmio_base = pci_bus_to_virt(pdev, rinfo->mmio_base_bus, + PCI_REGION_MEM, 0, MAP_NOCACHE); + DPRINT("rinfo->mmio_base = 0x%p bus=0x%x\n", + rinfo->mmio_base, rinfo->mmio_base_bus); + rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; + DPRINT("rinfo->fb_local_base = 0x%x\n",rinfo->fb_local_base); + /* PostBIOS with x86 emulater */ + if (!BootVideoCardBIOS(pdev, NULL, 0)) + return -1; + + /* + * Check for errata + * (These will be added in the future for the chipfamily + * R300, RV200, RS200, RV100, RS100.) + */ + + /* Get VRAM size and type */ + radeon_identify_vram(rinfo); + + rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, + rinfo->video_ram); + rinfo->fb_base = pci_bus_to_virt(pdev, rinfo->fb_base_bus, + PCI_REGION_MEM, 0, MAP_NOCACHE); + DPRINT("Radeon: framebuffer base address 0x%08x, " + "bus address 0x%08x\n" + "MMIO base address 0x%08x, bus address 0x%08x, " + "framebuffer local base 0x%08x.\n ", + (u32)rinfo->fb_base, rinfo->fb_base_bus, + (u32)rinfo->mmio_base, rinfo->mmio_base_bus, + rinfo->fb_local_base); + return 0; + } + return -1; +} + +/* + * The Graphic Device + */ +GraphicDevice ctfb; + +#define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */ +#define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */ +#define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */ +#define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */ + +void *video_hw_init(void) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + u32 *vm; + char *penv; + unsigned long t1, hsynch, vsynch; + int bits_per_pixel, i, tmp, vesa_idx = 0, videomode; + struct ctfb_res_modes *res_mode; + struct ctfb_res_modes var_mode; + + rinfo = malloc(sizeof(struct radeonfb_info)); + + printf("Video: "); + if(radeon_probe(rinfo)) { + printf("No radeon video card found!\n"); + return NULL; + } + + tmp = 0; + + videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE; + /* get video mode via environment */ + if ((penv = getenv ("videomode")) != NULL) { + /* deceide if it is a string */ + if (penv[0] <= '9') { + videomode = (int) simple_strtoul (penv, NULL, 16); + tmp = 1; + } + } else { + tmp = 1; + } + if (tmp) { + /* parameter are vesa modes */ + /* search params */ + for (i = 0; i < VESA_MODES_COUNT; i++) { + if (vesa_modes[i].vesanr == videomode) + break; + } + if (i == VESA_MODES_COUNT) { + printf ("no VESA Mode found, switching to mode 0x%x ", CONFIG_SYS_DEFAULT_VIDEO_MODE); + i = 0; + } + res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex]; + bits_per_pixel = vesa_modes[i].bits_per_pixel; + vesa_idx = vesa_modes[i].resindex; + } else { + res_mode = (struct ctfb_res_modes *) &var_mode; + bits_per_pixel = video_get_params (res_mode, penv); + } + + /* calculate hsynch and vsynch freq (info only) */ + t1 = (res_mode->left_margin + res_mode->xres + + res_mode->right_margin + res_mode->hsync_len) / 8; + t1 *= 8; + t1 *= res_mode->pixclock; + t1 /= 1000; + hsynch = 1000000000L / t1; + t1 *= (res_mode->upper_margin + res_mode->yres + + res_mode->lower_margin + res_mode->vsync_len); + t1 /= 1000; + vsynch = 1000000000L / t1; + + /* fill in Graphic device struct */ + sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, + res_mode->yres, bits_per_pixel, (hsynch / 1000), + (vsynch / 1000)); + printf ("%s\n", pGD->modeIdent); + pGD->winSizeX = res_mode->xres; + pGD->winSizeY = res_mode->yres; + pGD->plnSizeX = res_mode->xres; + pGD->plnSizeY = res_mode->yres; + + switch (bits_per_pixel) { + case 24: + pGD->gdfBytesPP = 4; + pGD->gdfIndex = GDF_32BIT_X888RGB; + if (res_mode->xres == 800) { + pGD->winSizeX = 832; + pGD->plnSizeX = 832; + } + break; + case 16: + pGD->gdfBytesPP = 2; + pGD->gdfIndex = GDF_16BIT_565RGB; + if (res_mode->xres == 800) { + pGD->winSizeX = 896; + pGD->plnSizeX = 896; + } + break; + default: + if (res_mode->xres == 800) { + pGD->winSizeX = 1024; + pGD->plnSizeX = 1024; + } + pGD->gdfBytesPP = 1; + pGD->gdfIndex = GDF__8BIT_INDEX; + break; + } + + pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS; + pGD->pciBase = (unsigned int)rinfo->fb_base; + pGD->frameAdrs = (unsigned int)rinfo->fb_base; + pGD->memSize = 64 * 1024 * 1024; + + /* Cursor Start Address */ + pGD->dprBase = (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + + (unsigned int)rinfo->fb_base; + if ((pGD->dprBase & 0x0fff) != 0) { + /* allign it */ + pGD->dprBase &= 0xfffff000; + pGD->dprBase += 0x00001000; + } + DPRINT ("Cursor Start %x Pattern Start %x\n", pGD->dprBase, + PATTERN_ADR); + pGD->vprBase = (unsigned int)rinfo->fb_base; /* Dummy */ + pGD->cprBase = (unsigned int)rinfo->fb_base; /* Dummy */ + /* set up Hardware */ + + /* Clear video memory (only visible screen area) */ + i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4; + vm = (unsigned int *) pGD->pciBase; + while (i--) + *vm++ = 0; + /*SetDrawingEngine (bits_per_pixel);*/ + + if (rinfo->family == CHIP_FAMILY_RV280) + radeon_setmode_9200(vesa_idx, bits_per_pixel); + else + radeon_setmode(); + + return ((void *) pGD); +} + +void video_set_lut (unsigned int index, /* color number */ + unsigned char r, /* red */ + unsigned char g, /* green */ + unsigned char b /* blue */ + ) +{ + OUTREG(PALETTE_INDEX, index); + OUTREG(PALETTE_DATA, (r << 16) | (g << 8) | b); +} diff --git a/qemu/roms/u-boot/drivers/video/ati_radeon_fb.h b/qemu/roms/u-boot/drivers/video/ati_radeon_fb.h new file mode 100644 index 000000000..9dd638bb9 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/ati_radeon_fb.h @@ -0,0 +1,282 @@ +#ifndef __ATI_RADEON_FB_H +#define __ATI_RADEON_FB_H + +/*************************************************************** + * Most of the definitions here are adapted right from XFree86 * + ***************************************************************/ + +/* + * Chip families. Must fit in the low 16 bits of a long word + */ +enum radeon_family { + CHIP_FAMILY_UNKNOW, + CHIP_FAMILY_LEGACY, + CHIP_FAMILY_RADEON, + CHIP_FAMILY_RV100, + CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ + CHIP_FAMILY_RV200, + CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), + RS250 (IGP 7000) */ + CHIP_FAMILY_R200, + CHIP_FAMILY_RV250, + CHIP_FAMILY_RS300, /* Radeon 9000 IGP */ + CHIP_FAMILY_RV280, + CHIP_FAMILY_R300, + CHIP_FAMILY_R350, + CHIP_FAMILY_RV350, + CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ + CHIP_FAMILY_R420, /* R420/R423/M18 */ + CHIP_FAMILY_LAST, +}; + +#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \ + ((rinfo)->family == CHIP_FAMILY_RV200) || \ + ((rinfo)->family == CHIP_FAMILY_RS100) || \ + ((rinfo)->family == CHIP_FAMILY_RS200) || \ + ((rinfo)->family == CHIP_FAMILY_RV250) || \ + ((rinfo)->family == CHIP_FAMILY_RV280) || \ + ((rinfo)->family == CHIP_FAMILY_RS300)) + +#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \ + ((rinfo)->family == CHIP_FAMILY_RV350) || \ + ((rinfo)->family == CHIP_FAMILY_R350) || \ + ((rinfo)->family == CHIP_FAMILY_RV380) || \ + ((rinfo)->family == CHIP_FAMILY_R420)) + +struct radeonfb_info { + char name[20]; + + struct pci_device_id pdev; + u16 family; + + u32 fb_base_bus; + u32 mmio_base_bus; + + void *mmio_base; + void *fb_base; + + u32 video_ram; + u32 mapped_vram; + int vram_width; + int vram_ddr; + + u32 fb_local_base; +}; + +#define INREG8(addr) readb((rinfo->mmio_base)+addr) +#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr) +#define INREG16(addr) readw((rinfo->mmio_base)+addr) +#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr) +#define INREG(addr) readl((rinfo->mmio_base)+addr) +#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) + +static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, + u32 val, u32 mask) +{ + unsigned int tmp; + + tmp = INREG(addr); + tmp &= (mask); + tmp |= (val); + OUTREG(addr, tmp); +} + +#define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask) + +/* + * 2D Engine helper routines + */ +static inline void radeon_engine_flush (struct radeonfb_info *rinfo) +{ + int i; + + /* initiate flush */ + OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, + ~RB2D_DC_FLUSH_ALL); + + for (i=0; i < 2000000; i++) { + if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) + return; + udelay(1); + } + printf("radeonfb: Flush Timeout !\n"); +} + +static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) +{ + int i; + + for (i=0; i<2000000; i++) { + if ((INREG(RBBM_STATUS) & 0x7f) >= entries) + return; + udelay(1); + } + printf("radeonfb: FIFO Timeout !\n"); +} + +static inline void _radeon_engine_idle(struct radeonfb_info *rinfo) +{ + int i; + + /* ensure FIFO is empty before waiting for idle */ + _radeon_fifo_wait (rinfo, 64); + + for (i=0; i<2000000; i++) { + if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { + radeon_engine_flush (rinfo); + return; + } + udelay(1); + } + printf("radeonfb: Idle Timeout !\n"); +} + +#define radeon_engine_idle() _radeon_engine_idle(rinfo) +#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries) +#define radeon_msleep(ms) _radeon_msleep(rinfo,ms) + +/* + * This structure contains the various registers manipulated by this + * driver for setting or restoring a mode. It's mostly copied from + * XFree's RADEONSaveRec structure. A few chip settings might still be + * tweaked without beeing reflected or saved in these registers though + */ +struct radeon_regs { + /* Common registers */ + u32 ovr_clr; + u32 ovr_wid_left_right; + u32 ovr_wid_top_bottom; + u32 ov0_scale_cntl; + u32 mpp_tb_config; + u32 mpp_gp_config; + u32 subpic_cntl; + u32 viph_control; + u32 i2c_cntl_1; + u32 gen_int_cntl; + u32 cap0_trig_cntl; + u32 cap1_trig_cntl; + u32 bus_cntl; + u32 surface_cntl; + u32 bios_5_scratch; + + /* Other registers to save for VT switches or driver load/unload */ + u32 dp_datatype; + u32 rbbm_soft_reset; + u32 clock_cntl_index; + u32 amcgpio_en_reg; + u32 amcgpio_mask; + + /* Surface/tiling registers */ + u32 surf_lower_bound[8]; + u32 surf_upper_bound[8]; + u32 surf_info[8]; + + /* CRTC registers */ + u32 crtc_gen_cntl; + u32 crtc_ext_cntl; + u32 dac_cntl; + u32 crtc_h_total_disp; + u32 crtc_h_sync_strt_wid; + u32 crtc_v_total_disp; + u32 crtc_v_sync_strt_wid; + u32 crtc_offset; + u32 crtc_offset_cntl; + u32 crtc_pitch; + u32 disp_merge_cntl; + u32 grph_buffer_cntl; + u32 crtc_more_cntl; + + /* CRTC2 registers */ + u32 crtc2_gen_cntl; + u32 dac2_cntl; + u32 disp_output_cntl; + u32 disp_hw_debug; + u32 disp2_merge_cntl; + u32 grph2_buffer_cntl; + u32 crtc2_h_total_disp; + u32 crtc2_h_sync_strt_wid; + u32 crtc2_v_total_disp; + u32 crtc2_v_sync_strt_wid; + u32 crtc2_offset; + u32 crtc2_offset_cntl; + u32 crtc2_pitch; + + /* Flat panel regs */ + u32 fp_crtc_h_total_disp; + u32 fp_crtc_v_total_disp; + u32 fp_gen_cntl; + u32 fp2_gen_cntl; + u32 fp_h_sync_strt_wid; + u32 fp2_h_sync_strt_wid; + u32 fp_horz_stretch; + u32 fp_panel_cntl; + u32 fp_v_sync_strt_wid; + u32 fp2_v_sync_strt_wid; + u32 fp_vert_stretch; + u32 lvds_gen_cntl; + u32 lvds_pll_cntl; + u32 tmds_crc; + u32 tmds_transmitter_cntl; + + /* Computed values for PLL */ + u32 dot_clock_freq; + int feedback_div; + int post_div; + + /* PLL registers */ + u32 ppll_div_3; + u32 ppll_ref_div; + u32 vclk_ecp_cntl; + u32 clk_cntl_index; + + /* Computed values for PLL2 */ + u32 dot_clock_freq_2; + int feedback_div_2; + int post_div_2; + + /* PLL2 registers */ + u32 p2pll_ref_div; + u32 p2pll_div_0; + u32 htotal_cntl2; + + /* Palette */ + int palette_valid; +}; + +static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr) +{ + u32 data; + + OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); + /* radeon_pll_errata_after_index(rinfo); */ + data = INREG(CLOCK_CNTL_DATA); + /* radeon_pll_errata_after_data(rinfo); */ + return data; +} + +static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, + u32 val) +{ + + OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); + /* radeon_pll_errata_after_index(rinfo); */ + OUTREG(CLOCK_CNTL_DATA, val); + /* radeon_pll_errata_after_data(rinfo); */ +} + +static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index, + u32 val, u32 mask) +{ + unsigned int tmp; + + tmp = __INPLL(rinfo, index); + tmp &= (mask); + tmp |= (val); + __OUTPLL(rinfo, index, tmp); +} + +#define INPLL(addr) __INPLL(rinfo, addr) +#define OUTPLL(index, val) __OUTPLL(rinfo, index, val) +#define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask) + +#endif diff --git a/qemu/roms/u-boot/drivers/video/atmel_hlcdfb.c b/qemu/roms/u-boot/drivers/video/atmel_hlcdfb.c new file mode 100644 index 000000000..bb4d7d8c1 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/atmel_hlcdfb.c @@ -0,0 +1,197 @@ +/* + * Driver for AT91/AT32 MULTI LAYER LCD Controller + * + * Copyright (C) 2012 Atmel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/gpio.h> +#include <asm/arch/clk.h> +#include <lcd.h> +#include <atmel_hlcdc.h> + +/* configurable parameters */ +#define ATMEL_LCDC_CVAL_DEFAULT 0xc8 +#define ATMEL_LCDC_DMA_BURST_LEN 8 +#ifndef ATMEL_LCDC_GUARD_TIME +#define ATMEL_LCDC_GUARD_TIME 1 +#endif + +#define ATMEL_LCDC_FIFO_SIZE 512 + +#define lcdc_readl(reg) __raw_readl((reg)) +#define lcdc_writel(reg, val) __raw_writel((val), (reg)) + +/* + * the CLUT register map as following + * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0) + */ +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ + lcdc_writel(((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk) + | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk) + | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk), + panel_info.mmio + ATMEL_LCDC_LUT(regno)); +} + +void lcd_ctrl_init(void *lcdbase) +{ + unsigned long value; + struct lcd_dma_desc *desc; + struct atmel_hlcd_regs *regs; + + if (!has_lcdc()) + return; /* No lcdc */ + + regs = (struct atmel_hlcd_regs *)panel_info.mmio; + + /* Disable DISP signal */ + lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_DISPDIS); + while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS)) + udelay(1); + /* Disable synchronization */ + lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_SYNCDIS); + while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS)) + udelay(1); + /* Disable pixel clock */ + lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_CLKDIS); + while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS)) + udelay(1); + /* Disable PWM */ + lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_PWMDIS); + while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS)) + udelay(1); + + /* Set pixel clock */ + value = get_lcdc_clk_rate(0) / panel_info.vl_clk; + if (get_lcdc_clk_rate(0) % panel_info.vl_clk) + value++; + + if (value < 1) { + /* Using system clock as pixel clock */ + lcdc_writel(®s->lcdc_lcdcfg0, + LCDC_LCDCFG0_CLKDIV(0) + | LCDC_LCDCFG0_CGDISHCR + | LCDC_LCDCFG0_CGDISHEO + | LCDC_LCDCFG0_CGDISOVR1 + | LCDC_LCDCFG0_CGDISBASE + | panel_info.vl_clk_pol + | LCDC_LCDCFG0_CLKSEL); + + } else { + lcdc_writel(®s->lcdc_lcdcfg0, + LCDC_LCDCFG0_CLKDIV(value - 2) + | LCDC_LCDCFG0_CGDISHCR + | LCDC_LCDCFG0_CGDISHEO + | LCDC_LCDCFG0_CGDISOVR1 + | LCDC_LCDCFG0_CGDISBASE + | panel_info.vl_clk_pol); + } + + /* Initialize control register 5 */ + value = 0; + + value |= panel_info.vl_sync; + +#ifndef LCD_OUTPUT_BPP + /* Output is 24bpp */ + value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP; +#else + switch (LCD_OUTPUT_BPP) { + case 12: + value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP; + break; + case 16: + value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP; + break; + case 18: + value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP; + break; + case 24: + value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP; + break; + default: + BUG(); + break; + } +#endif + + value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME); + value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS); + lcdc_writel(®s->lcdc_lcdcfg5, value); + + /* Vertical & Horizontal Timing */ + value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1); + value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1); + lcdc_writel(®s->lcdc_lcdcfg1, value); + + value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin); + value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1); + lcdc_writel(®s->lcdc_lcdcfg2, value); + + value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1); + value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1); + lcdc_writel(®s->lcdc_lcdcfg3, value); + + /* Display size */ + value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1); + value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1); + lcdc_writel(®s->lcdc_lcdcfg4, value); + + lcdc_writel(®s->lcdc_basecfg0, + LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO); + + switch (NBITS(panel_info.vl_bpix)) { + case 16: + lcdc_writel(®s->lcdc_basecfg1, + LCDC_BASECFG1_RGBMODE_16BPP_RGB_565); + break; + default: + BUG(); + break; + } + + lcdc_writel(®s->lcdc_basecfg2, LCDC_BASECFG2_XSTRIDE(0)); + lcdc_writel(®s->lcdc_basecfg3, 0); + lcdc_writel(®s->lcdc_basecfg4, LCDC_BASECFG4_DMA); + + /* Disable all interrupts */ + lcdc_writel(®s->lcdc_lcdidr, ~0UL); + lcdc_writel(®s->lcdc_baseidr, ~0UL); + + /* Setup the DMA descriptor, this descriptor will loop to itself */ + desc = (struct lcd_dma_desc *)(lcdbase - 16); + + desc->address = (u32)lcdbase; + /* Disable DMA transfer interrupt & descriptor loaded interrupt. */ + desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN + | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH; + desc->next = (u32)desc; + + lcdc_writel(®s->lcdc_baseaddr, desc->address); + lcdc_writel(®s->lcdc_basectrl, desc->control); + lcdc_writel(®s->lcdc_basenext, desc->next); + lcdc_writel(®s->lcdc_basecher, LCDC_BASECHER_CHEN | + LCDC_BASECHER_UPDATEEN); + + /* Enable LCD */ + value = lcdc_readl(®s->lcdc_lcden); + lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_CLKEN); + while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS)) + udelay(1); + value = lcdc_readl(®s->lcdc_lcden); + lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_SYNCEN); + while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS)) + udelay(1); + value = lcdc_readl(®s->lcdc_lcden); + lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_DISPEN); + while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS)) + udelay(1); + value = lcdc_readl(®s->lcdc_lcden); + lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_PWMEN); + while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS)) + udelay(1); +} diff --git a/qemu/roms/u-boot/drivers/video/atmel_lcdfb.c b/qemu/roms/u-boot/drivers/video/atmel_lcdfb.c new file mode 100644 index 000000000..3cf008ce6 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/atmel_lcdfb.c @@ -0,0 +1,138 @@ +/* + * Driver for AT91/AT32 LCD Controller + * + * Copyright (C) 2007 Atmel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/gpio.h> +#include <asm/arch/clk.h> +#include <lcd.h> +#include <atmel_lcdc.h> + +/* configurable parameters */ +#define ATMEL_LCDC_CVAL_DEFAULT 0xc8 +#define ATMEL_LCDC_DMA_BURST_LEN 8 +#ifndef ATMEL_LCDC_GUARD_TIME +#define ATMEL_LCDC_GUARD_TIME 1 +#endif + +#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91CAP9) +#define ATMEL_LCDC_FIFO_SIZE 2048 +#else +#define ATMEL_LCDC_FIFO_SIZE 512 +#endif + +#define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg)) +#define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg)) + +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ +#if defined(CONFIG_ATMEL_LCD_BGR555) + lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno), + (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7)); +#else + lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno), + (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8)); +#endif +} + +void lcd_ctrl_init(void *lcdbase) +{ + unsigned long value; + + /* Turn off the LCD controller and the DMA controller */ + lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON, + ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET); + + /* Wait for the LCDC core to become idle */ + while (lcdc_readl(panel_info.mmio, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY) + udelay(10); + + lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, 0); + + /* Reset LCDC DMA */ + lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST); + + /* ...set frame size and burst length = 8 words (?) */ + value = (panel_info.vl_col * panel_info.vl_row * + NBITS(panel_info.vl_bpix)) / 32; + value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET); + lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMAFRMCFG, value); + + /* Set pixel clock */ + value = get_lcdc_clk_rate(0) / panel_info.vl_clk; + if (get_lcdc_clk_rate(0) % panel_info.vl_clk) + value++; + value = (value / 2) - 1; + + if (!value) { + lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS); + } else + lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1, + value << ATMEL_LCDC_CLKVAL_OFFSET); + + /* Initialize control register 2 */ +#ifdef CONFIG_AVR32 + value = ATMEL_LCDC_MEMOR_BIG | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE; +#else + value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE; +#endif + if (panel_info.vl_tft) + value |= ATMEL_LCDC_DISTYPE_TFT; + + value |= panel_info.vl_sync; + value |= (panel_info.vl_bpix << 5); + lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON2, value); + + /* Vertical timing */ + value = (panel_info.vl_vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET; + value |= panel_info.vl_upper_margin << ATMEL_LCDC_VBP_OFFSET; + value |= panel_info.vl_lower_margin; + lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM1, value); + + /* Horizontal timing */ + value = (panel_info.vl_right_margin - 1) << ATMEL_LCDC_HFP_OFFSET; + value |= (panel_info.vl_hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET; + value |= (panel_info.vl_left_margin - 1); + lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM2, value); + + /* Display size */ + value = (panel_info.vl_col - 1) << ATMEL_LCDC_HOZVAL_OFFSET; + value |= panel_info.vl_row - 1; + lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDFRMCFG, value); + + /* FIFO Threshold: Use formula from data sheet */ + value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3); + lcdc_writel(panel_info.mmio, ATMEL_LCDC_FIFO, value); + + /* Toggle LCD_MODE every frame */ + lcdc_writel(panel_info.mmio, ATMEL_LCDC_MVAL, 0); + + /* Disable all interrupts */ + lcdc_writel(panel_info.mmio, ATMEL_LCDC_IDR, ~0UL); + + /* Set contrast */ + value = ATMEL_LCDC_PS_DIV8 | + ATMEL_LCDC_ENA_PWMENABLE; + if (!panel_info.vl_cont_pol_low) + value |= ATMEL_LCDC_POL_POSITIVE; + lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_CTR, value); + lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT); + + /* Set framebuffer DMA base address and pixel offset */ + lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMABADDR1, (u_long)lcdbase); + + lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN); + lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON, + (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR); +} + +ulong calc_fbsize(void) +{ + return ((panel_info.vl_col * panel_info.vl_row * + NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE; +} diff --git a/qemu/roms/u-boot/drivers/video/bcm2835.c b/qemu/roms/u-boot/drivers/video/bcm2835.c new file mode 100644 index 000000000..1f18231ac --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/bcm2835.c @@ -0,0 +1,116 @@ +/* + * (C) Copyright 2012 Stephen Warren + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <lcd.h> +#include <asm/arch/mbox.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Global variables that lcd.c expects to exist */ +vidinfo_t panel_info; + +static u32 bcm2835_pitch; + +struct msg_query { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_physical_w_h physical_w_h; + u32 end_tag; +}; + +struct msg_setup { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_physical_w_h physical_w_h; + struct bcm2835_mbox_tag_virtual_w_h virtual_w_h; + struct bcm2835_mbox_tag_depth depth; + struct bcm2835_mbox_tag_pixel_order pixel_order; + struct bcm2835_mbox_tag_alpha_mode alpha_mode; + struct bcm2835_mbox_tag_virtual_offset virtual_offset; + struct bcm2835_mbox_tag_overscan overscan; + struct bcm2835_mbox_tag_allocate_buffer allocate_buffer; + struct bcm2835_mbox_tag_pitch pitch; + u32 end_tag; +}; + +void lcd_ctrl_init(void *lcdbase) +{ + ALLOC_ALIGN_BUFFER(struct msg_query, msg_query, 1, 16); + ALLOC_ALIGN_BUFFER(struct msg_setup, msg_setup, 1, 16); + int ret; + u32 w, h; + + debug("bcm2835: Query resolution...\n"); + + BCM2835_MBOX_INIT_HDR(msg_query); + BCM2835_MBOX_INIT_TAG_NO_REQ(&msg_query->physical_w_h, + GET_PHYSICAL_W_H); + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg_query->hdr); + if (ret) { + printf("bcm2835: Could not query display resolution\n"); + /* FIXME: How to disable the LCD to prevent errors? hang()? */ + return; + } + + w = msg_query->physical_w_h.body.resp.width; + h = msg_query->physical_w_h.body.resp.height; + + debug("bcm2835: Setting up display for %d x %d\n", w, h); + + BCM2835_MBOX_INIT_HDR(msg_setup); + BCM2835_MBOX_INIT_TAG(&msg_setup->physical_w_h, SET_PHYSICAL_W_H); + msg_setup->physical_w_h.body.req.width = w; + msg_setup->physical_w_h.body.req.height = h; + BCM2835_MBOX_INIT_TAG(&msg_setup->virtual_w_h, SET_VIRTUAL_W_H); + msg_setup->virtual_w_h.body.req.width = w; + msg_setup->virtual_w_h.body.req.height = h; + BCM2835_MBOX_INIT_TAG(&msg_setup->depth, SET_DEPTH); + msg_setup->depth.body.req.bpp = 16; + BCM2835_MBOX_INIT_TAG(&msg_setup->pixel_order, SET_PIXEL_ORDER); + msg_setup->pixel_order.body.req.order = BCM2835_MBOX_PIXEL_ORDER_BGR; + BCM2835_MBOX_INIT_TAG(&msg_setup->alpha_mode, SET_ALPHA_MODE); + msg_setup->alpha_mode.body.req.alpha = BCM2835_MBOX_ALPHA_MODE_IGNORED; + BCM2835_MBOX_INIT_TAG(&msg_setup->virtual_offset, SET_VIRTUAL_OFFSET); + msg_setup->virtual_offset.body.req.x = 0; + msg_setup->virtual_offset.body.req.y = 0; + BCM2835_MBOX_INIT_TAG(&msg_setup->overscan, SET_OVERSCAN); + msg_setup->overscan.body.req.top = 0; + msg_setup->overscan.body.req.bottom = 0; + msg_setup->overscan.body.req.left = 0; + msg_setup->overscan.body.req.right = 0; + BCM2835_MBOX_INIT_TAG(&msg_setup->allocate_buffer, ALLOCATE_BUFFER); + msg_setup->allocate_buffer.body.req.alignment = 0x100; + BCM2835_MBOX_INIT_TAG_NO_REQ(&msg_setup->pitch, GET_PITCH); + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg_setup->hdr); + if (ret) { + printf("bcm2835: Could not configure display\n"); + /* FIXME: How to disable the LCD to prevent errors? hang()? */ + return; + } + + w = msg_setup->physical_w_h.body.resp.width; + h = msg_setup->physical_w_h.body.resp.height; + bcm2835_pitch = msg_setup->pitch.body.resp.pitch; + + debug("bcm2835: Final resolution is %d x %d\n", w, h); + + panel_info.vl_col = w; + panel_info.vl_row = h; + panel_info.vl_bpix = LCD_COLOR16; + + gd->fb_base = msg_setup->allocate_buffer.body.resp.fb_address; +} + +void lcd_enable(void) +{ +} + +int lcd_get_size(int *line_length) +{ + *line_length = bcm2835_pitch; + return *line_length * panel_info.vl_row; +} diff --git a/qemu/roms/u-boot/drivers/video/bus_vcxk.c b/qemu/roms/u-boot/drivers/video/bus_vcxk.c new file mode 100644 index 000000000..60a5cc5b7 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/bus_vcxk.c @@ -0,0 +1,426 @@ +/* + * (C) Copyright 2005-2009 + * Jens Scharsig @ BuS Elektronik GmbH & Co. KG, <esw@bus-elektronik.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <bmp_layout.h> +#include <asm/io.h> + +vu_char *vcxk_bws = ((vu_char *) (CONFIG_SYS_VCXK_BASE)); +vu_short *vcxk_bws_word = ((vu_short *)(CONFIG_SYS_VCXK_BASE)); +vu_long *vcxk_bws_long = ((vu_long *) (CONFIG_SYS_VCXK_BASE)); + +#ifdef CONFIG_AT91RM9200 + #include <asm/arch/hardware.h> + #include <asm/arch/at91_pio.h> + + #ifndef VCBITMASK + #define VCBITMASK(bitno) (0x0001 << (bitno % 16)) + #endif +at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; +#define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ + do { \ + writel(PIN, &pio->PORT.per); \ + writel(PIN, &pio->PORT.DDR); \ + writel(PIN, &pio->PORT.mddr); \ + if (!I0O1) \ + writel(PIN, &pio->PORT.puer); \ + } while (0); + +#define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); +#define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); + +#define VCXK_ACKNOWLEDGE \ + (!(readl(&pio->CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT.pdsr) & \ + CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN)) +#elif defined(CONFIG_MCF52x2) + #include <asm/m5282.h> + #ifndef VCBITMASK + #define VCBITMASK(bitno) (0x8000 >> (bitno % 16)) + #endif + + #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ + if (I0O1) DDR |= PIN; else DDR &= ~PIN; + + #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; + #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; + + #define VCXK_ACKNOWLEDGE \ + (!(CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT & \ + CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN)) + +#else + #error no vcxk support for selected ARCH +#endif + +#define VCXK_DISABLE\ + VCXK_SET_PIN(CONFIG_SYS_VCXK_ENABLE_PORT, CONFIG_SYS_VCXK_ENABLE_PIN) +#define VCXK_ENABLE\ + VCXK_CLR_PIN(CONFIG_SYS_VCXK_ENABLE_PORT, CONFIG_SYS_VCXK_ENABLE_PIN) + +#ifndef CONFIG_SYS_VCXK_DOUBLEBUFFERED + #define VCXK_BWS(x, data) vcxk_bws[x] = data; + #define VCXK_BWS_WORD_SET(x, mask) vcxk_bws_word[x] |= mask; + #define VCXK_BWS_WORD_CLEAR(x, mask) vcxk_bws_word[x] &= ~mask; + #define VCXK_BWS_LONG(x, data) vcxk_bws_long[x] = data; +#else + u_char double_bws[16384]; + u_short *double_bws_word; + u_long *double_bws_long; + #define VCXK_BWS(x,data) \ + double_bws[x] = data; vcxk_bws[x] = data; + #define VCXK_BWS_WORD_SET(x,mask) \ + double_bws_word[x] |= mask; \ + vcxk_bws_word[x] = double_bws_word[x]; + #define VCXK_BWS_WORD_CLEAR(x,mask) \ + double_bws_word[x] &= ~mask; \ + vcxk_bws_word[x] = double_bws_word[x]; + #define VCXK_BWS_LONG(x,data) \ + double_bws_long[x] = data; vcxk_bws_long[x] = data; +#endif + +#define VC4K16_Bright1 vcxk_bws_word[0x20004 / 2] +#define VC4K16_Bright2 vcxk_bws_word[0x20006 / 2] +#define VC2K_Bright vcxk_bws[0x8000] +#define VC8K_BrightH vcxk_bws[0xC000] +#define VC8K_BrightL vcxk_bws[0xC001] + +vu_char VC4K16; + +u_long display_width; +u_long display_height; +u_long display_bwidth; + +ulong search_vcxk_driver(void); +void vcxk_cls(void); +void vcxk_setbrightness(unsigned int side, short brightness); +int vcxk_request(void); +int vcxk_acknowledge_wait(void); +void vcxk_clear(void); + +/* + ****f* bus_vcxk/vcxk_init + * FUNCTION + * initialalize Video Controller + * PARAMETERS + * width visible display width in pixel + * height visible display height in pixel + *** + */ + +int vcxk_init(unsigned long width, unsigned long height) +{ +#ifdef CONFIG_SYS_VCXK_RESET_PORT + VCXK_INIT_PIN(CONFIG_SYS_VCXK_RESET_PORT, + CONFIG_SYS_VCXK_RESET_PIN, CONFIG_SYS_VCXK_RESET_DDR, 1) + VCXK_SET_PIN(CONFIG_SYS_VCXK_RESET_PORT, CONFIG_SYS_VCXK_RESET_PIN); +#endif + +#ifdef CONFIG_SYS_VCXK_DOUBLEBUFFERED + double_bws_word = (u_short *)double_bws; + double_bws_long = (u_long *)double_bws; + debug("%px %px %px\n", double_bws, double_bws_word, double_bws_long); +#endif + display_width = width; + display_height = height; +#if (CONFIG_SYS_VCXK_DEFAULT_LINEALIGN == 4) + display_bwidth = ((width + 31) / 8) & ~0x3; +#elif (CONFIG_SYS_VCXK_DEFAULT_LINEALIGN == 2) + display_bwidth = ((width + 15) / 8) & ~0x1; +#else + #error CONFIG_SYS_VCXK_DEFAULT_LINEALIGN is invalid +#endif + debug("linesize ((%ld + 15) / 8 & ~0x1) = %ld\n", + display_width, display_bwidth); + +#ifdef CONFIG_SYS_VCXK_AUTODETECT + VC4K16 = 0; + vcxk_bws_long[1] = 0x0; + vcxk_bws_long[1] = 0x55AAAA55; + vcxk_bws_long[5] = 0x0; + if (vcxk_bws_long[1] == 0x55AAAA55) + VC4K16 = 1; +#else + VC4K16 = 1; + debug("No autodetect: use vc4k\n"); +#endif + + VCXK_INIT_PIN(CONFIG_SYS_VCXK_INVERT_PORT, + CONFIG_SYS_VCXK_INVERT_PIN, CONFIG_SYS_VCXK_INVERT_DDR, 1) + VCXK_SET_PIN(CONFIG_SYS_VCXK_INVERT_PORT, CONFIG_SYS_VCXK_INVERT_PIN) + + VCXK_SET_PIN(CONFIG_SYS_VCXK_REQUEST_PORT, CONFIG_SYS_VCXK_REQUEST_PIN); + VCXK_INIT_PIN(CONFIG_SYS_VCXK_REQUEST_PORT, + CONFIG_SYS_VCXK_REQUEST_PIN, CONFIG_SYS_VCXK_REQUEST_DDR, 1) + + VCXK_INIT_PIN(CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT, + CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN, + CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR, 0) + + VCXK_DISABLE; + VCXK_INIT_PIN(CONFIG_SYS_VCXK_ENABLE_PORT, + CONFIG_SYS_VCXK_ENABLE_PIN, CONFIG_SYS_VCXK_ENABLE_DDR, 1) + + vcxk_cls(); + vcxk_cls(); /* clear second/hidden page */ + + vcxk_setbrightness(3, 1000); + VCXK_ENABLE; + return 1; +} + +/* + ****f* bus_vcxk/vcxk_setpixel + * FUNCTION + * set the pixel[x,y] with the given color + * PARAMETER + * x pixel colum + * y pixel row + * color <0x40 off/black + * >0x40 on + *** + */ + +void vcxk_setpixel(int x, int y, unsigned long color) +{ + vu_short dataptr; + + if ((x < display_width) && (y < display_height)) { + dataptr = ((x / 16)) + (y * (display_bwidth >> 1)); + + color = ((color >> 16) & 0xFF) | + ((color >> 8) & 0xFF) | (color & 0xFF); + + if (color > 0x40) { + VCXK_BWS_WORD_SET(dataptr, VCBITMASK(x)); + } else { + VCXK_BWS_WORD_CLEAR(dataptr, VCBITMASK(x)); + } + } +} + +/* + ****f* bus_vcxk/vcxk_loadimage + * FUNCTION + * copies a binary image to display memory + *** + */ + +void vcxk_loadimage(ulong source) +{ + int cnt; + vcxk_acknowledge_wait(); + if (VC4K16) { + for (cnt = 0; cnt < (16384 / 4); cnt++) { + VCXK_BWS_LONG(cnt, (*(ulong *) source)); + source = source + 4; + } + } else { + for (cnt = 0; cnt < 16384; cnt++) { + VCXK_BWS_LONG(cnt*2, (*(vu_char *) source)); + source++; + } + } + vcxk_request(); +} + +/* + ****f* bus_vcxk/vcxk_cls + * FUNCTION + * clear the display + *** + */ + +void vcxk_cls(void) +{ + vcxk_acknowledge_wait(); + vcxk_clear(); + vcxk_request(); +} + +/* + ****f* bus_vcxk/vcxk_clear(void) + * FUNCTION + * clear the display memory + *** + */ + +void vcxk_clear(void) +{ + int cnt; + + for (cnt = 0; cnt < (16384 / 4); cnt++) { + VCXK_BWS_LONG(cnt, 0) + } +} + +/* + ****f* bus_vcxk/vcxk_setbrightness + * FUNCTION + * set the display brightness + * PARAMETER + * side 1 set front side brightness + * 2 set back side brightness + * 3 set brightness for both sides + * brightness 0..1000 + *** + */ + +void vcxk_setbrightness(unsigned int side, short brightness) +{ + if (VC4K16) { + if ((side == 0) || (side & 0x1)) + VC4K16_Bright1 = brightness + 23; + if ((side == 0) || (side & 0x2)) + VC4K16_Bright2 = brightness + 23; + } else { + VC2K_Bright = (brightness >> 4) + 2; + VC8K_BrightH = (brightness + 23) >> 8; + VC8K_BrightL = (brightness + 23) & 0xFF; + } +} + +/* + ****f* bus_vcxk/vcxk_request + * FUNCTION + * requests viewing of display memory + *** + */ + +int vcxk_request(void) +{ + VCXK_CLR_PIN(CONFIG_SYS_VCXK_REQUEST_PORT, + CONFIG_SYS_VCXK_REQUEST_PIN) + VCXK_SET_PIN(CONFIG_SYS_VCXK_REQUEST_PORT, + CONFIG_SYS_VCXK_REQUEST_PIN); + return 1; +} + +/* + ****f* bus_vcxk/vcxk_acknowledge_wait + * FUNCTION + * wait for acknowledge viewing requests + *** + */ + +int vcxk_acknowledge_wait(void) +{ + while (VCXK_ACKNOWLEDGE) + ; + return 1; +} + +/* + ****f* bus_vcxk/vcxk_draw_mono + * FUNCTION + * copies a monochrom bitmap (BMP-Format) from given memory + * PARAMETER + * dataptr pointer to bitmap + * x output bitmap @ columne + * y output bitmap @ row + *** + */ + +void vcxk_draw_mono(unsigned char *dataptr, unsigned long linewidth, + unsigned long cp_width, unsigned long cp_height) +{ + unsigned char *lineptr; + unsigned long xcnt, ycnt; + + for (ycnt = cp_height; ycnt > 0; ycnt--) { + lineptr = dataptr; + for (xcnt = 0; xcnt < cp_width; xcnt++) { + if ((*lineptr << (xcnt % 8)) & 0x80) + vcxk_setpixel(xcnt, ycnt - 1, 0xFFFFFF); + else + vcxk_setpixel(xcnt, ycnt-1, 0); + + if ((xcnt % 8) == 7) + lineptr++; + } /* endfor xcnt */ + dataptr = dataptr + linewidth; + } /* endfor ycnt */ +} + +/* + ****f* bus_vcxk/vcxk_display_bitmap + * FUNCTION + * copies a bitmap (BMP-Format) to the given position + * PARAMETER + * addr pointer to bitmap + * x output bitmap @ columne + * y output bitmap @ row + *** + */ + +int vcxk_display_bitmap(ulong addr, int x, int y) +{ + bmp_image_t *bmp; + unsigned long width; + unsigned long height; + unsigned long bpp; + + unsigned long lw; + + unsigned long c_width; + unsigned long c_height; + unsigned char *dataptr; + + bmp = (bmp_image_t *) addr; + if ((bmp->header.signature[0] == 'B') && + (bmp->header.signature[1] == 'M')) { + width = le32_to_cpu(bmp->header.width); + height = le32_to_cpu(bmp->header.height); + bpp = le16_to_cpu(bmp->header.bit_count); + + dataptr = (unsigned char *) bmp + + le32_to_cpu(bmp->header.data_offset); + + if (display_width < (width + x)) + c_width = display_width - x; + else + c_width = width; + if (display_height < (height + y)) + c_height = display_height - y; + else + c_height = height; + + lw = (((width + 7) / 8) + 3) & ~0x3; + + if (c_height < height) + dataptr = dataptr + lw * (height - c_height); + switch (bpp) { + case 1: + vcxk_draw_mono(dataptr, lw, c_width, c_height); + break; + default: + printf("Error: %ld bit per pixel " + "not supported by VCxK\n", bpp); + return 0; + } + } else { + printf("Error: no valid bmp at %lx\n", (ulong) bmp); + return 0; + } + return 1; +} + +/* + ****f* bus_vcxk/video_display_bitmap + *** + */ + +int video_display_bitmap(ulong addr, int x, int y) +{ + vcxk_acknowledge_wait(); + if (vcxk_display_bitmap(addr, x, y)) { + vcxk_request(); + return 0; + } + return 1; +} + +/* EOF */ diff --git a/qemu/roms/u-boot/drivers/video/cfb_console.c b/qemu/roms/u-boot/drivers/video/cfb_console.c new file mode 100644 index 000000000..b52e9edd2 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/cfb_console.c @@ -0,0 +1,2323 @@ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling <fgottschling@eltec.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * cfb_console.c + * + * Color Framebuffer Console driver for 8/15/16/24/32 bits per pixel. + * + * At the moment only the 8x16 font is tested and the font fore- and + * background color is limited to black/white/gray colors. The Linux + * logo can be placed in the upper left corner and additional board + * information strings (that normally goes to serial port) can be drawn. + * + * The console driver can use the standard PC keyboard interface (i8042) + * for character input. Character output goes to a memory mapped video + * framebuffer with little or big-endian organisation. + * With environment setting 'console=serial' the console i/o can be + * forced to serial port. + * + * The driver uses graphic specific defines/parameters/functions: + * + * (for SMI LynxE graphic chip) + * + * CONFIG_VIDEO_SMI_LYNXEM - use graphic driver for SMI 710,712,810 + * VIDEO_FB_LITTLE_ENDIAN - framebuffer organisation default: big endian + * VIDEO_HW_RECTFILL - graphic driver supports hardware rectangle fill + * VIDEO_HW_BITBLT - graphic driver supports hardware bit blt + * + * Console Parameters are set by graphic drivers global struct: + * + * VIDEO_VISIBLE_COLS - x resolution + * VIDEO_VISIBLE_ROWS - y resolution + * VIDEO_PIXEL_SIZE - storage size in byte per pixel + * VIDEO_DATA_FORMAT - graphical data format GDF + * VIDEO_FB_ADRS - start of video memory + * + * CONFIG_I8042_KBD - AT Keyboard driver for i8042 + * VIDEO_KBD_INIT_FCT - init function for keyboard + * VIDEO_TSTC_FCT - keyboard_tstc function + * VIDEO_GETC_FCT - keyboard_getc function + * + * CONFIG_CONSOLE_CURSOR - on/off drawing cursor is done with + * delay loop in VIDEO_TSTC_FCT (i8042) + * + * CONFIG_SYS_CONSOLE_BLINK_COUNT - value for delay loop - blink rate + * CONFIG_CONSOLE_TIME - display time/date in upper right + * corner, needs CONFIG_CMD_DATE and + * CONFIG_CONSOLE_CURSOR + * CONFIG_VIDEO_LOGO - display Linux Logo in upper left corner. + * Use CONFIG_SPLASH_SCREEN_ALIGN with + * environment variable "splashpos" to place + * the logo on other position. In this case + * no CONSOLE_EXTRA_INFO is possible. + * CONFIG_VIDEO_BMP_LOGO - use bmp_logo instead of linux_logo + * CONFIG_CONSOLE_EXTRA_INFO - display additional board information + * strings that normaly goes to serial + * port. This define requires a board + * specific function: + * video_drawstring (VIDEO_INFO_X, + * VIDEO_INFO_Y + i*VIDEO_FONT_HEIGHT, + * info); + * that fills a info buffer at i=row. + * s.a: board/eltec/bab7xx. + * CONFIG_VGA_AS_SINGLE_DEVICE - If set the framebuffer device will be + * initialized as an output only device. + * The Keyboard driver will not be + * set-up. This may be used, if you have + * no or more than one Keyboard devices + * (USB Keyboard, AT Keyboard). + * + * CONFIG_VIDEO_SW_CURSOR: - Draws a cursor after the last + * character. No blinking is provided. + * Uses the macros CURSOR_SET and + * CURSOR_OFF. + * + * CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability + * of the graphic chip. Uses the macro + * CURSOR_SET. ATTENTION: If booting an + * OS, the display driver must disable + * the hardware register of the graphic + * chip. Otherwise a blinking field is + * displayed. + */ + +#include <common.h> +#include <version.h> +#include <malloc.h> +#include <linux/compiler.h> + +/* + * Console device defines with SMI graphic + * Any other graphic must change this section + */ + +#ifdef CONFIG_VIDEO_SMI_LYNXEM + +#define VIDEO_FB_LITTLE_ENDIAN +#define VIDEO_HW_RECTFILL +#define VIDEO_HW_BITBLT +#endif + +/* + * Defines for the CT69000 driver + */ +#ifdef CONFIG_VIDEO_CT69000 + +#define VIDEO_FB_LITTLE_ENDIAN +#define VIDEO_HW_RECTFILL +#define VIDEO_HW_BITBLT +#endif + +/* + * Defines for the SED13806 driver + */ +#ifdef CONFIG_VIDEO_SED13806 + +#ifndef CONFIG_TOTAL5200 +#define VIDEO_FB_LITTLE_ENDIAN +#endif +#define VIDEO_HW_RECTFILL +#define VIDEO_HW_BITBLT +#endif + +/* + * Defines for the SED13806 driver + */ +#ifdef CONFIG_VIDEO_SM501 + +#ifdef CONFIG_HH405 +#define VIDEO_FB_LITTLE_ENDIAN +#endif +#endif + +#ifdef CONFIG_VIDEO_MXS +#define VIDEO_FB_16BPP_WORD_SWAP +#endif + +/* + * Defines for the MB862xx driver + */ +#ifdef CONFIG_VIDEO_MB862xx + +#ifdef CONFIG_VIDEO_CORALP +#define VIDEO_FB_LITTLE_ENDIAN +#endif +#ifdef CONFIG_VIDEO_MB862xx_ACCEL +#define VIDEO_HW_RECTFILL +#define VIDEO_HW_BITBLT +#endif +#endif + +/* + * Defines for the i.MX31 driver (mx3fb.c) + */ +#if defined(CONFIG_VIDEO_MX3) || defined(CONFIG_VIDEO_IPUV3) +#define VIDEO_FB_16BPP_WORD_SWAP +#endif + +/* + * Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc. + */ +#include <video_fb.h> + +#include <splash.h> + +/* + * some Macros + */ +#define VIDEO_VISIBLE_COLS (pGD->winSizeX) +#define VIDEO_VISIBLE_ROWS (pGD->winSizeY) +#define VIDEO_PIXEL_SIZE (pGD->gdfBytesPP) +#define VIDEO_DATA_FORMAT (pGD->gdfIndex) +#define VIDEO_FB_ADRS (pGD->frameAdrs) + +/* + * Console device defines with i8042 keyboard controller + * Any other keyboard controller must change this section + */ + +#ifdef CONFIG_I8042_KBD +#include <i8042.h> + +#define VIDEO_KBD_INIT_FCT i8042_kbd_init() +#define VIDEO_TSTC_FCT i8042_tstc +#define VIDEO_GETC_FCT i8042_getc +#endif + +/* + * Console device + */ + +#include <version.h> +#include <linux/types.h> +#include <stdio_dev.h> +#include <video_font.h> + +#if defined(CONFIG_CMD_DATE) +#include <rtc.h> +#endif + +#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) +#include <watchdog.h> +#include <bmp_layout.h> +#include <splash.h> +#endif + +/* + * Cursor definition: + * CONFIG_CONSOLE_CURSOR: Uses a timer function (see drivers/input/i8042.c) + * to let the cursor blink. Uses the macros + * CURSOR_OFF and CURSOR_ON. + * CONFIG_VIDEO_SW_CURSOR: Draws a cursor after the last character. No + * blinking is provided. Uses the macros CURSOR_SET + * and CURSOR_OFF. + * CONFIG_VIDEO_HW_CURSOR: Uses the hardware cursor capability of the + * graphic chip. Uses the macro CURSOR_SET. + * ATTENTION: If booting an OS, the display driver + * must disable the hardware register of the graphic + * chip. Otherwise a blinking field is displayed + */ +#if !defined(CONFIG_CONSOLE_CURSOR) && \ + !defined(CONFIG_VIDEO_SW_CURSOR) && \ + !defined(CONFIG_VIDEO_HW_CURSOR) +/* no Cursor defined */ +#define CURSOR_ON +#define CURSOR_OFF +#define CURSOR_SET +#endif + +#if defined(CONFIG_CONSOLE_CURSOR) || defined(CONFIG_VIDEO_SW_CURSOR) +#if defined(CURSOR_ON) || \ + (defined(CONFIG_CONSOLE_CURSOR) && defined(CONFIG_VIDEO_SW_CURSOR)) +#error only one of CONFIG_CONSOLE_CURSOR, CONFIG_VIDEO_SW_CURSOR, \ + or CONFIG_VIDEO_HW_CURSOR can be defined +#endif +void console_cursor(int state); + +#define CURSOR_ON console_cursor(1) +#define CURSOR_OFF console_cursor(0) +#define CURSOR_SET video_set_cursor() +#endif /* CONFIG_CONSOLE_CURSOR || CONFIG_VIDEO_SW_CURSOR */ + +#ifdef CONFIG_CONSOLE_CURSOR +#ifndef CONFIG_CONSOLE_TIME +#error CONFIG_CONSOLE_CURSOR must be defined for CONFIG_CONSOLE_TIME +#endif +#ifndef CONFIG_I8042_KBD +#warning Cursor drawing on/off needs timer function s.a. drivers/input/i8042.c +#endif +#endif /* CONFIG_CONSOLE_CURSOR */ + + +#ifdef CONFIG_VIDEO_HW_CURSOR +#ifdef CURSOR_ON +#error only one of CONFIG_CONSOLE_CURSOR, CONFIG_VIDEO_SW_CURSOR, \ + or CONFIG_VIDEO_HW_CURSOR can be defined +#endif +#define CURSOR_ON +#define CURSOR_OFF +#define CURSOR_SET video_set_hw_cursor(console_col * VIDEO_FONT_WIDTH, \ + (console_row * VIDEO_FONT_HEIGHT) + video_logo_height) +#endif /* CONFIG_VIDEO_HW_CURSOR */ + +#ifdef CONFIG_VIDEO_LOGO +#ifdef CONFIG_VIDEO_BMP_LOGO +#include <bmp_logo.h> +#include <bmp_logo_data.h> +#define VIDEO_LOGO_WIDTH BMP_LOGO_WIDTH +#define VIDEO_LOGO_HEIGHT BMP_LOGO_HEIGHT +#define VIDEO_LOGO_LUT_OFFSET BMP_LOGO_OFFSET +#define VIDEO_LOGO_COLORS BMP_LOGO_COLORS + +#else /* CONFIG_VIDEO_BMP_LOGO */ +#define LINUX_LOGO_WIDTH 80 +#define LINUX_LOGO_HEIGHT 80 +#define LINUX_LOGO_COLORS 214 +#define LINUX_LOGO_LUT_OFFSET 0x20 +#define __initdata +#include <linux_logo.h> +#define VIDEO_LOGO_WIDTH LINUX_LOGO_WIDTH +#define VIDEO_LOGO_HEIGHT LINUX_LOGO_HEIGHT +#define VIDEO_LOGO_LUT_OFFSET LINUX_LOGO_LUT_OFFSET +#define VIDEO_LOGO_COLORS LINUX_LOGO_COLORS +#endif /* CONFIG_VIDEO_BMP_LOGO */ +#define VIDEO_INFO_X (VIDEO_LOGO_WIDTH) +#define VIDEO_INFO_Y (VIDEO_FONT_HEIGHT/2) +#else /* CONFIG_VIDEO_LOGO */ +#define VIDEO_LOGO_WIDTH 0 +#define VIDEO_LOGO_HEIGHT 0 +#endif /* CONFIG_VIDEO_LOGO */ + +#define VIDEO_COLS VIDEO_VISIBLE_COLS +#define VIDEO_ROWS VIDEO_VISIBLE_ROWS +#define VIDEO_SIZE (VIDEO_ROWS*VIDEO_COLS*VIDEO_PIXEL_SIZE) +#define VIDEO_PIX_BLOCKS (VIDEO_SIZE >> 2) +#define VIDEO_LINE_LEN (VIDEO_COLS*VIDEO_PIXEL_SIZE) +#define VIDEO_BURST_LEN (VIDEO_COLS/8) + +#ifdef CONFIG_VIDEO_LOGO +#define CONSOLE_ROWS ((VIDEO_ROWS - video_logo_height) / VIDEO_FONT_HEIGHT) +#else +#define CONSOLE_ROWS (VIDEO_ROWS / VIDEO_FONT_HEIGHT) +#endif + +#define CONSOLE_COLS (VIDEO_COLS / VIDEO_FONT_WIDTH) +#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * VIDEO_LINE_LEN) +#define CONSOLE_ROW_FIRST (video_console_address) +#define CONSOLE_ROW_SECOND (video_console_address + CONSOLE_ROW_SIZE) +#define CONSOLE_ROW_LAST (video_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE) +#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS) +#define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE) + +/* Macros */ +#ifdef VIDEO_FB_LITTLE_ENDIAN +#define SWAP16(x) ((((x) & 0x00ff) << 8) | \ + ((x) >> 8) \ + ) +#define SWAP32(x) ((((x) & 0x000000ff) << 24) | \ + (((x) & 0x0000ff00) << 8) | \ + (((x) & 0x00ff0000) >> 8) | \ + (((x) & 0xff000000) >> 24) \ + ) +#define SHORTSWAP32(x) ((((x) & 0x000000ff) << 8) | \ + (((x) & 0x0000ff00) >> 8) | \ + (((x) & 0x00ff0000) << 8) | \ + (((x) & 0xff000000) >> 8) \ + ) +#else +#define SWAP16(x) (x) +#define SWAP32(x) (x) +#if defined(VIDEO_FB_16BPP_WORD_SWAP) +#define SHORTSWAP32(x) (((x) >> 16) | ((x) << 16)) +#else +#define SHORTSWAP32(x) (x) +#endif +#endif + +#ifdef CONFIG_CONSOLE_EXTRA_INFO +/* + * setup a board string: type, speed, etc. + * + * line_number: location to place info string beside logo + * info: buffer for info string + */ +extern void video_get_info_str(int line_number, char *info); +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* Locals */ +static GraphicDevice *pGD; /* Pointer to Graphic array */ + +static void *video_fb_address; /* frame buffer address */ +static void *video_console_address; /* console buffer start address */ + +static int video_logo_height = VIDEO_LOGO_HEIGHT; + +static int __maybe_unused cursor_state; +static int __maybe_unused old_col; +static int __maybe_unused old_row; + +static int console_col; /* cursor col */ +static int console_row; /* cursor row */ + +static u32 eorx, fgx, bgx; /* color pats */ + +static int cfb_do_flush_cache; + +#ifdef CONFIG_CFB_CONSOLE_ANSI +static char ansi_buf[10]; +static int ansi_buf_size; +static int ansi_colors_need_revert; +static int ansi_cursor_hidden; +#endif + +static const int video_font_draw_table8[] = { + 0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff, + 0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff, + 0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff, + 0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff +}; + +static const int video_font_draw_table15[] = { + 0x00000000, 0x00007fff, 0x7fff0000, 0x7fff7fff +}; + +static const int video_font_draw_table16[] = { + 0x00000000, 0x0000ffff, 0xffff0000, 0xffffffff +}; + +static const int video_font_draw_table24[16][3] = { + {0x00000000, 0x00000000, 0x00000000}, + {0x00000000, 0x00000000, 0x00ffffff}, + {0x00000000, 0x0000ffff, 0xff000000}, + {0x00000000, 0x0000ffff, 0xffffffff}, + {0x000000ff, 0xffff0000, 0x00000000}, + {0x000000ff, 0xffff0000, 0x00ffffff}, + {0x000000ff, 0xffffffff, 0xff000000}, + {0x000000ff, 0xffffffff, 0xffffffff}, + {0xffffff00, 0x00000000, 0x00000000}, + {0xffffff00, 0x00000000, 0x00ffffff}, + {0xffffff00, 0x0000ffff, 0xff000000}, + {0xffffff00, 0x0000ffff, 0xffffffff}, + {0xffffffff, 0xffff0000, 0x00000000}, + {0xffffffff, 0xffff0000, 0x00ffffff}, + {0xffffffff, 0xffffffff, 0xff000000}, + {0xffffffff, 0xffffffff, 0xffffffff} +}; + +static const int video_font_draw_table32[16][4] = { + {0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x00000000, 0x00000000, 0x00000000, 0x00ffffff}, + {0x00000000, 0x00000000, 0x00ffffff, 0x00000000}, + {0x00000000, 0x00000000, 0x00ffffff, 0x00ffffff}, + {0x00000000, 0x00ffffff, 0x00000000, 0x00000000}, + {0x00000000, 0x00ffffff, 0x00000000, 0x00ffffff}, + {0x00000000, 0x00ffffff, 0x00ffffff, 0x00000000}, + {0x00000000, 0x00ffffff, 0x00ffffff, 0x00ffffff}, + {0x00ffffff, 0x00000000, 0x00000000, 0x00000000}, + {0x00ffffff, 0x00000000, 0x00000000, 0x00ffffff}, + {0x00ffffff, 0x00000000, 0x00ffffff, 0x00000000}, + {0x00ffffff, 0x00000000, 0x00ffffff, 0x00ffffff}, + {0x00ffffff, 0x00ffffff, 0x00000000, 0x00000000}, + {0x00ffffff, 0x00ffffff, 0x00000000, 0x00ffffff}, + {0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00000000}, + {0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff} +}; + +/* + * Implement a weak default function for boards that optionally + * need to skip the cfb initialization. + */ +__weak int board_cfb_skip(void) +{ + /* As default, don't skip cfb init */ + return 0; +} + +static void video_drawchars(int xx, int yy, unsigned char *s, int count) +{ + u8 *cdat, *dest, *dest0; + int rows, offset, c; + + offset = yy * VIDEO_LINE_LEN + xx * VIDEO_PIXEL_SIZE; + dest0 = video_fb_address + offset; + + switch (VIDEO_DATA_FORMAT) { + case GDF__8BIT_INDEX: + case GDF__8BIT_332RGB: + while (count--) { + c = *s; + cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; + rows--; dest += VIDEO_LINE_LEN) { + u8 bits = *cdat++; + + ((u32 *) dest)[0] = + (video_font_draw_table8[bits >> 4] & + eorx) ^ bgx; + + if (VIDEO_FONT_WIDTH == 4) + continue; + + ((u32 *) dest)[1] = + (video_font_draw_table8[bits & 15] & + eorx) ^ bgx; + } + dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; + s++; + } + break; + + case GDF_15BIT_555RGB: + while (count--) { + c = *s; + cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; + rows--; dest += VIDEO_LINE_LEN) { + u8 bits = *cdat++; + + ((u32 *) dest)[0] = + SHORTSWAP32((video_font_draw_table15 + [bits >> 6] & eorx) ^ + bgx); + ((u32 *) dest)[1] = + SHORTSWAP32((video_font_draw_table15 + [bits >> 4 & 3] & eorx) ^ + bgx); + + if (VIDEO_FONT_WIDTH == 4) + continue; + + ((u32 *) dest)[2] = + SHORTSWAP32((video_font_draw_table15 + [bits >> 2 & 3] & eorx) ^ + bgx); + ((u32 *) dest)[3] = + SHORTSWAP32((video_font_draw_table15 + [bits & 3] & eorx) ^ + bgx); + } + dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; + s++; + } + break; + + case GDF_16BIT_565RGB: + while (count--) { + c = *s; + cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; + rows--; dest += VIDEO_LINE_LEN) { + u8 bits = *cdat++; + + ((u32 *) dest)[0] = + SHORTSWAP32((video_font_draw_table16 + [bits >> 6] & eorx) ^ + bgx); + ((u32 *) dest)[1] = + SHORTSWAP32((video_font_draw_table16 + [bits >> 4 & 3] & eorx) ^ + bgx); + + if (VIDEO_FONT_WIDTH == 4) + continue; + + ((u32 *) dest)[2] = + SHORTSWAP32((video_font_draw_table16 + [bits >> 2 & 3] & eorx) ^ + bgx); + ((u32 *) dest)[3] = + SHORTSWAP32((video_font_draw_table16 + [bits & 3] & eorx) ^ + bgx); + } + dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; + s++; + } + break; + + case GDF_32BIT_X888RGB: + while (count--) { + c = *s; + cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; + rows--; dest += VIDEO_LINE_LEN) { + u8 bits = *cdat++; + + ((u32 *) dest)[0] = + SWAP32((video_font_draw_table32 + [bits >> 4][0] & eorx) ^ bgx); + ((u32 *) dest)[1] = + SWAP32((video_font_draw_table32 + [bits >> 4][1] & eorx) ^ bgx); + ((u32 *) dest)[2] = + SWAP32((video_font_draw_table32 + [bits >> 4][2] & eorx) ^ bgx); + ((u32 *) dest)[3] = + SWAP32((video_font_draw_table32 + [bits >> 4][3] & eorx) ^ bgx); + + + if (VIDEO_FONT_WIDTH == 4) + continue; + + ((u32 *) dest)[4] = + SWAP32((video_font_draw_table32 + [bits & 15][0] & eorx) ^ bgx); + ((u32 *) dest)[5] = + SWAP32((video_font_draw_table32 + [bits & 15][1] & eorx) ^ bgx); + ((u32 *) dest)[6] = + SWAP32((video_font_draw_table32 + [bits & 15][2] & eorx) ^ bgx); + ((u32 *) dest)[7] = + SWAP32((video_font_draw_table32 + [bits & 15][3] & eorx) ^ bgx); + } + dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; + s++; + } + break; + + case GDF_24BIT_888RGB: + while (count--) { + c = *s; + cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; + rows--; dest += VIDEO_LINE_LEN) { + u8 bits = *cdat++; + + ((u32 *) dest)[0] = + (video_font_draw_table24[bits >> 4][0] + & eorx) ^ bgx; + ((u32 *) dest)[1] = + (video_font_draw_table24[bits >> 4][1] + & eorx) ^ bgx; + ((u32 *) dest)[2] = + (video_font_draw_table24[bits >> 4][2] + & eorx) ^ bgx; + + if (VIDEO_FONT_WIDTH == 4) + continue; + + ((u32 *) dest)[3] = + (video_font_draw_table24[bits & 15][0] + & eorx) ^ bgx; + ((u32 *) dest)[4] = + (video_font_draw_table24[bits & 15][1] + & eorx) ^ bgx; + ((u32 *) dest)[5] = + (video_font_draw_table24[bits & 15][2] + & eorx) ^ bgx; + } + dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; + s++; + } + break; + } +} + +static inline void video_drawstring(int xx, int yy, unsigned char *s) +{ + video_drawchars(xx, yy, s, strlen((char *) s)); +} + +static void video_putchar(int xx, int yy, unsigned char c) +{ + video_drawchars(xx, yy + video_logo_height, &c, 1); +} + +#if defined(CONFIG_CONSOLE_CURSOR) || defined(CONFIG_VIDEO_SW_CURSOR) +static void video_set_cursor(void) +{ + if (cursor_state) + console_cursor(0); + console_cursor(1); +} + +static void video_invertchar(int xx, int yy) +{ + int firstx = xx * VIDEO_PIXEL_SIZE; + int lastx = (xx + VIDEO_FONT_WIDTH) * VIDEO_PIXEL_SIZE; + int firsty = yy * VIDEO_LINE_LEN; + int lasty = (yy + VIDEO_FONT_HEIGHT) * VIDEO_LINE_LEN; + int x, y; + for (y = firsty; y < lasty; y += VIDEO_LINE_LEN) { + for (x = firstx; x < lastx; x++) { + u8 *dest = (u8 *)(video_fb_address) + x + y; + *dest = ~*dest; + } + } +} + +void console_cursor(int state) +{ +#ifdef CONFIG_CONSOLE_TIME + struct rtc_time tm; + char info[16]; + + /* time update only if cursor is on (faster scroll) */ + if (state) { + rtc_get(&tm); + + sprintf(info, " %02d:%02d:%02d ", tm.tm_hour, tm.tm_min, + tm.tm_sec); + video_drawstring(VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH, + VIDEO_INFO_Y, (uchar *) info); + + sprintf(info, "%02d.%02d.%04d", tm.tm_mday, tm.tm_mon, + tm.tm_year); + video_drawstring(VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH, + VIDEO_INFO_Y + 1 * VIDEO_FONT_HEIGHT, + (uchar *) info); + } +#endif + + if (cursor_state != state) { + if (cursor_state) { + /* turn off the cursor */ + video_invertchar(old_col * VIDEO_FONT_WIDTH, + old_row * VIDEO_FONT_HEIGHT + + video_logo_height); + } else { + /* turn off the cursor and record where it is */ + video_invertchar(console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT + + video_logo_height); + old_col = console_col; + old_row = console_row; + } + cursor_state = state; + } + if (cfb_do_flush_cache) + flush_cache(VIDEO_FB_ADRS, VIDEO_SIZE); +} +#endif + +#ifndef VIDEO_HW_RECTFILL +static void memsetl(int *p, int c, int v) +{ + while (c--) + *(p++) = v; +} +#endif + +#ifndef VIDEO_HW_BITBLT +static void memcpyl(int *d, int *s, int c) +{ + while (c--) + *(d++) = *(s++); +} +#endif + +static void console_clear_line(int line, int begin, int end) +{ +#ifdef VIDEO_HW_RECTFILL + video_hw_rectfill(VIDEO_PIXEL_SIZE, /* bytes per pixel */ + VIDEO_FONT_WIDTH * begin, /* dest pos x */ + video_logo_height + + VIDEO_FONT_HEIGHT * line, /* dest pos y */ + VIDEO_FONT_WIDTH * (end - begin + 1), /* fr. width */ + VIDEO_FONT_HEIGHT, /* frame height */ + bgx /* fill color */ + ); +#else + if (begin == 0 && (end + 1) == CONSOLE_COLS) { + memsetl(CONSOLE_ROW_FIRST + + CONSOLE_ROW_SIZE * line, /* offset of row */ + CONSOLE_ROW_SIZE >> 2, /* length of row */ + bgx /* fill color */ + ); + } else { + void *offset; + int i, size; + + offset = CONSOLE_ROW_FIRST + + CONSOLE_ROW_SIZE * line + /* offset of row */ + VIDEO_FONT_WIDTH * + VIDEO_PIXEL_SIZE * begin; /* offset of col */ + size = VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE * (end - begin + 1); + size >>= 2; /* length to end for memsetl() */ + /* fill at col offset of i'th line using bgx as fill color */ + for (i = 0; i < VIDEO_FONT_HEIGHT; i++) + memsetl(offset + i * VIDEO_LINE_LEN, size, bgx); + } +#endif +} + +static void console_scrollup(void) +{ + /* copy up rows ignoring the first one */ + +#ifdef VIDEO_HW_BITBLT + video_hw_bitblt(VIDEO_PIXEL_SIZE, /* bytes per pixel */ + 0, /* source pos x */ + video_logo_height + + VIDEO_FONT_HEIGHT, /* source pos y */ + 0, /* dest pos x */ + video_logo_height, /* dest pos y */ + VIDEO_VISIBLE_COLS, /* frame width */ + VIDEO_VISIBLE_ROWS + - video_logo_height + - VIDEO_FONT_HEIGHT /* frame height */ + ); +#else + memcpyl(CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, + CONSOLE_SCROLL_SIZE >> 2); +#endif + /* clear the last one */ + console_clear_line(CONSOLE_ROWS - 1, 0, CONSOLE_COLS - 1); +} + +static void console_back(void) +{ + console_col--; + + if (console_col < 0) { + console_col = CONSOLE_COLS - 1; + console_row--; + if (console_row < 0) + console_row = 0; + } +} + +#ifdef CONFIG_CFB_CONSOLE_ANSI + +static void console_clear(void) +{ +#ifdef VIDEO_HW_RECTFILL + video_hw_rectfill(VIDEO_PIXEL_SIZE, /* bytes per pixel */ + 0, /* dest pos x */ + video_logo_height, /* dest pos y */ + VIDEO_VISIBLE_COLS, /* frame width */ + VIDEO_VISIBLE_ROWS, /* frame height */ + bgx /* fill color */ + ); +#else + memsetl(CONSOLE_ROW_FIRST, CONSOLE_SIZE, bgx); +#endif +} + +static void console_cursor_fix(void) +{ + if (console_row < 0) + console_row = 0; + if (console_row >= CONSOLE_ROWS) + console_row = CONSOLE_ROWS - 1; + if (console_col < 0) + console_col = 0; + if (console_col >= CONSOLE_COLS) + console_col = CONSOLE_COLS - 1; +} + +static void console_cursor_up(int n) +{ + console_row -= n; + console_cursor_fix(); +} + +static void console_cursor_down(int n) +{ + console_row += n; + console_cursor_fix(); +} + +static void console_cursor_left(int n) +{ + console_col -= n; + console_cursor_fix(); +} + +static void console_cursor_right(int n) +{ + console_col += n; + console_cursor_fix(); +} + +static void console_cursor_set_position(int row, int col) +{ + if (console_row != -1) + console_row = row; + if (console_col != -1) + console_col = col; + console_cursor_fix(); +} + +static void console_previousline(int n) +{ + /* FIXME: also scroll terminal ? */ + console_row -= n; + console_cursor_fix(); +} + +static void console_swap_colors(void) +{ + eorx = fgx; + fgx = bgx; + bgx = eorx; + eorx = fgx ^ bgx; +} + +static inline int console_cursor_is_visible(void) +{ + return !ansi_cursor_hidden; +} +#else +static inline int console_cursor_is_visible(void) +{ + return 1; +} +#endif + +static void console_newline(int n) +{ + console_row += n; + console_col = 0; + + /* Check if we need to scroll the terminal */ + if (console_row >= CONSOLE_ROWS) { + /* Scroll everything up */ + console_scrollup(); + + /* Decrement row number */ + console_row = CONSOLE_ROWS - 1; + } +} + +static void console_cr(void) +{ + console_col = 0; +} + +static void parse_putc(const char c) +{ + static int nl = 1; + + if (console_cursor_is_visible()) + CURSOR_OFF; + + switch (c) { + case 13: /* back to first column */ + console_cr(); + break; + + case '\n': /* next line */ + if (console_col || (!console_col && nl)) + console_newline(1); + nl = 1; + break; + + case 9: /* tab 8 */ + console_col |= 0x0008; + console_col &= ~0x0007; + + if (console_col >= CONSOLE_COLS) + console_newline(1); + break; + + case 8: /* backspace */ + console_back(); + break; + + case 7: /* bell */ + break; /* ignored */ + + default: /* draw the char */ + video_putchar(console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, c); + console_col++; + + /* check for newline */ + if (console_col >= CONSOLE_COLS) { + console_newline(1); + nl = 0; + } + } + + if (console_cursor_is_visible()) + CURSOR_SET; +} + +void video_putc(const char c) +{ +#ifdef CONFIG_CFB_CONSOLE_ANSI + int i; + + if (c == 27) { + for (i = 0; i < ansi_buf_size; ++i) + parse_putc(ansi_buf[i]); + ansi_buf[0] = 27; + ansi_buf_size = 1; + return; + } + + if (ansi_buf_size > 0) { + /* + * 0 - ESC + * 1 - [ + * 2 - num1 + * 3 - .. + * 4 - ; + * 5 - num2 + * 6 - .. + * - cchar + */ + int next = 0; + + int flush = 0; + int fail = 0; + + int num1 = 0; + int num2 = 0; + int cchar = 0; + + ansi_buf[ansi_buf_size++] = c; + + if (ansi_buf_size >= sizeof(ansi_buf)) + fail = 1; + + for (i = 0; i < ansi_buf_size; ++i) { + if (fail) + break; + + switch (next) { + case 0: + if (ansi_buf[i] == 27) + next = 1; + else + fail = 1; + break; + + case 1: + if (ansi_buf[i] == '[') + next = 2; + else + fail = 1; + break; + + case 2: + if (ansi_buf[i] >= '0' && ansi_buf[i] <= '9') { + num1 = ansi_buf[i]-'0'; + next = 3; + } else if (ansi_buf[i] != '?') { + --i; + num1 = 1; + next = 4; + } + break; + + case 3: + if (ansi_buf[i] >= '0' && ansi_buf[i] <= '9') { + num1 *= 10; + num1 += ansi_buf[i]-'0'; + } else { + --i; + next = 4; + } + break; + + case 4: + if (ansi_buf[i] != ';') { + --i; + next = 7; + } else + next = 5; + break; + + case 5: + if (ansi_buf[i] >= '0' && ansi_buf[i] <= '9') { + num2 = ansi_buf[i]-'0'; + next = 6; + } else + fail = 1; + break; + + case 6: + if (ansi_buf[i] >= '0' && ansi_buf[i] <= '9') { + num2 *= 10; + num2 += ansi_buf[i]-'0'; + } else { + --i; + next = 7; + } + break; + + case 7: + if ((ansi_buf[i] >= 'A' && ansi_buf[i] <= 'H') + || ansi_buf[i] == 'J' + || ansi_buf[i] == 'K' + || ansi_buf[i] == 'h' + || ansi_buf[i] == 'l' + || ansi_buf[i] == 'm') { + cchar = ansi_buf[i]; + flush = 1; + } else + fail = 1; + break; + } + } + + if (fail) { + for (i = 0; i < ansi_buf_size; ++i) + parse_putc(ansi_buf[i]); + ansi_buf_size = 0; + return; + } + + if (flush) { + if (!ansi_cursor_hidden) + CURSOR_OFF; + ansi_buf_size = 0; + switch (cchar) { + case 'A': + /* move cursor num1 rows up */ + console_cursor_up(num1); + break; + case 'B': + /* move cursor num1 rows down */ + console_cursor_down(num1); + break; + case 'C': + /* move cursor num1 columns forward */ + console_cursor_right(num1); + break; + case 'D': + /* move cursor num1 columns back */ + console_cursor_left(num1); + break; + case 'E': + /* move cursor num1 rows up at begin of row */ + console_previousline(num1); + break; + case 'F': + /* move cursor num1 rows down at begin of row */ + console_newline(num1); + break; + case 'G': + /* move cursor to column num1 */ + console_cursor_set_position(-1, num1-1); + break; + case 'H': + /* move cursor to row num1, column num2 */ + console_cursor_set_position(num1-1, num2-1); + break; + case 'J': + /* clear console and move cursor to 0, 0 */ + console_clear(); + console_cursor_set_position(0, 0); + break; + case 'K': + /* clear line */ + if (num1 == 0) + console_clear_line(console_row, + console_col, + CONSOLE_COLS-1); + else if (num1 == 1) + console_clear_line(console_row, + 0, console_col); + else + console_clear_line(console_row, + 0, CONSOLE_COLS-1); + break; + case 'h': + ansi_cursor_hidden = 0; + break; + case 'l': + ansi_cursor_hidden = 1; + break; + case 'm': + if (num1 == 0) { /* reset swapped colors */ + if (ansi_colors_need_revert) { + console_swap_colors(); + ansi_colors_need_revert = 0; + } + } else if (num1 == 7) { /* once swap colors */ + if (!ansi_colors_need_revert) { + console_swap_colors(); + ansi_colors_need_revert = 1; + } + } + break; + } + if (!ansi_cursor_hidden) + CURSOR_SET; + } + } else { + parse_putc(c); + } +#else + parse_putc(c); +#endif + if (cfb_do_flush_cache) + flush_cache(VIDEO_FB_ADRS, VIDEO_SIZE); +} + +void video_puts(const char *s) +{ + int count = strlen(s); + + while (count--) + video_putc(*s++); +} + +/* + * Do not enforce drivers (or board code) to provide empty + * video_set_lut() if they do not support 8 bpp format. + * Implement weak default function instead. + */ +void __video_set_lut(unsigned int index, unsigned char r, + unsigned char g, unsigned char b) +{ +} + +void video_set_lut(unsigned int, unsigned char, unsigned char, unsigned char) + __attribute__ ((weak, alias("__video_set_lut"))); + +#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) + +#define FILL_8BIT_332RGB(r,g,b) { \ + *fb = ((r>>5)<<5) | ((g>>5)<<2) | (b>>6); \ + fb ++; \ +} + +#define FILL_15BIT_555RGB(r,g,b) { \ + *(unsigned short *)fb = \ + SWAP16((unsigned short)(((r>>3)<<10) | \ + ((g>>3)<<5) | \ + (b>>3))); \ + fb += 2; \ +} + +#define FILL_16BIT_565RGB(r,g,b) { \ + *(unsigned short *)fb = \ + SWAP16((unsigned short)((((r)>>3)<<11)| \ + (((g)>>2)<<5) | \ + ((b)>>3))); \ + fb += 2; \ +} + +#define FILL_32BIT_X888RGB(r,g,b) { \ + *(unsigned long *)fb = \ + SWAP32((unsigned long)(((r<<16) | \ + (g<<8) | \ + b))); \ + fb += 4; \ +} + +#ifdef VIDEO_FB_LITTLE_ENDIAN +#define FILL_24BIT_888RGB(r,g,b) { \ + fb[0] = b; \ + fb[1] = g; \ + fb[2] = r; \ + fb += 3; \ +} +#else +#define FILL_24BIT_888RGB(r,g,b) { \ + fb[0] = r; \ + fb[1] = g; \ + fb[2] = b; \ + fb += 3; \ +} +#endif + +#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) +static inline void fill_555rgb_pswap(uchar *fb, int x, u8 r, u8 g, u8 b) +{ + ushort *dst = (ushort *) fb; + ushort color = (ushort) (((r >> 3) << 10) | + ((g >> 3) << 5) | + (b >> 3)); + if (x & 1) + *(--dst) = color; + else + *(++dst) = color; +} +#endif + +/* + * RLE8 bitmap support + */ + +#ifdef CONFIG_VIDEO_BMP_RLE8 +/* Pre-calculated color table entry */ +struct palette { + union { + unsigned short w; /* word */ + unsigned int dw; /* double word */ + } ce; /* color entry */ +}; + +/* + * Helper to draw encoded/unencoded run. + */ +static void draw_bitmap(uchar **fb, uchar *bm, struct palette *p, + int cnt, int enc) +{ + ulong addr = (ulong) *fb; + int *off; + int enc_off = 1; + int i; + + /* + * Setup offset of the color index in the bitmap. + * Color index of encoded run is at offset 1. + */ + off = enc ? &enc_off : &i; + + switch (VIDEO_DATA_FORMAT) { + case GDF__8BIT_INDEX: + for (i = 0; i < cnt; i++) + *(unsigned char *) addr++ = bm[*off]; + break; + case GDF_15BIT_555RGB: + case GDF_16BIT_565RGB: + /* differences handled while pre-calculating palette */ + for (i = 0; i < cnt; i++) { + *(unsigned short *) addr = p[bm[*off]].ce.w; + addr += 2; + } + break; + case GDF_32BIT_X888RGB: + for (i = 0; i < cnt; i++) { + *(unsigned long *) addr = p[bm[*off]].ce.dw; + addr += 4; + } + break; + } + *fb = (uchar *) addr; /* return modified address */ +} + +static int display_rle8_bitmap(bmp_image_t *img, int xoff, int yoff, + int width, int height) +{ + unsigned char *bm; + unsigned char *fbp; + unsigned int cnt, runlen; + int decode = 1; + int x, y, bpp, i, ncolors; + struct palette p[256]; + bmp_color_table_entry_t cte; + int green_shift, red_off; + int limit = VIDEO_COLS * VIDEO_ROWS; + int pixels = 0; + + x = 0; + y = __le32_to_cpu(img->header.height) - 1; + ncolors = __le32_to_cpu(img->header.colors_used); + bpp = VIDEO_PIXEL_SIZE; + fbp = (unsigned char *) ((unsigned int) video_fb_address + + (((y + yoff) * VIDEO_COLS) + xoff) * bpp); + + bm = (uchar *) img + __le32_to_cpu(img->header.data_offset); + + /* pre-calculate and setup palette */ + switch (VIDEO_DATA_FORMAT) { + case GDF__8BIT_INDEX: + for (i = 0; i < ncolors; i++) { + cte = img->color_table[i]; + video_set_lut(i, cte.red, cte.green, cte.blue); + } + break; + case GDF_15BIT_555RGB: + case GDF_16BIT_565RGB: + if (VIDEO_DATA_FORMAT == GDF_15BIT_555RGB) { + green_shift = 3; + red_off = 10; + } else { + green_shift = 2; + red_off = 11; + } + for (i = 0; i < ncolors; i++) { + cte = img->color_table[i]; + p[i].ce.w = SWAP16((unsigned short) + (((cte.red >> 3) << red_off) | + ((cte.green >> green_shift) << 5) | + cte.blue >> 3)); + } + break; + case GDF_32BIT_X888RGB: + for (i = 0; i < ncolors; i++) { + cte = img->color_table[i]; + p[i].ce.dw = SWAP32((cte.red << 16) | + (cte.green << 8) | + cte.blue); + } + break; + default: + printf("RLE Bitmap unsupported in video mode 0x%x\n", + VIDEO_DATA_FORMAT); + return -1; + } + + while (decode) { + switch (bm[0]) { + case 0: + switch (bm[1]) { + case 0: + /* scan line end marker */ + bm += 2; + x = 0; + y--; + fbp = (unsigned char *) + ((unsigned int) video_fb_address + + (((y + yoff) * VIDEO_COLS) + + xoff) * bpp); + continue; + case 1: + /* end of bitmap data marker */ + decode = 0; + break; + case 2: + /* run offset marker */ + x += bm[2]; + y -= bm[3]; + fbp = (unsigned char *) + ((unsigned int) video_fb_address + + (((y + yoff) * VIDEO_COLS) + + x + xoff) * bpp); + bm += 4; + break; + default: + /* unencoded run */ + cnt = bm[1]; + runlen = cnt; + pixels += cnt; + if (pixels > limit) + goto error; + + bm += 2; + if (y < height) { + if (x >= width) { + x += runlen; + goto next_run; + } + if (x + runlen > width) + cnt = width - x; + draw_bitmap(&fbp, bm, p, cnt, 0); + x += runlen; + } +next_run: + bm += runlen; + if (runlen & 1) + bm++; /* 0 padding if length is odd */ + } + break; + default: + /* encoded run */ + cnt = bm[0]; + runlen = cnt; + pixels += cnt; + if (pixels > limit) + goto error; + + if (y < height) { /* only draw into visible area */ + if (x >= width) { + x += runlen; + bm += 2; + continue; + } + if (x + runlen > width) + cnt = width - x; + draw_bitmap(&fbp, bm, p, cnt, 1); + x += runlen; + } + bm += 2; + break; + } + } + return 0; +error: + printf("Error: Too much encoded pixel data, validate your bitmap\n"); + return -1; +} +#endif + +/* + * Display the BMP file located at address bmp_image. + */ +int video_display_bitmap(ulong bmp_image, int x, int y) +{ + ushort xcount, ycount; + uchar *fb; + bmp_image_t *bmp = (bmp_image_t *) bmp_image; + uchar *bmap; + ushort padded_line; + unsigned long width, height, bpp; + unsigned colors; + unsigned long compression; + bmp_color_table_entry_t cte; + +#ifdef CONFIG_VIDEO_BMP_GZIP + unsigned char *dst = NULL; + ulong len; +#endif + + WATCHDOG_RESET(); + + if (!((bmp->header.signature[0] == 'B') && + (bmp->header.signature[1] == 'M'))) { + +#ifdef CONFIG_VIDEO_BMP_GZIP + /* + * Could be a gzipped bmp image, try to decrompress... + */ + len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE; + dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE); + if (dst == NULL) { + printf("Error: malloc in gunzip failed!\n"); + return 1; + } + /* + * NB: we need to force offset of +2 + * See doc/README.displaying-bmps + */ + if (gunzip(dst+2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE-2, + (uchar *) bmp_image, + &len) != 0) { + printf("Error: no valid bmp or bmp.gz image at %lx\n", + bmp_image); + free(dst); + return 1; + } + if (len == CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) { + printf("Image could be truncated " + "(increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n"); + } + + /* + * Set addr to decompressed image + */ + bmp = (bmp_image_t *)(dst+2); + + if (!((bmp->header.signature[0] == 'B') && + (bmp->header.signature[1] == 'M'))) { + printf("Error: no valid bmp.gz image at %lx\n", + bmp_image); + free(dst); + return 1; + } +#else + printf("Error: no valid bmp image at %lx\n", bmp_image); + return 1; +#endif /* CONFIG_VIDEO_BMP_GZIP */ + } + + width = le32_to_cpu(bmp->header.width); + height = le32_to_cpu(bmp->header.height); + bpp = le16_to_cpu(bmp->header.bit_count); + colors = le32_to_cpu(bmp->header.colors_used); + compression = le32_to_cpu(bmp->header.compression); + + debug("Display-bmp: %ld x %ld with %d colors\n", + width, height, colors); + + if (compression != BMP_BI_RGB +#ifdef CONFIG_VIDEO_BMP_RLE8 + && compression != BMP_BI_RLE8 +#endif + ) { + printf("Error: compression type %ld not supported\n", + compression); +#ifdef CONFIG_VIDEO_BMP_GZIP + if (dst) + free(dst); +#endif + return 1; + } + + padded_line = (((width * bpp + 7) / 8) + 3) & ~0x3; + +#ifdef CONFIG_SPLASH_SCREEN_ALIGN + if (x == BMP_ALIGN_CENTER) + x = max(0, (VIDEO_VISIBLE_COLS - width) / 2); + else if (x < 0) + x = max(0, VIDEO_VISIBLE_COLS - width + x + 1); + + if (y == BMP_ALIGN_CENTER) + y = max(0, (VIDEO_VISIBLE_ROWS - height) / 2); + else if (y < 0) + y = max(0, VIDEO_VISIBLE_ROWS - height + y + 1); +#endif /* CONFIG_SPLASH_SCREEN_ALIGN */ + + /* + * Just ignore elements which are completely beyond screen + * dimensions. + */ + if ((x >= VIDEO_VISIBLE_COLS) || (y >= VIDEO_VISIBLE_ROWS)) + return 0; + + if ((x + width) > VIDEO_VISIBLE_COLS) + width = VIDEO_VISIBLE_COLS - x; + if ((y + height) > VIDEO_VISIBLE_ROWS) + height = VIDEO_VISIBLE_ROWS - y; + + bmap = (uchar *) bmp + le32_to_cpu(bmp->header.data_offset); + fb = (uchar *) (video_fb_address + + ((y + height - 1) * VIDEO_COLS * VIDEO_PIXEL_SIZE) + + x * VIDEO_PIXEL_SIZE); + +#ifdef CONFIG_VIDEO_BMP_RLE8 + if (compression == BMP_BI_RLE8) { + return display_rle8_bitmap(bmp, x, y, width, height); + } +#endif + + /* We handle only 4, 8, or 24 bpp bitmaps */ + switch (le16_to_cpu(bmp->header.bit_count)) { + case 4: + padded_line -= width / 2; + ycount = height; + + switch (VIDEO_DATA_FORMAT) { + case GDF_32BIT_X888RGB: + while (ycount--) { + WATCHDOG_RESET(); + /* + * Don't assume that 'width' is an + * even number + */ + for (xcount = 0; xcount < width; xcount++) { + uchar idx; + + if (xcount & 1) { + idx = *bmap & 0xF; + bmap++; + } else + idx = *bmap >> 4; + cte = bmp->color_table[idx]; + FILL_32BIT_X888RGB(cte.red, cte.green, + cte.blue); + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; + } + break; + default: + puts("4bpp bitmap unsupported with current " + "video mode\n"); + break; + } + break; + + case 8: + padded_line -= width; + if (VIDEO_DATA_FORMAT == GDF__8BIT_INDEX) { + /* Copy colormap */ + for (xcount = 0; xcount < colors; ++xcount) { + cte = bmp->color_table[xcount]; + video_set_lut(xcount, cte.red, cte.green, + cte.blue); + } + } + ycount = height; + switch (VIDEO_DATA_FORMAT) { + case GDF__8BIT_INDEX: + while (ycount--) { + WATCHDOG_RESET(); + xcount = width; + while (xcount--) { + *fb++ = *bmap++; + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; + } + break; + case GDF__8BIT_332RGB: + while (ycount--) { + WATCHDOG_RESET(); + xcount = width; + while (xcount--) { + cte = bmp->color_table[*bmap++]; + FILL_8BIT_332RGB(cte.red, cte.green, + cte.blue); + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; + } + break; + case GDF_15BIT_555RGB: + while (ycount--) { +#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) + int xpos = x; +#endif + WATCHDOG_RESET(); + xcount = width; + while (xcount--) { + cte = bmp->color_table[*bmap++]; +#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) + fill_555rgb_pswap(fb, xpos++, cte.red, + cte.green, + cte.blue); + fb += 2; +#else + FILL_15BIT_555RGB(cte.red, cte.green, + cte.blue); +#endif + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; + } + break; + case GDF_16BIT_565RGB: + while (ycount--) { + WATCHDOG_RESET(); + xcount = width; + while (xcount--) { + cte = bmp->color_table[*bmap++]; + FILL_16BIT_565RGB(cte.red, cte.green, + cte.blue); + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; + } + break; + case GDF_32BIT_X888RGB: + while (ycount--) { + WATCHDOG_RESET(); + xcount = width; + while (xcount--) { + cte = bmp->color_table[*bmap++]; + FILL_32BIT_X888RGB(cte.red, cte.green, + cte.blue); + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; + } + break; + case GDF_24BIT_888RGB: + while (ycount--) { + WATCHDOG_RESET(); + xcount = width; + while (xcount--) { + cte = bmp->color_table[*bmap++]; + FILL_24BIT_888RGB(cte.red, cte.green, + cte.blue); + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; + } + break; + } + break; + case 24: + padded_line -= 3 * width; + ycount = height; + switch (VIDEO_DATA_FORMAT) { + case GDF__8BIT_332RGB: + while (ycount--) { + WATCHDOG_RESET(); + xcount = width; + while (xcount--) { + FILL_8BIT_332RGB(bmap[2], bmap[1], + bmap[0]); + bmap += 3; + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; + } + break; + case GDF_15BIT_555RGB: + while (ycount--) { +#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) + int xpos = x; +#endif + WATCHDOG_RESET(); + xcount = width; + while (xcount--) { +#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) + fill_555rgb_pswap(fb, xpos++, bmap[2], + bmap[1], bmap[0]); + fb += 2; +#else + FILL_15BIT_555RGB(bmap[2], bmap[1], + bmap[0]); +#endif + bmap += 3; + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; + } + break; + case GDF_16BIT_565RGB: + while (ycount--) { + WATCHDOG_RESET(); + xcount = width; + while (xcount--) { + FILL_16BIT_565RGB(bmap[2], bmap[1], + bmap[0]); + bmap += 3; + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; + } + break; + case GDF_32BIT_X888RGB: + while (ycount--) { + WATCHDOG_RESET(); + xcount = width; + while (xcount--) { + FILL_32BIT_X888RGB(bmap[2], bmap[1], + bmap[0]); + bmap += 3; + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; + } + break; + case GDF_24BIT_888RGB: + while (ycount--) { + WATCHDOG_RESET(); + xcount = width; + while (xcount--) { + FILL_24BIT_888RGB(bmap[2], bmap[1], + bmap[0]); + bmap += 3; + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; + } + break; + default: + printf("Error: 24 bits/pixel bitmap incompatible " + "with current video mode\n"); + break; + } + break; + default: + printf("Error: %d bit/pixel bitmaps not supported by U-Boot\n", + le16_to_cpu(bmp->header.bit_count)); + break; + } + +#ifdef CONFIG_VIDEO_BMP_GZIP + if (dst) { + free(dst); + } +#endif + + if (cfb_do_flush_cache) + flush_cache(VIDEO_FB_ADRS, VIDEO_SIZE); + return (0); +} +#endif + + +#ifdef CONFIG_VIDEO_LOGO +static int video_logo_xpos; +static int video_logo_ypos; + +static void plot_logo_or_black(void *screen, int width, int x, int y, \ + int black); + +static void logo_plot(void *screen, int width, int x, int y) +{ + plot_logo_or_black(screen, width, x, y, 0); +} + +static void logo_black(void) +{ + plot_logo_or_black(video_fb_address, \ + VIDEO_COLS, \ + video_logo_xpos, \ + video_logo_ypos, \ + 1); +} + +static int do_clrlogo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc != 1) + return cmd_usage(cmdtp); + + logo_black(); + return 0; +} + +U_BOOT_CMD( + clrlogo, 1, 0, do_clrlogo, + "fill the boot logo area with black", + " " + ); + +static void plot_logo_or_black(void *screen, int width, int x, int y, int black) +{ + + int xcount, i; + int skip = (width - VIDEO_LOGO_WIDTH) * VIDEO_PIXEL_SIZE; + int ycount = video_logo_height; + unsigned char r, g, b, *logo_red, *logo_blue, *logo_green; + unsigned char *source; + unsigned char *dest; + +#ifdef CONFIG_SPLASH_SCREEN_ALIGN + if (x == BMP_ALIGN_CENTER) + x = max(0, (VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH) / 2); + else if (x < 0) + x = max(0, VIDEO_VISIBLE_COLS - VIDEO_LOGO_WIDTH + x + 1); + + if (y == BMP_ALIGN_CENTER) + y = max(0, (VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT) / 2); + else if (y < 0) + y = max(0, VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT + y + 1); +#endif /* CONFIG_SPLASH_SCREEN_ALIGN */ + + dest = (unsigned char *)screen + (y * width + x) * VIDEO_PIXEL_SIZE; + +#ifdef CONFIG_VIDEO_BMP_LOGO + source = bmp_logo_bitmap; + + /* Allocate temporary space for computing colormap */ + logo_red = malloc(BMP_LOGO_COLORS); + logo_green = malloc(BMP_LOGO_COLORS); + logo_blue = malloc(BMP_LOGO_COLORS); + /* Compute color map */ + for (i = 0; i < VIDEO_LOGO_COLORS; i++) { + logo_red[i] = (bmp_logo_palette[i] & 0x0f00) >> 4; + logo_green[i] = (bmp_logo_palette[i] & 0x00f0); + logo_blue[i] = (bmp_logo_palette[i] & 0x000f) << 4; + } +#else + source = linux_logo; + logo_red = linux_logo_red; + logo_green = linux_logo_green; + logo_blue = linux_logo_blue; +#endif + + if (VIDEO_DATA_FORMAT == GDF__8BIT_INDEX) { + for (i = 0; i < VIDEO_LOGO_COLORS; i++) { + video_set_lut(i + VIDEO_LOGO_LUT_OFFSET, + logo_red[i], logo_green[i], + logo_blue[i]); + } + } + + while (ycount--) { +#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) + int xpos = x; +#endif + xcount = VIDEO_LOGO_WIDTH; + while (xcount--) { + if (black) { + r = 0x00; + g = 0x00; + b = 0x00; + } else { + r = logo_red[*source - VIDEO_LOGO_LUT_OFFSET]; + g = logo_green[*source - VIDEO_LOGO_LUT_OFFSET]; + b = logo_blue[*source - VIDEO_LOGO_LUT_OFFSET]; + } + + switch (VIDEO_DATA_FORMAT) { + case GDF__8BIT_INDEX: + *dest = *source; + break; + case GDF__8BIT_332RGB: + *dest = ((r >> 5) << 5) | + ((g >> 5) << 2) | + (b >> 6); + break; + case GDF_15BIT_555RGB: +#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) + fill_555rgb_pswap(dest, xpos++, r, g, b); +#else + *(unsigned short *) dest = + SWAP16((unsigned short) ( + ((r >> 3) << 10) | + ((g >> 3) << 5) | + (b >> 3))); +#endif + break; + case GDF_16BIT_565RGB: + *(unsigned short *) dest = + SWAP16((unsigned short) ( + ((r >> 3) << 11) | + ((g >> 2) << 5) | + (b >> 3))); + break; + case GDF_32BIT_X888RGB: + *(unsigned long *) dest = + SWAP32((unsigned long) ( + (r << 16) | + (g << 8) | + b)); + break; + case GDF_24BIT_888RGB: +#ifdef VIDEO_FB_LITTLE_ENDIAN + dest[0] = b; + dest[1] = g; + dest[2] = r; +#else + dest[0] = r; + dest[1] = g; + dest[2] = b; +#endif + break; + } + source++; + dest += VIDEO_PIXEL_SIZE; + } + dest += skip; + } +#ifdef CONFIG_VIDEO_BMP_LOGO + free(logo_red); + free(logo_green); + free(logo_blue); +#endif +} + +static void *video_logo(void) +{ + char info[128]; + int space, len; + __maybe_unused int y_off = 0; + __maybe_unused ulong addr; + __maybe_unused char *s; + + splash_get_pos(&video_logo_xpos, &video_logo_ypos); + +#ifdef CONFIG_SPLASH_SCREEN + s = getenv("splashimage"); + if (s != NULL) { + splash_screen_prepare(); + addr = simple_strtoul(s, NULL, 16); + + if (video_display_bitmap(addr, + video_logo_xpos, + video_logo_ypos) == 0) { + video_logo_height = 0; + return ((void *) (video_fb_address)); + } + } +#endif /* CONFIG_SPLASH_SCREEN */ + + logo_plot(video_fb_address, VIDEO_COLS, + video_logo_xpos, video_logo_ypos); + +#ifdef CONFIG_SPLASH_SCREEN_ALIGN + /* + * when using splashpos for video_logo, skip any info + * output on video console if the logo is not at 0,0 + */ + if (video_logo_xpos || video_logo_ypos) { + /* + * video_logo_height is used in text and cursor offset + * calculations. Since the console is below the logo, + * we need to adjust the logo height + */ + if (video_logo_ypos == BMP_ALIGN_CENTER) + video_logo_height += max(0, (VIDEO_VISIBLE_ROWS - \ + VIDEO_LOGO_HEIGHT) / 2); + else if (video_logo_ypos > 0) + video_logo_height += video_logo_ypos; + + return video_fb_address + video_logo_height * VIDEO_LINE_LEN; + } +#endif + if (board_cfb_skip()) + return 0; + + sprintf(info, " %s", version_string); + + space = (VIDEO_LINE_LEN / 2 - VIDEO_INFO_X) / VIDEO_FONT_WIDTH; + len = strlen(info); + + if (len > space) { + video_drawchars(VIDEO_INFO_X, VIDEO_INFO_Y, + (uchar *) info, space); + video_drawchars(VIDEO_INFO_X + VIDEO_FONT_WIDTH, + VIDEO_INFO_Y + VIDEO_FONT_HEIGHT, + (uchar *) info + space, len - space); + y_off = 1; + } else + video_drawstring(VIDEO_INFO_X, VIDEO_INFO_Y, (uchar *) info); + +#ifdef CONFIG_CONSOLE_EXTRA_INFO + { + int i, n = + ((video_logo_height - + VIDEO_FONT_HEIGHT) / VIDEO_FONT_HEIGHT); + + for (i = 1; i < n; i++) { + video_get_info_str(i, info); + if (!*info) + continue; + + len = strlen(info); + if (len > space) { + video_drawchars(VIDEO_INFO_X, + VIDEO_INFO_Y + + (i + y_off) * + VIDEO_FONT_HEIGHT, + (uchar *) info, space); + y_off++; + video_drawchars(VIDEO_INFO_X + + VIDEO_FONT_WIDTH, + VIDEO_INFO_Y + + (i + y_off) * + VIDEO_FONT_HEIGHT, + (uchar *) info + space, + len - space); + } else { + video_drawstring(VIDEO_INFO_X, + VIDEO_INFO_Y + + (i + y_off) * + VIDEO_FONT_HEIGHT, + (uchar *) info); + } + } + } +#endif + + return (video_fb_address + video_logo_height * VIDEO_LINE_LEN); +} +#endif + +static int cfb_fb_is_in_dram(void) +{ + bd_t *bd = gd->bd; +#if defined(CONFIG_ARM) || defined(CONFIG_AVR32) || defined(COFNIG_NDS32) || \ +defined(CONFIG_SANDBOX) || defined(CONFIG_X86) + ulong start, end; + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { + start = bd->bi_dram[i].start; + end = bd->bi_dram[i].start + bd->bi_dram[i].size - 1; + if ((ulong)video_fb_address >= start && + (ulong)video_fb_address < end) + return 1; + } +#else + if ((ulong)video_fb_address >= bd->bi_memstart && + (ulong)video_fb_address < bd->bi_memstart + bd->bi_memsize) + return 1; +#endif + return 0; +} + +void video_clear(void) +{ + if (!video_fb_address) + return; +#ifdef VIDEO_HW_RECTFILL + video_hw_rectfill(VIDEO_PIXEL_SIZE, /* bytes per pixel */ + 0, /* dest pos x */ + 0, /* dest pos y */ + VIDEO_VISIBLE_COLS, /* frame width */ + VIDEO_VISIBLE_ROWS, /* frame height */ + bgx /* fill color */ + ); +#else + memsetl(video_fb_address, + (VIDEO_VISIBLE_ROWS * VIDEO_LINE_LEN) / sizeof(int), bgx); +#endif +} + +static int video_init(void) +{ + unsigned char color8; + + pGD = video_hw_init(); + if (pGD == NULL) + return -1; + + video_fb_address = (void *) VIDEO_FB_ADRS; +#ifdef CONFIG_VIDEO_HW_CURSOR + video_init_hw_cursor(VIDEO_FONT_WIDTH, VIDEO_FONT_HEIGHT); +#endif + + cfb_do_flush_cache = cfb_fb_is_in_dram() && dcache_status(); + + /* Init drawing pats */ + switch (VIDEO_DATA_FORMAT) { + case GDF__8BIT_INDEX: + video_set_lut(0x01, CONSOLE_FG_COL, CONSOLE_FG_COL, + CONSOLE_FG_COL); + video_set_lut(0x00, CONSOLE_BG_COL, CONSOLE_BG_COL, + CONSOLE_BG_COL); + fgx = 0x01010101; + bgx = 0x00000000; + break; + case GDF__8BIT_332RGB: + color8 = ((CONSOLE_FG_COL & 0xe0) | + ((CONSOLE_FG_COL >> 3) & 0x1c) | + CONSOLE_FG_COL >> 6); + fgx = (color8 << 24) | (color8 << 16) | (color8 << 8) | + color8; + color8 = ((CONSOLE_BG_COL & 0xe0) | + ((CONSOLE_BG_COL >> 3) & 0x1c) | + CONSOLE_BG_COL >> 6); + bgx = (color8 << 24) | (color8 << 16) | (color8 << 8) | + color8; + break; + case GDF_15BIT_555RGB: + fgx = (((CONSOLE_FG_COL >> 3) << 26) | + ((CONSOLE_FG_COL >> 3) << 21) | + ((CONSOLE_FG_COL >> 3) << 16) | + ((CONSOLE_FG_COL >> 3) << 10) | + ((CONSOLE_FG_COL >> 3) << 5) | + (CONSOLE_FG_COL >> 3)); + bgx = (((CONSOLE_BG_COL >> 3) << 26) | + ((CONSOLE_BG_COL >> 3) << 21) | + ((CONSOLE_BG_COL >> 3) << 16) | + ((CONSOLE_BG_COL >> 3) << 10) | + ((CONSOLE_BG_COL >> 3) << 5) | + (CONSOLE_BG_COL >> 3)); + break; + case GDF_16BIT_565RGB: + fgx = (((CONSOLE_FG_COL >> 3) << 27) | + ((CONSOLE_FG_COL >> 2) << 21) | + ((CONSOLE_FG_COL >> 3) << 16) | + ((CONSOLE_FG_COL >> 3) << 11) | + ((CONSOLE_FG_COL >> 2) << 5) | + (CONSOLE_FG_COL >> 3)); + bgx = (((CONSOLE_BG_COL >> 3) << 27) | + ((CONSOLE_BG_COL >> 2) << 21) | + ((CONSOLE_BG_COL >> 3) << 16) | + ((CONSOLE_BG_COL >> 3) << 11) | + ((CONSOLE_BG_COL >> 2) << 5) | + (CONSOLE_BG_COL >> 3)); + break; + case GDF_32BIT_X888RGB: + fgx = (CONSOLE_FG_COL << 16) | + (CONSOLE_FG_COL << 8) | + CONSOLE_FG_COL; + bgx = (CONSOLE_BG_COL << 16) | + (CONSOLE_BG_COL << 8) | + CONSOLE_BG_COL; + break; + case GDF_24BIT_888RGB: + fgx = (CONSOLE_FG_COL << 24) | + (CONSOLE_FG_COL << 16) | + (CONSOLE_FG_COL << 8) | + CONSOLE_FG_COL; + bgx = (CONSOLE_BG_COL << 24) | + (CONSOLE_BG_COL << 16) | + (CONSOLE_BG_COL << 8) | + CONSOLE_BG_COL; + break; + } + eorx = fgx ^ bgx; + + video_clear(); + +#ifdef CONFIG_VIDEO_LOGO + /* Plot the logo and get start point of console */ + debug("Video: Drawing the logo ...\n"); + video_console_address = video_logo(); +#else + video_console_address = video_fb_address; +#endif + + /* Initialize the console */ + console_col = 0; + console_row = 0; + + if (cfb_do_flush_cache) + flush_cache(VIDEO_FB_ADRS, VIDEO_SIZE); + + return 0; +} + +/* + * Implement a weak default function for boards that optionally + * need to skip the video initialization. + */ +int __board_video_skip(void) +{ + /* As default, don't skip test */ + return 0; +} + +int board_video_skip(void) + __attribute__ ((weak, alias("__board_video_skip"))); + +int drv_video_init(void) +{ + int skip_dev_init; + struct stdio_dev console_dev; + + /* Check if video initialization should be skipped */ + if (board_video_skip()) + return 0; + + /* Init video chip - returns with framebuffer cleared */ + skip_dev_init = (video_init() == -1); + + if (board_cfb_skip()) + return 0; + +#if !defined(CONFIG_VGA_AS_SINGLE_DEVICE) + debug("KBD: Keyboard init ...\n"); + skip_dev_init |= (VIDEO_KBD_INIT_FCT == -1); +#endif + + if (skip_dev_init) + return 0; + + /* Init vga device */ + memset(&console_dev, 0, sizeof(console_dev)); + strcpy(console_dev.name, "vga"); + console_dev.ext = DEV_EXT_VIDEO; /* Video extensions */ + console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM; + console_dev.putc = video_putc; /* 'putc' function */ + console_dev.puts = video_puts; /* 'puts' function */ + console_dev.tstc = NULL; /* 'tstc' function */ + console_dev.getc = NULL; /* 'getc' function */ + +#if !defined(CONFIG_VGA_AS_SINGLE_DEVICE) + /* Also init console device */ + console_dev.flags |= DEV_FLAGS_INPUT; + console_dev.tstc = VIDEO_TSTC_FCT; /* 'tstc' function */ + console_dev.getc = VIDEO_GETC_FCT; /* 'getc' function */ +#endif /* CONFIG_VGA_AS_SINGLE_DEVICE */ + + if (stdio_register(&console_dev) != 0) + return 0; + + /* Return success */ + return 1; +} + +void video_position_cursor(unsigned col, unsigned row) +{ + console_col = min(col, CONSOLE_COLS - 1); + console_row = min(row, CONSOLE_ROWS - 1); +} + +int video_get_pixel_width(void) +{ + return VIDEO_VISIBLE_COLS; +} + +int video_get_pixel_height(void) +{ + return VIDEO_VISIBLE_ROWS; +} + +int video_get_screen_rows(void) +{ + return CONSOLE_ROWS; +} + +int video_get_screen_columns(void) +{ + return CONSOLE_COLS; +} diff --git a/qemu/roms/u-boot/drivers/video/coreboot_fb.c b/qemu/roms/u-boot/drivers/video/coreboot_fb.c new file mode 100644 index 000000000..56c35c18f --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/coreboot_fb.c @@ -0,0 +1,85 @@ +/* + * coreboot Framebuffer driver. + * + * Copyright (C) 2011 The Chromium OS authors + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/tables.h> +#include <asm/arch/sysinfo.h> +#include <video_fb.h> +#include "videomodes.h" + +/* + * The Graphic Device + */ +GraphicDevice ctfb; + +static int parse_coreboot_table_fb(GraphicDevice *gdev) +{ + struct cb_framebuffer *fb = lib_sysinfo.framebuffer; + + /* If there is no framebuffer structure, bail out and keep + * running on the serial console. + */ + if (!fb) + return 0; + + gdev->winSizeX = fb->x_resolution; + gdev->winSizeY = fb->y_resolution; + + gdev->plnSizeX = fb->x_resolution; + gdev->plnSizeY = fb->y_resolution; + + gdev->gdfBytesPP = fb->bits_per_pixel / 8; + + switch (fb->bits_per_pixel) { + case 24: + gdev->gdfIndex = GDF_32BIT_X888RGB; + break; + case 16: + gdev->gdfIndex = GDF_16BIT_565RGB; + break; + default: + gdev->gdfIndex = GDF__8BIT_INDEX; + break; + } + + gdev->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS; + gdev->pciBase = (unsigned int)fb->physical_address; + + gdev->frameAdrs = (unsigned int)fb->physical_address; + gdev->memSize = fb->bytes_per_line * fb->y_resolution; + + gdev->vprBase = (unsigned int)fb->physical_address; + gdev->cprBase = (unsigned int)fb->physical_address; + + return 1; +} + +void *video_hw_init(void) +{ + GraphicDevice *gdev = &ctfb; + int bits_per_pixel; + + printf("Video: "); + + if (!parse_coreboot_table_fb(gdev)) { + printf("No video mode configured in coreboot!\n"); + return NULL; + } + + bits_per_pixel = gdev->gdfBytesPP * 8; + + /* fill in Graphic device struct */ + sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY, + bits_per_pixel); + printf("%s\n", gdev->modeIdent); + + memset((void *)gdev->pciBase, 0, + gdev->winSizeX * gdev->winSizeY * gdev->gdfBytesPP); + + return (void *)gdev; +} diff --git a/qemu/roms/u-boot/drivers/video/ct69000.c b/qemu/roms/u-boot/drivers/video/ct69000.c new file mode 100644 index 000000000..168b9bad9 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/ct69000.c @@ -0,0 +1,1267 @@ +/* ported from ctfb.c (linux kernel): + * Created in Jan - July 2000 by Thomas Höhenleitner <th@visuelle-maschinen.de> + * + * Ported to U-Boot: + * (C) Copyright 2002 Denis Peter, MPL AG Switzerland + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +#ifdef CONFIG_VIDEO + +#include <pci.h> +#include <video_fb.h> +#include "videomodes.h" + +/* debug */ +#undef VGA_DEBUG +#undef VGA_DUMP_REG +#ifdef VGA_DEBUG +#undef _DEBUG +#define _DEBUG 1 +#else +#undef _DEBUG +#define _DEBUG 0 +#endif + +/* Macros */ +#ifndef min +#define min( a, b ) ( ( a ) < ( b ) ) ? ( a ) : ( b ) +#endif +#ifndef max +#define max( a, b ) ( ( a ) > ( b ) ) ? ( a ) : ( b ) +#endif +#ifdef minmax +#error "term minmax already used." +#endif +#define minmax( a, x, b ) max( ( a ), min( ( x ), ( b ) ) ) +#define N_ELTS( x ) ( sizeof( x ) / sizeof( x[ 0 ] ) ) + +/* CT Register Offsets */ +#define CT_AR_O 0x3c0 /* Index and Data write port of the attribute Registers */ +#define CT_GR_O 0x3ce /* Index port of the Graphic Controller Registers */ +#define CT_SR_O 0x3c4 /* Index port of the Sequencer Controller */ +#define CT_CR_O 0x3d4 /* Index port of the CRT Controller */ +#define CT_XR_O 0x3d6 /* Extended Register index */ +#define CT_MSR_W_O 0x3c2 /* Misc. Output Register (write only) */ +#define CT_LUT_MASK_O 0x3c6 /* Color Palette Mask */ +#define CT_LUT_START_O 0x3c8 /* Color Palette Write Mode Index */ +#define CT_LUT_RGB_O 0x3c9 /* Color Palette Data Port */ +#define CT_STATUS_REG0_O 0x3c2 /* Status Register 0 (read only) */ +#define CT_STATUS_REG1_O 0x3da /* Input Status Register 1 (read only) */ + +#define CT_FP_O 0x3d0 /* Index port of the Flat panel Registers */ +#define CT_MR_O 0x3d2 /* Index Port of the Multimedia Extension */ + +/* defines for the memory mapped registers */ +#define BR00_o 0x400000 /* Source and Destination Span Register */ +#define BR01_o 0x400004 /* Pattern/Source Expansion Background Color & Transparency Key Register */ +#define BR02_o 0x400008 /* Pattern/Source Expansion Foreground Color Register */ +#define BR03_o 0x40000C /* Monochrome Source Control Register */ +#define BR04_o 0x400010 /* BitBLT Control Register */ +#define BR05_o 0x400014 /* Pattern Address Registe */ +#define BR06_o 0x400018 /* Source Address Register */ +#define BR07_o 0x40001C /* Destination Address Register */ +#define BR08_o 0x400020 /* Destination Width & Height Register */ +#define BR09_o 0x400024 /* Source Expansion Background Color & Transparency Key Register */ +#define BR0A_o 0x400028 /* Source Expansion Foreground Color Register */ + +#define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */ +#define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */ +#define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */ +#define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */ + +/* Some Mode definitions */ +#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */ +#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */ +#define FB_SYNC_EXT 4 /* external sync */ +#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */ +#define FB_SYNC_BROADCAST 16 /* broadcast video timings */ + /* vtotal = 144d/288n/576i => PAL */ + /* vtotal = 121d/242n/484i => NTSC */ +#define FB_SYNC_ON_GREEN 32 /* sync on green */ + +#define FB_VMODE_NONINTERLACED 0 /* non interlaced */ +#define FB_VMODE_INTERLACED 1 /* interlaced */ +#define FB_VMODE_DOUBLE 2 /* double scan */ +#define FB_VMODE_MASK 255 + +#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */ +#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */ +#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */ + +#define text 0 +#define fntwidth 8 + +/* table for VGA Initialization */ +typedef struct { + const unsigned char reg; + const unsigned char val; +} CT_CFG_TABLE; + +/* this table provides some basic initialisations such as Memory Clock etc */ +static CT_CFG_TABLE xreg[] = { + {0x09, 0x01}, /* CRT Controller Extensions Enable */ + {0x0A, 0x02}, /* Frame Buffer Mapping */ + {0x0B, 0x01}, /* PCI Write Burst support */ + {0x20, 0x00}, /* BitBLT Configuration */ + {0x40, 0x03}, /* Memory Access Control */ + {0x60, 0x00}, /* Video Pin Control */ + {0x61, 0x00}, /* DPMS Synch control */ + {0x62, 0x00}, /* GPIO Pin Control */ + {0x63, 0xBD}, /* GPIO Pin Data */ + {0x67, 0x00}, /* Pin Tri-State */ + {0x80, 0x80}, /* Pixel Pipeline Config 0 register */ + {0xA0, 0x00}, /* Cursor 1 Control Reg */ + {0xA1, 0x00}, /* Cursor 1 Vertical Extension Reg */ + {0xA2, 0x00}, /* Cursor 1 Base Address Low */ + {0xA3, 0x00}, /* Cursor 1 Base Address High */ + {0xA4, 0x00}, /* Cursor 1 X-Position Low */ + {0xA5, 0x00}, /* Cursor 1 X-Position High */ + {0xA6, 0x00}, /* Cursor 1 Y-Position Low */ + {0xA7, 0x00}, /* Cursor 1 Y-Position High */ + {0xA8, 0x00}, /* Cursor 2 Control Reg */ + {0xA9, 0x00}, /* Cursor 2 Vertical Extension Reg */ + {0xAA, 0x00}, /* Cursor 2 Base Address Low */ + {0xAB, 0x00}, /* Cursor 2 Base Address High */ + {0xAC, 0x00}, /* Cursor 2 X-Position Low */ + {0xAD, 0x00}, /* Cursor 2 X-Position High */ + {0xAE, 0x00}, /* Cursor 2 Y-Position Low */ + {0xAF, 0x00}, /* Cursor 2 Y-Position High */ + {0xC0, 0x7D}, /* Dot Clock 0 VCO M-Divisor */ + {0xC1, 0x07}, /* Dot Clock 0 VCO N-Divisor */ + {0xC3, 0x34}, /* Dot Clock 0 Divisor select */ + {0xC4, 0x55}, /* Dot Clock 1 VCO M-Divisor */ + {0xC5, 0x09}, /* Dot Clock 1 VCO N-Divisor */ + {0xC7, 0x24}, /* Dot Clock 1 Divisor select */ + {0xC8, 0x7D}, /* Dot Clock 2 VCO M-Divisor */ + {0xC9, 0x07}, /* Dot Clock 2 VCO N-Divisor */ + {0xCB, 0x34}, /* Dot Clock 2 Divisor select */ + {0xCC, 0x38}, /* Memory Clock 0 VCO M-Divisor */ + {0xCD, 0x03}, /* Memory Clock 0 VCO N-Divisor */ + {0xCE, 0x90}, /* Memory Clock 0 Divisor select */ + {0xCF, 0x06}, /* Clock Config */ + {0xD0, 0x0F}, /* Power Down */ + {0xD1, 0x01}, /* Power Down BitBLT */ + {0xFF, 0xFF} /* end of table */ +}; +/* Clock Config: + * ============= + * + * PD Registers: + * ------------- + * Bit2 and Bit4..6 are used for the Loop Divisor and Post Divisor. + * They are encoded as follows: + * + * +---+--------------+ + * | 2 | Loop Divisor | + * +---+--------------+ + * | 1 | 1 | + * +---+--------------+ + * | 0 | 4 | + * +---+--------------+ + * Note: The Memory Clock does not have a Loop Divisor. + * +---+---+---+--------------+ + * | 6 | 5 | 4 | Post Divisor | + * +---+---+---+--------------+ + * | 0 | 0 | 0 | 1 | + * +---+---+---+--------------+ + * | 0 | 0 | 1 | 2 | + * +---+---+---+--------------+ + * | 0 | 1 | 0 | 4 | + * +---+---+---+--------------+ + * | 0 | 1 | 1 | 8 | + * +---+---+---+--------------+ + * | 1 | 0 | 0 | 16 | + * +---+---+---+--------------+ + * | 1 | 0 | 1 | 32 | + * +---+---+---+--------------+ + * | 1 | 1 | X | reserved | + * +---+---+---+--------------+ + * + * All other bits are reserved in these registers. + * + * Clock VCO M Registers: + * ---------------------- + * These Registers contain the M Value -2. + * + * Clock VCO N Registers: + * ---------------------- + * These Registers contain the N Value -2. + * + * Formulas: + * --------- + * Fvco = (Fref * Loop Divisor * M/N), whereas 100MHz < Fvco < 220MHz + * Fout = Fvco / Post Divisor + * + * Dot Clk0 (default 25MHz): + * ------------------------- + * Fvco = 14.318 * 127 / 9 = 202.045MHz + * Fout = 202.045MHz / 8 = 25.25MHz + * Post Divisor = 8 + * Loop Divisor = 1 + * XRC0 = (M - 2) = 125 = 0x7D + * XRC1 = (N - 2) = 7 = 0x07 + * XRC3 = 0x34 + * + * Dot Clk1 (default 28MHz): + * ------------------------- + * Fvco = 14.318 * 87 / 11 = 113.24MHz + * Fout = 113.24MHz / 4 = 28.31MHz + * Post Divisor = 4 + * Loop Divisor = 1 + * XRC4 = (M - 2) = 85 = 0x55 + * XRC5 = (N - 2) = 9 = 0x09 + * XRC7 = 0x24 + * + * Dot Clk2 (variable for extended modes set to 25MHz): + * ---------------------------------------------------- + * Fvco = 14.318 * 127 / 9 = 202.045MHz + * Fout = 202.045MHz / 8 = 25.25MHz + * Post Divisor = 8 + * Loop Divisor = 1 + * XRC8 = (M - 2) = 125 = 0x7D + * XRC9 = (N - 2) = 7 = 0x07 + * XRCB = 0x34 + * + * Memory Clk for most modes >50MHz: + * ---------------------------------- + * Fvco = 14.318 * 58 / 5 = 166MHz + * Fout = 166MHz / 2 = 83MHz + * Post Divisor = 2 + * XRCC = (M - 2) = 57 = 0x38 + * XRCD = (N - 2) = 3 = 0x03 + * XRCE = 0x90 + * + * Note Bit7 enables the clock source from the VCO + * + */ + +/******************************************************************* + * Chips struct + *******************************************************************/ +struct ctfb_chips_properties { + int device_id; /* PCI Device ID */ + unsigned long max_mem; /* memory for frame buffer */ + int vld_set; /* value of VLD if bit2 in clock control is set */ + int vld_not_set; /* value of VLD if bit2 in clock control is set */ + int mn_diff; /* difference between M/N Value + mn_diff = M/N Register */ + int mn_min; /* min value of M/N Value */ + int mn_max; /* max value of M/N Value */ + int vco_min; /* VCO Min in MHz */ + int vco_max; /* VCO Max in MHz */ +}; + +static const struct ctfb_chips_properties chips[] = { + {PCI_DEVICE_ID_CT_69000, 0x200000, 1, 4, -2, 3, 257, 100, 220}, +#ifdef CONFIG_USE_CPCIDVI + {PCI_DEVICE_ID_CT_69030, 0x400000, 1, 4, -2, 3, 257, 100, 220}, +#endif + {PCI_DEVICE_ID_CT_65555, 0x100000, 16, 4, 0, 1, 255, 48, 220}, /* NOT TESTED */ + {0, 0, 0, 0, 0, 0, 0, 0, 0} /* Terminator */ +}; + +/* + * The Graphic Device + */ +GraphicDevice ctfb; + +/******************************************************************************* +* +* Low Level Routines +*/ + +/******************************************************************************* +* +* Read CT ISA register +*/ +#ifdef VGA_DEBUG +static unsigned char +ctRead (unsigned short index) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + if (index == CT_AR_O) + /* synch the Flip Flop */ + in8 (pGD->isaBase + CT_STATUS_REG1_O); + + return (in8 (pGD->isaBase + index)); +} +#endif +/******************************************************************************* +* +* Write CT ISA register +*/ +static void +ctWrite (unsigned short index, unsigned char val) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + + out8 ((pGD->isaBase + index), val); +} + +/******************************************************************************* +* +* Read CT ISA register indexed +*/ +static unsigned char +ctRead_i (unsigned short index, char reg) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + if (index == CT_AR_O) + /* synch the Flip Flop */ + in8 (pGD->isaBase + CT_STATUS_REG1_O); + out8 ((pGD->isaBase + index), reg); + return (in8 (pGD->isaBase + index + 1)); +} + +/******************************************************************************* +* +* Write CT ISA register indexed +*/ +static void +ctWrite_i (unsigned short index, char reg, char val) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + if (index == CT_AR_O) { + /* synch the Flip Flop */ + in8 (pGD->isaBase + CT_STATUS_REG1_O); + out8 ((pGD->isaBase + index), reg); + out8 ((pGD->isaBase + index), val); + } else { + out8 ((pGD->isaBase + index), reg); + out8 ((pGD->isaBase + index + 1), val); + } +} + +/******************************************************************************* +* +* Write a table of CT ISA register +*/ +static void +ctLoadRegs (unsigned short index, CT_CFG_TABLE * regTab) +{ + while (regTab->reg != 0xFF) { + ctWrite_i (index, regTab->reg, regTab->val); + regTab++; + } +} + +/*****************************************************************************/ +static void +SetArRegs (void) +{ + int i, tmp; + + for (i = 0; i < 0x10; i++) + ctWrite_i (CT_AR_O, i, i); + if (text) + tmp = 0x04; + else + tmp = 0x41; + + ctWrite_i (CT_AR_O, 0x10, tmp); /* Mode Control Register */ + ctWrite_i (CT_AR_O, 0x11, 0x00); /* Overscan Color Register */ + ctWrite_i (CT_AR_O, 0x12, 0x0f); /* Memory Plane Enable Register */ + if (fntwidth == 9) + tmp = 0x08; + else + tmp = 0x00; + ctWrite_i (CT_AR_O, 0x13, tmp); /* Horizontal Pixel Panning */ + ctWrite_i (CT_AR_O, 0x14, 0x00); /* Color Select Register */ + ctWrite (CT_AR_O, 0x20); /* enable video */ +} + +/*****************************************************************************/ +static void +SetGrRegs (void) +{ /* Set Graphics Mode */ + int i; + + for (i = 0; i < 0x05; i++) + ctWrite_i (CT_GR_O, i, 0); + if (text) { + ctWrite_i (CT_GR_O, 0x05, 0x10); + ctWrite_i (CT_GR_O, 0x06, 0x02); + } else { + ctWrite_i (CT_GR_O, 0x05, 0x40); + ctWrite_i (CT_GR_O, 0x06, 0x05); + } + ctWrite_i (CT_GR_O, 0x07, 0x0f); + ctWrite_i (CT_GR_O, 0x08, 0xff); +} + +/*****************************************************************************/ +static void +SetSrRegs (void) +{ + int tmp = 0; + + ctWrite_i (CT_SR_O, 0x00, 0x00); /* reset */ + /*rr( sr, 0x01, tmp ); + if( fntwidth == 8 ) tmp |= 0x01; else tmp &= ~0x01; + wr( sr, 0x01, tmp ); */ + if (fntwidth == 8) + ctWrite_i (CT_SR_O, 0x01, 0x01); /* Clocking Mode Register */ + else + ctWrite_i (CT_SR_O, 0x01, 0x00); /* Clocking Mode Register */ + ctWrite_i (CT_SR_O, 0x02, 0x0f); /* Enable CPU wr access to given memory plane */ + ctWrite_i (CT_SR_O, 0x03, 0x00); /* Character Map Select Register */ + if (text) + tmp = 0x02; + else + tmp = 0x0e; + ctWrite_i (CT_SR_O, 0x04, tmp); /* Enable CPU accesses to the rest of the 256KB + total VGA memory beyond the first 64KB and set + fb mapping mode. */ + ctWrite_i (CT_SR_O, 0x00, 0x03); /* enable */ +} + +/*****************************************************************************/ +static void +SetBitsPerPixelIntoXrRegs (int bpp) +{ + unsigned int n = (bpp >> 3), tmp; /* only for 15, 8, 16, 24 bpp */ + static char md[4] = { 0x04, 0x02, 0x05, 0x06 }; /* DisplayColorMode */ + static char off[4] = { ~0x20, ~0x30, ~0x20, ~0x10 }; /* mask */ + static char on[4] = { 0x10, 0x00, 0x10, 0x20 }; /* mask */ + if (bpp == 15) + n = 0; + tmp = ctRead_i (CT_XR_O, 0x20); + tmp &= off[n]; + tmp |= on[n]; + ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */ + ctWrite_i (CT_XR_O, 0x81, md[n]); +} + +/*****************************************************************************/ +static void +SetCrRegs (struct ctfb_res_modes *var, int bits_per_pixel) +{ /* he -le- ht|0 hd -ri- hs -h- he */ + unsigned char cr[0x7a]; + int i, tmp; + unsigned int hd, hs, he, ht, hbe; /* Horizontal. */ + unsigned int vd, vs, ve, vt; /* vertical */ + unsigned int bpp, wd, dblscan, interlaced, bcast, CrtHalfLine; + unsigned int CompSyncCharClkDelay, CompSyncPixelClkDelay; + unsigned int NTSC_PAL_HorizontalPulseWidth, BlDelayCtrl; + unsigned int HorizontalEqualizationPulses; + unsigned int HorizontalSerration1Start, HorizontalSerration2Start; + + const int LineCompare = 0x3ff; + unsigned int TextScanLines = 1; /* this is in fact a vertical zoom factor */ + unsigned int RAMDAC_BlankPedestalEnable = 0; /* 1=en-, 0=disable, see XR82 */ + + hd = (var->xres) / 8; /* HDisp. */ + hs = (var->xres + var->right_margin) / 8; /* HsStrt */ + he = (var->xres + var->right_margin + var->hsync_len) / 8; /* HsEnd */ + ht = (var->left_margin + var->xres + var->right_margin + var->hsync_len) / 8; /* HTotal */ + hbe = ht - 1; /* HBlankEnable todo docu wants ht here, but it does not work */ + /* ve -up- vt|0 vd -lo- vs -v- ve */ + vd = var->yres; /* VDisplay */ + vs = var->yres + var->lower_margin; /* VSyncStart */ + ve = var->yres + var->lower_margin + var->vsync_len; /* VSyncEnd */ + vt = var->upper_margin + var->yres + var->lower_margin + var->vsync_len; /* VTotal */ + bpp = bits_per_pixel; + dblscan = (var->vmode & FB_VMODE_DOUBLE) ? 1 : 0; + interlaced = var->vmode & FB_VMODE_INTERLACED; + bcast = var->sync & FB_SYNC_BROADCAST; + CrtHalfLine = bcast ? (hd >> 1) : 0; + BlDelayCtrl = bcast ? 1 : 0; + CompSyncCharClkDelay = 0; /* 2 bit */ + CompSyncPixelClkDelay = 0; /* 3 bit */ + if (bcast) { + NTSC_PAL_HorizontalPulseWidth = 7; /*( var->hsync_len >> 1 ) + 1 */ + HorizontalEqualizationPulses = 0; /* inverse value */ + HorizontalSerration1Start = 31; /* ( ht >> 1 ) */ + HorizontalSerration2Start = 89; /* ( ht >> 1 ) */ + } else { + NTSC_PAL_HorizontalPulseWidth = 0; + /* 4 bit: hsync pulse width = ( ( CR74[4:0] - CR74[5] ) + * / 2 ) + 1 --> CR74[4:0] = 2*(hs-1) + CR74[5] */ + HorizontalEqualizationPulses = 1; /* inverse value */ + HorizontalSerration1Start = 0; /* ( ht >> 1 ) */ + HorizontalSerration2Start = 0; /* ( ht >> 1 ) */ + } + + if (bpp == 15) + bpp = 16; + wd = var->xres * bpp / 64; /* double words per line */ + if (interlaced) { /* we divide all vertical timings, exept vd */ + vs >>= 1; + ve >>= 1; + vt >>= 1; + } + memset (cr, 0, sizeof (cr)); + cr[0x00] = 0xff & (ht - 5); + cr[0x01] = hd - 1; /* soll:4f ist 59 */ + cr[0x02] = hd; + cr[0x03] = (hbe & 0x1F) | 0x80; /* hd + ht - hd */ + cr[0x04] = hs; + cr[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f); + cr[0x06] = (vt - 2) & 0xFF; + cr[0x30] = (vt - 2) >> 8; + cr[0x07] = ((vt & 0x100) >> 8) + | ((vd & 0x100) >> 7) + | ((vs & 0x100) >> 6) + | ((vs & 0x100) >> 5) + | ((LineCompare & 0x100) >> 4) + | ((vt & 0x200) >> 4) + | ((vd & 0x200) >> 3) + | ((vs & 0x200) >> 2); + cr[0x08] = 0x00; + cr[0x09] = (dblscan << 7) + | ((LineCompare & 0x200) >> 3) + | ((vs & 0x200) >> 4) + | (TextScanLines - 1); + cr[0x10] = vs & 0xff; /* VSyncPulseStart */ + cr[0x32] = (vs & 0xf00) >> 8; /* VSyncPulseStart */ + cr[0x11] = (ve & 0x0f); /* | 0x20; */ + cr[0x12] = (vd - 1) & 0xff; /* LineCount */ + cr[0x31] = ((vd - 1) & 0xf00) >> 8; /* LineCount */ + cr[0x13] = wd & 0xff; + cr[0x41] = (wd & 0xf00) >> 8; + cr[0x15] = vs & 0xff; + cr[0x33] = (vs & 0xf00) >> 8; + cr[0x38] = (0x100 & (ht - 5)) >> 8; + cr[0x3C] = 0xc0 & hbe; + cr[0x16] = (vt - 1) & 0xff; /* vbe - docu wants vt here, */ + cr[0x17] = 0xe3; /* but it does not work */ + cr[0x18] = 0xff & LineCompare; + cr[0x22] = 0xff; /* todo? */ + cr[0x70] = interlaced ? (0x80 | CrtHalfLine) : 0x00; /* check:0xa6 */ + cr[0x71] = 0x80 | (RAMDAC_BlankPedestalEnable << 6) + | (BlDelayCtrl << 5) + | ((0x03 & CompSyncCharClkDelay) << 3) + | (0x07 & CompSyncPixelClkDelay); /* todo: see XR82 */ + cr[0x72] = HorizontalSerration1Start; + cr[0x73] = HorizontalSerration2Start; + cr[0x74] = (HorizontalEqualizationPulses << 5) + | NTSC_PAL_HorizontalPulseWidth; + /* todo: ct69000 has also 0x75-79 */ + /* now set the registers */ + for (i = 0; i <= 0x0d; i++) { /*CR00 .. CR0D */ + ctWrite_i (CT_CR_O, i, cr[i]); + } + for (i = 0x10; i <= 0x18; i++) { /*CR10 .. CR18 */ + ctWrite_i (CT_CR_O, i, cr[i]); + } + i = 0x22; /*CR22 */ + ctWrite_i (CT_CR_O, i, cr[i]); + for (i = 0x30; i <= 0x33; i++) { /*CR30 .. CR33 */ + ctWrite_i (CT_CR_O, i, cr[i]); + } + i = 0x38; /*CR38 */ + ctWrite_i (CT_CR_O, i, cr[i]); + i = 0x3C; /*CR3C */ + ctWrite_i (CT_CR_O, i, cr[i]); + for (i = 0x40; i <= 0x41; i++) { /*CR40 .. CR41 */ + ctWrite_i (CT_CR_O, i, cr[i]); + } + for (i = 0x70; i <= 0x74; i++) { /*CR70 .. CR74 */ + ctWrite_i (CT_CR_O, i, cr[i]); + } + tmp = ctRead_i (CT_CR_O, 0x40); + tmp &= 0x0f; + tmp |= 0x80; + ctWrite_i (CT_CR_O, 0x40, tmp); /* StartAddressEnable */ +} + +/* pixelclock control */ + +/***************************************************************************** + We have a rational number p/q and need an m/n which is very close to p/q + but has m and n within mnmin and mnmax. We have no floating point in the + kernel. We can use long long without divide. And we have time to compute... +******************************************************************************/ +static unsigned int +FindBestPQFittingMN (unsigned int p, unsigned int q, unsigned int mnmin, + unsigned int mnmax, unsigned int *pm, unsigned int *pn) +{ + /* this code is not for general purpose usable but good for our number ranges */ + unsigned int n = mnmin, m = 0; + long long int L = 0, P = p, Q = q, H = P >> 1; + long long int D = 0x7ffffffffffffffLL; + for (n = mnmin; n <= mnmax; n++) { + m = mnmin; /* p/q ~ m/n -> p*n ~ m*q -> p*n-x*q ~ 0 */ + L = P * n - m * Q; /* n * vco - m * fref should be near 0 */ + while (L > 0 && m < mnmax) { + L -= q; /* difference is greater as 0 subtract fref */ + m++; /* and increment m */ + } + /* difference is less or equal than 0 or m > maximum */ + if (m > mnmax) + break; /* no solution: if we increase n we get the same situation */ + /* L is <= 0 now */ + if (-L > H && m > mnmin) { /* if difference > the half fref */ + L += q; /* we take the situation before */ + m--; /* because its closer to 0 */ + } + L = (L < 0) ? -L : +L; /* absolute value */ + if (D < L) /* if last difference was better take next n */ + continue; + D = L; + *pm = m; + *pn = n; /* keep improved data */ + if (D == 0) + break; /* best result we can get */ + } + return (unsigned int) (0xffffffff & D); +} + +/* that is the hardware < 69000 we have to manage + +---------+ +-------------------+ +----------------------+ +--+ + | REFCLK |__|NTSC Divisor Select|__|FVCO Reference Divisor|__|÷N|__ + | 14.3MHz | |(NTSCDS) (÷1, ÷5) | |Select (RDS) (÷1, ÷4) | | | | + +---------+ +-------------------+ +----------------------+ +--+ | + ___________________________________________________________________| + | + | fvco fout + | +--------+ +------------+ +-----+ +-------------------+ +----+ + +-| Phase |__|Charge Pump |__| VCO |_____|Post Divisor (PD) |___|CLK |---> + +-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | | + | +--------+ +------------+ +-----+ | +-------------------+ +----+ + | | + | +--+ +---------------+ | + |____|÷M|___|VCO Loop Divide|__________| + | | |(VLD)(÷4, ÷16) | + +--+ +---------------+ +**************************************************************************** + that is the hardware >= 69000 we have to manage + +---------+ +--+ + | REFCLK |__|÷N|__ + | 14.3MHz | | | | + +---------+ +--+ | + __________________| + | + | fvco fout + | +--------+ +------------+ +-----+ +-------------------+ +----+ + +-| Phase |__|Charge Pump |__| VCO |_____|Post Divisor (PD) |___|CLK |---> + +-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | | + | +--------+ +------------+ +-----+ | +-------------------+ +----+ + | | + | +--+ +---------------+ | + |____|÷M|___|VCO Loop Divide|__________| + | | |(VLD)(÷1, ÷4) | + +--+ +---------------+ + + +*/ + +#define VIDEO_FREF 14318180; /* Hz */ +/*****************************************************************************/ +static int +ReadPixClckFromXrRegsBack (struct ctfb_chips_properties *param) +{ + unsigned int m, n, vld, pd, PD, fref, xr_cb, i, pixclock; + i = 0; + pixclock = -1; + fref = VIDEO_FREF; + m = ctRead_i (CT_XR_O, 0xc8); + n = ctRead_i (CT_XR_O, 0xc9); + m -= param->mn_diff; + n -= param->mn_diff; + xr_cb = ctRead_i (CT_XR_O, 0xcb); + PD = (0x70 & xr_cb) >> 4; + pd = 1; + for (i = 0; i < PD; i++) { + pd *= 2; + } + vld = (0x04 & xr_cb) ? param->vld_set : param->vld_not_set; + if (n * vld * m) { + unsigned long long p = 1000000000000LL * pd * n; + unsigned long long q = (long long) fref * vld * m; + while ((p > 0xffffffffLL) || (q > 0xffffffffLL)) { + p >>= 1; /* can't divide with long long so we scale down */ + q >>= 1; + } + pixclock = (unsigned) p / (unsigned) q; + } else + printf ("Invalid data in xr regs.\n"); + return pixclock; +} + +/*****************************************************************************/ +static void +FindAndSetPllParamIntoXrRegs (unsigned int pixelclock, + struct ctfb_chips_properties *param) +{ + unsigned int m, n, vld, pd, PD, fref, xr_cb; + unsigned int fvcomin, fvcomax, pclckmin, pclckmax, pclk; + unsigned int pfreq, fvco, new_pixclock; + unsigned int D,nback,mback; + + fref = VIDEO_FREF; + pd = 1; + PD = 0; + fvcomin = param->vco_min; + fvcomax = param->vco_max; /* MHz */ + pclckmin = 1000000 / fvcomax + 1; /* 4546 */ + pclckmax = 32000000 / fvcomin - 1; /* 666665 */ + pclk = minmax (pclckmin, pixelclock, pclckmax); /* ps pp */ + pfreq = 250 * (4000000000U / pclk); + fvco = pfreq; /* Hz */ + new_pixclock = 0; + while (fvco < fvcomin * 1000000) { + /* double VCO starting with the pixelclock frequency + * as long as it is lower than the minimal VCO frequency */ + fvco *= 2; + pd *= 2; + PD++; + } + /* fvco is exactly pd * pixelclock and higher than the ninmal VCO frequency */ + /* first try */ + vld = param->vld_set; + D=FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n); /* rds = 1 */ + mback=m; + nback=n; + /* second try */ + vld = param->vld_not_set; + if(D<FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n)) { /* rds = 1 */ + /* first try was better */ + m=mback; + n=nback; + vld = param->vld_set; + } + m += param->mn_diff; + n += param->mn_diff; + debug("VCO %d, pd %d, m %d n %d vld %d\n", fvco, pd, m, n, vld); + xr_cb = ((0x7 & PD) << 4) | (vld == param->vld_set ? 0x04 : 0); + /* All four of the registers used for dot clock 2 (XRC8 - XRCB) must be + * written, and in order from XRC8 to XRCB, before the hardware will + * update the synthesizer s settings. + */ + ctWrite_i (CT_XR_O, 0xc8, m); + ctWrite_i (CT_XR_O, 0xc9, n); /* xrca does not exist in CT69000 and CT69030 */ + ctWrite_i (CT_XR_O, 0xca, 0); /* because of a hw bug I guess, but we write */ + ctWrite_i (CT_XR_O, 0xcb, xr_cb); /* 0 to it for savety */ + new_pixclock = ReadPixClckFromXrRegsBack (param); + debug("pixelclock.set = %d, pixelclock.real = %d\n", + pixelclock, new_pixclock); +} + +/*****************************************************************************/ +static void +SetMsrRegs (struct ctfb_res_modes *mode) +{ + unsigned char h_synch_high, v_synch_high; + + h_synch_high = (mode->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x40; /* horizontal Synch High active */ + v_synch_high = (mode->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x80; /* vertical Synch High active */ + ctWrite (CT_MSR_W_O, (h_synch_high | v_synch_high | 0x29)); + /* upper64K==0x20, CLC2select==0x08, RAMenable==0x02!(todo), CGA==0x01 + * Selects the upper 64KB page.Bit5=1 + * CLK2 (left reserved in standard VGA) Bit3|2=1|0 + * Disables CPU access to frame buffer. Bit1=0 + * Sets the I/O address decode for ST01, FCR, and all CR registers + * to the 3Dx I/O address range (CGA emulation). Bit0=1 + */ +} + +/************************************************************************************/ +#ifdef VGA_DUMP_REG + +static void +ctDispRegs (unsigned short index, int from, int to) +{ + unsigned char status; + int i; + + for (i = from; i < to; i++) { + status = ctRead_i (index, i); + printf ("%02X: is %02X\n", i, status); + } +} + +void +video_dump_reg (void) +{ + int i; + + printf ("Extended Regs:\n"); + ctDispRegs (CT_XR_O, 0, 0xC); + ctDispRegs (CT_XR_O, 0xe, 0xf); + ctDispRegs (CT_XR_O, 0x20, 0x21); + ctDispRegs (CT_XR_O, 0x40, 0x50); + ctDispRegs (CT_XR_O, 0x60, 0x64); + ctDispRegs (CT_XR_O, 0x67, 0x68); + ctDispRegs (CT_XR_O, 0x70, 0x72); + ctDispRegs (CT_XR_O, 0x80, 0x83); + ctDispRegs (CT_XR_O, 0xA0, 0xB0); + ctDispRegs (CT_XR_O, 0xC0, 0xD3); + printf ("Sequencer Regs:\n"); + ctDispRegs (CT_SR_O, 0, 0x8); + printf ("Graphic Regs:\n"); + ctDispRegs (CT_GR_O, 0, 0x9); + printf ("CRT Regs:\n"); + ctDispRegs (CT_CR_O, 0, 0x19); + ctDispRegs (CT_CR_O, 0x22, 0x23); + ctDispRegs (CT_CR_O, 0x30, 0x34); + ctDispRegs (CT_CR_O, 0x38, 0x39); + ctDispRegs (CT_CR_O, 0x3C, 0x3D); + ctDispRegs (CT_CR_O, 0x40, 0x42); + ctDispRegs (CT_CR_O, 0x70, 0x80); + /* don't display the attributes */ +} + +#endif + +#ifdef CONFIG_VIDEO_HW_CURSOR +/*************************************************************** + * Set Hardware Cursor in Pixel + */ +void +video_set_hw_cursor (int x, int y) +{ + int sig_x = 0, sig_y = 0; + if (x < 0) { + x *= -1; + sig_x = 1; + } + if (y < 0) { + y *= -1; + sig_y = 1; + } + ctWrite_i (CT_XR_O, 0xa4, x & 0xff); + ctWrite_i (CT_XR_O, 0xa5, (x >> 8) & 0x7); + ctWrite_i (CT_XR_O, 0xa6, y & 0xff); + ctWrite_i (CT_XR_O, 0xa7, (y >> 8) & 0x7); +} + +/*************************************************************** + * Init Hardware Cursor. To know the size of the Cursor, + * we have to know the Font size. + */ +void +video_init_hw_cursor (int font_width, int font_height) +{ + unsigned char xr_80; + unsigned long *curs, pattern; + int i; + int cursor_start; + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + + cursor_start = pGD->dprBase; + xr_80 = ctRead_i (CT_XR_O, 0x80); + /* set start address */ + ctWrite_i (CT_XR_O, 0xa2, (cursor_start >> 8) & 0xf0); + ctWrite_i (CT_XR_O, 0xa3, (cursor_start >> 16) & 0x3f); + /* set cursor shape */ + curs = (unsigned long *) cursor_start; + i = 0; + while (i < 0x400) { + curs[i++] = 0xffffffff; /* AND mask */ + curs[i++] = 0xffffffff; /* AND mask */ + curs[i++] = 0; /* XOR mask */ + curs[i++] = 0; /* XOR mask */ + /* Transparent */ + } + pattern = 0xffffffff >> font_width; + i = 0; + while (i < (font_height * 2)) { + curs[i++] = pattern; /* AND mask */ + curs[i++] = pattern; /* AND mask */ + curs[i++] = 0; /* XOR mask */ + curs[i++] = 0; /* XOR mask */ + /* Cursor Color 0 */ + } + /* set blink rate */ + ctWrite_i (CT_FP_O, 0x19, 0xf); + + /* set cursors colors */ + xr_80 = ctRead_i (CT_XR_O, 0x80); + xr_80 |= 0x1; /* alternate palette select */ + ctWrite_i (CT_XR_O, 0x80, xr_80); + video_set_lut (4, CONSOLE_FG_COL, CONSOLE_FG_COL, CONSOLE_FG_COL); + /* position 4 is color 0 cursor 0 */ + xr_80 &= 0xfe; /* normal palette select */ + ctWrite_i (CT_XR_O, 0x80, xr_80); + /* cursor enable */ + ctWrite_i (CT_XR_O, 0xa0, 0x91); + xr_80 |= 0x10; /* enable hwcursor */ + ctWrite_i (CT_XR_O, 0x80, xr_80); + video_set_hw_cursor (0, 0); +} +#endif /* CONFIG_VIDEO_HW_CURSOR */ + +/*************************************************************** + * Wait for BitBlt ready + */ +static int +video_wait_bitblt (unsigned long addr) +{ + unsigned long br04; + int i = 0; + br04 = in32r (addr); + while (br04 & 0x80000000) { + udelay (1); + br04 = in32r (addr); + if (i++ > 1000000) { + printf ("ERROR Timeout %lx\n", br04); + return 1; + } + } + return 0; +} + +/*************************************************************** + * Set up BitBlt Registrs + */ +static void +SetDrawingEngine (int bits_per_pixel) +{ + unsigned long br04, br00; + unsigned char tmp; + + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + + tmp = ctRead_i (CT_XR_O, 0x20); /* BitBLT Configuration */ + tmp |= 0x02; /* reset BitBLT */ + ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */ + udelay (10); + tmp &= 0xfd; /* release reset BitBLT */ + ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */ + video_wait_bitblt (pGD->pciBase + BR04_o); + + /* set pattern Address */ + out32r (pGD->pciBase + BR05_o, PATTERN_ADR & 0x003ffff8); + br04 = 0; + if (bits_per_pixel == 1) { + br04 |= 0x00040000; /* monochome Pattern */ + br04 |= 0x00001000; /* monochome source */ + } + br00 = ((pGD->winSizeX * pGD->gdfBytesPP) << 16) + (pGD->winSizeX * pGD->gdfBytesPP); /* bytes per scanline */ + out32r (pGD->pciBase + BR00_o, br00); /* */ + out32r (pGD->pciBase + BR08_o, (10 << 16) + 10); /* dummy */ + out32r (pGD->pciBase + BR04_o, br04); /* write all 0 */ + out32r (pGD->pciBase + BR07_o, 0); /* destination */ + video_wait_bitblt (pGD->pciBase + BR04_o); +} + +/**************************************************************************** +* supported Video Chips +*/ +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000}, +#ifdef CONFIG_USE_CPCIDVI + {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030}, +#endif + {} +}; + +/******************************************************************************* +* +* Init video chip +*/ +void * +video_hw_init (void) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + unsigned short device_id; + pci_dev_t devbusfn; + int videomode; + unsigned long t1, hsynch, vsynch; + unsigned int pci_mem_base, *vm; + int tmp, i, bits_per_pixel; + char *penv; + struct ctfb_res_modes *res_mode; + struct ctfb_res_modes var_mode; + struct ctfb_chips_properties *chips_param; + /* Search for video chip */ + + if ((devbusfn = pci_find_devices (supported, 0)) < 0) { +#ifdef CONFIG_VIDEO_ONBOARD + printf ("Video: Controller not found !\n"); +#endif + return (NULL); + } + + /* PCI setup */ + pci_write_config_dword (devbusfn, PCI_COMMAND, + (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); + pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id); + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base); + pci_mem_base = pci_mem_to_phys (devbusfn, pci_mem_base); + + /* get chips params */ + for (chips_param = (struct ctfb_chips_properties *) &chips[0]; + chips_param->device_id != 0; chips_param++) { + if (chips_param->device_id == device_id) + break; + } + if (chips_param->device_id == 0) { +#ifdef CONFIG_VIDEO_ONBOARD + printf ("Video: controller 0x%X not supported\n", device_id); +#endif + return NULL; + } + /* supported Video controller found */ + printf ("Video: "); + + tmp = 0; + videomode = 0x301; + /* get video mode via environment */ + if ((penv = getenv ("videomode")) != NULL) { + /* deceide if it is a string */ + if (penv[0] <= '9') { + videomode = (int) simple_strtoul (penv, NULL, 16); + tmp = 1; + } + } else { + tmp = 1; + } + if (tmp) { + /* parameter are vesa modes */ + /* search params */ + for (i = 0; i < VESA_MODES_COUNT; i++) { + if (vesa_modes[i].vesanr == videomode) + break; + } + if (i == VESA_MODES_COUNT) { + printf ("no VESA Mode found, switching to mode 0x301 "); + i = 0; + } + res_mode = + (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i]. + resindex]; + bits_per_pixel = vesa_modes[i].bits_per_pixel; + } else { + + res_mode = (struct ctfb_res_modes *) &var_mode; + bits_per_pixel = video_get_params (res_mode, penv); + } + + /* calculate available color depth for controller memory */ + if (bits_per_pixel == 15) + tmp = 2; + else + tmp = bits_per_pixel >> 3; /* /8 */ + if (((chips_param->max_mem - + ACCELMEMORY) / (res_mode->xres * res_mode->yres)) < tmp) { + tmp = + ((chips_param->max_mem - + ACCELMEMORY) / (res_mode->xres * res_mode->yres)); + if (tmp == 0) { + printf + ("No matching videomode found .-> reduce resolution\n"); + return NULL; + } else { + printf ("Switching back to %d Bits per Pixel ", + tmp << 3); + bits_per_pixel = tmp << 3; + } + } + + /* calculate hsynch and vsynch freq (info only) */ + t1 = (res_mode->left_margin + res_mode->xres + + res_mode->right_margin + res_mode->hsync_len) / 8; + t1 *= 8; + t1 *= res_mode->pixclock; + t1 /= 1000; + hsynch = 1000000000L / t1; + t1 *= + (res_mode->upper_margin + res_mode->yres + + res_mode->lower_margin + res_mode->vsync_len); + t1 /= 1000; + vsynch = 1000000000L / t1; + + /* fill in Graphic device struct */ + sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, + res_mode->yres, bits_per_pixel, (hsynch / 1000), + (vsynch / 1000)); + printf ("%s\n", pGD->modeIdent); + pGD->winSizeX = res_mode->xres; + pGD->winSizeY = res_mode->yres; + pGD->plnSizeX = res_mode->xres; + pGD->plnSizeY = res_mode->yres; + switch (bits_per_pixel) { + case 8: + pGD->gdfBytesPP = 1; + pGD->gdfIndex = GDF__8BIT_INDEX; + break; + case 15: + pGD->gdfBytesPP = 2; + pGD->gdfIndex = GDF_15BIT_555RGB; + break; + case 16: + pGD->gdfBytesPP = 2; + pGD->gdfIndex = GDF_16BIT_565RGB; + break; + case 24: + pGD->gdfBytesPP = 3; + pGD->gdfIndex = GDF_24BIT_888RGB; + break; + } + pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS; + pGD->pciBase = pci_mem_base; + pGD->frameAdrs = pci_mem_base; + pGD->memSize = chips_param->max_mem; + /* Cursor Start Address */ + pGD->dprBase = + (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + pci_mem_base; + if ((pGD->dprBase & 0x0fff) != 0) { + /* allign it */ + pGD->dprBase &= 0xfffff000; + pGD->dprBase += 0x00001000; + } + debug("Cursor Start %x Pattern Start %x\n", pGD->dprBase, + PATTERN_ADR); + pGD->vprBase = pci_mem_base; /* Dummy */ + pGD->cprBase = pci_mem_base; /* Dummy */ + /* set up Hardware */ + +#ifdef CONFIG_USE_CPCIDVI + if (device_id == PCI_DEVICE_ID_CT_69030) { + ctWrite (CT_MSR_W_O, 0x0b); + ctWrite (0x3cd, 0x13); + ctWrite_i (CT_FP_O, 0x02, 0x00); + ctWrite_i (CT_FP_O, 0x05, 0x00); + ctWrite_i (CT_FP_O, 0x06, 0x00); + ctWrite (0x3c2, 0x0b); + ctWrite_i (CT_FP_O, 0x02, 0x10); + ctWrite_i (CT_FP_O, 0x01, 0x09); + } else { + ctWrite (CT_MSR_W_O, 0x01); + } +#else + ctWrite (CT_MSR_W_O, 0x01); +#endif + + /* set the extended Registers */ + ctLoadRegs (CT_XR_O, xreg); + /* set atribute registers */ + SetArRegs (); + /* set Graphics register */ + SetGrRegs (); + /* set sequencer */ + SetSrRegs (); + + /* set msr */ + SetMsrRegs (res_mode); + + /* set CRT Registers */ + SetCrRegs (res_mode, bits_per_pixel); + /* set color mode */ + SetBitsPerPixelIntoXrRegs (bits_per_pixel); + + /* set PLL */ + FindAndSetPllParamIntoXrRegs (res_mode->pixclock, chips_param); + + ctWrite_i (CT_SR_O, 0, 0x03); /* clear synchronous reset */ + /* Clear video memory */ + i = pGD->memSize / 4; + vm = (unsigned int *) pGD->pciBase; + while (i--) + *vm++ = 0; + SetDrawingEngine (bits_per_pixel); +#ifdef VGA_DUMP_REG + video_dump_reg (); +#endif + + return ((void *) &ctfb); +} + + /******************************************************************************* +* +* Set a RGB color in the LUT (8 bit index) +*/ +void +video_set_lut (unsigned int index, /* color number */ + unsigned char r, /* red */ + unsigned char g, /* green */ + unsigned char b /* blue */ + ) +{ + + ctWrite (CT_LUT_MASK_O, 0xff); + + ctWrite (CT_LUT_START_O, (char) index); + + ctWrite (CT_LUT_RGB_O, r); /* red */ + ctWrite (CT_LUT_RGB_O, g); /* green */ + ctWrite (CT_LUT_RGB_O, b); /* blue */ + udelay (1); + ctWrite (CT_LUT_MASK_O, 0xff); +} + +/******************************************************************************* +* +* Drawing engine fill on screen region +*/ +void +video_hw_rectfill (unsigned int bpp, /* bytes per pixel */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y, /* frame height */ + unsigned int color /* fill color */ + ) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + unsigned long *p, br04; + + video_wait_bitblt (pGD->pciBase + BR04_o); + + p = (unsigned long *) PATTERN_ADR; + dim_x *= bpp; + if (bpp == 3) + bpp++; /* 24Bit needs a 32bit pattern */ + memset (p, color, (bpp * sizeof (unsigned char) * 8 * 8)); /* 8 x 8 pattern data */ + out32r (pGD->pciBase + BR07_o, ((pGD->winSizeX * dst_y) + dst_x) * pGD->gdfBytesPP); /* destination */ + br04 = in32r (pGD->pciBase + BR04_o) & 0xffffff00; + br04 |= 0xF0; /* write Pattern P -> D */ + out32r (pGD->pciBase + BR04_o, br04); /* */ + out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x); /* starts the BITBlt */ + video_wait_bitblt (pGD->pciBase + BR04_o); +} + +/******************************************************************************* +* +* Drawing engine bitblt with screen region +*/ +void +video_hw_bitblt (unsigned int bpp, /* bytes per pixel */ + unsigned int src_x, /* source pos x */ + unsigned int src_y, /* source pos y */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y /* frame height */ + ) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + unsigned long br04; + + br04 = in32r (pGD->pciBase + BR04_o); + + /* to prevent data corruption due to overlap, we have to + * find out if, and how the frames overlaps */ + if (src_x < dst_x) { + /* src is more left than dest + * the frame may overlap -> start from right to left */ + br04 |= 0x00000100; /* set bit 8 */ + src_x += dim_x; + dst_x += dim_x; + } else { + br04 &= 0xfffffeff; /* clear bit 8 left to right */ + } + if (src_y < dst_y) { + /* src is higher than dst + * the frame may overlap => start from bottom */ + br04 |= 0x00000200; /* set bit 9 */ + src_y += dim_y; + dst_y += dim_y; + } else { + br04 &= 0xfffffdff; /* clear bit 9 top to bottom */ + } + dim_x *= bpp; + out32r (pGD->pciBase + BR06_o, ((pGD->winSizeX * src_y) + src_x) * pGD->gdfBytesPP); /* source */ + out32r (pGD->pciBase + BR07_o, ((pGD->winSizeX * dst_y) + dst_x) * pGD->gdfBytesPP); /* destination */ + br04 &= 0xffffff00; + br04 |= 0x000000CC; /* S -> D */ + out32r (pGD->pciBase + BR04_o, br04); /* */ + out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x); /* start the BITBlt */ + video_wait_bitblt (pGD->pciBase + BR04_o); +} +#endif /* CONFIG_VIDEO */ diff --git a/qemu/roms/u-boot/drivers/video/da8xx-fb.c b/qemu/roms/u-boot/drivers/video/da8xx-fb.c new file mode 100644 index 000000000..3a5f325cd --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/da8xx-fb.c @@ -0,0 +1,1054 @@ +/* + * Porting to u-boot: + * + * (C) Copyright 2011 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * Copyright (C) 2008-2009 MontaVista Software Inc. + * Copyright (C) 2008-2009 Texas Instruments Inc + * + * Based on the LCD driver for TI Avalanche processors written by + * Ajay Singh and Shalom Hai. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <video_fb.h> +#include <linux/list.h> +#include <linux/fb.h> + +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +#include "videomodes.h" +#include "da8xx-fb.h" + +#if !defined(DA8XX_LCD_CNTL_BASE) +#define DA8XX_LCD_CNTL_BASE DAVINCI_LCD_CNTL_BASE +#endif + +#define DRIVER_NAME "da8xx_lcdc" + +#define LCD_VERSION_1 1 +#define LCD_VERSION_2 2 + +/* LCD Status Register */ +#define LCD_END_OF_FRAME1 (1 << 9) +#define LCD_END_OF_FRAME0 (1 << 8) +#define LCD_PL_LOAD_DONE (1 << 6) +#define LCD_FIFO_UNDERFLOW (1 << 5) +#define LCD_SYNC_LOST (1 << 2) + +/* LCD DMA Control Register */ +#define LCD_DMA_BURST_SIZE(x) ((x) << 4) +#define LCD_DMA_BURST_1 0x0 +#define LCD_DMA_BURST_2 0x1 +#define LCD_DMA_BURST_4 0x2 +#define LCD_DMA_BURST_8 0x3 +#define LCD_DMA_BURST_16 0x4 +#define LCD_V1_END_OF_FRAME_INT_ENA (1 << 2) +#define LCD_V2_END_OF_FRAME0_INT_ENA (1 << 8) +#define LCD_V2_END_OF_FRAME1_INT_ENA (1 << 9) +#define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0) + +#define LCD_V2_TFT_24BPP_MODE (1 << 25) +#define LCD_V2_TFT_24BPP_UNPACK (1 << 26) + +/* LCD Control Register */ +#define LCD_CLK_DIVISOR(x) ((x) << 8) +#define LCD_RASTER_MODE 0x01 + +/* LCD Raster Control Register */ +#define LCD_PALETTE_LOAD_MODE(x) ((x) << 20) +#define PALETTE_AND_DATA 0x00 +#define PALETTE_ONLY 0x01 +#define DATA_ONLY 0x02 + +#define LCD_MONO_8BIT_MODE (1 << 9) +#define LCD_RASTER_ORDER (1 << 8) +#define LCD_TFT_MODE (1 << 7) +#define LCD_V1_UNDERFLOW_INT_ENA (1 << 6) +#define LCD_V2_UNDERFLOW_INT_ENA (1 << 5) +#define LCD_V1_PL_INT_ENA (1 << 4) +#define LCD_V2_PL_INT_ENA (1 << 6) +#define LCD_MONOCHROME_MODE (1 << 1) +#define LCD_RASTER_ENABLE (1 << 0) +#define LCD_TFT_ALT_ENABLE (1 << 23) +#define LCD_STN_565_ENABLE (1 << 24) +#define LCD_V2_DMA_CLK_EN (1 << 2) +#define LCD_V2_LIDD_CLK_EN (1 << 1) +#define LCD_V2_CORE_CLK_EN (1 << 0) +#define LCD_V2_LPP_B10 26 +#define LCD_V2_TFT_24BPP_MODE (1 << 25) +#define LCD_V2_TFT_24BPP_UNPACK (1 << 26) + +/* LCD Raster Timing 2 Register */ +#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16) +#define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8) +#define LCD_SYNC_CTRL (1 << 25) +#define LCD_SYNC_EDGE (1 << 24) +#define LCD_INVERT_PIXEL_CLOCK (1 << 22) +#define LCD_INVERT_LINE_CLOCK (1 << 21) +#define LCD_INVERT_FRAME_CLOCK (1 << 20) + +/* Clock registers available only on Version 2 */ +#define LCD_CLK_MAIN_RESET (1 << 3) +/* LCD Block */ +struct da8xx_lcd_regs { + u32 revid; + u32 ctrl; + u32 stat; + u32 lidd_ctrl; + u32 lidd_cs0_conf; + u32 lidd_cs0_addr; + u32 lidd_cs0_data; + u32 lidd_cs1_conf; + u32 lidd_cs1_addr; + u32 lidd_cs1_data; + u32 raster_ctrl; + u32 raster_timing_0; + u32 raster_timing_1; + u32 raster_timing_2; + u32 raster_subpanel; + u32 reserved; + u32 dma_ctrl; + u32 dma_frm_buf_base_addr_0; + u32 dma_frm_buf_ceiling_addr_0; + u32 dma_frm_buf_base_addr_1; + u32 dma_frm_buf_ceiling_addr_1; + u32 resv1; + u32 raw_stat; + u32 masked_stat; + u32 int_ena_set; + u32 int_ena_clr; + u32 end_of_int_ind; + /* Clock registers available only on Version 2 */ + u32 clk_ena; + u32 clk_reset; +}; + +#define LCD_NUM_BUFFERS 1 + +#define WSI_TIMEOUT 50 +#define PALETTE_SIZE 256 +#define LEFT_MARGIN 64 +#define RIGHT_MARGIN 64 +#define UPPER_MARGIN 32 +#define LOWER_MARGIN 32 +#define WAIT_FOR_FRAME_DONE true +#define NO_WAIT_FOR_FRAME_DONE false + +#define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP) + +static struct da8xx_lcd_regs *da8xx_fb_reg_base; + +DECLARE_GLOBAL_DATA_PTR; + +/* graphics setup */ +static GraphicDevice gpanel; +static const struct da8xx_panel *lcd_panel; +static struct fb_info *da8xx_fb_info; +static int bits_x_pixel; +static unsigned int lcd_revision; +const struct lcd_ctrl_config *da8xx_lcd_cfg; + +static inline unsigned int lcdc_read(u32 *addr) +{ + return (unsigned int)readl(addr); +} + +static inline void lcdc_write(unsigned int val, u32 *addr) +{ + writel(val, addr); +} + +struct da8xx_fb_par { + u32 p_palette_base; + unsigned char *v_palette_base; + dma_addr_t vram_phys; + unsigned long vram_size; + void *vram_virt; + unsigned int dma_start; + unsigned int dma_end; + struct clk *lcdc_clk; + int irq; + unsigned short pseudo_palette[16]; + unsigned int palette_sz; + unsigned int pxl_clk; + int blank; + int vsync_flag; + int vsync_timeout; +}; + + +/* Variable Screen Information */ +static struct fb_var_screeninfo da8xx_fb_var = { + .xoffset = 0, + .yoffset = 0, + .transp = {0, 0, 0}, + .nonstd = 0, + .activate = 0, + .height = -1, + .width = -1, + .pixclock = 46666, /* 46us - AUO display */ + .accel_flags = 0, + .left_margin = LEFT_MARGIN, + .right_margin = RIGHT_MARGIN, + .upper_margin = UPPER_MARGIN, + .lower_margin = LOWER_MARGIN, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +}; + +static struct fb_fix_screeninfo da8xx_fb_fix = { + .id = "DA8xx FB Drv", + .type = FB_TYPE_PACKED_PIXELS, + .type_aux = 0, + .visual = FB_VISUAL_PSEUDOCOLOR, + .xpanstep = 0, + .ypanstep = 1, + .ywrapstep = 0, + .accel = FB_ACCEL_NONE +}; + +/* Enable the Raster Engine of the LCD Controller */ +static inline void lcd_enable_raster(void) +{ + u32 reg; + + /* Put LCDC in reset for several cycles */ + if (lcd_revision == LCD_VERSION_2) + lcdc_write(LCD_CLK_MAIN_RESET, + &da8xx_fb_reg_base->clk_reset); + + udelay(1000); + /* Bring LCDC out of reset */ + if (lcd_revision == LCD_VERSION_2) + lcdc_write(0, + &da8xx_fb_reg_base->clk_reset); + + udelay(1000); + + reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); + if (!(reg & LCD_RASTER_ENABLE)) + lcdc_write(reg | LCD_RASTER_ENABLE, + &da8xx_fb_reg_base->raster_ctrl); +} + +/* Disable the Raster Engine of the LCD Controller */ +static inline void lcd_disable_raster(bool wait_for_frame_done) +{ + u32 reg; + u32 loop_cnt = 0; + u32 stat; + u32 i = 0; + + if (wait_for_frame_done) + loop_cnt = 5000; + + reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); + if (reg & LCD_RASTER_ENABLE) + lcdc_write(reg & ~LCD_RASTER_ENABLE, + &da8xx_fb_reg_base->raster_ctrl); + + /* Wait for the current frame to complete */ + do { + if (lcd_revision == LCD_VERSION_1) + stat = lcdc_read(&da8xx_fb_reg_base->stat); + else + stat = lcdc_read(&da8xx_fb_reg_base->raw_stat); + + mdelay(1); + } while (!(stat & 0x01) && (i++ < loop_cnt)); + + if (lcd_revision == LCD_VERSION_1) + lcdc_write(stat, &da8xx_fb_reg_base->stat); + else + lcdc_write(stat, &da8xx_fb_reg_base->raw_stat); + + if ((loop_cnt != 0) && (i >= loop_cnt)) { + printf("LCD Controller timed out\n"); + return; + } +} + +static void lcd_blit(int load_mode, struct da8xx_fb_par *par) +{ + u32 start; + u32 end; + u32 reg_ras; + u32 reg_dma; + u32 reg_int; + + /* init reg to clear PLM (loading mode) fields */ + reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); + reg_ras &= ~(3 << 20); + + reg_dma = lcdc_read(&da8xx_fb_reg_base->dma_ctrl); + + if (load_mode == LOAD_DATA) { + start = par->dma_start; + end = par->dma_end; + + reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY); + if (lcd_revision == LCD_VERSION_1) { + reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA; + } else { + reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) | + LCD_V2_END_OF_FRAME0_INT_ENA | + LCD_V2_END_OF_FRAME1_INT_ENA | + LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST; + lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); + } + +#if (LCD_NUM_BUFFERS == 2) + reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE; + lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); + lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); + lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); + lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); +#else + reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE; + lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); + lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); + lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); + lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); +#endif + + } else if (load_mode == LOAD_PALETTE) { + start = par->p_palette_base; + end = start + par->palette_sz - 1; + + reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY); + if (lcd_revision == LCD_VERSION_1) { + reg_ras |= LCD_V1_PL_INT_ENA; + } else { + reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) | + LCD_V2_PL_INT_ENA; + lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); + } + + lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); + lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); + } + + lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl); + lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl); + + /* + * The Raster enable bit must be set after all other control fields are + * set. + */ + lcd_enable_raster(); +} + +/* Configure the Burst Size of DMA */ +static int lcd_cfg_dma(int burst_size) +{ + u32 reg; + + reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001; + switch (burst_size) { + case 1: + reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1); + break; + case 2: + reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2); + break; + case 4: + reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4); + break; + case 8: + reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8); + break; + case 16: + reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16); + break; + default: + return -EINVAL; + } + lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl); + + return 0; +} + +static void lcd_cfg_ac_bias(int period, int transitions_per_int) +{ + u32 reg; + + /* Set the AC Bias Period and Number of Transisitons per Interrupt */ + reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000; + reg |= LCD_AC_BIAS_FREQUENCY(period) | + LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int); + lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); +} + +static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width, + int front_porch) +{ + u32 reg; + + reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf; + reg |= ((back_porch & 0xff) << 24) + | ((front_porch & 0xff) << 16) + | ((pulse_width & 0x3f) << 10); + lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0); +} + +static void lcd_cfg_vertical_sync(int back_porch, int pulse_width, + int front_porch) +{ + u32 reg; + + reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff; + reg |= ((back_porch & 0xff) << 24) + | ((front_porch & 0xff) << 16) + | ((pulse_width & 0x3f) << 10); + lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1); +} + +static int lcd_cfg_display(const struct lcd_ctrl_config *cfg) +{ + u32 reg; + u32 reg_int; + + reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE | + LCD_MONO_8BIT_MODE | + LCD_MONOCHROME_MODE); + + switch (cfg->p_disp_panel->panel_shade) { + case MONOCHROME: + reg |= LCD_MONOCHROME_MODE; + if (cfg->mono_8bit_mode) + reg |= LCD_MONO_8BIT_MODE; + break; + case COLOR_ACTIVE: + reg |= LCD_TFT_MODE; + if (cfg->tft_alt_mode) + reg |= LCD_TFT_ALT_ENABLE; + break; + + case COLOR_PASSIVE: + if (cfg->stn_565_mode) + reg |= LCD_STN_565_ENABLE; + break; + + default: + return -EINVAL; + } + + /* enable additional interrupts here */ + if (lcd_revision == LCD_VERSION_1) { + reg |= LCD_V1_UNDERFLOW_INT_ENA; + } else { + reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) | + LCD_V2_UNDERFLOW_INT_ENA; + lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); + } + + lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl); + + reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2); + + if (cfg->sync_ctrl) + reg |= LCD_SYNC_CTRL; + else + reg &= ~LCD_SYNC_CTRL; + + if (cfg->sync_edge) + reg |= LCD_SYNC_EDGE; + else + reg &= ~LCD_SYNC_EDGE; + + if (cfg->invert_line_clock) + reg |= LCD_INVERT_LINE_CLOCK; + else + reg &= ~LCD_INVERT_LINE_CLOCK; + + if (cfg->invert_frm_clock) + reg |= LCD_INVERT_FRAME_CLOCK; + else + reg &= ~LCD_INVERT_FRAME_CLOCK; + + lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); + + return 0; +} + +static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, + u32 bpp, u32 raster_order) +{ + u32 reg; + + /* Set the Panel Width */ + /* Pixels per line = (PPL + 1)*16 */ + if (lcd_revision == LCD_VERSION_1) { + /* + * 0x3F in bits 4..9 gives max horisontal resolution = 1024 + * pixels + */ + width &= 0x3f0; + } else { + /* + * 0x7F in bits 4..10 gives max horizontal resolution = 2048 + * pixels. + */ + width &= 0x7f0; + } + reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0); + reg &= 0xfffffc00; + if (lcd_revision == LCD_VERSION_1) { + reg |= ((width >> 4) - 1) << 4; + } else { + width = (width >> 4) - 1; + reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3); + } + lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0); + + /* Set the Panel Height */ + /* Set bits 9:0 of Lines Per Pixel */ + reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1); + reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00); + lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1); + + /* Set bit 10 of Lines Per Pixel */ + if (lcd_revision == LCD_VERSION_2) { + reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2); + reg |= ((height - 1) & 0x400) << 16; + lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); + } + + /* Set the Raster Order of the Frame Buffer */ + reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8); + if (raster_order) + reg |= LCD_RASTER_ORDER; + + if (bpp == 24) + reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE); + else if (bpp == 32) + reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE + | LCD_V2_TFT_24BPP_UNPACK); + + lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl); + + switch (bpp) { + case 1: + case 2: + case 4: + case 16: + case 24: + case 32: + par->palette_sz = 16 * 2; + break; + + case 8: + par->palette_sz = 256 * 2; + break; + + default: + return -EINVAL; + } + + return 0; +} + +static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, + unsigned blue, unsigned transp, + struct fb_info *info) +{ + struct da8xx_fb_par *par = info->par; + unsigned short *palette = (unsigned short *) par->v_palette_base; + u_short pal; + int update_hw = 0; + + if (regno > 255) + return 1; + + if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) + return 1; + + if (info->var.bits_per_pixel == 8) { + red >>= 4; + green >>= 8; + blue >>= 12; + + pal = (red & 0x0f00); + pal |= (green & 0x00f0); + pal |= (blue & 0x000f); + + if (palette[regno] != pal) { + update_hw = 1; + palette[regno] = pal; + } + } else if ((info->var.bits_per_pixel == 16) && regno < 16) { + red >>= (16 - info->var.red.length); + red <<= info->var.red.offset; + + green >>= (16 - info->var.green.length); + green <<= info->var.green.offset; + + blue >>= (16 - info->var.blue.length); + blue <<= info->var.blue.offset; + + par->pseudo_palette[regno] = red | green | blue; + + if (palette[0] != 0x4000) { + update_hw = 1; + palette[0] = 0x4000; + } + } else if (((info->var.bits_per_pixel == 32) && regno < 32) || + ((info->var.bits_per_pixel == 24) && regno < 24)) { + red >>= (24 - info->var.red.length); + red <<= info->var.red.offset; + + green >>= (24 - info->var.green.length); + green <<= info->var.green.offset; + + blue >>= (24 - info->var.blue.length); + blue <<= info->var.blue.offset; + + par->pseudo_palette[regno] = red | green | blue; + + if (palette[0] != 0x4000) { + update_hw = 1; + palette[0] = 0x4000; + } + } + + /* Update the palette in the h/w as needed. */ + if (update_hw) + lcd_blit(LOAD_PALETTE, par); + + return 0; +} + +static void lcd_reset(struct da8xx_fb_par *par) +{ + /* Disable the Raster if previously Enabled */ + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); + + /* DMA has to be disabled */ + lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl); + lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl); + + if (lcd_revision == LCD_VERSION_2) { + lcdc_write(0, &da8xx_fb_reg_base->int_ena_set); + /* Write 1 to reset */ + lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset); + lcdc_write(0, &da8xx_fb_reg_base->clk_reset); + } +} + +static void lcd_calc_clk_divider(struct da8xx_fb_par *par) +{ + unsigned int lcd_clk, div; + + /* Get clock from sysclk2 */ + lcd_clk = clk_get(2); + + div = lcd_clk / par->pxl_clk; + debug("LCD Clock: %d Divider: %d PixClk: %d\n", + lcd_clk, div, par->pxl_clk); + + /* Configure the LCD clock divisor. */ + lcdc_write(LCD_CLK_DIVISOR(div) | + (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl); + + if (lcd_revision == LCD_VERSION_2) + lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN | + LCD_V2_CORE_CLK_EN, + &da8xx_fb_reg_base->clk_ena); +} + +static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, + const struct da8xx_panel *panel) +{ + u32 bpp; + int ret = 0; + + lcd_reset(par); + + /* Calculate the divider */ + lcd_calc_clk_divider(par); + + if (panel->invert_pxl_clk) + lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) | + LCD_INVERT_PIXEL_CLOCK), + &da8xx_fb_reg_base->raster_timing_2); + else + lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & + ~LCD_INVERT_PIXEL_CLOCK), + &da8xx_fb_reg_base->raster_timing_2); + + /* Configure the DMA burst size. */ + ret = lcd_cfg_dma(cfg->dma_burst_sz); + if (ret < 0) + return ret; + + /* Configure the AC bias properties. */ + lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt); + + /* Configure the vertical and horizontal sync properties. */ + lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp); + lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp); + + /* Configure for disply */ + ret = lcd_cfg_display(cfg); + if (ret < 0) + return ret; + + if ((QVGA != cfg->p_disp_panel->panel_type) && + (WVGA != cfg->p_disp_panel->panel_type)) + return -EINVAL; + + if (cfg->bpp <= cfg->p_disp_panel->max_bpp && + cfg->bpp >= cfg->p_disp_panel->min_bpp) + bpp = cfg->bpp; + else + bpp = cfg->p_disp_panel->max_bpp; + if (bpp == 12) + bpp = 16; + ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width, + (unsigned int)panel->height, bpp, + cfg->raster_order); + if (ret < 0) + return ret; + + /* Configure FDD */ + lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) | + (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl); + + return 0; +} + +static void lcdc_dma_start(void) +{ + struct da8xx_fb_par *par = da8xx_fb_info->par; + lcdc_write(par->dma_start, + &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); + lcdc_write(par->dma_end, + &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); + lcdc_write(0, + &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); + lcdc_write(0, + &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); +} + +static u32 lcdc_irq_handler_rev01(void) +{ + struct da8xx_fb_par *par = da8xx_fb_info->par; + u32 stat = lcdc_read(&da8xx_fb_reg_base->stat); + u32 reg_ras; + + if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { + debug("LCD_SYNC_LOST\n"); + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); + lcdc_write(stat, &da8xx_fb_reg_base->stat); + lcd_enable_raster(); + return LCD_SYNC_LOST; + } else if (stat & LCD_PL_LOAD_DONE) { + debug("LCD_PL_LOAD_DONE\n"); + /* + * Must disable raster before changing state of any control bit. + * And also must be disabled before clearing the PL loading + * interrupt via the following write to the status register. If + * this is done after then one gets multiple PL done interrupts. + */ + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); + + lcdc_write(stat, &da8xx_fb_reg_base->stat); + + /* Disable PL completion inerrupt */ + reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); + reg_ras &= ~LCD_V1_PL_INT_ENA; + lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl); + + /* Setup and start data loading mode */ + lcd_blit(LOAD_DATA, par); + return LCD_PL_LOAD_DONE; + } else { + lcdc_write(stat, &da8xx_fb_reg_base->stat); + + if (stat & LCD_END_OF_FRAME0) + debug("LCD_END_OF_FRAME0\n"); + + lcdc_write(par->dma_start, + &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); + lcdc_write(par->dma_end, + &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); + par->vsync_flag = 1; + return LCD_END_OF_FRAME0; + } + return stat; +} + +static u32 lcdc_irq_handler_rev02(void) +{ + struct da8xx_fb_par *par = da8xx_fb_info->par; + u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat); + u32 reg_int; + + if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { + debug("LCD_SYNC_LOST\n"); + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); + lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); + lcd_enable_raster(); + lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); + return LCD_SYNC_LOST; + } else if (stat & LCD_PL_LOAD_DONE) { + debug("LCD_PL_LOAD_DONE\n"); + /* + * Must disable raster before changing state of any control bit. + * And also must be disabled before clearing the PL loading + * interrupt via the following write to the status register. If + * this is done after then one gets multiple PL done interrupts. + */ + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); + + lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); + + /* Disable PL completion inerrupt */ + reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) | + (LCD_V2_PL_INT_ENA); + lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr); + + /* Setup and start data loading mode */ + lcd_blit(LOAD_DATA, par); + lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); + return LCD_PL_LOAD_DONE; + } else { + lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); + + if (stat & LCD_END_OF_FRAME0) + debug("LCD_END_OF_FRAME0\n"); + + lcdc_write(par->dma_start, + &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); + lcdc_write(par->dma_end, + &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); + par->vsync_flag = 1; + lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); + return LCD_END_OF_FRAME0; + } + lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); + return stat; +} + +static u32 lcdc_irq_handler(void) +{ + if (lcd_revision == LCD_VERSION_1) + return lcdc_irq_handler_rev01(); + else + return lcdc_irq_handler_rev02(); +} + +static u32 wait_for_event(u32 event) +{ + u32 timeout = 50000; + u32 ret; + + do { + ret = lcdc_irq_handler(); + udelay(1000); + } while (!(ret & event)); + + if (timeout <= 0) { + printf("%s: event %d not hit\n", __func__, event); + return -1; + } + + return 0; + +} + +void *video_hw_init(void) +{ + struct da8xx_fb_par *par; + u32 size; + u32 rev; + char *p; + + if (!lcd_panel) { + printf("Display not initialized\n"); + return NULL; + } + gpanel.winSizeX = lcd_panel->width; + gpanel.winSizeY = lcd_panel->height; + gpanel.plnSizeX = lcd_panel->width; + gpanel.plnSizeY = lcd_panel->height; + + switch (bits_x_pixel) { + case 32: + gpanel.gdfBytesPP = 4; + gpanel.gdfIndex = GDF_32BIT_X888RGB; + break; + case 24: + gpanel.gdfBytesPP = 4; + gpanel.gdfIndex = GDF_32BIT_X888RGB; + break; + case 16: + gpanel.gdfBytesPP = 2; + gpanel.gdfIndex = GDF_16BIT_565RGB; + break; + default: + gpanel.gdfBytesPP = 1; + gpanel.gdfIndex = GDF__8BIT_INDEX; + break; + } + + da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DA8XX_LCD_CNTL_BASE; + + /* Determine LCD IP Version */ + rev = lcdc_read(&da8xx_fb_reg_base->revid); + switch (rev) { + case 0x4C100102: + lcd_revision = LCD_VERSION_1; + break; + case 0x4F200800: + case 0x4F201000: + lcd_revision = LCD_VERSION_2; + break; + default: + printf("Unknown PID Reg value 0x%x, defaulting to LCD revision 1\n", + rev); + lcd_revision = LCD_VERSION_1; + break; + } + + debug("rev: 0x%x Resolution: %dx%d %d\n", rev, + gpanel.winSizeX, + gpanel.winSizeY, + da8xx_lcd_cfg->bpp); + + size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par); + da8xx_fb_info = malloc(size); + debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info); + + if (!da8xx_fb_info) { + printf("Memory allocation failed for fb_info\n"); + return NULL; + } + memset(da8xx_fb_info, 0, size); + p = (char *)da8xx_fb_info; + da8xx_fb_info->par = p + sizeof(struct fb_info); + debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par); + + par = da8xx_fb_info->par; + par->pxl_clk = lcd_panel->pxl_clk; + + if (lcd_init(par, da8xx_lcd_cfg, lcd_panel) < 0) { + printf("lcd_init failed\n"); + goto err_release_fb; + } + + /* allocate frame buffer */ + par->vram_size = lcd_panel->width * lcd_panel->height * + da8xx_lcd_cfg->bpp; + par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8; + + par->vram_virt = malloc(par->vram_size); + + par->vram_phys = (dma_addr_t) par->vram_virt; + debug("Requesting 0x%x bytes for framebuffer at 0x%x\n", + (unsigned int)par->vram_size, + (unsigned int)par->vram_virt); + if (!par->vram_virt) { + printf("GLCD: malloc for frame buffer failed\n"); + goto err_release_fb; + } + gd->fb_base = (int)par->vram_virt; + + gpanel.frameAdrs = (unsigned int)par->vram_virt; + da8xx_fb_info->screen_base = (char *) par->vram_virt; + da8xx_fb_fix.smem_start = gpanel.frameAdrs; + da8xx_fb_fix.smem_len = par->vram_size; + da8xx_fb_fix.line_length = (lcd_panel->width * da8xx_lcd_cfg->bpp) / 8; + + par->dma_start = par->vram_phys; + par->dma_end = par->dma_start + lcd_panel->height * + da8xx_fb_fix.line_length - 1; + + /* allocate palette buffer */ + par->v_palette_base = malloc(PALETTE_SIZE); + if (!par->v_palette_base) { + printf("GLCD: malloc for palette buffer failed\n"); + goto err_release_fb_mem; + } + memset(par->v_palette_base, 0, PALETTE_SIZE); + par->p_palette_base = (unsigned int)par->v_palette_base; + + /* Initialize par */ + da8xx_fb_info->var.bits_per_pixel = da8xx_lcd_cfg->bpp; + + da8xx_fb_var.xres = lcd_panel->width; + da8xx_fb_var.xres_virtual = lcd_panel->width; + + da8xx_fb_var.yres = lcd_panel->height; + da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS; + + da8xx_fb_var.grayscale = + da8xx_lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0; + da8xx_fb_var.bits_per_pixel = da8xx_lcd_cfg->bpp; + + da8xx_fb_var.hsync_len = lcd_panel->hsw; + da8xx_fb_var.vsync_len = lcd_panel->vsw; + + /* Initialize fbinfo */ + da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT; + da8xx_fb_info->fix = da8xx_fb_fix; + da8xx_fb_info->var = da8xx_fb_var; + da8xx_fb_info->pseudo_palette = par->pseudo_palette; + da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ? + FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; + + /* Clear interrupt */ + memset((void *)par->vram_virt, 0, par->vram_size); + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE); + if (lcd_revision == LCD_VERSION_1) + lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat); + else + lcdc_write(0xFFFF, &da8xx_fb_reg_base->masked_stat); + debug("Palette at 0x%x size %d\n", par->p_palette_base, + par->palette_sz); + lcdc_dma_start(); + + /* Load a default palette */ + fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info); + + /* Check that the palette is loaded */ + wait_for_event(LCD_PL_LOAD_DONE); + + /* Wait until DMA is working */ + wait_for_event(LCD_END_OF_FRAME0); + + return (void *)&gpanel; + +err_release_fb_mem: + free(par->vram_virt); + +err_release_fb: + free(da8xx_fb_info); + + return NULL; +} + +void video_set_lut(unsigned int index, /* color number */ + unsigned char r, /* red */ + unsigned char g, /* green */ + unsigned char b /* blue */ + ) +{ + + return; +} + +void da8xx_video_init(const struct da8xx_panel *panel, + const struct lcd_ctrl_config *lcd_cfg, int bits_pixel) +{ + lcd_panel = panel; + da8xx_lcd_cfg = lcd_cfg; + bits_x_pixel = bits_pixel; +} diff --git a/qemu/roms/u-boot/drivers/video/da8xx-fb.h b/qemu/roms/u-boot/drivers/video/da8xx-fb.h new file mode 100644 index 000000000..6447a4047 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/da8xx-fb.h @@ -0,0 +1,116 @@ +/* + * Porting to u-boot: + * + * (C) Copyright 2011 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * Copyright (C) 2008-2009 MontaVista Software Inc. + * Copyright (C) 2008-2009 Texas Instruments Inc + * + * Based on the LCD driver for TI Avalanche processors written by + * Ajay Singh and Shalom Hai. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef DA8XX_FB_H +#define DA8XX_FB_H + +enum panel_type { + QVGA = 0, + WVGA +}; + +enum panel_shade { + MONOCHROME = 0, + COLOR_ACTIVE, + COLOR_PASSIVE, +}; + +enum raster_load_mode { + LOAD_DATA = 1, + LOAD_PALETTE, +}; + +struct display_panel { + enum panel_type panel_type; /* QVGA */ + int max_bpp; + int min_bpp; + enum panel_shade panel_shade; +}; + +struct da8xx_panel { + const char name[25]; /* Full name <vendor>_<model> */ + unsigned short width; + unsigned short height; + int hfp; /* Horizontal front porch */ + int hbp; /* Horizontal back porch */ + int hsw; /* Horizontal Sync Pulse Width */ + int vfp; /* Vertical front porch */ + int vbp; /* Vertical back porch */ + int vsw; /* Vertical Sync Pulse Width */ + unsigned int pxl_clk; /* Pixel clock */ + unsigned char invert_pxl_clk; /* Invert Pixel clock */ +}; + +struct da8xx_lcdc_platform_data { + const char manu_name[10]; + void *controller_data; + const char type[25]; + void (*panel_power_ctrl)(int); +}; + +struct lcd_ctrl_config { + const struct display_panel *p_disp_panel; + + /* AC Bias Pin Frequency */ + int ac_bias; + + /* AC Bias Pin Transitions per Interrupt */ + int ac_bias_intrpt; + + /* DMA burst size */ + int dma_burst_sz; + + /* Bits per pixel */ + int bpp; + + /* FIFO DMA Request Delay */ + int fdd; + + /* TFT Alternative Signal Mapping (Only for active) */ + unsigned char tft_alt_mode; + + /* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */ + unsigned char stn_565_mode; + + /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */ + unsigned char mono_8bit_mode; + + /* Invert line clock */ + unsigned char invert_line_clock; + + /* Invert frame clock */ + unsigned char invert_frm_clock; + + /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */ + unsigned char sync_edge; + + /* Horizontal and Vertical Sync: Control: 0=ignore */ + unsigned char sync_ctrl; + + /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */ + unsigned char raster_order; +}; + +struct lcd_sync_arg { + int back_porch; + int front_porch; + int pulse_width; +}; + +void da8xx_video_init(const struct da8xx_panel *panel, + const struct lcd_ctrl_config *lcd_cfg, + int bits_pixel); + +#endif /* ifndef DA8XX_FB_H */ diff --git a/qemu/roms/u-boot/drivers/video/exynos_dp.c b/qemu/roms/u-boot/drivers/video/exynos_dp.c new file mode 100644 index 000000000..682483fc3 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/exynos_dp.c @@ -0,0 +1,982 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <malloc.h> +#include <linux/err.h> +#include <asm/arch/clk.h> +#include <asm/arch/cpu.h> +#include <asm/arch/dp_info.h> +#include <asm/arch/dp.h> +#include <fdtdec.h> +#include <libfdt.h> + +#include "exynos_dp_lowlevel.h" + +DECLARE_GLOBAL_DATA_PTR; + +static struct exynos_dp_platform_data *dp_pd; + +void __exynos_set_dp_phy(unsigned int onoff) +{ +} +void exynos_set_dp_phy(unsigned int onoff) + __attribute__((weak, alias("__exynos_set_dp_phy"))); + +static void exynos_dp_disp_info(struct edp_disp_info *disp_info) +{ + disp_info->h_total = disp_info->h_res + disp_info->h_sync_width + + disp_info->h_back_porch + disp_info->h_front_porch; + disp_info->v_total = disp_info->v_res + disp_info->v_sync_width + + disp_info->v_back_porch + disp_info->v_front_porch; + + return; +} + +static int exynos_dp_init_dp(void) +{ + int ret; + exynos_dp_reset(); + + /* SW defined function Normal operation */ + exynos_dp_enable_sw_func(DP_ENABLE); + + ret = exynos_dp_init_analog_func(); + if (ret != EXYNOS_DP_SUCCESS) + return ret; + + exynos_dp_init_hpd(); + exynos_dp_init_aux(); + + return ret; +} + +static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data) +{ + int i; + unsigned char sum = 0; + + for (i = 0; i < EDID_BLOCK_LENGTH; i++) + sum = sum + edid_data[i]; + + return sum; +} + +static unsigned int exynos_dp_read_edid(void) +{ + unsigned char edid[EDID_BLOCK_LENGTH * 2]; + unsigned int extend_block = 0; + unsigned char sum; + unsigned char test_vector; + int retval; + + /* + * EDID device address is 0x50. + * However, if necessary, you must have set upper address + * into E-EDID in I2C device, 0x30. + */ + + /* Read Extension Flag, Number of 128-byte EDID extension blocks */ + exynos_dp_read_byte_from_i2c(I2C_EDID_DEVICE_ADDR, EDID_EXTENSION_FLAG, + &extend_block); + + if (extend_block > 0) { + printf("DP EDID data includes a single extension!\n"); + + /* Read EDID data */ + retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR, + EDID_HEADER_PATTERN, + EDID_BLOCK_LENGTH, + &edid[EDID_HEADER_PATTERN]); + if (retval != 0) { + printf("DP EDID Read failed!\n"); + return -1; + } + sum = exynos_dp_calc_edid_check_sum(edid); + if (sum != 0) { + printf("DP EDID bad checksum!\n"); + return -1; + } + + /* Read additional EDID data */ + retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR, + EDID_BLOCK_LENGTH, + EDID_BLOCK_LENGTH, + &edid[EDID_BLOCK_LENGTH]); + if (retval != 0) { + printf("DP EDID Read failed!\n"); + return -1; + } + sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]); + if (sum != 0) { + printf("DP EDID bad checksum!\n"); + return -1; + } + + exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST, + &test_vector); + if (test_vector & DPCD_TEST_EDID_READ) { + exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM, + edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); + exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE, + DPCD_TEST_EDID_CHECKSUM_WRITE); + } + } else { + debug("DP EDID data does not include any extensions.\n"); + + /* Read EDID data */ + retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR, + EDID_HEADER_PATTERN, + EDID_BLOCK_LENGTH, + &edid[EDID_HEADER_PATTERN]); + + if (retval != 0) { + printf("DP EDID Read failed!\n"); + return -1; + } + sum = exynos_dp_calc_edid_check_sum(edid); + if (sum != 0) { + printf("DP EDID bad checksum!\n"); + return -1; + } + + exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST, + &test_vector); + if (test_vector & DPCD_TEST_EDID_READ) { + exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM, + edid[EDID_CHECKSUM]); + exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE, + DPCD_TEST_EDID_CHECKSUM_WRITE); + } + } + + debug("DP EDID Read success!\n"); + + return 0; +} + +static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info) +{ + unsigned char buf[12]; + unsigned int ret; + unsigned char temp; + unsigned char retry_cnt; + unsigned char dpcd_rev[16]; + unsigned char lane_bw[16]; + unsigned char lane_cnt[16]; + + memset(dpcd_rev, 0, 16); + memset(lane_bw, 0, 16); + memset(lane_cnt, 0, 16); + memset(buf, 0, 12); + + retry_cnt = 5; + while (retry_cnt) { + /* Read DPCD 0x0000-0x000b */ + ret = exynos_dp_read_bytes_from_dpcd(DPCD_DPCD_REV, 12, + buf); + if (ret != EXYNOS_DP_SUCCESS) { + if (retry_cnt == 0) { + printf("DP read_byte_from_dpcd() failed\n"); + return ret; + } + retry_cnt--; + } else + break; + } + + /* */ + temp = buf[DPCD_DPCD_REV]; + if (temp == DP_DPCD_REV_10 || temp == DP_DPCD_REV_11) + edp_info->dpcd_rev = temp; + else { + printf("DP Wrong DPCD Rev : %x\n", temp); + return -ENODEV; + } + + temp = buf[DPCD_MAX_LINK_RATE]; + if (temp == DP_LANE_BW_1_62 || temp == DP_LANE_BW_2_70) + edp_info->lane_bw = temp; + else { + printf("DP Wrong MAX LINK RATE : %x\n", temp); + return -EINVAL; + } + + /*Refer VESA Display Port Stnadard Ver1.1a Page 120 */ + if (edp_info->dpcd_rev == DP_DPCD_REV_11) { + temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f; + if (buf[DPCD_MAX_LANE_COUNT] & 0x80) + edp_info->dpcd_efc = 1; + else + edp_info->dpcd_efc = 0; + } else { + temp = buf[DPCD_MAX_LANE_COUNT]; + edp_info->dpcd_efc = 0; + } + + if (temp == DP_LANE_CNT_1 || temp == DP_LANE_CNT_2 || + temp == DP_LANE_CNT_4) { + edp_info->lane_cnt = temp; + } else { + printf("DP Wrong MAX LANE COUNT : %x\n", temp); + return -EINVAL; + } + + ret = exynos_dp_read_edid(); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP exynos_dp_read_edid() failed\n"); + return -EINVAL; + } + + return ret; +} + +static void exynos_dp_init_training(void) +{ + /* + * MACRO_RST must be applied after the PLL_LOCK to avoid + * the DP inter pair skew issue for at least 10 us + */ + exynos_dp_reset_macro(); + + /* All DP analog module power up */ + exynos_dp_set_analog_power_down(POWER_ALL, 0); +} + +static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info) +{ + unsigned char buf[5]; + unsigned int ret = 0; + + debug("DP: %s was called\n", __func__); + + edp_info->lt_info.lt_status = DP_LT_CR; + edp_info->lt_info.ep_loop = 0; + edp_info->lt_info.cr_loop[0] = 0; + edp_info->lt_info.cr_loop[1] = 0; + edp_info->lt_info.cr_loop[2] = 0; + edp_info->lt_info.cr_loop[3] = 0; + + /* Set sink to D0 (Sink Not Ready) mode. */ + ret = exynos_dp_write_byte_to_dpcd(DPCD_SINK_POWER_STATE, + DPCD_SET_POWER_STATE_D0); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP write_dpcd_byte failed\n"); + return ret; + } + + /* Set link rate and count as you want to establish*/ + exynos_dp_set_link_bandwidth(edp_info->lane_bw); + exynos_dp_set_lane_count(edp_info->lane_cnt); + + /* Setup RX configuration */ + buf[0] = edp_info->lane_bw; + buf[1] = edp_info->lane_cnt; + + ret = exynos_dp_write_bytes_to_dpcd(DPCD_LINK_BW_SET, 2, + buf); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP write_dpcd_byte failed\n"); + return ret; + } + + exynos_dp_set_lane_pre_emphasis(PRE_EMPHASIS_LEVEL_0, + edp_info->lane_cnt); + + /* Set training pattern 1 */ + exynos_dp_set_training_pattern(TRAINING_PTN1); + + /* Set RX training pattern */ + buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1; + + buf[1] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | + DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; + buf[2] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | + DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; + buf[3] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | + DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; + buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | + DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; + + ret = exynos_dp_write_bytes_to_dpcd(DPCD_TRAINING_PATTERN_SET, + 5, buf); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP write_dpcd_byte failed\n"); + return ret; + } + + return ret; +} + +static unsigned int exynos_dp_training_pattern_dis(void) +{ + unsigned int ret = EXYNOS_DP_SUCCESS; + + exynos_dp_set_training_pattern(DP_NONE); + + ret = exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET, + DPCD_TRAINING_PATTERN_DISABLED); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP requst_link_traninig_req failed\n"); + return -EAGAIN; + } + + return ret; +} + +static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable) +{ + unsigned char data; + unsigned int ret = EXYNOS_DP_SUCCESS; + + ret = exynos_dp_read_byte_from_dpcd(DPCD_LANE_COUNT_SET, + &data); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP read_from_dpcd failed\n"); + return -EAGAIN; + } + + if (enable) + data = DPCD_ENHANCED_FRAME_EN | DPCD_LN_COUNT_SET(data); + else + data = DPCD_LN_COUNT_SET(data); + + ret = exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET, + data); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP write_to_dpcd failed\n"); + return -EAGAIN; + + } + + return ret; +} + +static unsigned int exynos_dp_set_enhanced_mode(unsigned char enhance_mode) +{ + unsigned int ret = EXYNOS_DP_SUCCESS; + + ret = exynos_dp_enable_rx_to_enhanced_mode(enhance_mode); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP rx_enhance_mode failed\n"); + return -EAGAIN; + } + + exynos_dp_enable_enhanced_mode(enhance_mode); + + return ret; +} + +static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info *edp_info, + unsigned char *status) +{ + unsigned int ret, i; + unsigned char buf[2]; + unsigned char lane_stat[DP_LANE_CNT_4] = {0,}; + unsigned char shift_val[DP_LANE_CNT_4] = {0,}; + + shift_val[0] = 0; + shift_val[1] = 4; + shift_val[2] = 0; + shift_val[3] = 4; + + ret = exynos_dp_read_bytes_from_dpcd(DPCD_LANE0_1_STATUS, 2, buf); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP read lane status failed\n"); + return ret; + } + + for (i = 0; i < edp_info->lane_cnt; i++) { + lane_stat[i] = (buf[(i / 2)] >> shift_val[i]) & 0x0f; + if (lane_stat[0] != lane_stat[i]) { + printf("Wrong lane status\n"); + return -EINVAL; + } + } + + *status = lane_stat[0]; + + return ret; +} + +static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num, + unsigned char *sw, unsigned char *em) +{ + unsigned int ret = EXYNOS_DP_SUCCESS; + unsigned char buf; + unsigned int dpcd_addr; + unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4}; + + /*lane_num value is used as arry index, so this range 0 ~ 3 */ + dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2); + + ret = exynos_dp_read_byte_from_dpcd(dpcd_addr, &buf); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP read adjust request failed\n"); + return -EAGAIN; + } + + *sw = ((buf >> shift_val[lane_num]) & 0x03); + *em = ((buf >> shift_val[lane_num]) & 0x0c) >> 2; + + return ret; +} + +static int exynos_dp_equalizer_err_link(struct edp_device_info *edp_info) +{ + int ret; + + ret = exynos_dp_training_pattern_dis(); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP training_patter_disable() failed\n"); + edp_info->lt_info.lt_status = DP_LT_FAIL; + } + + ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP set_enhanced_mode() failed\n"); + edp_info->lt_info.lt_status = DP_LT_FAIL; + } + + return ret; +} + +static int exynos_dp_reduce_link_rate(struct edp_device_info *edp_info) +{ + int ret; + + if (edp_info->lane_bw == DP_LANE_BW_2_70) { + edp_info->lane_bw = DP_LANE_BW_1_62; + printf("DP Change lane bw to 1.62Gbps\n"); + edp_info->lt_info.lt_status = DP_LT_START; + ret = EXYNOS_DP_SUCCESS; + } else { + ret = exynos_dp_training_pattern_dis(); + if (ret != EXYNOS_DP_SUCCESS) + printf("DP training_patter_disable() failed\n"); + + ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc); + if (ret != EXYNOS_DP_SUCCESS) + printf("DP set_enhanced_mode() failed\n"); + + edp_info->lt_info.lt_status = DP_LT_FAIL; + } + + return ret; +} + +static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info + *edp_info) +{ + unsigned int ret = EXYNOS_DP_SUCCESS; + unsigned char lane_stat; + unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, }; + unsigned int i; + unsigned char adj_req_sw; + unsigned char adj_req_em; + unsigned char buf[5]; + + debug("DP: %s was called\n", __func__); + mdelay(1); + + ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP read lane status failed\n"); + edp_info->lt_info.lt_status = DP_LT_FAIL; + return ret; + } + + if (lane_stat & DP_LANE_STAT_CR_DONE) { + debug("DP clock Recovery training succeed\n"); + exynos_dp_set_training_pattern(TRAINING_PTN2); + + for (i = 0; i < edp_info->lane_cnt; i++) { + ret = exynos_dp_read_dpcd_adj_req(i, &adj_req_sw, + &adj_req_em); + if (ret != EXYNOS_DP_SUCCESS) { + edp_info->lt_info.lt_status = DP_LT_FAIL; + return ret; + } + + lt_ctl_val[i] = 0; + lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw; + + if ((adj_req_sw == VOLTAGE_LEVEL_3) + || (adj_req_em == PRE_EMPHASIS_LEVEL_3)) { + lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 | + MAX_PRE_EMPHASIS_REACH_3; + } + exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i); + } + + buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2; + buf[1] = lt_ctl_val[0]; + buf[2] = lt_ctl_val[1]; + buf[3] = lt_ctl_val[2]; + buf[4] = lt_ctl_val[3]; + + ret = exynos_dp_write_bytes_to_dpcd( + DPCD_TRAINING_PATTERN_SET, 5, buf); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP write traning pattern1 failed\n"); + edp_info->lt_info.lt_status = DP_LT_FAIL; + return ret; + } else + edp_info->lt_info.lt_status = DP_LT_ET; + } else { + for (i = 0; i < edp_info->lane_cnt; i++) { + lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(i); + ret = exynos_dp_read_dpcd_adj_req(i, + &adj_req_sw, &adj_req_em); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP read adj req failed\n"); + edp_info->lt_info.lt_status = DP_LT_FAIL; + return ret; + } + + if ((adj_req_sw == VOLTAGE_LEVEL_3) || + (adj_req_em == PRE_EMPHASIS_LEVEL_3)) + ret = exynos_dp_reduce_link_rate(edp_info); + + if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) == + adj_req_sw) && + (PRE_EMPHASIS_SET_0_GET(lt_ctl_val[i]) == + adj_req_em)) { + edp_info->lt_info.cr_loop[i]++; + if (edp_info->lt_info.cr_loop[i] == MAX_CR_LOOP) + ret = exynos_dp_reduce_link_rate( + edp_info); + } + + lt_ctl_val[i] = 0; + lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw; + + if ((adj_req_sw == VOLTAGE_LEVEL_3) || + (adj_req_em == PRE_EMPHASIS_LEVEL_3)) { + lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 | + MAX_PRE_EMPHASIS_REACH_3; + } + exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i); + } + + ret = exynos_dp_write_bytes_to_dpcd( + DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP write traning pattern2 failed\n"); + edp_info->lt_info.lt_status = DP_LT_FAIL; + return ret; + } + } + + return ret; +} + +static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info + *edp_info) +{ + unsigned int ret = EXYNOS_DP_SUCCESS; + unsigned char lane_stat, adj_req_sw, adj_req_em, i; + unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,}; + unsigned char interlane_aligned = 0; + unsigned char f_bw; + unsigned char f_lane_cnt; + unsigned char sink_stat; + + mdelay(1); + + ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP read lane status failed\n"); + edp_info->lt_info.lt_status = DP_LT_FAIL; + return ret; + } + + debug("DP lane stat : %x\n", lane_stat); + + if (lane_stat & DP_LANE_STAT_CR_DONE) { + ret = exynos_dp_read_byte_from_dpcd(DPCD_LN_ALIGN_UPDATED, + &sink_stat); + if (ret != EXYNOS_DP_SUCCESS) { + edp_info->lt_info.lt_status = DP_LT_FAIL; + + return ret; + } + + interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE); + + for (i = 0; i < edp_info->lane_cnt; i++) { + ret = exynos_dp_read_dpcd_adj_req(i, + &adj_req_sw, &adj_req_em); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP read adj req 1 failed\n"); + edp_info->lt_info.lt_status = DP_LT_FAIL; + + return ret; + } + + lt_ctl_val[i] = 0; + lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw; + + if ((adj_req_sw == VOLTAGE_LEVEL_3) || + (adj_req_em == PRE_EMPHASIS_LEVEL_3)) { + lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3; + lt_ctl_val[i] |= MAX_PRE_EMPHASIS_REACH_3; + } + } + + if (((lane_stat&DP_LANE_STAT_CE_DONE) && + (lane_stat&DP_LANE_STAT_SYM_LOCK)) + && (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) { + debug("DP Equalizer training succeed\n"); + + f_bw = exynos_dp_get_link_bandwidth(); + f_lane_cnt = exynos_dp_get_lane_count(); + + debug("DP final BandWidth : %x\n", f_bw); + debug("DP final Lane Count : %x\n", f_lane_cnt); + + edp_info->lt_info.lt_status = DP_LT_FINISHED; + + exynos_dp_equalizer_err_link(edp_info); + + } else { + edp_info->lt_info.ep_loop++; + + if (edp_info->lt_info.ep_loop > MAX_EQ_LOOP) { + if (edp_info->lane_bw == DP_LANE_BW_2_70) { + ret = exynos_dp_reduce_link_rate( + edp_info); + } else { + edp_info->lt_info.lt_status = + DP_LT_FAIL; + exynos_dp_equalizer_err_link(edp_info); + } + } else { + for (i = 0; i < edp_info->lane_cnt; i++) + exynos_dp_set_lanex_pre_emphasis( + lt_ctl_val[i], i); + + ret = exynos_dp_write_bytes_to_dpcd( + DPCD_TRAINING_LANE0_SET, + 4, lt_ctl_val); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP set lt pattern failed\n"); + edp_info->lt_info.lt_status = + DP_LT_FAIL; + exynos_dp_equalizer_err_link(edp_info); + } + } + } + } else if (edp_info->lane_bw == DP_LANE_BW_2_70) { + ret = exynos_dp_reduce_link_rate(edp_info); + } else { + edp_info->lt_info.lt_status = DP_LT_FAIL; + exynos_dp_equalizer_err_link(edp_info); + } + + return ret; +} + +static unsigned int exynos_dp_sw_link_training(struct edp_device_info *edp_info) +{ + unsigned int ret = 0; + int training_finished; + + /* Turn off unnecessary lane */ + if (edp_info->lane_cnt == 1) + exynos_dp_set_analog_power_down(CH1_BLOCK, 1); + + training_finished = 0; + + edp_info->lt_info.lt_status = DP_LT_START; + + /* Process here */ + while (!training_finished) { + switch (edp_info->lt_info.lt_status) { + case DP_LT_START: + ret = exynos_dp_link_start(edp_info); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP LT:link start failed\n"); + return ret; + } + break; + case DP_LT_CR: + ret = exynos_dp_process_clock_recovery(edp_info); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP LT:clock recovery failed\n"); + return ret; + } + break; + case DP_LT_ET: + ret = exynos_dp_process_equalizer_training(edp_info); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP LT:equalizer training failed\n"); + return ret; + } + break; + case DP_LT_FINISHED: + training_finished = 1; + break; + case DP_LT_FAIL: + return -1; + } + } + + return ret; +} + +static unsigned int exynos_dp_set_link_train(struct edp_device_info *edp_info) +{ + unsigned int ret; + + exynos_dp_init_training(); + + ret = exynos_dp_sw_link_training(edp_info); + if (ret != EXYNOS_DP_SUCCESS) + printf("DP dp_sw_link_traning() failed\n"); + + return ret; +} + +static void exynos_dp_enable_scramble(unsigned int enable) +{ + unsigned char data; + + if (enable) { + exynos_dp_enable_scrambling(DP_ENABLE); + + exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET, + &data); + exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET, + (u8)(data & ~DPCD_SCRAMBLING_DISABLED)); + } else { + exynos_dp_enable_scrambling(DP_DISABLE); + exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET, + &data); + exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET, + (u8)(data | DPCD_SCRAMBLING_DISABLED)); + } +} + +static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info) +{ + unsigned int ret = 0; + unsigned int retry_cnt; + + mdelay(1); + + if (edp_info->video_info.master_mode) { + printf("DP does not support master mode\n"); + return -ENODEV; + } else { + /* debug slave */ + exynos_dp_config_video_slave_mode(&edp_info->video_info); + } + + exynos_dp_set_video_color_format(&edp_info->video_info); + + if (edp_info->video_info.bist_mode) { + if (exynos_dp_config_video_bist(edp_info) != 0) + return -1; + } + + ret = exynos_dp_get_pll_lock_status(); + if (ret != PLL_LOCKED) { + printf("DP PLL is not locked yet\n"); + return -EIO; + } + + if (edp_info->video_info.master_mode == 0) { + retry_cnt = 10; + while (retry_cnt) { + ret = exynos_dp_is_slave_video_stream_clock_on(); + if (ret != EXYNOS_DP_SUCCESS) { + if (retry_cnt == 0) { + printf("DP stream_clock_on failed\n"); + return ret; + } + retry_cnt--; + mdelay(1); + } else + break; + } + } + + /* Set to use the register calculated M/N video */ + exynos_dp_set_video_cr_mn(CALCULATED_M, 0, 0); + + /* For video bist, Video timing must be generated by register */ + exynos_dp_set_video_timing_mode(VIDEO_TIMING_FROM_CAPTURE); + + /* Enable video bist */ + if (edp_info->video_info.bist_pattern != COLOR_RAMP && + edp_info->video_info.bist_pattern != BALCK_WHITE_V_LINES && + edp_info->video_info.bist_pattern != COLOR_SQUARE) + exynos_dp_enable_video_bist(edp_info->video_info.bist_mode); + else + exynos_dp_enable_video_bist(DP_DISABLE); + + /* Disable video mute */ + exynos_dp_enable_video_mute(DP_DISABLE); + + /* Configure video Master or Slave mode */ + exynos_dp_enable_video_master(edp_info->video_info.master_mode); + + /* Enable video */ + exynos_dp_start_video(); + + if (edp_info->video_info.master_mode == 0) { + retry_cnt = 100; + while (retry_cnt) { + ret = exynos_dp_is_video_stream_on(); + if (ret != EXYNOS_DP_SUCCESS) { + if (retry_cnt == 0) { + printf("DP Timeout of video stream\n"); + return ret; + } + retry_cnt--; + mdelay(5); + } else + break; + } + } + + return ret; +} + +#ifdef CONFIG_OF_CONTROL +int exynos_dp_parse_dt(const void *blob, struct edp_device_info *edp_info) +{ + unsigned int node = fdtdec_next_compatible(blob, 0, + COMPAT_SAMSUNG_EXYNOS5_DP); + if (node <= 0) { + debug("exynos_dp: Can't get device node for dp\n"); + return -ENODEV; + } + + edp_info->disp_info.h_res = fdtdec_get_int(blob, node, + "samsung,h-res", 0); + edp_info->disp_info.h_sync_width = fdtdec_get_int(blob, node, + "samsung,h-sync-width", 0); + edp_info->disp_info.h_back_porch = fdtdec_get_int(blob, node, + "samsung,h-back-porch", 0); + edp_info->disp_info.h_front_porch = fdtdec_get_int(blob, node, + "samsung,h-front-porch", 0); + edp_info->disp_info.v_res = fdtdec_get_int(blob, node, + "samsung,v-res", 0); + edp_info->disp_info.v_sync_width = fdtdec_get_int(blob, node, + "samsung,v-sync-width", 0); + edp_info->disp_info.v_back_porch = fdtdec_get_int(blob, node, + "samsung,v-back-porch", 0); + edp_info->disp_info.v_front_porch = fdtdec_get_int(blob, node, + "samsung,v-front-porch", 0); + edp_info->disp_info.v_sync_rate = fdtdec_get_int(blob, node, + "samsung,v-sync-rate", 0); + + edp_info->lt_info.lt_status = fdtdec_get_int(blob, node, + "samsung,lt-status", 0); + + edp_info->video_info.master_mode = fdtdec_get_int(blob, node, + "samsung,master-mode", 0); + edp_info->video_info.bist_mode = fdtdec_get_int(blob, node, + "samsung,bist-mode", 0); + edp_info->video_info.bist_pattern = fdtdec_get_int(blob, node, + "samsung,bist-pattern", 0); + edp_info->video_info.h_sync_polarity = fdtdec_get_int(blob, node, + "samsung,h-sync-polarity", 0); + edp_info->video_info.v_sync_polarity = fdtdec_get_int(blob, node, + "samsung,v-sync-polarity", 0); + edp_info->video_info.interlaced = fdtdec_get_int(blob, node, + "samsung,interlaced", 0); + edp_info->video_info.color_space = fdtdec_get_int(blob, node, + "samsung,color-space", 0); + edp_info->video_info.dynamic_range = fdtdec_get_int(blob, node, + "samsung,dynamic-range", 0); + edp_info->video_info.ycbcr_coeff = fdtdec_get_int(blob, node, + "samsung,ycbcr-coeff", 0); + edp_info->video_info.color_depth = fdtdec_get_int(blob, node, + "samsung,color-depth", 0); + return 0; +} +#endif + +unsigned int exynos_init_dp(void) +{ + unsigned int ret; + struct edp_device_info *edp_info; + + edp_info = kzalloc(sizeof(struct edp_device_info), GFP_KERNEL); + if (!edp_info) { + debug("failed to allocate edp device object.\n"); + return -EFAULT; + } + +#ifdef CONFIG_OF_CONTROL + if (exynos_dp_parse_dt(gd->fdt_blob, edp_info)) + debug("unable to parse DP DT node\n"); +#else + edp_info = dp_pd->edp_dev_info; + if (edp_info == NULL) { + debug("failed to get edp_info data.\n"); + return -EFAULT; + } +#endif + + exynos_dp_set_base_addr(); + + exynos_dp_disp_info(&edp_info->disp_info); + + exynos_set_dp_phy(1); + + ret = exynos_dp_init_dp(); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP exynos_dp_init_dp() failed\n"); + return ret; + } + + ret = exynos_dp_handle_edid(edp_info); + if (ret != EXYNOS_DP_SUCCESS) { + printf("EDP handle_edid fail\n"); + return ret; + } + + ret = exynos_dp_set_link_train(edp_info); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP link training fail\n"); + return ret; + } + + exynos_dp_enable_scramble(DP_ENABLE); + exynos_dp_enable_rx_to_enhanced_mode(DP_ENABLE); + exynos_dp_enable_enhanced_mode(DP_ENABLE); + + exynos_dp_set_link_bandwidth(edp_info->lane_bw); + exynos_dp_set_lane_count(edp_info->lane_cnt); + + exynos_dp_init_video(); + ret = exynos_dp_config_video(edp_info); + if (ret != EXYNOS_DP_SUCCESS) { + printf("Exynos DP init failed\n"); + return ret; + } + + printf("Exynos DP init done\n"); + + return ret; +} + +void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd) +{ + if (pd == NULL) { + debug("pd is NULL\n"); + return; + } + + dp_pd = pd; +} diff --git a/qemu/roms/u-boot/drivers/video/exynos_dp_lowlevel.c b/qemu/roms/u-boot/drivers/video/exynos_dp_lowlevel.c new file mode 100644 index 000000000..bf0ea108e --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/exynos_dp_lowlevel.c @@ -0,0 +1,1257 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <linux/err.h> +#include <asm/arch/cpu.h> +#include <asm/arch/dp_info.h> +#include <asm/arch/dp.h> +#include <fdtdec.h> +#include <libfdt.h> + +/* Declare global data pointer */ +DECLARE_GLOBAL_DATA_PTR; + +struct exynos_dp *dp_regs; + +void exynos_dp_set_base_addr(void) +{ +#ifdef CONFIG_OF_CONTROL + unsigned int node = fdtdec_next_compatible(gd->fdt_blob, + 0, COMPAT_SAMSUNG_EXYNOS5_DP); + if (node <= 0) + debug("exynos_dp: Can't get device node for dp\n"); + + dp_regs = (struct exynos_dp *)fdtdec_get_addr(gd->fdt_blob, + node, "reg"); + if (dp_regs == NULL) + debug("Can't get the DP base address\n"); +#else + dp_regs = (struct exynos_dp *)samsung_get_base_dp(); +#endif +} + +static void exynos_dp_enable_video_input(unsigned int enable) +{ + unsigned int reg; + + reg = readl(&dp_regs->video_ctl1); + reg &= ~VIDEO_EN_MASK; + + /* enable video input*/ + if (enable) + reg |= VIDEO_EN_MASK; + + writel(reg, &dp_regs->video_ctl1); + + return; +} + +void exynos_dp_enable_video_bist(unsigned int enable) +{ + /*enable video bist*/ + unsigned int reg; + + reg = readl(&dp_regs->video_ctl4); + reg &= ~VIDEO_BIST_MASK; + + /*enable video bist*/ + if (enable) + reg |= VIDEO_BIST_MASK; + + writel(reg, &dp_regs->video_ctl4); + + return; +} + +void exynos_dp_enable_video_mute(unsigned int enable) +{ + unsigned int reg; + + reg = readl(&dp_regs->video_ctl1); + reg &= ~(VIDEO_MUTE_MASK); + if (enable) + reg |= VIDEO_MUTE_MASK; + + writel(reg, &dp_regs->video_ctl1); + + return; +} + + +static void exynos_dp_init_analog_param(void) +{ + unsigned int reg; + + /* + * Set termination + * Normal bandgap, Normal swing, Tx terminal registor 61 ohm + * 24M Phy clock, TX digital logic power is 100:1.0625V + */ + reg = SEL_BG_NEW_BANDGAP | TX_TERMINAL_CTRL_61_OHM | + SWING_A_30PER_G_NORMAL; + writel(reg, &dp_regs->analog_ctl1); + + reg = SEL_24M | TX_DVDD_BIT_1_0625V; + writel(reg, &dp_regs->analog_ctl2); + + /* + * Set power source for internal clk driver to 1.0625v. + * Select current reference of TX driver current to 00:Ipp/2+Ic/2. + * Set VCO range of PLL +- 0uA + */ + reg = DRIVE_DVDD_BIT_1_0625V | SEL_CURRENT_DEFAULT | VCO_BIT_000_MICRO; + writel(reg, &dp_regs->analog_ctl3); + + /* + * Set AUX TX terminal resistor to 102 ohm + * Set AUX channel amplitude control + */ + reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA; + writel(reg, &dp_regs->pll_filter_ctl1); + + /* + * PLL loop filter bandwidth + * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz + * PLL digital power select: 1.2500V + */ + reg = CH3_AMP_0_MV | CH2_AMP_0_MV | CH1_AMP_0_MV | CH0_AMP_0_MV; + + writel(reg, &dp_regs->amp_tuning_ctl); + + /* + * PLL loop filter bandwidth + * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz + * PLL digital power select: 1.1250V + */ + reg = DP_PLL_LOOP_BIT_DEFAULT | DP_PLL_REF_BIT_1_1250V; + writel(reg, &dp_regs->pll_ctl); +} + +static void exynos_dp_init_interrupt(void) +{ + /* Set interrupt registers to initial states */ + + /* + * Disable interrupt + * INT pin assertion polarity. It must be configured + * correctly according to ICU setting. + * 1 = assert high, 0 = assert low + */ + writel(INT_POL, &dp_regs->int_ctl); + + /* Clear pending regisers */ + writel(0xff, &dp_regs->common_int_sta1); + writel(0xff, &dp_regs->common_int_sta2); + writel(0xff, &dp_regs->common_int_sta3); + writel(0xff, &dp_regs->common_int_sta4); + writel(0xff, &dp_regs->int_sta); + + /* 0:mask,1: unmask */ + writel(0x00, &dp_regs->int_sta_mask1); + writel(0x00, &dp_regs->int_sta_mask2); + writel(0x00, &dp_regs->int_sta_mask3); + writel(0x00, &dp_regs->int_sta_mask4); + writel(0x00, &dp_regs->int_sta_mask); +} + +void exynos_dp_reset(void) +{ + unsigned int reg_func_1; + + /*dp tx sw reset*/ + writel(RESET_DP_TX, &dp_regs->tx_sw_reset); + + exynos_dp_enable_video_input(DP_DISABLE); + exynos_dp_enable_video_bist(DP_DISABLE); + exynos_dp_enable_video_mute(DP_DISABLE); + + /* software reset */ + reg_func_1 = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | + AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | + HDCP_FUNC_EN_N | SW_FUNC_EN_N; + + writel(reg_func_1, &dp_regs->func_en1); + writel(reg_func_1, &dp_regs->func_en2); + + mdelay(1); + + exynos_dp_init_analog_param(); + exynos_dp_init_interrupt(); + + return; +} + +void exynos_dp_enable_sw_func(unsigned int enable) +{ + unsigned int reg; + + reg = readl(&dp_regs->func_en1); + reg &= ~(SW_FUNC_EN_N); + + if (!enable) + reg |= SW_FUNC_EN_N; + + writel(reg, &dp_regs->func_en1); + + return; +} + +unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable) +{ + unsigned int reg; + + reg = readl(&dp_regs->phy_pd); + switch (block) { + case AUX_BLOCK: + reg &= ~(AUX_PD); + if (enable) + reg |= AUX_PD; + break; + case CH0_BLOCK: + reg &= ~(CH0_PD); + if (enable) + reg |= CH0_PD; + break; + case CH1_BLOCK: + reg &= ~(CH1_PD); + if (enable) + reg |= CH1_PD; + break; + case CH2_BLOCK: + reg &= ~(CH2_PD); + if (enable) + reg |= CH2_PD; + break; + case CH3_BLOCK: + reg &= ~(CH3_PD); + if (enable) + reg |= CH3_PD; + break; + case ANALOG_TOTAL: + reg &= ~PHY_PD; + if (enable) + reg |= PHY_PD; + break; + case POWER_ALL: + reg &= ~(PHY_PD | AUX_PD | CH0_PD | CH1_PD | CH2_PD | + CH3_PD); + if (enable) + reg |= (PHY_PD | AUX_PD | CH0_PD | CH1_PD | + CH2_PD | CH3_PD); + break; + default: + printf("DP undefined block number : %d\n", block); + return -1; + } + + writel(reg, &dp_regs->phy_pd); + + return 0; +} + +unsigned int exynos_dp_get_pll_lock_status(void) +{ + unsigned int reg; + + reg = readl(&dp_regs->debug_ctl); + + if (reg & PLL_LOCK) + return PLL_LOCKED; + else + return PLL_UNLOCKED; +} + +static void exynos_dp_set_pll_power(unsigned int enable) +{ + unsigned int reg; + + reg = readl(&dp_regs->pll_ctl); + reg &= ~(DP_PLL_PD); + + if (!enable) + reg |= DP_PLL_PD; + + writel(reg, &dp_regs->pll_ctl); +} + +int exynos_dp_init_analog_func(void) +{ + int ret = EXYNOS_DP_SUCCESS; + unsigned int retry_cnt = 10; + unsigned int reg; + + /*Power On All Analog block */ + exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE); + + reg = PLL_LOCK_CHG; + writel(reg, &dp_regs->common_int_sta1); + + reg = readl(&dp_regs->debug_ctl); + reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); + writel(reg, &dp_regs->debug_ctl); + + /*Assert DP PLL Reset*/ + reg = readl(&dp_regs->pll_ctl); + reg |= DP_PLL_RESET; + writel(reg, &dp_regs->pll_ctl); + + mdelay(1); + + /*Deassert DP PLL Reset*/ + reg = readl(&dp_regs->pll_ctl); + reg &= ~(DP_PLL_RESET); + writel(reg, &dp_regs->pll_ctl); + + exynos_dp_set_pll_power(DP_ENABLE); + + while (exynos_dp_get_pll_lock_status() == PLL_UNLOCKED) { + mdelay(1); + retry_cnt--; + if (retry_cnt == 0) { + printf("DP dp's pll lock failed : retry : %d\n", + retry_cnt); + return -EINVAL; + } + } + + debug("dp's pll lock success(%d)\n", retry_cnt); + + /* Enable Serdes FIFO function and Link symbol clock domain module */ + reg = readl(&dp_regs->func_en2); + reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N + | AUX_FUNC_EN_N); + writel(reg, &dp_regs->func_en2); + + return ret; +} + +void exynos_dp_init_hpd(void) +{ + unsigned int reg; + + /* Clear interrupts releated to Hot Plug Dectect */ + reg = HOTPLUG_CHG | HPD_LOST | PLUG; + writel(reg, &dp_regs->common_int_sta4); + + reg = INT_HPD; + writel(reg, &dp_regs->int_sta); + + reg = readl(&dp_regs->sys_ctl3); + reg &= ~(F_HPD | HPD_CTRL); + writel(reg, &dp_regs->sys_ctl3); + + return; +} + +static inline void exynos_dp_reset_aux(void) +{ + unsigned int reg; + + /* Disable AUX channel module */ + reg = readl(&dp_regs->func_en2); + reg |= AUX_FUNC_EN_N; + writel(reg, &dp_regs->func_en2); + + return; +} + +void exynos_dp_init_aux(void) +{ + unsigned int reg; + + /* Clear inerrupts related to AUX channel */ + reg = RPLY_RECEIV | AUX_ERR; + writel(reg, &dp_regs->int_sta); + + exynos_dp_reset_aux(); + + /* Disable AUX transaction H/W retry */ + reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(3)| + AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; + writel(reg, &dp_regs->aux_hw_retry_ctl); + + /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ + reg = DEFER_CTRL_EN | DEFER_COUNT(1); + writel(reg, &dp_regs->aux_ch_defer_ctl); + + /* Enable AUX channel module */ + reg = readl(&dp_regs->func_en2); + reg &= ~AUX_FUNC_EN_N; + writel(reg, &dp_regs->func_en2); + + return; +} + +void exynos_dp_config_interrupt(void) +{ + unsigned int reg; + + /* 0: mask, 1: unmask */ + reg = COMMON_INT_MASK_1; + writel(reg, &dp_regs->common_int_mask1); + + reg = COMMON_INT_MASK_2; + writel(reg, &dp_regs->common_int_mask2); + + reg = COMMON_INT_MASK_3; + writel(reg, &dp_regs->common_int_mask3); + + reg = COMMON_INT_MASK_4; + writel(reg, &dp_regs->common_int_mask4); + + reg = INT_STA_MASK; + writel(reg, &dp_regs->int_sta_mask); + + return; +} + +unsigned int exynos_dp_get_plug_in_status(void) +{ + unsigned int reg; + + reg = readl(&dp_regs->sys_ctl3); + if (reg & HPD_STATUS) + return 0; + + return -1; +} + +unsigned int exynos_dp_detect_hpd(void) +{ + int timeout_loop = DP_TIMEOUT_LOOP_COUNT; + + mdelay(2); + + while (exynos_dp_get_plug_in_status() != 0) { + if (timeout_loop == 0) + return -EINVAL; + mdelay(10); + timeout_loop--; + } + + return EXYNOS_DP_SUCCESS; +} + +unsigned int exynos_dp_start_aux_transaction(void) +{ + unsigned int reg; + unsigned int ret = 0; + unsigned int retry_cnt; + + /* Enable AUX CH operation */ + reg = readl(&dp_regs->aux_ch_ctl2); + reg |= AUX_EN; + writel(reg, &dp_regs->aux_ch_ctl2); + + retry_cnt = 10; + while (retry_cnt) { + reg = readl(&dp_regs->int_sta); + if (!(reg & RPLY_RECEIV)) { + if (retry_cnt == 0) { + printf("DP Reply Timeout!!\n"); + ret = -EAGAIN; + return ret; + } + mdelay(1); + retry_cnt--; + } else + break; + } + + /* Clear interrupt source for AUX CH command reply */ + writel(reg, &dp_regs->int_sta); + + /* Clear interrupt source for AUX CH access error */ + reg = readl(&dp_regs->int_sta); + if (reg & AUX_ERR) { + printf("DP Aux Access Error\n"); + writel(AUX_ERR, &dp_regs->int_sta); + ret = -EAGAIN; + return ret; + } + + /* Check AUX CH error access status */ + reg = readl(&dp_regs->aux_ch_sta); + if ((reg & AUX_STATUS_MASK) != 0) { + debug("DP AUX CH error happens: %x\n", reg & AUX_STATUS_MASK); + ret = -EAGAIN; + return ret; + } + + return EXYNOS_DP_SUCCESS; +} + +unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr, + unsigned char data) +{ + unsigned int reg, ret; + + /* Clear AUX CH data buffer */ + reg = BUF_CLR; + writel(reg, &dp_regs->buffer_data_ctl); + + /* Select DPCD device address */ + reg = AUX_ADDR_7_0(reg_addr); + writel(reg, &dp_regs->aux_addr_7_0); + reg = AUX_ADDR_15_8(reg_addr); + writel(reg, &dp_regs->aux_addr_15_8); + reg = AUX_ADDR_19_16(reg_addr); + writel(reg, &dp_regs->aux_addr_19_16); + + /* Write data buffer */ + reg = (unsigned int)data; + writel(reg, &dp_regs->buf_data0); + + /* + * Set DisplayPort transaction and write 1 byte + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; + writel(reg, &dp_regs->aux_ch_ctl1); + + /* Start AUX transaction */ + ret = exynos_dp_start_aux_transaction(); + if (ret != EXYNOS_DP_SUCCESS) { + printf("DP Aux transaction failed\n"); + return ret; + } + + return ret; +} + +unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr, + unsigned char *data) +{ + unsigned int reg; + int retval; + + /* Clear AUX CH data buffer */ + reg = BUF_CLR; + writel(reg, &dp_regs->buffer_data_ctl); + + /* Select DPCD device address */ + reg = AUX_ADDR_7_0(reg_addr); + writel(reg, &dp_regs->aux_addr_7_0); + reg = AUX_ADDR_15_8(reg_addr); + writel(reg, &dp_regs->aux_addr_15_8); + reg = AUX_ADDR_19_16(reg_addr); + writel(reg, &dp_regs->aux_addr_19_16); + + /* + * Set DisplayPort transaction and read 1 byte + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; + writel(reg, &dp_regs->aux_ch_ctl1); + + /* Start AUX transaction */ + retval = exynos_dp_start_aux_transaction(); + if (!retval) + debug("DP Aux Transaction fail!\n"); + + /* Read data buffer */ + reg = readl(&dp_regs->buf_data0); + *data = (unsigned char)(reg & 0xff); + + return retval; +} + +unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr, + unsigned int count, + unsigned char data[]) +{ + unsigned int reg; + unsigned int start_offset; + unsigned int cur_data_count; + unsigned int cur_data_idx; + unsigned int retry_cnt; + unsigned int ret = 0; + + /* Clear AUX CH data buffer */ + reg = BUF_CLR; + writel(reg, &dp_regs->buffer_data_ctl); + + start_offset = 0; + while (start_offset < count) { + /* Buffer size of AUX CH is 16 * 4bytes */ + if ((count - start_offset) > 16) + cur_data_count = 16; + else + cur_data_count = count - start_offset; + + retry_cnt = 5; + while (retry_cnt) { + /* Select DPCD device address */ + reg = AUX_ADDR_7_0(reg_addr + start_offset); + writel(reg, &dp_regs->aux_addr_7_0); + reg = AUX_ADDR_15_8(reg_addr + start_offset); + writel(reg, &dp_regs->aux_addr_15_8); + reg = AUX_ADDR_19_16(reg_addr + start_offset); + writel(reg, &dp_regs->aux_addr_19_16); + + for (cur_data_idx = 0; cur_data_idx < cur_data_count; + cur_data_idx++) { + reg = data[start_offset + cur_data_idx]; + writel(reg, (unsigned int)&dp_regs->buf_data0 + + (4 * cur_data_idx)); + } + /* + * Set DisplayPort transaction and write + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_LENGTH(cur_data_count) | + AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; + writel(reg, &dp_regs->aux_ch_ctl1); + + /* Start AUX transaction */ + ret = exynos_dp_start_aux_transaction(); + if (ret != EXYNOS_DP_SUCCESS) { + if (retry_cnt == 0) { + printf("DP Aux Transaction failed\n"); + return ret; + } + retry_cnt--; + } else + break; + } + start_offset += cur_data_count; + } + + return ret; +} + +unsigned int exynos_dp_read_bytes_from_dpcd(unsigned int reg_addr, + unsigned int count, + unsigned char data[]) +{ + unsigned int reg; + unsigned int start_offset; + unsigned int cur_data_count; + unsigned int cur_data_idx; + unsigned int retry_cnt; + unsigned int ret = 0; + + /* Clear AUX CH data buffer */ + reg = BUF_CLR; + writel(reg, &dp_regs->buffer_data_ctl); + + start_offset = 0; + while (start_offset < count) { + /* Buffer size of AUX CH is 16 * 4bytes */ + if ((count - start_offset) > 16) + cur_data_count = 16; + else + cur_data_count = count - start_offset; + + retry_cnt = 5; + while (retry_cnt) { + /* Select DPCD device address */ + reg = AUX_ADDR_7_0(reg_addr + start_offset); + writel(reg, &dp_regs->aux_addr_7_0); + reg = AUX_ADDR_15_8(reg_addr + start_offset); + writel(reg, &dp_regs->aux_addr_15_8); + reg = AUX_ADDR_19_16(reg_addr + start_offset); + writel(reg, &dp_regs->aux_addr_19_16); + /* + * Set DisplayPort transaction and read + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_LENGTH(cur_data_count) | + AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; + writel(reg, &dp_regs->aux_ch_ctl1); + + /* Start AUX transaction */ + ret = exynos_dp_start_aux_transaction(); + if (ret != EXYNOS_DP_SUCCESS) { + if (retry_cnt == 0) { + printf("DP Aux Transaction failed\n"); + return ret; + } + retry_cnt--; + } else + break; + } + + for (cur_data_idx = 0; cur_data_idx < cur_data_count; + cur_data_idx++) { + reg = readl((unsigned int)&dp_regs->buf_data0 + + 4 * cur_data_idx); + data[start_offset + cur_data_idx] = (unsigned char)reg; + } + + start_offset += cur_data_count; + } + + return ret; +} + +int exynos_dp_select_i2c_device(unsigned int device_addr, + unsigned int reg_addr) +{ + unsigned int reg; + int retval; + + /* Set EDID device address */ + reg = device_addr; + writel(reg, &dp_regs->aux_addr_7_0); + writel(0x0, &dp_regs->aux_addr_15_8); + writel(0x0, &dp_regs->aux_addr_19_16); + + /* Set offset from base address of EDID device */ + writel(reg_addr, &dp_regs->buf_data0); + + /* + * Set I2C transaction and write address + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | + AUX_TX_COMM_WRITE; + writel(reg, &dp_regs->aux_ch_ctl1); + + /* Start AUX transaction */ + retval = exynos_dp_start_aux_transaction(); + if (retval != 0) + printf("%s: DP Aux Transaction fail!\n", __func__); + + return retval; +} + +int exynos_dp_read_byte_from_i2c(unsigned int device_addr, + unsigned int reg_addr, + unsigned int *data) +{ + unsigned int reg; + int i; + int retval; + + for (i = 0; i < 10; i++) { + /* Clear AUX CH data buffer */ + reg = BUF_CLR; + writel(reg, &dp_regs->buffer_data_ctl); + + /* Select EDID device */ + retval = exynos_dp_select_i2c_device(device_addr, reg_addr); + if (retval != 0) { + printf("DP Select EDID device fail. retry !\n"); + continue; + } + + /* + * Set I2C transaction and read data + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_TX_COMM_I2C_TRANSACTION | + AUX_TX_COMM_READ; + writel(reg, &dp_regs->aux_ch_ctl1); + + /* Start AUX transaction */ + retval = exynos_dp_start_aux_transaction(); + if (retval != EXYNOS_DP_SUCCESS) + printf("%s: DP Aux Transaction fail!\n", __func__); + } + + /* Read data */ + if (retval == 0) + *data = readl(&dp_regs->buf_data0); + + return retval; +} + +int exynos_dp_read_bytes_from_i2c(unsigned int device_addr, + unsigned int reg_addr, unsigned int count, unsigned char edid[]) +{ + unsigned int reg; + unsigned int i, j; + unsigned int cur_data_idx; + unsigned int defer = 0; + int retval = 0; + + for (i = 0; i < count; i += 16) { /* use 16 burst */ + for (j = 0; j < 100; j++) { + /* Clear AUX CH data buffer */ + reg = BUF_CLR; + writel(reg, &dp_regs->buffer_data_ctl); + + /* Set normal AUX CH command */ + reg = readl(&dp_regs->aux_ch_ctl2); + reg &= ~ADDR_ONLY; + writel(reg, &dp_regs->aux_ch_ctl2); + + /* + * If Rx sends defer, Tx sends only reads + * request without sending addres + */ + if (!defer) + retval = + exynos_dp_select_i2c_device(device_addr, + reg_addr + i); + else + defer = 0; + + if (retval == EXYNOS_DP_SUCCESS) { + /* + * Set I2C transaction and write data + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + reg = AUX_LENGTH(16) | + AUX_TX_COMM_I2C_TRANSACTION | + AUX_TX_COMM_READ; + writel(reg, &dp_regs->aux_ch_ctl1); + + /* Start AUX transaction */ + retval = exynos_dp_start_aux_transaction(); + if (retval == 0) + break; + else + printf("DP Aux Transaction fail!\n"); + } + /* Check if Rx sends defer */ + reg = readl(&dp_regs->aux_rx_comm); + if (reg == AUX_RX_COMM_AUX_DEFER || + reg == AUX_RX_COMM_I2C_DEFER) { + printf("DP Defer: %d\n\n", reg); + defer = 1; + } + } + + for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) { + reg = readl((unsigned int)&dp_regs->buf_data0 + + 4 * cur_data_idx); + edid[i + cur_data_idx] = (unsigned char)reg; + } + } + + return retval; +} + +void exynos_dp_reset_macro(void) +{ + unsigned int reg; + + reg = readl(&dp_regs->phy_test); + reg |= MACRO_RST; + writel(reg, &dp_regs->phy_test); + + /* 10 us is the minimum Macro reset time. */ + mdelay(1); + + reg &= ~MACRO_RST; + writel(reg, &dp_regs->phy_test); +} + +void exynos_dp_set_link_bandwidth(unsigned char bwtype) +{ + unsigned int reg; + + reg = (unsigned int)bwtype; + + /* Set bandwidth to 2.7G or 1.62G */ + if ((bwtype == DP_LANE_BW_1_62) || (bwtype == DP_LANE_BW_2_70)) + writel(reg, &dp_regs->link_bw_set); +} + +unsigned char exynos_dp_get_link_bandwidth(void) +{ + unsigned char ret; + unsigned int reg; + + reg = readl(&dp_regs->link_bw_set); + ret = (unsigned char)reg; + + return ret; +} + +void exynos_dp_set_lane_count(unsigned char count) +{ + unsigned int reg; + + reg = (unsigned int)count; + + if ((count == DP_LANE_CNT_1) || (count == DP_LANE_CNT_2) || + (count == DP_LANE_CNT_4)) + writel(reg, &dp_regs->lane_count_set); +} + +unsigned int exynos_dp_get_lane_count(void) +{ + unsigned int reg; + + reg = readl(&dp_regs->lane_count_set); + + return reg; +} + +unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt) +{ + unsigned int reg_list[DP_LANE_CNT_4] = { + (unsigned int)&dp_regs->ln0_link_training_ctl, + (unsigned int)&dp_regs->ln1_link_training_ctl, + (unsigned int)&dp_regs->ln2_link_training_ctl, + (unsigned int)&dp_regs->ln3_link_training_ctl, + }; + + return readl(reg_list[lanecnt]); +} + +void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val, + unsigned char lanecnt) +{ + unsigned int reg_list[DP_LANE_CNT_4] = { + (unsigned int)&dp_regs->ln0_link_training_ctl, + (unsigned int)&dp_regs->ln1_link_training_ctl, + (unsigned int)&dp_regs->ln2_link_training_ctl, + (unsigned int)&dp_regs->ln3_link_training_ctl, + }; + + writel(request_val, reg_list[lanecnt]); +} + +void exynos_dp_set_lane_pre_emphasis(unsigned int level, unsigned char lanecnt) +{ + unsigned char i; + unsigned int reg; + unsigned int reg_list[DP_LANE_CNT_4] = { + (unsigned int)&dp_regs->ln0_link_training_ctl, + (unsigned int)&dp_regs->ln1_link_training_ctl, + (unsigned int)&dp_regs->ln2_link_training_ctl, + (unsigned int)&dp_regs->ln3_link_training_ctl, + }; + unsigned int reg_shift[DP_LANE_CNT_4] = { + PRE_EMPHASIS_SET_0_SHIFT, + PRE_EMPHASIS_SET_1_SHIFT, + PRE_EMPHASIS_SET_2_SHIFT, + PRE_EMPHASIS_SET_3_SHIFT + }; + + for (i = 0; i < lanecnt; i++) { + reg = level << reg_shift[i]; + writel(reg, reg_list[i]); + } +} + +void exynos_dp_set_training_pattern(unsigned int pattern) +{ + unsigned int reg = 0; + + switch (pattern) { + case PRBS7: + reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; + break; + case D10_2: + reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; + break; + case TRAINING_PTN1: + reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; + break; + case TRAINING_PTN2: + reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; + break; + case DP_NONE: + reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_DISABLE | + SW_TRAINING_PATTERN_SET_NORMAL; + break; + default: + break; + } + + writel(reg, &dp_regs->training_ptn_set); +} + +void exynos_dp_enable_enhanced_mode(unsigned char enable) +{ + unsigned int reg; + + reg = readl(&dp_regs->sys_ctl4); + reg &= ~ENHANCED; + + if (enable) + reg |= ENHANCED; + + writel(reg, &dp_regs->sys_ctl4); +} + +void exynos_dp_enable_scrambling(unsigned int enable) +{ + unsigned int reg; + + reg = readl(&dp_regs->training_ptn_set); + reg &= ~(SCRAMBLING_DISABLE); + + if (!enable) + reg |= SCRAMBLING_DISABLE; + + writel(reg, &dp_regs->training_ptn_set); +} + +int exynos_dp_init_video(void) +{ + unsigned int reg; + + /* Clear VID_CLK_CHG[1] and VID_FORMAT_CHG[3] and VSYNC_DET[7] */ + reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; + writel(reg, &dp_regs->common_int_sta1); + + /* I_STRM__CLK detect : DE_CTL : Auto detect */ + reg &= ~DET_CTRL; + writel(reg, &dp_regs->sys_ctl1); + + return 0; +} + +void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info) +{ + unsigned int reg; + + /* Video Slave mode setting */ + reg = readl(&dp_regs->func_en1); + reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N); + reg |= MASTER_VID_FUNC_EN_N; + writel(reg, &dp_regs->func_en1); + + /* Configure Interlaced for slave mode video */ + reg = readl(&dp_regs->video_ctl10); + reg &= ~INTERACE_SCAN_CFG; + reg |= (video_info->interlaced << INTERACE_SCAN_CFG_SHIFT); + writel(reg, &dp_regs->video_ctl10); + + /* Configure V sync polarity for slave mode video */ + reg = readl(&dp_regs->video_ctl10); + reg &= ~VSYNC_POLARITY_CFG; + reg |= (video_info->v_sync_polarity << V_S_POLARITY_CFG_SHIFT); + writel(reg, &dp_regs->video_ctl10); + + /* Configure H sync polarity for slave mode video */ + reg = readl(&dp_regs->video_ctl10); + reg &= ~HSYNC_POLARITY_CFG; + reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT); + writel(reg, &dp_regs->video_ctl10); + + /*Set video mode to slave mode */ + reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; + writel(reg, &dp_regs->soc_general_ctl); +} + +void exynos_dp_set_video_color_format(struct edp_video_info *video_info) +{ + unsigned int reg; + + /* Configure the input color depth, color space, dynamic range */ + reg = (video_info->dynamic_range << IN_D_RANGE_SHIFT) | + (video_info->color_depth << IN_BPC_SHIFT) | + (video_info->color_space << IN_COLOR_F_SHIFT); + writel(reg, &dp_regs->video_ctl2); + + /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ + reg = readl(&dp_regs->video_ctl3); + reg &= ~IN_YC_COEFFI_MASK; + if (video_info->ycbcr_coeff) + reg |= IN_YC_COEFFI_ITU709; + else + reg |= IN_YC_COEFFI_ITU601; + writel(reg, &dp_regs->video_ctl3); +} + +int exynos_dp_config_video_bist(struct edp_device_info *edp_info) +{ + unsigned int reg; + unsigned int bist_type = 0; + struct edp_video_info video_info = edp_info->video_info; + + /* For master mode, you don't need to set the video format */ + if (video_info.master_mode == 0) { + writel(TOTAL_LINE_CFG_L(edp_info->disp_info.v_total), + &dp_regs->total_ln_cfg_l); + writel(TOTAL_LINE_CFG_H(edp_info->disp_info.v_total), + &dp_regs->total_ln_cfg_h); + writel(ACTIVE_LINE_CFG_L(edp_info->disp_info.v_res), + &dp_regs->active_ln_cfg_l); + writel(ACTIVE_LINE_CFG_H(edp_info->disp_info.v_res), + &dp_regs->active_ln_cfg_h); + writel(edp_info->disp_info.v_sync_width, + &dp_regs->vsw_cfg); + writel(edp_info->disp_info.v_back_porch, + &dp_regs->vbp_cfg); + writel(edp_info->disp_info.v_front_porch, + &dp_regs->vfp_cfg); + + writel(TOTAL_PIXEL_CFG_L(edp_info->disp_info.h_total), + &dp_regs->total_pix_cfg_l); + writel(TOTAL_PIXEL_CFG_H(edp_info->disp_info.h_total), + &dp_regs->total_pix_cfg_h); + writel(ACTIVE_PIXEL_CFG_L(edp_info->disp_info.h_res), + &dp_regs->active_pix_cfg_l); + writel(ACTIVE_PIXEL_CFG_H(edp_info->disp_info.h_res), + &dp_regs->active_pix_cfg_h); + writel(H_F_PORCH_CFG_L(edp_info->disp_info.h_front_porch), + &dp_regs->hfp_cfg_l); + writel(H_F_PORCH_CFG_H(edp_info->disp_info.h_front_porch), + &dp_regs->hfp_cfg_h); + writel(H_SYNC_PORCH_CFG_L(edp_info->disp_info.h_sync_width), + &dp_regs->hsw_cfg_l); + writel(H_SYNC_PORCH_CFG_H(edp_info->disp_info.h_sync_width), + &dp_regs->hsw_cfg_h); + writel(H_B_PORCH_CFG_L(edp_info->disp_info.h_back_porch), + &dp_regs->hbp_cfg_l); + writel(H_B_PORCH_CFG_H(edp_info->disp_info.h_back_porch), + &dp_regs->hbp_cfg_h); + + /* + * Set SLAVE_I_SCAN_CFG[2], VSYNC_P_CFG[1], + * HSYNC_P_CFG[0] properly + */ + reg = (video_info.interlaced << INTERACE_SCAN_CFG_SHIFT | + video_info.v_sync_polarity << V_S_POLARITY_CFG_SHIFT | + video_info.h_sync_polarity << H_S_POLARITY_CFG_SHIFT); + writel(reg, &dp_regs->video_ctl10); + } + + /* BIST color bar width set--set to each bar is 32 pixel width */ + switch (video_info.bist_pattern) { + case COLORBAR_32: + bist_type = BIST_WIDTH_BAR_32_PIXEL | + BIST_TYPE_COLOR_BAR; + break; + case COLORBAR_64: + bist_type = BIST_WIDTH_BAR_64_PIXEL | + BIST_TYPE_COLOR_BAR; + break; + case WHITE_GRAY_BALCKBAR_32: + bist_type = BIST_WIDTH_BAR_32_PIXEL | + BIST_TYPE_WHITE_GRAY_BLACK_BAR; + break; + case WHITE_GRAY_BALCKBAR_64: + bist_type = BIST_WIDTH_BAR_64_PIXEL | + BIST_TYPE_WHITE_GRAY_BLACK_BAR; + break; + case MOBILE_WHITEBAR_32: + bist_type = BIST_WIDTH_BAR_32_PIXEL | + BIST_TYPE_MOBILE_WHITE_BAR; + break; + case MOBILE_WHITEBAR_64: + bist_type = BIST_WIDTH_BAR_64_PIXEL | + BIST_TYPE_MOBILE_WHITE_BAR; + break; + default: + return -1; + } + + reg = bist_type; + writel(reg, &dp_regs->video_ctl4); + + return 0; +} + +unsigned int exynos_dp_is_slave_video_stream_clock_on(void) +{ + unsigned int reg; + + /* Update Video stream clk detect status */ + reg = readl(&dp_regs->sys_ctl1); + writel(reg, &dp_regs->sys_ctl1); + + reg = readl(&dp_regs->sys_ctl1); + + if (!(reg & DET_STA)) { + debug("DP Input stream clock not detected.\n"); + return -EIO; + } + + return EXYNOS_DP_SUCCESS; +} + +void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value, + unsigned int n_value) +{ + unsigned int reg; + + if (type == REGISTER_M) { + reg = readl(&dp_regs->sys_ctl4); + reg |= FIX_M_VID; + writel(reg, &dp_regs->sys_ctl4); + reg = M_VID0_CFG(m_value); + writel(reg, &dp_regs->m_vid0); + reg = M_VID1_CFG(m_value); + writel(reg, &dp_regs->m_vid1); + reg = M_VID2_CFG(m_value); + writel(reg, &dp_regs->m_vid2); + + reg = N_VID0_CFG(n_value); + writel(reg, &dp_regs->n_vid0); + reg = N_VID1_CFG(n_value); + writel(reg, &dp_regs->n_vid1); + reg = N_VID2_CFG(n_value); + writel(reg, &dp_regs->n_vid2); + } else { + reg = readl(&dp_regs->sys_ctl4); + reg &= ~FIX_M_VID; + writel(reg, &dp_regs->sys_ctl4); + } +} + +void exynos_dp_set_video_timing_mode(unsigned int type) +{ + unsigned int reg; + + reg = readl(&dp_regs->video_ctl10); + reg &= ~FORMAT_SEL; + + if (type != VIDEO_TIMING_FROM_CAPTURE) + reg |= FORMAT_SEL; + + writel(reg, &dp_regs->video_ctl10); +} + +void exynos_dp_enable_video_master(unsigned int enable) +{ + unsigned int reg; + + reg = readl(&dp_regs->soc_general_ctl); + if (enable) { + reg &= ~VIDEO_MODE_MASK; + reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; + } else { + reg &= ~VIDEO_MODE_MASK; + reg |= VIDEO_MODE_SLAVE_MODE; + } + + writel(reg, &dp_regs->soc_general_ctl); +} + +void exynos_dp_start_video(void) +{ + unsigned int reg; + + /* Enable Video input and disable Mute */ + reg = readl(&dp_regs->video_ctl1); + reg |= VIDEO_EN; + writel(reg, &dp_regs->video_ctl1); +} + +unsigned int exynos_dp_is_video_stream_on(void) +{ + unsigned int reg; + + /* Update STRM_VALID */ + reg = readl(&dp_regs->sys_ctl3); + writel(reg, &dp_regs->sys_ctl3); + + reg = readl(&dp_regs->sys_ctl3); + if (!(reg & STRM_VALID)) + return -EIO; + + return EXYNOS_DP_SUCCESS; +} diff --git a/qemu/roms/u-boot/drivers/video/exynos_dp_lowlevel.h b/qemu/roms/u-boot/drivers/video/exynos_dp_lowlevel.h new file mode 100644 index 000000000..865168152 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/exynos_dp_lowlevel.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _EXYNOS_EDP_LOWLEVEL_H +#define _EXYNOS_EDP_LOWLEVEL_H + +void exynos_dp_enable_video_bist(unsigned int enable); +void exynos_dp_enable_video_mute(unsigned int enable); +void exynos_dp_reset(void); +void exynos_dp_enable_sw_func(unsigned int enable); +unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable); +unsigned int exynos_dp_get_pll_lock_status(void); +int exynos_dp_init_analog_func(void); +void exynos_dp_init_hpd(void); +void exynos_dp_init_aux(void); +void exynos_dp_config_interrupt(void); +unsigned int exynos_dp_get_plug_in_status(void); +unsigned int exynos_dp_detect_hpd(void); +unsigned int exynos_dp_start_aux_transaction(void); +unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr, + unsigned char data); +unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr, + unsigned char *data); +unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr, + unsigned int count, + unsigned char data[]); +unsigned int exynos_dp_read_bytes_from_dpcd( unsigned int reg_addr, + unsigned int count, + unsigned char data[]); +int exynos_dp_select_i2c_device( unsigned int device_addr, + unsigned int reg_addr); +int exynos_dp_read_byte_from_i2c(unsigned int device_addr, + unsigned int reg_addr, unsigned int *data); +int exynos_dp_read_bytes_from_i2c(unsigned int device_addr, + unsigned int reg_addr, unsigned int count, + unsigned char edid[]); +void exynos_dp_reset_macro(void); +void exynos_dp_set_link_bandwidth(unsigned char bwtype); +unsigned char exynos_dp_get_link_bandwidth(void); +void exynos_dp_set_lane_count(unsigned char count); +unsigned int exynos_dp_get_lane_count(void); +unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt); +void exynos_dp_set_lane_pre_emphasis(unsigned int level, + unsigned char lanecnt); +void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val, + unsigned char lanecnt); +void exynos_dp_set_training_pattern(unsigned int pattern); +void exynos_dp_enable_enhanced_mode(unsigned char enable); +void exynos_dp_enable_scrambling(unsigned int enable); +int exynos_dp_init_video(void); +void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info); +void exynos_dp_set_video_color_format(struct edp_video_info *video_info); +int exynos_dp_config_video_bist(struct edp_device_info *edp_info); +unsigned int exynos_dp_is_slave_video_stream_clock_on(void); +void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value, + unsigned int n_value); +void exynos_dp_set_video_timing_mode(unsigned int type); +void exynos_dp_enable_video_master(unsigned int enable); +void exynos_dp_start_video(void); +unsigned int exynos_dp_is_video_stream_on(void); +void exynos_dp_set_base_addr(void); + +#endif /* _EXYNOS_DP_LOWLEVEL_H */ diff --git a/qemu/roms/u-boot/drivers/video/exynos_fb.c b/qemu/roms/u-boot/drivers/video/exynos_fb.c new file mode 100644 index 000000000..e1e0d802f --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/exynos_fb.c @@ -0,0 +1,322 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: InKi Dae <inki.dae@samsung.com> + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <lcd.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clock.h> +#include <asm/arch/clk.h> +#include <asm/arch/mipi_dsim.h> +#include <asm/arch/dp_info.h> +#include <asm/arch/system.h> +#include <asm-generic/errno.h> + +#include "exynos_fb.h" + +DECLARE_GLOBAL_DATA_PTR; + +static unsigned int panel_width, panel_height; + +/* + * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs + * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix to reserve + * FB memory at a very early stage, i.e even before exynos_fimd_parse_dt() + * is called. So, we are forced to statically assign it. + */ +#ifdef CONFIG_OF_CONTROL +vidinfo_t panel_info = { + .vl_col = LCD_XRES, + .vl_row = LCD_YRES, + .vl_bpix = LCD_COLOR16, +}; +#endif + +static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid) +{ + unsigned long palette_size; + unsigned int fb_size; + + fb_size = vid->vl_row * vid->vl_col * (NBITS(vid->vl_bpix) >> 3); + + palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16; + + exynos_fimd_lcd_init_mem((unsigned long)lcdbase, + (unsigned long)fb_size, palette_size); +} + +static void exynos_lcd_init(vidinfo_t *vid) +{ + exynos_fimd_lcd_init(vid); + + /* Enable flushing after LCD writes if requested */ + lcd_set_flush_dcache(1); +} + +void __exynos_cfg_lcd_gpio(void) +{ +} +void exynos_cfg_lcd_gpio(void) + __attribute__((weak, alias("__exynos_cfg_lcd_gpio"))); + +void __exynos_backlight_on(unsigned int onoff) +{ +} +void exynos_backlight_on(unsigned int onoff) + __attribute__((weak, alias("__exynos_cfg_lcd_gpio"))); + +void __exynos_reset_lcd(void) +{ +} +void exynos_reset_lcd(void) + __attribute__((weak, alias("__exynos_reset_lcd"))); + +void __exynos_lcd_power_on(void) +{ +} +void exynos_lcd_power_on(void) + __attribute__((weak, alias("__exynos_lcd_power_on"))); + +void __exynos_cfg_ldo(void) +{ +} +void exynos_cfg_ldo(void) + __attribute__((weak, alias("__exynos_cfg_ldo"))); + +void __exynos_enable_ldo(unsigned int onoff) +{ +} +void exynos_enable_ldo(unsigned int onoff) + __attribute__((weak, alias("__exynos_enable_ldo"))); + +void __exynos_backlight_reset(void) +{ +} +void exynos_backlight_reset(void) + __attribute__((weak, alias("__exynos_backlight_reset"))); + +int __exynos_lcd_misc_init(vidinfo_t *vid) +{ + return 0; +} +int exynos_lcd_misc_init(vidinfo_t *vid) + __attribute__((weak, alias("__exynos_lcd_misc_init"))); + +static void lcd_panel_on(vidinfo_t *vid) +{ + udelay(vid->init_delay); + + exynos_backlight_reset(); + + exynos_cfg_lcd_gpio(); + + exynos_lcd_power_on(); + + udelay(vid->power_on_delay); + + if (vid->dp_enabled) + exynos_init_dp(); + + exynos_reset_lcd(); + + udelay(vid->reset_delay); + + exynos_backlight_on(1); + + exynos_cfg_ldo(); + + exynos_enable_ldo(1); + + if (vid->mipi_enabled) + exynos_mipi_dsi_init(); +} + +#ifdef CONFIG_OF_CONTROL +int exynos_fimd_parse_dt(const void *blob) +{ + unsigned int node; + node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD); + if (node <= 0) { + debug("exynos_fb: Can't get device node for fimd\n"); + return -ENODEV; + } + + panel_info.vl_col = fdtdec_get_int(blob, node, "samsung,vl-col", 0); + if (panel_info.vl_col == 0) { + debug("Can't get XRES\n"); + return -ENXIO; + } + + panel_info.vl_row = fdtdec_get_int(blob, node, "samsung,vl-row", 0); + if (panel_info.vl_row == 0) { + debug("Can't get YRES\n"); + return -ENXIO; + } + + panel_info.vl_width = fdtdec_get_int(blob, node, + "samsung,vl-width", 0); + + panel_info.vl_height = fdtdec_get_int(blob, node, + "samsung,vl-height", 0); + + panel_info.vl_freq = fdtdec_get_int(blob, node, "samsung,vl-freq", 0); + if (panel_info.vl_freq == 0) { + debug("Can't get refresh rate\n"); + return -ENXIO; + } + + if (fdtdec_get_bool(blob, node, "samsung,vl-clkp")) + panel_info.vl_clkp = CONFIG_SYS_LOW; + + if (fdtdec_get_bool(blob, node, "samsung,vl-oep")) + panel_info.vl_oep = CONFIG_SYS_LOW; + + if (fdtdec_get_bool(blob, node, "samsung,vl-hsp")) + panel_info.vl_hsp = CONFIG_SYS_LOW; + + if (fdtdec_get_bool(blob, node, "samsung,vl-vsp")) + panel_info.vl_vsp = CONFIG_SYS_LOW; + + if (fdtdec_get_bool(blob, node, "samsung,vl-dp")) + panel_info.vl_dp = CONFIG_SYS_LOW; + + panel_info.vl_bpix = fdtdec_get_int(blob, node, "samsung,vl-bpix", 0); + if (panel_info.vl_bpix == 0) { + debug("Can't get bits per pixel\n"); + return -ENXIO; + } + + panel_info.vl_hspw = fdtdec_get_int(blob, node, "samsung,vl-hspw", 0); + if (panel_info.vl_hspw == 0) { + debug("Can't get hsync width\n"); + return -ENXIO; + } + + panel_info.vl_hfpd = fdtdec_get_int(blob, node, "samsung,vl-hfpd", 0); + if (panel_info.vl_hfpd == 0) { + debug("Can't get right margin\n"); + return -ENXIO; + } + + panel_info.vl_hbpd = (u_char)fdtdec_get_int(blob, node, + "samsung,vl-hbpd", 0); + if (panel_info.vl_hbpd == 0) { + debug("Can't get left margin\n"); + return -ENXIO; + } + + panel_info.vl_vspw = (u_char)fdtdec_get_int(blob, node, + "samsung,vl-vspw", 0); + if (panel_info.vl_vspw == 0) { + debug("Can't get vsync width\n"); + return -ENXIO; + } + + panel_info.vl_vfpd = fdtdec_get_int(blob, node, + "samsung,vl-vfpd", 0); + if (panel_info.vl_vfpd == 0) { + debug("Can't get lower margin\n"); + return -ENXIO; + } + + panel_info.vl_vbpd = fdtdec_get_int(blob, node, "samsung,vl-vbpd", 0); + if (panel_info.vl_vbpd == 0) { + debug("Can't get upper margin\n"); + return -ENXIO; + } + + panel_info.vl_cmd_allow_len = fdtdec_get_int(blob, node, + "samsung,vl-cmd-allow-len", 0); + + panel_info.win_id = fdtdec_get_int(blob, node, "samsung,winid", 0); + panel_info.init_delay = fdtdec_get_int(blob, node, + "samsung,init-delay", 0); + panel_info.power_on_delay = fdtdec_get_int(blob, node, + "samsung,power-on-delay", 0); + panel_info.reset_delay = fdtdec_get_int(blob, node, + "samsung,reset-delay", 0); + panel_info.interface_mode = fdtdec_get_int(blob, node, + "samsung,interface-mode", 0); + panel_info.mipi_enabled = fdtdec_get_int(blob, node, + "samsung,mipi-enabled", 0); + panel_info.dp_enabled = fdtdec_get_int(blob, node, + "samsung,dp-enabled", 0); + panel_info.cs_setup = fdtdec_get_int(blob, node, + "samsung,cs-setup", 0); + panel_info.wr_setup = fdtdec_get_int(blob, node, + "samsung,wr-setup", 0); + panel_info.wr_act = fdtdec_get_int(blob, node, "samsung,wr-act", 0); + panel_info.wr_hold = fdtdec_get_int(blob, node, "samsung,wr-hold", 0); + + panel_info.logo_on = fdtdec_get_int(blob, node, "samsung,logo-on", 0); + if (panel_info.logo_on) { + panel_info.logo_width = fdtdec_get_int(blob, node, + "samsung,logo-width", 0); + panel_info.logo_height = fdtdec_get_int(blob, node, + "samsung,logo-height", 0); + panel_info.logo_addr = fdtdec_get_int(blob, node, + "samsung,logo-addr", 0); + } + + panel_info.rgb_mode = fdtdec_get_int(blob, node, + "samsung,rgb-mode", 0); + panel_info.pclk_name = fdtdec_get_int(blob, node, + "samsung,pclk-name", 0); + panel_info.sclk_div = fdtdec_get_int(blob, node, + "samsung,sclk-div", 0); + panel_info.dual_lcd_enabled = fdtdec_get_int(blob, node, + "samsung,dual-lcd-enabled", 0); + + return 0; +} +#endif + +void lcd_ctrl_init(void *lcdbase) +{ + set_system_display_ctrl(); + set_lcd_clk(); + +#ifdef CONFIG_OF_CONTROL + if (exynos_fimd_parse_dt(gd->fdt_blob)) + debug("Can't get proper panel info\n"); +#ifdef CONFIG_EXYNOS_MIPI_DSIM + exynos_init_dsim_platform_data(&panel_info); +#endif + exynos_lcd_misc_init(&panel_info); +#else + /* initialize parameters which is specific to panel. */ + init_panel_info(&panel_info); +#endif + + panel_width = panel_info.vl_width; + panel_height = panel_info.vl_height; + + exynos_lcd_init_mem(lcdbase, &panel_info); + + exynos_lcd_init(&panel_info); +} + +void lcd_enable(void) +{ + if (panel_info.logo_on) { + memset((void *) gd->fb_base, 0, panel_width * panel_height * + (NBITS(panel_info.vl_bpix) >> 3)); + } + + lcd_panel_on(&panel_info); +} + +/* dummy function */ +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ + return; +} diff --git a/qemu/roms/u-boot/drivers/video/exynos_fb.h b/qemu/roms/u-boot/drivers/video/exynos_fb.h new file mode 100644 index 000000000..2c2f94bd0 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/exynos_fb.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: InKi Dae <inki.dae@samsung.com> + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _EXYNOS_FB_H_ +#define _EXYNOS_FB_H_ + +#include <asm/arch/fb.h> + +#define MAX_CLOCK (86 * 1000000) + +enum exynos_cpu_auto_cmd_rate { + DISABLE_AUTO_FRM, + PER_TWO_FRM, + PER_FOUR_FRM, + PER_SIX_FRM, + PER_EIGHT_FRM, + PER_TEN_FRM, + PER_TWELVE_FRM, + PER_FOURTEEN_FRM, + PER_SIXTEEN_FRM, + PER_EIGHTEEN_FRM, + PER_TWENTY_FRM, + PER_TWENTY_TWO_FRM, + PER_TWENTY_FOUR_FRM, + PER_TWENTY_SIX_FRM, + PER_TWENTY_EIGHT_FRM, + PER_THIRTY_FRM, +}; + +void exynos_fimd_lcd_init_mem(unsigned long screen_base, unsigned long fb_size, + unsigned long palette_size); +void exynos_fimd_lcd_init(vidinfo_t *vid); +unsigned long exynos_fimd_calc_fbsize(void); + +#endif diff --git a/qemu/roms/u-boot/drivers/video/exynos_fimd.c b/qemu/roms/u-boot/drivers/video/exynos_fimd.c new file mode 100644 index 000000000..cebbba758 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/exynos_fimd.c @@ -0,0 +1,366 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: InKi Dae <inki.dae@samsung.com> + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <lcd.h> +#include <div64.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <asm/arch/clk.h> +#include <asm/arch/clock.h> +#include <asm/arch/cpu.h> +#include "exynos_fb.h" + +DECLARE_GLOBAL_DATA_PTR; + +static unsigned long *lcd_base_addr; +static vidinfo_t *pvid; +static struct exynos_fb *fimd_ctrl; + +void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size, + u_long palette_size) +{ + lcd_base_addr = (unsigned long *)screen_base; +} + +static void exynos_fimd_set_dualrgb(unsigned int enabled) +{ + unsigned int cfg = 0; + + if (enabled) { + cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT | + EXYNOS_DUALRGB_VDEN_EN_ENABLE; + + /* in case of Line Split mode, MAIN_CNT doesn't neet to set. */ + cfg |= EXYNOS_DUALRGB_SUB_CNT(pvid->vl_col / 2) | + EXYNOS_DUALRGB_MAIN_CNT(0); + } + + writel(cfg, &fimd_ctrl->dualrgb); +} + +static void exynos_fimd_set_dp_clkcon(unsigned int enabled) +{ + unsigned int cfg = 0; + + if (enabled) + cfg = EXYNOS_DP_CLK_ENABLE; + + writel(cfg, &fimd_ctrl->dp_mie_clkcon); +} + +static void exynos_fimd_set_par(unsigned int win_id) +{ + unsigned int cfg = 0; + + /* set window control */ + cfg = readl((unsigned int)&fimd_ctrl->wincon0 + + EXYNOS_WINCON(win_id)); + + cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE | + EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE | + EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK | + EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK); + + /* DATAPATH is DMA */ + cfg |= EXYNOS_WINCON_DATAPATH_DMA; + + cfg |= EXYNOS_WINCON_HAWSWP_ENABLE; + + /* dma burst is 16 */ + cfg |= EXYNOS_WINCON_BURSTLEN_16WORD; + + switch (pvid->vl_bpix) { + case 4: + cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565; + break; + default: + cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888; + break; + } + + writel(cfg, (unsigned int)&fimd_ctrl->wincon0 + + EXYNOS_WINCON(win_id)); + + /* set window position to x=0, y=0*/ + cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0); + writel(cfg, (unsigned int)&fimd_ctrl->vidosd0a + + EXYNOS_VIDOSD(win_id)); + + cfg = EXYNOS_VIDOSD_RIGHT_X(pvid->vl_col - 1) | + EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1) | + EXYNOS_VIDOSD_RIGHT_X_E(1) | + EXYNOS_VIDOSD_BOTTOM_Y_E(0); + + writel(cfg, (unsigned int)&fimd_ctrl->vidosd0b + + EXYNOS_VIDOSD(win_id)); + + /* set window size for window0*/ + cfg = EXYNOS_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row); + writel(cfg, (unsigned int)&fimd_ctrl->vidosd0c + + EXYNOS_VIDOSD(win_id)); +} + +static void exynos_fimd_set_buffer_address(unsigned int win_id) +{ + unsigned long start_addr, end_addr; + + start_addr = (unsigned long)lcd_base_addr; + end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) * + pvid->vl_row); + + writel(start_addr, (unsigned int)&fimd_ctrl->vidw00add0b0 + + EXYNOS_BUFFER_OFFSET(win_id)); + writel(end_addr, (unsigned int)&fimd_ctrl->vidw00add1b0 + + EXYNOS_BUFFER_OFFSET(win_id)); +} + +static void exynos_fimd_set_clock(vidinfo_t *pvid) +{ + unsigned int cfg = 0, div = 0, remainder, remainder_div; + unsigned long pixel_clock; + unsigned long long src_clock; + + if (pvid->dual_lcd_enabled) { + pixel_clock = pvid->vl_freq * + (pvid->vl_hspw + pvid->vl_hfpd + + pvid->vl_hbpd + pvid->vl_col / 2) * + (pvid->vl_vspw + pvid->vl_vfpd + + pvid->vl_vbpd + pvid->vl_row); + } else if (pvid->interface_mode == FIMD_CPU_INTERFACE) { + pixel_clock = pvid->vl_freq * + pvid->vl_width * pvid->vl_height * + (pvid->cs_setup + pvid->wr_setup + + pvid->wr_act + pvid->wr_hold + 1); + } else { + pixel_clock = pvid->vl_freq * + (pvid->vl_hspw + pvid->vl_hfpd + + pvid->vl_hbpd + pvid->vl_col) * + (pvid->vl_vspw + pvid->vl_vfpd + + pvid->vl_vbpd + pvid->vl_row); + } + + cfg = readl(&fimd_ctrl->vidcon0); + cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK | + EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK | + EXYNOS_VIDCON0_CLKDIR_MASK); + cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS | + EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED); + + src_clock = (unsigned long long) get_lcd_clk(); + + /* get quotient and remainder. */ + remainder = do_div(src_clock, pixel_clock); + div = src_clock; + + remainder *= 10; + remainder_div = remainder / pixel_clock; + + /* round about one places of decimals. */ + if (remainder_div >= 5) + div++; + + /* in case of dual lcd mode. */ + if (pvid->dual_lcd_enabled) + div--; + + cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1); + writel(cfg, &fimd_ctrl->vidcon0); +} + +void exynos_set_trigger(void) +{ + unsigned int cfg = 0; + + cfg = readl(&fimd_ctrl->trigcon); + + cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG); + + writel(cfg, &fimd_ctrl->trigcon); +} + +int exynos_is_i80_frame_done(void) +{ + unsigned int cfg = 0; + int status; + + cfg = readl(&fimd_ctrl->trigcon); + + /* frame done func is valid only when TRIMODE[0] is set to 1. */ + status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) == + EXYNOS_I80STATUS_TRIG_DONE; + + return status; +} + +static void exynos_fimd_lcd_on(void) +{ + unsigned int cfg = 0; + + /* display on */ + cfg = readl(&fimd_ctrl->vidcon0); + cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE); + writel(cfg, &fimd_ctrl->vidcon0); +} + +static void exynos_fimd_window_on(unsigned int win_id) +{ + unsigned int cfg = 0; + + /* enable window */ + cfg = readl((unsigned int)&fimd_ctrl->wincon0 + + EXYNOS_WINCON(win_id)); + cfg |= EXYNOS_WINCON_ENWIN_ENABLE; + writel(cfg, (unsigned int)&fimd_ctrl->wincon0 + + EXYNOS_WINCON(win_id)); + + cfg = readl(&fimd_ctrl->winshmap); + cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id); + writel(cfg, &fimd_ctrl->winshmap); +} + +void exynos_fimd_lcd_off(void) +{ + unsigned int cfg = 0; + + cfg = readl(&fimd_ctrl->vidcon0); + cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE); + writel(cfg, &fimd_ctrl->vidcon0); +} + +void exynos_fimd_window_off(unsigned int win_id) +{ + unsigned int cfg = 0; + + cfg = readl((unsigned int)&fimd_ctrl->wincon0 + + EXYNOS_WINCON(win_id)); + cfg &= EXYNOS_WINCON_ENWIN_DISABLE; + writel(cfg, (unsigned int)&fimd_ctrl->wincon0 + + EXYNOS_WINCON(win_id)); + + cfg = readl(&fimd_ctrl->winshmap); + cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id); + writel(cfg, &fimd_ctrl->winshmap); +} + + +void exynos_fimd_lcd_init(vidinfo_t *vid) +{ + unsigned int cfg = 0, rgb_mode; + unsigned int offset; +#ifdef CONFIG_OF_CONTROL + unsigned int node; + + node = fdtdec_next_compatible(gd->fdt_blob, + 0, COMPAT_SAMSUNG_EXYNOS_FIMD); + if (node <= 0) + debug("exynos_fb: Can't get device node for fimd\n"); + + fimd_ctrl = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob, + node, "reg"); + if (fimd_ctrl == NULL) + debug("Can't get the FIMD base address\n"); +#else + fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd(); +#endif + + offset = exynos_fimd_get_base_offset(); + + /* store panel info to global variable */ + pvid = vid; + + rgb_mode = vid->rgb_mode; + + if (vid->interface_mode == FIMD_RGB_INTERFACE) { + cfg |= EXYNOS_VIDCON0_VIDOUT_RGB; + writel(cfg, &fimd_ctrl->vidcon0); + + cfg = readl(&fimd_ctrl->vidcon2); + cfg &= ~(EXYNOS_VIDCON2_WB_MASK | + EXYNOS_VIDCON2_TVFORMATSEL_MASK | + EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK); + cfg |= EXYNOS_VIDCON2_WB_DISABLE; + writel(cfg, &fimd_ctrl->vidcon2); + + /* set polarity */ + cfg = 0; + if (!pvid->vl_clkp) + cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE; + if (!pvid->vl_hsp) + cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT; + if (!pvid->vl_vsp) + cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT; + if (!pvid->vl_dp) + cfg |= EXYNOS_VIDCON1_IVDEN_INVERT; + + writel(cfg, (unsigned int)&fimd_ctrl->vidcon1 + offset); + + /* set timing */ + cfg = EXYNOS_VIDTCON0_VFPD(pvid->vl_vfpd - 1); + cfg |= EXYNOS_VIDTCON0_VBPD(pvid->vl_vbpd - 1); + cfg |= EXYNOS_VIDTCON0_VSPW(pvid->vl_vspw - 1); + writel(cfg, (unsigned int)&fimd_ctrl->vidtcon0 + offset); + + cfg = EXYNOS_VIDTCON1_HFPD(pvid->vl_hfpd - 1); + cfg |= EXYNOS_VIDTCON1_HBPD(pvid->vl_hbpd - 1); + cfg |= EXYNOS_VIDTCON1_HSPW(pvid->vl_hspw - 1); + + writel(cfg, (unsigned int)&fimd_ctrl->vidtcon1 + offset); + + /* set lcd size */ + cfg = EXYNOS_VIDTCON2_HOZVAL(pvid->vl_col - 1) | + EXYNOS_VIDTCON2_LINEVAL(pvid->vl_row - 1) | + EXYNOS_VIDTCON2_HOZVAL_E(pvid->vl_col - 1) | + EXYNOS_VIDTCON2_LINEVAL_E(pvid->vl_row - 1); + + writel(cfg, (unsigned int)&fimd_ctrl->vidtcon2 + offset); + } + + /* set display mode */ + cfg = readl(&fimd_ctrl->vidcon0); + cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK; + cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT); + writel(cfg, &fimd_ctrl->vidcon0); + + /* set par */ + exynos_fimd_set_par(pvid->win_id); + + /* set memory address */ + exynos_fimd_set_buffer_address(pvid->win_id); + + /* set buffer size */ + cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) | + EXYNOS_VIDADDR_PAGEWIDTH_E(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) | + EXYNOS_VIDADDR_OFFSIZE(0) | + EXYNOS_VIDADDR_OFFSIZE_E(0); + + writel(cfg, (unsigned int)&fimd_ctrl->vidw00add2 + + EXYNOS_BUFFER_SIZE(pvid->win_id)); + + /* set clock */ + exynos_fimd_set_clock(pvid); + + /* set rgb mode to dual lcd. */ + exynos_fimd_set_dualrgb(pvid->dual_lcd_enabled); + + /* display on */ + exynos_fimd_lcd_on(); + + /* window on */ + exynos_fimd_window_on(pvid->win_id); + + exynos_fimd_set_dp_clkcon(pvid->dp_enabled); +} + +unsigned long exynos_fimd_calc_fbsize(void) +{ + return pvid->vl_col * pvid->vl_row * (NBITS(pvid->vl_bpix) / 8); +} diff --git a/qemu/roms/u-boot/drivers/video/exynos_mipi_dsi.c b/qemu/roms/u-boot/drivers/video/exynos_mipi_dsi.c new file mode 100644 index 000000000..7dd465293 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/exynos_mipi_dsi.c @@ -0,0 +1,336 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: InKi Dae <inki.dae@samsung.com> + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <linux/err.h> +#include <asm/arch/dsim.h> +#include <asm/arch/mipi_dsim.h> +#include <asm/arch/power.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clk.h> + +#include "exynos_mipi_dsi_lowlevel.h" +#include "exynos_mipi_dsi_common.h" + +#define master_to_driver(a) (a->dsim_lcd_drv) +#define master_to_device(a) (a->dsim_lcd_dev) + +DECLARE_GLOBAL_DATA_PTR; + +static struct exynos_platform_mipi_dsim *dsim_pd; +#ifdef CONFIG_OF_CONTROL +static struct mipi_dsim_config dsim_config_dt; +static struct exynos_platform_mipi_dsim dsim_platform_data_dt; +static struct mipi_dsim_lcd_device mipi_lcd_device_dt; +#endif + +struct mipi_dsim_ddi { + int bus_id; + struct list_head list; + struct mipi_dsim_lcd_device *dsim_lcd_dev; + struct mipi_dsim_lcd_driver *dsim_lcd_drv; +}; + +static LIST_HEAD(dsim_ddi_list); +static LIST_HEAD(dsim_lcd_dev_list); + +int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device *lcd_dev) +{ + struct mipi_dsim_ddi *dsim_ddi; + + if (!lcd_dev) { + debug("mipi_dsim_lcd_device is NULL.\n"); + return -EFAULT; + } + + if (!lcd_dev->name) { + debug("dsim_lcd_device name is NULL.\n"); + return -EFAULT; + } + + dsim_ddi = kzalloc(sizeof(struct mipi_dsim_ddi), GFP_KERNEL); + if (!dsim_ddi) { + debug("failed to allocate dsim_ddi object.\n"); + return -EFAULT; + } + + dsim_ddi->dsim_lcd_dev = lcd_dev; + + list_add_tail(&dsim_ddi->list, &dsim_ddi_list); + + return 0; +} + +struct mipi_dsim_ddi + *exynos_mipi_dsi_find_lcd_device(struct mipi_dsim_lcd_driver *lcd_drv) +{ + struct mipi_dsim_ddi *dsim_ddi; + struct mipi_dsim_lcd_device *lcd_dev; + + list_for_each_entry(dsim_ddi, &dsim_ddi_list, list) { + lcd_dev = dsim_ddi->dsim_lcd_dev; + if (!lcd_dev) + continue; + + if (lcd_drv->id >= 0) { + if ((strcmp(lcd_drv->name, lcd_dev->name)) == 0 && + lcd_drv->id == lcd_dev->id) { + /** + * bus_id would be used to identify + * connected bus. + */ + dsim_ddi->bus_id = lcd_dev->bus_id; + + return dsim_ddi; + } + } else { + if ((strcmp(lcd_drv->name, lcd_dev->name)) == 0) { + /** + * bus_id would be used to identify + * connected bus. + */ + dsim_ddi->bus_id = lcd_dev->bus_id; + + return dsim_ddi; + } + } + + kfree(dsim_ddi); + list_del(&dsim_ddi_list); + } + + return NULL; +} + +int exynos_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver *lcd_drv) +{ + struct mipi_dsim_ddi *dsim_ddi; + + if (!lcd_drv) { + debug("mipi_dsim_lcd_driver is NULL.\n"); + return -EFAULT; + } + + if (!lcd_drv->name) { + debug("dsim_lcd_driver name is NULL.\n"); + return -EFAULT; + } + + dsim_ddi = exynos_mipi_dsi_find_lcd_device(lcd_drv); + if (!dsim_ddi) { + debug("mipi_dsim_ddi object not found.\n"); + return -EFAULT; + } + + dsim_ddi->dsim_lcd_drv = lcd_drv; + + debug("registered panel driver(%s) to mipi-dsi driver.\n", + lcd_drv->name); + + return 0; + +} + +struct mipi_dsim_ddi + *exynos_mipi_dsi_bind_lcd_ddi(struct mipi_dsim_device *dsim, + const char *name) +{ + struct mipi_dsim_ddi *dsim_ddi; + struct mipi_dsim_lcd_driver *lcd_drv; + struct mipi_dsim_lcd_device *lcd_dev; + + list_for_each_entry(dsim_ddi, &dsim_ddi_list, list) { + lcd_drv = dsim_ddi->dsim_lcd_drv; + lcd_dev = dsim_ddi->dsim_lcd_dev; + if (!lcd_drv || !lcd_dev) + continue; + + debug("lcd_drv->id = %d, lcd_dev->id = %d\n", + lcd_drv->id, lcd_dev->id); + + if ((strcmp(lcd_drv->name, name) == 0)) { + lcd_dev->master = dsim; + + dsim->dsim_lcd_dev = lcd_dev; + dsim->dsim_lcd_drv = lcd_drv; + + return dsim_ddi; + } + } + + return NULL; +} + +/* define MIPI-DSI Master operations. */ +static struct mipi_dsim_master_ops master_ops = { + .cmd_write = exynos_mipi_dsi_wr_data, + .get_dsim_frame_done = exynos_mipi_dsi_get_frame_done_status, + .clear_dsim_frame_done = exynos_mipi_dsi_clear_frame_done, +}; + +int exynos_mipi_dsi_init(void) +{ + struct mipi_dsim_device *dsim; + struct mipi_dsim_config *dsim_config; + struct mipi_dsim_ddi *dsim_ddi; + + dsim = kzalloc(sizeof(struct mipi_dsim_device), GFP_KERNEL); + if (!dsim) { + debug("failed to allocate dsim object.\n"); + return -EFAULT; + } + + /* get mipi_dsim_config. */ + dsim_config = dsim_pd->dsim_config; + if (dsim_config == NULL) { + debug("failed to get dsim config data.\n"); + return -EFAULT; + } + + dsim->pd = dsim_pd; + dsim->dsim_config = dsim_config; + dsim->master_ops = &master_ops; + + /* bind lcd ddi matched with panel name. */ + dsim_ddi = exynos_mipi_dsi_bind_lcd_ddi(dsim, dsim_pd->lcd_panel_name); + if (!dsim_ddi) { + debug("mipi_dsim_ddi object not found.\n"); + return -ENOSYS; + } + if (dsim_pd->lcd_power) + dsim_pd->lcd_power(); + + if (dsim_pd->mipi_power) + dsim_pd->mipi_power(); + + /* phy_enable(unsigned int dev_index, unsigned int enable) */ + if (dsim_pd->phy_enable) + dsim_pd->phy_enable(0, 1); + + set_mipi_clk(); + + exynos_mipi_dsi_init_dsim(dsim); + exynos_mipi_dsi_init_link(dsim); + exynos_mipi_dsi_set_hs_enable(dsim); + + /* set display timing. */ + exynos_mipi_dsi_set_display_mode(dsim, dsim->dsim_config); + + /* initialize mipi-dsi client(lcd panel). */ + if (dsim_ddi->dsim_lcd_drv && dsim_ddi->dsim_lcd_drv->mipi_panel_init) { + dsim_ddi->dsim_lcd_drv->mipi_panel_init(dsim); + dsim_ddi->dsim_lcd_drv->mipi_display_on(dsim); + } + + debug("mipi-dsi driver(%s mode) has been probed.\n", + (dsim_config->e_interface == DSIM_COMMAND) ? + "CPU" : "RGB"); + + return 0; +} + +void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd) +{ + if (pd == NULL) { + debug("pd is NULL\n"); + return; + } + + dsim_pd = pd; +} + +#ifdef CONFIG_OF_CONTROL +int exynos_dsim_config_parse_dt(const void *blob) +{ + int node; + + node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_MIPI_DSI); + if (node <= 0) { + printf("exynos_mipi_dsi: Can't get device node for mipi dsi\n"); + return -ENODEV; + } + + dsim_config_dt.e_interface = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-interface", 0); + + dsim_config_dt.e_virtual_ch = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-virtual-ch", 0); + + dsim_config_dt.e_pixel_format = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-pixel-format", 0); + + dsim_config_dt.e_burst_mode = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-burst-mode", 0); + + dsim_config_dt.e_no_data_lane = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-no-data-lane", 0); + + dsim_config_dt.e_byte_clk = fdtdec_get_int(blob, node, + "samsung,dsim-config-e-byte-clk", 0); + + dsim_config_dt.hfp = fdtdec_get_int(blob, node, + "samsung,dsim-config-hfp", 0); + + dsim_config_dt.p = fdtdec_get_int(blob, node, + "samsung,dsim-config-p", 0); + dsim_config_dt.m = fdtdec_get_int(blob, node, + "samsung,dsim-config-m", 0); + dsim_config_dt.s = fdtdec_get_int(blob, node, + "samsung,dsim-config-s", 0); + + dsim_config_dt.pll_stable_time = fdtdec_get_int(blob, node, + "samsung,dsim-config-pll-stable-time", 0); + + dsim_config_dt.esc_clk = fdtdec_get_int(blob, node, + "samsung,dsim-config-esc-clk", 0); + + dsim_config_dt.stop_holding_cnt = fdtdec_get_int(blob, node, + "samsung,dsim-config-stop-holding-cnt", 0); + + dsim_config_dt.bta_timeout = fdtdec_get_int(blob, node, + "samsung,dsim-config-bta-timeout", 0); + + dsim_config_dt.rx_timeout = fdtdec_get_int(blob, node, + "samsung,dsim-config-rx-timeout", 0); + + mipi_lcd_device_dt.name = fdtdec_get_config_string(blob, + "samsung,dsim-device-name"); + + mipi_lcd_device_dt.id = fdtdec_get_int(blob, node, + "samsung,dsim-device-id", 0); + + mipi_lcd_device_dt.bus_id = fdtdec_get_int(blob, node, + "samsung,dsim-device-bus_id", 0); + + mipi_lcd_device_dt.reverse_panel = fdtdec_get_int(blob, node, + "samsung,dsim-device-reverse-panel", 0); + + return 0; +} + +void exynos_init_dsim_platform_data(vidinfo_t *vid) +{ + if (exynos_dsim_config_parse_dt(gd->fdt_blob)) + debug("Can't get proper dsim config.\n"); + + strcpy(dsim_platform_data_dt.lcd_panel_name, mipi_lcd_device_dt.name); + dsim_platform_data_dt.dsim_config = &dsim_config_dt; + dsim_platform_data_dt.mipi_power = mipi_power; + dsim_platform_data_dt.phy_enable = set_mipi_phy_ctrl; + dsim_platform_data_dt.lcd_panel_info = (void *)vid; + + mipi_lcd_device_dt.platform_data = (void *)&dsim_platform_data_dt; + exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device_dt); + + dsim_pd = &dsim_platform_data_dt; +} +#endif diff --git a/qemu/roms/u-boot/drivers/video/exynos_mipi_dsi_common.c b/qemu/roms/u-boot/drivers/video/exynos_mipi_dsi_common.c new file mode 100644 index 000000000..925d51500 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/exynos_mipi_dsi_common.c @@ -0,0 +1,620 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: InKi Dae <inki.dae@samsung.com> + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <lcd.h> +#include <linux/err.h> +#include <asm/arch/dsim.h> +#include <asm/arch/mipi_dsim.h> + +#include "exynos_mipi_dsi_lowlevel.h" + +#define MHZ (1000 * 1000) +#define FIN_HZ (24 * MHZ) + +#define DFIN_PLL_MIN_HZ (6 * MHZ) +#define DFIN_PLL_MAX_HZ (12 * MHZ) + +#define DFVCO_MIN_HZ (500 * MHZ) +#define DFVCO_MAX_HZ (1000 * MHZ) + +#define TRY_GET_FIFO_TIMEOUT (5000 * 2) + +/* MIPI-DSIM status types. */ +enum { + DSIM_STATE_INIT, /* should be initialized. */ + DSIM_STATE_STOP, /* CPU and LCDC are LP mode. */ + DSIM_STATE_HSCLKEN, /* HS clock was enabled. */ + DSIM_STATE_ULPS +}; + +/* define DSI lane types. */ +enum { + DSIM_LANE_CLOCK = (1 << 0), + DSIM_LANE_DATA0 = (1 << 1), + DSIM_LANE_DATA1 = (1 << 2), + DSIM_LANE_DATA2 = (1 << 3), + DSIM_LANE_DATA3 = (1 << 4) +}; + +static unsigned int dpll_table[15] = { + 100, 120, 170, 220, 270, + 320, 390, 450, 510, 560, + 640, 690, 770, 870, 950 +}; + +static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim, + const unsigned char *data0, unsigned int data1) +{ + unsigned int data_cnt = 0, payload = 0; + + /* in case that data count is more then 4 */ + for (data_cnt = 0; data_cnt < data1; data_cnt += 4) { + /* + * after sending 4bytes per one time, + * send remainder data less then 4. + */ + if ((data1 - data_cnt) < 4) { + if ((data1 - data_cnt) == 3) { + payload = data0[data_cnt] | + data0[data_cnt + 1] << 8 | + data0[data_cnt + 2] << 16; + debug("count = 3 payload = %x, %x %x %x\n", + payload, data0[data_cnt], + data0[data_cnt + 1], + data0[data_cnt + 2]); + } else if ((data1 - data_cnt) == 2) { + payload = data0[data_cnt] | + data0[data_cnt + 1] << 8; + debug("count = 2 payload = %x, %x %x\n", payload, + data0[data_cnt], data0[data_cnt + 1]); + } else if ((data1 - data_cnt) == 1) { + payload = data0[data_cnt]; + } + } else { + /* send 4bytes per one time. */ + payload = data0[data_cnt] | + data0[data_cnt + 1] << 8 | + data0[data_cnt + 2] << 16 | + data0[data_cnt + 3] << 24; + + debug("count = 4 payload = %x, %x %x %x %x\n", + payload, *(u8 *)(data0 + data_cnt), + data0[data_cnt + 1], + data0[data_cnt + 2], + data0[data_cnt + 3]); + } + exynos_mipi_dsi_wr_tx_data(dsim, payload); + } +} + +int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id, + const unsigned char *data0, unsigned int data1) +{ + unsigned int timeout = TRY_GET_FIFO_TIMEOUT; + unsigned long delay_val, delay; + unsigned int check_rx_ack = 0; + + if (dsim->state == DSIM_STATE_ULPS) { + debug("state is ULPS.\n"); + + return -EINVAL; + } + + delay_val = MHZ / dsim->dsim_config->esc_clk; + delay = 10 * delay_val; + + mdelay(delay); + + /* only if transfer mode is LPDT, wait SFR becomes empty. */ + if (dsim->state == DSIM_STATE_STOP) { + while (!(exynos_mipi_dsi_get_fifo_state(dsim) & + SFR_HEADER_EMPTY)) { + if ((timeout--) > 0) + mdelay(1); + else { + debug("SRF header fifo is not empty.\n"); + return -EINVAL; + } + } + } + + switch (data_id) { + /* short packet types of packet types for command. */ + case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: + case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: + case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: + case MIPI_DSI_DCS_SHORT_WRITE: + case MIPI_DSI_DCS_SHORT_WRITE_PARAM: + case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: + debug("data0 = %x data1 = %x\n", + data0[0], data0[1]); + exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]); + if (check_rx_ack) { + /* process response func should be implemented */ + return 0; + } else { + return -EINVAL; + } + + /* general command */ + case MIPI_DSI_COLOR_MODE_OFF: + case MIPI_DSI_COLOR_MODE_ON: + case MIPI_DSI_SHUTDOWN_PERIPHERAL: + case MIPI_DSI_TURN_ON_PERIPHERAL: + exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]); + if (check_rx_ack) { + /* process response func should be implemented. */ + return 0; + } else { + return -EINVAL; + } + + /* packet types for video data */ + case MIPI_DSI_V_SYNC_START: + case MIPI_DSI_V_SYNC_END: + case MIPI_DSI_H_SYNC_START: + case MIPI_DSI_H_SYNC_END: + case MIPI_DSI_END_OF_TRANSMISSION: + return 0; + + /* short and response packet types for command */ + case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: + case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: + case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: + case MIPI_DSI_DCS_READ: + exynos_mipi_dsi_clear_all_interrupt(dsim); + exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]); + /* process response func should be implemented. */ + return 0; + + /* long packet type and null packet */ + case MIPI_DSI_NULL_PACKET: + case MIPI_DSI_BLANKING_PACKET: + return 0; + case MIPI_DSI_GENERIC_LONG_WRITE: + case MIPI_DSI_DCS_LONG_WRITE: + { + unsigned int payload = 0; + + /* if data count is less then 4, then send 3bytes data. */ + if (data1 < 4) { + payload = data0[0] | + data0[1] << 8 | + data0[2] << 16; + + exynos_mipi_dsi_wr_tx_data(dsim, payload); + + debug("count = %d payload = %x,%x %x %x\n", + data1, payload, data0[0], + data0[1], data0[2]); + } else { + /* in case that data count is more then 4 */ + exynos_mipi_dsi_long_data_wr(dsim, data0, data1); + } + + /* put data into header fifo */ + exynos_mipi_dsi_wr_tx_header(dsim, data_id, data1 & 0xff, + (data1 & 0xff00) >> 8); + + } + if (check_rx_ack) + /* process response func should be implemented. */ + return 0; + else + return -EINVAL; + + /* packet typo for video data */ + case MIPI_DSI_PACKED_PIXEL_STREAM_16: + case MIPI_DSI_PACKED_PIXEL_STREAM_18: + case MIPI_DSI_PIXEL_STREAM_3BYTE_18: + case MIPI_DSI_PACKED_PIXEL_STREAM_24: + if (check_rx_ack) { + /* process response func should be implemented. */ + return 0; + } else { + return -EINVAL; + } + default: + debug("data id %x is not supported current DSI spec.\n", + data_id); + + return -EINVAL; + } + + return 0; +} + +int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, unsigned int enable) +{ + int sw_timeout; + + if (enable) { + sw_timeout = 1000; + + exynos_mipi_dsi_clear_interrupt(dsim); + exynos_mipi_dsi_enable_pll(dsim, 1); + while (1) { + sw_timeout--; + if (exynos_mipi_dsi_is_pll_stable(dsim)) + return 0; + if (sw_timeout == 0) + return -EINVAL; + } + } else + exynos_mipi_dsi_enable_pll(dsim, 0); + + return 0; +} + +unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim, + unsigned int pre_divider, unsigned int main_divider, + unsigned int scaler) +{ + unsigned long dfin_pll, dfvco, dpll_out; + unsigned int i, freq_band = 0xf; + + dfin_pll = (FIN_HZ / pre_divider); + + /****************************************************** + * Serial Clock(=ByteClk X 8) FreqBand[3:0] * + ****************************************************** + * ~ 99.99 MHz 0000 + * 100 ~ 119.99 MHz 0001 + * 120 ~ 159.99 MHz 0010 + * 160 ~ 199.99 MHz 0011 + * 200 ~ 239.99 MHz 0100 + * 140 ~ 319.99 MHz 0101 + * 320 ~ 389.99 MHz 0110 + * 390 ~ 449.99 MHz 0111 + * 450 ~ 509.99 MHz 1000 + * 510 ~ 559.99 MHz 1001 + * 560 ~ 639.99 MHz 1010 + * 640 ~ 689.99 MHz 1011 + * 690 ~ 769.99 MHz 1100 + * 770 ~ 869.99 MHz 1101 + * 870 ~ 949.99 MHz 1110 + * 950 ~ 1000 MHz 1111 + ******************************************************/ + if (dfin_pll < DFIN_PLL_MIN_HZ || dfin_pll > DFIN_PLL_MAX_HZ) { + debug("fin_pll range should be 6MHz ~ 12MHz\n"); + exynos_mipi_dsi_enable_afc(dsim, 0, 0); + } else { + if (dfin_pll < 7 * MHZ) + exynos_mipi_dsi_enable_afc(dsim, 1, 0x1); + else if (dfin_pll < 8 * MHZ) + exynos_mipi_dsi_enable_afc(dsim, 1, 0x0); + else if (dfin_pll < 9 * MHZ) + exynos_mipi_dsi_enable_afc(dsim, 1, 0x3); + else if (dfin_pll < 10 * MHZ) + exynos_mipi_dsi_enable_afc(dsim, 1, 0x2); + else if (dfin_pll < 11 * MHZ) + exynos_mipi_dsi_enable_afc(dsim, 1, 0x5); + else + exynos_mipi_dsi_enable_afc(dsim, 1, 0x4); + } + + dfvco = dfin_pll * main_divider; + debug("dfvco = %lu, dfin_pll = %lu, main_divider = %d\n", + dfvco, dfin_pll, main_divider); + if (dfvco < DFVCO_MIN_HZ || dfvco > DFVCO_MAX_HZ) + debug("fvco range should be 500MHz ~ 1000MHz\n"); + + dpll_out = dfvco / (1 << scaler); + debug("dpll_out = %lu, dfvco = %lu, scaler = %d\n", + dpll_out, dfvco, scaler); + + for (i = 0; i < ARRAY_SIZE(dpll_table); i++) { + if (dpll_out < dpll_table[i] * MHZ) { + freq_band = i; + break; + } + } + + debug("freq_band = %d\n", freq_band); + + exynos_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler); + + exynos_mipi_dsi_hs_zero_ctrl(dsim, 0); + exynos_mipi_dsi_prep_ctrl(dsim, 0); + + /* Freq Band */ + exynos_mipi_dsi_pll_freq_band(dsim, freq_band); + + /* Stable time */ + exynos_mipi_dsi_pll_stable_time(dsim, + dsim->dsim_config->pll_stable_time); + + /* Enable PLL */ + debug("FOUT of mipi dphy pll is %luMHz\n", + (dpll_out / MHZ)); + + return dpll_out; +} + +int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim, + unsigned int byte_clk_sel, unsigned int enable) +{ + unsigned int esc_div; + unsigned long esc_clk_error_rate; + unsigned long hs_clk = 0, byte_clk = 0, escape_clk = 0; + + if (enable) { + dsim->e_clk_src = byte_clk_sel; + + /* Escape mode clock and byte clock source */ + exynos_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel); + + /* DPHY, DSIM Link : D-PHY clock out */ + if (byte_clk_sel == DSIM_PLL_OUT_DIV8) { + hs_clk = exynos_mipi_dsi_change_pll(dsim, + dsim->dsim_config->p, dsim->dsim_config->m, + dsim->dsim_config->s); + if (hs_clk == 0) { + debug("failed to get hs clock.\n"); + return -EINVAL; + } + + byte_clk = hs_clk / 8; + exynos_mipi_dsi_enable_pll_bypass(dsim, 0); + exynos_mipi_dsi_pll_on(dsim, 1); + /* DPHY : D-PHY clock out, DSIM link : external clock out */ + } else if (byte_clk_sel == DSIM_EXT_CLK_DIV8) + debug("not support EXT CLK source for MIPI DSIM\n"); + else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS) + debug("not support EXT CLK source for MIPI DSIM\n"); + + /* escape clock divider */ + esc_div = byte_clk / (dsim->dsim_config->esc_clk); + debug("esc_div = %d, byte_clk = %lu, esc_clk = %lu\n", + esc_div, byte_clk, dsim->dsim_config->esc_clk); + if ((byte_clk / esc_div) >= (20 * MHZ) || + (byte_clk / esc_div) > dsim->dsim_config->esc_clk) + esc_div += 1; + + escape_clk = byte_clk / esc_div; + debug("escape_clk = %lu, byte_clk = %lu, esc_div = %d\n", + escape_clk, byte_clk, esc_div); + + /* enable escape clock. */ + exynos_mipi_dsi_enable_byte_clock(dsim, 1); + + /* enable byte clk and escape clock */ + exynos_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div); + /* escape clock on lane */ + exynos_mipi_dsi_enable_esc_clk_on_lane(dsim, + (DSIM_LANE_CLOCK | dsim->data_lane), 1); + + debug("byte clock is %luMHz\n", + (byte_clk / MHZ)); + debug("escape clock that user's need is %lu\n", + (dsim->dsim_config->esc_clk / MHZ)); + debug("escape clock divider is %x\n", esc_div); + debug("escape clock is %luMHz\n", + ((byte_clk / esc_div) / MHZ)); + + if ((byte_clk / esc_div) > escape_clk) { + esc_clk_error_rate = escape_clk / + (byte_clk / esc_div); + debug("error rate is %lu over.\n", + (esc_clk_error_rate / 100)); + } else if ((byte_clk / esc_div) < (escape_clk)) { + esc_clk_error_rate = (byte_clk / esc_div) / + escape_clk; + debug("error rate is %lu under.\n", + (esc_clk_error_rate / 100)); + } + } else { + exynos_mipi_dsi_enable_esc_clk_on_lane(dsim, + (DSIM_LANE_CLOCK | dsim->data_lane), 0); + exynos_mipi_dsi_set_esc_clk_prs(dsim, 0, 0); + + /* disable escape clock. */ + exynos_mipi_dsi_enable_byte_clock(dsim, 0); + + if (byte_clk_sel == DSIM_PLL_OUT_DIV8) + exynos_mipi_dsi_pll_on(dsim, 0); + } + + return 0; +} + +int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim) +{ + dsim->state = DSIM_STATE_INIT; + + switch (dsim->dsim_config->e_no_data_lane) { + case DSIM_DATA_LANE_1: + dsim->data_lane = DSIM_LANE_DATA0; + break; + case DSIM_DATA_LANE_2: + dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1; + break; + case DSIM_DATA_LANE_3: + dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 | + DSIM_LANE_DATA2; + break; + case DSIM_DATA_LANE_4: + dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 | + DSIM_LANE_DATA2 | DSIM_LANE_DATA3; + break; + default: + debug("data lane is invalid.\n"); + return -EINVAL; + }; + + exynos_mipi_dsi_sw_reset(dsim); + exynos_mipi_dsi_dp_dn_swap(dsim, 0); + + return 0; +} + +int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim, + unsigned int enable) +{ + /* enable only frame done interrupt */ + exynos_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable); + + return 0; +} + +static void convert_to_fb_videomode(struct fb_videomode *mode1, + vidinfo_t *mode2) +{ + mode1->xres = mode2->vl_width; + mode1->yres = mode2->vl_height; + mode1->upper_margin = mode2->vl_vfpd; + mode1->lower_margin = mode2->vl_vbpd; + mode1->left_margin = mode2->vl_hfpd; + mode1->right_margin = mode2->vl_hbpd; + mode1->vsync_len = mode2->vl_vspw; + mode1->hsync_len = mode2->vl_hspw; +} + +int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim, + struct mipi_dsim_config *dsim_config) +{ + struct exynos_platform_mipi_dsim *dsim_pd; + struct fb_videomode lcd_video; + vidinfo_t *vid; + + dsim_pd = (struct exynos_platform_mipi_dsim *)dsim->pd; + vid = (vidinfo_t *)dsim_pd->lcd_panel_info; + + convert_to_fb_videomode(&lcd_video, vid); + + /* in case of VIDEO MODE (RGB INTERFACE), it sets polarities. */ + if (dsim->dsim_config->e_interface == (u32) DSIM_VIDEO) { + if (dsim->dsim_config->auto_vertical_cnt == 0) { + exynos_mipi_dsi_set_main_disp_vporch(dsim, + vid->vl_cmd_allow_len, + lcd_video.upper_margin, + lcd_video.lower_margin); + exynos_mipi_dsi_set_main_disp_hporch(dsim, + lcd_video.left_margin, + lcd_video.right_margin); + exynos_mipi_dsi_set_main_disp_sync_area(dsim, + lcd_video.vsync_len, + lcd_video.hsync_len); + } + } + + exynos_mipi_dsi_set_main_disp_resol(dsim, lcd_video.xres, + lcd_video.yres); + + exynos_mipi_dsi_display_config(dsim, dsim->dsim_config); + + debug("lcd panel ==> width = %d, height = %d\n", + lcd_video.xres, lcd_video.yres); + + return 0; +} + +int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim) +{ + unsigned int time_out = 100; + + switch (dsim->state) { + case DSIM_STATE_INIT: + exynos_mipi_dsi_init_fifo_pointer(dsim, 0x1f); + + /* dsi configuration */ + exynos_mipi_dsi_init_config(dsim); + exynos_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1); + exynos_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1); + + /* set clock configuration */ + exynos_mipi_dsi_set_clock(dsim, + dsim->dsim_config->e_byte_clk, 1); + + /* check clock and data lane state are stop state */ + while (!(exynos_mipi_dsi_is_lane_state(dsim))) { + time_out--; + if (time_out == 0) { + debug("DSI Master is not stop state.\n"); + debug("Check initialization process\n"); + + return -EINVAL; + } + } + + dsim->state = DSIM_STATE_STOP; + + /* BTA sequence counters */ + exynos_mipi_dsi_set_stop_state_counter(dsim, + dsim->dsim_config->stop_holding_cnt); + exynos_mipi_dsi_set_bta_timeout(dsim, + dsim->dsim_config->bta_timeout); + exynos_mipi_dsi_set_lpdr_timeout(dsim, + dsim->dsim_config->rx_timeout); + + return 0; + default: + debug("DSI Master is already init.\n"); + return 0; + } + + return 0; +} + +int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim) +{ + if (dsim->state == DSIM_STATE_STOP) { + if (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) { + dsim->state = DSIM_STATE_HSCLKEN; + + /* set LCDC and CPU transfer mode to HS. */ + exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0); + exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0); + + exynos_mipi_dsi_enable_hs_clock(dsim, 1); + + return 0; + } else + debug("clock source is external bypass.\n"); + } else + debug("DSIM is not stop state.\n"); + + return 0; +} + +int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim, + unsigned int mode) +{ + if (mode) { + if (dsim->state != DSIM_STATE_HSCLKEN) { + debug("HS Clock lane is not enabled.\n"); + return -EINVAL; + } + + exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0); + } else { + if (dsim->state == DSIM_STATE_INIT || dsim->state == + DSIM_STATE_ULPS) { + debug("DSI Master is not STOP or HSDT state.\n"); + return -EINVAL; + } + + exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0); + } + + return 0; +} + +int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim) +{ + return _exynos_mipi_dsi_get_frame_done_status(dsim); +} + +int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim) +{ + _exynos_mipi_dsi_clear_frame_done(dsim); + + return 0; +} diff --git a/qemu/roms/u-boot/drivers/video/exynos_mipi_dsi_common.h b/qemu/roms/u-boot/drivers/video/exynos_mipi_dsi_common.h new file mode 100644 index 000000000..98eb78e5f --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/exynos_mipi_dsi_common.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: InKi Dae <inki.dae@samsung.com> + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/fb.h> + +#ifndef _EXYNOS_MIPI_DSI_COMMON_H +#define _EXYNOS_MIPI_DSI_COMMON_H + +int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id, + const unsigned char *data0, unsigned int data1); +int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, unsigned int enable); +unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim, + unsigned int pre_divider, unsigned int main_divider, + unsigned int scaler); +int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim, + unsigned int byte_clk_sel, unsigned int enable); +int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim); +int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim, + struct mipi_dsim_config *dsim_info); +int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim); +int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim); +int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim, + unsigned int mode); +int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim, + unsigned int enable); +int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim); +int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim); + +#endif /* _EXYNOS_MIPI_DSI_COMMON_H */ diff --git a/qemu/roms/u-boot/drivers/video/exynos_mipi_dsi_lowlevel.c b/qemu/roms/u-boot/drivers/video/exynos_mipi_dsi_lowlevel.c new file mode 100644 index 000000000..fcfdc8d12 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/exynos_mipi_dsi_lowlevel.c @@ -0,0 +1,639 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: InKi Dae <inki.dae@samsung.com> + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/dsim.h> +#include <asm/arch/mipi_dsim.h> +#include <asm/arch/power.h> +#include <asm/arch/cpu.h> + +#include "exynos_mipi_dsi_lowlevel.h" +#include "exynos_mipi_dsi_common.h" + +void exynos_mipi_dsi_func_reset(struct mipi_dsim_device *dsim) +{ + unsigned int reg; + + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + + reg = readl(&mipi_dsim->swrst); + + reg |= DSIM_FUNCRST; + + writel(reg, &mipi_dsim->swrst); +} + +void exynos_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim) +{ + unsigned int reg = 0; + + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + + reg = readl(&mipi_dsim->swrst); + + reg |= DSIM_SWRST; + reg |= DSIM_FUNCRST; + + writel(reg, &mipi_dsim->swrst); +} + +void exynos_mipi_dsi_sw_release(struct mipi_dsim_device *dsim) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = readl(&mipi_dsim->intsrc); + + reg |= INTSRC_SWRST_RELEASE; + + writel(reg, &mipi_dsim->intsrc); +} + +void exynos_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim, + unsigned int mode, unsigned int mask) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = readl(&mipi_dsim->intmsk); + + if (mask) + reg |= mode; + else + reg &= ~mode; + + writel(reg, &mipi_dsim->intmsk); +} + +void exynos_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim, + unsigned int cfg) +{ + unsigned int reg; + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + + reg = readl(&mipi_dsim->fifoctrl); + + writel(reg & ~(cfg), &mipi_dsim->fifoctrl); + udelay(10 * 1000); + reg |= cfg; + + writel(reg, &mipi_dsim->fifoctrl); +} + +/* + * this function set PLL P, M and S value in D-PHY + */ +void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim, + unsigned int value) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + + writel(DSIM_AFC_CTL(value), &mipi_dsim->phyacchr); +} + +void exynos_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim, + unsigned int width_resol, unsigned int height_resol) +{ + unsigned int reg; + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + + /* standby should be set after configuration so set to not ready*/ + reg = (readl(&mipi_dsim->mdresol)) & ~(DSIM_MAIN_STAND_BY); + writel(reg, &mipi_dsim->mdresol); + + /* reset resolution */ + reg &= ~(DSIM_MAIN_VRESOL(0x7ff) | DSIM_MAIN_HRESOL(0x7ff)); + reg |= DSIM_MAIN_VRESOL(height_resol) | DSIM_MAIN_HRESOL(width_resol); + + reg |= DSIM_MAIN_STAND_BY; + writel(reg, &mipi_dsim->mdresol); +} + +void exynos_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim, + unsigned int cmd_allow, unsigned int vfront, unsigned int vback) +{ + unsigned int reg; + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + + reg = (readl(&mipi_dsim->mvporch)) & + ~((DSIM_CMD_ALLOW_MASK) | (DSIM_STABLE_VFP_MASK) | + (DSIM_MAIN_VBP_MASK)); + + reg |= ((cmd_allow & 0xf) << DSIM_CMD_ALLOW_SHIFT) | + ((vfront & 0x7ff) << DSIM_STABLE_VFP_SHIFT) | + ((vback & 0x7ff) << DSIM_MAIN_VBP_SHIFT); + + writel(reg, &mipi_dsim->mvporch); +} + +void exynos_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim, + unsigned int front, unsigned int back) +{ + unsigned int reg; + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + + reg = (readl(&mipi_dsim->mhporch)) & + ~((DSIM_MAIN_HFP_MASK) | (DSIM_MAIN_HBP_MASK)); + + reg |= (front << DSIM_MAIN_HFP_SHIFT) | (back << DSIM_MAIN_HBP_SHIFT); + + writel(reg, &mipi_dsim->mhporch); +} + +void exynos_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim, + unsigned int vert, unsigned int hori) +{ + unsigned int reg; + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + + reg = (readl(&mipi_dsim->msync)) & + ~((DSIM_MAIN_VSA_MASK) | (DSIM_MAIN_HSA_MASK)); + + reg |= ((vert & 0x3ff) << DSIM_MAIN_VSA_SHIFT) | + (hori << DSIM_MAIN_HSA_SHIFT); + + writel(reg, &mipi_dsim->msync); +} + +void exynos_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim, + unsigned int vert, unsigned int hori) +{ + unsigned int reg; + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + + reg = (readl(&mipi_dsim->sdresol)) & + ~(DSIM_SUB_STANDY_MASK); + + writel(reg, &mipi_dsim->sdresol); + + reg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK); + reg |= ((vert & 0x7ff) << DSIM_SUB_VRESOL_SHIFT) | + ((hori & 0x7ff) << DSIM_SUB_HRESOL_SHIFT); + writel(reg, &mipi_dsim->sdresol); + + /* DSIM STANDBY */ + reg |= (1 << DSIM_SUB_STANDY_SHIFT); + writel(reg, &mipi_dsim->sdresol); +} + +void exynos_mipi_dsi_init_config(struct mipi_dsim_device *dsim) +{ + struct mipi_dsim_config *dsim_config = dsim->dsim_config; + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int cfg = (readl(&mipi_dsim->config)) & + ~((1 << DSIM_EOT_PACKET_SHIFT) | + (0x1f << DSIM_HSA_MODE_SHIFT) | + (0x3 << DSIM_NUM_OF_DATALANE_SHIFT)); + + cfg |= (dsim_config->auto_flush << DSIM_AUTO_FLUSH_SHIFT) | + (dsim_config->eot_disable << DSIM_EOT_PACKET_SHIFT) | + (dsim_config->auto_vertical_cnt << DSIM_AUTO_MODE_SHIFT) | + (dsim_config->hse << DSIM_HSE_MODE_SHIFT) | + (dsim_config->hfp << DSIM_HFP_MODE_SHIFT) | + (dsim_config->hbp << DSIM_HBP_MODE_SHIFT) | + (dsim_config->hsa << DSIM_HSA_MODE_SHIFT) | + (dsim_config->e_no_data_lane << DSIM_NUM_OF_DATALANE_SHIFT); + + writel(cfg, &mipi_dsim->config); +} + +void exynos_mipi_dsi_display_config(struct mipi_dsim_device *dsim, + struct mipi_dsim_config *dsim_config) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + + u32 reg = (readl(&mipi_dsim->config)) & + ~((0x3 << DSIM_BURST_MODE_SHIFT) | (1 << DSIM_VIDEO_MODE_SHIFT) + | (0x3 << DSIM_MAINVC_SHIFT) | (0x7 << DSIM_MAINPIX_SHIFT) + | (0x3 << DSIM_SUBVC_SHIFT) | (0x7 << DSIM_SUBPIX_SHIFT)); + + if (dsim_config->e_interface == DSIM_VIDEO) + reg |= (1 << DSIM_VIDEO_MODE_SHIFT); + else if (dsim_config->e_interface == DSIM_COMMAND) + reg &= ~(1 << DSIM_VIDEO_MODE_SHIFT); + else { + printf("unknown lcd type.\n"); + return; + } + + /* main lcd */ + reg |= ((u8) (dsim_config->e_burst_mode) & 0x3) << DSIM_BURST_MODE_SHIFT + | ((u8) (dsim_config->e_virtual_ch) & 0x3) << DSIM_MAINVC_SHIFT + | ((u8) (dsim_config->e_pixel_format) & 0x7) << DSIM_MAINPIX_SHIFT; + + writel(reg, &mipi_dsim->config); +} + +void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, + unsigned int lane, unsigned int enable) +{ + unsigned int reg; + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + + reg = readl(&mipi_dsim->config); + + if (enable) + reg |= DSIM_LANE_ENx(lane); + else + reg &= ~DSIM_LANE_ENx(lane); + + writel(reg, &mipi_dsim->config); +} + +void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim, + unsigned int count) +{ + unsigned int cfg; + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + + /* get the data lane number. */ + cfg = DSIM_NUM_OF_DATA_LANE(count); + + writel(cfg, &mipi_dsim->config); +} + +void exynos_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim, + unsigned int enable, unsigned int afc_code) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = readl(&mipi_dsim->phyacchr); + + reg = 0; + + if (enable) { + reg |= DSIM_AFC_EN; + reg &= ~(0x7 << DSIM_AFC_CTL_SHIFT); + reg |= DSIM_AFC_CTL(afc_code); + } else + reg &= ~DSIM_AFC_EN; + + writel(reg, &mipi_dsim->phyacchr); +} + +void exynos_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim, + unsigned int enable) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = (readl(&mipi_dsim->clkctrl)) & + ~(DSIM_PLL_BYPASS_EXTERNAL); + + reg |= enable << DSIM_PLL_BYPASS_SHIFT; + + writel(reg, &mipi_dsim->clkctrl); +} + +void exynos_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim, + unsigned int freq_band) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = (readl(&mipi_dsim->pllctrl)) & + ~(0x1f << DSIM_FREQ_BAND_SHIFT); + + reg |= ((freq_band & 0x1f) << DSIM_FREQ_BAND_SHIFT); + + writel(reg, &mipi_dsim->pllctrl); +} + +void exynos_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim, + unsigned int pre_divider, unsigned int main_divider, + unsigned int scaler) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = (readl(&mipi_dsim->pllctrl)) & + ~(0x7ffff << 1); + + reg |= ((pre_divider & 0x3f) << DSIM_PREDIV_SHIFT) | + ((main_divider & 0x1ff) << DSIM_MAIN_SHIFT) | + ((scaler & 0x7) << DSIM_SCALER_SHIFT); + + writel(reg, &mipi_dsim->pllctrl); +} + +void exynos_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim, + unsigned int lock_time) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + + writel(lock_time, &mipi_dsim->plltmr); +} + +void exynos_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim, + unsigned int enable) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = (readl(&mipi_dsim->pllctrl)) & + ~(0x1 << DSIM_PLL_EN_SHIFT); + + reg |= ((enable & 0x1) << DSIM_PLL_EN_SHIFT); + + writel(reg, &mipi_dsim->pllctrl); +} + +void exynos_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim, + unsigned int src) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = (readl(&mipi_dsim->clkctrl)) & + ~(0x3 << DSIM_BYTE_CLK_SRC_SHIFT); + + reg |= ((unsigned int) src) << DSIM_BYTE_CLK_SRC_SHIFT; + + writel(reg, &mipi_dsim->clkctrl); +} + +void exynos_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim, + unsigned int enable) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = (readl(&mipi_dsim->clkctrl)) & + ~(1 << DSIM_BYTE_CLKEN_SHIFT); + + reg |= enable << DSIM_BYTE_CLKEN_SHIFT; + + writel(reg, &mipi_dsim->clkctrl); +} + +void exynos_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim, + unsigned int enable, unsigned int prs_val) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = (readl(&mipi_dsim->clkctrl)) & + ~((1 << DSIM_ESC_CLKEN_SHIFT) | (0xffff)); + + reg |= enable << DSIM_ESC_CLKEN_SHIFT; + if (enable) + reg |= prs_val; + + writel(reg, &mipi_dsim->clkctrl); +} + +void exynos_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim, + unsigned int lane_sel, unsigned int enable) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = readl(&mipi_dsim->clkctrl); + + if (enable) + reg |= DSIM_LANE_ESC_CLKEN(lane_sel); + else + reg &= ~DSIM_LANE_ESC_CLKEN(lane_sel); + + writel(reg, &mipi_dsim->clkctrl); +} + +void exynos_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim, + unsigned int enable) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = (readl(&mipi_dsim->escmode)) & + ~(0x1 << DSIM_FORCE_STOP_STATE_SHIFT); + + reg |= ((enable & 0x1) << DSIM_FORCE_STOP_STATE_SHIFT); + + writel(reg, &mipi_dsim->escmode); +} + +unsigned int exynos_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = readl(&mipi_dsim->status); + + /** + * check clock and data lane states. + * if MIPI-DSI controller was enabled at bootloader then + * TX_READY_HS_CLK is enabled otherwise STOP_STATE_CLK. + * so it should be checked for two case. + */ + if ((reg & DSIM_STOP_STATE_DAT(0xf)) && + ((reg & DSIM_STOP_STATE_CLK) || + (reg & DSIM_TX_READY_HS_CLK))) + return 1; + else + return 0; +} + +void exynos_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim, + unsigned int cnt_val) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = (readl(&mipi_dsim->escmode)) & + ~(0x7ff << DSIM_STOP_STATE_CNT_SHIFT); + + reg |= ((cnt_val & 0x7ff) << DSIM_STOP_STATE_CNT_SHIFT); + + writel(reg, &mipi_dsim->escmode); +} + +void exynos_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim, + unsigned int timeout) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = (readl(&mipi_dsim->timeout)) & + ~(0xff << DSIM_BTA_TOUT_SHIFT); + + reg |= (timeout << DSIM_BTA_TOUT_SHIFT); + + writel(reg, &mipi_dsim->timeout); +} + +void exynos_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim, + unsigned int timeout) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = (readl(&mipi_dsim->timeout)) & + ~(0xffff << DSIM_LPDR_TOUT_SHIFT); + + reg |= (timeout << DSIM_LPDR_TOUT_SHIFT); + + writel(reg, &mipi_dsim->timeout); +} + +void exynos_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim, + unsigned int lp) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = readl(&mipi_dsim->escmode); + + reg &= ~DSIM_CMD_LPDT_LP; + + if (lp) + reg |= DSIM_CMD_LPDT_LP; + + writel(reg, &mipi_dsim->escmode); +} + +void exynos_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim, + unsigned int lp) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = readl(&mipi_dsim->escmode); + + reg &= ~DSIM_TX_LPDT_LP; + + if (lp) + reg |= DSIM_TX_LPDT_LP; + + writel(reg, &mipi_dsim->escmode); +} + +void exynos_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim, + unsigned int enable) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = (readl(&mipi_dsim->clkctrl)) & + ~(1 << DSIM_TX_REQUEST_HSCLK_SHIFT); + + reg |= enable << DSIM_TX_REQUEST_HSCLK_SHIFT; + + writel(reg, &mipi_dsim->clkctrl); +} + +void exynos_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim, + unsigned int swap_en) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = readl(&mipi_dsim->phyacchr1); + + reg &= ~(0x3 << DSIM_DPDN_SWAP_DATA_SHIFT); + reg |= (swap_en & 0x3) << DSIM_DPDN_SWAP_DATA_SHIFT; + + writel(reg, &mipi_dsim->phyacchr1); +} + +void exynos_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim, + unsigned int hs_zero) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = (readl(&mipi_dsim->pllctrl)) & + ~(0xf << DSIM_ZEROCTRL_SHIFT); + + reg |= ((hs_zero & 0xf) << DSIM_ZEROCTRL_SHIFT); + + writel(reg, &mipi_dsim->pllctrl); +} + +void exynos_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim, unsigned int prep) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = (readl(&mipi_dsim->pllctrl)) & + ~(0x7 << DSIM_PRECTRL_SHIFT); + + reg |= ((prep & 0x7) << DSIM_PRECTRL_SHIFT); + + writel(reg, &mipi_dsim->pllctrl); +} + +void exynos_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = readl(&mipi_dsim->intsrc); + + reg |= INTSRC_PLL_STABLE; + + writel(reg, &mipi_dsim->intsrc); +} + +void exynos_mipi_dsi_clear_all_interrupt(struct mipi_dsim_device *dsim) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + + writel(0xffffffff, &mipi_dsim->intsrc); +} + +unsigned int exynos_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim) +{ + unsigned int reg; + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + + reg = readl(&mipi_dsim->status); + + return reg & DSIM_PLL_STABLE ? 1 : 0; +} + +unsigned int exynos_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + + return readl(&mipi_dsim->fifoctrl) & ~(0x1f); +} + +void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim, + unsigned int di, const unsigned char data0, const unsigned char data1) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = (DSIM_PKTHDR_DAT1(data1) | DSIM_PKTHDR_DAT0(data0) | + DSIM_PKTHDR_DI(di)); + + writel(reg, &mipi_dsim->pkthdr); +} + +unsigned int _exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device + *dsim) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = readl(&mipi_dsim->intsrc); + + return (reg & INTSRC_FRAME_DONE) ? 1 : 0; +} + +void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + unsigned int reg = readl(&mipi_dsim->intsrc); + + writel(reg | INTSRC_FRAME_DONE, &mipi_dsim->intsrc); +} + +void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim, + unsigned int tx_data) +{ + struct exynos_mipi_dsim *mipi_dsim = + (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim(); + + writel(tx_data, &mipi_dsim->payload); +} diff --git a/qemu/roms/u-boot/drivers/video/exynos_mipi_dsi_lowlevel.h b/qemu/roms/u-boot/drivers/video/exynos_mipi_dsi_lowlevel.h new file mode 100644 index 000000000..0bede25e4 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/exynos_mipi_dsi_lowlevel.h @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: InKi Dae <inki.dae@samsung.com> + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _EXYNOS_MIPI_DSI_LOWLEVEL_H +#define _EXYNOS_MIPI_DSI_LOWLEVEL_H + +void exynos_mipi_dsi_register(struct mipi_dsim_device *dsim); +void exynos_mipi_dsi_func_reset(struct mipi_dsim_device *dsim); +void exynos_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim); +void exynos_mipi_dsi_sw_release(struct mipi_dsim_device *dsim); +void exynos_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim, + unsigned int mode, unsigned int mask); +void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim, + unsigned int count); +void exynos_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim, + unsigned int cfg); +void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim, + unsigned int value); +void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim, + unsigned int value); +void exynos_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim, + unsigned int width_resol, unsigned int height_resol); +void exynos_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim, + unsigned int cmd_allow, unsigned int vfront, unsigned int vback); +void exynos_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim, + unsigned int front, unsigned int back); +void exynos_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim, + unsigned int vert, unsigned int hori); +void exynos_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim, + unsigned int vert, unsigned int hori); +void exynos_mipi_dsi_init_config(struct mipi_dsim_device *dsim); +void exynos_mipi_dsi_display_config(struct mipi_dsim_device *dsim, + struct mipi_dsim_config *dsim_config); +void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim, + unsigned int count); +void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, + unsigned int lane, unsigned int enable); +void exynos_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim, + unsigned int enable, unsigned int afc_code); +void exynos_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim, + unsigned int enable); +void exynos_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim, + unsigned int freq_band); +void exynos_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim, + unsigned int pre_divider, unsigned int main_divider, + unsigned int scaler); +void exynos_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim, + unsigned int lock_time); +void exynos_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim, + unsigned int enable); +void exynos_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim, + unsigned int src); +void exynos_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim, + unsigned int enable); +void exynos_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim, + unsigned int enable, unsigned int prs_val); +void exynos_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim, + unsigned int lane_sel, unsigned int enable); +void exynos_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim, + unsigned int enable); +unsigned int exynos_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim); +void exynos_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim, + unsigned int cnt_val); +void exynos_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim, + unsigned int timeout); +void exynos_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim, + unsigned int timeout); +void exynos_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim, + unsigned int lp); +void exynos_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim, + unsigned int lp); +void exynos_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim, + unsigned int enable); +void exynos_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim, + unsigned int swap_en); +void exynos_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim, + unsigned int hs_zero); +void exynos_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim, + unsigned int prep); +void exynos_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim); +void exynos_mipi_dsi_clear_all_interrupt(struct mipi_dsim_device *dsim); +unsigned int exynos_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim); +unsigned int exynos_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim); +unsigned int _exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device + *dsim); +void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim); +void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim, + unsigned int di, const unsigned char data0, const unsigned char data1); +void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim, + unsigned int tx_data); + +#endif /* _EXYNOS_MIPI_DSI_LOWLEVEL_H */ diff --git a/qemu/roms/u-boot/drivers/video/exynos_pwm_bl.c b/qemu/roms/u-boot/drivers/video/exynos_pwm_bl.c new file mode 100644 index 000000000..a6890daf2 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/exynos_pwm_bl.c @@ -0,0 +1,45 @@ +/* + * PWM BACKLIGHT driver for Board based on EXYNOS. + * + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * Derived from linux/drivers/video/backlight/pwm_backlight.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <pwm.h> +#include <linux/types.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pwm.h> +#include <asm/arch/pwm_backlight.h> + +static struct pwm_backlight_data *pwm; + +static int exynos_pwm_backlight_update_status(void) +{ + int brightness = pwm->brightness; + int max = pwm->max_brightness; + + if (brightness == 0) { + pwm_config(pwm->pwm_id, 0, pwm->period); + pwm_disable(pwm->pwm_id); + } else { + pwm_config(pwm->pwm_id, + brightness * pwm->period / max, pwm->period); + pwm_enable(pwm->pwm_id); + } + return 0; +} + +int exynos_pwm_backlight_init(struct pwm_backlight_data *pd) +{ + pwm = pd; + + exynos_pwm_backlight_update_status(); + + return 0; +} diff --git a/qemu/roms/u-boot/drivers/video/formike.c b/qemu/roms/u-boot/drivers/video/formike.c new file mode 100644 index 000000000..138315843 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/formike.c @@ -0,0 +1,512 @@ +/* + * LCD: Formike, TFT 4.3", 480x800, RGB24, KWH043ST20-F01, DriverIC NT35510-16 + * LCD initialization via SPI + * + * SPDX-License-Identifier: GPL-2.0 + * Based on: + * + */ +#include <common.h> +#include <errno.h> +#include <spi.h> + +#define TAG_READ 0x80 +#define TAG_WRITE 0x00 + +#define TAG_DATA 0x40 +#define TAG_COMMAND 0x00 + +#define TAG_ADDR_H 0x20 +#define TAG_ADDR_L 0x00 + +static int spi_write_tag_val(struct spi_slave *spi, unsigned char tag, + unsigned char val) +{ + unsigned long flags = SPI_XFER_BEGIN; + u8 buf[2]; + int ret; + + buf[0] = tag; + ret = spi_xfer(spi, 8, buf, NULL, flags); + buf[0] = val; + flags = SPI_XFER_END; + ret = spi_xfer(spi, 8, buf, NULL, flags); + +#ifdef KWH043ST20_F01_SPI_DEBUG + printf("spi_write_tag_val: tag=%02X, val=%02X ret: %d\n", + tag, val, ret); +#endif /* KWH043ST20_F01_SPI_DEBUG */ + if (ret) + debug("%s: Failed to send: %d\n", __func__, ret); + + return ret; +} + +static void spi_write_dat(struct spi_slave *spi, unsigned int val) +{ + spi_write_tag_val(spi, TAG_WRITE|TAG_DATA, val); +} + +static void spi_write_com(struct spi_slave *spi, unsigned int addr) +{ + spi_write_tag_val(spi, TAG_WRITE|TAG_COMMAND|TAG_ADDR_H, + (addr & 0xff00) >> 8); + spi_write_tag_val(spi, TAG_WRITE|TAG_COMMAND|TAG_ADDR_L, + (addr & 0x00ff) >> 0); +} + +int kwh043st20_f01_spi_startup(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode) +{ + struct spi_slave *spi; + int ret; + + spi = spi_setup_slave(bus, cs, max_hz, spi_mode); + if (!spi) { + debug("%s: Failed to set up slave\n", __func__); + return -1; + } + + ret = spi_claim_bus(spi); + if (ret) { + debug("%s: Failed to claim SPI bus: %d\n", __func__, ret); + goto err_claim_bus; + } + + + /* LV2 Page 1 enable */ + spi_write_com(spi, 0xF000); spi_write_dat(spi, 0x55); + spi_write_com(spi, 0xF001); spi_write_dat(spi, 0xAA); + spi_write_com(spi, 0xF002); spi_write_dat(spi, 0x52); + spi_write_com(spi, 0xF003); spi_write_dat(spi, 0x08); + spi_write_com(spi, 0xF004); spi_write_dat(spi, 0x01); + + /* AVDD Set AVDD 5.2V */ + spi_write_com(spi, 0xB000); spi_write_dat(spi, 0x0D); + spi_write_com(spi, 0xB001); spi_write_dat(spi, 0x0D); + spi_write_com(spi, 0xB002); spi_write_dat(spi, 0x0D); + + /* AVDD ratio */ + spi_write_com(spi, 0xB600); spi_write_dat(spi, 0x34); + spi_write_com(spi, 0xB601); spi_write_dat(spi, 0x34); + spi_write_com(spi, 0xB602); spi_write_dat(spi, 0x34); + + /* AVEE -5.2V */ + spi_write_com(spi, 0xB100); spi_write_dat(spi, 0x0D); + spi_write_com(spi, 0xB101); spi_write_dat(spi, 0x0D); + spi_write_com(spi, 0xB102); spi_write_dat(spi, 0x0D); + + /* AVEE ratio */ + spi_write_com(spi, 0xB700); spi_write_dat(spi, 0x35); + spi_write_com(spi, 0xB701); spi_write_dat(spi, 0x35); + spi_write_com(spi, 0xB702); spi_write_dat(spi, 0x35); + + /* VCL -2.5V */ + spi_write_com(spi, 0xB200); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xB201); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xB202); spi_write_dat(spi, 0x00); + + /* VCL ratio */ + spi_write_com(spi, 0xB800); spi_write_dat(spi, 0x24); + spi_write_com(spi, 0xB801); spi_write_dat(spi, 0x24); + spi_write_com(spi, 0xB802); spi_write_dat(spi, 0x24); + + /* VGH 15V */ + spi_write_com(spi, 0xBF00); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xB300); spi_write_dat(spi, 0x08); + spi_write_com(spi, 0xB301); spi_write_dat(spi, 0x08); + spi_write_com(spi, 0xB302); spi_write_dat(spi, 0x08); + + /* VGH ratio */ + spi_write_com(spi, 0xB900); spi_write_dat(spi, 0x34); + spi_write_com(spi, 0xB901); spi_write_dat(spi, 0x34); + spi_write_com(spi, 0xB902); spi_write_dat(spi, 0x34); + + /* VGLX ratio */ + spi_write_com(spi, 0xBA00); spi_write_dat(spi, 0x24); + spi_write_com(spi, 0xBA01); spi_write_dat(spi, 0x24); + spi_write_com(spi, 0xBA02); spi_write_dat(spi, 0x24); + + /* VGMP/VGSP 4.7V/0V */ + spi_write_com(spi, 0xBC00); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xBC01); spi_write_dat(spi, 0x88); + spi_write_com(spi, 0xBC02); spi_write_dat(spi, 0x00); + + /* VGMN/VGSN -4.7V/0V */ + spi_write_com(spi, 0xBD00); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xBD01); spi_write_dat(spi, 0x88); + spi_write_com(spi, 0xBD02); spi_write_dat(spi, 0x00); + + /* VCOM 1.525V */ + spi_write_com(spi, 0xBE00); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xBE01); spi_write_dat(spi, 0x7A); + + /* Gamma Setting */ + spi_write_com(spi, 0xD100); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD101); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD102); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD103); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD104); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD105); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD106); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD107); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD108); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD109); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD10A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD10B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD10C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD10D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD10E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD10F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD110); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD111); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD112); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD113); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD114); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD115); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD116); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD117); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD118); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD119); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD11A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD11B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD11C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD11D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD11E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD11F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD120); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD121); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD122); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD123); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD124); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD125); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD126); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD127); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD128); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD129); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD12A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD12B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD12C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD12D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD12E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD12F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD130); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD131); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD132); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD133); spi_write_dat(spi, 0xFF); + + spi_write_com(spi, 0xD200); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD201); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD202); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD203); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD204); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD205); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD206); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD207); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD208); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD209); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD20A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD20B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD20C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD20D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD20E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD20F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD210); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD211); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD212); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD213); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD214); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD215); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD216); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD217); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD218); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD219); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD21A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD21B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD21C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD21D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD21E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD21F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD220); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD221); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD222); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD223); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD224); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD225); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD226); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD227); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD228); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD229); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD22A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD22B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD22C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD22D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD22E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD22F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD230); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD231); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD232); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD233); spi_write_dat(spi, 0xFF); + + spi_write_com(spi, 0xD300); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD301); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD302); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD303); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD304); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD305); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD306); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD307); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD308); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD309); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD30A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD30B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD30C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD30D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD30E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD30F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD310); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD311); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD312); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD313); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD314); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD315); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD316); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD317); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD318); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD319); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD31A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD31B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD31C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD31D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD31E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD31F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD320); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD321); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD322); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD323); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD324); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD325); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD326); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD327); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD328); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD329); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD32A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD32B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD32C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD32D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD32E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD32F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD330); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD331); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD332); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD333); spi_write_dat(spi, 0xFF); + + spi_write_com(spi, 0xD400); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD401); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD402); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD403); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD404); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD405); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD406); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD407); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD408); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD409); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD40A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD40B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD40C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD40D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD40E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD40F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD410); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD411); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD412); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD413); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD414); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD415); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD416); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD417); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD418); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD419); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD41A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD41B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD41C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD41D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD41E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD41F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD420); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD421); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD422); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD423); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD424); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD425); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD426); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD427); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD428); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD429); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD42A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD42B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD42C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD42D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD42E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD42F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD430); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD431); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD432); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD433); spi_write_dat(spi, 0xFF); + + spi_write_com(spi, 0xD500); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD501); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD502); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD503); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD504); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD505); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD506); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD507); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD508); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD509); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD50A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD50B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD50C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD50D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD50E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD50F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD510); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD511); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD512); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD513); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD514); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD515); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD516); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD517); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD518); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD519); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD51A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD51B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD51C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD51D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD51E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD51F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD520); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD521); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD522); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD523); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD524); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD525); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD526); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD527); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD528); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD529); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD52A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD52B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD52C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD52D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD52E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD52F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD530); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD531); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD532); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD533); spi_write_dat(spi, 0xFF); + + spi_write_com(spi, 0xD600); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD601); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD602); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD603); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD604); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD605); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD606); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD607); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD608); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD609); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD60A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD60B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD60C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD60D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD60E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD60F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD610); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD611); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD612); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD613); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD614); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD615); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD616); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD617); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD618); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD619); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD61A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD61B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD61C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD61D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD61E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD61F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD620); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD621); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD622); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD623); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD624); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD625); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD626); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD627); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD628); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD629); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD62A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD62B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD62C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD62D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD62E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD62F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD630); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD631); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD632); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD633); spi_write_dat(spi, 0xFF); + + /* LV2 Page 0 enable */ + spi_write_com(spi, 0xF000); spi_write_dat(spi, 0x55); + spi_write_com(spi, 0xF001); spi_write_dat(spi, 0xAA); + spi_write_com(spi, 0xF002); spi_write_dat(spi, 0x52); + spi_write_com(spi, 0xF003); spi_write_dat(spi, 0x08); + spi_write_com(spi, 0xF004); spi_write_dat(spi, 0x00); + + /* Display control */ + spi_write_com(spi, 0xB100); spi_write_dat(spi, 0xFC); + spi_write_com(spi, 0xB101); spi_write_dat(spi, 0x00); + + /* Source hold time */ + spi_write_com(spi, 0xB600); spi_write_dat(spi, 0x05); + + /* Gate EQ control */ + spi_write_com(spi, 0xB700); spi_write_dat(spi, 0x70); + spi_write_com(spi, 0xB701); spi_write_dat(spi, 0x70); + + /* Source EQ control (Mode 2) */ + spi_write_com(spi, 0xB800); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xB801); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xB802); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xB803); spi_write_dat(spi, 0x05); + + /* Inversion mode (Column) */ + spi_write_com(spi, 0xBC00); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xBC01); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xBC02); spi_write_dat(spi, 0x00); + + /* Timing control 8phase dual side/4H/4delay/RST_EN */ + spi_write_com(spi, 0xC900); spi_write_dat(spi, 0xD0); + spi_write_com(spi, 0xC901); spi_write_dat(spi, 0x82); + spi_write_com(spi, 0xC902); spi_write_dat(spi, 0x50); + spi_write_com(spi, 0xC903); spi_write_dat(spi, 0x50); + spi_write_com(spi, 0xC904); spi_write_dat(spi, 0x50); + + spi_write_com(spi, 0x3A00); spi_write_dat(spi, 0x55); + mdelay(120); + spi_write_com(spi, 0x1100); + mdelay(120); + spi_write_com(spi, 0x2900); + mdelay(120); + /* spi_write_com(spi, 0x2100); spi_write_dat(spi, 0x00); */ + spi_write_com(spi, 0x2C00); + + return 0; +err_claim_bus: + spi_free_slave(spi); + return -1; +} diff --git a/qemu/roms/u-boot/drivers/video/fsl_diu_fb.c b/qemu/roms/u-boot/drivers/video/fsl_diu_fb.c new file mode 100644 index 000000000..b3d46b86f --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/fsl_diu_fb.c @@ -0,0 +1,417 @@ +/* + * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. + * Authors: York Sun <yorksun@freescale.com> + * Timur Tabi <timur@freescale.com> + * + * FSL DIU Framebuffer driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <asm/io.h> + +#include "videomodes.h" +#include <video_fb.h> +#include <fsl_diu_fb.h> +#include <linux/list.h> +#include <linux/fb.h> + +/* This setting is used for the ifm pdm360ng with PRIMEVIEW PM070WL3 */ +static struct fb_videomode fsl_diu_mode_800_480 = { + .name = "800x480-60", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 31250, + .left_margin = 86, + .right_margin = 42, + .upper_margin = 33, + .lower_margin = 10, + .hsync_len = 128, + .vsync_len = 2, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +}; + +/* For the SHARP LQ084S3LG01, used on the P1022DS board */ +static struct fb_videomode fsl_diu_mode_800_600 = { + .name = "800x600-60", + .refresh = 60, + .xres = 800, + .yres = 600, + .pixclock = 25000, + .left_margin = 88, + .right_margin = 40, + .upper_margin = 23, + .lower_margin = 1, + .hsync_len = 128, + .vsync_len = 4, + .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; + +/* + * These parameters give default parameters + * for video output 1024x768, + * FIXME - change timing to proper amounts + * hsync 31.5kHz, vsync 60Hz + */ +static struct fb_videomode fsl_diu_mode_1024_768 = { + .name = "1024x768-60", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 160, + .right_margin = 24, + .upper_margin = 29, + .lower_margin = 3, + .hsync_len = 136, + .vsync_len = 6, + .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; + +static struct fb_videomode fsl_diu_mode_1280_1024 = { + .name = "1280x1024-60", + .refresh = 60, + .xres = 1280, + .yres = 1024, + .pixclock = 9375, + .left_margin = 38, + .right_margin = 128, + .upper_margin = 2, + .lower_margin = 7, + .hsync_len = 216, + .vsync_len = 37, + .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; + +static struct fb_videomode fsl_diu_mode_1280_720 = { + .name = "1280x720-60", + .refresh = 60, + .xres = 1280, + .yres = 720, + .pixclock = 13426, + .left_margin = 192, + .right_margin = 64, + .upper_margin = 22, + .lower_margin = 1, + .hsync_len = 136, + .vsync_len = 3, + .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; + +static struct fb_videomode fsl_diu_mode_1920_1080 = { + .name = "1920x1080-60", + .refresh = 60, + .xres = 1920, + .yres = 1080, + .pixclock = 5787, + .left_margin = 328, + .right_margin = 120, + .upper_margin = 34, + .lower_margin = 1, + .hsync_len = 208, + .vsync_len = 3, + .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; + +/* + * These are the fields of area descriptor(in DDR memory) for every plane + */ +struct diu_ad { + /* Word 0(32-bit) in DDR memory */ + __le32 pix_fmt; /* hard coding pixel format */ + /* Word 1(32-bit) in DDR memory */ + __le32 addr; + /* Word 2(32-bit) in DDR memory */ + __le32 src_size_g_alpha; + /* Word 3(32-bit) in DDR memory */ + __le32 aoi_size; + /* Word 4(32-bit) in DDR memory */ + __le32 offset_xyi; + /* Word 5(32-bit) in DDR memory */ + __le32 offset_xyd; + /* Word 6(32-bit) in DDR memory */ + __le32 ckmax_r:8; + __le32 ckmax_g:8; + __le32 ckmax_b:8; + __le32 res9:8; + /* Word 7(32-bit) in DDR memory */ + __le32 ckmin_r:8; + __le32 ckmin_g:8; + __le32 ckmin_b:8; + __le32 res10:8; + /* Word 8(32-bit) in DDR memory */ + __le32 next_ad; + /* Word 9(32-bit) in DDR memory, just for 64-bit aligned */ + __le32 res[3]; +} __attribute__ ((packed)); + +/* + * DIU register map + */ +struct diu { + __be32 desc[3]; + __be32 gamma; + __be32 pallete; + __be32 cursor; + __be32 curs_pos; + __be32 diu_mode; + __be32 bgnd; + __be32 bgnd_wb; + __be32 disp_size; + __be32 wb_size; + __be32 wb_mem_addr; + __be32 hsyn_para; + __be32 vsyn_para; + __be32 syn_pol; + __be32 thresholds; + __be32 int_status; + __be32 int_mask; + __be32 colorbar[8]; + __be32 filling; + __be32 plut; +} __attribute__ ((packed)); + +struct diu_addr { + void *vaddr; /* Virtual address */ + u32 paddr; /* 32-bit physical address */ + unsigned int offset; /* Alignment offset */ +}; + +static struct fb_info info; + +/* + * Align to 64-bit(8-byte), 32-byte, etc. + */ +static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align) +{ + u32 offset, ssize; + u32 mask; + + ssize = size + bytes_align; + buf->vaddr = malloc(ssize); + if (!buf->vaddr) + return -1; + + memset(buf->vaddr, 0, ssize); + mask = bytes_align - 1; + offset = (u32)buf->vaddr & mask; + if (offset) { + buf->offset = bytes_align - offset; + buf->vaddr += offset; + } else + buf->offset = 0; + + buf->paddr = virt_to_phys(buf->vaddr); + return 0; +} + +/* + * Allocate a framebuffer and an Area Descriptor that points to it. Both + * are created in the same memory block. The Area Descriptor is updated to + * point to the framebuffer memory. Memory is aligned as needed. + */ +static struct diu_ad *allocate_fb(unsigned int xres, unsigned int yres, + unsigned int depth, char **fb) +{ + unsigned long size = xres * yres * depth; + struct diu_addr addr; + struct diu_ad *ad; + size_t ad_size = roundup(sizeof(struct diu_ad), 32); + + /* + * Allocate a memory block that holds the Area Descriptor and the + * frame buffer right behind it. To keep the code simple, everything + * is aligned on a 32-byte address. + */ + if (allocate_buf(&addr, ad_size + size, 32) < 0) + return NULL; + + ad = addr.vaddr; + ad->addr = cpu_to_le32(addr.paddr + ad_size); + ad->aoi_size = cpu_to_le32((yres << 16) | xres); + ad->src_size_g_alpha = cpu_to_le32((yres << 12) | xres); + ad->offset_xyi = 0; + ad->offset_xyd = 0; + + if (fb) + *fb = addr.vaddr + ad_size; + + return ad; +} + +int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int gamma_fix) +{ + struct fb_videomode *fsl_diu_mode_db; + struct diu_ad *ad; + struct diu *hw = (struct diu *)CONFIG_SYS_DIU_ADDR; + u8 *gamma_table_base; + unsigned int i, j; + struct diu_addr gamma; + struct diu_addr cursor; + +/* Convert the X,Y resolution pair into a single number */ +#define RESOLUTION(x, y) (((u32)(x) << 16) | (y)) + + switch (RESOLUTION(xres, yres)) { + case RESOLUTION(800, 480): + fsl_diu_mode_db = &fsl_diu_mode_800_480; + break; + case RESOLUTION(800, 600): + fsl_diu_mode_db = &fsl_diu_mode_800_600; + break; + case RESOLUTION(1024, 768): + fsl_diu_mode_db = &fsl_diu_mode_1024_768; + break; + case RESOLUTION(1280, 1024): + fsl_diu_mode_db = &fsl_diu_mode_1280_1024; + break; + case RESOLUTION(1280, 720): + fsl_diu_mode_db = &fsl_diu_mode_1280_720; + break; + case RESOLUTION(1920, 1080): + fsl_diu_mode_db = &fsl_diu_mode_1920_1080; + break; + default: + printf("DIU: Unsupported resolution %ux%u\n", xres, yres); + return -1; + } + + /* read mode info */ + info.var.xres = fsl_diu_mode_db->xres; + info.var.yres = fsl_diu_mode_db->yres; + info.var.bits_per_pixel = 32; + info.var.pixclock = fsl_diu_mode_db->pixclock; + info.var.left_margin = fsl_diu_mode_db->left_margin; + info.var.right_margin = fsl_diu_mode_db->right_margin; + info.var.upper_margin = fsl_diu_mode_db->upper_margin; + info.var.lower_margin = fsl_diu_mode_db->lower_margin; + info.var.hsync_len = fsl_diu_mode_db->hsync_len; + info.var.vsync_len = fsl_diu_mode_db->vsync_len; + info.var.sync = fsl_diu_mode_db->sync; + info.var.vmode = fsl_diu_mode_db->vmode; + info.fix.line_length = info.var.xres * info.var.bits_per_pixel / 8; + + /* Memory allocation for framebuffer */ + info.screen_size = + info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8); + ad = allocate_fb(info.var.xres, info.var.yres, + info.var.bits_per_pixel / 8, &info.screen_base); + if (!ad) { + printf("DIU: Out of memory\n"); + return -1; + } + + ad->pix_fmt = pixel_format; + + /* Disable chroma keying function */ + ad->ckmax_r = 0; + ad->ckmax_g = 0; + ad->ckmax_b = 0; + + ad->ckmin_r = 255; + ad->ckmin_g = 255; + ad->ckmin_b = 255; + + /* Initialize the gamma table */ + if (allocate_buf(&gamma, 256 * 3, 32) < 0) { + printf("DIU: Out of memory\n"); + return -1; + } + gamma_table_base = gamma.vaddr; + for (i = 0; i <= 2; i++) + for (j = 0; j < 256; j++) + *gamma_table_base++ = j; + + if (gamma_fix == 1) { /* fix the gamma */ + gamma_table_base = gamma.vaddr; + for (i = 0; i < 256 * 3; i++) { + gamma_table_base[i] = (gamma_table_base[i] << 2) + | ((gamma_table_base[i] >> 6) & 0x03); + } + } + + /* Initialize the cursor */ + if (allocate_buf(&cursor, 32 * 32 * 2, 32) < 0) { + printf("DIU: Can't alloc cursor data\n"); + return -1; + } + + /* Program DIU registers */ + out_be32(&hw->diu_mode, 0); /* Temporarily disable the DIU */ + + out_be32(&hw->gamma, gamma.paddr); + out_be32(&hw->cursor, cursor.paddr); + out_be32(&hw->bgnd, 0x007F7F7F); + out_be32(&hw->disp_size, info.var.yres << 16 | info.var.xres); + out_be32(&hw->hsyn_para, info.var.left_margin << 22 | + info.var.hsync_len << 11 | + info.var.right_margin); + + out_be32(&hw->vsyn_para, info.var.upper_margin << 22 | + info.var.vsync_len << 11 | + info.var.lower_margin); + + /* Pixel Clock configuration */ + diu_set_pixel_clock(info.var.pixclock); + + /* Set the frame buffers */ + out_be32(&hw->desc[0], virt_to_phys(ad)); + out_be32(&hw->desc[1], 0); + out_be32(&hw->desc[2], 0); + + /* Enable the DIU, set display to all three planes */ + out_be32(&hw->diu_mode, 1); + + return 0; +} + +void *video_hw_init(void) +{ + static GraphicDevice ctfb; + const char *options; + unsigned int depth = 0, freq = 0; + + if (!video_get_video_mode(&ctfb.winSizeX, &ctfb.winSizeY, &depth, &freq, + &options)) + return NULL; + + /* Find the monitor port, which is a required option */ + if (!options) + return NULL; + if (strncmp(options, "monitor=", 8) != 0) + return NULL; + + if (platform_diu_init(ctfb.winSizeX, ctfb.winSizeY, options + 8) < 0) + return NULL; + + /* fill in Graphic device struct */ + sprintf(ctfb.modeIdent, "%ix%ix%i %ikHz %iHz", + ctfb.winSizeX, ctfb.winSizeY, depth, 64, freq); + + ctfb.frameAdrs = (unsigned int)info.screen_base; + ctfb.plnSizeX = ctfb.winSizeX; + ctfb.plnSizeY = ctfb.winSizeY; + + ctfb.gdfBytesPP = 4; + ctfb.gdfIndex = GDF_32BIT_X888RGB; + + ctfb.isaBase = 0; + ctfb.pciBase = 0; + ctfb.memSize = info.screen_size; + + /* Cursor Start Address */ + ctfb.dprBase = 0; + ctfb.vprBase = 0; + ctfb.cprBase = 0; + + return &ctfb; +} diff --git a/qemu/roms/u-boot/drivers/video/ipu.h b/qemu/roms/u-boot/drivers/video/ipu.h new file mode 100644 index 000000000..3d2741f22 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/ipu.h @@ -0,0 +1,261 @@ +/* + * Porting to u-boot: + * + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de + * + * Linux IPU driver for MX51: + * + * (C) Copyright 2005-2010 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_IPU_H__ +#define __ASM_ARCH_IPU_H__ + +#include <linux/types.h> +#include <ipu_pixfmt.h> + +#define IDMA_CHAN_INVALID 0xFF +#define HIGH_RESOLUTION_WIDTH 1024 + +struct clk { + const char *name; + int id; + /* Source clock this clk depends on */ + struct clk *parent; + /* Secondary clock to enable/disable with this clock */ + struct clk *secondary; + /* Current clock rate */ + unsigned long rate; + /* Reference count of clock enable/disable */ + __s8 usecount; + /* Register bit position for clock's enable/disable control. */ + u8 enable_shift; + /* Register address for clock's enable/disable control. */ + void *enable_reg; + u32 flags; + /* + * Function ptr to recalculate the clock's rate based on parent + * clock's rate + */ + void (*recalc) (struct clk *); + /* + * Function ptr to set the clock to a new rate. The rate must match a + * supported rate returned from round_rate. Leave blank if clock is not + * programmable + */ + int (*set_rate) (struct clk *, unsigned long); + /* + * Function ptr to round the requested clock rate to the nearest + * supported rate that is less than or equal to the requested rate. + */ + unsigned long (*round_rate) (struct clk *, unsigned long); + /* + * Function ptr to enable the clock. Leave blank if clock can not + * be gated. + */ + int (*enable) (struct clk *); + /* + * Function ptr to disable the clock. Leave blank if clock can not + * be gated. + */ + void (*disable) (struct clk *); + /* Function ptr to set the parent clock of the clock. */ + int (*set_parent) (struct clk *, struct clk *); +}; + +/* + * Enumeration of Synchronous (Memory-less) panel types + */ +typedef enum { + IPU_PANEL_SHARP_TFT, + IPU_PANEL_TFT, +} ipu_panel_t; + +/* + * IPU Driver channels definitions. + * Note these are different from IDMA channels + */ +#define IPU_MAX_CH 32 +#define _MAKE_CHAN(num, v_in, g_in, a_in, out) \ + ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out) +#define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24)) +#define IPU_CHAN_ID(ch) (ch >> 24) +#define IPU_CHAN_ALT(ch) (ch & 0x02000000) +#define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F) +#define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F) +#define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F) +#define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F)) +#define NO_DMA 0x3F +#define ALT 1 + +/* + * Enumeration of IPU logical channels. An IPU logical channel is defined as a + * combination of an input (memory to IPU), output (IPU to memory), and/or + * secondary input IDMA channels and in some cases an Image Converter task. + * Some channels consist of only an input or output. + */ +typedef enum { + CHAN_NONE = -1, + + MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA), + MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA), + MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA), + MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA), + + MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA), + MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA), + MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0), + MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0), + + DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA), + DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA), + +} ipu_channel_t; + +/* + * Enumeration of types of buffers for a logical channel. + */ +typedef enum { + IPU_OUTPUT_BUFFER = 0, /*< Buffer for output from IPU */ + IPU_ALPHA_IN_BUFFER = 1, /*< Buffer for input to IPU */ + IPU_GRAPH_IN_BUFFER = 2, /*< Buffer for input to IPU */ + IPU_VIDEO_IN_BUFFER = 3, /*< Buffer for input to IPU */ + IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER, + IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER, +} ipu_buffer_t; + +#define IPU_PANEL_SERIAL 1 +#define IPU_PANEL_PARALLEL 2 + +struct ipu_channel { + u8 video_in_dma; + u8 alpha_in_dma; + u8 graph_in_dma; + u8 out_dma; +}; + +enum ipu_dmfc_type { + DMFC_NORMAL = 0, + DMFC_HIGH_RESOLUTION_DC, + DMFC_HIGH_RESOLUTION_DP, + DMFC_HIGH_RESOLUTION_ONLY_DP, +}; + + +/* + * Union of initialization parameters for a logical channel. + */ +typedef union { + struct { + uint32_t di; + unsigned char interlaced; + } mem_dc_sync; + struct { + uint32_t temp; + } mem_sdc_fg; + struct { + uint32_t di; + unsigned char interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + unsigned char alpha_chan_en; + } mem_dp_bg_sync; + struct { + uint32_t temp; + } mem_sdc_bg; + struct { + uint32_t di; + unsigned char interlaced; + uint32_t in_pixel_fmt; + uint32_t out_pixel_fmt; + unsigned char alpha_chan_en; + } mem_dp_fg_sync; +} ipu_channel_params_t; + +/* + * Bitfield of Display Interface signal polarities. + */ +typedef struct { + unsigned datamask_en:1; + unsigned ext_clk:1; + unsigned interlaced:1; + unsigned odd_field_first:1; + unsigned clksel_en:1; + unsigned clkidle_en:1; + unsigned data_pol:1; /* true = inverted */ + unsigned clk_pol:1; /* true = rising edge */ + unsigned enable_pol:1; + unsigned Hsync_pol:1; /* true = active high */ + unsigned Vsync_pol:1; +} ipu_di_signal_cfg_t; + +typedef enum { + RGB, + YCbCr, + YUV +} ipu_color_space_t; + +/* Common IPU API */ +int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params); +void ipu_uninit_channel(ipu_channel_t channel); + +int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + dma_addr_t phyaddr_0, dma_addr_t phyaddr_1, + uint32_t u_offset, uint32_t v_offset); + +int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum, dma_addr_t phyaddr); + +int32_t ipu_is_channel_busy(ipu_channel_t channel); +void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum); +int32_t ipu_enable_channel(ipu_channel_t channel); +int32_t ipu_disable_channel(ipu_channel_t channel); + +int32_t ipu_init_sync_panel(int disp, + uint32_t pixel_clk, + uint16_t width, uint16_t height, + uint32_t pixel_fmt, + uint16_t h_start_width, uint16_t h_sync_width, + uint16_t h_end_width, uint16_t v_start_width, + uint16_t v_sync_width, uint16_t v_end_width, + uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig); + +int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable, + uint8_t alpha); +int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable, + uint32_t colorKey); + +uint32_t bytes_per_pixel(uint32_t fmt); + +void clk_enable(struct clk *clk); +void clk_disable(struct clk *clk); +u32 clk_get_rate(struct clk *clk); +int clk_set_rate(struct clk *clk, unsigned long rate); +long clk_round_rate(struct clk *clk, unsigned long rate); +int clk_set_parent(struct clk *clk, struct clk *parent); +int clk_get_usecount(struct clk *clk); +struct clk *clk_get_parent(struct clk *clk); + +void ipu_dump_registers(void); +int ipu_probe(void); + +void ipu_dmfc_init(int dmfc_type, int first); +void ipu_init_dc_mappings(void); +void ipu_dmfc_set_wait4eot(int dma_chan, int width); +void ipu_dc_init(int dc_chan, int di, unsigned char interlaced); +void ipu_dc_uninit(int dc_chan); +void ipu_dp_dc_enable(ipu_channel_t channel); +int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt, + uint32_t out_pixel_fmt); +void ipu_dp_uninit(ipu_channel_t channel); +void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap); +ipu_color_space_t format_to_colorspace(uint32_t fmt); + +#endif diff --git a/qemu/roms/u-boot/drivers/video/ipu_common.c b/qemu/roms/u-boot/drivers/video/ipu_common.c new file mode 100644 index 000000000..8d4e92547 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/ipu_common.c @@ -0,0 +1,1196 @@ +/* + * Porting to u-boot: + * + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de + * + * Linux IPU driver for MX51: + * + * (C) Copyright 2005-2010 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* #define DEBUG */ +#include <common.h> +#include <linux/types.h> +#include <linux/err.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include "ipu.h" +#include "ipu_regs.h" + +extern struct mxc_ccm_reg *mxc_ccm; +extern u32 *ipu_cpmem_base; + +struct ipu_ch_param_word { + uint32_t data[5]; + uint32_t res[3]; +}; + +struct ipu_ch_param { + struct ipu_ch_param_word word[2]; +}; + +#define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch)) + +#define _param_word(base, w) \ + (((struct ipu_ch_param *)(base))->word[(w)].data) + +#define ipu_ch_param_set_field(base, w, bit, size, v) { \ + int i = (bit) / 32; \ + int off = (bit) % 32; \ + _param_word(base, w)[i] |= (v) << off; \ + if (((bit) + (size) - 1) / 32 > i) { \ + _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \ + } \ +} + +#define ipu_ch_param_mod_field(base, w, bit, size, v) { \ + int i = (bit) / 32; \ + int off = (bit) % 32; \ + u32 mask = (1UL << size) - 1; \ + u32 temp = _param_word(base, w)[i]; \ + temp &= ~(mask << off); \ + _param_word(base, w)[i] = temp | (v) << off; \ + if (((bit) + (size) - 1) / 32 > i) { \ + temp = _param_word(base, w)[i + 1]; \ + temp &= ~(mask >> (32 - off)); \ + _param_word(base, w)[i + 1] = \ + temp | ((v) >> (off ? (32 - off) : 0)); \ + } \ +} + +#define ipu_ch_param_read_field(base, w, bit, size) ({ \ + u32 temp2; \ + int i = (bit) / 32; \ + int off = (bit) % 32; \ + u32 mask = (1UL << size) - 1; \ + u32 temp1 = _param_word(base, w)[i]; \ + temp1 = mask & (temp1 >> off); \ + if (((bit)+(size) - 1) / 32 > i) { \ + temp2 = _param_word(base, w)[i + 1]; \ + temp2 &= mask >> (off ? (32 - off) : 0); \ + temp1 |= temp2 << (off ? (32 - off) : 0); \ + } \ + temp1; \ +}) + +#define IPU_SW_RST_TOUT_USEC (10000) + +void clk_enable(struct clk *clk) +{ + if (clk) { + if (clk->usecount++ == 0) { + clk->enable(clk); + } + } +} + +void clk_disable(struct clk *clk) +{ + if (clk) { + if (!(--clk->usecount)) { + if (clk->disable) + clk->disable(clk); + } + } +} + +int clk_get_usecount(struct clk *clk) +{ + if (clk == NULL) + return 0; + + return clk->usecount; +} + +u32 clk_get_rate(struct clk *clk) +{ + if (!clk) + return 0; + + return clk->rate; +} + +struct clk *clk_get_parent(struct clk *clk) +{ + if (!clk) + return 0; + + return clk->parent; +} + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + if (clk && clk->set_rate) + clk->set_rate(clk, rate); + return clk->rate; +} + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + if (clk == NULL || !clk->round_rate) + return 0; + + return clk->round_rate(clk, rate); +} + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + clk->parent = parent; + if (clk->set_parent) + return clk->set_parent(clk, parent); + return 0; +} + +static int clk_ipu_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) + /* Handshake with IPU when certain clock rates are changed. */ + reg = __raw_readl(&mxc_ccm->ccdr); + reg &= ~MXC_CCM_CCDR_IPU_HS_MASK; + __raw_writel(reg, &mxc_ccm->ccdr); + + /* Handshake with IPU when LPM is entered as its enabled. */ + reg = __raw_readl(&mxc_ccm->clpcr); + reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; + __raw_writel(reg, &mxc_ccm->clpcr); +#endif + return 0; +} + +static void clk_ipu_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); + +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) + /* + * No handshake with IPU whe dividers are changed + * as its not enabled. + */ + reg = __raw_readl(&mxc_ccm->ccdr); + reg |= MXC_CCM_CCDR_IPU_HS_MASK; + __raw_writel(reg, &mxc_ccm->ccdr); + + /* No handshake with IPU when LPM is entered as its not enabled. */ + reg = __raw_readl(&mxc_ccm->clpcr); + reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; + __raw_writel(reg, &mxc_ccm->clpcr); +#endif +} + + +static struct clk ipu_clk = { + .name = "ipu_clk", + .rate = CONFIG_IPUV3_CLK, +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) + .enable_reg = (u32 *)(CCM_BASE_ADDR + + offsetof(struct mxc_ccm_reg, CCGR5)), + .enable_shift = MXC_CCM_CCGR5_IPU_OFFSET, +#else + .enable_reg = (u32 *)(CCM_BASE_ADDR + + offsetof(struct mxc_ccm_reg, CCGR3)), + .enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET, +#endif + .enable = clk_ipu_enable, + .disable = clk_ipu_disable, + .usecount = 0, +}; + +static struct clk ldb_clk = { + .name = "ldb_clk", + .rate = 65000000, + .usecount = 0, +}; + +/* Globals */ +struct clk *g_ipu_clk; +struct clk *g_ldb_clk; +unsigned char g_ipu_clk_enabled; +struct clk *g_di_clk[2]; +struct clk *g_pixel_clk[2]; +unsigned char g_dc_di_assignment[10]; +uint32_t g_channel_init_mask; +uint32_t g_channel_enable_mask; + +static int ipu_dc_use_count; +static int ipu_dp_use_count; +static int ipu_dmfc_use_count; +static int ipu_di_use_count[2]; + +u32 *ipu_cpmem_base; +u32 *ipu_dc_tmpl_reg; + +/* Static functions */ + +static inline void ipu_ch_param_set_high_priority(uint32_t ch) +{ + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1); +}; + +static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type) +{ + return ((uint32_t) ch >> (6 * type)) & 0x3F; +}; + +/* Either DP BG or DP FG can be graphic window */ +static inline int ipu_is_dp_graphic_chan(uint32_t dma_chan) +{ + return (dma_chan == 23 || dma_chan == 27); +} + +static inline int ipu_is_dmfc_chan(uint32_t dma_chan) +{ + return ((dma_chan >= 23) && (dma_chan <= 29)); +} + + +static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum, + dma_addr_t phyaddr) +{ + ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29, + phyaddr / 8); +}; + +#define idma_is_valid(ch) (ch != NO_DMA) +#define idma_mask(ch) (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0) +#define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma)) + +static void ipu_pixel_clk_recalc(struct clk *clk) +{ + u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id)); + if (div == 0) + clk->rate = 0; + else + clk->rate = (clk->parent->rate * 16) / div; +} + +static unsigned long ipu_pixel_clk_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div, div1; + u32 tmp; + /* + * Calculate divider + * Fractional part is 4 bits, + * so simply multiply by 2^4 to get fractional part. + */ + tmp = (clk->parent->rate * 16); + div = tmp / rate; + + if (div < 0x10) /* Min DI disp clock divider is 1 */ + div = 0x10; + if (div & ~0xFEF) + div &= 0xFF8; + else { + div1 = div & 0xFE0; + if ((tmp/div1 - tmp/div) < rate / 4) + div = div1; + else + div &= 0xFF8; + } + return (clk->parent->rate * 16) / div; +} + +static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate) +{ + u32 div = (clk->parent->rate * 16) / rate; + + __raw_writel(div, DI_BS_CLKGEN0(clk->id)); + + /* Setup pixel clock timing */ + __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id)); + + clk->rate = (clk->parent->rate * 16) / div; + return 0; +} + +static int ipu_pixel_clk_enable(struct clk *clk) +{ + u32 disp_gen = __raw_readl(IPU_DISP_GEN); + disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE; + __raw_writel(disp_gen, IPU_DISP_GEN); + + return 0; +} + +static void ipu_pixel_clk_disable(struct clk *clk) +{ + u32 disp_gen = __raw_readl(IPU_DISP_GEN); + disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE; + __raw_writel(disp_gen, IPU_DISP_GEN); + +} + +static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent) +{ + u32 di_gen = __raw_readl(DI_GENERAL(clk->id)); + + if (parent == g_ipu_clk) + di_gen &= ~DI_GEN_DI_CLK_EXT; + else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_ldb_clk) + di_gen |= DI_GEN_DI_CLK_EXT; + else + return -EINVAL; + + __raw_writel(di_gen, DI_GENERAL(clk->id)); + ipu_pixel_clk_recalc(clk); + return 0; +} + +static struct clk pixel_clk[] = { + { + .name = "pixel_clk", + .id = 0, + .recalc = ipu_pixel_clk_recalc, + .set_rate = ipu_pixel_clk_set_rate, + .round_rate = ipu_pixel_clk_round_rate, + .set_parent = ipu_pixel_clk_set_parent, + .enable = ipu_pixel_clk_enable, + .disable = ipu_pixel_clk_disable, + .usecount = 0, + }, + { + .name = "pixel_clk", + .id = 1, + .recalc = ipu_pixel_clk_recalc, + .set_rate = ipu_pixel_clk_set_rate, + .round_rate = ipu_pixel_clk_round_rate, + .set_parent = ipu_pixel_clk_set_parent, + .enable = ipu_pixel_clk_enable, + .disable = ipu_pixel_clk_disable, + .usecount = 0, + }, +}; + +/* + * This function resets IPU + */ +void ipu_reset(void) +{ + u32 *reg; + u32 value; + int timeout = IPU_SW_RST_TOUT_USEC; + + reg = (u32 *)SRC_BASE_ADDR; + value = __raw_readl(reg); + value = value | SW_IPU_RST; + __raw_writel(value, reg); + + while (__raw_readl(reg) & SW_IPU_RST) { + udelay(1); + if (!(timeout--)) { + printf("ipu software reset timeout\n"); + break; + } + }; +} + +/* + * This function is called by the driver framework to initialize the IPU + * hardware. + * + * @param dev The device structure for the IPU passed in by the + * driver framework. + * + * @return Returns 0 on success or negative error code on error + */ +int ipu_probe(void) +{ + unsigned long ipu_base; +#if defined CONFIG_MX51 + u32 temp; + + u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR; + u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800); + + __raw_writel(0xF00, reg_hsc_mcd); + + /* CSI mode reserved*/ + temp = __raw_readl(reg_hsc_mxt_conf); + __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf); + + temp = __raw_readl(reg_hsc_mxt_conf); + __raw_writel(temp | 0x10000, reg_hsc_mxt_conf); +#endif + + ipu_base = IPU_CTRL_BASE_ADDR; + ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE); + ipu_dc_tmpl_reg = (u32 *)(ipu_base + IPU_DC_TMPL_REG_BASE); + + g_pixel_clk[0] = &pixel_clk[0]; + g_pixel_clk[1] = &pixel_clk[1]; + + g_ipu_clk = &ipu_clk; + debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk)); + g_ldb_clk = &ldb_clk; + debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk)); + ipu_reset(); + + clk_set_parent(g_pixel_clk[0], g_ipu_clk); + clk_set_parent(g_pixel_clk[1], g_ipu_clk); + clk_enable(g_ipu_clk); + + g_di_clk[0] = NULL; + g_di_clk[1] = NULL; + + __raw_writel(0x807FFFFF, IPU_MEM_RST); + while (__raw_readl(IPU_MEM_RST) & 0x80000000) + ; + + ipu_init_dc_mappings(); + + __raw_writel(0, IPU_INT_CTRL(5)); + __raw_writel(0, IPU_INT_CTRL(6)); + __raw_writel(0, IPU_INT_CTRL(9)); + __raw_writel(0, IPU_INT_CTRL(10)); + + /* DMFC Init */ + ipu_dmfc_init(DMFC_NORMAL, 1); + + /* Set sync refresh channels as high priority */ + __raw_writel(0x18800000L, IDMAC_CHA_PRI(0)); + + /* Set MCU_T to divide MCU access window into 2 */ + __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN); + + clk_disable(g_ipu_clk); + + return 0; +} + +void ipu_dump_registers(void) +{ + debug("IPU_CONF = \t0x%08X\n", __raw_readl(IPU_CONF)); + debug("IDMAC_CONF = \t0x%08X\n", __raw_readl(IDMAC_CONF)); + debug("IDMAC_CHA_EN1 = \t0x%08X\n", + __raw_readl(IDMAC_CHA_EN(0))); + debug("IDMAC_CHA_EN2 = \t0x%08X\n", + __raw_readl(IDMAC_CHA_EN(32))); + debug("IDMAC_CHA_PRI1 = \t0x%08X\n", + __raw_readl(IDMAC_CHA_PRI(0))); + debug("IDMAC_CHA_PRI2 = \t0x%08X\n", + __raw_readl(IDMAC_CHA_PRI(32))); + debug("IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n", + __raw_readl(IPU_CHA_DB_MODE_SEL(0))); + debug("IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n", + __raw_readl(IPU_CHA_DB_MODE_SEL(32))); + debug("DMFC_WR_CHAN = \t0x%08X\n", + __raw_readl(DMFC_WR_CHAN)); + debug("DMFC_WR_CHAN_DEF = \t0x%08X\n", + __raw_readl(DMFC_WR_CHAN_DEF)); + debug("DMFC_DP_CHAN = \t0x%08X\n", + __raw_readl(DMFC_DP_CHAN)); + debug("DMFC_DP_CHAN_DEF = \t0x%08X\n", + __raw_readl(DMFC_DP_CHAN_DEF)); + debug("DMFC_IC_CTRL = \t0x%08X\n", + __raw_readl(DMFC_IC_CTRL)); + debug("IPU_FS_PROC_FLOW1 = \t0x%08X\n", + __raw_readl(IPU_FS_PROC_FLOW1)); + debug("IPU_FS_PROC_FLOW2 = \t0x%08X\n", + __raw_readl(IPU_FS_PROC_FLOW2)); + debug("IPU_FS_PROC_FLOW3 = \t0x%08X\n", + __raw_readl(IPU_FS_PROC_FLOW3)); + debug("IPU_FS_DISP_FLOW1 = \t0x%08X\n", + __raw_readl(IPU_FS_DISP_FLOW1)); +} + +/* + * This function is called to initialize a logical IPU channel. + * + * @param channel Input parameter for the logical channel ID to init. + * + * @param params Input parameter containing union of channel + * initialization parameters. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params) +{ + int ret = 0; + uint32_t ipu_conf; + + debug("init channel = %d\n", IPU_CHAN_ID(channel)); + + if (g_ipu_clk_enabled == 0) { + g_ipu_clk_enabled = 1; + clk_enable(g_ipu_clk); + } + + + if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) { + printf("Warning: channel already initialized %d\n", + IPU_CHAN_ID(channel)); + } + + ipu_conf = __raw_readl(IPU_CONF); + + switch (channel) { + case MEM_DC_SYNC: + if (params->mem_dc_sync.di > 1) { + ret = -EINVAL; + goto err; + } + + g_dc_di_assignment[1] = params->mem_dc_sync.di; + ipu_dc_init(1, params->mem_dc_sync.di, + params->mem_dc_sync.interlaced); + ipu_di_use_count[params->mem_dc_sync.di]++; + ipu_dc_use_count++; + ipu_dmfc_use_count++; + break; + case MEM_BG_SYNC: + if (params->mem_dp_bg_sync.di > 1) { + ret = -EINVAL; + goto err; + } + + g_dc_di_assignment[5] = params->mem_dp_bg_sync.di; + ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt, + params->mem_dp_bg_sync.out_pixel_fmt); + ipu_dc_init(5, params->mem_dp_bg_sync.di, + params->mem_dp_bg_sync.interlaced); + ipu_di_use_count[params->mem_dp_bg_sync.di]++; + ipu_dc_use_count++; + ipu_dp_use_count++; + ipu_dmfc_use_count++; + break; + case MEM_FG_SYNC: + ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt, + params->mem_dp_fg_sync.out_pixel_fmt); + + ipu_dc_use_count++; + ipu_dp_use_count++; + ipu_dmfc_use_count++; + break; + default: + printf("Missing channel initialization\n"); + break; + } + + /* Enable IPU sub module */ + g_channel_init_mask |= 1L << IPU_CHAN_ID(channel); + if (ipu_dc_use_count == 1) + ipu_conf |= IPU_CONF_DC_EN; + if (ipu_dp_use_count == 1) + ipu_conf |= IPU_CONF_DP_EN; + if (ipu_dmfc_use_count == 1) + ipu_conf |= IPU_CONF_DMFC_EN; + if (ipu_di_use_count[0] == 1) { + ipu_conf |= IPU_CONF_DI0_EN; + } + if (ipu_di_use_count[1] == 1) { + ipu_conf |= IPU_CONF_DI1_EN; + } + + __raw_writel(ipu_conf, IPU_CONF); + +err: + return ret; +} + +/* + * This function is called to uninitialize a logical IPU channel. + * + * @param channel Input parameter for the logical channel ID to uninit. + */ +void ipu_uninit_channel(ipu_channel_t channel) +{ + uint32_t reg; + uint32_t in_dma, out_dma = 0; + uint32_t ipu_conf; + + if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) { + debug("Channel already uninitialized %d\n", + IPU_CHAN_ID(channel)); + return; + } + + /* + * Make sure channel is disabled + * Get input and output dma channels + */ + in_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); + out_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER); + + if (idma_is_set(IDMAC_CHA_EN, in_dma) || + idma_is_set(IDMAC_CHA_EN, out_dma)) { + printf( + "Channel %d is not disabled, disable first\n", + IPU_CHAN_ID(channel)); + return; + } + + ipu_conf = __raw_readl(IPU_CONF); + + /* Reset the double buffer */ + reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma)); + __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma)); + reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma)); + __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma)); + + switch (channel) { + case MEM_DC_SYNC: + ipu_dc_uninit(1); + ipu_di_use_count[g_dc_di_assignment[1]]--; + ipu_dc_use_count--; + ipu_dmfc_use_count--; + break; + case MEM_BG_SYNC: + ipu_dp_uninit(channel); + ipu_dc_uninit(5); + ipu_di_use_count[g_dc_di_assignment[5]]--; + ipu_dc_use_count--; + ipu_dp_use_count--; + ipu_dmfc_use_count--; + break; + case MEM_FG_SYNC: + ipu_dp_uninit(channel); + ipu_dc_use_count--; + ipu_dp_use_count--; + ipu_dmfc_use_count--; + break; + default: + break; + } + + g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel)); + + if (ipu_dc_use_count == 0) + ipu_conf &= ~IPU_CONF_DC_EN; + if (ipu_dp_use_count == 0) + ipu_conf &= ~IPU_CONF_DP_EN; + if (ipu_dmfc_use_count == 0) + ipu_conf &= ~IPU_CONF_DMFC_EN; + if (ipu_di_use_count[0] == 0) { + ipu_conf &= ~IPU_CONF_DI0_EN; + } + if (ipu_di_use_count[1] == 0) { + ipu_conf &= ~IPU_CONF_DI1_EN; + } + + __raw_writel(ipu_conf, IPU_CONF); + + if (ipu_conf == 0) { + clk_disable(g_ipu_clk); + g_ipu_clk_enabled = 0; + } + +} + +static inline void ipu_ch_param_dump(int ch) +{ +#ifdef DEBUG + struct ipu_ch_param *p = ipu_ch_param_addr(ch); + debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch, + p->word[0].data[0], p->word[0].data[1], p->word[0].data[2], + p->word[0].data[3], p->word[0].data[4]); + debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch, + p->word[1].data[0], p->word[1].data[1], p->word[1].data[2], + p->word[1].data[3], p->word[1].data[4]); + debug("PFS 0x%x, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4)); + debug("BPP 0x%x, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3)); + debug("NPB 0x%x\n", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7)); + + debug("FW %d, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13)); + debug("FH %d, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12)); + debug("Stride %d\n", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14)); + + debug("Width0 %d+1, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3)); + debug("Width1 %d+1, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3)); + debug("Width2 %d+1, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3)); + debug("Width3 %d+1, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3)); + debug("Offset0 %d, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5)); + debug("Offset1 %d, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5)); + debug("Offset2 %d, ", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5)); + debug("Offset3 %d\n", + ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5)); +#endif +} + +static inline void ipu_ch_params_set_packing(struct ipu_ch_param *p, + int red_width, int red_offset, + int green_width, int green_offset, + int blue_width, int blue_offset, + int alpha_width, int alpha_offset) +{ + /* Setup red width and offset */ + ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1); + ipu_ch_param_set_field(p, 1, 128, 5, red_offset); + /* Setup green width and offset */ + ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1); + ipu_ch_param_set_field(p, 1, 133, 5, green_offset); + /* Setup blue width and offset */ + ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1); + ipu_ch_param_set_field(p, 1, 138, 5, blue_offset); + /* Setup alpha width and offset */ + ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1); + ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset); +} + +static void ipu_ch_param_init(int ch, + uint32_t pixel_fmt, uint32_t width, + uint32_t height, uint32_t stride, + uint32_t u, uint32_t v, + uint32_t uv_stride, dma_addr_t addr0, + dma_addr_t addr1) +{ + uint32_t u_offset = 0; + uint32_t v_offset = 0; + struct ipu_ch_param params; + + memset(¶ms, 0, sizeof(params)); + + ipu_ch_param_set_field(¶ms, 0, 125, 13, width - 1); + + if ((ch == 8) || (ch == 9) || (ch == 10)) { + ipu_ch_param_set_field(¶ms, 0, 138, 12, (height / 2) - 1); + ipu_ch_param_set_field(¶ms, 1, 102, 14, (stride * 2) - 1); + } else { + ipu_ch_param_set_field(¶ms, 0, 138, 12, height - 1); + ipu_ch_param_set_field(¶ms, 1, 102, 14, stride - 1); + } + + ipu_ch_param_set_field(¶ms, 1, 0, 29, addr0 >> 3); + ipu_ch_param_set_field(¶ms, 1, 29, 29, addr1 >> 3); + + switch (pixel_fmt) { + case IPU_PIX_FMT_GENERIC: + /*Represents 8-bit Generic data */ + ipu_ch_param_set_field(¶ms, 0, 107, 3, 5); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 6); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 63); /* burst size */ + + break; + case IPU_PIX_FMT_GENERIC_32: + /*Represents 32-bit Generic data */ + break; + case IPU_PIX_FMT_RGB565: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ + + ipu_ch_params_set_packing(¶ms, 5, 0, 6, 5, 5, 11, 8, 16); + break; + case IPU_PIX_FMT_BGR24: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 1); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 19); /* burst size */ + + ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 8, 24); + break; + case IPU_PIX_FMT_RGB24: + case IPU_PIX_FMT_YUV444: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 1); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 19); /* burst size */ + + ipu_ch_params_set_packing(¶ms, 8, 16, 8, 8, 8, 0, 8, 24); + break; + case IPU_PIX_FMT_BGRA32: + case IPU_PIX_FMT_BGR32: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ + + ipu_ch_params_set_packing(¶ms, 8, 8, 8, 16, 8, 24, 8, 0); + break; + case IPU_PIX_FMT_RGBA32: + case IPU_PIX_FMT_RGB32: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ + + ipu_ch_params_set_packing(¶ms, 8, 24, 8, 16, 8, 8, 8, 0); + break; + case IPU_PIX_FMT_ABGR32: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 0); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 7); /* pix format */ + + ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 8, 24); + break; + case IPU_PIX_FMT_UYVY: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 0xA); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); /* burst size */ + break; + case IPU_PIX_FMT_YUYV: + ipu_ch_param_set_field(¶ms, 0, 107, 3, 3); /* bits/pixel */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 0x8); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ + break; + case IPU_PIX_FMT_YUV420P2: + case IPU_PIX_FMT_YUV420P: + ipu_ch_param_set_field(¶ms, 1, 85, 4, 2); /* pix format */ + + if (uv_stride < stride / 2) + uv_stride = stride / 2; + + u_offset = stride * height; + v_offset = u_offset + (uv_stride * height / 2); + /* burst size */ + if ((ch == 8) || (ch == 9) || (ch == 10)) { + ipu_ch_param_set_field(¶ms, 1, 78, 7, 15); + uv_stride = uv_stride*2; + } else { + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); + } + break; + case IPU_PIX_FMT_YVU422P: + /* BPP & pixel format */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 1); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ + + if (uv_stride < stride / 2) + uv_stride = stride / 2; + + v_offset = (v == 0) ? stride * height : v; + u_offset = (u == 0) ? v_offset + v_offset / 2 : u; + break; + case IPU_PIX_FMT_YUV422P: + /* BPP & pixel format */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 1); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ + + if (uv_stride < stride / 2) + uv_stride = stride / 2; + + u_offset = (u == 0) ? stride * height : u; + v_offset = (v == 0) ? u_offset + u_offset / 2 : v; + break; + case IPU_PIX_FMT_NV12: + /* BPP & pixel format */ + ipu_ch_param_set_field(¶ms, 1, 85, 4, 4); /* pix format */ + ipu_ch_param_set_field(¶ms, 1, 78, 7, 31); /* burst size */ + uv_stride = stride; + u_offset = (u == 0) ? stride * height : u; + break; + default: + puts("mxc ipu: unimplemented pixel format\n"); + break; + } + + + if (uv_stride) + ipu_ch_param_set_field(¶ms, 1, 128, 14, uv_stride - 1); + + /* Get the uv offset from user when need cropping */ + if (u || v) { + u_offset = u; + v_offset = v; + } + + /* UBO and VBO are 22-bit */ + if (u_offset/8 > 0x3fffff) + puts("The value of U offset exceeds IPU limitation\n"); + if (v_offset/8 > 0x3fffff) + puts("The value of V offset exceeds IPU limitation\n"); + + ipu_ch_param_set_field(¶ms, 0, 46, 22, u_offset / 8); + ipu_ch_param_set_field(¶ms, 0, 68, 22, v_offset / 8); + + debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch)); + memcpy(ipu_ch_param_addr(ch), ¶ms, sizeof(params)); +}; + +/* + * This function is called to initialize a buffer for logical IPU channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to initialize. + * + * @param pixel_fmt Input parameter for pixel format of buffer. + * Pixel format is a FOURCC ASCII code. + * + * @param width Input parameter for width of buffer in pixels. + * + * @param height Input parameter for height of buffer in pixels. + * + * @param stride Input parameter for stride length of buffer + * in pixels. + * + * @param phyaddr_0 Input parameter buffer 0 physical address. + * + * @param phyaddr_1 Input parameter buffer 1 physical address. + * Setting this to a value other than NULL enables + * double buffering mode. + * + * @param u private u offset for additional cropping, + * zero if not used. + * + * @param v private v offset for additional cropping, + * zero if not used. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type, + uint32_t pixel_fmt, + uint16_t width, uint16_t height, + uint32_t stride, + dma_addr_t phyaddr_0, dma_addr_t phyaddr_1, + uint32_t u, uint32_t v) +{ + uint32_t reg; + uint32_t dma_chan; + + dma_chan = channel_2_dma(channel, type); + if (!idma_is_valid(dma_chan)) + return -EINVAL; + + if (stride < width * bytes_per_pixel(pixel_fmt)) + stride = width * bytes_per_pixel(pixel_fmt); + + if (stride % 4) { + printf( + "Stride not 32-bit aligned, stride = %d\n", stride); + return -EINVAL; + } + /* Build parameter memory data for DMA channel */ + ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0, + phyaddr_0, phyaddr_1); + + if (ipu_is_dmfc_chan(dma_chan)) { + ipu_dmfc_set_wait4eot(dma_chan, width); + } + + if (idma_is_set(IDMAC_CHA_PRI, dma_chan)) + ipu_ch_param_set_high_priority(dma_chan); + + ipu_ch_param_dump(dma_chan); + + reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan)); + if (phyaddr_1) + reg |= idma_mask(dma_chan); + else + reg &= ~idma_mask(dma_chan); + __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan)); + + /* Reset to buffer 0 */ + __raw_writel(idma_mask(dma_chan), IPU_CHA_CUR_BUF(dma_chan)); + + return 0; +} + +/* + * This function enables a logical channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_enable_channel(ipu_channel_t channel) +{ + uint32_t reg; + uint32_t in_dma; + uint32_t out_dma; + + if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) { + printf("Warning: channel already enabled %d\n", + IPU_CHAN_ID(channel)); + } + + /* Get input and output dma channels */ + out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); + in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER); + + if (idma_is_valid(in_dma)) { + reg = __raw_readl(IDMAC_CHA_EN(in_dma)); + __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma)); + } + if (idma_is_valid(out_dma)) { + reg = __raw_readl(IDMAC_CHA_EN(out_dma)); + __raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma)); + } + + if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) || + (channel == MEM_FG_SYNC)) + ipu_dp_dc_enable(channel); + + g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel); + + return 0; +} + +/* + * This function clear buffer ready for a logical channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param type Input parameter which buffer to clear. + * + * @param bufNum Input parameter for which buffer number clear + * ready state. + * + */ +void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type, + uint32_t bufNum) +{ + uint32_t dma_ch = channel_2_dma(channel, type); + + if (!idma_is_valid(dma_ch)) + return; + + __raw_writel(0xF0000000, IPU_GPR); /* write one to clear */ + if (bufNum == 0) { + if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) { + __raw_writel(idma_mask(dma_ch), + IPU_CHA_BUF0_RDY(dma_ch)); + } + } else { + if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) { + __raw_writel(idma_mask(dma_ch), + IPU_CHA_BUF1_RDY(dma_ch)); + } + } + __raw_writel(0x0, IPU_GPR); /* write one to set */ +} + +/* + * This function disables a logical channel. + * + * @param channel Input parameter for the logical channel ID. + * + * @param wait_for_stop Flag to set whether to wait for channel end + * of frame or return immediately. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t ipu_disable_channel(ipu_channel_t channel) +{ + uint32_t reg; + uint32_t in_dma; + uint32_t out_dma; + + if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) { + debug("Channel already disabled %d\n", + IPU_CHAN_ID(channel)); + return 0; + } + + /* Get input and output dma channels */ + out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER); + in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER); + + if ((idma_is_valid(in_dma) && + !idma_is_set(IDMAC_CHA_EN, in_dma)) + && (idma_is_valid(out_dma) && + !idma_is_set(IDMAC_CHA_EN, out_dma))) + return -EINVAL; + + if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) || + (channel == MEM_DC_SYNC)) { + ipu_dp_dc_disable(channel, 0); + } + + /* Disable DMA channel(s) */ + if (idma_is_valid(in_dma)) { + reg = __raw_readl(IDMAC_CHA_EN(in_dma)); + __raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma)); + __raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma)); + } + if (idma_is_valid(out_dma)) { + reg = __raw_readl(IDMAC_CHA_EN(out_dma)); + __raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma)); + __raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma)); + } + + g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel)); + + /* Set channel buffers NOT to be ready */ + if (idma_is_valid(in_dma)) { + ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0); + ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1); + } + if (idma_is_valid(out_dma)) { + ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0); + ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1); + } + + return 0; +} + +uint32_t bytes_per_pixel(uint32_t fmt) +{ + switch (fmt) { + case IPU_PIX_FMT_GENERIC: /*generic data */ + case IPU_PIX_FMT_RGB332: + case IPU_PIX_FMT_YUV420P: + case IPU_PIX_FMT_YUV422P: + return 1; + break; + case IPU_PIX_FMT_RGB565: + case IPU_PIX_FMT_YUYV: + case IPU_PIX_FMT_UYVY: + return 2; + break; + case IPU_PIX_FMT_BGR24: + case IPU_PIX_FMT_RGB24: + return 3; + break; + case IPU_PIX_FMT_GENERIC_32: /*generic data */ + case IPU_PIX_FMT_BGR32: + case IPU_PIX_FMT_BGRA32: + case IPU_PIX_FMT_RGB32: + case IPU_PIX_FMT_RGBA32: + case IPU_PIX_FMT_ABGR32: + return 4; + break; + default: + return 1; + break; + } + return 0; +} + +ipu_color_space_t format_to_colorspace(uint32_t fmt) +{ + switch (fmt) { + case IPU_PIX_FMT_RGB666: + case IPU_PIX_FMT_RGB565: + case IPU_PIX_FMT_BGR24: + case IPU_PIX_FMT_RGB24: + case IPU_PIX_FMT_BGR32: + case IPU_PIX_FMT_BGRA32: + case IPU_PIX_FMT_RGB32: + case IPU_PIX_FMT_RGBA32: + case IPU_PIX_FMT_ABGR32: + case IPU_PIX_FMT_LVDS666: + case IPU_PIX_FMT_LVDS888: + return RGB; + break; + + default: + return YCbCr; + break; + } + return RGB; +} diff --git a/qemu/roms/u-boot/drivers/video/ipu_disp.c b/qemu/roms/u-boot/drivers/video/ipu_disp.c new file mode 100644 index 000000000..cefd2dc14 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/ipu_disp.c @@ -0,0 +1,1335 @@ +/* + * Porting to u-boot: + * + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de + * + * Linux IPU driver for MX51: + * + * (C) Copyright 2005-2010 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* #define DEBUG */ + +#include <common.h> +#include <linux/types.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> +#include "ipu.h" +#include "ipu_regs.h" + +enum csc_type_t { + RGB2YUV = 0, + YUV2RGB, + RGB2RGB, + YUV2YUV, + CSC_NONE, + CSC_NUM +}; + +struct dp_csc_param_t { + int mode; + void *coeff; +}; + +#define SYNC_WAVE 0 + +/* DC display ID assignments */ +#define DC_DISP_ID_SYNC(di) (di) +#define DC_DISP_ID_SERIAL 2 +#define DC_DISP_ID_ASYNC 3 + +int dmfc_type_setup; +static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23; +int g_di1_tvout; + +extern struct clk *g_ipu_clk; +extern struct clk *g_ldb_clk; +extern struct clk *g_di_clk[2]; +extern struct clk *g_pixel_clk[2]; + +extern unsigned char g_ipu_clk_enabled; +extern unsigned char g_dc_di_assignment[]; + +void ipu_dmfc_init(int dmfc_type, int first) +{ + u32 dmfc_wr_chan, dmfc_dp_chan; + + if (first) { + if (dmfc_type_setup > dmfc_type) + dmfc_type = dmfc_type_setup; + else + dmfc_type_setup = dmfc_type; + + /* disable DMFC-IC channel*/ + __raw_writel(0x2, DMFC_IC_CTRL); + } else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) { + printf("DMFC high resolution has set, will not change\n"); + return; + } else + dmfc_type_setup = dmfc_type; + + if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) { + /* 1 - segment 0~3; + * 5B - segement 4, 5; + * 5F - segement 6, 7; + * 1C, 2C and 6B, 6F unused; + */ + debug("IPU DMFC DC HIGH RES: 1(0~3), 5B(4,5), 5F(6,7)\n"); + dmfc_wr_chan = 0x00000088; + dmfc_dp_chan = 0x00009694; + dmfc_size_28 = 256 * 4; + dmfc_size_29 = 0; + dmfc_size_24 = 0; + dmfc_size_27 = 128 * 4; + dmfc_size_23 = 128 * 4; + } else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) { + /* 1 - segment 0, 1; + * 5B - segement 2~5; + * 5F - segement 6,7; + * 1C, 2C and 6B, 6F unused; + */ + debug("IPU DMFC DP HIGH RES: 1(0,1), 5B(2~5), 5F(6,7)\n"); + dmfc_wr_chan = 0x00000090; + dmfc_dp_chan = 0x0000968a; + dmfc_size_28 = 128 * 4; + dmfc_size_29 = 0; + dmfc_size_24 = 0; + dmfc_size_27 = 128 * 4; + dmfc_size_23 = 256 * 4; + } else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) { + /* 5B - segement 0~3; + * 5F - segement 4~7; + * 1, 1C, 2C and 6B, 6F unused; + */ + debug("IPU DMFC ONLY-DP HIGH RES: 5B(0~3), 5F(4~7)\n"); + dmfc_wr_chan = 0x00000000; + dmfc_dp_chan = 0x00008c88; + dmfc_size_28 = 0; + dmfc_size_29 = 0; + dmfc_size_24 = 0; + dmfc_size_27 = 256 * 4; + dmfc_size_23 = 256 * 4; + } else { + /* 1 - segment 0, 1; + * 5B - segement 4, 5; + * 5F - segement 6, 7; + * 1C, 2C and 6B, 6F unused; + */ + debug("IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n"); + dmfc_wr_chan = 0x00000090; + dmfc_dp_chan = 0x00009694; + dmfc_size_28 = 128 * 4; + dmfc_size_29 = 0; + dmfc_size_24 = 0; + dmfc_size_27 = 128 * 4; + dmfc_size_23 = 128 * 4; + } + __raw_writel(dmfc_wr_chan, DMFC_WR_CHAN); + __raw_writel(0x202020F6, DMFC_WR_CHAN_DEF); + __raw_writel(dmfc_dp_chan, DMFC_DP_CHAN); + /* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */ + __raw_writel(0x2020F6F6, DMFC_DP_CHAN_DEF); +} + +void ipu_dmfc_set_wait4eot(int dma_chan, int width) +{ + u32 dmfc_gen1 = __raw_readl(DMFC_GENERAL1); + + if (width >= HIGH_RESOLUTION_WIDTH) { + if (dma_chan == 23) + ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DP, 0); + else if (dma_chan == 28) + ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DC, 0); + } + + if (dma_chan == 23) { /*5B*/ + if (dmfc_size_23 / width > 3) + dmfc_gen1 |= 1UL << 20; + else + dmfc_gen1 &= ~(1UL << 20); + } else if (dma_chan == 24) { /*6B*/ + if (dmfc_size_24 / width > 1) + dmfc_gen1 |= 1UL << 22; + else + dmfc_gen1 &= ~(1UL << 22); + } else if (dma_chan == 27) { /*5F*/ + if (dmfc_size_27 / width > 2) + dmfc_gen1 |= 1UL << 21; + else + dmfc_gen1 &= ~(1UL << 21); + } else if (dma_chan == 28) { /*1*/ + if (dmfc_size_28 / width > 2) + dmfc_gen1 |= 1UL << 16; + else + dmfc_gen1 &= ~(1UL << 16); + } else if (dma_chan == 29) { /*6F*/ + if (dmfc_size_29 / width > 1) + dmfc_gen1 |= 1UL << 23; + else + dmfc_gen1 &= ~(1UL << 23); + } + + __raw_writel(dmfc_gen1, DMFC_GENERAL1); +} + +static void ipu_di_data_wave_config(int di, + int wave_gen, + int access_size, int component_size) +{ + u32 reg; + reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) | + (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET); + __raw_writel(reg, DI_DW_GEN(di, wave_gen)); +} + +static void ipu_di_data_pin_config(int di, int wave_gen, int di_pin, int set, + int up, int down) +{ + u32 reg; + + reg = __raw_readl(DI_DW_GEN(di, wave_gen)); + reg &= ~(0x3 << (di_pin * 2)); + reg |= set << (di_pin * 2); + __raw_writel(reg, DI_DW_GEN(di, wave_gen)); + + __raw_writel((down << 16) | up, DI_DW_SET(di, wave_gen, set)); +} + +static void ipu_di_sync_config(int di, int wave_gen, + int run_count, int run_src, + int offset_count, int offset_src, + int repeat_count, int cnt_clr_src, + int cnt_polarity_gen_en, + int cnt_polarity_clr_src, + int cnt_polarity_trigger_src, + int cnt_up, int cnt_down) +{ + u32 reg; + + if ((run_count >= 0x1000) || (offset_count >= 0x1000) || + (repeat_count >= 0x1000) || + (cnt_up >= 0x400) || (cnt_down >= 0x400)) { + printf("DI%d counters out of range.\n", di); + return; + } + + reg = (run_count << 19) | (++run_src << 16) | + (offset_count << 3) | ++offset_src; + __raw_writel(reg, DI_SW_GEN0(di, wave_gen)); + reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) | + (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9); + reg |= (cnt_down << 16) | cnt_up; + if (repeat_count == 0) { + /* Enable auto reload */ + reg |= 0x10000000; + } + __raw_writel(reg, DI_SW_GEN1(di, wave_gen)); + reg = __raw_readl(DI_STP_REP(di, wave_gen)); + reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1))); + reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1)); + __raw_writel(reg, DI_STP_REP(di, wave_gen)); +} + +static void ipu_dc_map_config(int map, int byte_num, int offset, int mask) +{ + int ptr = map * 3 + byte_num; + u32 reg; + + reg = __raw_readl(DC_MAP_CONF_VAL(ptr)); + reg &= ~(0xFFFF << (16 * (ptr & 0x1))); + reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1)); + __raw_writel(reg, DC_MAP_CONF_VAL(ptr)); + + reg = __raw_readl(DC_MAP_CONF_PTR(map)); + reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num))); + reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num)); + __raw_writel(reg, DC_MAP_CONF_PTR(map)); +} + +static void ipu_dc_map_clear(int map) +{ + u32 reg = __raw_readl(DC_MAP_CONF_PTR(map)); + __raw_writel(reg & ~(0xFFFF << (16 * (map & 0x1))), + DC_MAP_CONF_PTR(map)); +} + +static void ipu_dc_write_tmpl(int word, u32 opcode, u32 operand, int map, + int wave, int glue, int sync) +{ + u32 reg; + int stop = 1; + + reg = sync; + reg |= (glue << 4); + reg |= (++wave << 11); + reg |= (++map << 15); + reg |= (operand << 20) & 0xFFF00000; + __raw_writel(reg, ipu_dc_tmpl_reg + word * 2); + + reg = (operand >> 12); + reg |= opcode << 4; + reg |= (stop << 9); + __raw_writel(reg, ipu_dc_tmpl_reg + word * 2 + 1); +} + +static void ipu_dc_link_event(int chan, int event, int addr, int priority) +{ + u32 reg; + + reg = __raw_readl(DC_RL_CH(chan, event)); + reg &= ~(0xFFFF << (16 * (event & 0x1))); + reg |= ((addr << 8) | priority) << (16 * (event & 0x1)); + __raw_writel(reg, DC_RL_CH(chan, event)); +} + +/* Y = R * 1.200 + G * 2.343 + B * .453 + 0.250; + * U = R * -.672 + G * -1.328 + B * 2.000 + 512.250.; + * V = R * 2.000 + G * -1.672 + B * -.328 + 512.250.; + */ +static const int rgb2ycbcr_coeff[5][3] = { + {0x4D, 0x96, 0x1D}, + {0x3D5, 0x3AB, 0x80}, + {0x80, 0x395, 0x3EB}, + {0x0000, 0x0200, 0x0200}, /* B0, B1, B2 */ + {0x2, 0x2, 0x2}, /* S0, S1, S2 */ +}; + +/* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128)); + * G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128)); + * B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); + */ +static const int ycbcr2rgb_coeff[5][3] = { + {0x095, 0x000, 0x0CC}, + {0x095, 0x3CE, 0x398}, + {0x095, 0x0FF, 0x000}, + {0x3E42, 0x010A, 0x3DD6}, /*B0,B1,B2 */ + {0x1, 0x1, 0x1}, /*S0,S1,S2 */ +}; + +#define mask_a(a) ((u32)(a) & 0x3FF) +#define mask_b(b) ((u32)(b) & 0x3FFF) + +/* Pls keep S0, S1 and S2 as 0x2 by using this convertion */ +static int rgb_to_yuv(int n, int red, int green, int blue) +{ + int c; + c = red * rgb2ycbcr_coeff[n][0]; + c += green * rgb2ycbcr_coeff[n][1]; + c += blue * rgb2ycbcr_coeff[n][2]; + c /= 16; + c += rgb2ycbcr_coeff[3][n] * 4; + c += 8; + c /= 16; + if (c < 0) + c = 0; + if (c > 255) + c = 255; + return c; +} + +/* + * Row is for BG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE + * Column is for FG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE + */ +static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = { + { + {DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff}, + {0, 0}, + {0, 0}, + {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}, + {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff} + }, + { + {0, 0}, + {DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff}, + {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}, + {0, 0}, + {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff} + }, + { + {0, 0}, + {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, + {0, 0}, + {0, 0}, + {0, 0} + }, + { + {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, + {0, 0}, + {0, 0}, + {0, 0}, + {0, 0} + }, + { + {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, + {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, + {0, 0}, + {0, 0}, + {0, 0} + } +}; + +static enum csc_type_t fg_csc_type = CSC_NONE, bg_csc_type = CSC_NONE; +static int color_key_4rgb = 1; + +void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param, + unsigned char srm_mode_update) +{ + u32 reg; + const int (*coeff)[5][3]; + + if (dp_csc_param.mode >= 0) { + reg = __raw_readl(DP_COM_CONF()); + reg &= ~DP_COM_CONF_CSC_DEF_MASK; + reg |= dp_csc_param.mode; + __raw_writel(reg, DP_COM_CONF()); + } + + coeff = dp_csc_param.coeff; + + if (coeff) { + __raw_writel(mask_a((*coeff)[0][0]) | + (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0()); + __raw_writel(mask_a((*coeff)[0][2]) | + (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1()); + __raw_writel(mask_a((*coeff)[1][1]) | + (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2()); + __raw_writel(mask_a((*coeff)[2][0]) | + (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3()); + __raw_writel(mask_a((*coeff)[2][2]) | + (mask_b((*coeff)[3][0]) << 16) | + ((*coeff)[4][0] << 30), DP_CSC_0()); + __raw_writel(mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) | + (mask_b((*coeff)[3][2]) << 16) | + ((*coeff)[4][2] << 30), DP_CSC_1()); + } + + if (srm_mode_update) { + reg = __raw_readl(IPU_SRM_PRI2) | 0x8; + __raw_writel(reg, IPU_SRM_PRI2); + } +} + +int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt, + uint32_t out_pixel_fmt) +{ + int in_fmt, out_fmt; + int dp; + int partial = 0; + uint32_t reg; + + if (channel == MEM_FG_SYNC) { + dp = DP_SYNC; + partial = 1; + } else if (channel == MEM_BG_SYNC) { + dp = DP_SYNC; + partial = 0; + } else if (channel == MEM_BG_ASYNC0) { + dp = DP_ASYNC0; + partial = 0; + } else { + return -EINVAL; + } + + in_fmt = format_to_colorspace(in_pixel_fmt); + out_fmt = format_to_colorspace(out_pixel_fmt); + + if (partial) { + if (in_fmt == RGB) { + if (out_fmt == RGB) + fg_csc_type = RGB2RGB; + else + fg_csc_type = RGB2YUV; + } else { + if (out_fmt == RGB) + fg_csc_type = YUV2RGB; + else + fg_csc_type = YUV2YUV; + } + } else { + if (in_fmt == RGB) { + if (out_fmt == RGB) + bg_csc_type = RGB2RGB; + else + bg_csc_type = RGB2YUV; + } else { + if (out_fmt == RGB) + bg_csc_type = YUV2RGB; + else + bg_csc_type = YUV2YUV; + } + } + + /* Transform color key from rgb to yuv if CSC is enabled */ + reg = __raw_readl(DP_COM_CONF()); + if (color_key_4rgb && (reg & DP_COM_CONF_GWCKE) && + (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) || + ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) || + ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) || + ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB)))) { + int red, green, blue; + int y, u, v; + uint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL()) & + 0xFFFFFFL; + + debug("_ipu_dp_init color key 0x%x need change to yuv fmt!\n", + color_key); + + red = (color_key >> 16) & 0xFF; + green = (color_key >> 8) & 0xFF; + blue = color_key & 0xFF; + + y = rgb_to_yuv(0, red, green, blue); + u = rgb_to_yuv(1, red, green, blue); + v = rgb_to_yuv(2, red, green, blue); + color_key = (y << 16) | (u << 8) | v; + + reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L; + __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL()); + color_key_4rgb = 0; + + debug("_ipu_dp_init color key change to yuv fmt 0x%x!\n", + color_key); + } + + ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 1); + + return 0; +} + +void ipu_dp_uninit(ipu_channel_t channel) +{ + int dp; + int partial = 0; + + if (channel == MEM_FG_SYNC) { + dp = DP_SYNC; + partial = 1; + } else if (channel == MEM_BG_SYNC) { + dp = DP_SYNC; + partial = 0; + } else if (channel == MEM_BG_ASYNC0) { + dp = DP_ASYNC0; + partial = 0; + } else { + return; + } + + if (partial) + fg_csc_type = CSC_NONE; + else + bg_csc_type = CSC_NONE; + + ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 0); +} + +void ipu_dc_init(int dc_chan, int di, unsigned char interlaced) +{ + u32 reg = 0; + + if ((dc_chan == 1) || (dc_chan == 5)) { + if (interlaced) { + ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 3); + ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 2); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 1); + } else { + if (di) { + ipu_dc_link_event(dc_chan, DC_EVT_NL, 2, 3); + ipu_dc_link_event(dc_chan, DC_EVT_EOL, 3, 2); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, + 4, 1); + } else { + ipu_dc_link_event(dc_chan, DC_EVT_NL, 5, 3); + ipu_dc_link_event(dc_chan, DC_EVT_EOL, 6, 2); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, + 7, 1); + } + } + ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0); + + reg = 0x2; + reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET; + reg |= di << 2; + if (interlaced) + reg |= DC_WR_CH_CONF_FIELD_MODE; + } else if ((dc_chan == 8) || (dc_chan == 9)) { + /* async channels */ + ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1); + + reg = 0x3; + reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET; + } + __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); + + __raw_writel(0x00000000, DC_WR_CH_ADDR(dc_chan)); + + __raw_writel(0x00000084, DC_GEN); +} + +void ipu_dc_uninit(int dc_chan) +{ + if ((dc_chan == 1) || (dc_chan == 5)) { + ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0); + } else if ((dc_chan == 8) || (dc_chan == 9)) { + ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0); + ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0); + } +} + +int ipu_chan_is_interlaced(ipu_channel_t channel) +{ + if (channel == MEM_DC_SYNC) + return !!(__raw_readl(DC_WR_CH_CONF_1) & + DC_WR_CH_CONF_FIELD_MODE); + else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC)) + return !!(__raw_readl(DC_WR_CH_CONF_5) & + DC_WR_CH_CONF_FIELD_MODE); + return 0; +} + +void ipu_dp_dc_enable(ipu_channel_t channel) +{ + int di; + uint32_t reg; + uint32_t dc_chan; + + if (channel == MEM_FG_SYNC) + dc_chan = 5; + if (channel == MEM_DC_SYNC) + dc_chan = 1; + else if (channel == MEM_BG_SYNC) + dc_chan = 5; + else + return; + + if (channel == MEM_FG_SYNC) { + /* Enable FG channel */ + reg = __raw_readl(DP_COM_CONF()); + __raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF()); + + reg = __raw_readl(IPU_SRM_PRI2) | 0x8; + __raw_writel(reg, IPU_SRM_PRI2); + return; + } + + di = g_dc_di_assignment[dc_chan]; + + /* Make sure other DC sync channel is not assigned same DI */ + reg = __raw_readl(DC_WR_CH_CONF(6 - dc_chan)); + if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) { + reg &= ~DC_WR_CH_CONF_PROG_DI_ID; + reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID; + __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan)); + } + + reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); + reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET; + __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); + + clk_enable(g_pixel_clk[di]); +} + +static unsigned char dc_swap; + +void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap) +{ + uint32_t reg; + uint32_t csc; + uint32_t dc_chan = 0; + int timeout = 50; + + dc_swap = swap; + + if (channel == MEM_DC_SYNC) { + dc_chan = 1; + } else if (channel == MEM_BG_SYNC) { + dc_chan = 5; + } else if (channel == MEM_FG_SYNC) { + /* Disable FG channel */ + dc_chan = 5; + + reg = __raw_readl(DP_COM_CONF()); + csc = reg & DP_COM_CONF_CSC_DEF_MASK; + if (csc == DP_COM_CONF_CSC_DEF_FG) + reg &= ~DP_COM_CONF_CSC_DEF_MASK; + + reg &= ~DP_COM_CONF_FG_EN; + __raw_writel(reg, DP_COM_CONF()); + + reg = __raw_readl(IPU_SRM_PRI2) | 0x8; + __raw_writel(reg, IPU_SRM_PRI2); + + timeout = 50; + + /* + * Wait for DC triple buffer to empty, + * this check is useful for tv overlay. + */ + if (g_dc_di_assignment[dc_chan] == 0) + while ((__raw_readl(DC_STAT) & 0x00000002) + != 0x00000002) { + udelay(2000); + timeout -= 2; + if (timeout <= 0) + break; + } + else if (g_dc_di_assignment[dc_chan] == 1) + while ((__raw_readl(DC_STAT) & 0x00000020) + != 0x00000020) { + udelay(2000); + timeout -= 2; + if (timeout <= 0) + break; + } + return; + } else { + return; + } + + if (dc_swap) { + /* Swap DC channel 1 and 5 settings, and disable old dc chan */ + reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); + __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan)); + reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK; + reg ^= DC_WR_CH_CONF_PROG_DI_ID; + __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); + } else { + timeout = 50; + + /* Wait for DC triple buffer to empty */ + if (g_dc_di_assignment[dc_chan] == 0) + while ((__raw_readl(DC_STAT) & 0x00000002) + != 0x00000002) { + udelay(2000); + timeout -= 2; + if (timeout <= 0) + break; + } + else if (g_dc_di_assignment[dc_chan] == 1) + while ((__raw_readl(DC_STAT) & 0x00000020) + != 0x00000020) { + udelay(2000); + timeout -= 2; + if (timeout <= 0) + break; + } + + reg = __raw_readl(DC_WR_CH_CONF(dc_chan)); + reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK; + __raw_writel(reg, DC_WR_CH_CONF(dc_chan)); + + reg = __raw_readl(IPU_DISP_GEN); + if (g_dc_di_assignment[dc_chan]) + reg &= ~DI1_COUNTER_RELEASE; + else + reg &= ~DI0_COUNTER_RELEASE; + __raw_writel(reg, IPU_DISP_GEN); + + /* Clock is already off because it must be done quickly, but + we need to fix the ref count */ + clk_disable(g_pixel_clk[g_dc_di_assignment[dc_chan]]); + } +} + +void ipu_init_dc_mappings(void) +{ + /* IPU_PIX_FMT_RGB24 */ + ipu_dc_map_clear(0); + ipu_dc_map_config(0, 0, 7, 0xFF); + ipu_dc_map_config(0, 1, 15, 0xFF); + ipu_dc_map_config(0, 2, 23, 0xFF); + + /* IPU_PIX_FMT_RGB666 */ + ipu_dc_map_clear(1); + ipu_dc_map_config(1, 0, 5, 0xFC); + ipu_dc_map_config(1, 1, 11, 0xFC); + ipu_dc_map_config(1, 2, 17, 0xFC); + + /* IPU_PIX_FMT_YUV444 */ + ipu_dc_map_clear(2); + ipu_dc_map_config(2, 0, 15, 0xFF); + ipu_dc_map_config(2, 1, 23, 0xFF); + ipu_dc_map_config(2, 2, 7, 0xFF); + + /* IPU_PIX_FMT_RGB565 */ + ipu_dc_map_clear(3); + ipu_dc_map_config(3, 0, 4, 0xF8); + ipu_dc_map_config(3, 1, 10, 0xFC); + ipu_dc_map_config(3, 2, 15, 0xF8); + + /* IPU_PIX_FMT_LVDS666 */ + ipu_dc_map_clear(4); + ipu_dc_map_config(4, 0, 5, 0xFC); + ipu_dc_map_config(4, 1, 13, 0xFC); + ipu_dc_map_config(4, 2, 21, 0xFC); +} + +int ipu_pixfmt_to_map(uint32_t fmt) +{ + switch (fmt) { + case IPU_PIX_FMT_GENERIC: + case IPU_PIX_FMT_RGB24: + return 0; + case IPU_PIX_FMT_RGB666: + return 1; + case IPU_PIX_FMT_YUV444: + return 2; + case IPU_PIX_FMT_RGB565: + return 3; + case IPU_PIX_FMT_LVDS666: + return 4; + } + + return -1; +} + +/* + * This function is called to adapt synchronous LCD panel to IPU restriction. + */ +void adapt_panel_to_ipu_restricitions(uint32_t *pixel_clk, + uint16_t width, uint16_t height, + uint16_t h_start_width, + uint16_t h_end_width, + uint16_t v_start_width, + uint16_t *v_end_width) +{ + if (*v_end_width < 2) { + uint16_t total_width = width + h_start_width + h_end_width; + uint16_t total_height_old = height + v_start_width + + (*v_end_width); + uint16_t total_height_new = height + v_start_width + 2; + *v_end_width = 2; + *pixel_clk = (*pixel_clk) * total_width * total_height_new / + (total_width * total_height_old); + printf("WARNING: adapt panel end blank lines\n"); + } +} + +/* + * This function is called to initialize a synchronous LCD panel. + * + * @param disp The DI the panel is attached to. + * + * @param pixel_clk Desired pixel clock frequency in Hz. + * + * @param pixel_fmt Input parameter for pixel format of buffer. + * Pixel format is a FOURCC ASCII code. + * + * @param width The width of panel in pixels. + * + * @param height The height of panel in pixels. + * + * @param hStartWidth The number of pixel clocks between the HSYNC + * signal pulse and the start of valid data. + * + * @param hSyncWidth The width of the HSYNC signal in units of pixel + * clocks. + * + * @param hEndWidth The number of pixel clocks between the end of + * valid data and the HSYNC signal for next line. + * + * @param vStartWidth The number of lines between the VSYNC + * signal pulse and the start of valid data. + * + * @param vSyncWidth The width of the VSYNC signal in units of lines + * + * @param vEndWidth The number of lines between the end of valid + * data and the VSYNC signal for next frame. + * + * @param sig Bitfield of signal polarities for LCD interface. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ + +int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, + uint16_t width, uint16_t height, + uint32_t pixel_fmt, + uint16_t h_start_width, uint16_t h_sync_width, + uint16_t h_end_width, uint16_t v_start_width, + uint16_t v_sync_width, uint16_t v_end_width, + uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig) +{ + uint32_t reg; + uint32_t di_gen, vsync_cnt; + uint32_t div, rounded_pixel_clk; + uint32_t h_total, v_total; + int map; + struct clk *di_parent; + + debug("panel size = %d x %d\n", width, height); + + if ((v_sync_width == 0) || (h_sync_width == 0)) + return -EINVAL; + + adapt_panel_to_ipu_restricitions(&pixel_clk, width, height, + h_start_width, h_end_width, + v_start_width, &v_end_width); + h_total = width + h_sync_width + h_start_width + h_end_width; + v_total = height + v_sync_width + v_start_width + v_end_width; + + /* Init clocking */ + debug("pixel clk = %d\n", pixel_clk); + + if (sig.ext_clk) { + if (!(g_di1_tvout && (disp == 1))) { /*not round div for tvout*/ + /* + * Set the PLL to be an even multiple + * of the pixel clock. + */ + if ((clk_get_usecount(g_pixel_clk[0]) == 0) && + (clk_get_usecount(g_pixel_clk[1]) == 0)) { + di_parent = clk_get_parent(g_di_clk[disp]); + rounded_pixel_clk = + clk_round_rate(g_pixel_clk[disp], + pixel_clk); + div = clk_get_rate(di_parent) / + rounded_pixel_clk; + if (div % 2) + div++; + if (clk_get_rate(di_parent) != div * + rounded_pixel_clk) + clk_set_rate(di_parent, + div * rounded_pixel_clk); + udelay(10000); + clk_set_rate(g_di_clk[disp], + 2 * rounded_pixel_clk); + udelay(10000); + } + } + clk_set_parent(g_pixel_clk[disp], g_ldb_clk); + } else { + if (clk_get_usecount(g_pixel_clk[disp]) != 0) + clk_set_parent(g_pixel_clk[disp], g_ipu_clk); + } + rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk); + clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk); + udelay(5000); + /* Get integer portion of divider */ + div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) / + rounded_pixel_clk; + + ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1); + ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2); + + map = ipu_pixfmt_to_map(pixel_fmt); + if (map < 0) { + debug("IPU_DISP: No MAP\n"); + return -EINVAL; + } + + di_gen = __raw_readl(DI_GENERAL(disp)); + + if (sig.interlaced) { + /* Setup internal HSYNC waveform */ + ipu_di_sync_config( + disp, /* display */ + 1, /* counter */ + h_total / 2 - 1,/* run count */ + DI_SYNC_CLK, /* run_resolution */ + 0, /* offset */ + DI_SYNC_NONE, /* offset resolution */ + 0, /* repeat count */ + DI_SYNC_NONE, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* Field 1 VSYNC waveform */ + ipu_di_sync_config( + disp, /* display */ + 2, /* counter */ + h_total - 1, /* run count */ + DI_SYNC_CLK, /* run_resolution */ + 0, /* offset */ + DI_SYNC_NONE, /* offset resolution */ + 0, /* repeat count */ + DI_SYNC_NONE, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 4 /* COUNT DOWN */ + ); + + /* Setup internal HSYNC waveform */ + ipu_di_sync_config( + disp, /* display */ + 3, /* counter */ + v_total * 2 - 1,/* run count */ + DI_SYNC_INT_HSYNC, /* run_resolution */ + 1, /* offset */ + DI_SYNC_INT_HSYNC, /* offset resolution */ + 0, /* repeat count */ + DI_SYNC_NONE, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 4 /* COUNT DOWN */ + ); + + /* Active Field ? */ + ipu_di_sync_config( + disp, /* display */ + 4, /* counter */ + v_total / 2 - 1,/* run count */ + DI_SYNC_HSYNC, /* run_resolution */ + v_start_width, /* offset */ + DI_SYNC_HSYNC, /* offset resolution */ + 2, /* repeat count */ + DI_SYNC_VSYNC, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* Active Line */ + ipu_di_sync_config( + disp, /* display */ + 5, /* counter */ + 0, /* run count */ + DI_SYNC_HSYNC, /* run_resolution */ + 0, /* offset */ + DI_SYNC_NONE, /* offset resolution */ + height / 2, /* repeat count */ + 4, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* Field 0 VSYNC waveform */ + ipu_di_sync_config( + disp, /* display */ + 6, /* counter */ + v_total - 1, /* run count */ + DI_SYNC_HSYNC, /* run_resolution */ + 0, /* offset */ + DI_SYNC_NONE, /* offset resolution */ + 0, /* repeat count */ + DI_SYNC_NONE, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* DC VSYNC waveform */ + vsync_cnt = 7; + ipu_di_sync_config( + disp, /* display */ + 7, /* counter */ + v_total / 2 - 1,/* run count */ + DI_SYNC_HSYNC, /* run_resolution */ + 9, /* offset */ + DI_SYNC_HSYNC, /* offset resolution */ + 2, /* repeat count */ + DI_SYNC_VSYNC, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + /* active pixel waveform */ + ipu_di_sync_config( + disp, /* display */ + 8, /* counter */ + 0, /* run count */ + DI_SYNC_CLK, /* run_resolution */ + h_start_width, /* offset */ + DI_SYNC_CLK, /* offset resolution */ + width, /* repeat count */ + 5, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 0 /* COUNT DOWN */ + ); + + ipu_di_sync_config( + disp, /* display */ + 9, /* counter */ + v_total - 1, /* run count */ + DI_SYNC_INT_HSYNC,/* run_resolution */ + v_total / 2, /* offset */ + DI_SYNC_INT_HSYNC,/* offset resolution */ + 0, /* repeat count */ + DI_SYNC_HSYNC, /* CNT_CLR_SEL */ + 0, /* CNT_POLARITY_GEN_EN */ + DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */ + DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */ + 0, /* COUNT UP */ + 4 /* COUNT DOWN */ + ); + + /* set gentime select and tag sel */ + reg = __raw_readl(DI_SW_GEN1(disp, 9)); + reg &= 0x1FFFFFFF; + reg |= (3 - 1)<<29 | 0x00008000; + __raw_writel(reg, DI_SW_GEN1(disp, 9)); + + __raw_writel(v_total / 2 - 1, DI_SCR_CONF(disp)); + + /* set y_sel = 1 */ + di_gen |= 0x10000000; + di_gen |= DI_GEN_POLARITY_5; + di_gen |= DI_GEN_POLARITY_8; + } else { + /* Setup internal HSYNC waveform */ + ipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK, + 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, + 0, DI_SYNC_NONE, + DI_SYNC_NONE, 0, 0); + + /* Setup external (delayed) HSYNC waveform */ + ipu_di_sync_config(disp, DI_SYNC_HSYNC, h_total - 1, + DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK, + 0, DI_SYNC_NONE, 1, DI_SYNC_NONE, + DI_SYNC_CLK, 0, h_sync_width * 2); + /* Setup VSYNC waveform */ + vsync_cnt = DI_SYNC_VSYNC; + ipu_di_sync_config(disp, DI_SYNC_VSYNC, v_total - 1, + DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0, + DI_SYNC_NONE, 1, DI_SYNC_NONE, + DI_SYNC_INT_HSYNC, 0, v_sync_width * 2); + __raw_writel(v_total - 1, DI_SCR_CONF(disp)); + + /* Setup active data waveform to sync with DC */ + ipu_di_sync_config(disp, 4, 0, DI_SYNC_HSYNC, + v_sync_width + v_start_width, DI_SYNC_HSYNC, + height, + DI_SYNC_VSYNC, 0, DI_SYNC_NONE, + DI_SYNC_NONE, 0, 0); + ipu_di_sync_config(disp, 5, 0, DI_SYNC_CLK, + h_sync_width + h_start_width, DI_SYNC_CLK, + width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, + 0); + + /* reset all unused counters */ + __raw_writel(0, DI_SW_GEN0(disp, 6)); + __raw_writel(0, DI_SW_GEN1(disp, 6)); + __raw_writel(0, DI_SW_GEN0(disp, 7)); + __raw_writel(0, DI_SW_GEN1(disp, 7)); + __raw_writel(0, DI_SW_GEN0(disp, 8)); + __raw_writel(0, DI_SW_GEN1(disp, 8)); + __raw_writel(0, DI_SW_GEN0(disp, 9)); + __raw_writel(0, DI_SW_GEN1(disp, 9)); + + reg = __raw_readl(DI_STP_REP(disp, 6)); + reg &= 0x0000FFFF; + __raw_writel(reg, DI_STP_REP(disp, 6)); + __raw_writel(0, DI_STP_REP(disp, 7)); + __raw_writel(0, DI_STP_REP(disp, 9)); + + /* Init template microcode */ + if (disp) { + ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5); + ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5); + ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5); + } else { + ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5); + ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5); + ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5); + } + + if (sig.Hsync_pol) + di_gen |= DI_GEN_POLARITY_2; + if (sig.Vsync_pol) + di_gen |= DI_GEN_POLARITY_3; + + if (!sig.clk_pol) + di_gen |= DI_GEN_POL_CLK; + + } + + __raw_writel(di_gen, DI_GENERAL(disp)); + + __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) | + 0x00000002, DI_SYNC_AS_GEN(disp)); + + reg = __raw_readl(DI_POL(disp)); + reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15); + if (sig.enable_pol) + reg |= DI_POL_DRDY_POLARITY_15; + if (sig.data_pol) + reg |= DI_POL_DRDY_DATA_POLARITY; + __raw_writel(reg, DI_POL(disp)); + + __raw_writel(width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp))); + + return 0; +} + +/* + * This function sets the foreground and background plane global alpha blending + * modes. This function also sets the DP graphic plane according to the + * parameter of IPUv3 DP channel. + * + * @param channel IPUv3 DP channel + * + * @param enable Boolean to enable or disable global alpha + * blending. If disabled, local blending is used. + * + * @param alpha Global alpha value. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable, + uint8_t alpha) +{ + uint32_t reg; + + unsigned char bg_chan; + + if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) || + (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) || + (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1))) + return -EINVAL; + + if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 || + channel == MEM_BG_ASYNC1) + bg_chan = 1; + else + bg_chan = 0; + + if (!g_ipu_clk_enabled) + clk_enable(g_ipu_clk); + + if (bg_chan) { + reg = __raw_readl(DP_COM_CONF()); + __raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF()); + } else { + reg = __raw_readl(DP_COM_CONF()); + __raw_writel(reg | DP_COM_CONF_GWSEL, DP_COM_CONF()); + } + + if (enable) { + reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0x00FFFFFFL; + __raw_writel(reg | ((uint32_t) alpha << 24), + DP_GRAPH_WIND_CTRL()); + + reg = __raw_readl(DP_COM_CONF()); + __raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF()); + } else { + reg = __raw_readl(DP_COM_CONF()); + __raw_writel(reg & ~DP_COM_CONF_GWAM, DP_COM_CONF()); + } + + reg = __raw_readl(IPU_SRM_PRI2) | 0x8; + __raw_writel(reg, IPU_SRM_PRI2); + + if (!g_ipu_clk_enabled) + clk_disable(g_ipu_clk); + + return 0; +} + +/* + * This function sets the transparent color key for SDC graphic plane. + * + * @param channel Input parameter for the logical channel ID. + * + * @param enable Boolean to enable or disable color key + * + * @param colorKey 24-bit RGB color for transparent color key. + * + * @return Returns 0 on success or negative error code on fail + */ +int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable, + uint32_t color_key) +{ + uint32_t reg; + int y, u, v; + int red, green, blue; + + if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) || + (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) || + (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1))) + return -EINVAL; + + if (!g_ipu_clk_enabled) + clk_enable(g_ipu_clk); + + color_key_4rgb = 1; + /* Transform color key from rgb to yuv if CSC is enabled */ + if (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) || + ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) || + ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) || + ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB))) { + + debug("color key 0x%x need change to yuv fmt\n", color_key); + + red = (color_key >> 16) & 0xFF; + green = (color_key >> 8) & 0xFF; + blue = color_key & 0xFF; + + y = rgb_to_yuv(0, red, green, blue); + u = rgb_to_yuv(1, red, green, blue); + v = rgb_to_yuv(2, red, green, blue); + color_key = (y << 16) | (u << 8) | v; + + color_key_4rgb = 0; + + debug("color key change to yuv fmt 0x%x\n", color_key); + } + + if (enable) { + reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L; + __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL()); + + reg = __raw_readl(DP_COM_CONF()); + __raw_writel(reg | DP_COM_CONF_GWCKE, DP_COM_CONF()); + } else { + reg = __raw_readl(DP_COM_CONF()); + __raw_writel(reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF()); + } + + reg = __raw_readl(IPU_SRM_PRI2) | 0x8; + __raw_writel(reg, IPU_SRM_PRI2); + + if (!g_ipu_clk_enabled) + clk_disable(g_ipu_clk); + + return 0; +} diff --git a/qemu/roms/u-boot/drivers/video/ipu_regs.h b/qemu/roms/u-boot/drivers/video/ipu_regs.h new file mode 100644 index 000000000..21e9c99e0 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/ipu_regs.h @@ -0,0 +1,412 @@ +/* + * Porting to u-boot: + * + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de + * + * Linux IPU driver for MX51: + * + * (C) Copyright 2005-2009 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IPU_REGS_INCLUDED__ +#define __IPU_REGS_INCLUDED__ + +#define IPU_DISP0_BASE 0x00000000 +#define IPU_MCU_T_DEFAULT 8 +#define IPU_DISP1_BASE (IPU_MCU_T_DEFAULT << 25) +#define IPU_CM_REG_BASE 0x00000000 +#define IPU_STAT_REG_BASE 0x00000200 +#define IPU_IDMAC_REG_BASE 0x00008000 +#define IPU_ISP_REG_BASE 0x00010000 +#define IPU_DP_REG_BASE 0x00018000 +#define IPU_IC_REG_BASE 0x00020000 +#define IPU_IRT_REG_BASE 0x00028000 +#define IPU_CSI0_REG_BASE 0x00030000 +#define IPU_CSI1_REG_BASE 0x00038000 +#define IPU_DI0_REG_BASE 0x00040000 +#define IPU_DI1_REG_BASE 0x00048000 +#define IPU_SMFC_REG_BASE 0x00050000 +#define IPU_DC_REG_BASE 0x00058000 +#define IPU_DMFC_REG_BASE 0x00060000 +#define IPU_VDI_REG_BASE 0x00680000 +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) +#define IPU_CPMEM_REG_BASE 0x01000000 +#define IPU_LUT_REG_BASE 0x01020000 +#define IPU_SRM_REG_BASE 0x01040000 +#define IPU_TPM_REG_BASE 0x01060000 +#define IPU_DC_TMPL_REG_BASE 0x01080000 +#define IPU_ISP_TBPR_REG_BASE 0x010C0000 +#elif defined(CONFIG_MX6) +#define IPU_CPMEM_REG_BASE 0x00100000 +#define IPU_LUT_REG_BASE 0x00120000 +#define IPU_SRM_REG_BASE 0x00140000 +#define IPU_TPM_REG_BASE 0x00160000 +#define IPU_DC_TMPL_REG_BASE 0x00180000 +#define IPU_ISP_TBPR_REG_BASE 0x001C0000 +#endif + +#define IPU_CTRL_BASE_ADDR (IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET) + +extern u32 *ipu_dc_tmpl_reg; + +#define DC_EVT_NF 0 +#define DC_EVT_NL 1 +#define DC_EVT_EOF 2 +#define DC_EVT_NFIELD 3 +#define DC_EVT_EOL 4 +#define DC_EVT_EOFIELD 5 +#define DC_EVT_NEW_ADDR 6 +#define DC_EVT_NEW_CHAN 7 +#define DC_EVT_NEW_DATA 8 + +#define DC_EVT_NEW_ADDR_W_0 0 +#define DC_EVT_NEW_ADDR_W_1 1 +#define DC_EVT_NEW_CHAN_W_0 2 +#define DC_EVT_NEW_CHAN_W_1 3 +#define DC_EVT_NEW_DATA_W_0 4 +#define DC_EVT_NEW_DATA_W_1 5 +#define DC_EVT_NEW_ADDR_R_0 6 +#define DC_EVT_NEW_ADDR_R_1 7 +#define DC_EVT_NEW_CHAN_R_0 8 +#define DC_EVT_NEW_CHAN_R_1 9 +#define DC_EVT_NEW_DATA_R_0 10 +#define DC_EVT_NEW_DATA_R_1 11 + +/* Software reset for ipu */ +#define SW_IPU_RST 8 + +enum { + IPU_CONF_DP_EN = 0x00000020, + IPU_CONF_DI0_EN = 0x00000040, + IPU_CONF_DI1_EN = 0x00000080, + IPU_CONF_DMFC_EN = 0x00000400, + IPU_CONF_DC_EN = 0x00000200, + + DI0_COUNTER_RELEASE = 0x01000000, + DI1_COUNTER_RELEASE = 0x02000000, + + DI_DW_GEN_ACCESS_SIZE_OFFSET = 24, + DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16, + + DI_GEN_DI_CLK_EXT = 0x100000, + DI_GEN_POLARITY_1 = 0x00000001, + DI_GEN_POLARITY_2 = 0x00000002, + DI_GEN_POLARITY_3 = 0x00000004, + DI_GEN_POLARITY_4 = 0x00000008, + DI_GEN_POLARITY_5 = 0x00000010, + DI_GEN_POLARITY_6 = 0x00000020, + DI_GEN_POLARITY_7 = 0x00000040, + DI_GEN_POLARITY_8 = 0x00000080, + DI_GEN_POL_CLK = 0x20000, + + DI_POL_DRDY_DATA_POLARITY = 0x00000080, + DI_POL_DRDY_POLARITY_15 = 0x00000010, + DI_VSYNC_SEL_OFFSET = 13, + + DC_WR_CH_CONF_FIELD_MODE = 0x00000200, + DC_WR_CH_CONF_PROG_TYPE_OFFSET = 5, + DC_WR_CH_CONF_PROG_TYPE_MASK = 0x000000E0, + DC_WR_CH_CONF_PROG_DI_ID = 0x00000004, + DC_WR_CH_CONF_PROG_DISP_ID_OFFSET = 3, + DC_WR_CH_CONF_PROG_DISP_ID_MASK = 0x00000018, + + DP_COM_CONF_FG_EN = 0x00000001, + DP_COM_CONF_GWSEL = 0x00000002, + DP_COM_CONF_GWAM = 0x00000004, + DP_COM_CONF_GWCKE = 0x00000008, + DP_COM_CONF_CSC_DEF_MASK = 0x00000300, + DP_COM_CONF_CSC_DEF_OFFSET = 8, + DP_COM_CONF_CSC_DEF_FG = 0x00000300, + DP_COM_CONF_CSC_DEF_BG = 0x00000200, + DP_COM_CONF_CSC_DEF_BOTH = 0x00000100, + DP_COM_CONF_GAMMA_EN = 0x00001000, + DP_COM_CONF_GAMMA_YUV_EN = 0x00002000, +}; + +enum di_pins { + DI_PIN11 = 0, + DI_PIN12 = 1, + DI_PIN13 = 2, + DI_PIN14 = 3, + DI_PIN15 = 4, + DI_PIN16 = 5, + DI_PIN17 = 6, + DI_PIN_CS = 7, + + DI_PIN_SER_CLK = 0, + DI_PIN_SER_RS = 1, +}; + +enum di_sync_wave { + DI_SYNC_NONE = -1, + DI_SYNC_CLK = 0, + DI_SYNC_INT_HSYNC = 1, + DI_SYNC_HSYNC = 2, + DI_SYNC_VSYNC = 3, + DI_SYNC_DE = 5, +}; + +struct ipu_cm { + u32 conf; + u32 sisg_ctrl0; + u32 sisg_ctrl1; + u32 sisg_set[6]; + u32 sisg_clear[6]; + u32 int_ctrl[15]; + u32 sdma_event[10]; + u32 srm_pri1; + u32 srm_pri2; + u32 fs_proc_flow[3]; + u32 fs_disp_flow[2]; + u32 skip; + u32 disp_alt_conf; + u32 disp_gen; + u32 disp_alt[4]; + u32 snoop; + u32 mem_rst; + u32 pm; + u32 gpr; + u32 reserved0[26]; + u32 ch_db_mode_sel[2]; + u32 reserved1[4]; + u32 alt_ch_db_mode_sel[2]; + u32 reserved2[2]; + u32 ch_trb_mode_sel[2]; +}; + +struct ipu_idmac { + u32 conf; + u32 ch_en[2]; + u32 sep_alpha; + u32 alt_sep_alpha; + u32 ch_pri[2]; + u32 wm_en[2]; + u32 lock_en[2]; + u32 sub_addr[5]; + u32 bndm_en[2]; + u32 sc_cord[2]; + u32 reserved[44]; + u32 ch_busy[2]; +}; + +struct ipu_com_async { + u32 com_conf_async; + u32 graph_wind_ctrl_async; + u32 fg_pos_async; + u32 cur_pos_async; + u32 cur_map_async; + u32 gamma_c_async[8]; + u32 gamma_s_async[4]; + u32 dp_csca_async[4]; + u32 dp_csc_async[2]; +}; + +struct ipu_dp { + u32 com_conf_sync; + u32 graph_wind_ctrl_sync; + u32 fg_pos_sync; + u32 cur_pos_sync; + u32 cur_map_sync; + u32 gamma_c_sync[8]; + u32 gamma_s_sync[4]; + u32 csca_sync[4]; + u32 csc_sync[2]; + u32 cur_pos_alt; + struct ipu_com_async async[2]; +}; + +struct ipu_di { + u32 general; + u32 bs_clkgen0; + u32 bs_clkgen1; + u32 sw_gen0[9]; + u32 sw_gen1[9]; + u32 sync_as; + u32 dw_gen[12]; + u32 dw_set[48]; + u32 stp_rep[4]; + u32 stp_rep9; + u32 ser_conf; + u32 ssc; + u32 pol; + u32 aw0; + u32 aw1; + u32 scr_conf; + u32 stat; +}; + +struct ipu_stat { + u32 int_stat[15]; + u32 cur_buf[2]; + u32 alt_cur_buf_0; + u32 alt_cur_buf_1; + u32 srm_stat; + u32 proc_task_stat; + u32 disp_task_stat; + u32 triple_cur_buf[4]; + u32 ch_buf0_rdy[2]; + u32 ch_buf1_rdy[2]; + u32 alt_ch_buf0_rdy[2]; + u32 alt_ch_buf1_rdy[2]; + u32 ch_buf2_rdy[2]; +}; + +struct ipu_dc_ch { + u32 wr_ch_conf; + u32 wr_ch_addr; + u32 rl[5]; +}; + +struct ipu_dc { + struct ipu_dc_ch dc_ch0_1_2[3]; + u32 cmd_ch_conf_3; + u32 cmd_ch_conf_4; + struct ipu_dc_ch dc_ch5_6[2]; + struct ipu_dc_ch dc_ch8; + u32 rl6_ch_8; + struct ipu_dc_ch dc_ch9; + u32 rl6_ch_9; + u32 gen; + u32 disp_conf1[4]; + u32 disp_conf2[4]; + u32 di0_conf[2]; + u32 di1_conf[2]; + u32 dc_map_ptr[15]; + u32 dc_map_val[12]; + u32 udge[16]; + u32 lla[2]; + u32 r_lla[2]; + u32 wr_ch_addr_5_alt; + u32 stat; +}; + +struct ipu_dmfc { + u32 rd_chan; + u32 wr_chan; + u32 wr_chan_def; + u32 dp_chan; + u32 dp_chan_def; + u32 general[2]; + u32 ic_ctrl; + u32 wr_chan_alt; + u32 wr_chan_def_alt; + u32 general1_alt; + u32 stat; +}; + +#define IPU_CM_REG ((struct ipu_cm *)(IPU_CTRL_BASE_ADDR + \ + IPU_CM_REG_BASE)) +#define IPU_CONF (&IPU_CM_REG->conf) +#define IPU_SRM_PRI1 (&IPU_CM_REG->srm_pri1) +#define IPU_SRM_PRI2 (&IPU_CM_REG->srm_pri2) +#define IPU_FS_PROC_FLOW1 (&IPU_CM_REG->fs_proc_flow[0]) +#define IPU_FS_PROC_FLOW2 (&IPU_CM_REG->fs_proc_flow[1]) +#define IPU_FS_PROC_FLOW3 (&IPU_CM_REG->fs_proc_flow[2]) +#define IPU_FS_DISP_FLOW1 (&IPU_CM_REG->fs_disp_flow[0]) +#define IPU_DISP_GEN (&IPU_CM_REG->disp_gen) +#define IPU_MEM_RST (&IPU_CM_REG->mem_rst) +#define IPU_GPR (&IPU_CM_REG->gpr) +#define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[ch / 32]) + +#define IPU_STAT ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \ + IPU_STAT_REG_BASE)) +#define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[ch / 32]) +#define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[ch / 32]) +#define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[ch / 32]) + +#define IPU_INT_CTRL(n) (&IPU_CM_REG->int_ctrl[(n) - 1]) + +#define IDMAC_REG ((struct ipu_idmac *)(IPU_CTRL_BASE_ADDR + \ + IPU_IDMAC_REG_BASE)) +#define IDMAC_CONF (&IDMAC_REG->conf) +#define IDMAC_CHA_EN(ch) (&IDMAC_REG->ch_en[ch / 32]) +#define IDMAC_CHA_PRI(ch) (&IDMAC_REG->ch_pri[ch / 32]) + +#define DI_REG(di) ((struct ipu_di *)(IPU_CTRL_BASE_ADDR + \ + ((di == 1) ? IPU_DI1_REG_BASE : \ + IPU_DI0_REG_BASE))) +#define DI_GENERAL(di) (&DI_REG(di)->general) +#define DI_BS_CLKGEN0(di) (&DI_REG(di)->bs_clkgen0) +#define DI_BS_CLKGEN1(di) (&DI_REG(di)->bs_clkgen1) + +#define DI_SW_GEN0(di, gen) (&DI_REG(di)->sw_gen0[gen - 1]) +#define DI_SW_GEN1(di, gen) (&DI_REG(di)->sw_gen1[gen - 1]) +#define DI_STP_REP(di, gen) (&DI_REG(di)->stp_rep[(gen - 1) / 2]) +#define DI_SYNC_AS_GEN(di) (&DI_REG(di)->sync_as) +#define DI_DW_GEN(di, gen) (&DI_REG(di)->dw_gen[gen]) +#define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[gen + 12 * set]) +#define DI_POL(di) (&DI_REG(di)->pol) +#define DI_SCR_CONF(di) (&DI_REG(di)->scr_conf) + +#define DMFC_REG ((struct ipu_dmfc *)(IPU_CTRL_BASE_ADDR + \ + IPU_DMFC_REG_BASE)) +#define DMFC_WR_CHAN (&DMFC_REG->wr_chan) +#define DMFC_WR_CHAN_DEF (&DMFC_REG->wr_chan_def) +#define DMFC_DP_CHAN (&DMFC_REG->dp_chan) +#define DMFC_DP_CHAN_DEF (&DMFC_REG->dp_chan_def) +#define DMFC_GENERAL1 (&DMFC_REG->general[0]) +#define DMFC_IC_CTRL (&DMFC_REG->ic_ctrl) + + +#define DC_REG ((struct ipu_dc *)(IPU_CTRL_BASE_ADDR + \ + IPU_DC_REG_BASE)) +#define DC_MAP_CONF_PTR(n) (&DC_REG->dc_map_ptr[n / 2]) +#define DC_MAP_CONF_VAL(n) (&DC_REG->dc_map_val[n / 2]) + + +static inline struct ipu_dc_ch *dc_ch_offset(int ch) +{ + switch (ch) { + case 0: + case 1: + case 2: + return &DC_REG->dc_ch0_1_2[ch]; + case 5: + case 6: + return &DC_REG->dc_ch5_6[ch - 5]; + case 8: + return &DC_REG->dc_ch8; + case 9: + return &DC_REG->dc_ch9; + default: + printf("%s: invalid channel %d\n", __func__, ch); + return NULL; + } + +} + +#define DC_RL_CH(ch, evt) (&dc_ch_offset(ch)->rl[evt / 2]) + +#define DC_WR_CH_CONF(ch) (&dc_ch_offset(ch)->wr_ch_conf) +#define DC_WR_CH_ADDR(ch) (&dc_ch_offset(ch)->wr_ch_addr) + +#define DC_WR_CH_CONF_1 DC_WR_CH_CONF(1) +#define DC_WR_CH_CONF_5 DC_WR_CH_CONF(5) + +#define DC_GEN (&DC_REG->gen) +#define DC_DISP_CONF2(disp) (&DC_REG->disp_conf2[disp]) +#define DC_STAT (&DC_REG->stat) + +#define DP_SYNC 0 +#define DP_ASYNC0 0x60 +#define DP_ASYNC1 0xBC + +#define DP_REG ((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + \ + IPU_DP_REG_BASE)) +#define DP_COM_CONF() (&DP_REG->com_conf_sync) +#define DP_GRAPH_WIND_CTRL() (&DP_REG->graph_wind_ctrl_sync) +#define DP_CSC_A_0() (&DP_REG->csca_sync[0]) +#define DP_CSC_A_1() (&DP_REG->csca_sync[1]) +#define DP_CSC_A_2() (&DP_REG->csca_sync[2]) +#define DP_CSC_A_3() (&DP_REG->csca_sync[3]) + +#define DP_CSC_0() (&DP_REG->csc_sync[0]) +#define DP_CSC_1() (&DP_REG->csc_sync[1]) + +/* DC template opcodes */ +#define WROD(lf) (0x18 | (lf << 1)) + +#endif diff --git a/qemu/roms/u-boot/drivers/video/l5f31188.c b/qemu/roms/u-boot/drivers/video/l5f31188.c new file mode 100644 index 000000000..3312dcfb3 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/l5f31188.c @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2013 Samsung Electronics Co., Ltd. All rights reserved. + * Hyungwon Hwang <human.hwang@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/mipi_dsim.h> + +#define SCAN_FROM_LEFT_TO_RIGHT 0 +#define SCAN_FROM_RIGHT_TO_LEFT 1 +#define SCAN_FROM_TOP_TO_BOTTOM 0 +#define SCAN_FROM_BOTTOM_TO_TOP 1 + +static void l5f31188_sleep_in(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x10, 0x00); +} + +static void l5f31188_sleep_out(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x11, 0x00); +} + +static void l5f31188_set_gamma(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x26, 0x00); +} + +static void l5f31188_display_off(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x28, 0x00); +} + +static void l5f31188_display_on(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x29, 0x00); +} + +static void l5f31188_ctl_memory_access(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops, + int h_direction, int v_direction) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x36, + (((h_direction & 0x1) << 1) | (v_direction & 0x1))); +} + +static void l5f31188_set_pixel_format(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x3A, 0x70); +} + +static void l5f31188_write_disbv(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops, unsigned int brightness) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x51, brightness); +} + +static void l5f31188_write_ctrld(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x53, 0x2C); +} + +static void l5f31188_write_cabc(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops, + unsigned int wm_mode) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x55, wm_mode); +} + +static void l5f31188_write_cabcmb(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops, unsigned int min_brightness) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x5E, + min_brightness); +} + +static void l5f31188_set_extension(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + const unsigned char data_to_send[] = { + 0xB9, 0xFF, 0x83, 0x94 + }; + + ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE, + (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void l5f31188_set_dgc_lut(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + const unsigned char data_to_send[] = { + 0xC1, 0x01, 0x00, 0x04, 0x0E, 0x18, 0x1E, 0x26, + 0x2F, 0x36, 0x3E, 0x47, 0x4E, 0x56, 0x5D, 0x65, + 0x6D, 0x75, 0x7D, 0x84, 0x8C, 0x94, 0x9C, 0xA4, + 0xAD, 0xB5, 0xBD, 0xC5, 0xCC, 0xD4, 0xDE, 0xE5, + 0xEE, 0xF7, 0xFF, 0x3F, 0x9A, 0xCE, 0xD4, 0x21, + 0xA1, 0x26, 0x54, 0x00, 0x00, 0x04, 0x0E, 0x19, + 0x1F, 0x27, 0x30, 0x37, 0x40, 0x48, 0x50, 0x58, + 0x60, 0x67, 0x6F, 0x77, 0x7F, 0x87, 0x8F, 0x97, + 0x9F, 0xA7, 0xB0, 0xB8, 0xC0, 0xC8, 0xCE, 0xD8, + 0xE0, 0xE7, 0xF0, 0xF7, 0xFF, 0x3C, 0xEB, 0xFD, + 0x2F, 0x66, 0xA8, 0x2C, 0x46, 0x00, 0x00, 0x04, + 0x0E, 0x18, 0x1E, 0x26, 0x30, 0x38, 0x41, 0x4A, + 0x52, 0x5A, 0x62, 0x6B, 0x73, 0x7B, 0x83, 0x8C, + 0x94, 0x9C, 0xA5, 0xAD, 0xB6, 0xBD, 0xC5, 0xCC, + 0xD4, 0xDD, 0xE3, 0xEB, 0xF2, 0xF9, 0xFF, 0x3F, + 0xA4, 0x8A, 0x8F, 0xC7, 0x33, 0xF5, 0xE9, 0x00 + }; + ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE, + (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void l5f31188_set_tcon(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + const unsigned char data_to_send[] = { + 0xC7, 0x00, 0x20 + }; + ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE, + (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void l5f31188_set_ptba(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + const unsigned char data_to_send[] = { + 0xBF, 0x06, 0x10 + }; + ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE, + (unsigned int)data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void l5f31188_set_eco(struct mipi_dsim_device *dev, + struct mipi_dsim_master_ops *ops) +{ + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xC6, 0x0C); +} + +static int l5f31188_panel_init(struct mipi_dsim_device *dev) +{ + struct mipi_dsim_master_ops *ops = dev->master_ops; + + l5f31188_set_extension(dev, ops); + l5f31188_set_dgc_lut(dev, ops); + + l5f31188_set_eco(dev, ops); + l5f31188_set_tcon(dev, ops); + l5f31188_set_ptba(dev, ops); + l5f31188_set_gamma(dev, ops); + l5f31188_ctl_memory_access(dev, ops, + SCAN_FROM_LEFT_TO_RIGHT, SCAN_FROM_TOP_TO_BOTTOM); + l5f31188_set_pixel_format(dev, ops); + l5f31188_write_disbv(dev, ops, 0xFF); + l5f31188_write_ctrld(dev, ops); + l5f31188_write_cabc(dev, ops, 0x0); + l5f31188_write_cabcmb(dev, ops, 0x0); + + l5f31188_sleep_out(dev, ops); + + /* 120 msec */ + udelay(120 * 1000); + + return 0; +} + +static void l5f31188_display_enable(struct mipi_dsim_device *dev) +{ + struct mipi_dsim_master_ops *ops = dev->master_ops; + l5f31188_display_on(dev, ops); +} + +static struct mipi_dsim_lcd_driver l5f31188_dsim_ddi_driver = { + .name = "l5f31188", + .id = -1, + + .mipi_panel_init = l5f31188_panel_init, + .mipi_display_on = l5f31188_display_enable, +}; + +void l5f31188_init(void) +{ + exynos_mipi_dsi_register_lcd_driver(&l5f31188_dsim_ddi_driver); +} diff --git a/qemu/roms/u-boot/drivers/video/ld9040.c b/qemu/roms/u-boot/drivers/video/ld9040.c new file mode 100644 index 000000000..23fe783c8 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/ld9040.c @@ -0,0 +1,128 @@ +/* + * ld9040 AMOLED LCD panel driver. + * + * Copyright (C) 2012 Samsung Electronics + * Donghwa Lee <dh09.lee@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spi.h> + +static const unsigned char SEQ_SWRESET[] = { + 0x01, +}; + +static const unsigned char SEQ_USER_SETTING[] = { + 0xF0, 0x5A, 0x5A +}; + +static const unsigned char SEQ_ELVSS_ON[] = { + 0xB1, 0x0D, 0x00, 0x16, +}; + +static const unsigned char SEQ_TEMP_SWIRE[] = { + 0xB2, 0x06, 0x06, 0x06, 0x06, +}; + +static const unsigned char SEQ_GTCON[] = { + 0xF7, 0x09, 0x00, 0x00, +}; + +static const unsigned char SEQ_PANEL_CONDITION[] = { + 0xF8, 0x05, 0x65, 0x96, 0x71, 0x7D, 0x19, 0x3B, + 0x0D, 0x19, 0x7E, 0x0D, 0xE2, 0x00, 0x00, 0x7E, + 0x7D, 0x07, 0x07, 0x20, 0x20, 0x20, 0x02, 0x02, +}; + +static const unsigned char SEQ_GAMMA_SET1[] = { + 0xF9, 0x00, 0xA7, 0xB4, 0xAE, 0xBF, 0x00, 0x91, + 0x00, 0xB2, 0xB4, 0xAA, 0xBB, 0x00, 0xAC, 0x00, + 0xB3, 0xB1, 0xAA, 0xBC, 0x00, 0xB3, +}; + +static const unsigned char SEQ_GAMMA_CTRL[] = { + 0xFB, 0x02, 0x5A, +}; + +static const unsigned char SEQ_APON[] = { + 0xF3, 0x00, 0x00, 0x00, 0x0A, 0x02, +}; + +static const unsigned char SEQ_DISPCTL[] = { + 0xF2, 0x02, 0x08, 0x08, 0x10, 0x10, +}; + +static const unsigned char SEQ_MANPWR[] = { + 0xB0, 0x04, +}; + +static const unsigned char SEQ_PWR_CTRL[] = { + 0xF4, 0x0A, 0x87, 0x25, 0x6A, 0x44, 0x02, 0x88, +}; + +static const unsigned char SEQ_SLPOUT[] = { + 0x11, +}; + +static const unsigned char SEQ_SLPIN[] = { + 0x10, +}; + +static const unsigned char SEQ_DISPON[] = { + 0x29, +}; + +static const unsigned char SEQ_DISPOFF[] = { + 0x28, +}; + +static void ld9040_spi_write(const unsigned char *wbuf, unsigned int size_cmd) +{ + int i = 0; + + /* + * Data are transmitted in 9-bit words: + * the first bit is command/parameter, the other are the value. + * The value's LSB is shifted to MSB position, to be sent as 9th bit + */ + + unsigned int data_out = 0, data_in = 0; + for (i = 0; i < size_cmd; i++) { + data_out = wbuf[i] >> 1; + if (i != 0) + data_out += 0x0080; + if (wbuf[i] & 0x01) + data_out += 0x8000; + spi_xfer(NULL, 9, &data_out, &data_in, SPI_XFER_BEGIN); + } +} + +void ld9040_cfg_ldo(void) +{ + udelay(10); + + ld9040_spi_write(SEQ_USER_SETTING, + ARRAY_SIZE(SEQ_USER_SETTING)); + ld9040_spi_write(SEQ_PANEL_CONDITION, + ARRAY_SIZE(SEQ_PANEL_CONDITION)); + ld9040_spi_write(SEQ_DISPCTL, ARRAY_SIZE(SEQ_DISPCTL)); + ld9040_spi_write(SEQ_MANPWR, ARRAY_SIZE(SEQ_MANPWR)); + ld9040_spi_write(SEQ_PWR_CTRL, ARRAY_SIZE(SEQ_PWR_CTRL)); + ld9040_spi_write(SEQ_ELVSS_ON, ARRAY_SIZE(SEQ_ELVSS_ON)); + ld9040_spi_write(SEQ_GTCON, ARRAY_SIZE(SEQ_GTCON)); + ld9040_spi_write(SEQ_GAMMA_SET1, ARRAY_SIZE(SEQ_GAMMA_SET1)); + ld9040_spi_write(SEQ_GAMMA_CTRL, ARRAY_SIZE(SEQ_GAMMA_CTRL)); + ld9040_spi_write(SEQ_SLPOUT, ARRAY_SIZE(SEQ_SLPOUT)); + + udelay(120); +} + +void ld9040_enable_ldo(unsigned int onoff) +{ + if (onoff) + ld9040_spi_write(SEQ_DISPON, ARRAY_SIZE(SEQ_DISPON)); + else + ld9040_spi_write(SEQ_DISPOFF, ARRAY_SIZE(SEQ_DISPOFF)); +} diff --git a/qemu/roms/u-boot/drivers/video/mb862xx.c b/qemu/roms/u-boot/drivers/video/mb862xx.c new file mode 100644 index 000000000..1c74e97c5 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/mb862xx.c @@ -0,0 +1,484 @@ +/* + * (C) Copyright 2007 + * DENX Software Engineering, Anatolij Gustschin, agust@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * mb862xx.c - Graphic interface for Fujitsu CoralP/Lime + * PCI and video mode code was derived from smiLynxEM driver. + */ + +#include <common.h> + +#include <asm/io.h> +#include <pci.h> +#include <video_fb.h> +#include "videomodes.h" +#include <mb862xx.h> + +#if defined(CONFIG_POST) +#include <post.h> +#endif + +/* + * Graphic Device + */ +GraphicDevice mb862xx; + +/* + * 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ; + */ +#define VIDEO_MEM_SIZE 0x01FC0000 + +#if defined(CONFIG_PCI) +#if defined(CONFIG_VIDEO_CORALP) + +static struct pci_device_id supported[] = { + { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P }, + { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA }, + { } +}; + +/* Internal clock frequency divider table, index is mode number */ +unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 }; +#endif +#endif + +#if defined(CONFIG_VIDEO_CORALP) +#define rd_io in32r +#define wr_io out32r +#else +#define rd_io(addr) in_be32((volatile unsigned *)(addr)) +#define wr_io(addr, val) out_be32((volatile unsigned *)(addr), (val)) +#endif + +#define HOST_RD_REG(off) rd_io((dev->frameAdrs + GC_HOST_BASE + (off))) +#define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \ + (val)) +#define DISP_RD_REG(off) rd_io((dev->frameAdrs + GC_DISP_BASE + (off))) +#define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \ + (val)) +#define DE_RD_REG(off) rd_io((dev->dprBase + (off))) +#define DE_WR_REG(off, val) wr_io((dev->dprBase + (off)), (val)) + +#if defined(CONFIG_VIDEO_CORALP) +#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_GEO_FIFO)), (val)) +#else +#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_FIFO)), (val)) +#endif + +#define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + \ + (GC_DISP_BASE | GC_L0PAL0) + \ + ((idx) << 2)), (val)) + +#if defined(CONFIG_VIDEO_MB862xx_ACCEL) +static void gdc_sw_reset (void) +{ + GraphicDevice *dev = &mb862xx; + + HOST_WR_REG (GC_SRST, 0x1); + udelay (500); + video_hw_init (); +} + + +static void de_wait (void) +{ + GraphicDevice *dev = &mb862xx; + int lc = 0x10000; + + /* + * Sync with software writes to framebuffer, + * try to reset if engine locked + */ + while (DE_RD_REG (GC_CTR) & 0x00000131) + if (lc-- < 0) { + gdc_sw_reset (); + puts ("gdc reset done after drawing engine lock.\n"); + break; + } +} + +static void de_wait_slots (int slots) +{ + GraphicDevice *dev = &mb862xx; + int lc = 0x10000; + + /* Wait for free fifo slots */ + while (DE_RD_REG (GC_IFCNT) < slots) + if (lc-- < 0) { + gdc_sw_reset (); + puts ("gdc reset done after drawing engine lock.\n"); + break; + } +} +#endif + +#if !defined(CONFIG_VIDEO_CORALP) +static void board_disp_init (void) +{ + GraphicDevice *dev = &mb862xx; + const gdc_regs *regs = board_get_regs (); + + while (regs->index) { + DISP_WR_REG (regs->index, regs->value); + regs++; + } +} +#endif + +/* + * Init drawing engine if accel enabled. + * Also clears visible framebuffer. + */ +static void de_init (void) +{ + GraphicDevice *dev = &mb862xx; +#if defined(CONFIG_VIDEO_MB862xx_ACCEL) + int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000; + + dev->dprBase = dev->frameAdrs + GC_DRAW_BASE; + + /* Setup mode and fbbase, xres, fg, bg */ + de_wait_slots (2); + DE_WR_FIFO (0xf1010108); + DE_WR_FIFO (cf | 0x0300); + DE_WR_REG (GC_FBR, 0x0); + DE_WR_REG (GC_XRES, dev->winSizeX); + DE_WR_REG (GC_FC, 0x0); + DE_WR_REG (GC_BC, 0x0); + /* Reset clipping */ + DE_WR_REG (GC_CXMIN, 0x0); + DE_WR_REG (GC_CXMAX, dev->winSizeX); + DE_WR_REG (GC_CYMIN, 0x0); + DE_WR_REG (GC_CYMAX, dev->winSizeY); + + /* Clear framebuffer using drawing engine */ + de_wait_slots (3); + DE_WR_FIFO (0x09410000); + DE_WR_FIFO (0x00000000); + DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX); + /* sync with SW access to framebuffer */ + de_wait (); +#else + unsigned int i, *p; + + i = dev->winSizeX * dev->winSizeY; + p = (unsigned int *)dev->frameAdrs; + while (i--) + *p++ = 0; +#endif +} + +#if defined(CONFIG_VIDEO_CORALP) +/* use CCF and MMR parameters for Coral-P Eval. Board as default */ +#ifndef CONFIG_SYS_MB862xx_CCF +#define CONFIG_SYS_MB862xx_CCF 0x00090000 +#endif +#ifndef CONFIG_SYS_MB862xx_MMR +#define CONFIG_SYS_MB862xx_MMR 0x11d7fa13 +#endif + +unsigned int pci_video_init (void) +{ + GraphicDevice *dev = &mb862xx; + pci_dev_t devbusfn; + u16 device; + + if ((devbusfn = pci_find_devices (supported, 0)) < 0) { + puts("controller not present\n"); + return 0; + } + + /* PCI setup */ + pci_write_config_dword (devbusfn, PCI_COMMAND, + (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &dev->frameAdrs); + dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs); + + if (dev->frameAdrs == 0) { + puts ("PCI config: failed to get base address\n"); + return 0; + } + + dev->pciBase = dev->frameAdrs; + + puts("Coral-"); + + pci_read_config_word(devbusfn, PCI_DEVICE_ID, &device); + switch (device) { + case PCI_DEVICE_ID_CORAL_P: + puts("P\n"); + break; + case PCI_DEVICE_ID_CORAL_PA: + puts("PA\n"); + break; + default: + puts("Unknown\n"); + return 0; + } + + /* Setup clocks and memory mode for Coral-P(A) */ + HOST_WR_REG(GC_CCF, CONFIG_SYS_MB862xx_CCF); + udelay (200); + HOST_WR_REG(GC_MMR, CONFIG_SYS_MB862xx_MMR); + udelay (100); + return dev->frameAdrs; +} + +unsigned int card_init (void) +{ + GraphicDevice *dev = &mb862xx; + unsigned int cf, videomode, div = 0; + unsigned long t1, hsync, vsync; + char *penv; + int tmp, i, bpp; + struct ctfb_res_modes *res_mode; + struct ctfb_res_modes var_mode; + + memset (dev, 0, sizeof (GraphicDevice)); + + if (!pci_video_init ()) + return 0; + + tmp = 0; + videomode = 0x310; + /* get video mode via environment */ + if ((penv = getenv ("videomode")) != NULL) { + /* decide if it is a string */ + if (penv[0] <= '9') { + videomode = (int) simple_strtoul (penv, NULL, 16); + tmp = 1; + } + } else { + tmp = 1; + } + + if (tmp) { + /* parameter are vesa modes, search params */ + for (i = 0; i < VESA_MODES_COUNT; i++) { + if (vesa_modes[i].vesanr == videomode) + break; + } + if (i == VESA_MODES_COUNT) { + printf ("\tno VESA Mode found, fallback to mode 0x%x\n", + videomode); + i = 0; + } + res_mode = (struct ctfb_res_modes *) + &res_mode_init[vesa_modes[i].resindex]; + if (vesa_modes[i].resindex > 2) { + puts ("\tUnsupported resolution, using default\n"); + bpp = vesa_modes[1].bits_per_pixel; + div = fr_div[1]; + } + bpp = vesa_modes[i].bits_per_pixel; + div = fr_div[vesa_modes[i].resindex]; + } else { + res_mode = (struct ctfb_res_modes *) &var_mode; + bpp = video_get_params (res_mode, penv); + } + + /* calculate hsync and vsync freq (info only) */ + t1 = (res_mode->left_margin + res_mode->xres + + res_mode->right_margin + res_mode->hsync_len) / 8; + t1 *= 8; + t1 *= res_mode->pixclock; + t1 /= 1000; + hsync = 1000000000L / t1; + t1 *= (res_mode->upper_margin + res_mode->yres + + res_mode->lower_margin + res_mode->vsync_len); + t1 /= 1000; + vsync = 1000000000L / t1; + + /* fill in Graphic device struct */ + sprintf (dev->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, + res_mode->yres, bpp, (hsync / 1000), (vsync / 1000)); + printf ("\t%s\n", dev->modeIdent); + dev->winSizeX = res_mode->xres; + dev->winSizeY = res_mode->yres; + dev->memSize = VIDEO_MEM_SIZE; + + switch (bpp) { + case 8: + dev->gdfIndex = GDF__8BIT_INDEX; + dev->gdfBytesPP = 1; + break; + case 15: + case 16: + dev->gdfIndex = GDF_15BIT_555RGB; + dev->gdfBytesPP = 2; + break; + default: + printf ("\t%d bpp configured, but only 8,15 and 16 supported\n", + bpp); + puts ("\tfallback to 15bpp\n"); + dev->gdfIndex = GDF_15BIT_555RGB; + dev->gdfBytesPP = 2; + } + + /* Setup dot clock (internal pll, division rate) */ + DISP_WR_REG (GC_DCM1, div); + /* L0 init */ + cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000; + DISP_WR_REG (GC_L0M, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 | + (dev->winSizeY - 1) | cf); + DISP_WR_REG (GC_L0OA0, 0x0); + DISP_WR_REG (GC_L0DA0, 0x0); + DISP_WR_REG (GC_L0DY_L0DX, 0x0); + DISP_WR_REG (GC_L0EM, 0x0); + DISP_WR_REG (GC_L0WY_L0WX, 0x0); + DISP_WR_REG (GC_L0WH_L0WW, (dev->winSizeY - 1) << 16 | dev->winSizeX); + + /* Display timing init */ + DISP_WR_REG (GC_HTP_A, (dev->winSizeX + + res_mode->left_margin + + res_mode->right_margin + + res_mode->hsync_len - 1) << 16); + DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 | + (dev->winSizeX - 1)); + DISP_WR_REG (GC_VSW_HSW_HSP_A, (res_mode->vsync_len - 1) << 24 | + (res_mode->hsync_len - 1) << 16 | + (dev->winSizeX + + res_mode->right_margin - 1)); + DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin + + res_mode->upper_margin + + res_mode->vsync_len - 1) << 16); + DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 | + (dev->winSizeY + + res_mode->lower_margin - 1)); + DISP_WR_REG (GC_WY_WX, 0x0); + DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 | dev->winSizeX); + /* Display enable, L0 layer */ + DISP_WR_REG (GC_DCM1, 0x80010000 | div); + + return dev->frameAdrs; +} +#endif + + +#if !defined(CONFIG_VIDEO_CORALP) +int mb862xx_probe(unsigned int addr) +{ + GraphicDevice *dev = &mb862xx; + unsigned int reg; + + dev->frameAdrs = addr; + dev->dprBase = dev->frameAdrs + GC_DRAW_BASE; + + /* Try to access GDC ID/Revision registers */ + reg = HOST_RD_REG (GC_CID); + reg = HOST_RD_REG (GC_CID); + if (reg == 0x303) { + reg = DE_RD_REG(GC_REV); + reg = DE_RD_REG(GC_REV); + if ((reg & ~0xff) == 0x20050100) + return MB862XX_TYPE_LIME; + } + + return 0; +} +#endif + +void *video_hw_init (void) +{ + GraphicDevice *dev = &mb862xx; + + puts ("Video: Fujitsu "); + + memset (dev, 0, sizeof (GraphicDevice)); + +#if defined(CONFIG_VIDEO_CORALP) + if (card_init () == 0) + return NULL; +#else + /* + * Preliminary init of the onboard graphic controller, + * retrieve base address + */ + if ((dev->frameAdrs = board_video_init ()) == 0) { + puts ("Controller not found!\n"); + return NULL; + } else { + puts ("Lime\n"); + + /* Set Change of Clock Frequency Register */ + HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF); + /* Delay required */ + udelay(300); + /* Set Memory I/F Mode Register) */ + HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR); + } +#endif + + de_init (); + +#if !defined(CONFIG_VIDEO_CORALP) + board_disp_init (); +#endif + +#if (defined(CONFIG_LWMON5) || \ + defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON) + /* Lamp on */ + board_backlight_switch (1); +#endif + + return dev; +} + +/* + * Set a RGB color in the LUT + */ +void video_set_lut (unsigned int index, unsigned char r, + unsigned char g, unsigned char b) +{ + GraphicDevice *dev = &mb862xx; + + L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b)); +} + +#if defined(CONFIG_VIDEO_MB862xx_ACCEL) +/* + * Drawing engine Fill and BitBlt screen region + */ +void video_hw_rectfill (unsigned int bpp, unsigned int dst_x, + unsigned int dst_y, unsigned int dim_x, + unsigned int dim_y, unsigned int color) +{ + GraphicDevice *dev = &mb862xx; + + de_wait_slots (3); + DE_WR_REG (GC_FC, color); + DE_WR_FIFO (0x09410000); + DE_WR_FIFO ((dst_y << 16) | dst_x); + DE_WR_FIFO ((dim_y << 16) | dim_x); + de_wait (); +} + +void video_hw_bitblt (unsigned int bpp, unsigned int src_x, + unsigned int src_y, unsigned int dst_x, + unsigned int dst_y, unsigned int width, + unsigned int height) +{ + GraphicDevice *dev = &mb862xx; + unsigned int ctrl = 0x0d000000L; + + if (src_x >= dst_x && src_y >= dst_y) + ctrl |= 0x00440000L; + else if (src_x >= dst_x && src_y <= dst_y) + ctrl |= 0x00460000L; + else if (src_x <= dst_x && src_y >= dst_y) + ctrl |= 0x00450000L; + else + ctrl |= 0x00470000L; + + de_wait_slots (4); + DE_WR_FIFO (ctrl); + DE_WR_FIFO ((src_y << 16) | src_x); + DE_WR_FIFO ((dst_y << 16) | dst_x); + DE_WR_FIFO ((height << 16) | width); + de_wait (); /* sync */ +} +#endif diff --git a/qemu/roms/u-boot/drivers/video/mb86r0xgdc.c b/qemu/roms/u-boot/drivers/video/mb86r0xgdc.c new file mode 100644 index 000000000..bb7a7497c --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/mb86r0xgdc.c @@ -0,0 +1,168 @@ +/* + * (C) Copyright 2010 + * Matthias Weisser <weisserm@arcor.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * mb86r0xgdc.c - Graphic interface for Fujitsu MB86R0x integrated graphic + * controller. + */ + +#include <common.h> + +#include <malloc.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <video_fb.h> +#include "videomodes.h" + +/* + * 4MB (at the end of system RAM) + */ +#define VIDEO_MEM_SIZE 0x400000 + +#define FB_SYNC_CLK_INV (1<<16) /* pixel clock inverted */ + +/* + * Graphic Device + */ +static GraphicDevice mb86r0x; + +static void dsp_init(struct mb86r0x_gdc_dsp *dsp, char *modestr, + u32 *videomem) +{ + struct ctfb_res_modes var_mode; + u32 dcm1, dcm2, dcm3; + u16 htp, hdp, hdb, hsp, vtr, vsp, vdp; + u8 hsw, vsw; + u32 l2m, l2em, l2oa0, l2da0, l2oa1, l2da1; + u16 l2dx, l2dy, l2wx, l2wy, l2ww, l2wh; + unsigned long div; + int bpp; + + bpp = video_get_params(&var_mode, modestr); + + if (bpp == 0) { + var_mode.xres = 640; + var_mode.yres = 480; + var_mode.pixclock = 39721; /* 25MHz */ + var_mode.left_margin = 48; + var_mode.right_margin = 16; + var_mode.upper_margin = 33; + var_mode.lower_margin = 10; + var_mode.hsync_len = 96; + var_mode.vsync_len = 2; + var_mode.sync = 0; + var_mode.vmode = 0; + bpp = 15; + } + + /* Fill memory with white */ + memset(videomem, 0xFF, var_mode.xres * var_mode.yres * 2); + + mb86r0x.winSizeX = var_mode.xres; + mb86r0x.winSizeY = var_mode.yres; + + /* LCD base clock is ~ 660MHZ. We do calculations in kHz */ + div = 660000 / (1000000000L / var_mode.pixclock); + if (div > 64) + div = 64; + if (0 == div) + div = 1; + + dcm1 = (div - 1) << 8; + dcm2 = 0x00000000; + if (var_mode.sync & FB_SYNC_CLK_INV) + dcm3 = 0x00000100; + else + dcm3 = 0x00000000; + + htp = var_mode.left_margin + var_mode.xres + + var_mode.hsync_len + var_mode.right_margin; + hdp = var_mode.xres; + hdb = var_mode.xres; + hsp = var_mode.xres + var_mode.right_margin; + hsw = var_mode.hsync_len; + + vsw = var_mode.vsync_len; + vtr = var_mode.upper_margin + var_mode.yres + + var_mode.vsync_len + var_mode.lower_margin; + vsp = var_mode.yres + var_mode.lower_margin; + vdp = var_mode.yres; + + l2m = ((var_mode.yres - 1) << (0)) | + (((var_mode.xres * 2) / 64) << (16)) | + ((1) << (31)); + + l2em = (1 << 0) | (1 << 1); + + l2oa0 = mb86r0x.frameAdrs; + l2da0 = mb86r0x.frameAdrs; + l2oa1 = mb86r0x.frameAdrs; + l2da1 = mb86r0x.frameAdrs; + l2dx = 0; + l2dy = 0; + l2wx = 0; + l2wy = 0; + l2ww = var_mode.xres; + l2wh = var_mode.yres - 1; + + writel(dcm1, &dsp->dcm1); + writel(dcm2, &dsp->dcm2); + writel(dcm3, &dsp->dcm3); + + writew(htp, &dsp->htp); + writew(hdp, &dsp->hdp); + writew(hdb, &dsp->hdb); + writew(hsp, &dsp->hsp); + writeb(hsw, &dsp->hsw); + + writeb(vsw, &dsp->vsw); + writew(vtr, &dsp->vtr); + writew(vsp, &dsp->vsp); + writew(vdp, &dsp->vdp); + + writel(l2m, &dsp->l2m); + writel(l2em, &dsp->l2em); + writel(l2oa0, &dsp->l2oa0); + writel(l2da0, &dsp->l2da0); + writel(l2oa1, &dsp->l2oa1); + writel(l2da1, &dsp->l2da1); + writew(l2dx, &dsp->l2dx); + writew(l2dy, &dsp->l2dy); + writew(l2wx, &dsp->l2wx); + writew(l2wy, &dsp->l2wy); + writew(l2ww, &dsp->l2ww); + writew(l2wh, &dsp->l2wh); + + writel(dcm1 | (1 << 18) | (1 << 31), &dsp->dcm1); +} + +void *video_hw_init(void) +{ + struct mb86r0x_gdc *gdc = (struct mb86r0x_gdc *) MB86R0x_GDC_BASE; + GraphicDevice *pGD = &mb86r0x; + char *s; + u32 *vid; + + memset(pGD, 0, sizeof(GraphicDevice)); + + pGD->gdfIndex = GDF_15BIT_555RGB; + pGD->gdfBytesPP = 2; + pGD->memSize = VIDEO_MEM_SIZE; + pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE; + + vid = (u32 *)pGD->frameAdrs; + + s = getenv("videomode"); + if (s != NULL) + dsp_init(&gdc->dsp0, s, vid); + + s = getenv("videomode1"); + if (s != NULL) + dsp_init(&gdc->dsp1, s, vid); + + return pGD; +} diff --git a/qemu/roms/u-boot/drivers/video/mpc8xx_lcd.c b/qemu/roms/u-boot/drivers/video/mpc8xx_lcd.c new file mode 100644 index 000000000..fceed871a --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/mpc8xx_lcd.c @@ -0,0 +1,548 @@ +/* + * (C) Copyright 2001-2002 + * Wolfgang Denk, DENX Software Engineering -- wd@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/************************************************************************/ +/* ** HEADER FILES */ +/************************************************************************/ + +/* #define DEBUG */ + +#include <config.h> +#include <common.h> +#include <command.h> +#include <watchdog.h> +#include <version.h> +#include <stdarg.h> +#include <lcdvideo.h> +#include <linux/types.h> +#include <stdio_dev.h> +#if defined(CONFIG_POST) +#include <post.h> +#endif +#include <lcd.h> + +#ifdef CONFIG_LCD + +/************************************************************************/ +/* ** CONFIG STUFF -- should be moved to board config file */ +/************************************************************************/ +#ifndef CONFIG_LCD_INFO +#define CONFIG_LCD_INFO /* Display Logo, (C) and system info */ +#endif + +#if defined(CONFIG_V37) || defined(CONFIG_EDT32F10) +#undef CONFIG_LCD_LOGO +#undef CONFIG_LCD_INFO +#endif + +/*----------------------------------------------------------------------*/ +#ifdef CONFIG_KYOCERA_KCS057QV1AJ +/* + * Kyocera KCS057QV1AJ-G23. Passive, color, single scan. + */ +#define LCD_BPP LCD_COLOR4 + +vidinfo_t panel_info = { + 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, + LCD_BPP, 1, 0, 1, 0, 5, 0, 0, 0 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_KYOCERA_KCS057QV1AJ */ +/*----------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------*/ +#ifdef CONFIG_HITACHI_SP19X001_Z1A +/* + * Hitachi SP19X001-. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, + LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_HITACHI_SP19X001_Z1A */ +/*----------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------*/ +#ifdef CONFIG_NEC_NL6448AC33 +/* + * NEC NL6448AC33-18. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, + 3, 0, 0, 1, 1, 144, 2, 0, 33 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_NEC_NL6448AC33 */ +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_NEC_NL6448BC20 +/* + * NEC NL6448BC20-08. 6.5", 640x480. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, + 3, 0, 0, 1, 1, 144, 2, 0, 33 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_NEC_NL6448BC20 */ +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_NEC_NL6448BC33_54 +/* + * NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, + 3, 0, 0, 1, 1, 144, 2, 0, 33 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_NEC_NL6448BC33_54 */ +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_SHARP_LQ104V7DS01 +/* + * SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW, + 3, 0, 0, 1, 1, 25, 1, 0, 33 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_SHARP_LQ104V7DS01 */ +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_SHARP_16x9 +/* + * Sharp 320x240. Active, color, single scan. It isn't 16x9, and I am + * not sure what it is....... + */ +vidinfo_t panel_info = { + 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, + 3, 0, 0, 1, 1, 15, 4, 0, 3 +}; +#endif /* CONFIG_SHARP_16x9 */ +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_SHARP_LQ057Q3DC02 +/* + * Sharp LQ057Q3DC02 display. Active, color, single scan. + */ +#undef LCD_DF +#define LCD_DF 12 + +vidinfo_t panel_info = { + 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, + 3, 0, 0, 1, 1, 15, 4, 0, 3 + /* wbl, vpw, lcdac, wbf */ +}; +#define CONFIG_LCD_INFO_BELOW_LOGO +#endif /* CONFIG_SHARP_LQ057Q3DC02 */ +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_SHARP_LQ64D341 +/* + * Sharp LQ64D341 display, 640x480. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, + 3, 0, 0, 1, 1, 128, 16, 0, 32 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_SHARP_LQ64D341 */ + +#ifdef CONFIG_SHARP_LQ065T9DR51U +/* + * Sharp LQ065T9DR51U display, 400x240. Active, color, single scan. + */ +vidinfo_t panel_info = { + 400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, + 3, 0, 0, 1, 1, 248, 4, 0, 35 + /* wbl, vpw, lcdac, wbf */ +}; +#define CONFIG_LCD_INFO_BELOW_LOGO +#endif /* CONFIG_SHARP_LQ065T9DR51U */ + +#ifdef CONFIG_SHARP_LQ084V1DG21 +/* + * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW, + 3, 0, 0, 1, 1, 160, 3, 0, 48 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_SHARP_LQ084V1DG21 */ + +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_HLD1045 +/* + * HLD1045 display, 640x480. Active, color, single scan. + */ +vidinfo_t panel_info = { + 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, + 3, 0, 0, 1, 1, 160, 3, 0, 48 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_HLD1045 */ +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_PRIMEVIEW_V16C6448AC +/* + * Prime View V16C6448AC + */ +vidinfo_t panel_info = { + 640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, + 3, 0, 0, 1, 1, 144, 2, 0, 35 + /* wbl, vpw, lcdac, wbf */ +}; +#endif /* CONFIG_PRIMEVIEW_V16C6448AC */ + +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_OPTREX_BW +/* + * Optrex CBL50840-2 NF-FW 99 22 M5 + * or + * Hitachi LMG6912RPFC-00T + * or + * Hitachi SP14Q002 + * + * 320x240. Black & white. + */ +#define OPTREX_BPP 0 /* 0 - monochrome, 1 bpp */ + /* 1 - 4 grey levels, 2 bpp */ + /* 2 - 16 grey levels, 4 bpp */ +vidinfo_t panel_info = { + 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, + OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4 +}; +#endif /* CONFIG_OPTREX_BW */ + +/*-----------------------------------------------------------------*/ +#ifdef CONFIG_EDT32F10 +/* + * Emerging Display Technologies 320x240. Passive, monochrome, single scan. + */ +#define LCD_BPP LCD_MONOCHROME +#define LCD_DF 10 + +vidinfo_t panel_info = { + 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, + LCD_BPP, 0, 0, 0, 0, 33, 0, 0, 0 +}; +#endif + +/************************************************************************/ +/* ----------------- chipset specific functions ----------------------- */ +/************************************************************************/ + +/* + * Calculate fb size for VIDEOLFB_ATAG. + */ +ulong calc_fbsize (void) +{ + ulong size; + int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; + + size = line_length * panel_info.vl_row; + + return size; +} + +void lcd_ctrl_init (void *lcdbase) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + volatile lcd823_t *lcdp = &immr->im_lcd; + + uint lccrtmp; + uint lchcr_hpc_tmp; + + /* Initialize the LCD control register according to the LCD + * parameters defined. We do everything here but enable + * the controller. + */ + +#ifdef CONFIG_RPXLITE + /* This is special for RPXlite_DW Software Development Platform **[Sam]** */ + panel_info.vl_dp = CONFIG_SYS_LOW; +#endif + + lccrtmp = LCDBIT (LCCR_BNUM_BIT, + (((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128)); + + lccrtmp |= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp) | + LCDBIT (LCCR_OEP_BIT, panel_info.vl_oep) | + LCDBIT (LCCR_HSP_BIT, panel_info.vl_hsp) | + LCDBIT (LCCR_VSP_BIT, panel_info.vl_vsp) | + LCDBIT (LCCR_DP_BIT, panel_info.vl_dp) | + LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix) | + LCDBIT (LCCR_LBW_BIT, panel_info.vl_lbw) | + LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt) | + LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor) | + LCDBIT (LCCR_TFT_BIT, panel_info.vl_tft); + +#if 0 + lccrtmp |= ((SIU_LEVEL5 / 2) << 12); + lccrtmp |= LCCR_EIEN; +#endif + + lcdp->lcd_lccr = lccrtmp; + lcdp->lcd_lcsr = 0xFF; /* Clear pending interrupts */ + + /* Initialize LCD controller bus priorities. + */ +#ifdef CONFIG_RBC823 + immr->im_siu_conf.sc_sdcr = (immr->im_siu_conf.sc_sdcr & ~0x0f) | 1; /* RAID = 01, LAID = 00 */ +#else + immr->im_siu_conf.sc_sdcr &= ~0x0f; /* RAID = LAID = 0 */ + + /* set SHFT/CLOCK division factor 4 + * This needs to be set based upon display type and processor + * speed. The TFT displays run about 20 to 30 MHz. + * I was running 64 MHz processor speed. + * The value for this divider must be chosen so the result is + * an integer of the processor speed (i.e., divide by 3 with + * 64 MHz would be bad). + */ + immr->im_clkrst.car_sccr &= ~0x1F; + immr->im_clkrst.car_sccr |= LCD_DF; /* was 8 */ + +#endif /* CONFIG_RBC823 */ + +#if defined(CONFIG_RBC823) + /* Enable LCD on port D. + */ + immr->im_ioport.iop_pddat &= 0x0300; + immr->im_ioport.iop_pdpar |= 0x1CFF; + immr->im_ioport.iop_pddir |= 0x1CFF; + + /* Configure LCD_ON, VEE_ON, CCFL_ON on port B. + */ + immr->im_cpm.cp_pbdat &= ~0x00005001; + immr->im_cpm.cp_pbpar &= ~0x00005001; + immr->im_cpm.cp_pbdir |= 0x00005001; +#elif !defined(CONFIG_EDT32F10) + /* Enable LCD on port D. + */ + immr->im_ioport.iop_pdpar |= 0x1FFF; + immr->im_ioport.iop_pddir |= 0x1FFF; + + /* Enable LCD_A/B/C on port B. + */ + immr->im_cpm.cp_pbpar |= 0x00005001; + immr->im_cpm.cp_pbdir |= 0x00005001; +#else + /* Enable LCD on port D. + */ + immr->im_ioport.iop_pdpar |= 0x1DFF; + immr->im_ioport.iop_pdpar &= ~0x0200; + immr->im_ioport.iop_pddir |= 0x1FFF; + immr->im_ioport.iop_pddat |= 0x0200; +#endif + + /* Load the physical address of the linear frame buffer + * into the LCD controller. + * BIG NOTE: This has to be modified to load A and B depending + * upon the split mode of the LCD. + */ + lcdp->lcd_lcfaa = (ulong)lcdbase; + lcdp->lcd_lcfba = (ulong)lcdbase; + + /* MORE HACKS...This must be updated according to 823 manual + * for different panels. + * Udi Finkelstein - done - see below: + * Note: You better not try unsupported combinations such as + * 4-bit wide passive dual scan LCD at 4/8 Bit color. + */ + lchcr_hpc_tmp = + (panel_info.vl_col * + (panel_info.vl_tft ? 8 : + (((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */ + /* use << to mult by: single scan = 1, dual scan = 2 */ + panel_info.vl_splt) * + (panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */ + + lcdp->lcd_lchcr = LCHCR_BO | + LCDBIT (LCHCR_AT_BIT, 4) | + LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) | + panel_info.vl_wbl; + + lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) | + LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) | + LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) | + panel_info.vl_wbf; + +} + +/*----------------------------------------------------------------------*/ + +#if LCD_BPP == LCD_COLOR8 +void +lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + volatile cpm8xx_t *cp = &(immr->im_cpm); + unsigned short colreg, *cmap_ptr; + + cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2]; + + colreg = ((red & 0x0F) << 8) | + ((green & 0x0F) << 4) | + (blue & 0x0F) ; +#ifdef CONFIG_SYS_INVERT_COLORS + colreg ^= 0x0FFF; +#endif + *cmap_ptr = colreg; + + debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n", + regno, &(cp->lcd_cmap[regno * 2]), + red, green, blue, + cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]); +} +#endif /* LCD_COLOR8 */ + +/*----------------------------------------------------------------------*/ + +#if LCD_BPP == LCD_MONOCHROME +static +void lcd_initcolregs (void) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + volatile cpm8xx_t *cp = &(immr->im_cpm); + ushort regno; + + for (regno = 0; regno < 16; regno++) { + cp->lcd_cmap[regno * 2] = 0; + cp->lcd_cmap[(regno * 2) + 1] = regno & 0x0f; + } +} +#endif + +/*----------------------------------------------------------------------*/ + +void lcd_enable (void) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + volatile lcd823_t *lcdp = &immr->im_lcd; + + /* Enable the LCD panel */ +#ifndef CONFIG_RBC823 + immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */ +#endif + lcdp->lcd_lccr |= LCCR_PON; + +#ifdef CONFIG_V37 + /* Turn on display backlight */ + immr->im_cpm.cp_pbpar |= 0x00008000; + immr->im_cpm.cp_pbdir |= 0x00008000; +#elif defined(CONFIG_RBC823) + /* Turn on display backlight */ + immr->im_cpm.cp_pbdat |= 0x00004000; +#endif + +#if defined(CONFIG_LWMON) + { uchar c = pic_read (0x60); +#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON) + /* Enable LCD later in sysmon test, only if temperature is OK */ +#else + c |= 0x07; /* Power on CCFL, Enable CCFL, Chip Enable LCD */ +#endif + pic_write (0x60, c); + } +#endif /* CONFIG_LWMON */ + +#if defined(CONFIG_R360MPI) + { + extern void r360_i2c_lcd_write (uchar data0, uchar data1); + unsigned long bgi, ctr; + char *p; + + if ((p = getenv("lcdbgi")) != NULL) { + bgi = simple_strtoul (p, 0, 10) & 0xFFF; + } else { + bgi = 0xFFF; + } + + if ((p = getenv("lcdctr")) != NULL) { + ctr = simple_strtoul (p, 0, 10) & 0xFFF; + } else { + ctr=0x7FF; + } + + r360_i2c_lcd_write(0x10, 0x01); + r360_i2c_lcd_write(0x20, 0x01); + r360_i2c_lcd_write(0x30 | ((bgi>>8) & 0xF), bgi & 0xFF); + r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF); + } +#endif /* CONFIG_R360MPI */ +#ifdef CONFIG_RBC823 + udelay(200000); /* wait 200ms */ + /* Turn VEE_ON first */ + immr->im_cpm.cp_pbdat |= 0x00000001; + udelay(200000); /* wait 200ms */ + /* Now turn on LCD_ON */ + immr->im_cpm.cp_pbdat |= 0x00001000; +#endif +#ifdef CONFIG_RRVISION + debug ("PC4->Output(1): enable LVDS\n"); + debug ("PC5->Output(0): disable PAL clock\n"); + immr->im_ioport.iop_pddir |= 0x1000; + immr->im_ioport.iop_pcpar &= ~(0x0C00); + immr->im_ioport.iop_pcdir |= 0x0C00 ; + immr->im_ioport.iop_pcdat |= 0x0800 ; + immr->im_ioport.iop_pcdat &= ~(0x0400); + debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n", + immr->im_ioport.iop_pdpar, + immr->im_ioport.iop_pddir, + immr->im_ioport.iop_pddat); + debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n", + immr->im_ioport.iop_pcpar, + immr->im_ioport.iop_pcdir, + immr->im_ioport.iop_pcdat); +#endif +} + +/*----------------------------------------------------------------------*/ + +#if defined (CONFIG_RBC823) +void lcd_disable (void) +{ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + volatile lcd823_t *lcdp = &immr->im_lcd; + +#if defined(CONFIG_LWMON) + { uchar c = pic_read (0x60); + c &= ~0x07; /* Power off CCFL, Disable CCFL, Chip Disable LCD */ + pic_write (0x60, c); + } +#elif defined(CONFIG_R360MPI) + { + extern void r360_i2c_lcd_write (uchar data0, uchar data1); + + r360_i2c_lcd_write(0x10, 0x00); + r360_i2c_lcd_write(0x20, 0x00); + r360_i2c_lcd_write(0x30, 0x00); + r360_i2c_lcd_write(0x40, 0x00); + } +#endif /* CONFIG_LWMON */ + /* Disable the LCD panel */ + lcdp->lcd_lccr &= ~LCCR_PON; +#ifdef CONFIG_RBC823 + /* Turn off display backlight, VEE and LCD_ON */ + immr->im_cpm.cp_pbdat &= ~0x00005001; +#else + immr->im_siu_conf.sc_sdcr &= ~(1 << (31 - 25)); /* LAM = 0 */ +#endif /* CONFIG_RBC823 */ +} +#endif /* NOT_USED_SO_FAR || CONFIG_RBC823 */ + + +/************************************************************************/ + +#endif /* CONFIG_LCD */ diff --git a/qemu/roms/u-boot/drivers/video/mx3fb.c b/qemu/roms/u-boot/drivers/video/mx3fb.c new file mode 100644 index 000000000..aa4cc433b --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/mx3fb.c @@ -0,0 +1,915 @@ +/* + * Copyright (C) 2009 + * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> + * Copyright (C) 2011 + * HALE electronic GmbH, <helmut.raiger@hale.at> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <malloc.h> +#include <video_fb.h> + +#include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> +#include <asm/errno.h> +#include <asm/io.h> + +#include "videomodes.h" + +/* this might need panel specific set-up as-well */ +#define IF_CONF 0 + +/* -------------- controller specific stuff -------------- */ + +/* IPU DMA Controller channel definitions. */ +enum ipu_channel { + IDMAC_IC_0 = 0, /* IC (encoding task) to memory */ + IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */ + IDMAC_ADC_0 = 1, + IDMAC_IC_2 = 2, + IDMAC_ADC_1 = 2, + IDMAC_IC_3 = 3, + IDMAC_IC_4 = 4, + IDMAC_IC_5 = 5, + IDMAC_IC_6 = 6, + IDMAC_IC_7 = 7, /* IC (sensor data) to memory */ + IDMAC_IC_8 = 8, + IDMAC_IC_9 = 9, + IDMAC_IC_10 = 10, + IDMAC_IC_11 = 11, + IDMAC_IC_12 = 12, + IDMAC_IC_13 = 13, + IDMAC_SDC_0 = 14, /* Background synchronous display data */ + IDMAC_SDC_1 = 15, /* Foreground data (overlay) */ + IDMAC_SDC_2 = 16, + IDMAC_SDC_3 = 17, + IDMAC_ADC_2 = 18, + IDMAC_ADC_3 = 19, + IDMAC_ADC_4 = 20, + IDMAC_ADC_5 = 21, + IDMAC_ADC_6 = 22, + IDMAC_ADC_7 = 23, + IDMAC_PF_0 = 24, + IDMAC_PF_1 = 25, + IDMAC_PF_2 = 26, + IDMAC_PF_3 = 27, + IDMAC_PF_4 = 28, + IDMAC_PF_5 = 29, + IDMAC_PF_6 = 30, + IDMAC_PF_7 = 31, +}; + +/* More formats can be copied from the Linux driver if needed */ +enum pixel_fmt { + /* 2 bytes */ + IPU_PIX_FMT_RGB565, + IPU_PIX_FMT_RGB666, + IPU_PIX_FMT_BGR666, + /* 3 bytes */ + IPU_PIX_FMT_RGB24, +}; + +struct pixel_fmt_cfg { + u32 b0; + u32 b1; + u32 b2; + u32 acc; +}; + +static struct pixel_fmt_cfg fmt_cfg[] = { + [IPU_PIX_FMT_RGB24] = { + 0x1600AAAA, 0x00E05555, 0x00070000, 3, + }, + [IPU_PIX_FMT_RGB666] = { + 0x0005000F, 0x000B000F, 0x0011000F, 1, + }, + [IPU_PIX_FMT_BGR666] = { + 0x0011000F, 0x000B000F, 0x0005000F, 1, + }, + [IPU_PIX_FMT_RGB565] = { + 0x0004003F, 0x000A000F, 0x000F003F, 1, + } +}; + +enum ipu_panel { + IPU_PANEL_SHARP_TFT, + IPU_PANEL_TFT, +}; + +/* IPU Common registers */ +/* IPU_CONF and its bits already defined in imx-regs.h */ +#define IPU_CHA_BUF0_RDY (0x04 + IPU_BASE) +#define IPU_CHA_BUF1_RDY (0x08 + IPU_BASE) +#define IPU_CHA_DB_MODE_SEL (0x0C + IPU_BASE) +#define IPU_CHA_CUR_BUF (0x10 + IPU_BASE) +#define IPU_FS_PROC_FLOW (0x14 + IPU_BASE) +#define IPU_FS_DISP_FLOW (0x18 + IPU_BASE) +#define IPU_TASKS_STAT (0x1C + IPU_BASE) +#define IPU_IMA_ADDR (0x20 + IPU_BASE) +#define IPU_IMA_DATA (0x24 + IPU_BASE) +#define IPU_INT_CTRL_1 (0x28 + IPU_BASE) +#define IPU_INT_CTRL_2 (0x2C + IPU_BASE) +#define IPU_INT_CTRL_3 (0x30 + IPU_BASE) +#define IPU_INT_CTRL_4 (0x34 + IPU_BASE) +#define IPU_INT_CTRL_5 (0x38 + IPU_BASE) +#define IPU_INT_STAT_1 (0x3C + IPU_BASE) +#define IPU_INT_STAT_2 (0x40 + IPU_BASE) +#define IPU_INT_STAT_3 (0x44 + IPU_BASE) +#define IPU_INT_STAT_4 (0x48 + IPU_BASE) +#define IPU_INT_STAT_5 (0x4C + IPU_BASE) +#define IPU_BRK_CTRL_1 (0x50 + IPU_BASE) +#define IPU_BRK_CTRL_2 (0x54 + IPU_BASE) +#define IPU_BRK_STAT (0x58 + IPU_BASE) +#define IPU_DIAGB_CTRL (0x5C + IPU_BASE) + +/* Image Converter Registers */ +#define IC_CONF (0x88 + IPU_BASE) +#define IC_PRP_ENC_RSC (0x8C + IPU_BASE) +#define IC_PRP_VF_RSC (0x90 + IPU_BASE) +#define IC_PP_RSC (0x94 + IPU_BASE) +#define IC_CMBP_1 (0x98 + IPU_BASE) +#define IC_CMBP_2 (0x9C + IPU_BASE) +#define PF_CONF (0xA0 + IPU_BASE) +#define IDMAC_CONF (0xA4 + IPU_BASE) +#define IDMAC_CHA_EN (0xA8 + IPU_BASE) +#define IDMAC_CHA_PRI (0xAC + IPU_BASE) +#define IDMAC_CHA_BUSY (0xB0 + IPU_BASE) + +/* Image Converter Register bits */ +#define IC_CONF_PRPENC_EN 0x00000001 +#define IC_CONF_PRPENC_CSC1 0x00000002 +#define IC_CONF_PRPENC_ROT_EN 0x00000004 +#define IC_CONF_PRPVF_EN 0x00000100 +#define IC_CONF_PRPVF_CSC1 0x00000200 +#define IC_CONF_PRPVF_CSC2 0x00000400 +#define IC_CONF_PRPVF_CMB 0x00000800 +#define IC_CONF_PRPVF_ROT_EN 0x00001000 +#define IC_CONF_PP_EN 0x00010000 +#define IC_CONF_PP_CSC1 0x00020000 +#define IC_CONF_PP_CSC2 0x00040000 +#define IC_CONF_PP_CMB 0x00080000 +#define IC_CONF_PP_ROT_EN 0x00100000 +#define IC_CONF_IC_GLB_LOC_A 0x10000000 +#define IC_CONF_KEY_COLOR_EN 0x20000000 +#define IC_CONF_RWS_EN 0x40000000 +#define IC_CONF_CSI_MEM_WR_EN 0x80000000 + +/* SDC Registers */ +#define SDC_COM_CONF (0xB4 + IPU_BASE) +#define SDC_GW_CTRL (0xB8 + IPU_BASE) +#define SDC_FG_POS (0xBC + IPU_BASE) +#define SDC_BG_POS (0xC0 + IPU_BASE) +#define SDC_CUR_POS (0xC4 + IPU_BASE) +#define SDC_PWM_CTRL (0xC8 + IPU_BASE) +#define SDC_CUR_MAP (0xCC + IPU_BASE) +#define SDC_HOR_CONF (0xD0 + IPU_BASE) +#define SDC_VER_CONF (0xD4 + IPU_BASE) +#define SDC_SHARP_CONF_1 (0xD8 + IPU_BASE) +#define SDC_SHARP_CONF_2 (0xDC + IPU_BASE) + +/* Register bits */ +#define SDC_COM_TFT_COLOR 0x00000001UL +#define SDC_COM_FG_EN 0x00000010UL +#define SDC_COM_GWSEL 0x00000020UL +#define SDC_COM_GLB_A 0x00000040UL +#define SDC_COM_KEY_COLOR_G 0x00000080UL +#define SDC_COM_BG_EN 0x00000200UL +#define SDC_COM_SHARP 0x00001000UL + +#define SDC_V_SYNC_WIDTH_L 0x00000001UL + +/* Display Interface registers */ +#define DI_DISP_IF_CONF (0x0124 + IPU_BASE) +#define DI_DISP_SIG_POL (0x0128 + IPU_BASE) +#define DI_SER_DISP1_CONF (0x012C + IPU_BASE) +#define DI_SER_DISP2_CONF (0x0130 + IPU_BASE) +#define DI_HSP_CLK_PER (0x0134 + IPU_BASE) +#define DI_DISP0_TIME_CONF_1 (0x0138 + IPU_BASE) +#define DI_DISP0_TIME_CONF_2 (0x013C + IPU_BASE) +#define DI_DISP0_TIME_CONF_3 (0x0140 + IPU_BASE) +#define DI_DISP1_TIME_CONF_1 (0x0144 + IPU_BASE) +#define DI_DISP1_TIME_CONF_2 (0x0148 + IPU_BASE) +#define DI_DISP1_TIME_CONF_3 (0x014C + IPU_BASE) +#define DI_DISP2_TIME_CONF_1 (0x0150 + IPU_BASE) +#define DI_DISP2_TIME_CONF_2 (0x0154 + IPU_BASE) +#define DI_DISP2_TIME_CONF_3 (0x0158 + IPU_BASE) +#define DI_DISP3_TIME_CONF (0x015C + IPU_BASE) +#define DI_DISP0_DB0_MAP (0x0160 + IPU_BASE) +#define DI_DISP0_DB1_MAP (0x0164 + IPU_BASE) +#define DI_DISP0_DB2_MAP (0x0168 + IPU_BASE) +#define DI_DISP0_CB0_MAP (0x016C + IPU_BASE) +#define DI_DISP0_CB1_MAP (0x0170 + IPU_BASE) +#define DI_DISP0_CB2_MAP (0x0174 + IPU_BASE) +#define DI_DISP1_DB0_MAP (0x0178 + IPU_BASE) +#define DI_DISP1_DB1_MAP (0x017C + IPU_BASE) +#define DI_DISP1_DB2_MAP (0x0180 + IPU_BASE) +#define DI_DISP1_CB0_MAP (0x0184 + IPU_BASE) +#define DI_DISP1_CB1_MAP (0x0188 + IPU_BASE) +#define DI_DISP1_CB2_MAP (0x018C + IPU_BASE) +#define DI_DISP2_DB0_MAP (0x0190 + IPU_BASE) +#define DI_DISP2_DB1_MAP (0x0194 + IPU_BASE) +#define DI_DISP2_DB2_MAP (0x0198 + IPU_BASE) +#define DI_DISP2_CB0_MAP (0x019C + IPU_BASE) +#define DI_DISP2_CB1_MAP (0x01A0 + IPU_BASE) +#define DI_DISP2_CB2_MAP (0x01A4 + IPU_BASE) +#define DI_DISP3_B0_MAP (0x01A8 + IPU_BASE) +#define DI_DISP3_B1_MAP (0x01AC + IPU_BASE) +#define DI_DISP3_B2_MAP (0x01B0 + IPU_BASE) +#define DI_DISP_ACC_CC (0x01B4 + IPU_BASE) +#define DI_DISP_LLA_CONF (0x01B8 + IPU_BASE) +#define DI_DISP_LLA_DATA (0x01BC + IPU_BASE) + +/* DI_DISP_SIG_POL bits */ +#define DI_D3_VSYNC_POL (1 << 28) +#define DI_D3_HSYNC_POL (1 << 27) +#define DI_D3_DRDY_SHARP_POL (1 << 26) +#define DI_D3_CLK_POL (1 << 25) +#define DI_D3_DATA_POL (1 << 24) + +/* DI_DISP_IF_CONF bits */ +#define DI_D3_CLK_IDLE (1 << 26) +#define DI_D3_CLK_SEL (1 << 25) +#define DI_D3_DATAMSK (1 << 24) + +#define IOMUX_PADNUM_MASK 0x1ff +#define IOMUX_GPIONUM_SHIFT 9 +#define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT) + +#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK) + +#define IOMUX_MODE_L(pin, mode) IOMUX_MODE(((pin) + 0xc) ^ 3, mode) + +struct chan_param_mem_planar { + /* Word 0 */ + u32 xv:10; + u32 yv:10; + u32 xb:12; + + u32 yb:12; + u32 res1:2; + u32 nsb:1; + u32 lnpb:6; + u32 ubo_l:11; + + u32 ubo_h:15; + u32 vbo_l:17; + + u32 vbo_h:9; + u32 res2:3; + u32 fw:12; + u32 fh_l:8; + + u32 fh_h:4; + u32 res3:28; + + /* Word 1 */ + u32 eba0; + + u32 eba1; + + u32 bpp:3; + u32 sl:14; + u32 pfs:3; + u32 bam:3; + u32 res4:2; + u32 npb:6; + u32 res5:1; + + u32 sat:2; + u32 res6:30; +} __attribute__ ((packed)); + +struct chan_param_mem_interleaved { + /* Word 0 */ + u32 xv:10; + u32 yv:10; + u32 xb:12; + + u32 yb:12; + u32 sce:1; + u32 res1:1; + u32 nsb:1; + u32 lnpb:6; + u32 sx:10; + u32 sy_l:1; + + u32 sy_h:9; + u32 ns:10; + u32 sm:10; + u32 sdx_l:3; + + u32 sdx_h:2; + u32 sdy:5; + u32 sdrx:1; + u32 sdry:1; + u32 sdr1:1; + u32 res2:2; + u32 fw:12; + u32 fh_l:8; + + u32 fh_h:4; + u32 res3:28; + + /* Word 1 */ + u32 eba0; + + u32 eba1; + + u32 bpp:3; + u32 sl:14; + u32 pfs:3; + u32 bam:3; + u32 res4:2; + u32 npb:6; + u32 res5:1; + + u32 sat:2; + u32 scc:1; + u32 ofs0:5; + u32 ofs1:5; + u32 ofs2:5; + u32 ofs3:5; + u32 wid0:3; + u32 wid1:3; + u32 wid2:3; + + u32 wid3:3; + u32 dec_sel:1; + u32 res6:28; +} __attribute__ ((packed)); + +union chan_param_mem { + struct chan_param_mem_planar pp; + struct chan_param_mem_interleaved ip; +}; + +DECLARE_GLOBAL_DATA_PTR; + +/* graphics setup */ +static GraphicDevice panel; +static struct ctfb_res_modes *mode; +static struct ctfb_res_modes var_mode; + +/* + * sdc_init_panel() - initialize a synchronous LCD panel. + * @width: width of panel in pixels. + * @height: height of panel in pixels. + * @di_setup: pixel format of the frame buffer + * @di_panel: either SHARP or normal TFT + * @return: 0 on success or negative error code on failure. + */ +static int sdc_init_panel(u16 width, u16 height, + enum pixel_fmt di_setup, enum ipu_panel di_panel) +{ + u32 reg, div; + uint32_t old_conf; + int clock; + + debug("%s(width=%d, height=%d)\n", __func__, width, height); + + /* Init clocking, the IPU receives its clock from the hsp divder */ + clock = mxc_get_clock(MXC_IPU_CLK); + if (clock < 0) + return -EACCES; + + /* Init panel size and blanking periods */ + reg = width + mode->left_margin + mode->right_margin - 1; + if (reg > 1023) { + printf("mx3fb: Display width too large, coerced to 1023!"); + reg = 1023; + } + reg = ((mode->hsync_len - 1) << 26) | (reg << 16); + writel(reg, SDC_HOR_CONF); + + reg = height + mode->upper_margin + mode->lower_margin - 1; + if (reg > 1023) { + printf("mx3fb: Display height too large, coerced to 1023!"); + reg = 1023; + } + reg = ((mode->vsync_len - 1) << 26) | SDC_V_SYNC_WIDTH_L | (reg << 16); + writel(reg, SDC_VER_CONF); + + switch (di_panel) { + case IPU_PANEL_SHARP_TFT: + writel(0x00FD0102L, SDC_SHARP_CONF_1); + writel(0x00F500F4L, SDC_SHARP_CONF_2); + writel(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF); + /* TODO: probably IF_CONF must be adapted (see below)! */ + break; + case IPU_PANEL_TFT: + writel(SDC_COM_TFT_COLOR, SDC_COM_CONF); + break; + default: + return -EINVAL; + } + + /* + * Calculate divider: The fractional part is 4 bits so simply + * multiple by 2^4 to get it. + * + * Opposed to the kernel driver mode->pixclock is the time of one + * pixel in pico seconds, so: + * pixel_clk = 1e12 / mode->pixclock + * div = ipu_clk * 16 / pixel_clk + * leads to: + * div = ipu_clk * 16 / (1e12 / mode->pixclock) + * or: + * div = ipu_clk * 16 * mode->pixclock / 1e12 + * + * To avoid integer overflows this is split into 2 shifts and + * one divide with sufficient accuracy: + * 16*1024*128*476837 = 0.9999996682e12 + */ + div = ((clock/1024) * (mode->pixclock/128)) / 476837; + debug("hsp_clk is %d, div=%d\n", clock, div); + /* coerce to not less than 4.0, not more than 255.9375 */ + if (div < 0x40) + div = 0x40; + else if (div > 0xFFF) + div = 0xFFF; + /* DISP3_IF_CLK_DOWN_WR is half the divider value and 2 less + * fraction bits. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR + * based on timing debug DISP3_IF_CLK_UP_WR is 0 + */ + writel((((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF); + + /* DI settings for display 3: clock idle (bit 26) during vsync */ + old_conf = readl(DI_DISP_IF_CONF) & 0x78FFFFFF; + writel(old_conf | IF_CONF, DI_DISP_IF_CONF); + + /* only set display 3 polarity bits */ + old_conf = readl(DI_DISP_SIG_POL) & 0xE0FFFFFF; + writel(old_conf | mode->sync, DI_DISP_SIG_POL); + + writel(fmt_cfg[di_setup].b0, DI_DISP3_B0_MAP); + writel(fmt_cfg[di_setup].b1, DI_DISP3_B1_MAP); + writel(fmt_cfg[di_setup].b2, DI_DISP3_B2_MAP); + writel(readl(DI_DISP_ACC_CC) | + ((fmt_cfg[di_setup].acc - 1) << 12), DI_DISP_ACC_CC); + + debug("DI_DISP_IF_CONF = 0x%08X\n", readl(DI_DISP_IF_CONF)); + debug("DI_DISP_SIG_POL = 0x%08X\n", readl(DI_DISP_SIG_POL)); + debug("DI_DISP3_TIME_CONF = 0x%08X\n", readl(DI_DISP3_TIME_CONF)); + debug("SDC_HOR_CONF = 0x%08X\n", readl(SDC_HOR_CONF)); + debug("SDC_VER_CONF = 0x%08X\n", readl(SDC_VER_CONF)); + + return 0; +} + +static void ipu_ch_param_set_size(union chan_param_mem *params, + uint pixelfmt, uint16_t width, + uint16_t height, uint16_t stride) +{ + debug("%s(pixelfmt=%d, width=%d, height=%d, stride=%d)\n", + __func__, pixelfmt, width, height, stride); + + params->pp.fw = width - 1; + params->pp.fh_l = height - 1; + params->pp.fh_h = (height - 1) >> 8; + params->pp.sl = stride - 1; + + /* See above, for further formats see the Linux driver */ + switch (pixelfmt) { + case GDF_16BIT_565RGB: + params->ip.bpp = 2; + params->ip.pfs = 4; + params->ip.npb = 7; + params->ip.sat = 2; /* SAT = 32-bit access */ + params->ip.ofs0 = 0; /* Red bit offset */ + params->ip.ofs1 = 5; /* Green bit offset */ + params->ip.ofs2 = 11; /* Blue bit offset */ + params->ip.ofs3 = 16; /* Alpha bit offset */ + params->ip.wid0 = 4; /* Red bit width - 1 */ + params->ip.wid1 = 5; /* Green bit width - 1 */ + params->ip.wid2 = 4; /* Blue bit width - 1 */ + break; + case GDF_32BIT_X888RGB: + params->ip.bpp = 1; /* 24 BPP & RGB PFS */ + params->ip.pfs = 4; + params->ip.npb = 7; + params->ip.sat = 2; /* SAT = 32-bit access */ + params->ip.ofs0 = 16; /* Red bit offset */ + params->ip.ofs1 = 8; /* Green bit offset */ + params->ip.ofs2 = 0; /* Blue bit offset */ + params->ip.ofs3 = 24; /* Alpha bit offset */ + params->ip.wid0 = 7; /* Red bit width - 1 */ + params->ip.wid1 = 7; /* Green bit width - 1 */ + params->ip.wid2 = 7; /* Blue bit width - 1 */ + break; + default: + printf("mx3fb: Pixel format not supported!\n"); + break; + } + + params->pp.nsb = 1; +} + +static void ipu_ch_param_set_buffer(union chan_param_mem *params, + void *buf0, void *buf1) +{ + params->pp.eba0 = (u32)buf0; + params->pp.eba1 = (u32)buf1; +} + +static void ipu_write_param_mem(uint32_t addr, uint32_t *data, + uint32_t num_words) +{ + for (; num_words > 0; num_words--) { + writel(addr, IPU_IMA_ADDR); + writel(*data++, IPU_IMA_DATA); + addr++; + if ((addr & 0x7) == 5) { + addr &= ~0x7; /* set to word 0 */ + addr += 8; /* increment to next row */ + } + } +} + +static uint32_t dma_param_addr(enum ipu_channel channel) +{ + /* Channel Parameter Memory */ + return 0x10000 | (channel << 4); +} + +static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem) +{ + union chan_param_mem params = {}; + uint32_t reg; + uint32_t stride_bytes; + + stride_bytes = (panel.plnSizeX * panel.gdfBytesPP + 3) & ~3; + + debug("%s(channel=%d, fbmem=%p)\n", __func__, channel, fbmem); + + /* Build parameter memory data for DMA channel */ + ipu_ch_param_set_size(¶ms, panel.gdfIndex, + panel.plnSizeX, panel.plnSizeY, stride_bytes); + ipu_ch_param_set_buffer(¶ms, fbmem, NULL); + params.pp.bam = 0; + /* Some channels (rotation) have restriction on burst length */ + + switch (channel) { + case IDMAC_SDC_0: + /* In original code only IPU_PIX_FMT_RGB565 was setting burst */ + params.pp.npb = 16 - 1; + break; + default: + break; + } + + ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)¶ms, 10); + + /* Disable double-buffering */ + reg = readl(IPU_CHA_DB_MODE_SEL); + reg &= ~(1UL << channel); + writel(reg, IPU_CHA_DB_MODE_SEL); +} + +static void ipu_channel_set_priority(enum ipu_channel channel, + int prio) +{ + u32 reg = readl(IDMAC_CHA_PRI); + + if (prio) + reg |= 1UL << channel; + else + reg &= ~(1UL << channel); + + writel(reg, IDMAC_CHA_PRI); +} + +/* + * ipu_enable_channel() - enable an IPU channel. + * @channel: channel ID. + * @return: 0 on success or negative error code on failure. + */ +static int ipu_enable_channel(enum ipu_channel channel) +{ + uint32_t reg; + + /* Reset to buffer 0 */ + writel(1UL << channel, IPU_CHA_CUR_BUF); + + switch (channel) { + case IDMAC_SDC_0: + ipu_channel_set_priority(channel, 1); + break; + default: + break; + } + + reg = readl(IDMAC_CHA_EN); + writel(reg | (1UL << channel), IDMAC_CHA_EN); + + return 0; +} + +static int ipu_update_channel_buffer(enum ipu_channel channel, void *buf) +{ + uint32_t reg; + + reg = readl(IPU_CHA_BUF0_RDY); + if (reg & (1UL << channel)) + return -EACCES; + + /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */ + writel(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR); + writel((u32)buf, IPU_IMA_DATA); + + return 0; +} + +static int idmac_tx_submit(enum ipu_channel channel, void *buf) +{ + int ret; + + ipu_init_channel_buffer(channel, buf); + + + /* ipu_idmac.c::ipu_submit_channel_buffers() */ + ret = ipu_update_channel_buffer(channel, buf); + if (ret < 0) + return ret; + + /* ipu_idmac.c::ipu_select_buffer() */ + /* Mark buffer 0 as ready. */ + writel(1UL << channel, IPU_CHA_BUF0_RDY); + + + ret = ipu_enable_channel(channel); + return ret; +} + +static void sdc_enable_channel(void *fbmem) +{ + int ret; + u32 reg; + + ret = idmac_tx_submit(IDMAC_SDC_0, fbmem); + + /* mx3fb.c::sdc_fb_init() */ + if (ret >= 0) { + reg = readl(SDC_COM_CONF); + writel(reg | SDC_COM_BG_EN, SDC_COM_CONF); + } + + /* + * Attention! Without this msleep the channel keeps generating + * interrupts. Next sdc_set_brightness() is going to be called + * from mx3fb_blank(). + */ + udelay(2000); +} + +/* + * mx3fb_set_par() - set framebuffer parameters and change the operating mode. + * @return: 0 on success or negative error code on failure. + * TODO: currently only 666 and TFT as DI setup supported + */ +static int mx3fb_set_par(void) +{ + int ret; + + ret = sdc_init_panel(panel.plnSizeX, panel.plnSizeY, + IPU_PIX_FMT_RGB666, IPU_PANEL_TFT); + if (ret < 0) + return ret; + + writel((mode->left_margin << 16) | mode->upper_margin, SDC_BG_POS); + + return 0; +} + +static void ll_disp3_enable(void *base) +{ + u32 reg; + + debug("%s(base=0x%x)\n", __func__, (u32) base); + /* pcm037.c::mxc_board_init() */ + + /* Display Interface #3 */ + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD0, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD1, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD2, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD3, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD4, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD5, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD6, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD7, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD8, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD9, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD10, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD11, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD12, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD13, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD14, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD15, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD16, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD17, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_VSYNC3, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_HSYNC, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_FPSHIFT, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_DRDY0, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_REV, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_CONTRAST, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_SPL, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_CLS, MUX_CTL_FUNC)); + + + /* ipu_idmac.c::ipu_probe() */ + + /* Start the clock */ + __REG(CCM_CGR1) = __REG(CCM_CGR1) | (3 << 22); + + + /* ipu_idmac.c::ipu_idmac_init() */ + + /* Service request counter to maximum - shouldn't be needed */ + writel(0x00000070, IDMAC_CONF); + + + /* ipu_idmac.c::ipu_init_channel() */ + + /* Enable IPU sub modules */ + reg = readl(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN; + writel(reg, IPU_CONF); + + + /* mx3fb.c::init_fb_chan() */ + + /* set Display Interface clock period */ + writel(0x00100010L, DI_HSP_CLK_PER); + /* Might need to trigger HSP clock change - see 44.3.3.8.5 */ + + + /* mx3fb.c::sdc_set_brightness() */ + + /* This might be board-specific */ + writel(0x03000000UL | 255 << 16, SDC_PWM_CTRL); + + + /* mx3fb.c::sdc_set_global_alpha() */ + + /* Use global - not per-pixel - Alpha-blending */ + reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL; + writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL); + + reg = readl(SDC_COM_CONF); + writel(reg | SDC_COM_GLB_A, SDC_COM_CONF); + + + /* mx3fb.c::sdc_set_color_key() */ + + /* Disable colour-keying for background */ + reg = readl(SDC_COM_CONF) & + ~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G); + writel(reg, SDC_COM_CONF); + + + mx3fb_set_par(); + + sdc_enable_channel(base); + + /* + * Linux driver calls sdc_set_brightness() here again, + * once is enough for us + */ + debug("%s() done\n", __func__); +} + +/* ------------------------ public part ------------------- */ +ulong calc_fbsize(void) +{ + return panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP; +} + +/* + * The current implementation is only tested for GDF_16BIT_565RGB! + * It was switched from the original CONFIG_LCD setup to CONFIG_VIDEO, + * because the lcd code seemed loaded with color table stuff, that + * does not relate to most modern TFTs. cfb_console.c looks more + * straight forward. + * This is the environment setting for the original setup + * "unknown=video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,le:9,ri:17, + * up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0" + * "videomode=unknown" + * + * Settings for VBEST VGG322403 display: + * "videomode=video=ctfb:x:320,y:240,depth:16,mode:0,pclk:156000, + * "le:20,ri:68,up:7,lo:29,hs:30,vs:3,sync:100663296,vmode:0" + * + * Settings for COM57H5M10XRC display: + * "videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000, + * "le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296,vmode:0" + */ +void *video_hw_init(void) +{ + char *penv; + u32 memsize; + unsigned long t1, hsynch, vsynch; + int bits_per_pixel, i, tmp, videomode; + + tmp = 0; + + puts("Video: "); + + videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE; + /* get video mode via environment */ + penv = getenv("videomode"); + if (penv) { + /* decide if it is a string */ + if (penv[0] <= '9') { + videomode = (int) simple_strtoul(penv, NULL, 16); + tmp = 1; + } + } else { + tmp = 1; + } + if (tmp) { + /* parameter are vesa modes */ + /* search params */ + for (i = 0; i < VESA_MODES_COUNT; i++) { + if (vesa_modes[i].vesanr == videomode) + break; + } + if (i == VESA_MODES_COUNT) { + printf("No VESA Mode found, switching to mode 0x%x ", + CONFIG_SYS_DEFAULT_VIDEO_MODE); + i = 0; + } + mode = (struct ctfb_res_modes *) + &res_mode_init[vesa_modes[i].resindex]; + bits_per_pixel = vesa_modes[i].bits_per_pixel; + } else { + mode = (struct ctfb_res_modes *) &var_mode; + bits_per_pixel = video_get_params(mode, penv); + } + + /* calculate hsynch and vsynch freq (info only) */ + t1 = (mode->left_margin + mode->xres + + mode->right_margin + mode->hsync_len) / 8; + t1 *= 8; + t1 *= mode->pixclock; + t1 /= 1000; + hsynch = 1000000000L / t1; + t1 *= (mode->upper_margin + mode->yres + + mode->lower_margin + mode->vsync_len); + t1 /= 1000; + vsynch = 1000000000L / t1; + + /* fill in Graphic device struct */ + sprintf(panel.modeIdent, "%dx%dx%d %ldkHz %ldHz", + mode->xres, mode->yres, + bits_per_pixel, (hsynch / 1000), (vsynch / 1000)); + printf("%s\n", panel.modeIdent); + panel.winSizeX = mode->xres; + panel.winSizeY = mode->yres; + panel.plnSizeX = mode->xres; + panel.plnSizeY = mode->yres; + + switch (bits_per_pixel) { + case 24: + panel.gdfBytesPP = 4; + panel.gdfIndex = GDF_32BIT_X888RGB; + break; + case 16: + panel.gdfBytesPP = 2; + panel.gdfIndex = GDF_16BIT_565RGB; + break; + default: + panel.gdfBytesPP = 1; + panel.gdfIndex = GDF__8BIT_INDEX; + break; + } + + /* set up Hardware */ + memsize = calc_fbsize(); + + debug("%s() allocating %d bytes\n", __func__, memsize); + + /* fill in missing Graphic device struct */ + panel.frameAdrs = (u32) malloc(memsize); + if (panel.frameAdrs == 0) { + printf("%s() malloc(%d) failed\n", __func__, memsize); + return 0; + } + panel.memSize = memsize; + + ll_disp3_enable((void *) panel.frameAdrs); + memset((void *) panel.frameAdrs, 0, memsize); + + debug("%s() done, framebuffer at 0x%x, size=%d cleared\n", + __func__, panel.frameAdrs, memsize); + + return (void *) &panel; +} + +void video_set_lut(unsigned int index, /* color number */ + unsigned char r, /* red */ + unsigned char g, /* green */ + unsigned char b /* blue */ + ) +{ + return; +} diff --git a/qemu/roms/u-boot/drivers/video/mxc_ipuv3_fb.c b/qemu/roms/u-boot/drivers/video/mxc_ipuv3_fb.c new file mode 100644 index 000000000..f75d77064 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/mxc_ipuv3_fb.c @@ -0,0 +1,621 @@ +/* + * Porting to u-boot: + * + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de + * + * MX51 Linux framebuffer: + * + * (C) Copyright 2004-2010 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/errno.h> +#include <asm/global_data.h> +#include <linux/string.h> +#include <linux/list.h> +#include <linux/fb.h> +#include <asm/io.h> +#include <malloc.h> +#include <video_fb.h> +#include "videomodes.h" +#include "ipu.h" +#include "mxcfb.h" +#include "ipu_regs.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int mxcfb_map_video_memory(struct fb_info *fbi); +static int mxcfb_unmap_video_memory(struct fb_info *fbi); + +/* graphics setup */ +static GraphicDevice panel; +static struct fb_videomode const *gmode; +static uint8_t gdisp; +static uint32_t gpixfmt; + +void fb_videomode_to_var(struct fb_var_screeninfo *var, + const struct fb_videomode *mode) +{ + var->xres = mode->xres; + var->yres = mode->yres; + var->xres_virtual = mode->xres; + var->yres_virtual = mode->yres; + var->xoffset = 0; + var->yoffset = 0; + var->pixclock = mode->pixclock; + var->left_margin = mode->left_margin; + var->right_margin = mode->right_margin; + var->upper_margin = mode->upper_margin; + var->lower_margin = mode->lower_margin; + var->hsync_len = mode->hsync_len; + var->vsync_len = mode->vsync_len; + var->sync = mode->sync; + var->vmode = mode->vmode & FB_VMODE_MASK; +} + +/* + * Structure containing the MXC specific framebuffer information. + */ +struct mxcfb_info { + int blank; + ipu_channel_t ipu_ch; + int ipu_di; + u32 ipu_di_pix_fmt; + unsigned char overlay; + unsigned char alpha_chan_en; + dma_addr_t alpha_phy_addr0; + dma_addr_t alpha_phy_addr1; + void *alpha_virt_addr0; + void *alpha_virt_addr1; + uint32_t alpha_mem_len; + uint32_t cur_ipu_buf; + uint32_t cur_ipu_alpha_buf; + + u32 pseudo_palette[16]; +}; + +enum { + BOTH_ON, + SRC_ON, + TGT_ON, + BOTH_OFF +}; + +static unsigned long default_bpp = 16; +static unsigned char g_dp_in_use; +static struct fb_info *mxcfb_info[3]; +static int ext_clk_used; + +static uint32_t bpp_to_pixfmt(struct fb_info *fbi) +{ + uint32_t pixfmt = 0; + + debug("bpp_to_pixfmt: %d\n", fbi->var.bits_per_pixel); + + if (fbi->var.nonstd) + return fbi->var.nonstd; + + switch (fbi->var.bits_per_pixel) { + case 24: + pixfmt = IPU_PIX_FMT_BGR24; + break; + case 32: + pixfmt = IPU_PIX_FMT_BGR32; + break; + case 16: + pixfmt = IPU_PIX_FMT_RGB565; + break; + } + return pixfmt; +} + +/* + * Set fixed framebuffer parameters based on variable settings. + * + * @param info framebuffer information pointer + */ +static int mxcfb_set_fix(struct fb_info *info) +{ + struct fb_fix_screeninfo *fix = &info->fix; + struct fb_var_screeninfo *var = &info->var; + + fix->line_length = var->xres_virtual * var->bits_per_pixel / 8; + + fix->type = FB_TYPE_PACKED_PIXELS; + fix->accel = FB_ACCEL_NONE; + fix->visual = FB_VISUAL_TRUECOLOR; + fix->xpanstep = 1; + fix->ypanstep = 1; + + return 0; +} + +static int setup_disp_channel1(struct fb_info *fbi) +{ + ipu_channel_params_t params; + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par; + + memset(¶ms, 0, sizeof(params)); + params.mem_dp_bg_sync.di = mxc_fbi->ipu_di; + + debug("%s called\n", __func__); + /* + * Assuming interlaced means yuv output, below setting also + * valid for mem_dc_sync. FG should have the same vmode as BG. + */ + if (fbi->var.vmode & FB_VMODE_INTERLACED) { + params.mem_dp_bg_sync.interlaced = 1; + params.mem_dp_bg_sync.out_pixel_fmt = + IPU_PIX_FMT_YUV444; + } else { + if (mxc_fbi->ipu_di_pix_fmt) { + params.mem_dp_bg_sync.out_pixel_fmt = + mxc_fbi->ipu_di_pix_fmt; + } else { + params.mem_dp_bg_sync.out_pixel_fmt = + IPU_PIX_FMT_RGB666; + } + } + params.mem_dp_bg_sync.in_pixel_fmt = bpp_to_pixfmt(fbi); + if (mxc_fbi->alpha_chan_en) + params.mem_dp_bg_sync.alpha_chan_en = 1; + + ipu_init_channel(mxc_fbi->ipu_ch, ¶ms); + + return 0; +} + +static int setup_disp_channel2(struct fb_info *fbi) +{ + int retval = 0; + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par; + + mxc_fbi->cur_ipu_buf = 1; + if (mxc_fbi->alpha_chan_en) + mxc_fbi->cur_ipu_alpha_buf = 1; + + fbi->var.xoffset = fbi->var.yoffset = 0; + + debug("%s: %x %d %d %d %lx %lx\n", + __func__, + mxc_fbi->ipu_ch, + fbi->var.xres, + fbi->var.yres, + fbi->fix.line_length, + fbi->fix.smem_start, + fbi->fix.smem_start + + (fbi->fix.line_length * fbi->var.yres)); + + retval = ipu_init_channel_buffer(mxc_fbi->ipu_ch, IPU_INPUT_BUFFER, + bpp_to_pixfmt(fbi), + fbi->var.xres, fbi->var.yres, + fbi->fix.line_length, + fbi->fix.smem_start + + (fbi->fix.line_length * fbi->var.yres), + fbi->fix.smem_start, + 0, 0); + if (retval) + printf("ipu_init_channel_buffer error %d\n", retval); + + return retval; +} + +/* + * Set framebuffer parameters and change the operating mode. + * + * @param info framebuffer information pointer + */ +static int mxcfb_set_par(struct fb_info *fbi) +{ + int retval = 0; + u32 mem_len; + ipu_di_signal_cfg_t sig_cfg; + struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par; + uint32_t out_pixel_fmt; + + ipu_disable_channel(mxc_fbi->ipu_ch); + ipu_uninit_channel(mxc_fbi->ipu_ch); + mxcfb_set_fix(fbi); + + mem_len = fbi->var.yres_virtual * fbi->fix.line_length; + if (!fbi->fix.smem_start || (mem_len > fbi->fix.smem_len)) { + if (fbi->fix.smem_start) + mxcfb_unmap_video_memory(fbi); + + if (mxcfb_map_video_memory(fbi) < 0) + return -ENOMEM; + } + + setup_disp_channel1(fbi); + + memset(&sig_cfg, 0, sizeof(sig_cfg)); + if (fbi->var.vmode & FB_VMODE_INTERLACED) { + sig_cfg.interlaced = 1; + out_pixel_fmt = IPU_PIX_FMT_YUV444; + } else { + if (mxc_fbi->ipu_di_pix_fmt) + out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt; + else + out_pixel_fmt = IPU_PIX_FMT_RGB666; + } + if (fbi->var.vmode & FB_VMODE_ODD_FLD_FIRST) /* PAL */ + sig_cfg.odd_field_first = 1; + if ((fbi->var.sync & FB_SYNC_EXT) || ext_clk_used) + sig_cfg.ext_clk = 1; + if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT) + sig_cfg.Hsync_pol = 1; + if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT) + sig_cfg.Vsync_pol = 1; + if (!(fbi->var.sync & FB_SYNC_CLK_LAT_FALL)) + sig_cfg.clk_pol = 1; + if (fbi->var.sync & FB_SYNC_DATA_INVERT) + sig_cfg.data_pol = 1; + if (!(fbi->var.sync & FB_SYNC_OE_LOW_ACT)) + sig_cfg.enable_pol = 1; + if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN) + sig_cfg.clkidle_en = 1; + + debug("pixclock = %ul Hz\n", + (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL)); + + if (ipu_init_sync_panel(mxc_fbi->ipu_di, + (PICOS2KHZ(fbi->var.pixclock)) * 1000UL, + fbi->var.xres, fbi->var.yres, + out_pixel_fmt, + fbi->var.left_margin, + fbi->var.hsync_len, + fbi->var.right_margin, + fbi->var.upper_margin, + fbi->var.vsync_len, + fbi->var.lower_margin, + 0, sig_cfg) != 0) { + puts("mxcfb: Error initializing panel.\n"); + return -EINVAL; + } + + retval = setup_disp_channel2(fbi); + if (retval) + return retval; + + if (mxc_fbi->blank == FB_BLANK_UNBLANK) + ipu_enable_channel(mxc_fbi->ipu_ch); + + return retval; +} + +/* + * Check framebuffer variable parameters and adjust to valid values. + * + * @param var framebuffer variable parameters + * + * @param info framebuffer information pointer + */ +static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) +{ + u32 vtotal; + u32 htotal; + + if (var->xres_virtual < var->xres) + var->xres_virtual = var->xres; + if (var->yres_virtual < var->yres) + var->yres_virtual = var->yres; + + if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) && + (var->bits_per_pixel != 16) && (var->bits_per_pixel != 8)) + var->bits_per_pixel = default_bpp; + + switch (var->bits_per_pixel) { + case 8: + var->red.length = 3; + var->red.offset = 5; + var->red.msb_right = 0; + + var->green.length = 3; + var->green.offset = 2; + var->green.msb_right = 0; + + var->blue.length = 2; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 16: + var->red.length = 5; + var->red.offset = 11; + var->red.msb_right = 0; + + var->green.length = 6; + var->green.offset = 5; + var->green.msb_right = 0; + + var->blue.length = 5; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 24: + var->red.length = 8; + var->red.offset = 16; + var->red.msb_right = 0; + + var->green.length = 8; + var->green.offset = 8; + var->green.msb_right = 0; + + var->blue.length = 8; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 32: + var->red.length = 8; + var->red.offset = 16; + var->red.msb_right = 0; + + var->green.length = 8; + var->green.offset = 8; + var->green.msb_right = 0; + + var->blue.length = 8; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 8; + var->transp.offset = 24; + var->transp.msb_right = 0; + break; + } + + if (var->pixclock < 1000) { + htotal = var->xres + var->right_margin + var->hsync_len + + var->left_margin; + vtotal = var->yres + var->lower_margin + var->vsync_len + + var->upper_margin; + var->pixclock = (vtotal * htotal * 6UL) / 100UL; + var->pixclock = KHZ2PICOS(var->pixclock); + printf("pixclock set for 60Hz refresh = %u ps\n", + var->pixclock); + } + + var->height = -1; + var->width = -1; + var->grayscale = 0; + + return 0; +} + +static int mxcfb_map_video_memory(struct fb_info *fbi) +{ + if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length) { + fbi->fix.smem_len = fbi->var.yres_virtual * + fbi->fix.line_length; + } + fbi->fix.smem_len = roundup(fbi->fix.smem_len, ARCH_DMA_MINALIGN); + fbi->screen_base = (char *)memalign(ARCH_DMA_MINALIGN, + fbi->fix.smem_len); + fbi->fix.smem_start = (unsigned long)fbi->screen_base; + if (fbi->screen_base == 0) { + puts("Unable to allocate framebuffer memory\n"); + fbi->fix.smem_len = 0; + fbi->fix.smem_start = 0; + return -EBUSY; + } + + debug("allocated fb @ paddr=0x%08X, size=%d.\n", + (uint32_t) fbi->fix.smem_start, fbi->fix.smem_len); + + fbi->screen_size = fbi->fix.smem_len; + + gd->fb_base = fbi->fix.smem_start; + + /* Clear the screen */ + memset((char *)fbi->screen_base, 0, fbi->fix.smem_len); + + return 0; +} + +static int mxcfb_unmap_video_memory(struct fb_info *fbi) +{ + fbi->screen_base = 0; + fbi->fix.smem_start = 0; + fbi->fix.smem_len = 0; + return 0; +} + +/* + * Initializes the framebuffer information pointer. After allocating + * sufficient memory for the framebuffer structure, the fields are + * filled with custom information passed in from the configurable + * structures. This includes information such as bits per pixel, + * color maps, screen width/height and RGBA offsets. + * + * @return Framebuffer structure initialized with our information + */ +static struct fb_info *mxcfb_init_fbinfo(void) +{ +#define BYTES_PER_LONG 4 +#define PADDING (BYTES_PER_LONG - (sizeof(struct fb_info) % BYTES_PER_LONG)) + struct fb_info *fbi; + struct mxcfb_info *mxcfbi; + char *p; + int size = sizeof(struct mxcfb_info) + PADDING + + sizeof(struct fb_info); + + debug("%s: %d %d %d %d\n", + __func__, + PADDING, + size, + sizeof(struct mxcfb_info), + sizeof(struct fb_info)); + /* + * Allocate sufficient memory for the fb structure + */ + + p = malloc(size); + if (!p) + return NULL; + + memset(p, 0, size); + + fbi = (struct fb_info *)p; + fbi->par = p + sizeof(struct fb_info) + PADDING; + + mxcfbi = (struct mxcfb_info *)fbi->par; + debug("Framebuffer structures at: fbi=0x%x mxcfbi=0x%x\n", + (unsigned int)fbi, (unsigned int)mxcfbi); + + fbi->var.activate = FB_ACTIVATE_NOW; + + fbi->flags = FBINFO_FLAG_DEFAULT; + fbi->pseudo_palette = mxcfbi->pseudo_palette; + + return fbi; +} + +/* + * Probe routine for the framebuffer driver. It is called during the + * driver binding process. The following functions are performed in + * this routine: Framebuffer initialization, Memory allocation and + * mapping, Framebuffer registration, IPU initialization. + * + * @return Appropriate error code to the kernel common code + */ +static int mxcfb_probe(u32 interface_pix_fmt, uint8_t disp, + struct fb_videomode const *mode) +{ + struct fb_info *fbi; + struct mxcfb_info *mxcfbi; + int ret = 0; + + /* + * Initialize FB structures + */ + fbi = mxcfb_init_fbinfo(); + if (!fbi) { + ret = -ENOMEM; + goto err0; + } + mxcfbi = (struct mxcfb_info *)fbi->par; + + if (!g_dp_in_use) { + mxcfbi->ipu_ch = MEM_BG_SYNC; + mxcfbi->blank = FB_BLANK_UNBLANK; + } else { + mxcfbi->ipu_ch = MEM_DC_SYNC; + mxcfbi->blank = FB_BLANK_POWERDOWN; + } + + mxcfbi->ipu_di = disp; + + ipu_disp_set_global_alpha(mxcfbi->ipu_ch, 1, 0x80); + ipu_disp_set_color_key(mxcfbi->ipu_ch, 0, 0); + strcpy(fbi->fix.id, "DISP3 BG"); + + g_dp_in_use = 1; + + mxcfb_info[mxcfbi->ipu_di] = fbi; + + /* Need dummy values until real panel is configured */ + + mxcfbi->ipu_di_pix_fmt = interface_pix_fmt; + fb_videomode_to_var(&fbi->var, mode); + fbi->var.bits_per_pixel = 16; + fbi->fix.line_length = fbi->var.xres * (fbi->var.bits_per_pixel / 8); + fbi->fix.smem_len = fbi->var.yres_virtual * fbi->fix.line_length; + + mxcfb_check_var(&fbi->var, fbi); + + /* Default Y virtual size is 2x panel size */ + fbi->var.yres_virtual = fbi->var.yres * 2; + + mxcfb_set_fix(fbi); + + /* alocate fb first */ + if (mxcfb_map_video_memory(fbi) < 0) + return -ENOMEM; + + mxcfb_set_par(fbi); + + panel.winSizeX = mode->xres; + panel.winSizeY = mode->yres; + panel.plnSizeX = mode->xres; + panel.plnSizeY = mode->yres; + + panel.frameAdrs = (u32)fbi->screen_base; + panel.memSize = fbi->screen_size; + + panel.gdfBytesPP = 2; + panel.gdfIndex = GDF_16BIT_565RGB; + + ipu_dump_registers(); + + return 0; + +err0: + return ret; +} + +void ipuv3_fb_shutdown(void) +{ + int i; + struct ipu_stat *stat = (struct ipu_stat *)IPU_STAT; + + for (i = 0; i < ARRAY_SIZE(mxcfb_info); i++) { + struct fb_info *fbi = mxcfb_info[i]; + if (fbi) { + struct mxcfb_info *mxc_fbi = fbi->par; + ipu_disable_channel(mxc_fbi->ipu_ch); + ipu_uninit_channel(mxc_fbi->ipu_ch); + } + } + for (i = 0; i < ARRAY_SIZE(stat->int_stat); i++) { + __raw_writel(__raw_readl(&stat->int_stat[i]), + &stat->int_stat[i]); + } +} + +void *video_hw_init(void) +{ + int ret; + + ret = ipu_probe(); + if (ret) + puts("Error initializing IPU\n"); + + ret = mxcfb_probe(gpixfmt, gdisp, gmode); + debug("Framebuffer at 0x%x\n", (unsigned int)panel.frameAdrs); + + return (void *)&panel; +} + +void video_set_lut(unsigned int index, /* color number */ + unsigned char r, /* red */ + unsigned char g, /* green */ + unsigned char b /* blue */ + ) +{ + return; +} + +int ipuv3_fb_init(struct fb_videomode const *mode, + uint8_t disp, + uint32_t pixfmt) +{ + gmode = mode; + gdisp = disp; + gpixfmt = pixfmt; + + return 0; +} diff --git a/qemu/roms/u-boot/drivers/video/mxcfb.h b/qemu/roms/u-boot/drivers/video/mxcfb.h new file mode 100644 index 000000000..77079e85e --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/mxcfb.h @@ -0,0 +1,52 @@ +/* + * Porting to u-boot: + * + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de + * + * Linux IPU driver for MX51: + * + * (C) Copyright 2004-2009 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_MXCFB_H__ +#define __ASM_ARCH_MXCFB_H__ + +#define FB_SYNC_OE_LOW_ACT 0x80000000 +#define FB_SYNC_CLK_LAT_FALL 0x40000000 +#define FB_SYNC_DATA_INVERT 0x20000000 +#define FB_SYNC_CLK_IDLE_EN 0x10000000 +#define FB_SYNC_SHARP_MODE 0x08000000 +#define FB_SYNC_SWAP_RGB 0x04000000 + +struct mxcfb_gbl_alpha { + int enable; + int alpha; +}; + +struct mxcfb_loc_alpha { + int enable; + int alpha_in_pixel; + unsigned long alpha_phy_addr0; + unsigned long alpha_phy_addr1; +}; + +struct mxcfb_color_key { + int enable; + __u32 color_key; +}; + +struct mxcfb_pos { + __u16 x; + __u16 y; +}; + +struct mxcfb_gamma { + int enable; + int constk[16]; + int slopek[16]; +}; + +#endif diff --git a/qemu/roms/u-boot/drivers/video/mxsfb.c b/qemu/roms/u-boot/drivers/video/mxsfb.c new file mode 100644 index 000000000..03b0f88ac --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/mxsfb.c @@ -0,0 +1,224 @@ +/* + * Freescale i.MX23/i.MX28 LCDIF driver + * + * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <malloc.h> +#include <video_fb.h> + +#include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/errno.h> +#include <asm/io.h> + +#include <asm/imx-common/dma.h> + +#include "videomodes.h" + +#define PS2KHZ(ps) (1000000000UL / (ps)) + +static GraphicDevice panel; +struct mxs_dma_desc desc; + +/** + * mxsfb_system_setup() - Fine-tune LCDIF configuration + * + * This function is used to adjust the LCDIF configuration. This is usually + * needed when driving the controller in System-Mode to operate an 8080 or + * 6800 connected SmartLCD. + */ +__weak void mxsfb_system_setup(void) +{ +} + +/* + * DENX M28EVK: + * setenv videomode + * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066, + * le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0 + * + * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel: + * setenv videomode + * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851, + * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0 + */ + +static void mxs_lcd_init(GraphicDevice *panel, + struct ctfb_res_modes *mode, int bpp) +{ + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + uint32_t word_len = 0, bus_width = 0; + uint8_t valid_data = 0; + + /* Kick in the LCDIF clock */ + mxs_set_lcdclk(PS2KHZ(mode->pixclock)); + + /* Restart the LCDIF block */ + mxs_reset_block(®s->hw_lcdif_ctrl_reg); + + switch (bpp) { + case 24: + word_len = LCDIF_CTRL_WORD_LENGTH_24BIT; + bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT; + valid_data = 0x7; + break; + case 18: + word_len = LCDIF_CTRL_WORD_LENGTH_24BIT; + bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT; + valid_data = 0x7; + break; + case 16: + word_len = LCDIF_CTRL_WORD_LENGTH_16BIT; + bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT; + valid_data = 0xf; + break; + case 8: + word_len = LCDIF_CTRL_WORD_LENGTH_8BIT; + bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT; + valid_data = 0xf; + break; + } + + writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE | + LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER, + ®s->hw_lcdif_ctrl); + + writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET, + ®s->hw_lcdif_ctrl1); + + mxsfb_system_setup(); + + writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres, + ®s->hw_lcdif_transfer_count); + + writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL | + LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | + LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT | + mode->vsync_len, ®s->hw_lcdif_vdctrl0); + writel(mode->upper_margin + mode->lower_margin + + mode->vsync_len + mode->yres, + ®s->hw_lcdif_vdctrl1); + writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) | + (mode->left_margin + mode->right_margin + + mode->hsync_len + mode->xres), + ®s->hw_lcdif_vdctrl2); + writel(((mode->left_margin + mode->hsync_len) << + LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) | + (mode->upper_margin + mode->vsync_len), + ®s->hw_lcdif_vdctrl3); + writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres, + ®s->hw_lcdif_vdctrl4); + + writel(panel->frameAdrs, ®s->hw_lcdif_cur_buf); + writel(panel->frameAdrs, ®s->hw_lcdif_next_buf); + + /* Flush FIFO first */ + writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_set); + +#ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM + /* Sync signals ON */ + setbits_le32(®s->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON); +#endif + + /* FIFO cleared */ + writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_clr); + + /* RUN! */ + writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set); +} + +void *video_hw_init(void) +{ + int bpp = -1; + char *penv; + void *fb; + struct ctfb_res_modes mode; + + puts("Video: "); + + /* Suck display configuration from "videomode" variable */ + penv = getenv("videomode"); + if (!penv) { + puts("MXSFB: 'videomode' variable not set!\n"); + return NULL; + } + + bpp = video_get_params(&mode, penv); + + /* fill in Graphic device struct */ + sprintf(panel.modeIdent, "%dx%dx%d", + mode.xres, mode.yres, bpp); + + panel.winSizeX = mode.xres; + panel.winSizeY = mode.yres; + panel.plnSizeX = mode.xres; + panel.plnSizeY = mode.yres; + + switch (bpp) { + case 24: + case 18: + panel.gdfBytesPP = 4; + panel.gdfIndex = GDF_32BIT_X888RGB; + break; + case 16: + panel.gdfBytesPP = 2; + panel.gdfIndex = GDF_16BIT_565RGB; + break; + case 8: + panel.gdfBytesPP = 1; + panel.gdfIndex = GDF__8BIT_INDEX; + break; + default: + printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp); + return NULL; + } + + panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP; + + /* Allocate framebuffer */ + fb = memalign(ARCH_DMA_MINALIGN, + roundup(panel.memSize, ARCH_DMA_MINALIGN)); + if (!fb) { + printf("MXSFB: Error allocating framebuffer!\n"); + return NULL; + } + + /* Wipe framebuffer */ + memset(fb, 0, panel.memSize); + + panel.frameAdrs = (u32)fb; + + printf("%s\n", panel.modeIdent); + + /* Start framebuffer */ + mxs_lcd_init(&panel, &mode, bpp); + +#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM + /* + * If the LCD runs in system mode, the LCD refresh has to be triggered + * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid + * having to set this bit manually after every single change in the + * framebuffer memory, we set up specially crafted circular DMA, which + * sets the RUN bit, then waits until it gets cleared and repeats this + * infinitelly. This way, we get smooth continuous updates of the LCD. + */ + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + + memset(&desc, 0, sizeof(struct mxs_dma_desc)); + desc.address = (dma_addr_t)&desc; + desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN | + MXS_DMA_DESC_WAIT4END | + (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET); + desc.cmd.pio_words[0] = readl(®s->hw_lcdif_ctrl) | LCDIF_CTRL_RUN; + desc.cmd.next = (uint32_t)&desc.cmd; + + /* Execute the DMA chain. */ + mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc); +#endif + + return (void *)&panel; +} diff --git a/qemu/roms/u-boot/drivers/video/omap3_dss.c b/qemu/roms/u-boot/drivers/video/omap3_dss.c new file mode 100644 index 000000000..6efba122e --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/omap3_dss.c @@ -0,0 +1,167 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * + * Referred to Linux Kernel DSS driver files for OMAP3 by + * Tomi Valkeinen from drivers/video/omap2/dss/ + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 and any + * later version the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/dss.h> +#include <video_fb.h> + +/* Configure VENC for a given Mode (NTSC / PAL) */ +void omap3_dss_venc_config(const struct venc_regs *venc_cfg, + u32 height, u32 width) +{ + struct venc_regs *venc = (struct venc_regs *) OMAP3_VENC_BASE; + struct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE; + struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE; + + writel(venc_cfg->status, &venc->status); + writel(venc_cfg->f_control, &venc->f_control); + writel(venc_cfg->vidout_ctrl, &venc->vidout_ctrl); + writel(venc_cfg->sync_ctrl, &venc->sync_ctrl); + writel(venc_cfg->llen, &venc->llen); + writel(venc_cfg->flens, &venc->flens); + writel(venc_cfg->hfltr_ctrl, &venc->hfltr_ctrl); + writel(venc_cfg->cc_carr_wss_carr, &venc->cc_carr_wss_carr); + writel(venc_cfg->c_phase, &venc->c_phase); + writel(venc_cfg->gain_u, &venc->gain_u); + writel(venc_cfg->gain_v, &venc->gain_v); + writel(venc_cfg->gain_y, &venc->gain_y); + writel(venc_cfg->black_level, &venc->black_level); + writel(venc_cfg->blank_level, &venc->blank_level); + writel(venc_cfg->x_color, &venc->x_color); + writel(venc_cfg->m_control, &venc->m_control); + writel(venc_cfg->bstamp_wss_data, &venc->bstamp_wss_data); + writel(venc_cfg->s_carr, &venc->s_carr); + writel(venc_cfg->line21, &venc->line21); + writel(venc_cfg->ln_sel, &venc->ln_sel); + writel(venc_cfg->l21__wc_ctl, &venc->l21__wc_ctl); + writel(venc_cfg->htrigger_vtrigger, &venc->htrigger_vtrigger); + writel(venc_cfg->savid__eavid, &venc->savid__eavid); + writel(venc_cfg->flen__fal, &venc->flen__fal); + writel(venc_cfg->lal__phase_reset, &venc->lal__phase_reset); + writel(venc_cfg->hs_int_start_stop_x, &venc->hs_int_start_stop_x); + writel(venc_cfg->hs_ext_start_stop_x, &venc->hs_ext_start_stop_x); + writel(venc_cfg->vs_int_start_x, &venc->vs_int_start_x); + writel(venc_cfg->vs_int_stop_x__vs_int_start_y, + &venc->vs_int_stop_x__vs_int_start_y); + writel(venc_cfg->vs_int_stop_y__vs_ext_start_x, + &venc->vs_int_stop_y__vs_ext_start_x); + writel(venc_cfg->vs_ext_stop_x__vs_ext_start_y, + &venc->vs_ext_stop_x__vs_ext_start_y); + writel(venc_cfg->vs_ext_stop_y, &venc->vs_ext_stop_y); + writel(venc_cfg->avid_start_stop_x, &venc->avid_start_stop_x); + writel(venc_cfg->avid_start_stop_y, &venc->avid_start_stop_y); + writel(venc_cfg->fid_int_start_x__fid_int_start_y, + &venc->fid_int_start_x__fid_int_start_y); + writel(venc_cfg->fid_int_offset_y__fid_ext_start_x, + &venc->fid_int_offset_y__fid_ext_start_x); + writel(venc_cfg->fid_ext_start_y__fid_ext_offset_y, + &venc->fid_ext_start_y__fid_ext_offset_y); + writel(venc_cfg->tvdetgp_int_start_stop_x, + &venc->tvdetgp_int_start_stop_x); + writel(venc_cfg->tvdetgp_int_start_stop_y, + &venc->tvdetgp_int_start_stop_y); + writel(venc_cfg->gen_ctrl, &venc->gen_ctrl); + writel(venc_cfg->output_control, &venc->output_control); + writel(venc_cfg->dac_b__dac_c, &venc->dac_b__dac_c); + + /* Configure DSS for VENC Settings */ + writel(VENC_CLK_ENABLE | DAC_DEMEN | DAC_POWERDN | VENC_OUT_SEL, + &dss->control); + + /* Configure height and width for Digital out */ + writel(height << DIG_LPP_SHIFT | width, &dispc->size_dig); +} + +/* Configure Panel Specific Parameters */ +void omap3_dss_panel_config(const struct panel_config *panel_cfg) +{ + struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE; + struct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE; + + writel(DSS_SOFTRESET, &dss->sysconfig); + while (!(readl(&dss->sysstatus) & DSS_RESETDONE)) + ; + + writel(panel_cfg->timing_h, &dispc->timing_h); + writel(panel_cfg->timing_v, &dispc->timing_v); + writel(panel_cfg->pol_freq, &dispc->pol_freq); + writel(panel_cfg->divisor, &dispc->divisor); + writel(panel_cfg->lcd_size, &dispc->size_lcd); + writel(panel_cfg->load_mode << LOADMODE_SHIFT, &dispc->config); + writel(panel_cfg->panel_type << TFTSTN_SHIFT | + panel_cfg->data_lines << DATALINES_SHIFT, &dispc->control); + writel(panel_cfg->panel_color, &dispc->default_color0); + writel((u32) panel_cfg->frame_buffer, &dispc->gfx_ba0); + + if (!panel_cfg->frame_buffer) + return; + + writel(panel_cfg->gfx_format | GFX_ENABLE, &dispc->gfx_attributes); + writel(1, &dispc->gfx_row_inc); + writel(1, &dispc->gfx_pixel_inc); + writel(panel_cfg->lcd_size, &dispc->gfx_size); +} + +/* Enable LCD and DIGITAL OUT in DSS */ +void omap3_dss_enable(void) +{ + struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE; + u32 l; + + l = readl(&dispc->control); + l |= LCD_ENABLE | GO_LCD | DIG_ENABLE | GO_DIG | GP_OUT0 | GP_OUT1; + writel(l, &dispc->control); +} + +#ifdef CONFIG_CFB_CONSOLE +int __board_video_init(void) +{ + return -1; +} + +int board_video_init(void) + __attribute__((weak, alias("__board_video_init"))); + +void *video_hw_init(void) +{ + static GraphicDevice dssfb; + GraphicDevice *pGD = &dssfb; + struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE; + + if (board_video_init() || !readl(&dispc->gfx_ba0)) + return NULL; + + pGD->winSizeX = (readl(&dispc->size_lcd) & 0x7FF) + 1; + pGD->winSizeY = ((readl(&dispc->size_lcd) >> 16) & 0x7FF) + 1; + pGD->gdfBytesPP = 4; + pGD->gdfIndex = GDF_32BIT_X888RGB; + pGD->frameAdrs = readl(&dispc->gfx_ba0); + + return pGD; +} +#endif diff --git a/qemu/roms/u-boot/drivers/video/pxa_lcd.c b/qemu/roms/u-boot/drivers/video/pxa_lcd.c new file mode 100644 index 000000000..e19f6ac7d --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/pxa_lcd.c @@ -0,0 +1,625 @@ +/* + * PXA LCD Controller + * + * (C) Copyright 2001-2002 + * Wolfgang Denk, DENX Software Engineering -- wd@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/************************************************************************/ +/* ** HEADER FILES */ +/************************************************************************/ + +#include <config.h> +#include <common.h> +#include <version.h> +#include <stdarg.h> +#include <linux/types.h> +#include <stdio_dev.h> +#include <lcd.h> +#include <asm/arch/pxa-regs.h> +#include <asm/io.h> + +/* #define DEBUG */ + +#ifdef CONFIG_LCD + +/*----------------------------------------------------------------------*/ +/* + * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for + * your display. + */ + +#ifdef CONFIG_PXA_VGA +/* LCD outputs connected to a video DAC */ +# define LCD_BPP LCD_COLOR8 + +/* you have to set lccr0 and lccr3 (including pcd) */ +# define REG_LCCR0 0x003008f8 +# define REG_LCCR3 0x0300FF01 + +/* 640x480x16 @ 61 Hz */ +vidinfo_t panel_info = { + .vl_col = 640, + .vl_row = 480, + .vl_width = 640, + .vl_height = 480, + .vl_clkp = CONFIG_SYS_HIGH, + .vl_oep = CONFIG_SYS_HIGH, + .vl_hsp = CONFIG_SYS_HIGH, + .vl_vsp = CONFIG_SYS_HIGH, + .vl_dp = CONFIG_SYS_HIGH, + .vl_bpix = LCD_BPP, + .vl_lbw = 0, + .vl_splt = 0, + .vl_clor = 0, + .vl_tft = 1, + .vl_hpw = 40, + .vl_blw = 56, + .vl_elw = 56, + .vl_vpw = 20, + .vl_bfw = 8, + .vl_efw = 8, +}; +#endif /* CONFIG_PXA_VIDEO */ + +/*----------------------------------------------------------------------*/ +#ifdef CONFIG_SHARP_LM8V31 + +# define LCD_BPP LCD_COLOR8 +# define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */ + +/* you have to set lccr0 and lccr3 (including pcd) */ +# define REG_LCCR0 0x0030087C +# define REG_LCCR3 0x0340FF08 + +vidinfo_t panel_info = { + .vl_col = 640, + .vl_row = 480, + .vl_width = 157, + .vl_height = 118, + .vl_clkp = CONFIG_SYS_HIGH, + .vl_oep = CONFIG_SYS_HIGH, + .vl_hsp = CONFIG_SYS_HIGH, + .vl_vsp = CONFIG_SYS_HIGH, + .vl_dp = CONFIG_SYS_HIGH, + .vl_bpix = LCD_BPP, + .vl_lbw = 0, + .vl_splt = 1, + .vl_clor = 1, + .vl_tft = 0, + .vl_hpw = 1, + .vl_blw = 3, + .vl_elw = 3, + .vl_vpw = 1, + .vl_bfw = 0, + .vl_efw = 0, +}; +#endif /* CONFIG_SHARP_LM8V31 */ +/*----------------------------------------------------------------------*/ +#ifdef CONFIG_VOIPAC_LCD + +# define LCD_BPP LCD_COLOR8 +# define LCD_INVERT_COLORS + +/* you have to set lccr0 and lccr3 (including pcd) */ +# define REG_LCCR0 0x043008f8 +# define REG_LCCR3 0x0340FF08 + +vidinfo_t panel_info = { + .vl_col = 640, + .vl_row = 480, + .vl_width = 157, + .vl_height = 118, + .vl_clkp = CONFIG_SYS_HIGH, + .vl_oep = CONFIG_SYS_HIGH, + .vl_hsp = CONFIG_SYS_HIGH, + .vl_vsp = CONFIG_SYS_HIGH, + .vl_dp = CONFIG_SYS_HIGH, + .vl_bpix = LCD_BPP, + .vl_lbw = 0, + .vl_splt = 1, + .vl_clor = 1, + .vl_tft = 1, + .vl_hpw = 32, + .vl_blw = 144, + .vl_elw = 32, + .vl_vpw = 2, + .vl_bfw = 13, + .vl_efw = 30, +}; +#endif /* CONFIG_VOIPAC_LCD */ + +/*----------------------------------------------------------------------*/ +#ifdef CONFIG_HITACHI_SX14 +/* Hitachi SX14Q004-ZZA color STN LCD */ +#define LCD_BPP LCD_COLOR8 + +/* you have to set lccr0 and lccr3 (including pcd) */ +#define REG_LCCR0 0x00301079 +#define REG_LCCR3 0x0340FF20 + +vidinfo_t panel_info = { + .vl_col = 320, + .vl_row = 240, + .vl_width = 167, + .vl_height = 109, + .vl_clkp = CONFIG_SYS_HIGH, + .vl_oep = CONFIG_SYS_HIGH, + .vl_hsp = CONFIG_SYS_HIGH, + .vl_vsp = CONFIG_SYS_HIGH, + .vl_dp = CONFIG_SYS_HIGH, + .vl_bpix = LCD_BPP, + .vl_lbw = 1, + .vl_splt = 0, + .vl_clor = 1, + .vl_tft = 0, + .vl_hpw = 1, + .vl_blw = 1, + .vl_elw = 1, + .vl_vpw = 7, + .vl_bfw = 0, + .vl_efw = 0, +}; +#endif /* CONFIG_HITACHI_SX14 */ + +/*----------------------------------------------------------------------*/ +#ifdef CONFIG_LMS283GF05 + +# define LCD_BPP LCD_COLOR8 +/*# define LCD_INVERT_COLORS*/ + +/* you have to set lccr0 and lccr3 (including pcd) */ +# define REG_LCCR0 0x043008f8 +# define REG_LCCR3 0x03b00009 + +vidinfo_t panel_info = { + .vl_col = 240, + .vl_row = 320, + .vl_width = 240, + .vl_height = 320, + .vl_clkp = CONFIG_SYS_HIGH, + .vl_oep = CONFIG_SYS_LOW, + .vl_hsp = CONFIG_SYS_LOW, + .vl_vsp = CONFIG_SYS_LOW, + .vl_dp = CONFIG_SYS_HIGH, + .vl_bpix = LCD_BPP, + .vl_lbw = 0, + .vl_splt = 1, + .vl_clor = 1, + .vl_tft = 1, + .vl_hpw = 4, + .vl_blw = 4, + .vl_elw = 8, + .vl_vpw = 4, + .vl_bfw = 4, + .vl_efw = 8, +}; +#endif /* CONFIG_LMS283GF05 */ + +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_ACX517AKN + +# define LCD_BPP LCD_COLOR8 + +/* you have to set lccr0 and lccr3 (including pcd) */ +# define REG_LCCR0 0x003008f9 +# define REG_LCCR3 0x03700006 + +vidinfo_t panel_info = { + .vl_col = 320, + .vl_row = 320, + .vl_width = 320, + .vl_height = 320, + .vl_clkp = CONFIG_SYS_HIGH, + .vl_oep = CONFIG_SYS_LOW, + .vl_hsp = CONFIG_SYS_LOW, + .vl_vsp = CONFIG_SYS_LOW, + .vl_dp = CONFIG_SYS_HIGH, + .vl_bpix = LCD_BPP, + .vl_lbw = 0, + .vl_splt = 1, + .vl_clor = 1, + .vl_tft = 1, + .vl_hpw = 0x04, + .vl_blw = 0x1c, + .vl_elw = 0x08, + .vl_vpw = 0x01, + .vl_bfw = 0x07, + .vl_efw = 0x08, +}; +#endif /* CONFIG_ACX517AKN */ + +#ifdef CONFIG_ACX544AKN + +# define LCD_BPP LCD_COLOR16 + +/* you have to set lccr0 and lccr3 (including pcd) */ +# define REG_LCCR0 0x003008f9 +# define REG_LCCR3 0x04700007 /* 16bpp */ + +vidinfo_t panel_info = { + .vl_col = 320, + .vl_row = 320, + .vl_width = 320, + .vl_height = 320, + .vl_clkp = CONFIG_SYS_LOW, + .vl_oep = CONFIG_SYS_LOW, + .vl_hsp = CONFIG_SYS_LOW, + .vl_vsp = CONFIG_SYS_LOW, + .vl_dp = CONFIG_SYS_LOW, + .vl_bpix = LCD_BPP, + .vl_lbw = 0, + .vl_splt = 0, + .vl_clor = 1, + .vl_tft = 1, + .vl_hpw = 0x05, + .vl_blw = 0x13, + .vl_elw = 0x08, + .vl_vpw = 0x02, + .vl_bfw = 0x07, + .vl_efw = 0x05, +}; +#endif /* CONFIG_ACX544AKN */ + +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_LQ038J7DH53 + +# define LCD_BPP LCD_COLOR8 + +/* you have to set lccr0 and lccr3 (including pcd) */ +# define REG_LCCR0 0x003008f9 +# define REG_LCCR3 0x03700004 + +vidinfo_t panel_info = { + .vl_col = 320, + .vl_row = 480, + .vl_width = 320, + .vl_height = 480, + .vl_clkp = CONFIG_SYS_HIGH, + .vl_oep = CONFIG_SYS_LOW, + .vl_hsp = CONFIG_SYS_LOW, + .vl_vsp = CONFIG_SYS_LOW, + .vl_dp = CONFIG_SYS_HIGH, + .vl_bpix = LCD_BPP, + .vl_lbw = 0, + .vl_splt = 1, + .vl_clor = 1, + .vl_tft = 1, + .vl_hpw = 0x04, + .vl_blw = 0x20, + .vl_elw = 0x01, + .vl_vpw = 0x01, + .vl_bfw = 0x04, + .vl_efw = 0x01, +}; +#endif /* CONFIG_ACX517AKN */ + +/*----------------------------------------------------------------------*/ + +#ifdef CONFIG_LITTLETON_LCD +# define LCD_BPP LCD_COLOR8 + +/* you have to set lccr0 and lccr3 (including pcd) */ +# define REG_LCCR0 0x003008f8 +# define REG_LCCR3 0x0300FF04 + +vidinfo_t panel_info = { + .vl_col = 480, + .vl_row = 640, + .vl_width = 480, + .vl_height = 640, + .vl_clkp = CONFIG_SYS_HIGH, + .vl_oep = CONFIG_SYS_HIGH, + .vl_hsp = CONFIG_SYS_HIGH, + .vl_vsp = CONFIG_SYS_HIGH, + .vl_dp = CONFIG_SYS_HIGH, + .vl_bpix = LCD_BPP, + .vl_lbw = 0, + .vl_splt = 0, + .vl_clor = 0, + .vl_tft = 1, + .vl_hpw = 9, + .vl_blw = 8, + .vl_elw = 24, + .vl_vpw = 2, + .vl_bfw = 2, + .vl_efw = 4, +}; +#endif /* CONFIG_LITTLETON_LCD */ + +/*----------------------------------------------------------------------*/ + +static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid); +static void pxafb_setup_gpio (vidinfo_t *vid); +static void pxafb_enable_controller (vidinfo_t *vid); +static int pxafb_init (vidinfo_t *vid); + +/************************************************************************/ +/* --------------- PXA chipset specific functions ------------------- */ +/************************************************************************/ + +void lcd_ctrl_init (void *lcdbase) +{ + pxafb_init_mem(lcdbase, &panel_info); + pxafb_init(&panel_info); + pxafb_setup_gpio(&panel_info); + pxafb_enable_controller(&panel_info); +} + +/*----------------------------------------------------------------------*/ +#if LCD_BPP == LCD_COLOR8 +void +lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) +{ + struct pxafb_info *fbi = &panel_info.pxa; + unsigned short *palette = (unsigned short *)fbi->palette; + u_int val; + + if (regno < fbi->palette_size) { + val = ((red << 8) & 0xf800); + val |= ((green << 4) & 0x07e0); + val |= (blue & 0x001f); + +#ifdef LCD_INVERT_COLORS + palette[regno] = ~val; +#else + palette[regno] = val; +#endif + } + + debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n", + regno, &palette[regno], + red, green, blue, + palette[regno]); +} +#endif /* LCD_COLOR8 */ + +/*----------------------------------------------------------------------*/ +#if LCD_BPP == LCD_MONOCHROME +void lcd_initcolregs (void) +{ + struct pxafb_info *fbi = &panel_info.pxa; + cmap = (ushort *)fbi->palette; + ushort regno; + + for (regno = 0; regno < 16; regno++) { + cmap[regno * 2] = 0; + cmap[(regno * 2) + 1] = regno & 0x0f; + } +} +#endif /* LCD_MONOCHROME */ + +/*----------------------------------------------------------------------*/ +__weak void lcd_enable(void) +{ +} + +/************************************************************************/ +/* ** PXA255 specific routines */ +/************************************************************************/ + +/* + * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb, + * descriptors and palette areas. + */ +ulong calc_fbsize (void) +{ + ulong size; + int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; + + size = line_length * panel_info.vl_row; + size += PAGE_SIZE; + + return size; +} + +static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid) +{ + u_long palette_mem_size; + struct pxafb_info *fbi = &vid->pxa; + int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8; + + fbi->screen = (u_long)lcdbase; + + fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16; + palette_mem_size = fbi->palette_size * sizeof(u16); + + debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size); + /* locate palette and descs at end of page following fb */ + fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; + + return 0; +} +#ifdef CONFIG_CPU_MONAHANS +static inline void pxafb_setup_gpio (vidinfo_t *vid) {} +#else +static void pxafb_setup_gpio (vidinfo_t *vid) +{ + u_long lccr0; + + /* + * setup is based on type of panel supported + */ + + lccr0 = vid->pxa.reg_lccr0; + + /* 4 bit interface */ + if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD)) + { + debug("Setting GPIO for 4 bit data\n"); + /* bits 58-61 */ + writel(readl(GPDR1) | (0xf << 26), GPDR1); + writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20), + GAFR1_U); + + /* bits 74-77 */ + writel(readl(GPDR2) | (0xf << 10), GPDR2); + writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20), + GAFR2_L); + } + + /* 8 bit interface */ + else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) || + (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS))) + { + debug("Setting GPIO for 8 bit data\n"); + /* bits 58-65 */ + writel(readl(GPDR1) | (0x3f << 26), GPDR1); + writel(readl(GPDR2) | (0x3), GPDR2); + + writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20), + GAFR1_U); + writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L); + + /* bits 74-77 */ + writel(readl(GPDR2) | (0xf << 10), GPDR2); + writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20), + GAFR2_L); + } + + /* 16 bit interface */ + else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS))) + { + debug("Setting GPIO for 16 bit data\n"); + /* bits 58-77 */ + writel(readl(GPDR1) | (0x3f << 26), GPDR1); + writel(readl(GPDR2) | 0x00003fff, GPDR2); + + writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20), + GAFR1_U); + writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L); + } + else + { + printf("pxafb_setup_gpio: unable to determine bits per pixel\n"); + } +} +#endif + +static void pxafb_enable_controller (vidinfo_t *vid) +{ + debug("Enabling LCD controller\n"); + + /* Sequence from 11.7.10 */ + writel(vid->pxa.reg_lccr3, LCCR3); + writel(vid->pxa.reg_lccr2, LCCR2); + writel(vid->pxa.reg_lccr1, LCCR1); + writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0); + writel(vid->pxa.fdadr0, FDADR0); + writel(vid->pxa.fdadr1, FDADR1); + writel(readl(LCCR0) | LCCR0_ENB, LCCR0); + +#ifdef CONFIG_CPU_MONAHANS + writel(readl(CKENA) | CKENA_1_LCD, CKENA); +#else + writel(readl(CKEN) | CKEN16_LCD, CKEN); +#endif + + debug("FDADR0 = 0x%08x\n", readl(FDADR0)); + debug("FDADR1 = 0x%08x\n", readl(FDADR1)); + debug("LCCR0 = 0x%08x\n", readl(LCCR0)); + debug("LCCR1 = 0x%08x\n", readl(LCCR1)); + debug("LCCR2 = 0x%08x\n", readl(LCCR2)); + debug("LCCR3 = 0x%08x\n", readl(LCCR3)); +} + +static int pxafb_init (vidinfo_t *vid) +{ + struct pxafb_info *fbi = &vid->pxa; + + debug("Configuring PXA LCD\n"); + + fbi->reg_lccr0 = REG_LCCR0; + fbi->reg_lccr3 = REG_LCCR3; + + debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n", + vid->vl_col, vid->vl_hpw, + vid->vl_blw, vid->vl_elw); + debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n", + vid->vl_row, vid->vl_vpw, + vid->vl_bfw, vid->vl_efw); + + fbi->reg_lccr1 = + LCCR1_DisWdth(vid->vl_col) + + LCCR1_HorSnchWdth(vid->vl_hpw) + + LCCR1_BegLnDel(vid->vl_blw) + + LCCR1_EndLnDel(vid->vl_elw); + + fbi->reg_lccr2 = + LCCR2_DisHght(vid->vl_row) + + LCCR2_VrtSnchWdth(vid->vl_vpw) + + LCCR2_BegFrmDel(vid->vl_bfw) + + LCCR2_EndFrmDel(vid->vl_efw); + + fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP); + fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH) + | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH); + + + /* setup dma descriptors */ + fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); + fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); + fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); + + #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \ + (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \ + (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)) + + /* populate descriptors */ + fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow; + fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL; + fbi->dmadesc_fblow->fidr = 0; + fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL; + + fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */ + + fbi->dmadesc_fbhigh->fsadr = fbi->screen; + fbi->dmadesc_fbhigh->fidr = 0; + fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL; + + fbi->dmadesc_palette->fsadr = fbi->palette; + fbi->dmadesc_palette->fidr = 0; + fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL; + + if( NBITS(vid->vl_bpix) < 12) + { + /* assume any mode with <12 bpp is palette driven */ + fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh; + fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette; + /* flips back and forth between pal and fbhigh */ + fbi->fdadr0 = (u_long)fbi->dmadesc_palette; + } + else + { + /* palette shouldn't be loaded in true-color mode */ + fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh; + fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */ + } + + debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow); + debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh); + debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette); + + debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr); + debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr); + debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr); + + debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr); + debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr); + debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr); + + debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd); + debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd); + debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd); + + return 0; +} + +/************************************************************************/ +/************************************************************************/ + +#endif /* CONFIG_LCD */ diff --git a/qemu/roms/u-boot/drivers/video/s6e63d6.c b/qemu/roms/u-boot/drivers/video/s6e63d6.c new file mode 100644 index 000000000..f077260d7 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/s6e63d6.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2009 + * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <spi.h> +#include <s6e63d6.h> + +/* + * Each transfer is performed as: + * 1. chip-select active + * 2. send 8-bit start code + * 3. send 16-bit data + * 4. chip-select inactive + */ +static int send_word(struct s6e63d6 *data, u8 rs, u16 word) +{ + /* + * The start byte looks like (binary): + * 01110<ID><RS><R/W> + * RS is 0 for index or 1 for data, and R/W is 0 for write. + */ + u32 buf8 = 0x70 | data->id | (rs & 2); + u32 buf16 = cpu_to_le16(word); + u32 buf_in; + int err; + + err = spi_xfer(data->slave, 8, &buf8, &buf_in, SPI_XFER_BEGIN); + if (err) + return err; + + return spi_xfer(data->slave, 16, &buf16, &buf_in, SPI_XFER_END); +} + +/* Index and param differ in Register Select bit */ +int s6e63d6_index(struct s6e63d6 *data, u8 idx) +{ + return send_word(data, 0, idx); +} + +int s6e63d6_param(struct s6e63d6 *data, u16 param) +{ + return send_word(data, 2, param); +} + +int s6e63d6_init(struct s6e63d6 *data) +{ + if (data->id != 0 && data->id != 4) { + printf("s6e63d6: invalid ID %u\n", data->id); + return 1; + } + + data->slave = spi_setup_slave(data->bus, data->cs, 100000, SPI_MODE_3); + if (!data->slave) + return 1; + + return 0; +} diff --git a/qemu/roms/u-boot/drivers/video/s6e8ax0.c b/qemu/roms/u-boot/drivers/video/s6e8ax0.c new file mode 100644 index 000000000..84948177e --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/s6e8ax0.c @@ -0,0 +1,265 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * Author: Donghwa Lee <dh09.lee@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/mipi_dsim.h> + +#include "exynos_mipi_dsi_lowlevel.h" +#include "exynos_mipi_dsi_common.h" + +static void s6e8ax0_panel_cond(struct mipi_dsim_device *dsim_dev) +{ + struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + int reverse = dsim_dev->dsim_lcd_dev->reverse_panel; + static const unsigned char data_to_send[] = { + 0xf8, 0x3d, 0x35, 0x00, 0x00, 0x00, 0x8d, 0x00, 0x4c, + 0x6e, 0x10, 0x27, 0x7d, 0x3f, 0x10, 0x00, 0x00, 0x20, + 0x04, 0x08, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x08, 0x08, + 0x23, 0x23, 0xc0, 0xc8, 0x08, 0x48, 0xc1, 0x00, 0xc3, + 0xff, 0xff, 0xc8 + }; + + static const unsigned char data_to_send_reverse[] = { + 0xf8, 0x19, 0x35, 0x00, 0x00, 0x00, 0x93, 0x00, 0x3c, + 0x7d, 0x08, 0x27, 0x7d, 0x3f, 0x00, 0x00, 0x00, 0x20, + 0x04, 0x08, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x08, 0x08, + 0x23, 0x23, 0xc0, 0xc1, 0x01, 0x41, 0xc1, 0x00, 0xc1, + 0xf6, 0xf6, 0xc1 + }; + + if (reverse) { + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, + data_to_send_reverse, + ARRAY_SIZE(data_to_send_reverse)); + } else { + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, + data_to_send, ARRAY_SIZE(data_to_send)); + } +} + +static void s6e8ax0_display_cond(struct mipi_dsim_device *dsim_dev) +{ + struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0xf2, 0x80, 0x03, 0x0d + }; + + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, + data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void s6e8ax0_gamma_cond(struct mipi_dsim_device *dsim_dev) +{ + struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + /* 7500K 2.2 Set : 30cd */ + static const unsigned char data_to_send[] = { + 0xfa, 0x01, 0x60, 0x10, 0x60, 0xf5, 0x00, 0xff, 0xad, + 0xaf, 0xba, 0xc3, 0xd8, 0xc5, 0x9f, 0xc6, 0x9e, 0xc1, + 0xdc, 0xc0, 0x00, 0x61, 0x00, 0x5a, 0x00, 0x74, + }; + + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, + data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void s6e8ax0_gamma_update(struct mipi_dsim_device *dsim_dev) +{ + struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0xf7, 0x03 + }; + + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send, + ARRAY_SIZE(data_to_send)); +} + +static void s6e8ax0_etc_source_control(struct mipi_dsim_device *dsim_dev) +{ + struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0xf6, 0x00, 0x02, 0x00 + }; + + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, + data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void s6e8ax0_etc_pentile_control(struct mipi_dsim_device *dsim_dev) +{ + struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0xb6, 0x0c, 0x02, 0x03, 0x32, 0xff, 0x44, 0x44, 0xc0, + 0x00 + }; + + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, + data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void s6e8ax0_etc_mipi_control1(struct mipi_dsim_device *dsim_dev) +{ + struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0xe1, 0x10, 0x1c, 0x17, 0x08, 0x1d + }; + + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, + data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void s6e8ax0_etc_mipi_control2(struct mipi_dsim_device *dsim_dev) +{ + struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0xe2, 0xed, 0x07, 0xc3, 0x13, 0x0d, 0x03 + }; + + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, + data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void s6e8ax0_etc_power_control(struct mipi_dsim_device *dsim_dev) +{ + struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0xf4, 0xcf, 0x0a, 0x12, 0x10, 0x19, 0x33, 0x02 + }; + + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, + data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void s6e8ax0_etc_mipi_control3(struct mipi_dsim_device *dsim_dev) +{ + struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0xe3, 0x40 + }; + + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send, + ARRAY_SIZE(data_to_send)); +} + +static void s6e8ax0_etc_mipi_control4(struct mipi_dsim_device *dsim_dev) +{ + struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0xe4, 0x00, 0x00, 0x14, 0x80, 0x00, 0x00, 0x00 + }; + + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, + data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void s6e8ax0_elvss_set(struct mipi_dsim_device *dsim_dev) +{ + struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0xb1, 0x04, 0x00 + }; + + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, + data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void s6e8ax0_display_on(struct mipi_dsim_device *dsim_dev) +{ + struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0x29, 0x00 + }; + + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send, + ARRAY_SIZE(data_to_send)); +} + +static void s6e8ax0_sleep_out(struct mipi_dsim_device *dsim_dev) +{ + struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0x11, 0x00 + }; + + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send, + ARRAY_SIZE(data_to_send)); +} + +static void s6e8ax0_apply_level1_key(struct mipi_dsim_device *dsim_dev) +{ + struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0xf0, 0x5a, 0x5a + }; + + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, + data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void s6e8ax0_apply_mtp_key(struct mipi_dsim_device *dsim_dev) +{ + struct mipi_dsim_master_ops *ops = dsim_dev->master_ops; + static const unsigned char data_to_send[] = { + 0xf1, 0x5a, 0x5a + }; + + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE, + data_to_send, ARRAY_SIZE(data_to_send)); +} + +static void s6e8ax0_panel_init(struct mipi_dsim_device *dsim_dev) +{ + /* + * in case of setting gamma and panel condition at first, + * it shuold be setting like below. + * set_gamma() -> set_panel_condition() + */ + + s6e8ax0_apply_level1_key(dsim_dev); + s6e8ax0_apply_mtp_key(dsim_dev); + + s6e8ax0_sleep_out(dsim_dev); + mdelay(5); + s6e8ax0_panel_cond(dsim_dev); + s6e8ax0_display_cond(dsim_dev); + s6e8ax0_gamma_cond(dsim_dev); + s6e8ax0_gamma_update(dsim_dev); + + s6e8ax0_etc_source_control(dsim_dev); + s6e8ax0_elvss_set(dsim_dev); + s6e8ax0_etc_pentile_control(dsim_dev); + s6e8ax0_etc_mipi_control1(dsim_dev); + s6e8ax0_etc_mipi_control2(dsim_dev); + s6e8ax0_etc_power_control(dsim_dev); + s6e8ax0_etc_mipi_control3(dsim_dev); + s6e8ax0_etc_mipi_control4(dsim_dev); +} + +static int s6e8ax0_panel_set(struct mipi_dsim_device *dsim_dev) +{ + s6e8ax0_panel_init(dsim_dev); + + return 0; +} + +static void s6e8ax0_display_enable(struct mipi_dsim_device *dsim_dev) +{ + s6e8ax0_display_on(dsim_dev); +} + +static struct mipi_dsim_lcd_driver s6e8ax0_dsim_ddi_driver = { + .name = "s6e8ax0", + .id = -1, + + .mipi_panel_init = s6e8ax0_panel_set, + .mipi_display_on = s6e8ax0_display_enable, +}; + +void s6e8ax0_init(void) +{ + exynos_mipi_dsi_register_lcd_driver(&s6e8ax0_dsim_ddi_driver); +} diff --git a/qemu/roms/u-boot/drivers/video/sandbox_sdl.c b/qemu/roms/u-boot/drivers/video/sandbox_sdl.c new file mode 100644 index 000000000..ba4578e9d --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/sandbox_sdl.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2013 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <lcd.h> +#include <malloc.h> +#include <asm/sdl.h> +#include <asm/u-boot-sandbox.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum { + /* Maximum LCD size we support */ + LCD_MAX_WIDTH = 1366, + LCD_MAX_HEIGHT = 768, + LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */ +}; + +vidinfo_t panel_info; + +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ +} + +void lcd_ctrl_init(void *lcdbase) +{ + /* + * Allocate memory to keep BMP color conversion map. This is required + * for 8 bit BMPs only (hence 256 colors). If malloc fails - keep + * going, it is not even clear if displyaing the bitmap will be + * required on the way up. + */ + panel_info.cmap = malloc(256 * NBITS(panel_info.vl_bpix) / 8); +} + +void lcd_enable(void) +{ + if (sandbox_sdl_init_display(panel_info.vl_col, panel_info.vl_row, + panel_info.vl_bpix)) + puts("LCD init failed\n"); +} + +int sandbox_lcd_sdl_early_init(void) +{ + const void *blob = gd->fdt_blob; + int xres = LCD_MAX_WIDTH, yres = LCD_MAX_HEIGHT; + int node; + int ret = 0; + + /* + * The code in common/lcd.c does not cope with not being able to + * set up a frame buffer. It will just happily keep writing to + * invalid memory. So here we make sure that at least some buffer + * is available even if it actually won't be displayed. + */ + node = fdtdec_next_compatible(blob, 0, COMPAT_SANDBOX_LCD_SDL); + if (node >= 0) { + xres = fdtdec_get_int(blob, node, "xres", LCD_MAX_WIDTH); + yres = fdtdec_get_int(blob, node, "yres", LCD_MAX_HEIGHT); + if (xres < 0 || xres > LCD_MAX_WIDTH) { + xres = LCD_MAX_WIDTH; + ret = -EINVAL; + } + if (yres < 0 || yres > LCD_MAX_HEIGHT) { + yres = LCD_MAX_HEIGHT; + ret = -EINVAL; + } + } + + panel_info.vl_col = xres; + panel_info.vl_row = yres; + panel_info.vl_bpix = LCD_COLOR16; + + return ret; +} diff --git a/qemu/roms/u-boot/drivers/video/scf0403_lcd.c b/qemu/roms/u-boot/drivers/video/scf0403_lcd.c new file mode 100644 index 000000000..2bc8bcae8 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/scf0403_lcd.c @@ -0,0 +1,296 @@ +/* + * scf0403.c -- support for DataImage SCF0403 LCD + * + * Copyright (c) 2013 Adapted from Linux driver: + * Copyright (c) 2012 Anders Electronics plc. All Rights Reserved. + * Copyright (c) 2012 CompuLab, Ltd + * Dmitry Lifshitz <lifshitz@compulab.co.il> + * Ilya Ledvich <ilya@compulab.co.il> + * Inspired by Alberto Panizzo <maramaopercheseimorto@gmail.com> & + * Marek Vasut work in l4f00242t03.c + * + * U-Boot port: Nikita Kiryanov <nikita@compulab.co.il> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/gpio.h> +#include <spi.h> + +struct scf0403_cmd { + u16 cmd; + u16 *params; + int count; +}; + +struct scf0403_initseq_entry { + struct scf0403_cmd cmd; + int delay_ms; +}; + +struct scf0403_priv { + struct spi_slave *spi; + unsigned int reset_gpio; + u32 rddid; + struct scf0403_initseq_entry *init_seq; + int seq_size; +}; + +struct scf0403_priv priv; + +#define SCF0403852GGU04_ID 0x000080 + +/* SCF0403526GGU20 model commands parameters */ +static u16 extcmd_params_sn20[] = {0xff, 0x98, 0x06}; +static u16 spiinttype_params_sn20[] = {0x60}; +static u16 bc_params_sn20[] = { + 0x01, 0x10, 0x61, 0x74, 0x01, 0x01, 0x1B, + 0x12, 0x71, 0x00, 0x00, 0x00, 0x01, 0x01, + 0x05, 0x00, 0xFF, 0xF2, 0x01, 0x00, 0x40, +}; +static u16 bd_params_sn20[] = {0x01, 0x23, 0x45, 0x67, 0x01, 0x23, 0x45, 0x67}; +static u16 be_params_sn20[] = { + 0x01, 0x22, 0x22, 0xBA, 0xDC, 0x26, 0x28, 0x22, 0x22, +}; +static u16 vcom_params_sn20[] = {0x74}; +static u16 vmesur_params_sn20[] = {0x7F, 0x0F, 0x00}; +static u16 powerctl_params_sn20[] = {0x03, 0x0b, 0x00}; +static u16 lvglvolt_params_sn20[] = {0x08}; +static u16 engsetting_params_sn20[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x20}; +static u16 dispfunc_params_sn20[] = {0xa0}; +static u16 dvddvolt_params_sn20[] = {0x74}; +static u16 dispinv_params_sn20[] = {0x00, 0x00, 0x00}; +static u16 panelres_params_sn20[] = {0x82}; +static u16 framerate_params_sn20[] = {0x00, 0x13, 0x13}; +static u16 timing_params_sn20[] = {0x80, 0x05, 0x40, 0x28}; +static u16 powerctl2_params_sn20[] = {0x17, 0x75, 0x79, 0x20}; +static u16 memaccess_params_sn20[] = {0x00}; +static u16 pixfmt_params_sn20[] = {0x66}; +static u16 pgamma_params_sn20[] = { + 0x00, 0x03, 0x0b, 0x0c, 0x0e, 0x08, 0xc5, 0x04, + 0x08, 0x0c, 0x13, 0x11, 0x11, 0x14, 0x0c, 0x10, +}; +static u16 ngamma_params_sn20[] = { + 0x00, 0x0d, 0x11, 0x0c, 0x0c, 0x04, 0x76, 0x03, + 0x08, 0x0b, 0x16, 0x10, 0x0d, 0x16, 0x0a, 0x00, +}; +static u16 tearing_params_sn20[] = {0x00}; + +/* SCF0403852GGU04 model commands parameters */ +static u16 memaccess_params_sn04[] = {0x08}; +static u16 pixfmt_params_sn04[] = {0x66}; +static u16 modectl_params_sn04[] = {0x01}; +static u16 dispfunc_params_sn04[] = {0x22, 0xe2, 0xFF, 0x04}; +static u16 vcom_params_sn04[] = {0x00, 0x6A}; +static u16 pgamma_params_sn04[] = { + 0x00, 0x07, 0x0d, 0x10, 0x13, 0x19, 0x0f, 0x0c, + 0x05, 0x08, 0x06, 0x13, 0x0f, 0x30, 0x20, 0x1f, +}; +static u16 ngamma_params_sn04[] = { + 0x1F, 0x20, 0x30, 0x0F, 0x13, 0x06, 0x08, 0x05, + 0x0C, 0x0F, 0x19, 0x13, 0x10, 0x0D, 0x07, 0x00, +}; +static u16 dispinv_params_sn04[] = {0x02}; + +/* Common commands */ +static struct scf0403_cmd scf0403_cmd_slpout = {0x11, NULL, 0}; +static struct scf0403_cmd scf0403_cmd_dison = {0x29, NULL, 0}; + +/* SCF0403852GGU04 init sequence */ +static struct scf0403_initseq_entry scf0403_initseq_sn04[] = { + {{0x36, memaccess_params_sn04, ARRAY_SIZE(memaccess_params_sn04)}, 0}, + {{0x3A, pixfmt_params_sn04, ARRAY_SIZE(pixfmt_params_sn04)}, 0}, + {{0xB6, dispfunc_params_sn04, ARRAY_SIZE(dispfunc_params_sn04)}, 0}, + {{0xC5, vcom_params_sn04, ARRAY_SIZE(vcom_params_sn04)}, 0}, + {{0xE0, pgamma_params_sn04, ARRAY_SIZE(pgamma_params_sn04)}, 0}, + {{0xE1, ngamma_params_sn04, ARRAY_SIZE(ngamma_params_sn04)}, 20}, + {{0xB0, modectl_params_sn04, ARRAY_SIZE(modectl_params_sn04)}, 0}, + {{0xB4, dispinv_params_sn04, ARRAY_SIZE(dispinv_params_sn04)}, 100}, +}; + +/* SCF0403526GGU20 init sequence */ +static struct scf0403_initseq_entry scf0403_initseq_sn20[] = { + {{0xff, extcmd_params_sn20, ARRAY_SIZE(extcmd_params_sn20)}, 0}, + {{0xba, spiinttype_params_sn20, ARRAY_SIZE(spiinttype_params_sn20)}, 0}, + {{0xbc, bc_params_sn20, ARRAY_SIZE(bc_params_sn20)}, 0}, + {{0xbd, bd_params_sn20, ARRAY_SIZE(bd_params_sn20)}, 0}, + {{0xbe, be_params_sn20, ARRAY_SIZE(be_params_sn20)}, 0}, + {{0xc7, vcom_params_sn20, ARRAY_SIZE(vcom_params_sn20)}, 0}, + {{0xed, vmesur_params_sn20, ARRAY_SIZE(vmesur_params_sn20)}, 0}, + {{0xc0, powerctl_params_sn20, ARRAY_SIZE(powerctl_params_sn20)}, 0}, + {{0xfc, lvglvolt_params_sn20, ARRAY_SIZE(lvglvolt_params_sn20)}, 0}, + {{0xb6, dispfunc_params_sn20, ARRAY_SIZE(dispfunc_params_sn20)}, 0}, + {{0xdf, engsetting_params_sn20, ARRAY_SIZE(engsetting_params_sn20)}, 0}, + {{0xf3, dvddvolt_params_sn20, ARRAY_SIZE(dvddvolt_params_sn20)}, 0}, + {{0xb4, dispinv_params_sn20, ARRAY_SIZE(dispinv_params_sn20)}, 0}, + {{0xf7, panelres_params_sn20, ARRAY_SIZE(panelres_params_sn20)}, 0}, + {{0xb1, framerate_params_sn20, ARRAY_SIZE(framerate_params_sn20)}, 0}, + {{0xf2, timing_params_sn20, ARRAY_SIZE(timing_params_sn20)}, 0}, + {{0xc1, powerctl2_params_sn20, ARRAY_SIZE(powerctl2_params_sn20)}, 0}, + {{0x36, memaccess_params_sn20, ARRAY_SIZE(memaccess_params_sn20)}, 0}, + {{0x3a, pixfmt_params_sn20, ARRAY_SIZE(pixfmt_params_sn20)}, 0}, + {{0xe0, pgamma_params_sn20, ARRAY_SIZE(pgamma_params_sn20)}, 0}, + {{0xe1, ngamma_params_sn20, ARRAY_SIZE(ngamma_params_sn20)}, 0}, + {{0x35, tearing_params_sn20, ARRAY_SIZE(tearing_params_sn20)}, 0}, +}; + +static void scf0403_gpio_reset(unsigned int gpio) +{ + if (!gpio_is_valid(gpio)) + return; + + gpio_set_value(gpio, 1); + mdelay(100); + gpio_set_value(gpio, 0); + mdelay(40); + gpio_set_value(gpio, 1); + mdelay(100); +} + +static int scf0403_spi_read_rddid(struct spi_slave *spi, u32 *rddid) +{ + int error = 0; + u8 ids_buf = 0x00; + u16 dummy_buf = 0x00; + u16 cmd = 0x04; + + error = spi_set_wordlen(spi, 9); + if (error) + return error; + + /* Here 9 bits required to transmit a command */ + error = spi_xfer(spi, 9, &cmd, NULL, SPI_XFER_ONCE); + if (error) + return error; + + /* + * Here 8 + 1 bits required to arrange extra clock cycle + * before the first data bit. + * According to the datasheet - first parameter is the dummy data. + */ + error = spi_xfer(spi, 9, NULL, &dummy_buf, SPI_XFER_ONCE); + if (error) + return error; + + error = spi_set_wordlen(spi, 8); + if (error) + return error; + + /* Read rest of the data */ + error = spi_xfer(spi, 8, NULL, &ids_buf, SPI_XFER_ONCE); + if (error) + return error; + + *rddid = ids_buf; + + return 0; +} + +static int scf0403_spi_transfer(struct spi_slave *spi, struct scf0403_cmd *cmd) +{ + int i, error; + u32 command = cmd->cmd; + u32 msg; + + error = spi_set_wordlen(spi, 9); + if (error) + return error; + + error = spi_xfer(spi, 9, &command, NULL, SPI_XFER_ONCE); + if (error) + return error; + + for (i = 0; i < cmd->count; i++) { + msg = (cmd->params[i] | 0x100); + error = spi_xfer(spi, 9, &msg, NULL, SPI_XFER_ONCE); + if (error) + return error; + } + + return 0; +} + +static void scf0403_lcd_init(struct scf0403_priv *priv) +{ + int i; + + /* reset LCD */ + scf0403_gpio_reset(priv->reset_gpio); + + for (i = 0; i < priv->seq_size; i++) { + if (scf0403_spi_transfer(priv->spi, &priv->init_seq[i].cmd) < 0) + puts("SPI transfer failed\n"); + + mdelay(priv->init_seq[i].delay_ms); + } +} + +static int scf0403_request_reset_gpio(unsigned gpio) +{ + int err = gpio_request(gpio, "lcd reset"); + + if (err) + return err; + + err = gpio_direction_output(gpio, 0); + if (err) + gpio_free(gpio); + + return err; +} + +int scf0403_init(int reset_gpio) +{ + int error; + + if (gpio_is_valid(reset_gpio)) { + error = scf0403_request_reset_gpio(reset_gpio); + if (error) { + printf("Failed requesting reset GPIO%d: %d\n", + reset_gpio, error); + return error; + } + } + + priv.reset_gpio = reset_gpio; + priv.spi = spi_setup_slave(3, 0, 1000000, SPI_MODE_0); + error = spi_claim_bus(priv.spi); + if (error) + goto bus_claim_fail; + + /* reset LCD */ + scf0403_gpio_reset(reset_gpio); + + error = scf0403_spi_read_rddid(priv.spi, &priv.rddid); + if (error) { + puts("IDs read failed\n"); + goto readid_fail; + } + + if (priv.rddid == SCF0403852GGU04_ID) { + priv.init_seq = scf0403_initseq_sn04; + priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn04); + } else { + priv.init_seq = scf0403_initseq_sn20; + priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn20); + } + + scf0403_lcd_init(&priv); + + /* Start operation */ + scf0403_spi_transfer(priv.spi, &scf0403_cmd_dison); + mdelay(100); + scf0403_spi_transfer(priv.spi, &scf0403_cmd_slpout); + spi_release_bus(priv.spi); + + return 0; + +readid_fail: + spi_release_bus(priv.spi); +bus_claim_fail: + if (gpio_is_valid(priv.reset_gpio)) + gpio_free(priv.reset_gpio); + + return error; +} diff --git a/qemu/roms/u-boot/drivers/video/sed13806.c b/qemu/roms/u-boot/drivers/video/sed13806.c new file mode 100644 index 000000000..da653c0f5 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/sed13806.c @@ -0,0 +1,291 @@ +/* + * (C) Copyright 2002 + * Stäubli Faverges - <www.staubli.com> + * Pierre AUBERT p.aubert@staubli.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/* Video support for Epson SED13806 chipset */ + +#include <common.h> + +#include <video_fb.h> +#include <sed13806.h> + +#define readByte(ptrReg) \ + *(volatile unsigned char *)(sed13806.isaBase + ptrReg) + +#define writeByte(ptrReg,value) \ + *(volatile unsigned char *)(sed13806.isaBase + ptrReg) = value + +#ifdef CONFIG_TOTAL5200 +#define writeWord(ptrReg,value) \ + (*(volatile unsigned short *)(sed13806.isaBase + ptrReg) = value) +#else +#define writeWord(ptrReg,value) \ + (*(volatile unsigned short *)(sed13806.isaBase + ptrReg) = ((value >> 8 ) & 0xff) | ((value << 8) & 0xff00)) +#endif + +GraphicDevice sed13806; + +/*----------------------------------------------------------------------------- + * EpsonSetRegs -- + *----------------------------------------------------------------------------- + */ +static void EpsonSetRegs (void) +{ + /* the content of the chipset register depends on the board (clocks, ...)*/ + const S1D_REGS *preg = board_get_regs (); + while (preg -> Index) { + writeByte (preg -> Index, preg -> Value); + preg ++; + } +} + +/*----------------------------------------------------------------------------- + * video_hw_init -- + *----------------------------------------------------------------------------- + */ +void *video_hw_init (void) +{ + unsigned int *vm, i; + + memset (&sed13806, 0, sizeof (GraphicDevice)); + + /* Initialization of the access to the graphic chipset + Retreive base address of the chipset + (see board/RPXClassic/eccx.c) */ + if ((sed13806.isaBase = board_video_init ()) == 0) { + return (NULL); + } + + sed13806.frameAdrs = sed13806.isaBase + FRAME_BUFFER_OFFSET; + sed13806.winSizeX = board_get_width (); + sed13806.winSizeY = board_get_height (); + +#if defined(CONFIG_VIDEO_SED13806_8BPP) + sed13806.gdfIndex = GDF__8BIT_INDEX; + sed13806.gdfBytesPP = 1; + +#elif defined(CONFIG_VIDEO_SED13806_16BPP) + sed13806.gdfIndex = GDF_16BIT_565RGB; + sed13806.gdfBytesPP = 2; + +#else +#error Unsupported SED13806 BPP +#endif + + sed13806.memSize = sed13806.winSizeX * sed13806.winSizeY * sed13806.gdfBytesPP; + + /* Load SED registers */ + EpsonSetRegs (); + + /* (see board/RPXClassic/RPXClassic.c) */ + board_validate_screen (sed13806.isaBase); + + /* Clear video memory */ + i = sed13806.memSize/4; + vm = (unsigned int *)sed13806.frameAdrs; + while(i--) + *vm++ = 0; + + + return (&sed13806); +} +/*----------------------------------------------------------------------------- + * Epson_wait_idle -- Wait for hardware to become idle + *----------------------------------------------------------------------------- + */ +static void Epson_wait_idle (void) +{ + while (readByte (BLT_CTRL0) & 0x80); + + /* Read a word in the BitBLT memory area to shutdown the BitBLT engine */ + *(volatile unsigned short *)(sed13806.isaBase + BLT_REG); +} + +/*----------------------------------------------------------------------------- + * video_hw_bitblt -- + *----------------------------------------------------------------------------- + */ +void video_hw_bitblt ( + unsigned int bpp, /* bytes per pixel */ + unsigned int src_x, /* source pos x */ + unsigned int src_y, /* source pos y */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y /* frame height */ + ) +{ + register GraphicDevice *pGD = (GraphicDevice *)&sed13806; + unsigned long srcAddr, dstAddr; + unsigned int stride = bpp * pGD -> winSizeX; + + srcAddr = (src_y * stride) + (src_x * bpp); + dstAddr = (dst_y * stride) + (dst_x * bpp); + + Epson_wait_idle (); + + writeByte(BLT_ROP,0x0C); /* source */ + writeByte(BLT_OP,0x02);/* move blit in positive direction with ROP */ + writeWord(BLT_MEM_OFF0, stride / 2); + if (pGD -> gdfIndex == GDF__8BIT_INDEX) { + writeByte(BLT_CTRL1,0x00); + } + else { + writeByte(BLT_CTRL1,0x01); + } + + writeWord(BLT_WIDTH0,(dim_x - 1)); + writeWord(BLT_HEIGHT0,(dim_y - 1)); + + /* set up blit registers */ + writeByte(BLT_SRC_ADDR0,srcAddr); + writeByte(BLT_SRC_ADDR1,srcAddr>>8); + writeByte(BLT_SRC_ADDR2,srcAddr>>16); + + writeByte(BLT_DST_ADDR0,dstAddr); + writeByte(BLT_DST_ADDR1,dstAddr>>8); + writeByte(BLT_DST_ADDR2,dstAddr>>16); + + /* Engage the blt engine */ + /* rectangular region for src and dst */ + writeByte(BLT_CTRL0,0x80); + + /* wait untill current blits finished */ + Epson_wait_idle (); +} +/*----------------------------------------------------------------------------- + * video_hw_rectfill -- + *----------------------------------------------------------------------------- + */ +void video_hw_rectfill ( + unsigned int bpp, /* bytes per pixel */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y, /* frame height */ + unsigned int color /* fill color */ + ) +{ + register GraphicDevice *pGD = (GraphicDevice *)&sed13806; + unsigned long dstAddr; + unsigned int stride = bpp * pGD -> winSizeX; + + dstAddr = (dst_y * stride) + (dst_x * bpp); + + Epson_wait_idle (); + + /* set up blit registers */ + writeByte(BLT_DST_ADDR0,dstAddr); + writeByte(BLT_DST_ADDR1,dstAddr>>8); + writeByte(BLT_DST_ADDR2,dstAddr>>16); + + writeWord(BLT_WIDTH0,(dim_x - 1)); + writeWord(BLT_HEIGHT0,(dim_y - 1)); + writeWord(BLT_FGCOLOR0,color); + + writeByte(BLT_OP,0x0C); /* solid fill */ + writeWord(BLT_MEM_OFF0,stride / 2); + + if (pGD -> gdfIndex == GDF__8BIT_INDEX) { + writeByte(BLT_CTRL1,0x00); + } + else { + writeByte(BLT_CTRL1,0x01); + } + + /* Engage the blt engine */ + /* rectangular region for src and dst */ + writeByte(BLT_CTRL0,0x80); + + /* wait untill current blits finished */ + Epson_wait_idle (); +} + +/*----------------------------------------------------------------------------- + * video_set_lut -- + *----------------------------------------------------------------------------- + */ +void video_set_lut ( + unsigned int index, /* color number */ + unsigned char r, /* red */ + unsigned char g, /* green */ + unsigned char b /* blue */ + ) +{ + writeByte(REG_LUT_ADDR, index ); + writeByte(REG_LUT_DATA, r); + writeByte(REG_LUT_DATA, g); + writeByte(REG_LUT_DATA, b); +} +#ifdef CONFIG_VIDEO_HW_CURSOR +/*----------------------------------------------------------------------------- + * video_set_hw_cursor -- + *----------------------------------------------------------------------------- + */ +void video_set_hw_cursor (int x, int y) +{ + writeByte (LCD_CURSOR_XL, (x & 0xff)); + writeByte (LCD_CURSOR_XM, (x >> 8)); + writeByte (LCD_CURSOR_YL, (y & 0xff)); + writeByte (LCD_CURSOR_YM, (y >> 8)); +} + +/*----------------------------------------------------------------------------- + * video_init_hw_cursor -- + *----------------------------------------------------------------------------- + */ +void video_init_hw_cursor (int font_width, int font_height) +{ + volatile unsigned char *ptr; + unsigned char pattern; + int i; + + + /* Init cursor content + Cursor size is 64x64 pixels + Start of the cursor memory depends on panel type (dual panel ...) */ + if ((i = readByte (LCD_CURSOR_START)) == 0) { + ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - HWCURSORSIZE); + } + else { + ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - (i * 8192)); + } + + /* Fill the first line and the first empty line after cursor */ + for (i = 0, pattern = 0; i < 64; i++) { + if (i < font_width) { + /* Invert background */ + pattern |= 0x3; + + } + else { + /* Background */ + pattern |= 0x2; + } + if ((i & 3) == 3) { + *ptr = pattern; + *(ptr + font_height * 16) = 0xaa; + ptr ++; + pattern = 0; + } + pattern <<= 2; + } + + /* Duplicate this line */ + for (i = 1; i < font_height; i++) { + memcpy ((void *)ptr, (void *)(ptr - 16), 16); + ptr += 16; + } + + for (; i < 64; i++) { + memcpy ((void *)(ptr + 16), (void *)ptr, 16); + ptr += 16; + } + + /* Select cursor mode */ + writeByte (LCD_CURSOR_CNTL, 1); +} +#endif diff --git a/qemu/roms/u-boot/drivers/video/sed156x.c b/qemu/roms/u-boot/drivers/video/sed156x.c new file mode 100644 index 000000000..2c906ecf1 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/sed156x.c @@ -0,0 +1,546 @@ +/* + * (C) Copyright 2003 + * + * Pantelis Antoniou <panto@intracom.gr> + * Intracom S.A. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <watchdog.h> + +#include <sed156x.h> + +/* configure according to the selected display */ +#if defined(CONFIG_SED156X_PG12864Q) +#define LCD_WIDTH 128 +#define LCD_HEIGHT 64 +#define LCD_LINES 64 +#define LCD_PAGES 9 +#define LCD_COLUMNS 132 +#else +#error Unsupported SED156x configuration +#endif + +/* include the font data */ +#include <video_font.h> + +#if VIDEO_FONT_WIDTH != 8 || VIDEO_FONT_HEIGHT != 16 +#error Expecting VIDEO_FONT_WIDTH == 8 && VIDEO_FONT_HEIGHT == 16 +#endif + +#define LCD_BYTE_WIDTH (LCD_WIDTH / 8) +#define VIDEO_FONT_BYTE_WIDTH (VIDEO_FONT_WIDTH / 8) + +#define LCD_TEXT_WIDTH (LCD_WIDTH / VIDEO_FONT_WIDTH) +#define LCD_TEXT_HEIGHT (LCD_HEIGHT / VIDEO_FONT_HEIGHT) + +#define LCD_BYTE_LINESZ (LCD_BYTE_WIDTH * VIDEO_FONT_HEIGHT) + +const int sed156x_text_width = LCD_TEXT_WIDTH; +const int sed156x_text_height = LCD_TEXT_HEIGHT; + +/**************************************************************************************/ + +#define SED156X_SPI_RXD() (SED156X_SPI_RXD_PORT & SED156X_SPI_RXD_MASK) + +#define SED156X_SPI_TXD(x) \ + do { \ + if (x) \ + SED156X_SPI_TXD_PORT |= SED156X_SPI_TXD_MASK; \ + else \ + SED156X_SPI_TXD_PORT &= ~SED156X_SPI_TXD_MASK; \ + } while(0) + +#define SED156X_SPI_CLK(x) \ + do { \ + if (x) \ + SED156X_SPI_CLK_PORT |= SED156X_SPI_CLK_MASK; \ + else \ + SED156X_SPI_CLK_PORT &= ~SED156X_SPI_CLK_MASK; \ + } while(0) + +#define SED156X_SPI_CLK_TOGGLE() (SED156X_SPI_CLK_PORT ^= SED156X_SPI_CLK_MASK) + +#define SED156X_SPI_BIT_DELAY() /* no delay */ + +#define SED156X_CS(x) \ + do { \ + if (x) \ + SED156X_CS_PORT |= SED156X_CS_MASK; \ + else \ + SED156X_CS_PORT &= ~SED156X_CS_MASK; \ + } while(0) + +#define SED156X_A0(x) \ + do { \ + if (x) \ + SED156X_A0_PORT |= SED156X_A0_MASK; \ + else \ + SED156X_A0_PORT &= ~SED156X_A0_MASK; \ + } while(0) + +/**************************************************************************************/ + +/*** LCD Commands ***/ + +#define LCD_ON 0xAF /* Display ON */ +#define LCD_OFF 0xAE /* Display OFF */ +#define LCD_LADDR 0x40 /* Display start line set + (6-bit) address */ +#define LCD_PADDR 0xB0 /* Page address set + (4-bit) page */ +#define LCD_CADRH 0x10 /* Column address set upper + (4-bit) column hi */ +#define LCD_CADRL 0x00 /* Column address set lower + (4-bit) column lo */ +#define LCD_ADC_NRM 0xA0 /* ADC select Normal */ +#define LCD_ADC_REV 0xA1 /* ADC select Reverse */ +#define LCD_DSP_NRM 0xA6 /* LCD display Normal */ +#define LCD_DSP_REV 0xA7 /* LCD display Reverse */ +#define LCD_DPT_NRM 0xA4 /* Display all points Normal */ +#define LCD_DPT_ALL 0xA5 /* Display all points ON */ +#define LCD_BIAS9 0xA2 /* LCD bias set 1/9 */ +#define LCD_BIAS7 0xA3 /* LCD bias set 1/7 */ +#define LCD_CAINC 0xE0 /* Read/modify/write */ +#define LCD_CAEND 0xEE /* End */ +#define LCD_RESET 0xE2 /* Reset */ +#define LCD_C_NRM 0xC0 /* Common output mode select Normal direction */ +#define LCD_C_RVS 0xC8 /* Common output mode select Reverse direction */ +#define LCD_PWRMD 0x28 /* Power control set + (3-bit) mode */ +#define LCD_RESRT 0x20 /* V5 v. reg. int. resistor ratio set + (3-bit) ratio */ +#define LCD_EVSET 0x81 /* Electronic volume mode set + byte = (6-bit) volume */ +#define LCD_SIOFF 0xAC /* Static indicator OFF */ +#define LCD_SION 0xAD /* Static indicator ON + byte = (2-bit) mode */ +#define LCD_NOP 0xE3 /* NOP */ +#define LCD_TEST 0xF0 /* Test/Test mode reset (Note: *DO NOT USE*) */ + +/*------------------------------------------------------------------------------- + Compound commands + ------------------------------------------------------------------------------- + Command Description Commands + ---------- ------------------------ ------------------------------------- + POWS_ON POWER SAVER ON command LCD_OFF, LCD_D_ALL + POWS_OFF POWER SAVER OFF command LCD_D_NRM + SLEEPON SLEEP mode LCD_SIOFF, POWS_ON + SLEEPOFF SLEEP mode cancel LCD_D_NRM, LCD_SION, LCD_SIS_??? + STDBYON STAND BY mode LCD_SION, POWS_ON + STDBYOFF STAND BY mode cancel LCD_D_NRM + -------------------------------------------------------------------------------*/ + +/*** LCD various parameters ***/ +#define LCD_PPB 8 /* Pixels per byte (display is B/W, 1 bit per pixel) */ + +/*** LCD Status byte masks ***/ +#define LCD_S_BUSY 0x80 /* Status Read - BUSY mask */ +#define LCD_S_ADC 0x40 /* Status Read - ADC mask */ +#define LCD_S_ONOFF 0x20 /* Status Read - ON/OFF mask */ +#define LCD_S_RESET 0x10 /* Status Read - RESET mask */ + +/*** LCD commands parameter masks ***/ +#define LCD_M_LADDR 0x3F /* Display start line (6-bit) address mask */ +#define LCD_M_PADDR 0x0F /* Page address (4-bit) page mask */ +#define LCD_M_CADRH 0x0F /* Column address upper (4-bit) column hi mask */ +#define LCD_M_CADRL 0x0F /* Column address lower (4-bit) column lo mask */ +#define LCD_M_PWRMD 0x07 /* Power control (3-bit) mode mask */ +#define LCD_M_RESRT 0x07 /* V5 v. reg. int. resistor ratio (3-bit) ratio mask */ +#define LCD_M_EVSET 0x3F /* Electronic volume mode byte (6-bit) volume mask */ +#define LCD_M_SION 0x03 /* Static indicator ON (2-bit) mode mask */ + +/*** LCD Power control cirquits control masks ***/ +#define LCD_PWRBSTR 0x04 /* Power control mode - Booster cirquit ON */ +#define LCD_PWRVREG 0x02 /* Power control mode - Voltage regulator cirquit ON */ +#define LCD_PWRVFOL 0x01 /* Power control mode - Voltage follower cirquit ON */ + +/*** LCD Static indicator states ***/ +#define LCD_SIS_OFF 0x00 /* Static indicator register set - OFF state */ +#define LCD_SIS_BL 0x01 /* Static indicator register set - 1s blink state */ +#define LCD_SIS_RBL 0x02 /* Static indicator register set - .5s rapid blink state */ +#define LCD_SIS_ON 0x03 /* Static indicator register set - constantly on state */ + +/*** LCD functions special parameters (commands) ***/ +#define LCD_PREVP 0x80 /* Page number for moving to previous */ +#define LCD_NEXTP 0x81 /* or next page */ +#define LCD_ERR_P 0xFF /* Error in page number */ + +/*** LCD initialization settings ***/ +#define LCD_BIAS LCD_BIAS9 /* Bias: 1/9 */ +#define LCD_ADCMODE LCD_ADC_NRM /* ADC mode: normal */ +#define LCD_COMDIR LCD_C_NRM /* Common output mode: normal */ +#define LCD_RRATIO 0 /* Resistor ratio: 0 */ +#define LCD_CNTRST 0x1C /* electronic volume: 1Ch */ +#define LCD_POWERM (LCD_PWRBSTR | LCD_PWRVREG | LCD_PWRVFOL) /* Power mode: All on */ + +/**************************************************************************************/ + +static inline unsigned int sed156x_transfer(unsigned int val) +{ + unsigned int rx; + int b; + + rx = 0; b = 8; + while (--b >= 0) { + SED156X_SPI_TXD(val & 0x80); + val <<= 1; + SED156X_SPI_CLK_TOGGLE(); + SED156X_SPI_BIT_DELAY(); + rx <<= 1; + if (SED156X_SPI_RXD()) + rx |= 1; + SED156X_SPI_CLK_TOGGLE(); + SED156X_SPI_BIT_DELAY(); + } + + return rx; +} + +unsigned int sed156x_data_transfer(unsigned int val) +{ + unsigned int rx; + + SED156X_SPI_CLK(1); + SED156X_CS(0); + SED156X_A0(1); + + rx = sed156x_transfer(val); + + SED156X_CS(1); + + return rx; +} + +void sed156x_data_block_transfer(const u8 *p, int size) +{ + SED156X_SPI_CLK(1); + SED156X_CS(0); + SED156X_A0(1); + + while (--size >= 0) + sed156x_transfer(*p++); + + SED156X_CS(1); +} + +unsigned int sed156x_cmd_transfer(unsigned int val) +{ + unsigned int rx; + + SED156X_SPI_CLK(1); + SED156X_CS(0); + SED156X_A0(0); + + rx = sed156x_transfer(val); + + SED156X_CS(1); + SED156X_A0(1); + + return rx; +} + +/******************************************************************************/ + +static u8 hw_screen[LCD_PAGES][LCD_COLUMNS]; +static u8 last_hw_screen[LCD_PAGES][LCD_COLUMNS]; +static u8 sw_screen[LCD_BYTE_WIDTH * LCD_HEIGHT]; + +void sed156x_sync(void) +{ + int i, j, last_page; + u8 *d; + const u8 *s, *e, *b, *r; + u8 v0, v1, v2, v3, v4, v5, v6, v7; + + /* copy and rotate sw_screen to hw_screen */ + for (i = 0; i < LCD_HEIGHT / 8; i++) { + + d = &hw_screen[i][0]; + s = &sw_screen[LCD_BYTE_WIDTH * 8 * i + LCD_BYTE_WIDTH - 1]; + + for (j = 0; j < LCD_WIDTH / 8; j++) { + + v0 = s[0 * LCD_BYTE_WIDTH]; + v1 = s[1 * LCD_BYTE_WIDTH]; + v2 = s[2 * LCD_BYTE_WIDTH]; + v3 = s[3 * LCD_BYTE_WIDTH]; + v4 = s[4 * LCD_BYTE_WIDTH]; + v5 = s[5 * LCD_BYTE_WIDTH]; + v6 = s[6 * LCD_BYTE_WIDTH]; + v7 = s[7 * LCD_BYTE_WIDTH]; + + d[0] = ((v7 & 0x01) << 7) | + ((v6 & 0x01) << 6) | + ((v5 & 0x01) << 5) | + ((v4 & 0x01) << 4) | + ((v3 & 0x01) << 3) | + ((v2 & 0x01) << 2) | + ((v1 & 0x01) << 1) | + (v0 & 0x01) ; + + d[1] = ((v7 & 0x02) << 6) | + ((v6 & 0x02) << 5) | + ((v5 & 0x02) << 4) | + ((v4 & 0x02) << 3) | + ((v3 & 0x02) << 2) | + ((v2 & 0x02) << 1) | + ((v1 & 0x02) << 0) | + ((v0 & 0x02) >> 1) ; + + d[2] = ((v7 & 0x04) << 5) | + ((v6 & 0x04) << 4) | + ((v5 & 0x04) << 3) | + ((v4 & 0x04) << 2) | + ((v3 & 0x04) << 1) | + (v2 & 0x04) | + ((v1 & 0x04) >> 1) | + ((v0 & 0x04) >> 2) ; + + d[3] = ((v7 & 0x08) << 4) | + ((v6 & 0x08) << 3) | + ((v5 & 0x08) << 2) | + ((v4 & 0x08) << 1) | + (v3 & 0x08) | + ((v2 & 0x08) >> 1) | + ((v1 & 0x08) >> 2) | + ((v0 & 0x08) >> 3) ; + + d[4] = ((v7 & 0x10) << 3) | + ((v6 & 0x10) << 2) | + ((v5 & 0x10) << 1) | + (v4 & 0x10) | + ((v3 & 0x10) >> 1) | + ((v2 & 0x10) >> 2) | + ((v1 & 0x10) >> 3) | + ((v0 & 0x10) >> 4) ; + + d[5] = ((v7 & 0x20) << 2) | + ((v6 & 0x20) << 1) | + (v5 & 0x20) | + ((v4 & 0x20) >> 1) | + ((v3 & 0x20) >> 2) | + ((v2 & 0x20) >> 3) | + ((v1 & 0x20) >> 4) | + ((v0 & 0x20) >> 5) ; + + d[6] = ((v7 & 0x40) << 1) | + (v6 & 0x40) | + ((v5 & 0x40) >> 1) | + ((v4 & 0x40) >> 2) | + ((v3 & 0x40) >> 3) | + ((v2 & 0x40) >> 4) | + ((v1 & 0x40) >> 5) | + ((v0 & 0x40) >> 6) ; + + d[7] = (v7 & 0x80) | + ((v6 & 0x80) >> 1) | + ((v5 & 0x80) >> 2) | + ((v4 & 0x80) >> 3) | + ((v3 & 0x80) >> 4) | + ((v2 & 0x80) >> 5) | + ((v1 & 0x80) >> 6) | + ((v0 & 0x80) >> 7) ; + + d += 8; + s--; + } + } + + /* and now output only the differences */ + for (i = 0; i < LCD_PAGES; i++) { + + b = &hw_screen[i][0]; + e = &hw_screen[i][LCD_COLUMNS]; + + d = &last_hw_screen[i][0]; + s = b; + + last_page = -1; + + /* update only the differences */ + do { + while (s < e && *s == *d) { + s++; + d++; + } + if (s == e) + break; + r = s; + while (s < e && *s != *d) + *d++ = *s++; + + j = r - b; + + if (i != last_page) { + sed156x_cmd_transfer(LCD_PADDR | i); + last_page = i; + } + + sed156x_cmd_transfer(LCD_CADRH | ((j >> 4) & 0x0F)); + sed156x_cmd_transfer(LCD_CADRL | (j & 0x0F)); + sed156x_data_block_transfer(r, s - r); + + } while (s < e); + } + +/******** + for (i = 0; i < LCD_PAGES; i++) { + sed156x_cmd_transfer(LCD_PADDR | i); + sed156x_cmd_transfer(LCD_CADRH | 0); + sed156x_cmd_transfer(LCD_CADRL | 0); + sed156x_data_block_transfer(&hw_screen[i][0], LCD_COLUMNS); + } + memcpy(last_hw_screen, hw_screen, sizeof(last_hw_screen)); +********/ +} + +void sed156x_clear(void) +{ + memset(sw_screen, 0, sizeof(sw_screen)); +} + +void sed156x_output_at(int x, int y, const char *str, int size) +{ + int i, j; + u8 *p; + const u8 *s; + + if ((unsigned int)y >= LCD_TEXT_HEIGHT || (unsigned int)x >= LCD_TEXT_WIDTH) + return; + + p = &sw_screen[y * VIDEO_FONT_HEIGHT * LCD_BYTE_WIDTH + x * VIDEO_FONT_BYTE_WIDTH]; + + while (--size >= 0) { + + s = &video_fontdata[((int)*str++ & 0xff) * VIDEO_FONT_BYTE_WIDTH * VIDEO_FONT_HEIGHT]; + for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { + for (j = 0; j < VIDEO_FONT_BYTE_WIDTH; j++) + *p++ = *s++; + p += LCD_BYTE_WIDTH - VIDEO_FONT_BYTE_WIDTH; + } + p -= (LCD_BYTE_LINESZ - VIDEO_FONT_BYTE_WIDTH); + + if (x >= LCD_TEXT_WIDTH) + break; + x++; + } +} + +void sed156x_reverse_at(int x, int y, int size) +{ + int i, j; + u8 *p; + + if ((unsigned int)y >= LCD_TEXT_HEIGHT || (unsigned int)x >= LCD_TEXT_WIDTH) + return; + + p = &sw_screen[y * VIDEO_FONT_HEIGHT * LCD_BYTE_WIDTH + x * VIDEO_FONT_BYTE_WIDTH]; + + while (--size >= 0) { + + for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { + for (j = 0; j < VIDEO_FONT_BYTE_WIDTH; j++, p++) + *p = ~*p; + p += LCD_BYTE_WIDTH - VIDEO_FONT_BYTE_WIDTH; + } + p -= (LCD_BYTE_LINESZ - VIDEO_FONT_BYTE_WIDTH); + + if (x >= LCD_TEXT_WIDTH) + break; + x++; + } +} + +void sed156x_scroll_line(void) +{ + memmove(&sw_screen[0], + &sw_screen[LCD_BYTE_LINESZ], + LCD_BYTE_WIDTH * (LCD_HEIGHT - VIDEO_FONT_HEIGHT)); +} + +void sed156x_scroll(int dx, int dy) +{ + u8 *p1 = NULL, *p2 = NULL, *p3 = NULL; /* pacify gcc */ + int adx, ady, i, sz; + + adx = dx > 0 ? dx : -dx; + ady = dy > 0 ? dy : -dy; + + /* overscroll? erase everything */ + if (adx >= LCD_TEXT_WIDTH || ady >= LCD_TEXT_HEIGHT) { + memset(sw_screen, 0, sizeof(sw_screen)); + return; + } + + sz = LCD_BYTE_LINESZ * ady; + if (dy > 0) { + p1 = &sw_screen[0]; + p2 = &sw_screen[sz]; + p3 = &sw_screen[LCD_BYTE_WIDTH * LCD_HEIGHT - sz]; + } else if (dy < 0) { + p1 = &sw_screen[sz]; + p2 = &sw_screen[0]; + p3 = &sw_screen[0]; + } + + if (ady > 0) { + memmove(p1, p2, LCD_BYTE_WIDTH * LCD_HEIGHT - sz); + memset(p3, 0, sz); + } + + sz = VIDEO_FONT_BYTE_WIDTH * adx; + if (dx > 0) { + p1 = &sw_screen[0]; + p2 = &sw_screen[0] + sz; + p3 = &sw_screen[0] + LCD_BYTE_WIDTH - sz; + } else if (dx < 0) { + p1 = &sw_screen[0] + sz; + p2 = &sw_screen[0]; + p3 = &sw_screen[0]; + } + + /* xscroll */ + if (adx > 0) { + for (i = 0; i < LCD_HEIGHT; i++) { + memmove(p1, p2, LCD_BYTE_WIDTH - sz); + memset(p3, 0, sz); + p1 += LCD_BYTE_WIDTH; + p2 += LCD_BYTE_WIDTH; + p3 += LCD_BYTE_WIDTH; + } + } +} + +void sed156x_init(void) +{ + int i; + + SED156X_CS(1); + SED156X_A0(1); + + /* Send initialization commands to the LCD */ + sed156x_cmd_transfer(LCD_OFF); /* Turn display OFF */ + sed156x_cmd_transfer(LCD_BIAS); /* set the LCD Bias, */ + sed156x_cmd_transfer(LCD_ADCMODE); /* ADC mode, */ + sed156x_cmd_transfer(LCD_COMDIR); /* common output mode, */ + sed156x_cmd_transfer(LCD_RESRT | LCD_RRATIO); /* resistor ratio, */ + sed156x_cmd_transfer(LCD_EVSET); /* electronic volume, */ + sed156x_cmd_transfer(LCD_CNTRST); + sed156x_cmd_transfer(LCD_PWRMD | LCD_POWERM); /* and power mode */ + sed156x_cmd_transfer(LCD_PADDR | 0); /* cursor home */ + sed156x_cmd_transfer(LCD_CADRH | 0); + sed156x_cmd_transfer(LCD_CADRL | 0); + sed156x_cmd_transfer(LCD_LADDR | 0); /* and display start line */ + sed156x_cmd_transfer(LCD_DSP_NRM); /* LCD display Normal */ + + /* clear everything */ + memset(sw_screen, 0, sizeof(sw_screen)); + memset(hw_screen, 0, sizeof(hw_screen)); + memset(last_hw_screen, 0, sizeof(last_hw_screen)); + + for (i = 0; i < LCD_PAGES; i++) { + sed156x_cmd_transfer(LCD_PADDR | i); + sed156x_cmd_transfer(LCD_CADRH | 0); + sed156x_cmd_transfer(LCD_CADRL | 0); + sed156x_data_block_transfer(&hw_screen[i][0], LCD_COLUMNS); + } + + sed156x_clear(); + sed156x_sync(); + sed156x_cmd_transfer(LCD_ON); /* Turn display ON */ +} diff --git a/qemu/roms/u-boot/drivers/video/sm501.c b/qemu/roms/u-boot/drivers/video/sm501.c new file mode 100644 index 000000000..cafaae5f3 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/sm501.c @@ -0,0 +1,224 @@ +/* + * (C) Copyright 2002 + * Stäubli Faverges - <www.staubli.com> + * Pierre AUBERT p.aubert@staubli.com + * + * (C) Copyright 2005 + * Martin Krause TQ-Systems GmbH martin.krause@tqs.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Basic video support for SMI SM501 "Voyager" graphic controller + */ + +#include <common.h> + +#include <asm/io.h> +#include <video_fb.h> +#include <sm501.h> + +#define read8(ptrReg) \ + *(volatile unsigned char *)(sm501.isaBase + ptrReg) + +#define write8(ptrReg,value) \ + *(volatile unsigned char *)(sm501.isaBase + ptrReg) = value + +#define read16(ptrReg) \ + (*(volatile unsigned short *)(sm501.isaBase + ptrReg)) + +#define write16(ptrReg,value) \ + (*(volatile unsigned short *)(sm501.isaBase + ptrReg) = value) + +#define read32(ptrReg) \ + (*(volatile unsigned int *)(sm501.isaBase + ptrReg)) + +#define write32(ptrReg, value) \ + (*(volatile unsigned int *)(sm501.isaBase + ptrReg) = value) + +GraphicDevice sm501; + +void write_be32(int off, unsigned int val) +{ + out_be32((unsigned __iomem *)(sm501.isaBase + off), val); +} + +void write_le32(int off, unsigned int val) +{ + out_le32((unsigned __iomem *)(sm501.isaBase + off), val); +} + +void (*write_reg32)(int off, unsigned int val) = write_be32; + +/*----------------------------------------------------------------------------- + * SmiSetRegs -- + *----------------------------------------------------------------------------- + */ +static void SmiSetRegs (void) +{ + /* + * The content of the chipset register depends on the board (clocks, + * ...) + */ + const SMI_REGS *preg = board_get_regs (); + while (preg->Index) { + write_reg32 (preg->Index, preg->Value); + /* + * Insert a delay between + */ + udelay (1000); + preg ++; + } +} + +#ifdef CONFIG_VIDEO_SM501_PCI +static struct pci_device_id sm501_pci_tbl[] = { + { PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_501 }, + {} +}; +#endif + +/* + * We do not enforce board code to provide empty/unused + * functions for this driver and define weak default + * functions here. + */ +unsigned int __board_video_init (void) +{ + return 0; +} + +unsigned int board_video_init (void) + __attribute__((weak, alias("__board_video_init"))); + +unsigned int __board_video_get_fb (void) +{ + return 0; +} + +unsigned int board_video_get_fb (void) + __attribute__((weak, alias("__board_video_get_fb"))); + +void __board_validate_screen (unsigned int base) +{ +} + +void board_validate_screen (unsigned int base) + __attribute__((weak, alias("__board_validate_screen"))); + +/*----------------------------------------------------------------------------- + * video_hw_init -- + *----------------------------------------------------------------------------- + */ +void *video_hw_init (void) +{ +#ifdef CONFIG_VIDEO_SM501_PCI + unsigned int pci_mem_base, pci_mmio_base; + unsigned int id; + unsigned short device_id; + pci_dev_t devbusfn; + int mem; +#endif + unsigned int *vm, i; + + memset (&sm501, 0, sizeof (GraphicDevice)); + +#ifdef CONFIG_VIDEO_SM501_PCI + printf("Video: "); + + /* Look for SM501/SM502 chips */ + devbusfn = pci_find_devices(sm501_pci_tbl, 0); + if (devbusfn < 0) { + printf ("PCI Controller not found.\n"); + goto not_pci; + } + + /* Setup */ + pci_write_config_dword (devbusfn, PCI_COMMAND, + (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); + pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id); + pci_read_config_dword (devbusfn, PCI_REVISION_ID, &id); + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base); + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_1, &pci_mmio_base); + sm501.frameAdrs = pci_mem_to_phys (devbusfn, pci_mem_base); + sm501.isaBase = pci_mem_to_phys (devbusfn, pci_mmio_base); + + if (sm501.isaBase) + write_reg32 = write_le32; + + mem = in_le32 ((unsigned __iomem *)(sm501.isaBase + 0x10)); + mem = (mem & 0x0000e000) >> 13; + switch (mem) { + case 1: + mem = 8; + break; + case 2: + mem = 16; + break; + case 3: + mem = 32; + break; + case 4: + mem = 64; + break; + case 5: + mem = 2; + break; + case 0: + default: + mem = 4; + } + printf ("PCI SM50%d %d MB\n", ((id & 0xff) == 0xC0) ? 2 : 1, mem); +not_pci: +#endif + /* + * Initialization of the access to the graphic chipset Retreive base + * address of the chipset (see board/RPXClassic/eccx.c) + */ + if (!sm501.isaBase) { + sm501.isaBase = board_video_init (); + if (!sm501.isaBase) + return NULL; + } + + if (!sm501.frameAdrs) { + sm501.frameAdrs = board_video_get_fb (); + if (!sm501.frameAdrs) + return NULL; + } + + sm501.winSizeX = board_get_width (); + sm501.winSizeY = board_get_height (); + +#if defined(CONFIG_VIDEO_SM501_8BPP) + sm501.gdfIndex = GDF__8BIT_INDEX; + sm501.gdfBytesPP = 1; + +#elif defined(CONFIG_VIDEO_SM501_16BPP) + sm501.gdfIndex = GDF_16BIT_565RGB; + sm501.gdfBytesPP = 2; + +#elif defined(CONFIG_VIDEO_SM501_32BPP) + sm501.gdfIndex = GDF_32BIT_X888RGB; + sm501.gdfBytesPP = 4; +#else +#error Unsupported SM501 BPP +#endif + + sm501.memSize = sm501.winSizeX * sm501.winSizeY * sm501.gdfBytesPP; + + /* Load Smi registers */ + SmiSetRegs (); + + /* (see board/RPXClassic/RPXClassic.c) */ + board_validate_screen (sm501.isaBase); + + /* Clear video memory */ + i = sm501.memSize/4; + vm = (unsigned int *)sm501.frameAdrs; + while(i--) + *vm++ = 0; + + return (&sm501); +} diff --git a/qemu/roms/u-boot/drivers/video/smiLynxEM.c b/qemu/roms/u-boot/drivers/video/smiLynxEM.c new file mode 100644 index 000000000..614bcb3c9 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/smiLynxEM.c @@ -0,0 +1,838 @@ +/* + * (C) Copyright 1997-2002 ELTEC Elektronik AG + * Frank Gottschling <fgottschling@eltec.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * smiLynxEM.c + * + * Silicon Motion graphic interface for sm810/sm710/sm712 accelerator + * + * modification history + * -------------------- + * 04-18-2002 Rewritten for U-Boot <fgottschling@eltec.de>. + * + * 18-03-2004 - Unify videomodes handling with the ct69000 + * - The video output can be set via the variable "videoout" + * in the environment. + * videoout=1 output on LCD + * videoout=2 output on CRT (default value) + * <p.aubert@staubli.com> + */ + +#include <common.h> + +#include <pci.h> +#include <video_fb.h> +#include "videomodes.h" +/* + * Export Graphic Device + */ +GraphicDevice smi; + +/* + * SMI 710/712 have 4MB internal RAM; SMI 810 2MB internal + 2MB external + */ +#define VIDEO_MEM_SIZE 0x400000 + + +/* + * ISA mapped regs + */ +#define SMI_INDX_C4 (pGD->isaBase + 0x03c4) /* index reg */ +#define SMI_DATA_C5 (pGD->isaBase + 0x03c5) /* data reg */ +#define SMI_INDX_D4 (pGD->isaBase + 0x03d4) /* index reg */ +#define SMI_DATA_D5 (pGD->isaBase + 0x03d5) /* data reg */ +#define SMI_ISR1 (pGD->isaBase + 0x03ca) +#define SMI_INDX_CE (pGD->isaBase + 0x03ce) /* index reg */ +#define SMI_DATA_CF (pGD->isaBase + 0x03cf) /* data reg */ +#define SMI_LOCK_REG (pGD->isaBase + 0x03c3) /* unlock/lock ext crt reg */ +#define SMI_MISC_REG (pGD->isaBase + 0x03c2) /* misc reg */ +#define SMI_LUT_MASK (pGD->isaBase + 0x03c6) /* lut mask reg */ +#define SMI_LUT_START (pGD->isaBase + 0x03c8) /* lut start index */ +#define SMI_LUT_RGB (pGD->isaBase + 0x03c9) /* lut colors auto incr.*/ +#define SMI_INDX_ATTR (pGD->isaBase + 0x03c0) /* attributes index reg */ + +/* + * Video processor control + */ +typedef struct { + unsigned int control; + unsigned int colorKey; + unsigned int colorKeyMask; + unsigned int start; + unsigned short offset; + unsigned short width; + unsigned int fifoPrio; + unsigned int fifoERL; + unsigned int YUVtoRGB; +} SmiVideoProc; + +/* + * Video window control + */ +typedef struct { + unsigned short top; + unsigned short left; + unsigned short bottom; + unsigned short right; + unsigned int srcStart; + unsigned short width; + unsigned short offset; + unsigned char hStretch; + unsigned char vStretch; +} SmiVideoWin; + +/* + * Capture port control + */ +typedef struct { + unsigned int control; + unsigned short topClip; + unsigned short leftClip; + unsigned short srcHeight; + unsigned short srcWidth; + unsigned int srcBufStart1; + unsigned int srcBufStart2; + unsigned short srcOffset; + unsigned short fifoControl; +} SmiCapturePort; + + +/* + * Register values for common video modes + */ +static char SMI_SCR[] = { + /* all modes */ + 0x10, 0xff, 0x11, 0xff, 0x12, 0xff, 0x13, 0xff, 0x15, 0x90, + 0x17, 0x20, 0x18, 0xb1, 0x19, 0x00, +}; +static char SMI_EXT_CRT[] = { + 0x31, 0x00, 0x32, 0x00, 0x33, 0x00, 0x34, 0x00, 0x35, 0x00, + 0x36, 0x00, 0x3b, 0x00, 0x3c, 0x00, 0x3d, 0x00, 0x3e, 0x00, 0x3f, 0x00, +}; +static char SMI_ATTR [] = { + 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, + 0x06, 0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x09, 0x0a, 0x0a, 0x0b, 0x0b, + 0x0c, 0x0c, 0x0d, 0x0d, 0x0e, 0x0e, 0x0f, 0x0f, 0x10, 0x41, 0x11, 0x00, + 0x12, 0x0f, 0x13, 0x00, 0x14, 0x00, +}; +static char SMI_GCR[18] = { + 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x03, 0x00, 0x04, 0x00, 0x05, 0x40, + 0x06, 0x05, 0x07, 0x0f, 0x08, 0xff, +}; +static char SMI_SEQR[] = { + 0x00, 0x00, 0x01, 0x01, 0x02, 0x0f, 0x03, 0x03, 0x04, 0x0e, 0x00, 0x03, +}; +static char SMI_PCR [] = { + 0x20, 0x04, 0x21, 0x30, 0x22, 0x00, 0x23, 0x00, 0x24, 0x00, +}; +static char SMI_MCR[] = { + 0x60, 0x01, 0x61, 0x00, +#ifdef CONFIG_HMI1001 + 0x62, 0x74, /* Memory type is not configured by pins on HMI1001 */ +#endif +}; + +static char SMI_HCR[] = { + 0x80, 0xff, 0x81, 0x07, 0x82, 0x00, 0x83, 0xff, 0x84, 0xff, 0x88, 0x00, + 0x89, 0x02, 0x8a, 0x80, 0x8b, 0x01, 0x8c, 0xff, 0x8d, 0x00, +}; + + +/******************************************************************************* + * + * Write SMI ISA register + */ +static void smiWrite (unsigned short index, char reg, char val) +{ + register GraphicDevice *pGD = (GraphicDevice *)&smi; + + out8 ((pGD->isaBase + index), reg); + out8 ((pGD->isaBase + index + 1), val); +} + +/******************************************************************************* + * + * Write a table of SMI ISA register + */ +static void smiLoadRegs ( + unsigned int iReg, + unsigned int dReg, + char *regTab, + unsigned int tabSize + ) +{ + register GraphicDevice *pGD = (GraphicDevice *)&smi; + register int i; + + for (i=0; i<tabSize; i+=2) { + if (iReg == SMI_INDX_ATTR) { + /* Reset the Flip Flop */ + in8 (SMI_ISR1); + out8 (iReg, regTab[i]); + out8 (iReg, regTab[i+1]); + } else { + out8 (iReg, regTab[i]); + out8 (dReg, regTab[i+1]); + } + } +} + +/******************************************************************************* + * + * Init capture port registers + */ +static void smiInitCapturePort (void) +{ + SmiCapturePort smiCP = { 0x01400600, 0x30, 0x40, 480, 640, 0, 0, 2560, 6 }; + register GraphicDevice *pGD = (GraphicDevice *)&smi; + register SmiCapturePort *pCP = (SmiCapturePort *)&smiCP; + + out32r ((pGD->cprBase + 0x0004), ((pCP->topClip<<16) | pCP->leftClip)); + out32r ((pGD->cprBase + 0x0008), ((pCP->srcHeight<<16) | pCP->srcWidth)); + out32r ((pGD->cprBase + 0x000c), pCP->srcBufStart1/8); + out32r ((pGD->cprBase + 0x0010), pCP->srcBufStart2/8); + out32r ((pGD->cprBase + 0x0014), pCP->srcOffset/8); + out32r ((pGD->cprBase + 0x0018), pCP->fifoControl); + out32r ((pGD->cprBase + 0x0000), pCP->control); +} + + +/******************************************************************************* + * + * Init video processor registers + */ +static void smiInitVideoProcessor (void) +{ + SmiVideoProc smiVP = { 0x100000, 0, 0, 0, 0, 1600, 0x1200543, 4, 0xededed }; + SmiVideoWin smiVW = { 0, 0, 599, 799, 0, 1600, 0, 0, 0 }; + register GraphicDevice *pGD = (GraphicDevice *)&smi; + register SmiVideoProc *pVP = (SmiVideoProc *)&smiVP; + register SmiVideoWin *pVWin = (SmiVideoWin *)&smiVW; + + pVP->width = pGD->plnSizeX * pGD->gdfBytesPP; + pVP->control |= pGD->gdfIndex << 16; + pVWin->bottom = pGD->winSizeY - 1; + pVWin->right = pGD->winSizeX - 1; + pVWin->width = pVP->width; + + /* color key */ + out32r ((pGD->vprBase + 0x0004), pVP->colorKey); + + /* color key mask */ + out32r ((pGD->vprBase + 0x0008), pVP->colorKeyMask); + + /* data src start adrs */ + out32r ((pGD->vprBase + 0x000c), pVP->start / 8); + + /* data width and offset */ + out32r ((pGD->vprBase + 0x0010), + ((pVP->offset / 8 * pGD->gdfBytesPP) << 16) | + (pGD->plnSizeX / 8 * pGD->gdfBytesPP)); + + /* video window 1 */ + out32r ((pGD->vprBase + 0x0014), + ((pVWin->top << 16) | pVWin->left)); + + out32r ((pGD->vprBase + 0x0018), + ((pVWin->bottom << 16) | pVWin->right)); + + out32r ((pGD->vprBase + 0x001c), pVWin->srcStart / 8); + + out32r ((pGD->vprBase + 0x0020), + (((pVWin->offset / 8) << 16) | (pVWin->width / 8))); + + out32r ((pGD->vprBase + 0x0024), + (((pVWin->hStretch) << 8) | pVWin->vStretch)); + + /* video window 2 */ + out32r ((pGD->vprBase + 0x0028), + ((pVWin->top << 16) | pVWin->left)); + + out32r ((pGD->vprBase + 0x002c), + ((pVWin->bottom << 16) | pVWin->right)); + + out32r ((pGD->vprBase + 0x0030), + pVWin->srcStart / 8); + + out32r ((pGD->vprBase + 0x0034), + (((pVWin->offset / 8) << 16) | (pVWin->width / 8))); + + out32r ((pGD->vprBase + 0x0038), + (((pVWin->hStretch) << 8) | pVWin->vStretch)); + + /* fifo prio control */ + out32r ((pGD->vprBase + 0x0054), pVP->fifoPrio); + + /* fifo empty request levell */ + out32r ((pGD->vprBase + 0x0058), pVP->fifoERL); + + /* conversion constant */ + out32r ((pGD->vprBase + 0x005c), pVP->YUVtoRGB); + + /* vpr control word */ + out32r ((pGD->vprBase + 0x0000), pVP->control); +} + +/****************************************************************************** + * + * Init drawing engine registers + */ +static void smiInitDrawingEngine (void) +{ + GraphicDevice *pGD = (GraphicDevice *)&smi; + unsigned int val; + + /* don't start now */ + out32r ((pGD->dprBase + 0x000c), 0x000f0000); + + /* set rop2 to copypen */ + val = 0xffff3ff0 & in32r ((pGD->dprBase + 0x000c)); + out32r ((pGD->dprBase + 0x000c), (val | 0x8000 | 0x0c)); + + /* set clip rect */ + out32r ((pGD->dprBase + 0x002c), 0); + out32r ((pGD->dprBase + 0x0030), + ((pGD->winSizeY<<16) | pGD->winSizeX * pGD->gdfBytesPP )); + + /* src row pitch */ + val = 0xffff0000 & (in32r ((pGD->dprBase + 0x0010))); + out32r ((pGD->dprBase + 0x0010), + (val | pGD->plnSizeX * pGD->gdfBytesPP)); + + /* dst row pitch */ + val = 0x0000ffff & (in32r ((pGD->dprBase + 0x0010))); + out32r ((pGD->dprBase + 0x0010), + (((pGD->plnSizeX * pGD->gdfBytesPP)<<16) | val)); + + /* window width src/dst */ + out32r ((pGD->dprBase + 0x003c), + (((pGD->plnSizeX * pGD->gdfBytesPP & 0x0fff)<<16) | + (pGD->plnSizeX * pGD->gdfBytesPP & 0x0fff))); + out16r ((pGD->dprBase + 0x001e), 0x0000); + + /* src base adrs */ + out32r ((pGD->dprBase + 0x0040), + (((pGD->frameAdrs/8) & 0x000fffff))); + + /* dst base adrs */ + out32r ((pGD->dprBase + 0x0044), + (((pGD->frameAdrs/8) & 0x000fffff))); + + /* foreground color */ + out32r ((pGD->dprBase + 0x0014), pGD->fg); + + /* background color */ + out32r ((pGD->dprBase + 0x0018), pGD->bg); + + /* xcolor */ + out32r ((pGD->dprBase + 0x0020), 0x00ffffff); + + /* xcolor mask */ + out32r ((pGD->dprBase + 0x0024), 0x00ffffff); + + /* bit mask */ + out32r ((pGD->dprBase + 0x0028), 0x00ffffff); + + /* load mono pattern */ + out32r ((pGD->dprBase + 0x0034), 0); + out32r ((pGD->dprBase + 0x0038), 0); +} + +static struct pci_device_id supported[] = { + { PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_710 }, + { PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_712 }, + { PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_810 }, + { } +}; + +/*****************************************************************************/ +static void smiLoadMsr (struct ctfb_res_modes *mode) +{ + unsigned char h_synch_high, v_synch_high; + register GraphicDevice *pGD = (GraphicDevice *)&smi; + + h_synch_high = (mode->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x40; /* horizontal Synch High active */ + v_synch_high = (mode->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x80; /* vertical Synch High active */ + out8 (SMI_MISC_REG, (h_synch_high | v_synch_high | 0x29)); + /* upper64K==0x20, CLC2select==0x08, RAMenable==0x02!(todo), CGA==0x01 + * Selects the upper 64KB page.Bit5=1 + * CLK2 (left reserved in standard VGA) Bit3|2=1|0 + * Disables CPU access to frame buffer. Bit1=0 + * Sets the I/O address decode for ST01, FCR, and all CR registers + * to the 3Dx I/O address range (CGA emulation). Bit0=1 + */ +} +/*****************************************************************************/ +static void smiLoadCrt (struct ctfb_res_modes *var, int bits_per_pixel) +{ + unsigned char cr[0x7a]; + int i; + unsigned int hd, hs, he, ht, hbs, hbe; /* Horizontal. */ + unsigned int vd, vs, ve, vt, vbs, vbe; /* vertical */ + unsigned int bpp, wd, dblscan, interlaced; + + const int LineCompare = 0x3ff; + unsigned int TextScanLines = 1; /* this is in fact a vertical zoom factor */ + register GraphicDevice *pGD = (GraphicDevice *)&smi; + + /* Horizontal */ + hd = (var->xres) / 8; /* HDisp. */ + hs = (var->xres + var->right_margin) / 8; /* HsStrt */ + he = (var->xres + var->right_margin + var->hsync_len) / 8; /* HsEnd */ + ht = (var->left_margin + var->xres + var->right_margin + var->hsync_len) / 8; /* HTotal */ + /* Blank */ + hbs = hd; + hbe = 0; /* Blank end at 0 */ + + /* Vertical */ + vd = var->yres; /* VDisplay */ + vs = var->yres + var->lower_margin; /* VSyncStart */ + ve = var->yres + var->lower_margin + var->vsync_len; /* VSyncEnd */ + vt = var->upper_margin + var->yres + var->lower_margin + var->vsync_len; /* VTotal */ + vbs = vd; + vbe = 0; + + bpp = bits_per_pixel; + dblscan = (var->vmode & FB_VMODE_DOUBLE) ? 1 : 0; + interlaced = var->vmode & FB_VMODE_INTERLACED; + + + if (bpp == 15) + bpp = 16; + wd = var->xres * bpp / 64; /* double words per line */ + if (interlaced) { /* we divide all vertical timings, exept vd */ + vs >>= 1; + vbs >>= 1; + ve >>= 1; + vt >>= 1; + } + + memset (cr, 0, sizeof (cr)); + cr[0x00] = ht - 5; + cr[0x01] = hd - 1; + cr[0x02] = hbs - 1; + cr[0x03] = (hbe & 0x1F); + cr[0x04] = hs; + cr[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f); + + cr[0x06] = (vt - 2) & 0xFF; + cr[0x07] = (((vt - 2) & 0x100) >> 8) + | (((vd - 1) & 0x100) >> 7) + | ((vs & 0x100) >> 6) + | (((vbs - 1) & 0x100) >> 5) + | ((LineCompare & 0x100) >> 4) + | (((vt - 2) & 0x200) >> 4) + | (((vd - 1) & 0x200) >> 3) + | ((vs & 0x200) >> 2); + + cr[0x30] = ((vt - 2) & 0x400) >> 7 + | (((vd - 1) & 0x400) >> 8) + | (((vbs - 1) & 0x400) >> 9) + | ((vs & 0x400) >> 10) + | (interlaced) ? 0x80 : 0; + + + cr[0x08] = 0x00; + cr[0x09] = (dblscan << 7) + | ((LineCompare & 0x200) >> 3) + | (((vbs - 1) & 0x200) >> 4) + | (TextScanLines - 1); + + cr[0x10] = vs & 0xff; /* VSyncPulseStart */ + cr[0x11] = (ve & 0x0f); + cr[0x12] = (vd - 1) & 0xff; /* LineCount */ + cr[0x13] = wd & 0xff; + cr[0x14] = 0x40; + cr[0x15] = (vbs - 1) & 0xff; + cr[0x16] = vbe & 0xff; + cr[0x17] = 0xe3; /* but it does not work */ + cr[0x18] = 0xff & LineCompare; + cr[0x22] = 0x00; /* todo? */ + + + /* now set the registers */ + for (i = 0; i <= 0x18; i++) { /*CR00 .. CR18 */ + smiWrite (SMI_INDX_D4, i, cr[i]); + } + i = 0x22; /*CR22 */ + smiWrite (SMI_INDX_D4, i, cr[i]); + i = 0x30; /*CR30 */ + smiWrite (SMI_INDX_D4, i, cr[i]); +} + +/*****************************************************************************/ +#define REF_FREQ 14318180 +#define PMIN 1 +#define PMAX 255 +#define QMIN 1 +#define QMAX 63 + +static unsigned int FindPQ (unsigned int freq, unsigned int *pp, unsigned int *pq) +{ + unsigned int n = QMIN, m = 0; + long long int L = 0, P = freq, Q = REF_FREQ, H = P >> 1; + long long int D = 0x7ffffffffffffffLL; + + for (n = QMIN; n <= QMAX; n++) { + m = PMIN; /* p/q ~ freq/ref -> p*ref-freq*q ~ 0 */ + L = P * n - m * Q; + while (L > 0 && m < PMAX) { + L -= REF_FREQ; /* difference is greater as 0 subtract fref */ + m++; /* and increment m */ + } + /* difference is less or equal than 0 or m > maximum */ + if (m > PMAX) + break; /* no solution: if we increase n we get the same situation */ + /* L is <= 0 now */ + if (-L > H && m > PMIN) { /* if difference > the half fref */ + L += REF_FREQ; /* we take the situation before */ + m--; /* because its closer to 0 */ + } + L = (L < 0) ? -L : +L; /* absolute value */ + if (D < L) /* if last difference was better take next n */ + continue; + D = L; + *pp = m; + *pq = n; /* keep improved data */ + if (D == 0) + break; /* best result we can get */ + } + return (unsigned int) (0xffffffff & D); +} + +/*****************************************************************************/ +static void smiLoadCcr (struct ctfb_res_modes *var, unsigned short device_id) +{ + unsigned int p = 0; + unsigned int q = 0; + long long freq; + register GraphicDevice *pGD = (GraphicDevice *)&smi; + + smiWrite (SMI_INDX_C4, 0x65, 0); + smiWrite (SMI_INDX_C4, 0x66, 0); + smiWrite (SMI_INDX_C4, 0x68, 0x50); + if (device_id == PCI_DEVICE_ID_SMI_810) { + smiWrite (SMI_INDX_C4, 0x69, 0x3); + } else { + smiWrite (SMI_INDX_C4, 0x69, 0x0); + } + + /* Memory clock */ + switch (device_id) { + case PCI_DEVICE_ID_SMI_710 : + smiWrite (SMI_INDX_C4, 0x6a, 0x75); + break; + case PCI_DEVICE_ID_SMI_712 : + smiWrite (SMI_INDX_C4, 0x6a, 0x80); + break; + default : + smiWrite (SMI_INDX_C4, 0x6a, 0x53); + break; + } + smiWrite (SMI_INDX_C4, 0x6b, 0x15); + + /* VCLK */ + freq = 1000000000000LL / var -> pixclock; + + FindPQ ((unsigned int)freq, &p, &q); + + smiWrite (SMI_INDX_C4, 0x6c, p); + smiWrite (SMI_INDX_C4, 0x6d, q); + +} + +/******************************************************************************* + * + * Init video chip with common Linux graphic modes (lilo) + */ +void *video_hw_init (void) +{ + GraphicDevice *pGD = (GraphicDevice *)&smi; + unsigned short device_id; + pci_dev_t devbusfn; + int videomode; + unsigned long t1, hsynch, vsynch; + unsigned int pci_mem_base, *vm; + char *penv; + int tmp, i, bits_per_pixel; + struct ctfb_res_modes *res_mode; + struct ctfb_res_modes var_mode; + unsigned char videoout; + + /* Search for video chip */ + printf("Video: "); + + if ((devbusfn = pci_find_devices(supported, 0)) < 0) + { + printf ("Controller not found !\n"); + return (NULL); + } + + /* PCI setup */ + pci_write_config_dword (devbusfn, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); + pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id); + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base); + pci_mem_base = pci_mem_to_phys (devbusfn, pci_mem_base); + + tmp = 0; + + videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE; + /* get video mode via environment */ + if ((penv = getenv ("videomode")) != NULL) { + /* deceide if it is a string */ + if (penv[0] <= '9') { + videomode = (int) simple_strtoul (penv, NULL, 16); + tmp = 1; + } + } else { + tmp = 1; + } + if (tmp) { + /* parameter are vesa modes */ + /* search params */ + for (i = 0; i < VESA_MODES_COUNT; i++) { + if (vesa_modes[i].vesanr == videomode) + break; + } + if (i == VESA_MODES_COUNT) { + printf ("no VESA Mode found, switching to mode 0x%x ", CONFIG_SYS_DEFAULT_VIDEO_MODE); + i = 0; + } + res_mode = + (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i]. + resindex]; + bits_per_pixel = vesa_modes[i].bits_per_pixel; + } else { + + res_mode = (struct ctfb_res_modes *) &var_mode; + bits_per_pixel = video_get_params (res_mode, penv); + } + + /* calculate hsynch and vsynch freq (info only) */ + t1 = (res_mode->left_margin + res_mode->xres + + res_mode->right_margin + res_mode->hsync_len) / 8; + t1 *= 8; + t1 *= res_mode->pixclock; + t1 /= 1000; + hsynch = 1000000000L / t1; + t1 *= + (res_mode->upper_margin + res_mode->yres + + res_mode->lower_margin + res_mode->vsync_len); + t1 /= 1000; + vsynch = 1000000000L / t1; + + /* fill in Graphic device struct */ + sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, + res_mode->yres, bits_per_pixel, (hsynch / 1000), + (vsynch / 1000)); + printf ("%s\n", pGD->modeIdent); + pGD->winSizeX = res_mode->xres; + pGD->winSizeY = res_mode->yres; + pGD->plnSizeX = res_mode->xres; + pGD->plnSizeY = res_mode->yres; + switch (bits_per_pixel) { + case 8: + pGD->gdfBytesPP = 1; + pGD->gdfIndex = GDF__8BIT_INDEX; + break; + case 15: + pGD->gdfBytesPP = 2; + pGD->gdfIndex = GDF_15BIT_555RGB; + break; + case 16: + pGD->gdfBytesPP = 2; + pGD->gdfIndex = GDF_16BIT_565RGB; + break; + case 24: + pGD->gdfBytesPP = 3; + pGD->gdfIndex = GDF_24BIT_888RGB; + break; + } + + pGD->isaBase = CONFIG_SYS_ISA_IO; + pGD->pciBase = pci_mem_base; + pGD->dprBase = (pci_mem_base + 0x400000 + 0x8000); + pGD->vprBase = (pci_mem_base + 0x400000 + 0xc000); + pGD->cprBase = (pci_mem_base + 0x400000 + 0xe000); + pGD->frameAdrs = pci_mem_base; + pGD->memSize = VIDEO_MEM_SIZE; + + /* Set up hardware : select color mode, + set Register base to isa 3dx for 3?x regs*/ + out8 (SMI_MISC_REG, 0x01); + + /* Turn off display */ + smiWrite (SMI_INDX_C4, 0x01, 0x20); + + /* Unlock ext. crt regs */ + out8 (SMI_LOCK_REG, 0x40); + + /* Unlock crt regs 0-7 */ + smiWrite (SMI_INDX_D4, 0x11, 0x0e); + + /* Sytem Control Register */ + smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_SCR, sizeof(SMI_SCR)); + + /* extented CRT Register */ + smiLoadRegs (SMI_INDX_D4, SMI_DATA_D5, SMI_EXT_CRT, sizeof(SMI_EXT_CRT)); + + /* Attributes controller registers */ + smiLoadRegs (SMI_INDX_ATTR, SMI_INDX_ATTR, SMI_ATTR, sizeof(SMI_ATTR)); + + /* Graphics Controller Register */ + smiLoadRegs (SMI_INDX_CE, SMI_DATA_CF, SMI_GCR, sizeof(SMI_GCR)); + + /* Sequencer Register */ + smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_SEQR, sizeof(SMI_SEQR)); + + /* Power Control Register */ + smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_PCR, sizeof(SMI_PCR)); + + /* Memory Control Register */ + /* Register MSR62 is a power on configurable register. We don't */ + /* modify it */ + smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_MCR, sizeof(SMI_MCR)); + + /* Set misc output register */ + smiLoadMsr (res_mode); + + /* Set CRT and Clock control registers */ + smiLoadCrt (res_mode, bits_per_pixel); + + smiLoadCcr (res_mode, device_id); + + /* Hardware Cusor Register */ + smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_HCR, sizeof(SMI_HCR)); + + /* Enable Display */ + videoout = 2; /* Default output is CRT */ + if ((penv = getenv ("videoout")) != NULL) { + /* deceide if it is a string */ + videoout = (int) simple_strtoul (penv, NULL, 16); + } + smiWrite (SMI_INDX_C4, 0x31, videoout); + + /* Video processor default setup */ + smiInitVideoProcessor (); + + /* Capture port default setup */ + smiInitCapturePort (); + + /* Drawing engine default setup */ + smiInitDrawingEngine (); + + /* Turn on display */ + smiWrite (0x3c4, 0x01, 0x01); + + /* Clear video memory */ + i = pGD->memSize/4; + vm = (unsigned int *)pGD->pciBase; + while(i--) + *vm++ = 0; + return ((void*)&smi); +} + +/******************************************************************************* + * + * Drawing engine fill on screen region + */ +void video_hw_rectfill ( + unsigned int bpp, /* bytes per pixel */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y, /* frame height */ + unsigned int color /* fill color */ + ) +{ + register GraphicDevice *pGD = (GraphicDevice *)&smi; + register unsigned int control; + + dim_x *= bpp; + + out32r ((pGD->dprBase + 0x0014), color); + out32r ((pGD->dprBase + 0x0004), ((dst_x<<16) | dst_y)); + out32r ((pGD->dprBase + 0x0008), ((dim_x<<16) | dim_y)); + + control = 0x0000ffff & in32r ((pGD->dprBase + 0x000c)); + + control |= 0x80010000; + + out32r ((pGD->dprBase + 0x000c), control); + + /* Wait for drawing processor */ + do + { + out8 ((pGD->isaBase + 0x3c4), 0x16); + } while (in8 (pGD->isaBase + 0x3c5) & 0x08); +} + +/******************************************************************************* + * + * Drawing engine bitblt with screen region + */ +void video_hw_bitblt ( + unsigned int bpp, /* bytes per pixel */ + unsigned int src_x, /* source pos x */ + unsigned int src_y, /* source pos y */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y /* frame height */ + ) +{ + register GraphicDevice *pGD = (GraphicDevice *)&smi; + register unsigned int control; + + dim_x *= bpp; + + if ((src_y<dst_y) || ((src_y==dst_y) && (src_x<dst_x))) + { + out32r ((pGD->dprBase + 0x0000), (((src_x+dim_x-1)<<16) | (src_y+dim_y-1))); + out32r ((pGD->dprBase + 0x0004), (((dst_x+dim_x-1)<<16) | (dst_y+dim_y-1))); + control = 0x88000000; + } else { + out32r ((pGD->dprBase + 0x0000), ((src_x<<16) | src_y)); + out32r ((pGD->dprBase + 0x0004), ((dst_x<<16) | dst_y)); + control = 0x80000000; + } + + out32r ((pGD->dprBase + 0x0008), ((dim_x<<16) | dim_y)); + control |= (0x0000ffff & in32r ((pGD->dprBase + 0x000c))); + out32r ((pGD->dprBase + 0x000c), control); + + /* Wait for drawing processor */ + do + { + out8 ((pGD->isaBase + 0x3c4), 0x16); + } while (in8 (pGD->isaBase + 0x3c5) & 0x08); +} + +/******************************************************************************* + * + * Set a RGB color in the LUT (8 bit index) + */ +void video_set_lut ( + unsigned int index, /* color number */ + unsigned char r, /* red */ + unsigned char g, /* green */ + unsigned char b /* blue */ + ) +{ + register GraphicDevice *pGD = (GraphicDevice *)&smi; + + out8 (SMI_LUT_MASK, 0xff); + + out8 (SMI_LUT_START, (char)index); + + out8 (SMI_LUT_RGB, r>>2); /* red */ + udelay (10); + out8 (SMI_LUT_RGB, g>>2); /* green */ + udelay (10); + out8 (SMI_LUT_RGB, b>>2); /* blue */ + udelay (10); +} diff --git a/qemu/roms/u-boot/drivers/video/tegra.c b/qemu/roms/u-boot/drivers/video/tegra.c new file mode 100644 index 000000000..57cb0074e --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/tegra.c @@ -0,0 +1,299 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <lcd.h> + +#include <asm/system.h> +#include <asm/gpio.h> + +#include <asm/arch/clock.h> +#include <asm/arch/funcmux.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/pwm.h> +#include <asm/arch/display.h> +#include <asm/arch-tegra/timer.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* These are the stages we go throuh in enabling the LCD */ +enum stage_t { + STAGE_START, + STAGE_PANEL_VDD, + STAGE_LVDS, + STAGE_BACKLIGHT_VDD, + STAGE_PWM, + STAGE_BACKLIGHT_EN, + STAGE_DONE, +}; + +static enum stage_t stage; /* Current stage we are at */ +static unsigned long timer_next; /* Time we can move onto next stage */ + +/* Our LCD config, set up in handle_stage() */ +static struct fdt_panel_config config; +struct fdt_disp_config *disp_config; /* Display controller config */ + +enum { + /* Maximum LCD size we support */ + LCD_MAX_WIDTH = 1366, + LCD_MAX_HEIGHT = 768, + LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */ +}; + +vidinfo_t panel_info = { + /* Insert a value here so that we don't end up in the BSS */ + .vl_col = -1, +}; + +#ifndef CONFIG_OF_CONTROL +#error "You must enable CONFIG_OF_CONTROL to get Tegra LCD support" +#endif + +static void update_panel_size(struct fdt_disp_config *config) +{ + panel_info.vl_col = config->width; + panel_info.vl_row = config->height; + panel_info.vl_bpix = config->log2_bpp; +} + +/* + * Main init function called by lcd driver. + * Inits and then prints test pattern if required. + */ + +void lcd_ctrl_init(void *lcdbase) +{ + int type = DCACHE_OFF; + int size; + + assert(disp_config); + + /* Make sure that we can acommodate the selected LCD */ + assert(disp_config->width <= LCD_MAX_WIDTH); + assert(disp_config->height <= LCD_MAX_HEIGHT); + assert(disp_config->log2_bpp <= LCD_MAX_LOG2_BPP); + if (disp_config->width <= LCD_MAX_WIDTH + && disp_config->height <= LCD_MAX_HEIGHT + && disp_config->log2_bpp <= LCD_MAX_LOG2_BPP) + update_panel_size(disp_config); + size = lcd_get_size(&lcd_line_length); + + /* Set up the LCD caching as requested */ + if (config.cache_type & FDT_LCD_CACHE_WRITE_THROUGH) + type = DCACHE_WRITETHROUGH; + else if (config.cache_type & FDT_LCD_CACHE_WRITE_BACK) + type = DCACHE_WRITEBACK; + mmu_set_region_dcache_behaviour(disp_config->frame_buffer, size, type); + + /* Enable flushing after LCD writes if requested */ + lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH); + + debug("LCD frame buffer at %08X\n", disp_config->frame_buffer); +} + +ulong calc_fbsize(void) +{ + return (panel_info.vl_col * panel_info.vl_row * + NBITS(panel_info.vl_bpix)) / 8; +} + +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ +} + +void tegra_lcd_early_init(const void *blob) +{ + /* + * Go with the maximum size for now. We will fix this up after + * relocation. These values are only used for memory alocation. + */ + panel_info.vl_col = LCD_MAX_WIDTH; + panel_info.vl_row = LCD_MAX_HEIGHT; + panel_info.vl_bpix = LCD_MAX_LOG2_BPP; +} + +/** + * Decode the panel information from the fdt. + * + * @param blob fdt blob + * @param config structure to store fdt config into + * @return 0 if ok, -ve on error + */ +static int fdt_decode_lcd(const void *blob, struct fdt_panel_config *config) +{ + int display_node; + + disp_config = tegra_display_get_config(); + if (!disp_config) { + debug("%s: Display controller is not configured\n", __func__); + return -1; + } + display_node = disp_config->panel_node; + if (display_node < 0) { + debug("%s: No panel configuration available\n", __func__); + return -1; + } + + config->pwm_channel = pwm_request(blob, display_node, "nvidia,pwm"); + if (config->pwm_channel < 0) { + debug("%s: Unable to request PWM channel\n", __func__); + return -1; + } + + config->cache_type = fdtdec_get_int(blob, display_node, + "nvidia,cache-type", + FDT_LCD_CACHE_WRITE_BACK_FLUSH); + + /* These GPIOs are all optional */ + fdtdec_decode_gpio(blob, display_node, "nvidia,backlight-enable-gpios", + &config->backlight_en); + fdtdec_decode_gpio(blob, display_node, "nvidia,lvds-shutdown-gpios", + &config->lvds_shutdown); + fdtdec_decode_gpio(blob, display_node, "nvidia,backlight-vdd-gpios", + &config->backlight_vdd); + fdtdec_decode_gpio(blob, display_node, "nvidia,panel-vdd-gpios", + &config->panel_vdd); + + return fdtdec_get_int_array(blob, display_node, "nvidia,panel-timings", + config->panel_timings, FDT_LCD_TIMINGS); +} + +/** + * Handle the next stage of device init + */ +static int handle_stage(const void *blob) +{ + debug("%s: stage %d\n", __func__, stage); + + /* do the things for this stage */ + switch (stage) { + case STAGE_START: + /* Initialize the Tegra display controller */ + if (tegra_display_probe(gd->fdt_blob, (void *)gd->fb_base)) { + printf("%s: Failed to probe display driver\n", + __func__); + return -1; + } + + /* get panel details */ + if (fdt_decode_lcd(blob, &config)) { + printf("No valid LCD information in device tree\n"); + return -1; + } + + /* + * It is possible that the FDT has requested that the LCD be + * disabled. We currently don't support this. It would require + * changes to U-Boot LCD subsystem to have LCD support + * compiled in but not used. An easier option might be to + * still have a frame buffer, but leave the backlight off and + * remove all mention of lcd in the stdout environment + * variable. + */ + + funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); + + fdtdec_setup_gpio(&config.panel_vdd); + fdtdec_setup_gpio(&config.lvds_shutdown); + fdtdec_setup_gpio(&config.backlight_vdd); + fdtdec_setup_gpio(&config.backlight_en); + + /* + * TODO: If fdt includes output flag we can omit this code + * since fdtdec_setup_gpio will do it for us. + */ + if (fdt_gpio_isvalid(&config.panel_vdd)) + gpio_direction_output(config.panel_vdd.gpio, 0); + if (fdt_gpio_isvalid(&config.lvds_shutdown)) + gpio_direction_output(config.lvds_shutdown.gpio, 0); + if (fdt_gpio_isvalid(&config.backlight_vdd)) + gpio_direction_output(config.backlight_vdd.gpio, 0); + if (fdt_gpio_isvalid(&config.backlight_en)) + gpio_direction_output(config.backlight_en.gpio, 0); + break; + case STAGE_PANEL_VDD: + if (fdt_gpio_isvalid(&config.panel_vdd)) + gpio_direction_output(config.panel_vdd.gpio, 1); + break; + case STAGE_LVDS: + if (fdt_gpio_isvalid(&config.lvds_shutdown)) + gpio_set_value(config.lvds_shutdown.gpio, 1); + break; + case STAGE_BACKLIGHT_VDD: + if (fdt_gpio_isvalid(&config.backlight_vdd)) + gpio_set_value(config.backlight_vdd.gpio, 1); + break; + case STAGE_PWM: + /* Enable PWM at 15/16 high, 32768 Hz with divider 1 */ + pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM); + pinmux_tristate_disable(PMUX_PINGRP_GPU); + + pwm_enable(config.pwm_channel, 32768, 0xdf, 1); + break; + case STAGE_BACKLIGHT_EN: + if (fdt_gpio_isvalid(&config.backlight_en)) + gpio_set_value(config.backlight_en.gpio, 1); + break; + case STAGE_DONE: + break; + } + + /* set up timer for next stage */ + timer_next = timer_get_us(); + if (stage < FDT_LCD_TIMINGS) + timer_next += config.panel_timings[stage] * 1000; + + /* move to next stage */ + stage++; + return 0; +} + +int tegra_lcd_check_next_stage(const void *blob, int wait) +{ + if (stage == STAGE_DONE) + return 0; + + do { + /* wait if we need to */ + debug("%s: stage %d\n", __func__, stage); + if (stage != STAGE_START) { + int delay = timer_next - timer_get_us(); + + if (delay > 0) { + if (wait) + udelay(delay); + else + return 0; + } + } + + if (handle_stage(blob)) + return -1; + } while (wait && stage != STAGE_DONE); + if (stage == STAGE_DONE) + debug("%s: LCD init complete\n", __func__); + + return 0; +} + +void lcd_enable(void) +{ + /* + * Backlight and power init will be done separately in + * tegra_lcd_check_next_stage(), which should be called in + * board_late_init(). + * + * U-Boot code supports only colour depth, selected at compile time. + * The device tree setting should match this. Otherwise the display + * will not look right, and U-Boot may crash. + */ + if (disp_config->log2_bpp != LCD_BPP) { + printf("%s: Error: LCD depth configured in FDT (%d = %dbpp)" + " must match setting of LCD_BPP (%d)\n", __func__, + disp_config->log2_bpp, disp_config->bpp, LCD_BPP); + } +} diff --git a/qemu/roms/u-boot/drivers/video/videomodes.c b/qemu/roms/u-boot/drivers/video/videomodes.c new file mode 100644 index 000000000..18c1f3d8a --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/videomodes.c @@ -0,0 +1,262 @@ +/* + * (C) Copyright 2004 + * Pierre Aubert, Staubli Faverges , <p.aubert@staubli.com> + * Copyright 2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/************************************************************************ + Get Parameters for the video mode: + The default video mode can be defined in CONFIG_SYS_DEFAULT_VIDEO_MODE. + If undefined, default video mode is set to 0x301 + Parameters can be set via the variable "videomode" in the environment. + 2 diferent ways are possible: + "videomode=301" - 301 is a hexadecimal number describing the VESA + mode. Following modes are implemented: + + Colors 640x480 800x600 1024x768 1152x864 1280x1024 + --------+--------------------------------------------- + 8 bits | 0x301 0x303 0x305 0x161 0x307 + 15 bits | 0x310 0x313 0x316 0x162 0x319 + 16 bits | 0x311 0x314 0x317 0x163 0x31A + 24 bits | 0x312 0x315 0x318 ? 0x31B + --------+--------------------------------------------- + "videomode=bootargs" + - the parameters are parsed from the bootargs. + The format is "NAME:VALUE,NAME:VALUE" etc. + Ex.: + "bootargs=video=ctfb:x:800,y:600,depth:16,pclk:25000" + Parameters not included in the list will be taken from + the default mode, which is one of the following: + mode:0 640x480x24 + mode:1 800x600x16 + mode:2 1024x768x8 + mode:3 960x720x24 + mode:4 1152x864x16 + mode:5 1280x1024x8 + + if "mode" is not provided within the parameter list, + mode:0 is assumed. + Following parameters are supported: + x xres = visible resolution horizontal + y yres = visible resolution vertical + pclk pixelclocks in pico sec + le left_marging time from sync to picture in pixelclocks + ri right_marging time from picture to sync in pixelclocks + up upper_margin time from sync to picture + lo lower_margin + hs hsync_len length of horizontal sync + vs vsync_len length of vertical sync + sync see FB_SYNC_* + vmode see FB_VMODE_* + depth Color depth in bits per pixel + All other parameters in the variable bootargs are ignored. + It is also possible to set the parameters direct in the + variable "videomode", or in another variable i.e. + "myvideo" and setting the variable "videomode=myvideo".. +****************************************************************************/ + +#include <common.h> +#include <linux/ctype.h> + +#include "videomodes.h" + +const struct ctfb_vesa_modes vesa_modes[VESA_MODES_COUNT] = { + {0x301, RES_MODE_640x480, 8}, + {0x310, RES_MODE_640x480, 15}, + {0x311, RES_MODE_640x480, 16}, + {0x312, RES_MODE_640x480, 24}, + {0x303, RES_MODE_800x600, 8}, + {0x313, RES_MODE_800x600, 15}, + {0x314, RES_MODE_800x600, 16}, + {0x315, RES_MODE_800x600, 24}, + {0x305, RES_MODE_1024x768, 8}, + {0x316, RES_MODE_1024x768, 15}, + {0x317, RES_MODE_1024x768, 16}, + {0x318, RES_MODE_1024x768, 24}, + {0x161, RES_MODE_1152x864, 8}, + {0x162, RES_MODE_1152x864, 15}, + {0x163, RES_MODE_1152x864, 16}, + {0x307, RES_MODE_1280x1024, 8}, + {0x319, RES_MODE_1280x1024, 15}, + {0x31A, RES_MODE_1280x1024, 16}, + {0x31B, RES_MODE_1280x1024, 24}, +}; +const struct ctfb_res_modes res_mode_init[RES_MODES_COUNT] = { + /* x y pixclk le ri up lo hs vs s vmode */ + {640, 480, 39721, 40, 24, 32, 11, 96, 2, 0, FB_VMODE_NONINTERLACED}, + {800, 600, 27778, 64, 24, 22, 1, 72, 2, 0, FB_VMODE_NONINTERLACED}, + {1024, 768, 15384, 168, 8, 29, 3, 144, 4, 0, FB_VMODE_NONINTERLACED}, + {960, 720, 13100, 160, 40, 32, 8, 80, 4, 0, FB_VMODE_NONINTERLACED}, + {1152, 864, 12004, 200, 64, 32, 16, 80, 4, 0, FB_VMODE_NONINTERLACED}, + {1280, 1024, 9090, 200, 48, 26, 1, 184, 3, 0, FB_VMODE_NONINTERLACED}, +}; + +/************************************************************************ + * Get Parameters for the video mode: + */ +/********************************************************************* + * returns the length to the next seperator + */ +static int +video_get_param_len (char *start, char sep) +{ + int i = 0; + while ((*start != 0) && (*start != sep)) { + start++; + i++; + } + return i; +} + +static int +video_search_param (char *start, char *param) +{ + int len, totallen, i; + char *p = start; + len = strlen (param); + totallen = len + strlen (start); + for (i = 0; i < totallen; i++) { + if (strncmp (p++, param, len) == 0) + return (i); + } + return -1; +} + +/*************************************************************** + * Get parameter via the environment as it is done for the + * linux kernel i.e: + * video=ctfb:x:800,xv:1280,y:600,yv:1024,depth:16,mode:0,pclk:25000, + * le:56,ri:48,up:26,lo:5,hs:152,vs:2,sync:0,vmode:0,accel:0 + * + * penv is a pointer to the environment, containing the string, or the name of + * another environment variable. It could even be the term "bootargs" + */ + +#define GET_OPTION(name,var) \ + if(strncmp(p,name,strlen(name))==0) { \ + val_s=p+strlen(name); \ + var=simple_strtoul(val_s, NULL, 10); \ + } + +int video_get_params (struct ctfb_res_modes *pPar, char *penv) +{ + char *p, *s, *val_s; + int i = 0; + int bpp; + int mode; + + /* first search for the environment containing the real param string */ + s = penv; + + if ((p = getenv (s)) != NULL) + s = p; + + /* + * in case of the bootargs line, we have to start + * after "video=ctfb:" + */ + i = video_search_param (s, "video=ctfb:"); + if (i >= 0) { + s += i; + s += strlen ("video=ctfb:"); + } + /* search for mode as a default value */ + p = s; + mode = 0; /* default */ + + while ((i = video_get_param_len (p, ',')) != 0) { + GET_OPTION ("mode:", mode) + p += i; + if (*p != 0) + p++; /* skip ',' */ + } + + if (mode >= RES_MODES_COUNT) + mode = 0; + + *pPar = res_mode_init[mode]; /* copy default values */ + bpp = 24 - ((mode % 3) * 8); + p = s; /* restart */ + + while ((i = video_get_param_len (p, ',')) != 0) { + GET_OPTION ("x:", pPar->xres) + GET_OPTION ("y:", pPar->yres) + GET_OPTION ("le:", pPar->left_margin) + GET_OPTION ("ri:", pPar->right_margin) + GET_OPTION ("up:", pPar->upper_margin) + GET_OPTION ("lo:", pPar->lower_margin) + GET_OPTION ("hs:", pPar->hsync_len) + GET_OPTION ("vs:", pPar->vsync_len) + GET_OPTION ("sync:", pPar->sync) + GET_OPTION ("vmode:", pPar->vmode) + GET_OPTION ("pclk:", pPar->pixclock) + GET_OPTION ("depth:", bpp) + p += i; + if (*p != 0) + p++; /* skip ',' */ + } + return bpp; +} + +/* + * Parse the 'video-mode' environment variable + * + * Example: "video-mode=fslfb:1280x1024-32@60,monitor=dvi". See + * doc/README.video for more information on how to set the variable. + * + * @xres: returned value of X-resolution + * @yres: returned value of Y-resolution + * @depth: returned value of color depth + * @freq: returned value of monitor frequency + * @options: pointer to any remaining options, or NULL + * + * Returns 1 if valid values were found, 0 otherwise + */ +int video_get_video_mode(unsigned int *xres, unsigned int *yres, + unsigned int *depth, unsigned int *freq, const char **options) +{ + char *p = getenv("video-mode"); + if (!p) + return 0; + + /* Skip over the driver name, which we don't care about. */ + p = strchr(p, ':'); + if (!p) + return 0; + + /* Get the X-resolution*/ + while (*p && !isdigit(*p)) + p++; + *xres = simple_strtoul(p, &p, 10); + if (!*xres) + return 0; + + /* Get the Y-resolution */ + while (*p && !isdigit(*p)) + p++; + *yres = simple_strtoul(p, &p, 10); + if (!*yres) + return 0; + + /* Get the depth */ + while (*p && !isdigit(*p)) + p++; + *depth = simple_strtoul(p, &p, 10); + if (!*depth) + return 0; + + /* Get the frequency */ + while (*p && !isdigit(*p)) + p++; + *freq = simple_strtoul(p, &p, 10); + if (!*freq) + return 0; + + /* Find the extra options, if any */ + p = strchr(p, ','); + *options = p ? p + 1 : NULL; + + return 1; +} diff --git a/qemu/roms/u-boot/drivers/video/videomodes.h b/qemu/roms/u-boot/drivers/video/videomodes.h new file mode 100644 index 000000000..d83993a56 --- /dev/null +++ b/qemu/roms/u-boot/drivers/video/videomodes.h @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2004 + * Pierre Aubert, Staubli Faverges , <p.aubert@staubli.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#ifndef CONFIG_SYS_DEFAULT_VIDEO_MODE +#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x301 +#endif + +/* Some mode definitions */ +#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */ +#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */ +#define FB_SYNC_EXT 4 /* external sync */ +#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */ +#define FB_SYNC_BROADCAST 16 /* broadcast video timings */ + /* vtotal = 144d/288n/576i => PAL */ + /* vtotal = 121d/242n/484i => NTSC */ +#define FB_SYNC_ON_GREEN 32 /* sync on green */ +#define FB_VMODE_NONINTERLACED 0 /* non interlaced */ +#define FB_VMODE_INTERLACED 1 /* interlaced */ +#define FB_VMODE_DOUBLE 2 /* double scan */ +#define FB_VMODE_MASK 255 + +#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */ +#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */ +#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */ + + +/****************************************************************** + * Resolution Struct + ******************************************************************/ +struct ctfb_res_modes { + int xres; /* visible resolution */ + int yres; + /* Timing: All values in pixclocks, except pixclock (of course) */ + int pixclock; /* pixel clock in ps (pico seconds) */ + int left_margin; /* time from sync to picture */ + int right_margin; /* time from picture to sync */ + int upper_margin; /* time from sync to picture */ + int lower_margin; + int hsync_len; /* length of horizontal sync */ + int vsync_len; /* length of vertical sync */ + int sync; /* see FB_SYNC_* */ + int vmode; /* see FB_VMODE_* */ +}; + +/****************************************************************** + * Vesa Mode Struct + ******************************************************************/ +struct ctfb_vesa_modes { + int vesanr; /* Vesa number as in LILO (VESA Nr + 0x200} */ + int resindex; /* index to resolution struct */ + int bits_per_pixel; /* bpp */ +}; + +#define RES_MODE_640x480 0 +#define RES_MODE_800x600 1 +#define RES_MODE_1024x768 2 +#define RES_MODE_960_720 3 +#define RES_MODE_1152x864 4 +#define RES_MODE_1280x1024 5 +#define RES_MODES_COUNT 6 + +#define VESA_MODES_COUNT 19 + +extern const struct ctfb_vesa_modes vesa_modes[]; +extern const struct ctfb_res_modes res_mode_init[]; + +int video_get_params (struct ctfb_res_modes *pPar, char *penv); + +int video_get_video_mode(unsigned int *xres, unsigned int *yres, + unsigned int *depth, unsigned int *freq, const char **options); |