diff options
Diffstat (limited to 'qemu/roms/u-boot/board/xilinx')
17 files changed, 638 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/board/xilinx/microblaze-generic/Makefile b/qemu/roms/u-boot/board/xilinx/microblaze-generic/Makefile new file mode 100644 index 000000000..22c8bef11 --- /dev/null +++ b/qemu/roms/u-boot/board/xilinx/microblaze-generic/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = microblaze-generic.o diff --git a/qemu/roms/u-boot/board/xilinx/microblaze-generic/config.mk b/qemu/roms/u-boot/board/xilinx/microblaze-generic/config.mk new file mode 100644 index 000000000..36bdd9634 --- /dev/null +++ b/qemu/roms/u-boot/board/xilinx/microblaze-generic/config.mk @@ -0,0 +1,18 @@ +# +# (C) Copyright 2007 Michal Simek +# +# Michal SIMEK <monstr@monstr.eu> +# +# SPDX-License-Identifier: GPL-2.0+ +# +# CAUTION: This file is a faked configuration !!! +# There is no real target for the microblaze-generic +# configuration. You have to replace this file with +# the generated file from your Xilinx design flow. +# + +CONFIG_SYS_TEXT_BASE = 0x29000000 + +PLATFORM_CPPFLAGS += -mno-xl-soft-mul +PLATFORM_CPPFLAGS += -mno-xl-soft-div +PLATFORM_CPPFLAGS += -mxl-barrel-shift diff --git a/qemu/roms/u-boot/board/xilinx/microblaze-generic/microblaze-generic.c b/qemu/roms/u-boot/board/xilinx/microblaze-generic/microblaze-generic.c new file mode 100644 index 000000000..42a8d0c40 --- /dev/null +++ b/qemu/roms/u-boot/board/xilinx/microblaze-generic/microblaze-generic.c @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2007 Michal Simek + * + * Michal SIMEK <monstr@monstr.eu> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* This is a board specific file. It's OK to include board specific + * header files */ + +#include <common.h> +#include <config.h> +#include <netdev.h> +#include <asm/processor.h> +#include <asm/microblaze_intc.h> +#include <asm/asm.h> +#include <asm/gpio.h> + +#ifdef CONFIG_XILINX_GPIO +static int reset_pin = -1; +#endif + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ +#ifdef CONFIG_XILINX_GPIO + if (reset_pin != -1) + gpio_direction_output(reset_pin, 1); +#endif + +#ifdef CONFIG_XILINX_TB_WATCHDOG + hw_watchdog_disable(); +#endif + + puts ("Reseting board\n"); + __asm__ __volatile__ (" mts rmsr, r0;" \ + "bra r0"); + + return 0; +} + +int gpio_init (void) +{ +#ifdef CONFIG_XILINX_GPIO + reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1); + if (reset_pin != -1) + gpio_request(reset_pin, "reset_pin"); +#endif + return 0; +} + +void board_init(void) +{ + gpio_init(); +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; + +#ifdef CONFIG_XILINX_AXIEMAC + ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, + XILINX_AXIDMA_BASEADDR); +#endif + +#ifdef CONFIG_XILINX_EMACLITE + u32 txpp = 0; + u32 rxpp = 0; +# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG + txpp = 1; +# endif +# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG + rxpp = 1; +# endif + ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, + txpp, rxpp); +#endif + +#ifdef CONFIG_XILINX_LL_TEMAC +# ifdef XILINX_LLTEMAC_BASEADDR +# ifdef XILINX_LLTEMAC_FIFO_BASEADDR + ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR, + XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR); +# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR +# if XILINX_LLTEMAC_SDMA_USE_DCR == 1 + ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR, + XILINX_LL_TEMAC_M_SDMA_DCR, + XILINX_LLTEMAC_SDMA_CTRL_BASEADDR); +# else + ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR, + XILINX_LL_TEMAC_M_SDMA_PLB, + XILINX_LLTEMAC_SDMA_CTRL_BASEADDR); +# endif +# endif +# endif +# ifdef XILINX_LLTEMAC_BASEADDR1 +# ifdef XILINX_LLTEMAC_FIFO_BASEADDR1 + ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1, + XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR1); +# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1 +# if XILINX_LLTEMAC_SDMA_USE_DCR == 1 + ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1, + XILINX_LL_TEMAC_M_SDMA_DCR, + XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1); +# else + ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1, + XILINX_LL_TEMAC_M_SDMA_PLB, + XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1); +# endif +# endif +# endif +#endif + + return ret; +} diff --git a/qemu/roms/u-boot/board/xilinx/microblaze-generic/xparameters.h b/qemu/roms/u-boot/board/xilinx/microblaze-generic/xparameters.h new file mode 100644 index 000000000..d6d0d679e --- /dev/null +++ b/qemu/roms/u-boot/board/xilinx/microblaze-generic/xparameters.h @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2007 Michal Simek + * + * Michal SIMEK <monstr@monstr.eu> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * CAUTION: This file is a faked configuration !!! + * There is no real target for the microblaze-generic + * configuration. You have to replace this file with + * the generated file from your Xilinx design flow. + */ + +#define XILINX_BOARD_NAME microblaze-generic + +/* System Clock Frequency */ +#define XILINX_CLOCK_FREQ 100000000 + +/* Microblaze is microblaze_0 */ +#define XILINX_USE_MSR_INSTR 1 +#define XILINX_FSL_NUMBER 3 + +/* Interrupt controller is opb_intc_0 */ +#define XILINX_INTC_BASEADDR 0x41200000 +#define XILINX_INTC_NUM_INTR_INPUTS 6 + +/* Timer pheriphery is opb_timer_1 */ +#define XILINX_TIMER_BASEADDR 0x41c00000 +#define XILINX_TIMER_IRQ 0 + +/* Uart pheriphery is RS232_Uart */ +#define XILINX_UARTLITE_BASEADDR 0x40600000 +#define XILINX_UARTLITE_BAUDRATE 115200 + +/* IIC pheriphery is IIC_EEPROM */ +#define XILINX_IIC_0_BASEADDR 0x40800000 +#define XILINX_IIC_0_FREQ 100000 +#define XILINX_IIC_0_BIT 0 + +/* GPIO is LEDs_4Bit*/ +#define XILINX_GPIO_BASEADDR 0x40000000 + +/* Flash Memory is FLASH_2Mx32 */ +#define XILINX_FLASH_START 0x2c000000 +#define XILINX_FLASH_SIZE 0x00800000 + +/* Main Memory is DDR_SDRAM_64Mx32 */ +#define XILINX_RAM_START 0x28000000 +#define XILINX_RAM_SIZE 0x04000000 + +/* Sysace Controller is SysACE_CompactFlash */ +#define XILINX_SYSACE_BASEADDR 0x41800000 +#define XILINX_SYSACE_HIGHADDR 0x4180ffff +#define XILINX_SYSACE_MEM_WIDTH 16 + +/* Ethernet controller is Ethernet_MAC */ +#define XILINX_EMACLITE_BASEADDR 0x40C00000 + +/* LL_TEMAC Ethernet controller */ +#define XILINX_LLTEMAC_BASEADDR 0x44000000 +#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR 0x42000180 +#define XILINX_LLTEMAC_BASEADDR1 0x44200000 +#define XILINX_LLTEMAC_FIFO_BASEADDR1 0x42100000 + +/* Watchdog IP is wxi_timebase_wdt_0 */ +#define XILINX_WATCHDOG_BASEADDR 0x50000000 +#define XILINX_WATCHDOG_IRQ 1 diff --git a/qemu/roms/u-boot/board/xilinx/ml507/Makefile b/qemu/roms/u-boot/board/xilinx/ml507/Makefile new file mode 100644 index 000000000..9a3809f3c --- /dev/null +++ b/qemu/roms/u-boot/board/xilinx/ml507/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2008 +# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es +# This work has been supported by: Qtechnology http://qtec.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ml507.o + +include $(srctree)/board/xilinx/ppc440-generic/Makefile diff --git a/qemu/roms/u-boot/board/xilinx/ml507/ml507.c b/qemu/roms/u-boot/board/xilinx/ml507/ml507.c new file mode 100644 index 000000000..83b764b73 --- /dev/null +++ b/qemu/roms/u-boot/board/xilinx/ml507/ml507.c @@ -0,0 +1,17 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <config.h> +#include <common.h> +#include <asm/processor.h> + + +int checkboard(void) +{ + puts("Xilinx ML507 Board\n"); + return 0; +} diff --git a/qemu/roms/u-boot/board/xilinx/ml507/xparameters.h b/qemu/roms/u-boot/board/xilinx/ml507/xparameters.h new file mode 100644 index 000000000..e30e592bb --- /dev/null +++ b/qemu/roms/u-boot/board/xilinx/ml507/xparameters.h @@ -0,0 +1,23 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * based on xparameters-ml507.h by Xilinx + * + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef XPARAMETER_H +#define XPARAMETER_H + +#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 +#define XPAR_IIC_EEPROM_BASEADDR 0x81600000 +#define XPAR_INTC_0_BASEADDR 0x81800000 +#define XPAR_UARTLITE_0_BASEADDR 0x84000000 +#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 +#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 +#define XPAR_UARTLITE_0_BAUDRATE 9600 + +#endif diff --git a/qemu/roms/u-boot/board/xilinx/ppc405-generic/Makefile b/qemu/roms/u-boot/board/xilinx/ppc405-generic/Makefile new file mode 100644 index 000000000..c9da87065 --- /dev/null +++ b/qemu/roms/u-boot/board/xilinx/ppc405-generic/Makefile @@ -0,0 +1,12 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es +# Work supported by Qtechnology http://www.qtec.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o diff --git a/qemu/roms/u-boot/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c b/qemu/roms/u-boot/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c new file mode 100644 index 000000000..e3dd468f1 --- /dev/null +++ b/qemu/roms/u-boot/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <config.h> +#include <common.h> +#include <asm/processor.h> + +ulong __get_PCI_freq(void) +{ + return 0; +} + +ulong get_PCI_freq(void) __attribute__((weak, alias("__get_PCI_freq"))); + +int __board_pre_init(void) +{ + return 0; +} +int board_pre_init(void) __attribute__((weak, alias("__board_pre_init"))); + +int __checkboard(void) +{ + puts("Xilinx PPC405 Generic Board\n"); + return 0; +} +int checkboard(void) __attribute__((weak, alias("__checkboard"))); + +phys_size_t __initdram(int board_type) +{ + return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR, + CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024); +} +phys_size_t initdram(int) __attribute__((weak, alias("__initdram"))); + +void __get_sys_info(sys_info_t *sysInfo) +{ + sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; + sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; + sysInfo->freqPCI = 0; + + return; +} +void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info"))); diff --git a/qemu/roms/u-boot/board/xilinx/ppc405-generic/xparameters.h b/qemu/roms/u-boot/board/xilinx/ppc405-generic/xparameters.h new file mode 100644 index 000000000..f0ff78fca --- /dev/null +++ b/qemu/roms/u-boot/board/xilinx/ppc405-generic/xparameters.h @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * based on xparameters-ml507.h by Xilinx + * + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef XPARAMETER_H +#define XPARAMETER_H + +#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 +#define XPAR_IIC_EEPROM_BASEADDR 0x81600000 +#define XPAR_INTC_0_BASEADDR 0x81800000 +#define XPAR_SPI_0_BASEADDR 0x83400000 +#define XPAR_UARTLITE_0_BASEADDR 0x84000000 +#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 +#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 +#define XPAR_UARTLITE_0_BAUDRATE 9600 +#define XPAR_SPI_0_NUM_TRANSFER_BITS 8 + +#endif diff --git a/qemu/roms/u-boot/board/xilinx/ppc440-generic/Makefile b/qemu/roms/u-boot/board/xilinx/ppc440-generic/Makefile new file mode 100644 index 000000000..0acd95d6e --- /dev/null +++ b/qemu/roms/u-boot/board/xilinx/ppc440-generic/Makefile @@ -0,0 +1,13 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es +# Work supported by Qtechnology http://www.qtec.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o +extra-y += ../../xilinx/ppc440-generic/init.o diff --git a/qemu/roms/u-boot/board/xilinx/ppc440-generic/init.S b/qemu/roms/u-boot/board/xilinx/ppc440-generic/init.S new file mode 100644 index 000000000..4598a3768 --- /dev/null +++ b/qemu/roms/u-boot/board/xilinx/ppc440-generic/init.S @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <ppc_asm.tmpl> +#include <config.h> +#include <asm/mmu.h> + +.section .bootpg,"ax" +.globl tlbtab + +tlbtab: +tlbtab_start +tlbentry(0x00000000, SZ_256M, 0x00000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0x10000000, SZ_256M, 0x10000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0x20000000, SZ_256M, 0x20000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0x30000000, SZ_256M, 0x30000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0x40000000, SZ_256M, 0x40000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0x50000000, SZ_256M, 0x50000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0x60000000, SZ_256M, 0x60000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0x70000000, SZ_256M, 0x70000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0x80000000, SZ_256M, 0x80000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0x90000000, SZ_256M, 0x90000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0xa0000000, SZ_256M, 0xa0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0xb0000000, SZ_256M, 0xb0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0xc0000000, SZ_256M, 0xc0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0xd0000000, SZ_256M, 0xd0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0xe0000000, SZ_256M, 0xe0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0xf0000000, SZ_256M, 0xf0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbtab_end diff --git a/qemu/roms/u-boot/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c b/qemu/roms/u-boot/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c new file mode 100644 index 000000000..74df2f4ff --- /dev/null +++ b/qemu/roms/u-boot/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <config.h> +#include <common.h> +#include <asm/processor.h> + +int __board_pre_init(void) +{ + return 0; +} +int board_pre_init(void) __attribute__((weak, alias("__board_pre_init"))); + +int __checkboard(void) +{ + puts("Xilinx PPC440 Generic Board\n"); + return 0; +} +int checkboard(void) __attribute__((weak, alias("__checkboard"))); + +phys_size_t __initdram(int board_type) +{ + return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR, + CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024); +} +phys_size_t initdram(int) __attribute__((weak, alias("__initdram"))); + +void __get_sys_info(sys_info_t *sysInfo) +{ + sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; + sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; + sysInfo->freqPCI = 0; + + return; +} +void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info"))); diff --git a/qemu/roms/u-boot/board/xilinx/ppc440-generic/xparameters.h b/qemu/roms/u-boot/board/xilinx/ppc440-generic/xparameters.h new file mode 100644 index 000000000..e30e592bb --- /dev/null +++ b/qemu/roms/u-boot/board/xilinx/ppc440-generic/xparameters.h @@ -0,0 +1,23 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * based on xparameters-ml507.h by Xilinx + * + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef XPARAMETER_H +#define XPARAMETER_H + +#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 +#define XPAR_IIC_EEPROM_BASEADDR 0x81600000 +#define XPAR_INTC_0_BASEADDR 0x81800000 +#define XPAR_UARTLITE_0_BASEADDR 0x84000000 +#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 +#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 +#define XPAR_UARTLITE_0_BAUDRATE 9600 + +#endif diff --git a/qemu/roms/u-boot/board/xilinx/zynq/Makefile b/qemu/roms/u-boot/board/xilinx/zynq/Makefile new file mode 100644 index 000000000..3f19a1cd8 --- /dev/null +++ b/qemu/roms/u-boot/board/xilinx/zynq/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := board.o +obj-$(CONFIG_SPL_BUILD) += ps7_init.o diff --git a/qemu/roms/u-boot/board/xilinx/zynq/board.c b/qemu/roms/u-boot/board/xilinx/zynq/board.c new file mode 100644 index 000000000..c8cc2bc93 --- /dev/null +++ b/qemu/roms/u-boot/board/xilinx/zynq/board.c @@ -0,0 +1,162 @@ +/* + * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <netdev.h> +#include <zynqpl.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_FPGA +xilinx_desc fpga; + +/* It can be done differently */ +xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); +xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); +xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); +xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); +xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); +xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); +#endif + +int board_init(void) +{ +#ifdef CONFIG_FPGA + u32 idcode; + + idcode = zynq_slcr_get_idcode(); + + switch (idcode) { + case XILINX_ZYNQ_7010: + fpga = fpga010; + break; + case XILINX_ZYNQ_7015: + fpga = fpga015; + break; + case XILINX_ZYNQ_7020: + fpga = fpga020; + break; + case XILINX_ZYNQ_7030: + fpga = fpga030; + break; + case XILINX_ZYNQ_7045: + fpga = fpga045; + break; + case XILINX_ZYNQ_7100: + fpga = fpga100; + break; + } +#endif + +#ifdef CONFIG_FPGA + fpga_init(); + fpga_add(fpga_xilinx, &fpga); +#endif + + return 0; +} + +int board_late_init(void) +{ + switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { + case ZYNQ_BM_NOR: + setenv("modeboot", "norboot"); + break; + case ZYNQ_BM_SD: + setenv("modeboot", "sdboot"); + break; + case ZYNQ_BM_JTAG: + setenv("modeboot", "jtagboot"); + break; + default: + setenv("modeboot", ""); + break; + } + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + u32 ret = 0; + +#ifdef CONFIG_XILINX_AXIEMAC + ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, + XILINX_AXIDMA_BASEADDR); +#endif +#ifdef CONFIG_XILINX_EMACLITE + u32 txpp = 0; + u32 rxpp = 0; +# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG + txpp = 1; +# endif +# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG + rxpp = 1; +# endif + ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, + txpp, rxpp); +#endif + +#if defined(CONFIG_ZYNQ_GEM) +# if defined(CONFIG_ZYNQ_GEM0) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, + CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); +# endif +# if defined(CONFIG_ZYNQ_GEM1) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, + CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); +# endif +#endif + return ret; +} + +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bd) +{ + int ret = 0; + +#if defined(CONFIG_ZYNQ_SDHCI) +# if defined(CONFIG_ZYNQ_SDHCI0) + ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0); +# endif +# if defined(CONFIG_ZYNQ_SDHCI1) + ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1); +# endif +#endif + return ret; +} +#endif + +int dram_init(void) +{ +#ifdef CONFIG_OF_CONTROL + int node; + fdt_addr_t addr; + fdt_size_t size; + const void *blob = gd->fdt_blob; + + node = fdt_node_offset_by_prop_value(blob, -1, "device_type", + "memory", 7); + if (node == -FDT_ERR_NOTFOUND) { + debug("ZYNQ DRAM: Can't get memory node\n"); + return -1; + } + addr = fdtdec_get_addr_size(blob, node, "reg", &size); + if (addr == FDT_ADDR_T_NONE || size == 0) { + debug("ZYNQ DRAM: Can't get base address or size\n"); + return -1; + } + gd->ram_size = size; +#else + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; +#endif + zynq_ddrc_init(); + + return 0; +} diff --git a/qemu/roms/u-boot/board/xilinx/zynq/ps7_init.c b/qemu/roms/u-boot/board/xilinx/zynq/ps7_init.c new file mode 100644 index 000000000..c47da09b9 --- /dev/null +++ b/qemu/roms/u-boot/board/xilinx/zynq/ps7_init.c @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2014 Xilinx, Inc. Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/arch/spl.h> + +__weak void ps7_init(void) +{ + puts("Please copy ps7_init.c/h from hw project\n"); +} |