summaryrefslogtreecommitdiffstats
path: root/qemu/roms/u-boot/board/xes/xpedite537x
diff options
context:
space:
mode:
Diffstat (limited to 'qemu/roms/u-boot/board/xes/xpedite537x')
-rw-r--r--qemu/roms/u-boot/board/xes/xpedite537x/Makefile13
-rw-r--r--qemu/roms/u-boot/board/xes/xpedite537x/ddr.c234
-rw-r--r--qemu/roms/u-boot/board/xes/xpedite537x/law.c26
-rw-r--r--qemu/roms/u-boot/board/xes/xpedite537x/tlb.c83
-rw-r--r--qemu/roms/u-boot/board/xes/xpedite537x/xpedite537x.c82
5 files changed, 0 insertions, 438 deletions
diff --git a/qemu/roms/u-boot/board/xes/xpedite537x/Makefile b/qemu/roms/u-boot/board/xes/xpedite537x/Makefile
deleted file mode 100644
index 2dca0d751..000000000
--- a/qemu/roms/u-boot/board/xes/xpedite537x/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Copyright 2008 Extreme Engineering Solutions, Inc.
-# Copyright 2007 Freescale Semiconductor, Inc.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += xpedite537x.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/qemu/roms/u-boot/board/xes/xpedite537x/ddr.c b/qemu/roms/u-boot/board/xes/xpedite537x/ddr.c
deleted file mode 100644
index 56b5a187d..000000000
--- a/qemu/roms/u-boot/board/xes/xpedite537x/ddr.c
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
-{
- i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
- sizeof(ddr2_spd_eeprom_t));
-}
-
-/*
- * There are four board-specific SDRAM timing parameters which must be
- * calculated based on the particular PCB artwork. These are:
- * 1.) CPO (Read Capture Delay)
- * - TIMING_CFG_2 register
- * Source: Calculation based on board trace lengths and
- * chip-specific internal delays.
- * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
- * - TIMING_CFG_2 register
- * Source: Calculation based on board trace lengths.
- * Unless clock and DQ lanes are very different
- * lengths (>2"), this should be set to the nominal value
- * of 1/2 clock delay.
- * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
- * - DDR_SDRAM_CLK_CNTL register
- * Source: Signal Integrity Simulations
- * 4.) 2T Timing on Addr/Ctl
- * - TIMING_CFG_2 register
- * Source: Signal Integrity Simulations
- * Usually only needed with heavy load/very high speed (>DDR2-800)
- *
- * ====== XPedite5370 DDR2-600 read delay calculations ======
- *
- * See Freescale's App Note AN2583 as refrence. This document also
- * contains the chip-specific delays for 8548E, 8572, etc.
- *
- * For MPC8572E
- * Minimum chip delay (Ch 0): 1.372ns
- * Maximum chip delay (Ch 0): 2.914ns
- * Minimum chip delay (Ch 1): 1.220ns
- * Maximum chip delay (Ch 1): 2.595ns
- *
- * CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps
- *
- * Minimum delay calc (Ch 0):
- * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
- * 2.3" * 180 - 400ps + 1.9" * 180 + 2080ps + 1372ps
- * = 3808ps
- * = 3.808ns
- *
- * Maximum delay calc (Ch 0):
- * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
- * 2.3" * 180 + 400ps + 2.4" * 180 + 2080ps + 2914ps
- * = 6240ps
- * = 6.240ns
- *
- * Minimum delay calc (Ch 1):
- * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
- * 1.46" * 180- 400ps + 0.7" * 180 + 2080ps + 1220ps
- * = 3288ps
- * = 3.288ns
- *
- * Maximum delay calc (Ch 1):
- * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
- * 1.46" * 180+ 400ps + 1.1" * 180 + 2080ps + 2595ps
- * = 5536ps
- * = 5.536ns
- *
- * Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target)
- * This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
- * Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target)
- * This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7)
- *
- *
- * ====== XPedite5370 DDR2-800 read delay calculations ======
- *
- * See Freescale's App Note AN2583 as refrence. This document also
- * contains the chip-specific delays for 8548E, 8572, etc.
- *
- * For MPC8572E
- * Minimum chip delay (Ch 0): 1.372ns
- * Maximum chip delay (Ch 0): 2.914ns
- * Minimum chip delay (Ch 1): 1.220ns
- * Maximum chip delay (Ch 1): 2.595ns
- *
- * CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps
- *
- * Minimum delay calc (Ch 0):
- * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
- * 2.3" * 180 - 350ps + 1.9" * 180 + 1563ps + 1372ps
- * = 3341ps
- * = 3.341ns
- *
- * Maximum delay calc (Ch 0):
- * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
- * 2.3" * 180 + 350ps + 2.4" * 180 + 1563ps + 2914ps
- * = 5673ps
- * = 5.673ns
- *
- * Minimum delay calc (Ch 1):
- * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
- * 1.46" * 180- 350ps + 0.7" * 180 + 1563ps + 1220ps
- * = 2822ps
- * = 2.822ns
- *
- * Maximum delay calc (Ch 1):
- * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
- * 1.46" * 180+ 350ps + 1.1" * 180 + 1563ps + 2595ps
- * = 4968ps
- * = 4.968ns
- *
- * Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target)
- * This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9)
- * Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target)
- * This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
- *
- * Write latency (WR_DATA_DELAY) is calculated by doing the following:
- *
- * The DDR SDRAM specification requires DQS be received no sooner than
- * 75% of an SDRAM clock period—and no later than 125% of a clock
- * period—from the capturing clock edge of the command/address at the
- * SDRAM.
- *
- * Based on the above tracelengths, the following are calculated:
- * Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns
- * Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns
- * Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns
- * Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns
- *
- * Difference in arrival time CLK vs. DQS:
- * Ch. 0 0.072ns
- * Ch. 1 0.138ns
- *
- * Both of these values are much less than 25% of the clock
- * period at DDR2-600 or DDR2-800, so no additional delay is needed over
- * the 1/2 cycle which normally aligns the first DQS transition
- * exactly WL (CAS latency minus one cycle) after the CAS strobe.
- * See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's
- * terminology corresponds to exactly one clock period delay after
- * the CAS strobe. (due to the fact that the "delay" is referenced
- * from the *falling* edge of the CLK, just after the rising edge
- * which the CAS strobe is latched on.
- */
-
-typedef struct board_memctl_options {
- uint16_t datarate_mhz_low;
- uint16_t datarate_mhz_high;
- uint8_t clk_adjust;
- uint8_t cpo_override;
- uint8_t write_data_delay;
-} board_memctl_options_t;
-
-static struct board_memctl_options bopts_ctrl[][2] = {
- {
- /* Controller 0 */
- {
- /* DDR2 600/667 */
- .datarate_mhz_low = 500,
- .datarate_mhz_high = 750,
- .clk_adjust = 5,
- .cpo_override = 8,
- .write_data_delay = 2,
- },
- {
- /* DDR2 800 */
- .datarate_mhz_low = 750,
- .datarate_mhz_high = 850,
- .clk_adjust = 5,
- .cpo_override = 9,
- .write_data_delay = 2,
- },
- },
- {
- /* Controller 1 */
- {
- /* DDR2 600/667 */
- .datarate_mhz_low = 500,
- .datarate_mhz_high = 750,
- .clk_adjust = 5,
- .cpo_override = 7,
- .write_data_delay = 2,
- },
- {
- /* DDR2 800 */
- .datarate_mhz_low = 750,
- .datarate_mhz_high = 850,
- .clk_adjust = 5,
- .cpo_override = 8,
- .write_data_delay = 2,
- },
- },
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
- sys_info_t sysinfo;
- int i;
- unsigned int datarate;
-
- get_sys_info(&sysinfo);
- datarate = sysinfo.freq_ddrbus / 1000 / 1000;
-
- for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
- if ((bopts[i].datarate_mhz_low <= datarate) &&
- (bopts[i].datarate_mhz_high >= datarate)) {
- debug("controller %d:\n", ctrl_num);
- debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
- debug(" cpo = %d\n", bopts[i].cpo_override);
- debug(" write_data_delay = %d\n",
- bopts[i].write_data_delay);
- popts->clk_adjust = bopts[i].clk_adjust;
- popts->cpo_override = bopts[i].cpo_override;
- popts->write_data_delay = bopts[i].write_data_delay;
- }
- }
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
diff --git a/qemu/roms/u-boot/board/xes/xpedite537x/law.c b/qemu/roms/u-boot/board/xes/xpedite537x/law.c
deleted file mode 100644
index 092c9ac1e..000000000
--- a/qemu/roms/u-boot/board/xes/xpedite537x/law.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/qemu/roms/u-boot/board/xes/xpedite537x/tlb.c b/qemu/roms/u-boot/board/xes/xpedite537x/tlb.c
deleted file mode 100644
index 6d83f859e..000000000
--- a/qemu/roms/u-boot/board/xes/xpedite537x/tlb.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* W**G* - NOR flashes */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
- 0, 0, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
- /* *I*G* - NAND flash */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_1M, 1),
-
- /* **M** - Boot page for secondary processors */
- SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
- 0, 3, BOOKE_PAGESZ_4K, 1),
-
-#ifdef CONFIG_PCIE1
- /* *I*G* - PCIe */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_1G, 1),
-#endif
-
-#ifdef CONFIG_PCIE2
- /* *I*G* - PCIe */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#ifdef CONFIG_PCIE3
- /* *I*G* - PCIe */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256M, 1),
-#endif
-
-#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
- /* *I*G* - PCIe */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_64M, 1),
-#endif
-
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/qemu/roms/u-boot/board/xes/xpedite537x/xpedite537x.c b/qemu/roms/u-boot/board/xes/xpedite537x/xpedite537x.c
deleted file mode 100644
index efd563b26..000000000
--- a/qemu/roms/u-boot/board/xes/xpedite537x/xpedite537x.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright 2008 Extreme Engineering Solutions, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <pca953x.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void ft_board_pci_setup(void *blob, bd_t *bd);
-
-static void flash_cs_fixup(void)
-{
- int flash_sel;
-
- /*
- * Print boot dev and swap flash flash chip selects if booted from 2nd
- * flash. Swapping chip selects presents user with a common memory
- * map regardless of which flash was booted from.
- */
- flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
- CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
- printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
-
- if (flash_sel) {
- set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
- set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
-
- set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
- set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
- }
-}
-
-int board_early_init_r(void)
-{
- /* Initialize PCA9557 devices */
- pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
- pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
- pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
- pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
-
- /*
- * Remap NOR flash region to caching-inhibited
- * so that flash can be erased/programmed properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- /* Invalidate existing TLB entry for NOR flash */
- disable_tlb(0);
- set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
- (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_256M, 1);
-
- flash_cs_fixup();
-
- return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-#ifdef CONFIG_PCI
- ft_board_pci_setup(blob, bd);
-#endif
- ft_cpu_setup(blob, bd);
-}
-#endif