diff options
Diffstat (limited to 'qemu/roms/u-boot/board/xes/xpedite1000')
| -rw-r--r-- | qemu/roms/u-boot/board/xes/xpedite1000/Makefile | 9 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/xes/xpedite1000/README | 82 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/xes/xpedite1000/config.mk | 20 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/xes/xpedite1000/init.S | 33 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/xes/xpedite1000/u-boot.lds.debug | 126 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/xes/xpedite1000/xpedite1000.c | 184 |
6 files changed, 454 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/board/xes/xpedite1000/Makefile b/qemu/roms/u-boot/board/xes/xpedite1000/Makefile new file mode 100644 index 000000000..308de91c9 --- /dev/null +++ b/qemu/roms/u-boot/board/xes/xpedite1000/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2002-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = xpedite1000.o +extra-y += init.o diff --git a/qemu/roms/u-boot/board/xes/xpedite1000/README b/qemu/roms/u-boot/board/xes/xpedite1000/README new file mode 100644 index 000000000..1da8b800b --- /dev/null +++ b/qemu/roms/u-boot/board/xes/xpedite1000/README @@ -0,0 +1,82 @@ + XES XPedite1000 Board + + Last Update: December 29, 2003 +======================================================================= + +This file contains some handy info regarding U-Boot and the XES +XPedite1000 PPC440GX PrPMC board. See the README.ppc440 for additional +information. + + +SWITCH SETTINGS & JUMPERS +========================== + +Jumpers selected for AMD29LV040B flash part as the boot flash. + + +I2C Strap EEPROM & Environment Settings +======================================= + +The XPedite1000 uses a single I2C eeprom for the 440 strappings and for +the environment variables. The first page (256 bytes) contains the +strappings and the 2 EMAC HW Ethernet addresses. Be careful not to +change the 1st page of the EEPROM! Unpopulated jumper J560 can get you +out of trouble as it disables the strapping read from EEPROM. + +I2C probe +===================== + +The i2c utilities work and have been tested on Rev B. of the 440GX. See +README.ebony for more information about i2c probing with the 440. + + +GETTING OUT OF I2C TROUBLE +=========================== + +(Direct quote from README.ebony) +If you're like me ... you may have screwed up your bootstrap serial +eeprom ... or worse, your SPD eeprom when experimenting with the +i2c commands. If so, here are some ideas on how to get out of +trouble: + +Serial bootstrap eeprom corruption: +----------------------------------- +Power down the board and set the following straps: + +J560 - closed + +This will select the default sys0 and sys1 settings (the serial +eeproms are not used). Then power up the board and fix the serial +eeprom using the 'i2c mm' command. Here are the values I currently +use: + +=> i2c md 50 0 10 + +0000: 85 7d 42 06 07 80 11 00 00 00 00 00 00 00 00 00 .}B............. + +Once you have the eeproms set correctly change the +J560 straps as you desire. + + +PPC440GX Ethernet EMACs +======================= + +The XES XPedite1000 uses emac 2 & 3 and ignores emac 0 & 1. PHYs are connected +only to emac 2 & 3. The HW Ethernet addresses are read from the i2c eeprom and +placed in the bd info structure for enet2addr and enet3addr. The ethernet driver +senses that enetaddr and enet1addr are 0's and does not use them. + +As of this writing gigabit ethernet and the TCPIP acceleration hardware is not +supported. + + +Flash Support +============= + +As of this writing, there is support for the 1/2mb boot flash only. User flash +is not yet supported. + + +Regards, +--Travis +<travis.sawyer@sandburst.com> diff --git a/qemu/roms/u-boot/board/xes/xpedite1000/config.mk b/qemu/roms/u-boot/board/xes/xpedite1000/config.mk new file mode 100644 index 000000000..ec7651e42 --- /dev/null +++ b/qemu/roms/u-boot/board/xes/xpedite1000/config.mk @@ -0,0 +1,20 @@ +# +# (C) Copyright 2002-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +# +# XES XPedite1000 PPC440GX +# + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 +endif diff --git a/qemu/roms/u-boot/board/xes/xpedite1000/init.S b/qemu/roms/u-boot/board/xes/xpedite1000/init.S new file mode 100644 index 000000000..9708ecc89 --- /dev/null +++ b/qemu/roms/u-boot/board/xes/xpedite1000/init.S @@ -0,0 +1,33 @@ +/* +* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <ppc_asm.tmpl> +#include <asm/mmu.h> +#include <config.h> +#include <asm/ppc4xx.h> + +/* + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + */ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) + tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) + tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG ) + tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG ) + tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG ) + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG ) + tlbtab_end diff --git a/qemu/roms/u-boot/board/xes/xpedite1000/u-boot.lds.debug b/qemu/roms/u-boot/board/xes/xpedite1000/u-boot.lds.debug new file mode 100644 index 000000000..04089ae7e --- /dev/null +++ b/qemu/roms/u-boot/board/xes/xpedite1000/u-boot.lds.debug @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2002-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + arch/powerpc/cpu/ppc4xx/start.o (.text) + board/xes/xpedite1000/init.o (.text) + arch/powerpc/cpu/ppc4xx/kgdb.o (.text) + arch/powerpc/cpu/ppc4xx/traps.o (.text) + arch/powerpc/cpu/ppc4xx/interrupts.o (.text) + arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text) + arch/powerpc/cpu/ppc4xx/cpu_init.o (.text) + arch/powerpc/cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib/crc32.o (.text) + arch/powerpc/lib/extable.o (.text) + lib/zlib.o (.text) + +/* common/env_embedded.o(.text) */ + + *(.text) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + __bss_end = . ; + PROVIDE (end = .); +} diff --git a/qemu/roms/u-boot/board/xes/xpedite1000/xpedite1000.c b/qemu/roms/u-boot/board/xes/xpedite1000/xpedite1000.c new file mode 100644 index 000000000..daab578f8 --- /dev/null +++ b/qemu/roms/u-boot/board/xes/xpedite1000/xpedite1000.c @@ -0,0 +1,184 @@ +/* + * Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/processor.h> +#include <spd_sdram.h> +#include <i2c.h> +#include <net.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + unsigned long sdrreg; + + /* + * Enable GPIO for pins 18 - 24 + * 18 = SEEPROM_WP + * 19 = #M_RST + * 20 = #MONARCH + * 21 = #LED_ALARM + * 22 = #LED_ACT + * 23 = #LED_STATUS1 + * 24 = #LED_STATUS2 + */ + mfsdr(SDR0_PFC0, sdrreg); + mtsdr(SDR0_PFC0, (sdrreg & ~SDR0_PFC0_TRE_ENABLE) | 0x00003e00); + out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3)); + LED0_OFF(); + LED1_OFF(); + LED2_OFF(); + LED3_OFF(); + + /* Setup the external bus controller/chip selects */ + mtebc(PB0AP, 0x04055200); /* 16MB Strata FLASH */ + mtebc(PB0CR, 0xff098000); /* BAS=0xff0 16MB R/W 8-bit */ + mtebc(PB1AP, 0x04055200); /* 512KB Socketed AMD FLASH */ + mtebc(PB1CR, 0xfe018000); /* BAS=0xfe0 1MB R/W 8-bit */ + mtebc(PB6AP, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */ + mtebc(PB6CR, 0xf00da000); /* BAS=0xf00 64MB R/W i6-bit */ + mtebc(PB7AP, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */ + mtebc(PB7CR, 0xf40da000); /* BAS=0xf40 64MB R/W 16-bit */ + + /* + * Setup the interrupt controller polarities, triggers, etc. + * + * Because of the interrupt handling rework to handle 440GX interrupts + * with the common code, we needed to change names of the UIC registers. + * Here the new relationship: + * + * U-Boot name 440GX name + * ----------------------- + * UIC0 UICB0 + * UIC1 UIC0 + * UIC2 UIC1 + * UIC3 UIC2 + */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000003); /* SMI & UIC1 crit are critical */ + mtdcr(UIC1PR, 0xfffffe00); /* per ref-board manual */ + mtdcr(UIC1TR, 0x01c00000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffc0ff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00ff8000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + mtdcr(UIC3ER, 0x00000000); /* disable all */ + mtdcr(UIC3CR, 0x00000000); /* all non-critical */ + mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC3TR, 0x00ff8c0f); /* per ref-board manual */ + mtdcr(UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + + mtdcr(UIC0SR, 0xfc000000); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000000); /* all non-critical */ + mtdcr(UIC0PR, 0xfc000000); /* */ + mtdcr(UIC0TR, 0x00000000); /* */ + mtdcr(UIC0VR, 0x00000001); /* */ + + LED0_ON(); + + return 0; +} + +int checkboard(void) +{ + char buf[64]; + int i; + + printf("Board: X-ES %s PMC SBC\n", CONFIG_SYS_BOARD_NAME); + printf(" "); + i = getenv_f("board_rev", buf, sizeof(buf)); + if (i > 0) + printf("Rev %s, ", buf); + i = getenv_f("serial#", buf, sizeof(buf)); + if (i > 0) + printf("Serial# %s, ", buf); + i = getenv_f("board_cfg", buf, sizeof(buf)); + if (i > 0) + printf("Cfg %s", buf); + printf("\n"); + + return 0; +} + +phys_size_t initdram(int board_type) +{ + return spd_sdram(); +} + +/* + * Override weak pci_pre_init() + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + */ +#if defined(CONFIG_PCI) +int pci_pre_init(struct pci_controller * hose) +{ + unsigned long strap; + + /* See if we're supposed to setup the pci */ + mfsdr(SDR0_SDSTP1, strap); + if ((strap & 0x00010000) == 0) + return 0; + +#if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV) + /* Setup System Device Register PCIL0_XCR */ + mfsdr(SDR0_XCR, strap); + strap &= 0x0f000000; + mtsdr(SDR0_XCR, strap); +#endif + + return 1; +} +#endif /* defined(CONFIG_PCI) */ + +#if defined(CONFIG_PCI) +/* + * Override weak is_pci_host() + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + */ +int is_pci_host(struct pci_controller *hose) +{ + return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0); +} +#endif /* defined(CONFIG_PCI) */ + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + return ctrlc(); +} +#endif |