diff options
Diffstat (limited to 'qemu/roms/u-boot/board/xes/common')
| -rw-r--r-- | qemu/roms/u-boot/board/xes/common/Makefile | 14 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/xes/common/actl_nand.c | 49 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/xes/common/board.c | 66 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/xes/common/fsl_8xxx_clk.c | 54 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/xes/common/fsl_8xxx_misc.c | 44 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/xes/common/fsl_8xxx_misc.h | 12 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/xes/common/fsl_8xxx_pci.c | 72 |
7 files changed, 311 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/board/xes/common/Makefile b/qemu/roms/u-boot/board/xes/common/Makefile new file mode 100644 index 000000000..65d321abd --- /dev/null +++ b/qemu/roms/u-boot/board/xes/common/Makefile @@ -0,0 +1,14 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o +obj-$(CONFIG_MPC8572) += fsl_8xxx_clk.o +obj-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o +obj-$(CONFIG_P2020) += fsl_8xxx_clk.o +obj-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o +obj-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o +obj-$(CONFIG_NAND_ACTL) += actl_nand.o diff --git a/qemu/roms/u-boot/board/xes/common/actl_nand.c b/qemu/roms/u-boot/board/xes/common/actl_nand.c new file mode 100644 index 000000000..bf896fe0c --- /dev/null +++ b/qemu/roms/u-boot/board/xes/common/actl_nand.c @@ -0,0 +1,49 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * This driver support NAND devices which have address lines + * connected as ALE and CLE inputs. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <nand.h> +#include <asm/io.h> + +/* + * Hardware specific access to control-lines + */ +static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) +{ + struct nand_chip *this = mtd->priv; + ulong IO_ADDR_W; + + if (ctrl & NAND_CTRL_CHANGE) { + IO_ADDR_W = (ulong)this->IO_ADDR_W; + + IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE | + CONFIG_SYS_NAND_ACTL_ALE | + CONFIG_SYS_NAND_ACTL_NCE); + if (ctrl & NAND_CLE) + IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE; + if (ctrl & NAND_NCE) + IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE; + + this->IO_ADDR_W = (void *)IO_ADDR_W; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->ecc.mode = NAND_ECC_SOFT; + nand->cmd_ctrl = nand_addr_hwcontrol; + nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY; + + return 0; +} diff --git a/qemu/roms/u-boot/board/xes/common/board.c b/qemu/roms/u-boot/board/xes/common/board.c new file mode 100644 index 000000000..4ed6f50e5 --- /dev/null +++ b/qemu/roms/u-boot/board/xes/common/board.c @@ -0,0 +1,66 @@ +/* + * Copyright 2009 Extreme Engineering Solutions, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include "fsl_8xxx_misc.h" + +int checkboard(void) +{ + char name[] = CONFIG_SYS_BOARD_NAME; + char buf[64]; + char *s; + int i; + +#ifdef CONFIG_SYS_FORM_CUSTOM + s = "Custom"; +#elif CONFIG_SYS_FORM_6U_CPCI + s = "6U CompactPCI"; +#elif CONFIG_SYS_FORM_ATCA_PMC + s = "ATCA w/PMC"; +#elif CONFIG_SYS_FORM_ATCA_AMC + s = "ATCA w/AMC"; +#elif CONFIG_SYS_FORM_VME + s = "VME"; +#elif CONFIG_SYS_FORM_6U_VPX + s = "6U VPX"; +#elif CONFIG_SYS_FORM_PMC + s = "PMC"; +#elif CONFIG_SYS_FORM_PCI + s = "PCI"; +#elif CONFIG_SYS_FORM_3U_CPCI + s = "3U CompactPCI"; +#elif CONFIG_SYS_FORM_AMC + s = "AdvancedMC"; +#elif CONFIG_SYS_FORM_XMC + s = "XMC"; +#elif CONFIG_SYS_FORM_PMC_XMC + s = "PMC/XMC"; +#elif CONFIG_SYS_FORM_PCI_EXPRESS + s = "PCI Express"; +#elif CONFIG_SYS_FORM_3U_VPX + s = "3U VPX"; +#else +#error "Form factor not defined" +#endif + + name[strlen(name) - 1] += get_board_derivative(); + printf("Board: X-ES %s %s SBC\n", name, s); + + /* Display board specific information */ + puts(" "); + i = getenv_f("board_rev", buf, sizeof(buf)); + if (i > 0) + printf("Rev %s, ", buf); + i = getenv_f("serial#", buf, sizeof(buf)); + if (i > 0) + printf("Serial# %s, ", buf); + i = getenv_f("board_cfg", buf, sizeof(buf)); + if (i > 0) + printf("Cfg %s", buf); + puts("\n"); + + return 0; +} diff --git a/qemu/roms/u-boot/board/xes/common/fsl_8xxx_clk.c b/qemu/roms/u-boot/board/xes/common/fsl_8xxx_clk.c new file mode 100644 index 000000000..2a604d448 --- /dev/null +++ b/qemu/roms/u-boot/board/xes/common/fsl_8xxx_clk.c @@ -0,0 +1,54 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> + +/* + * Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config + */ +unsigned long get_board_sys_clk(ulong dummy) +{ +#if defined(CONFIG_MPC85xx) + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#elif defined(CONFIG_MPC86xx) + immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; +#endif + + if (in_be32(&gur->gpporcr) & 0x10000) + return 66666666; + else +#ifdef CONFIG_P2020 + return 100000000; +#else + return 50000000; +#endif +} + +#ifdef CONFIG_MPC85xx +/* + * Return DDR input clock - synchronous with SYSCLK or 66 MHz + * Note: 86xx doesn't support asynchronous DDR clk + */ +unsigned long get_board_ddr_clk(ulong dummy) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9; + + if (ddr_ratio == 0x7) + return get_board_sys_clk(dummy); + +#ifdef CONFIG_P2020 + if (in_be32(&gur->gpporcr) & 0x20000) + return 66666666; + else + return 100000000; +#else + return 66666666; +#endif +} +#endif diff --git a/qemu/roms/u-boot/board/xes/common/fsl_8xxx_misc.c b/qemu/roms/u-boot/board/xes/common/fsl_8xxx_misc.c new file mode 100644 index 000000000..2899e1117 --- /dev/null +++ b/qemu/roms/u-boot/board/xes/common/fsl_8xxx_misc.c @@ -0,0 +1,44 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/mmu.h> +#ifdef CONFIG_PCA953X +#include <pca953x.h> + +/* + * Determine if a board's flashes are write protected + */ +int board_flash_wp_on(void) +{ + if (pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) & + CONFIG_SYS_PCA953X_NVM_WP) + return 1; + + return 0; +} +#endif + +/* + * Return a board's derivative model number. For example: + * return 2 for the XPedite5372 and return 1 for the XPedite5201. + */ +uint get_board_derivative(void) +{ +#if defined(CONFIG_MPC85xx) + volatile ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; +#elif defined(CONFIG_MPC86xx) + volatile immap_t *immap = (immap_t *)CONFIG_SYS_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; +#endif + + /* + * The top 4 lines of the local bus address are pulled low/high and + * can be read to determine the least significant digit of a board's + * model number. + */ + return gur->gpporcr >> 28; +} diff --git a/qemu/roms/u-boot/board/xes/common/fsl_8xxx_misc.h b/qemu/roms/u-boot/board/xes/common/fsl_8xxx_misc.h new file mode 100644 index 000000000..106bb233a --- /dev/null +++ b/qemu/roms/u-boot/board/xes/common/fsl_8xxx_misc.h @@ -0,0 +1,12 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_8XXX_MISC_H___ +#define __FSL_8XXX_MISC_H___ + +uint get_board_derivative(void); + +#endif /* __FSL_8XXX_MISC_H__ */ diff --git a/qemu/roms/u-boot/board/xes/common/fsl_8xxx_pci.c b/qemu/roms/u-boot/board/xes/common/fsl_8xxx_pci.c new file mode 100644 index 000000000..510f638ff --- /dev/null +++ b/qemu/roms/u-boot/board/xes/common/fsl_8xxx_pci.c @@ -0,0 +1,72 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <pci.h> +#include <asm/fsl_pci.h> +#include <asm/fsl_serdes.h> +#include <asm/io.h> +#include <linux/compiler.h> +#include <libfdt.h> +#include <fdt_support.h> + + +#ifdef CONFIG_PCI1 +static struct pci_controller pci1_hose; +#endif + +void pci_init_board(void) +{ + int first_free_busno = 0; + +#ifdef CONFIG_PCI1 + int pcie_ep; + struct fsl_pci_info pci_info; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr = in_be32(&gur->devdisr); + uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD; + uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32; + uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB; + uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1; + uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000; + + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + SET_STD_PCI_INFO(pci_info, 1); + set_next_law(pci_info.mem_phys, + law_size_bits(pci_info.mem_size), pci_info.law); + set_next_law(pci_info.io_phys, + law_size_bits(pci_info.io_size), pci_info.law); + + pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs); + printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n", + pci_32 ? 32 : 64, + pcix ? "PCIX" : "PCI", + pci_spd_norm ? ">=" : "<=", + pcix ? freq * 2 : freq, + pcie_ep ? "agent" : "host", + pci_arb ? "arbiter" : "external-arbiter"); + + first_free_busno = fsl_pci_init_port(&pci_info, + &pci1_hose, first_free_busno); + } else { + printf("PCI1: disabled\n"); + } +#elif defined CONFIG_MPC8548 + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + /* PCI1 not present on MPC8572 */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); +#endif + + fsl_pcie_init_board(first_free_busno); +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_pci_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} +#endif /* CONFIG_OF_BOARD_SETUP */ |