diff options
Diffstat (limited to 'qemu/roms/u-boot/board/tqc/tqm8260')
| -rw-r--r-- | qemu/roms/u-boot/board/tqc/tqm8260/Makefile | 8 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/tqc/tqm8260/README | 415 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/tqc/tqm8260/tqm8260.c | 352 |
3 files changed, 775 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/board/tqc/tqm8260/Makefile b/qemu/roms/u-boot/board/tqc/tqm8260/Makefile new file mode 100644 index 000000000..6b8573d9a --- /dev/null +++ b/qemu/roms/u-boot/board/tqc/tqm8260/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = tqm8260.o ../tqm8xx/load_sernum_ethaddr.o diff --git a/qemu/roms/u-boot/board/tqc/tqm8260/README b/qemu/roms/u-boot/board/tqc/tqm8260/README new file mode 100644 index 000000000..93b55068f --- /dev/null +++ b/qemu/roms/u-boot/board/tqc/tqm8260/README @@ -0,0 +1,415 @@ + +This file contains basic information on the port of U-Boot to TQM8260. +All the changes fit in the common U-Boot infrastructure, providing a +new TQM8260-specific entry in makefiles. To build U-Boot for TQM8260, +type "make TQM8260_config", edit the "include/config_TQM8260.h" file +if necessary, then type "make". + + +Common file modifications: +-------------------------- + +The following common files have been modified by this project: +(starting from the ppcboot-0.9.3/ directory) + +MAKEALL - TQM8260 entry added +Makefile - TQM8260_config entry added +arch/powerpc/cpu/mpc8260/Makefile - soft_i2c.o module added +arch/powerpc/cpu/mpc8260/ether_scc.c - TQM8260-specific definitions added, an obvious + bug fixed (fcr -> scr) +arch/powerpc/cpu/mpc8260/ether_fcc.c - TQM8260-specific definitions added +include/flash.h - added definitions for the AM29LV640D Flash chip + + +New files: +---------- + +The following new files have been added by this project: +(starting from the ppcboot-0.9.3/ directory) + +board/tqm8260/ - board-specific directory +board/tqm8260/Makefile - board-specific makefile +board/tqm8260/config.mk - config file +board/tqm8260/flash.c - flash driver (for AM29LV640D) +board/tqm8260/ppcboot.lds - linker script +board/tqm8260/tqm8260.c - ioport and memory initialization +arch/powerpc/cpu/mpc8260/soft_i2c.c - software i2c EEPROM driver +include/config_TQM8260.h - main configuration file + + +New configuration options: +-------------------------- + +CONFIG_TQM8260 + + Main board-specific option (should be defined for TQM8260). + +CONFIG_82xx_CONS_SMC1 + + If defined, SMC1 will be used as the console + +CONFIG_82xx_CONS_SMC2 + + If defined, SMC2 will be used as the console + +CONFIG_SYS_INIT_LOCAL_SDRAM + + If defined, the SDRAM on the local bus will be initialized and + mapped at BR2. + + +Acceptance criteria tests: +-------------------------- + +The following tests have been conducted to validate the port of U-Boot +to TQM8260: + +1. Operation on serial console: + +With the CONFIG_82xx_CONS_SMC1 option defined in the main configuration file, +the U-Boot output appeared on the serial terminal connected to COM1 as +follows: + +------------------------------------------------------------------------------ +=> help +go - start application at address 'addr' +run - run commands in an environment variable +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +tftpboot- boot image via network using TFTP protocol + and env variables ipaddr and serverip +rarpboot- boot image via network using RARP/TFTP protocol +bootd - boot default, i.e., run 'bootcmd' +loads - load S-Record file over serial line +loadb - load binary file over serial line (kermit mode) +md - memory display +mm - memory modify (auto-incrementing) +nm - memory modify (constant address) +mw - memory write (fill) +cp - memory copy +cmp - memory compare +crc32 - checksum calculation +base - print or set address offset +printenv- print environment variables +setenv - set environment variables +saveenv - save environment variables to persistent storage +protect - enable or disable FLASH write protection +erase - erase FLASH memory +flinfo - print FLASH memory information +bdinfo - print Board Info structure +iminfo - print header information for application image +coninfo - print console devices and informations +eeprom - EEPROM sub-system +loop - infinite loop on address range +mtest - simple RAM test +icache - enable or disable instruction cache +dcache - enable or disable data cache +reset - Perform RESET of the CPU +echo - echo args to console +version - print monitor version +help - print online help +? - alias for 'help' +=> +------------------------------------------------------------------------------ + + +2. Flash driver operation + +The following sequence was performed to test the "flinfo" command: + +------------------------------------------------------------------------------ +=> flinfo + +Bank # 1: AMD 29LV640D (64 M, uniform sector) + Size: 32 MB in 128 Sectors + Sector Start Addresses: + 40000000 40040000 (RO) 40080000 400C0000 40100000 + 40140000 40180000 401C0000 40200000 40240000 + 40280000 402C0000 40300000 40340000 40380000 + 403C0000 40400000 40440000 40480000 404C0000 + 40500000 40540000 40580000 405C0000 40600000 + 40640000 40680000 406C0000 40700000 40740000 + 40780000 407C0000 40800000 40840000 40880000 + 408C0000 40900000 40940000 40980000 409C0000 + 40A00000 40A40000 40A80000 40AC0000 40B00000 + 40B40000 40B80000 40BC0000 40C00000 40C40000 + 40C80000 40CC0000 40D00000 40D40000 40D80000 + 40DC0000 40E00000 40E40000 40E80000 40EC0000 + 40F00000 40F40000 40F80000 40FC0000 41000000 + 41040000 41080000 410C0000 41100000 41140000 + 41180000 411C0000 41200000 41240000 41280000 + 412C0000 41300000 41340000 41380000 413C0000 + 41400000 41440000 41480000 414C0000 41500000 + 41540000 41580000 415C0000 41600000 41640000 + 41680000 416C0000 41700000 41740000 41780000 + 417C0000 41800000 41840000 41880000 418C0000 + 41900000 41940000 41980000 419C0000 41A00000 + 41A40000 41A80000 41AC0000 41B00000 41B40000 + 41B80000 41BC0000 41C00000 41C40000 41C80000 + 41CC0000 41D00000 41D40000 41D80000 41DC0000 + 41E00000 41E40000 41E80000 41EC0000 41F00000 + 41F40000 41F80000 41FC0000 +=> +------------------------------------------------------------------------------ + + +The following sequence was performed to test the erase command: + +------------------------------------------------------------------------------ +=> cp 0 40080000 10 +Copy to Flash... done +=> erase 40080000 400bffff +Erase Flash from 0x40080000 to 0x400bffff +.. done +Erased 1 sectors +=> md 40080000 +40080000: ffffffff ffffffff ffffffff ffffffff ................ +40080010: ffffffff ffffffff ffffffff ffffffff ................ +40080020: ffffffff ffffffff ffffffff ffffffff ................ +40080030: ffffffff ffffffff ffffffff ffffffff ................ +40080040: ffffffff ffffffff ffffffff ffffffff ................ +40080050: ffffffff ffffffff ffffffff ffffffff ................ +40080060: ffffffff ffffffff ffffffff ffffffff ................ +40080070: ffffffff ffffffff ffffffff ffffffff ................ +40080080: ffffffff ffffffff ffffffff ffffffff ................ +40080090: ffffffff ffffffff ffffffff ffffffff ................ +400800a0: ffffffff ffffffff ffffffff ffffffff ................ +400800b0: ffffffff ffffffff ffffffff ffffffff ................ +400800c0: ffffffff ffffffff ffffffff ffffffff ................ +400800d0: ffffffff ffffffff ffffffff ffffffff ................ +400800e0: ffffffff ffffffff ffffffff ffffffff ................ +400800f0: ffffffff ffffffff ffffffff ffffffff ................ +=> cp 0 40080000 10 +Copy to Flash... done +=> erase 1:2 +Erase Flash Sectors 2-2 in Bank # 1 +.. done +=> md 40080000 +40080000: ffffffff ffffffff ffffffff ffffffff ................ +40080010: ffffffff ffffffff ffffffff ffffffff ................ +40080020: ffffffff ffffffff ffffffff ffffffff ................ +40080030: ffffffff ffffffff ffffffff ffffffff ................ +40080040: ffffffff ffffffff ffffffff ffffffff ................ +40080050: ffffffff ffffffff ffffffff ffffffff ................ +40080060: ffffffff ffffffff ffffffff ffffffff ................ +40080070: ffffffff ffffffff ffffffff ffffffff ................ +40080080: ffffffff ffffffff ffffffff ffffffff ................ +40080090: ffffffff ffffffff ffffffff ffffffff ................ +400800a0: ffffffff ffffffff ffffffff ffffffff ................ +400800b0: ffffffff ffffffff ffffffff ffffffff ................ +400800c0: ffffffff ffffffff ffffffff ffffffff ................ +400800d0: ffffffff ffffffff ffffffff ffffffff ................ +400800e0: ffffffff ffffffff ffffffff ffffffff ................ +400800f0: ffffffff ffffffff ffffffff ffffffff ................ +=> cp 0 40080000 10 +Copy to Flash... done +=> cp 0 400c0000 10 +Copy to Flash... done +=> erase 1:2-3 +Erase Flash Sectors 2-3 in Bank # 1 +... done +=> md 40080000 +40080000: ffffffff ffffffff ffffffff ffffffff ................ +40080010: ffffffff ffffffff ffffffff ffffffff ................ +40080020: ffffffff ffffffff ffffffff ffffffff ................ +40080030: ffffffff ffffffff ffffffff ffffffff ................ +40080040: ffffffff ffffffff ffffffff ffffffff ................ +40080050: ffffffff ffffffff ffffffff ffffffff ................ +40080060: ffffffff ffffffff ffffffff ffffffff ................ +40080070: ffffffff ffffffff ffffffff ffffffff ................ +40080080: ffffffff ffffffff ffffffff ffffffff ................ +40080090: ffffffff ffffffff ffffffff ffffffff ................ +400800a0: ffffffff ffffffff ffffffff ffffffff ................ +400800b0: ffffffff ffffffff ffffffff ffffffff ................ +400800c0: ffffffff ffffffff ffffffff ffffffff ................ +400800d0: ffffffff ffffffff ffffffff ffffffff ................ +400800e0: ffffffff ffffffff ffffffff ffffffff ................ +400800f0: ffffffff ffffffff ffffffff ffffffff ................ +=> md 400c0000 +400c0000: ffffffff ffffffff ffffffff ffffffff ................ +400c0010: ffffffff ffffffff ffffffff ffffffff ................ +400c0020: ffffffff ffffffff ffffffff ffffffff ................ +400c0030: ffffffff ffffffff ffffffff ffffffff ................ +400c0040: ffffffff ffffffff ffffffff ffffffff ................ +400c0050: ffffffff ffffffff ffffffff ffffffff ................ +400c0060: ffffffff ffffffff ffffffff ffffffff ................ +400c0070: ffffffff ffffffff ffffffff ffffffff ................ +400c0080: ffffffff ffffffff ffffffff ffffffff ................ +400c0090: ffffffff ffffffff ffffffff ffffffff ................ +400c00a0: ffffffff ffffffff ffffffff ffffffff ................ +400c00b0: ffffffff ffffffff ffffffff ffffffff ................ +400c00c0: ffffffff ffffffff ffffffff ffffffff ................ +400c00d0: ffffffff ffffffff ffffffff ffffffff ................ +400c00e0: ffffffff ffffffff ffffffff ffffffff ................ +400c00f0: ffffffff ffffffff ffffffff ffffffff ................ +=> +------------------------------------------------------------------------------ + + +The following sequence was performed to test the Flash programming commands: + +------------------------------------------------------------------------------ +=> erase 40080000 400bffff +Erase Flash from 0x40080000 to 0x400bffff +.. done +Erased 1 sectors +=> cp 0 40080000 10 +Copy to Flash... done +=> md 0 +00000000: 00000000 00000104 61100200 01000000 ........a....... +00000010: 00000000 00000000 81140000 82000100 ................ +00000020: 01080000 00004000 22800000 00000600 ......@."....... +00000030: 00200800 00000000 10000100 00008000 . .............. +00000040: 00812000 00000200 00020000 80000000 .. ............. +00000050: 00028001 00001000 00040400 00000200 ................ +00000060: 20480000 00000000 20090000 00142000 H...... ..... . +00000070: 00000000 00004000 24210000 10000000 ......@.$!...... +00000080: 02440002 10000000 00200008 00000000 .D....... ...... +00000090: 02440900 00000000 30a40000 00004400 .D......0.....D. +000000a0: 04420800 00000000 00000040 00020000 .B.........@.... +000000b0: 05020000 00100000 00060000 00000000 ................ +000000c0: 00400000 00000000 00080000 00040000 .@.............. +000000d0: 10400000 00800004 00000000 00000200 .@.............. +000000e0: 80890000 00010004 00080000 00000020 ............... +000000f0: 08000000 10000000 00010000 00000000 ................ +=> md 40080000 +40080000: 00000000 00000104 61100200 01000000 ........a....... +40080010: 00000000 00000000 81140000 82000100 ................ +40080020: 01080000 00004000 22800000 00000600 ......@."....... +40080030: 00200800 00000000 10000100 00008000 . .............. +40080040: ffffffff ffffffff ffffffff ffffffff ................ +40080050: ffffffff ffffffff ffffffff ffffffff ................ +40080060: ffffffff ffffffff ffffffff ffffffff ................ +40080070: ffffffff ffffffff ffffffff ffffffff ................ +40080080: ffffffff ffffffff ffffffff ffffffff ................ +40080090: ffffffff ffffffff ffffffff ffffffff ................ +400800a0: ffffffff ffffffff ffffffff ffffffff ................ +400800b0: ffffffff ffffffff ffffffff ffffffff ................ +400800c0: ffffffff ffffffff ffffffff ffffffff ................ +400800d0: ffffffff ffffffff ffffffff ffffffff ................ +400800e0: ffffffff ffffffff ffffffff ffffffff ................ +400800f0: ffffffff ffffffff ffffffff ffffffff ................ +=> +------------------------------------------------------------------------------ + + +The following sequence was performed to test storage of the environment +variables in Flash: + +------------------------------------------------------------------------------ +=> setenv foo bar +=> saveenv +Un-Protected 1 sectors +Erasing Flash... +.. done +Erased 1 sectors +Saving Environment to Flash... +Protected 1 sectors +=> reset +... +=> printenv +bootdelay=CONFIG_BOOTDELAY +baudrate=9600 +ipaddr=192.168.4.7 +serverip=192.168.4.1 +ethaddr=66:55:44:33:22:11 +foo=bar +stdin=serial +stdout=serial +stderr=serial + +Environment size: 170/262140 bytes +=> +------------------------------------------------------------------------------ + + +The following sequence was performed to test image download and run over +Ethernet interface (both interfaces were tested): + +------------------------------------------------------------------------------ +=> tftpboot 40000 hello_world.bin +ARP broadcast 1 +TFTP from server 192.168.2.2; our IP address is 192.168.2.7 +Filename 'hello_world.bin'. +Load address: 0x40000 +Loading: ############# +done +Bytes transferred = 65912 (10178 hex) +=> go 40004 +## Starting application at 0x00040004 ... +Hello World +argc = 1 +argv[0] = "40004" +argv[1] = "<NULL>" +Hit any key to exit ... + +## Application terminated, rc = 0x0 +=> +------------------------------------------------------------------------------ + + +The following sequence was performed to test eeprom read/write commands: + +------------------------------------------------------------------------------ +=> md 40000 +00040000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. +00040010: 90010024 48000005 7fc802a6 801effe8 ...$H........... +00040020: 7fc0f214 7c7f1b78 813f004c 7c9c2378 ....|..x.?.L|.#x +00040030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. +00040040: 7c0803a6 4e800021 813f004c 7f84e378 |...N..!.?.L...x +00040050: 807e8004 80090010 7c0803a6 4e800021 .~......|...N..! +00040060: 7c1be000 4181003c 80bd0000 813f004c |...A..<.....?.L +00040070: 3bbd0004 2c050000 40820008 80be8008 ;...,...@....... +00040080: 80090010 7f64db78 807e800c 3b7b0001 .....d.x.~..;{.. +00040090: 7c0803a6 4e800021 7c1be000 4081ffcc |...N..!|...@... +000400a0: 813f004c 807e8010 80090010 7c0803a6 .?.L.~......|... +000400b0: 4e800021 813f004c 80090004 7c0803a6 N..!.?.L....|... +000400c0: 4e800021 2c030000 4182ffec 813f004c N..!,...A....?.L +000400d0: 80090000 7c0803a6 4e800021 813f004c ....|...N..!.?.L +000400e0: 807e8014 80090010 7c0803a6 4e800021 .~......|...N..! +000400f0: 38600000 80010024 7c0803a6 bb61000c 8`.....$|....a.. +=> eeprom write 40000 0 40 + +EEPROM write: addr 00040000 off 0000 count 64 ... done +=> mw 50000 0 1000 +=> eeprom read 50000 0 40 + +EEPROM read: addr 00050000 off 0000 count 64 ... done +=> md 50000 +00050000: 00018148 9421ffe0 7c0802a6 bf61000c ...H.!..|....a.. +00050010: 90010024 48000005 7fc802a6 801effe8 ...$H........... +00050020: 7fc0f214 7c7f1b78 813f004c 7c9c2378 ....|..x.?.L|.#x +00050030: 807e8000 7cbd2b78 80090010 3b600000 .~..|.+x....;`.. +00050040: 00000000 00000000 00000000 00000000 ................ +00050050: 00000000 00000000 00000000 00000000 ................ +00050060: 00000000 00000000 00000000 00000000 ................ +00050070: 00000000 00000000 00000000 00000000 ................ +00050080: 00000000 00000000 00000000 00000000 ................ +00050090: 00000000 00000000 00000000 00000000 ................ +000500a0: 00000000 00000000 00000000 00000000 ................ +000500b0: 00000000 00000000 00000000 00000000 ................ +000500c0: 00000000 00000000 00000000 00000000 ................ +000500d0: 00000000 00000000 00000000 00000000 ................ +000500e0: 00000000 00000000 00000000 00000000 ................ +000500f0: 00000000 00000000 00000000 00000000 ................ +=> +------------------------------------------------------------------------------ + + +Patch per Mon, 06 Aug 2001 17:57:27: + +- upgraded Flash support (added support for the following chips: + AM29LV800T/B, AM29LV160T/B, AM29DL322T/B, AM29DL323T/B) +- BCR tweakage for the 8260 bus mode +- SIUMCR tweakage enabling the MI interrupt (IRQ7) + +To simplify switching between the bus modes, a new configuration +option (CONFIG_BUSMODE_60x) has been added to the "config_TQM8260.h" +file. If it is defined, BCR will be configured for the 60x mode, +otherwise - for the 8260 mode. + +Concerning the SIUMCR modification: it's hard to predict whether it +will induce any problems on the other (60x mode) board. However, the +problems (if they appear) should be easy to notice - if the board +does not boot, it's most likely caused by the DPPC configuration in +SIUMCR. diff --git a/qemu/roms/u-boot/board/tqc/tqm8260/tqm8260.c b/qemu/roms/u-boot/board/tqc/tqm8260/tqm8260.c new file mode 100644 index 000000000..c361f188f --- /dev/null +++ b/qemu/roms/u-boot/board/tqc/tqm8260/tqm8260.c @@ -0,0 +1,352 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <ioports.h> +#include <mpc8260.h> + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */ + /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */ + /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */ + /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */ + /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */ + /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */ + /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ + /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ + /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ + /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ + /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ + /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ + /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ + /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ + /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ +#if defined(CONFIG_SYS_I2C_SOFT) + /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ + /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ +#else +#if defined(CONFIG_HARD_I2C) + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#else /* normal I/O port pins */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#endif +#endif + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +/* ------------------------------------------------------------------------- */ + +/* Check Board Identity: + */ +int checkboard (void) +{ + char buf[64]; + int i = getenv_f("serial#", buf, sizeof(buf)); + + puts ("Board: "); + + if (i < 0 || strncmp(buf, "TQM82", 5)) { + puts ("### No HW ID - assuming TQM8260\n"); + return (0); + } + + puts (buf); + putc ('\n'); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx + * + * This routine performs standard 8260 initialization sequence + * and calculates the available memory size. It may be called + * several times to try different SDRAM configurations on both + * 60x and local buses. + */ +static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, + ulong orx, volatile uchar * base) +{ + volatile uchar c = 0xff; + volatile uint *sdmr_ptr; + volatile uint *orx_ptr; + ulong maxsize, size; + int i; + + /* We must be able to test a location outsize the maximum legal size + * to find out THAT we are outside; but this address still has to be + * mapped by the controller. That means, that the initial mapping has + * to be (at least) twice as large as the maximum expected size. + */ + maxsize = (1 + (~orx | 0x7fff)) / 2; + + /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that + * we are configuring CS1 if base != 0 + */ + sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; + orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1; + + *orx_ptr = orx; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. + */ + + *sdmr_ptr = sdmr | PSDMR_OP_PREA; + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_MRW; + *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ + + *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *base = c; + + size = get_ram_size((long *)base, maxsize); + *orx_ptr = orx | ~(size - 1); + + return (size); +} + +phys_size_t initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + +#ifndef CONFIG_SYS_RAMBOOT + long size8, size9; +#endif + long psize, lsize; + + psize = 16 * 1024 * 1024; + lsize = 0; + + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; + +#if 0 /* Just for debugging */ +#define prt_br_or(brX,orX) do { \ + ulong start = memctl->memc_ ## brX & 0xFFFF8000; \ + ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \ + printf ("\n" \ + #brX " 0x%08x " #orX " 0x%08x " \ + "==> 0x%08lx ... 0x%08lx = %ld MB\n", \ + memctl->memc_ ## brX, memctl->memc_ ## orX, \ + start, start+sizem, (sizem+1)>>20); \ + } while (0) + prt_br_or (br0, or0); + prt_br_or (br1, or1); + prt_br_or (br2, or2); + prt_br_or (br3, or3); +#endif + +#ifndef CONFIG_SYS_RAMBOOT + /* 60x SDRAM setup: + */ + size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); + size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); + + if (size8 < size9) { + psize = size9; + printf ("(60x:9COL - %ld MB, ", psize >> 20); + } else { + psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); + printf ("(60x:8COL - %ld MB, ", psize >> 20); + } + + /* Local SDRAM setup: + */ +#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM + memctl->memc_lsrt = CONFIG_SYS_LSRT; + size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL, + (uchar *) SDRAM_BASE2_PRELIM); + size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL, + (uchar *) SDRAM_BASE2_PRELIM); + + if (size8 < size9) { + lsize = size9; + printf ("Local:9COL - %ld MB) using ", lsize >> 20); + } else { + lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL, + (uchar *) SDRAM_BASE2_PRELIM); + printf ("Local:8COL - %ld MB) using ", lsize >> 20); + } + +#if 0 + /* Set up BR2 so that the local SDRAM goes + * right after the 60x SDRAM + */ + memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) | + (CONFIG_SYS_SDRAM_BASE + psize); +#endif +#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */ +#endif /* CONFIG_SYS_RAMBOOT */ + + icache_enable (); + + return (psize); +} + +/* ------------------------------------------------------------------------- */ |