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-rw-r--r--qemu/roms/u-boot/board/ti/am335x/Makefile13
-rw-r--r--qemu/roms/u-boot/board/ti/am335x/README205
-rw-r--r--qemu/roms/u-boot/board/ti/am335x/board.c701
-rw-r--r--qemu/roms/u-boot/board/ti/am335x/board.h77
-rw-r--r--qemu/roms/u-boot/board/ti/am335x/mux.c385
-rw-r--r--qemu/roms/u-boot/board/ti/am335x/u-boot.lds126
-rw-r--r--qemu/roms/u-boot/board/ti/am3517crane/Makefile11
-rw-r--r--qemu/roms/u-boot/board/ti/am3517crane/am3517crane.c71
-rw-r--r--qemu/roms/u-boot/board/ti/am3517crane/am3517crane.h344
-rw-r--r--qemu/roms/u-boot/board/ti/am43xx/Makefile13
-rw-r--r--qemu/roms/u-boot/board/ti/am43xx/board.c502
-rw-r--r--qemu/roms/u-boot/board/ti/am43xx/board.h53
-rw-r--r--qemu/roms/u-boot/board/ti/am43xx/mux.c109
-rw-r--r--qemu/roms/u-boot/board/ti/beagle/Makefile9
-rw-r--r--qemu/roms/u-boot/board/ti/beagle/beagle.c553
-rw-r--r--qemu/roms/u-boot/board/ti/beagle/beagle.h546
-rw-r--r--qemu/roms/u-boot/board/ti/beagle/led.c73
-rw-r--r--qemu/roms/u-boot/board/ti/dra7xx/Makefile8
-rw-r--r--qemu/roms/u-boot/board/ti/dra7xx/README26
-rw-r--r--qemu/roms/u-boot/board/ti/dra7xx/evm.c263
-rw-r--r--qemu/roms/u-boot/board/ti/dra7xx/mux_data.h66
-rw-r--r--qemu/roms/u-boot/board/ti/evm/Makefile8
-rw-r--r--qemu/roms/u-boot/board/ti/evm/evm.c266
-rw-r--r--qemu/roms/u-boot/board/ti/evm/evm.h394
-rw-r--r--qemu/roms/u-boot/board/ti/k2hk_evm/Makefile9
-rw-r--r--qemu/roms/u-boot/board/ti/k2hk_evm/README122
-rw-r--r--qemu/roms/u-boot/board/ti/k2hk_evm/board.c301
-rw-r--r--qemu/roms/u-boot/board/ti/k2hk_evm/ddr3.c268
-rw-r--r--qemu/roms/u-boot/board/ti/omap5912osk/Makefile9
-rw-r--r--qemu/roms/u-boot/board/ti/omap5912osk/config.mk30
-rw-r--r--qemu/roms/u-boot/board/ti/omap5912osk/lowlevel_init.S477
-rw-r--r--qemu/roms/u-boot/board/ti/omap5912osk/omap5912osk.c307
-rw-r--r--qemu/roms/u-boot/board/ti/omap5_uevm/Makefile8
-rw-r--r--qemu/roms/u-boot/board/ti/omap5_uevm/README25
-rw-r--r--qemu/roms/u-boot/board/ti/omap5_uevm/evm.c221
-rw-r--r--qemu/roms/u-boot/board/ti/omap5_uevm/mux_data.h58
-rw-r--r--qemu/roms/u-boot/board/ti/panda/Makefile8
-rw-r--r--qemu/roms/u-boot/board/ti/panda/panda.c323
-rw-r--r--qemu/roms/u-boot/board/ti/panda/panda_mux_data.h87
-rw-r--r--qemu/roms/u-boot/board/ti/sdp3430/Makefile8
-rw-r--r--qemu/roms/u-boot/board/ti/sdp3430/config.mk17
-rw-r--r--qemu/roms/u-boot/board/ti/sdp3430/sdp.c198
-rw-r--r--qemu/roms/u-boot/board/ti/sdp3430/sdp.h401
-rw-r--r--qemu/roms/u-boot/board/ti/sdp4430/Makefile12
-rw-r--r--qemu/roms/u-boot/board/ti/sdp4430/cmd_bat.c42
-rw-r--r--qemu/roms/u-boot/board/ti/sdp4430/sdp.c91
-rw-r--r--qemu/roms/u-boot/board/ti/sdp4430/sdp4430_mux_data.h68
-rw-r--r--qemu/roms/u-boot/board/ti/ti814x/Makefile13
-rw-r--r--qemu/roms/u-boot/board/ti/ti814x/evm.c188
-rw-r--r--qemu/roms/u-boot/board/ti/ti814x/evm.h8
-rw-r--r--qemu/roms/u-boot/board/ti/ti814x/mux.c86
-rw-r--r--qemu/roms/u-boot/board/ti/ti816x/Makefile12
-rw-r--r--qemu/roms/u-boot/board/ti/ti816x/evm.c216
-rw-r--r--qemu/roms/u-boot/board/ti/tnetv107xevm/Makefile5
-rw-r--r--qemu/roms/u-boot/board/ti/tnetv107xevm/config.mk5
-rw-r--r--qemu/roms/u-boot/board/ti/tnetv107xevm/sdb_board.c134
56 files changed, 0 insertions, 8579 deletions
diff --git a/qemu/roms/u-boot/board/ti/am335x/Makefile b/qemu/roms/u-boot/board/ti/am335x/Makefile
deleted file mode 100644
index 804ac379d..000000000
--- a/qemu/roms/u-boot/board/ti/am335x/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Makefile
-#
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
-obj-y := mux.o
-endif
-
-obj-y += board.o
diff --git a/qemu/roms/u-boot/board/ti/am335x/README b/qemu/roms/u-boot/board/ti/am335x/README
deleted file mode 100644
index 947305b58..000000000
--- a/qemu/roms/u-boot/board/ti/am335x/README
+++ /dev/null
@@ -1,205 +0,0 @@
-Summary
-=======
-
-This document covers various features of the 'am335x_evm' build, and some of
-the related build targets (am335x_evm_uartN, etc).
-
-Hardware
-========
-
-The binary produced by this board supports, based on parsing of the EEPROM
-documented in TI's reference designs:
-- AM335x GP EVM
-- AM335x EVM SK
-- Beaglebone White
-- Beaglebone Black
-
-Customization
-=============
-
-Given that all of the above boards are reference platforms (and the
-Beaglebone platforms are OSHA), it is likely that this platform code and
-configuration will be used as the basis of a custom platform. It is
-worth noting that aside from things such as NAND or MMC only being
-required if a custom platform makes use of these blocks, the following
-are required, depending on design:
-
-- GPIO is only required if DDR3 power is controlled in a way similar to
- EVM SK
-- SPI is only required for SPI flash, or exposing the SPI bus.
-
-The following blocks are required:
-- I2C, to talk with the PMIC and ensure that we do not run afoul of
- errata 1.0.24.
-
-When removing options as part of customization,
-CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your
-needs and to remove no longer relevant options as in some cases we
-define additional text blocks (such as for NAND or DFU strings). Also
-note that all of the SPL options are grouped together, rather than with
-the IP blocks, so both areas will need their choices updated to reflect
-the custom design.
-
-NAND
-====
-
-The AM335x GP EVM ships with a 256MiB NAND available in most profiles. In
-this example to program the NAND we assume that an SD card has been
-inserted with the files to write in the first SD slot and that mtdparts
-have been configured correctly for the board. All images are first loaded
-into memory, then written to NAND.
-
-Step-1: Building u-boot for NAND boot
- Set following CONFIGxx options for NAND device.
- CONFIG_SYS_NAND_PAGE_SIZE number of main bytes in NAND page
- CONFIG_SYS_NAND_OOBSIZE number of OOB bytes in NAND page
- CONFIG_SYS_NAND_BLOCK_SIZE number of bytes in NAND erase-block
- CONFIG_SYS_NAND_ECCPOS ECC map for NAND page
- CONFIG_NAND_OMAP_ECCSCHEME (refer doc/README.nand)
-
-Step-2: Flashing NAND via MMC/SD
- # select BOOTSEL to MMC/SD boot and boot from MMC/SD card
- U-Boot # mmc rescan
- # erase flash
- U-Boot # nand erase.chip
- U-Boot # env default -f -a
- U-Boot # saveenv
- # flash MLO. Redundant copies of MLO are kept for failsafe
- U-Boot # load mmc 0 0x82000000 MLO
- U-Boot # nand write 0x82000000 0x00000 0x20000
- U-Boot # nand write 0x82000000 0x20000 0x20000
- U-Boot # nand write 0x82000000 0x40000 0x20000
- U-Boot # nand write 0x82000000 0x60000 0x20000
- # flash u-boot.img
- U-Boot # load mmc 0 0x82000000 u-boot.img
- U-Boot # nand write 0x82000000 0x80000 0x60000
- # flash kernel image
- U-Boot # load mmc 0 0x82000000 uImage
- U-Boot # nand write 0x82000000 ${nandsrcaddr} ${nandimgsize}
- # flash filesystem image
- U-Boot # load mmc 0 0x82000000 filesystem.img
- U-Boot # nand write 0x82000000 ${loadaddress} 0x300000
-
-Step-3: Set BOOTSEL pin to select NAND boot, and POR the device.
- The device should boot from images flashed on NAND device.
-
-NOR
-===
-
-The Beaglebone White can be equiped with a "memory cape" that in turn can
-have a NOR module plugged into it. In this case it is then possible to
-program and boot from NOR. Note that due to how U-Boot is architectured we
-must build a specific version of U-Boot that knows we have NOR flash. This
-build is named 'am335x_evm_nor'. Further, we have a 'am335x_evm_norboot'
-build that will assume that the environment is on NOR rather than NAND. In
-the following example we assume that and SD card has been populated with
-MLO and u-boot.img from a 'am335x_evm_nor' build and also contains the
-'u-boot.bin' from a 'am335x_evm_norboot' build. When booting from NOR, a
-binary must be written to the start of NOR, with no header or similar
-prepended. In the following example we use a size of 512KiB (0x80000)
-as that is how much space we set aside before the environment, as per
-the config file.
-
-U-Boot # mmc rescan
-U-Boot # load mmc 0 ${loadaddr} u-boot.bin
-U-Boot # protect off 08000000 +80000
-U-Boot # erase 08000000 +80000
-U-Boot # cp.b ${loadaddr} 08000000 ${filesize}
-
-Falcon Mode
-===========
-
-The default build includes "Falcon Mode" (see doc/README.falcon) via NAND,
-eMMC (or raw SD cards) and FAT SD cards. Our default behavior currently is
-to read a 'c' on the console while in SPL at any point prior to loading the
-OS payload (so as soon as possible) to opt to booting full U-Boot. Also
-note that while one can program Falcon Mode "in place" great care needs to
-be taken by the user to not 'brick' their setup. As these are all eval
-boards with multiple boot methods, recovery should not be an issue in this
-worst-case however.
-
-Falcon Mode: eMMC
-=================
-
-The recommended layout in this case is:
-
-MMC BLOCKS |--------------------------------| LOCATION IN BYTES
-0x0000 - 0x007F : MBR or GPT table : 0x000000 - 0x020000
-0x0080 - 0x00FF : ARGS or FDT file : 0x010000 - 0x020000
-0x0100 - 0x01FF : SPL.backup1 (first copy used) : 0x020000 - 0x040000
-0x0200 - 0x02FF : SPL.backup2 (second copy used) : 0x040000 - 0x060000
-0x0300 - 0x06FF : U-Boot : 0x060000 - 0x0e0000
-0x0700 - 0x08FF : U-Boot Env + Redundant : 0x0e0000 - 0x120000
-0x0900 - 0x28FF : Kernel : 0x120000 - 0x520000
-
-Note that when we run 'spl export' it will prepare to boot the kernel.
-This includes relocation of the uImage from where we loaded it to the entry
-point defined in the header. As these locations overlap by default, it
-would leave us with an image that if written to MMC will not boot, so
-instead of using the loadaddr variable we use 0x81000000 in the following
-example. In this example we are loading from the network, for simplicity,
-and assume a valid partition table already exists and 'mmc dev' has already
-been run to select the correct device. Also note that if you previously
-had a FAT partition (such as on a Beaglebone Black) it is not enough to
-write garbage into the area, you must delete it from the partition table
-first.
-
-# Ensure we are able to talk with this mmc device
-U-Boot # mmc rescan
-U-Boot # tftp 81000000 am335x/MLO
-# Write to two of the backup locations ROM uses
-U-Boot # mmc write 81000000 100 100
-U-Boot # mmc write 81000000 200 100
-# Write U-Boot to the location set in the config
-U-Boot # tftp 81000000 am335x/u-boot.img
-U-Boot # mmc write 81000000 300 400
-# Load kernel and device tree into memory, perform export
-U-Boot # tftp 81000000 am335x/uImage
-U-Boot # run findfdt
-U-Boot # tftp ${fdtaddr} am335x/${fdtfile}
-U-Boot # run mmcargs
-U-Boot # spl export fdt 81000000 - ${fdtaddr}
-# Write the updated device tree to MMC
-U-Boot # mmc write ${fdtaddr} 80 80
-# Write the uImage to MMC
-U-Boot # mmc write 81000000 900 2000
-
-Falcon Mode: FAT SD cards
-=========================
-
-In this case the additional file is written to the filesystem. In this
-example we assume that the uImage and device tree to be used are already on
-the FAT filesystem (only the uImage MUST be for this to function
-afterwards) along with a Falcon Mode aware MLO and the FAT partition has
-already been created and marked bootable:
-
-U-Boot # mmc rescan
-# Load kernel and device tree into memory, perform export
-U-Boot # load mmc 0:1 ${loadaddr} uImage
-U-Boot # run findfdt
-U-Boot # load mmc 0:1 ${fdtaddr} ${fdtfile}
-U-Boot # run mmcargs
-U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
-
-This will print a number of lines and then end with something like:
- Using Device Tree in place at 80f80000, end 80f85928
- Using Device Tree in place at 80f80000, end 80f88928
-So then you:
-
-U-Boot # fatwrite mmc 0:1 0x80f80000 args 8928
-
-Falcon Mode: NAND
-=================
-
-In this case the additional data is written to another partition of the
-NAND. In this example we assume that the uImage and device tree to be are
-already located on the NAND somewhere (such as fileystem or mtd partition)
-along with a Falcon Mode aware MLO written to the correct locations for
-booting and mtdparts have been configured correctly for the board:
-
-U-Boot # nand read ${loadaddr} kernel
-U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb
-U-Boot # run nandargs
-U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
-U-Boot # nand erase.part u-boot-spl-os
-U-Boot # nand write ${fdtaddr} u-boot-spl-os
diff --git a/qemu/roms/u-boot/board/ti/am335x/board.c b/qemu/roms/u-boot/board/ti/am335x/board.c
deleted file mode 100644
index da780edb8..000000000
--- a/qemu/roms/u-boot/board/ti/am335x/board.c
+++ /dev/null
@@ -1,701 +0,0 @@
-/*
- * board.c
- *
- * Board functions for TI AM335X based boards
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <spl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mem.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <cpsw.h>
-#include <power/tps65217.h>
-#include <power/tps65910.h>
-#include <environment.h>
-#include <watchdog.h>
-#include <environment.h>
-#include "board.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* GPIO that controls power to DDR on EVM-SK */
-#define GPIO_DDR_VTT_EN 7
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-/*
- * Read header information from EEPROM into global structure.
- */
-static int read_eeprom(struct am335x_baseboard_id *header)
-{
- /* Check if baseboard eeprom is available */
- if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
- puts("Could not probe the EEPROM; something fundamentally "
- "wrong on the I2C bus.\n");
- return -ENODEV;
- }
-
- /* read the eeprom using i2c */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
- sizeof(struct am335x_baseboard_id))) {
- puts("Could not read the EEPROM; something fundamentally"
- " wrong on the I2C bus.\n");
- return -EIO;
- }
-
- if (header->magic != 0xEE3355AA) {
- /*
- * read the eeprom using i2c again,
- * but use only a 1 byte address
- */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
- sizeof(struct am335x_baseboard_id))) {
- puts("Could not read the EEPROM; something "
- "fundamentally wrong on the I2C bus.\n");
- return -EIO;
- }
-
- if (header->magic != 0xEE3355AA) {
- printf("Incorrect magic number (0x%x) in EEPROM\n",
- header->magic);
- return -EINVAL;
- }
- }
-
- return 0;
-}
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-static const struct ddr_data ddr2_data = {
- .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
- (MT47H128M16RT25E_RD_DQS<<20) |
- (MT47H128M16RT25E_RD_DQS<<10) |
- (MT47H128M16RT25E_RD_DQS<<0)),
- .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
- (MT47H128M16RT25E_WR_DQS<<20) |
- (MT47H128M16RT25E_WR_DQS<<10) |
- (MT47H128M16RT25E_WR_DQS<<0)),
- .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
- (MT47H128M16RT25E_PHY_WRLVL<<20) |
- (MT47H128M16RT25E_PHY_WRLVL<<10) |
- (MT47H128M16RT25E_PHY_WRLVL<<0)),
- .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
- (MT47H128M16RT25E_PHY_GATELVL<<20) |
- (MT47H128M16RT25E_PHY_GATELVL<<10) |
- (MT47H128M16RT25E_PHY_GATELVL<<0)),
- .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
- (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
- .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
- (MT47H128M16RT25E_PHY_WR_DATA<<20) |
- (MT47H128M16RT25E_PHY_WR_DATA<<10) |
- (MT47H128M16RT25E_PHY_WR_DATA<<0)),
-};
-
-static const struct cmd_control ddr2_cmd_ctrl_data = {
- .cmd0csratio = MT47H128M16RT25E_RATIO,
- .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
-
- .cmd1csratio = MT47H128M16RT25E_RATIO,
- .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
-
- .cmd2csratio = MT47H128M16RT25E_RATIO,
- .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
-};
-
-static const struct emif_regs ddr2_emif_reg_data = {
- .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
- .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
- .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
- .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
- .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
- .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
-};
-
-static const struct ddr_data ddr3_data = {
- .datardsratio0 = MT41J128MJT125_RD_DQS,
- .datawdsratio0 = MT41J128MJT125_WR_DQS,
- .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
- .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
-};
-
-static const struct ddr_data ddr3_beagleblack_data = {
- .datardsratio0 = MT41K256M16HA125E_RD_DQS,
- .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
- .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
- .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
-};
-
-static const struct ddr_data ddr3_evm_data = {
- .datardsratio0 = MT41J512M8RH125_RD_DQS,
- .datawdsratio0 = MT41J512M8RH125_WR_DQS,
- .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
- .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
- .cmd0csratio = MT41J128MJT125_RATIO,
- .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
-
- .cmd1csratio = MT41J128MJT125_RATIO,
- .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
-
- .cmd2csratio = MT41J128MJT125_RATIO,
- .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
-};
-
-static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
- .cmd0csratio = MT41K256M16HA125E_RATIO,
- .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
- .cmd1csratio = MT41K256M16HA125E_RATIO,
- .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-
- .cmd2csratio = MT41K256M16HA125E_RATIO,
- .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
-};
-
-static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
- .cmd0csratio = MT41J512M8RH125_RATIO,
- .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
-
- .cmd1csratio = MT41J512M8RH125_RATIO,
- .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
-
- .cmd2csratio = MT41J512M8RH125_RATIO,
- .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
- .sdram_config = MT41J128MJT125_EMIF_SDCFG,
- .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
- .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
- .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
- .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
- .zq_config = MT41J128MJT125_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
- PHY_EN_DYN_PWRDN,
-};
-
-static struct emif_regs ddr3_beagleblack_emif_reg_data = {
- .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
- .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
- .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
- .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
- .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
- .zq_config = MT41K256M16HA125E_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
-};
-
-static struct emif_regs ddr3_evm_emif_reg_data = {
- .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
- .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
- .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
- .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
- .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
- .zq_config = MT41J512M8RH125_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
- PHY_EN_DYN_PWRDN,
-};
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- /* break into full u-boot on 'c' */
- if (serial_tstc() && serial_getc() == 'c')
- return 1;
-
-#ifdef CONFIG_SPL_ENV_SUPPORT
- env_init();
- env_relocate_spec();
- if (getenv_yesno("boot_os") != 1)
- return 1;
-#endif
-
- return 0;
-}
-#endif
-
-#define OSC (V_OSCK/1000000)
-const struct dpll_params dpll_ddr = {
- 266, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_ddr_evm_sk = {
- 303, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_ddr_bone_black = {
- 400, OSC-1, 1, -1, -1, -1, -1};
-
-void am33xx_spl_board_init(void)
-{
- struct am335x_baseboard_id header;
- int mpu_vdd;
-
- if (read_eeprom(&header) < 0)
- puts("Could not get board ID.\n");
-
- /* Get the frequency */
- dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
-
- if (board_is_bone(&header) || board_is_bone_lt(&header)) {
- /* BeagleBone PMIC Code */
- int usb_cur_lim;
-
- /*
- * Only perform PMIC configurations if board rev > A1
- * on Beaglebone White
- */
- if (board_is_bone(&header) && !strncmp(header.version,
- "00A1", 4))
- return;
-
- if (i2c_probe(TPS65217_CHIP_PM))
- return;
-
- /*
- * On Beaglebone White we need to ensure we have AC power
- * before increasing the frequency.
- */
- if (board_is_bone(&header)) {
- uchar pmic_status_reg;
- if (tps65217_reg_read(TPS65217_STATUS,
- &pmic_status_reg))
- return;
- if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
- puts("No AC power, disabling frequency switch\n");
- return;
- }
- }
-
- /*
- * Override what we have detected since we know if we have
- * a Beaglebone Black it supports 1GHz.
- */
- if (board_is_bone_lt(&header))
- dpll_mpu_opp100.m = MPUPLL_M_1000;
-
- /*
- * Increase USB current limit to 1300mA or 1800mA and set
- * the MPU voltage controller as needed.
- */
- if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
- usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
- mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
- } else {
- usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
- mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
- }
-
- if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
- TPS65217_POWER_PATH,
- usb_cur_lim,
- TPS65217_USB_INPUT_CUR_LIMIT_MASK))
- puts("tps65217_reg_write failure\n");
-
- /* Set DCDC3 (CORE) voltage to 1.125V */
- if (tps65217_voltage_update(TPS65217_DEFDCDC3,
- TPS65217_DCDC_VOLT_SEL_1125MV)) {
- puts("tps65217_voltage_update failure\n");
- return;
- }
-
- /* Set CORE Frequencies to OPP100 */
- do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
-
- /* Set DCDC2 (MPU) voltage */
- if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
- puts("tps65217_voltage_update failure\n");
- return;
- }
-
- /*
- * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
- * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
- */
- if (board_is_bone(&header)) {
- if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
- TPS65217_DEFLS1,
- TPS65217_LDO_VOLTAGE_OUT_3_3,
- TPS65217_LDO_MASK))
- puts("tps65217_reg_write failure\n");
- } else {
- if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
- TPS65217_DEFLS1,
- TPS65217_LDO_VOLTAGE_OUT_1_8,
- TPS65217_LDO_MASK))
- puts("tps65217_reg_write failure\n");
- }
-
- if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
- TPS65217_DEFLS2,
- TPS65217_LDO_VOLTAGE_OUT_3_3,
- TPS65217_LDO_MASK))
- puts("tps65217_reg_write failure\n");
- } else {
- int sil_rev;
-
- /*
- * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
- * MPU frequencies we support we use a CORE voltage of
- * 1.1375V. For MPU voltage we need to switch based on
- * the frequency we are running at.
- */
- if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
- return;
-
- /*
- * Depending on MPU clock and PG we will need a different
- * VDD to drive at that speed.
- */
- sil_rev = readl(&cdev->deviceid) >> 28;
- mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
- dpll_mpu_opp100.m);
-
- /* Tell the TPS65910 to use i2c */
- tps65910_set_i2c_control();
-
- /* First update MPU voltage. */
- if (tps65910_voltage_update(MPU, mpu_vdd))
- return;
-
- /* Second, update the CORE voltage. */
- if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
- return;
-
- /* Set CORE Frequencies to OPP100 */
- do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
- }
-
- /* Set MPU Frequency to what we detected now that voltages are set */
- do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
-}
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
- struct am335x_baseboard_id header;
-
- enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
- if (read_eeprom(&header) < 0)
- puts("Could not get board ID.\n");
-
- if (board_is_evm_sk(&header))
- return &dpll_ddr_evm_sk;
- else if (board_is_bone_lt(&header))
- return &dpll_ddr_bone_black;
- else if (board_is_evm_15_or_later(&header))
- return &dpll_ddr_evm_sk;
- else
- return &dpll_ddr;
-}
-
-void set_uart_mux_conf(void)
-{
-#ifdef CONFIG_SERIAL1
- enable_uart0_pin_mux();
-#endif /* CONFIG_SERIAL1 */
-#ifdef CONFIG_SERIAL2
- enable_uart1_pin_mux();
-#endif /* CONFIG_SERIAL2 */
-#ifdef CONFIG_SERIAL3
- enable_uart2_pin_mux();
-#endif /* CONFIG_SERIAL3 */
-#ifdef CONFIG_SERIAL4
- enable_uart3_pin_mux();
-#endif /* CONFIG_SERIAL4 */
-#ifdef CONFIG_SERIAL5
- enable_uart4_pin_mux();
-#endif /* CONFIG_SERIAL5 */
-#ifdef CONFIG_SERIAL6
- enable_uart5_pin_mux();
-#endif /* CONFIG_SERIAL6 */
-}
-
-void set_mux_conf_regs(void)
-{
- __maybe_unused struct am335x_baseboard_id header;
-
- if (read_eeprom(&header) < 0)
- puts("Could not get board ID.\n");
-
- enable_board_pin_mux(&header);
-}
-
-const struct ctrl_ioregs ioregs_evmsk = {
- .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
- .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
- .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
- .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
- .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
-};
-
-const struct ctrl_ioregs ioregs_bonelt = {
- .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
- .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
-};
-
-const struct ctrl_ioregs ioregs_evm15 = {
- .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
- .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
- .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
- .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
- .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
-};
-
-const struct ctrl_ioregs ioregs = {
- .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
- .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
- .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
- .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
- .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
-};
-
-void sdram_init(void)
-{
- __maybe_unused struct am335x_baseboard_id header;
-
- if (read_eeprom(&header) < 0)
- puts("Could not get board ID.\n");
-
- if (board_is_evm_sk(&header)) {
- /*
- * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
- * This is safe enough to do on older revs.
- */
- gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
- gpio_direction_output(GPIO_DDR_VTT_EN, 1);
- }
-
- if (board_is_evm_sk(&header))
- config_ddr(303, &ioregs_evmsk, &ddr3_data,
- &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
- else if (board_is_bone_lt(&header))
- config_ddr(400, &ioregs_bonelt,
- &ddr3_beagleblack_data,
- &ddr3_beagleblack_cmd_ctrl_data,
- &ddr3_beagleblack_emif_reg_data, 0);
- else if (board_is_evm_15_or_later(&header))
- config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
- &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
- else
- config_ddr(266, &ioregs, &ddr2_data,
- &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
-}
-#endif
-
-/*
- * Basic board specific setup. Pinmux has been handled already.
- */
-int board_init(void)
-{
-#if defined(CONFIG_HW_WATCHDOG)
- hw_watchdog_init();
-#endif
-
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
- gpmc_init();
-#endif
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- char safe_string[HDR_NAME_LEN + 1];
- struct am335x_baseboard_id header;
-
- if (read_eeprom(&header) < 0)
- puts("Could not get board ID.\n");
-
- /* Now set variables based on the header. */
- strncpy(safe_string, (char *)header.name, sizeof(header.name));
- safe_string[sizeof(header.name)] = 0;
- setenv("board_name", safe_string);
-
- strncpy(safe_string, (char *)header.version, sizeof(header.version));
- safe_string[sizeof(header.version)] = 0;
- setenv("board_rev", safe_string);
-#endif
-
- return 0;
-}
-#endif
-
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
-
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 0,
- },
- {
- .slave_reg_ofs = 0x308,
- .sliver_reg_ofs = 0xdc0,
- .phy_addr = 1,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 1,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-#endif
-
-/*
- * This function will:
- * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
- * in the environment
- * Perform fixups to the PHY present on certain boards. We only need this
- * function in:
- * - SPL with either CPSW or USB ethernet support
- * - Full U-Boot, with either CPSW or USB ethernet
- * Build in only these cases to avoid warnings about unused variables
- * when we build an SPL that has neither option but full U-Boot will.
- */
-#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
- && defined(CONFIG_SPL_BUILD)) || \
- ((defined(CONFIG_DRIVER_TI_CPSW) || \
- defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
- !defined(CONFIG_SPL_BUILD))
-int board_eth_init(bd_t *bis)
-{
- int rv, n = 0;
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
- __maybe_unused struct am335x_baseboard_id header;
-
- /* try reading mac address from efuse */
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
- if (!getenv("ethaddr")) {
- printf("<ethaddr> not set. Validating first E-fuse MAC\n");
-
- if (is_valid_ether_addr(mac_addr))
- eth_setenv_enetaddr("ethaddr", mac_addr);
- }
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-
- mac_lo = readl(&cdev->macid1l);
- mac_hi = readl(&cdev->macid1h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (!getenv("eth1addr")) {
- if (is_valid_ether_addr(mac_addr))
- eth_setenv_enetaddr("eth1addr", mac_addr);
- }
-
- if (read_eeprom(&header) < 0)
- puts("Could not get board ID.\n");
-
- if (board_is_bone(&header) || board_is_bone_lt(&header) ||
- board_is_idk(&header)) {
- writel(MII_MODE_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
- PHY_INTERFACE_MODE_MII;
- } else {
- writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
- cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
- PHY_INTERFACE_MODE_RGMII;
- }
-
- rv = cpsw_register(&cpsw_data);
- if (rv < 0)
- printf("Error %d registering CPSW switch\n", rv);
- else
- n += rv;
-#endif
-
- /*
- *
- * CPSW RGMII Internal Delay Mode is not supported in all PVT
- * operating points. So we must set the TX clock delay feature
- * in the AR8051 PHY. Since we only support a single ethernet
- * device in U-Boot, we only do this for the first instance.
- */
-#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
-#define AR8051_PHY_DEBUG_DATA_REG 0x1e
-#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
-#define AR8051_RGMII_TX_CLK_DLY 0x100
-
- if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
- const char *devname;
- devname = miiphy_get_current_dev();
-
- miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
- AR8051_DEBUG_RGMII_CLK_DLY_REG);
- miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
- AR8051_RGMII_TX_CLK_DLY);
- }
-#endif
-#if defined(CONFIG_USB_ETHER) && \
- (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
- if (is_valid_ether_addr(mac_addr))
- eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
-
- rv = usb_eth_initialize(bis);
- if (rv < 0)
- printf("Error %d registering USB_ETHER\n", rv);
- else
- n += rv;
-#endif
- return n;
-}
-#endif
diff --git a/qemu/roms/u-boot/board/ti/am335x/board.h b/qemu/roms/u-boot/board/ti/am335x/board.h
deleted file mode 100644
index bc700d56f..000000000
--- a/qemu/roms/u-boot/board/ti/am335x/board.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * board.h
- *
- * TI AM335x boards information header
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * TI AM335x parts define a system EEPROM that defines certain sub-fields.
- * We use these fields to in turn see what board we are on, and what
- * that might require us to set or not set.
- */
-#define HDR_NO_OF_MAC_ADDR 3
-#define HDR_ETH_ALEN 6
-#define HDR_NAME_LEN 8
-
-struct am335x_baseboard_id {
- unsigned int magic;
- char name[HDR_NAME_LEN];
- char version[4];
- char serial[12];
- char config[32];
- char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
-};
-
-static inline int board_is_bone(struct am335x_baseboard_id *header)
-{
- return !strncmp(header->name, "A335BONE", HDR_NAME_LEN);
-}
-
-static inline int board_is_bone_lt(struct am335x_baseboard_id *header)
-{
- return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN);
-}
-
-static inline int board_is_evm_sk(struct am335x_baseboard_id *header)
-{
- return !strncmp("A335X_SK", header->name, HDR_NAME_LEN);
-}
-
-static inline int board_is_idk(struct am335x_baseboard_id *header)
-{
- return !strncmp(header->config, "SKU#02", 6);
-}
-
-static inline int board_is_gp_evm(struct am335x_baseboard_id *header)
-{
- return !strncmp("A33515BB", header->name, HDR_NAME_LEN);
-}
-
-static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header)
-{
- return (board_is_gp_evm(header) &&
- strncmp("1.5", header->version, 3) <= 0);
-}
-
-/*
- * We have three pin mux functions that must exist. We must be able to enable
- * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
- * main pinmux function that can be overridden to enable all other pinmux that
- * is required on the board.
- */
-void enable_uart0_pin_mux(void);
-void enable_uart1_pin_mux(void);
-void enable_uart2_pin_mux(void);
-void enable_uart3_pin_mux(void);
-void enable_uart4_pin_mux(void);
-void enable_uart5_pin_mux(void);
-void enable_i2c0_pin_mux(void);
-void enable_board_pin_mux(struct am335x_baseboard_id *header);
-#endif
diff --git a/qemu/roms/u-boot/board/ti/am335x/mux.c b/qemu/roms/u-boot/board/ti/am335x/mux.c
deleted file mode 100644
index b2bfda5ea..000000000
--- a/qemu/roms/u-boot/board/ti/am335x/mux.c
+++ /dev/null
@@ -1,385 +0,0 @@
-/*
- * mux.c
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include <i2c.h>
-#include "board.h"
-
-static struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
- {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart1_pin_mux[] = {
- {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
- {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart2_pin_mux[] = {
- {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
- {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart3_pin_mux[] = {
- {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
- {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart4_pin_mux[] = {
- {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
- {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
- {-1},
-};
-
-static struct module_pin_mux uart5_pin_mux[] = {
- {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
- {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
- {-1},
-};
-
-static struct module_pin_mux mmc0_pin_mux[] = {
- {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
- {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
- {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
- {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
- {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
- {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
- {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
- {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
- {-1},
-};
-
-static struct module_pin_mux mmc0_no_cd_pin_mux[] = {
- {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
- {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
- {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
- {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
- {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
- {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
- {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
- {-1},
-};
-
-static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
- {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
- {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
- {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
- {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
- {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
- {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
- {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
- {-1},
-};
-
-static struct module_pin_mux mmc1_pin_mux[] = {
- {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
- {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
- {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
- {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
- {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
- {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
- {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
- {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */
- {-1},
-};
-
-static struct module_pin_mux i2c0_pin_mux[] = {
- {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
- {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
- {-1},
-};
-
-static struct module_pin_mux i2c1_pin_mux[] = {
- {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
- {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
- {-1},
-};
-
-static struct module_pin_mux spi0_pin_mux[] = {
- {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
- {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
- PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
- {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
- {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
- PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
- {-1},
-};
-
-static struct module_pin_mux gpio0_7_pin_mux[] = {
- {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
- {-1},
-};
-
-static struct module_pin_mux rgmii1_pin_mux[] = {
- {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
- {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
- {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
- {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
- {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
- {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
- {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
- {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
- {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
- {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
- {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
- {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
- {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
- {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
- {-1},
-};
-
-static struct module_pin_mux mii1_pin_mux[] = {
- {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
- {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
- {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
- {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
- {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
- {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
- {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
- {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
- {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
- {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
- {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
- {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
- {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
- {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
- {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
- {-1},
-};
-
-static struct module_pin_mux nand_pin_mux[] = {
- {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
- {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
- {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
- {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
- {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
- {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
- {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
- {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
- {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
- {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
- {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
- {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
- {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
- {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
- {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
- {-1},
-};
-
-#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
-static struct module_pin_mux bone_norcape_pin_mux[] = {
- {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */
- {OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A1 */
- {OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A2 */
- {OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A3 */
- {OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A4 */
- {OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A5 */
- {OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A6 */
- {OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A7 */
- {OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A8 */
- {OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A9 */
- {OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A10 */
- {OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */
- {OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A12 */
- {OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A13 */
- {OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A14 */
- {OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A15 */
- {OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A16 */
- {OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A17 */
- {OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A18 */
- {OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A19 */
- {OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD0 */
- {OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD1 */
- {OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD2 */
- {OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD3 */
- {OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD4 */
- {OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD5 */
- {OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD6 */
- {OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD7 */
- {OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD8 */
- {OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD9 */
- {OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD10 */
- {OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD11 */
- {OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD12 */
- {OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD13 */
- {OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD14 */
- {OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD15 */
-
- {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_CE */
- {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_ADVN_ALE */
- {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */
- {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_BE0N_CLE */
- {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)}, /* NOR_WEN */
- {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */
- {-1},
-};
-#endif
-
-#if defined(CONFIG_NOR_BOOT)
-static struct module_pin_mux norboot_pin_mux[] = {
- {OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
- {OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
- {OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
- {OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
- {OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
- {OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
- {OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
- {OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
- {OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
- {-1},
-};
-
-void enable_norboot_pin_mux(void)
-{
- configure_module_pin_mux(norboot_pin_mux);
-}
-#endif
-
-void enable_uart0_pin_mux(void)
-{
- configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_uart1_pin_mux(void)
-{
- configure_module_pin_mux(uart1_pin_mux);
-}
-
-void enable_uart2_pin_mux(void)
-{
- configure_module_pin_mux(uart2_pin_mux);
-}
-
-void enable_uart3_pin_mux(void)
-{
- configure_module_pin_mux(uart3_pin_mux);
-}
-
-void enable_uart4_pin_mux(void)
-{
- configure_module_pin_mux(uart4_pin_mux);
-}
-
-void enable_uart5_pin_mux(void)
-{
- configure_module_pin_mux(uart5_pin_mux);
-}
-
-void enable_i2c0_pin_mux(void)
-{
- configure_module_pin_mux(i2c0_pin_mux);
-}
-
-/*
- * The AM335x GP EVM, if daughter card(s) are connected, can have 8
- * different profiles. These profiles determine what peripherals are
- * valid and need pinmux to be configured.
- */
-#define PROFILE_NONE 0x0
-#define PROFILE_0 (1 << 0)
-#define PROFILE_1 (1 << 1)
-#define PROFILE_2 (1 << 2)
-#define PROFILE_3 (1 << 3)
-#define PROFILE_4 (1 << 4)
-#define PROFILE_5 (1 << 5)
-#define PROFILE_6 (1 << 6)
-#define PROFILE_7 (1 << 7)
-#define PROFILE_MASK 0x7
-#define PROFILE_ALL 0xFF
-
-/* CPLD registers */
-#define I2C_CPLD_ADDR 0x35
-#define CFG_REG 0x10
-
-static unsigned short detect_daughter_board_profile(void)
-{
- unsigned short val;
-
- if (i2c_probe(I2C_CPLD_ADDR))
- return PROFILE_NONE;
-
- if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
- return PROFILE_NONE;
-
- return (1 << (val & PROFILE_MASK));
-}
-
-void enable_board_pin_mux(struct am335x_baseboard_id *header)
-{
- /* Do board-specific muxes. */
- if (board_is_bone(header)) {
- /* Beaglebone pinmux */
- configure_module_pin_mux(i2c1_pin_mux);
- configure_module_pin_mux(mii1_pin_mux);
- configure_module_pin_mux(mmc0_pin_mux);
-#ifndef CONFIG_NOR
- configure_module_pin_mux(mmc1_pin_mux);
-#endif
-#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
- configure_module_pin_mux(bone_norcape_pin_mux);
-#endif
- } else if (board_is_gp_evm(header)) {
- /* General Purpose EVM */
- unsigned short profile = detect_daughter_board_profile();
- configure_module_pin_mux(rgmii1_pin_mux);
- configure_module_pin_mux(mmc0_pin_mux);
- /* In profile #2 i2c1 and spi0 conflict. */
- if (profile & ~PROFILE_2)
- configure_module_pin_mux(i2c1_pin_mux);
- /* Profiles 2 & 3 don't have NAND */
- if (profile & ~(PROFILE_2 | PROFILE_3))
- configure_module_pin_mux(nand_pin_mux);
- else if (profile == PROFILE_2) {
- configure_module_pin_mux(mmc1_pin_mux);
- configure_module_pin_mux(spi0_pin_mux);
- }
- } else if (board_is_idk(header)) {
- /*
- * Industrial Motor Control (IDK)
- * note: IDK console is on UART3 by default.
- * So u-boot mus be build with CONFIG_SERIAL4 and
- * CONFIG_CONS_INDEX=4
- */
- configure_module_pin_mux(mii1_pin_mux);
- configure_module_pin_mux(mmc0_no_cd_pin_mux);
- } else if (board_is_evm_sk(header)) {
- /* Starter Kit EVM */
- configure_module_pin_mux(i2c1_pin_mux);
- configure_module_pin_mux(gpio0_7_pin_mux);
- configure_module_pin_mux(rgmii1_pin_mux);
- configure_module_pin_mux(mmc0_pin_mux_sk_evm);
- } else if (board_is_bone_lt(header)) {
- /* Beaglebone LT pinmux */
- configure_module_pin_mux(i2c1_pin_mux);
- configure_module_pin_mux(mii1_pin_mux);
- configure_module_pin_mux(mmc0_pin_mux);
- configure_module_pin_mux(mmc1_pin_mux);
- } else {
- puts("Unknown board, cannot configure pinmux.");
- hang();
- }
-}
diff --git a/qemu/roms/u-boot/board/ti/am335x/u-boot.lds b/qemu/roms/u-boot/board/ti/am335x/u-boot.lds
deleted file mode 100644
index a9e3d34df..000000000
--- a/qemu/roms/u-boot/board/ti/am335x/u-boot.lds
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.__image_copy_start)
- CPUDIR/start.o (.text*)
- board/ti/am335x/built-in.o (.text*)
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN(4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- .end :
- {
- *(.__end)
- }
-
- _image_binary_end = .;
-
- /*
- * Deprecated: this MMU section is used by pxa at present but
- * should not be used by new boards/CPUs.
- */
- . = ALIGN(4096);
- .mmutable : {
- *(.mmutable)
- }
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
-
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _image_binary_end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .hash : { *(.hash*) }
- .gnu.hash : { *(.gnu.hash) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
diff --git a/qemu/roms/u-boot/board/ti/am3517crane/Makefile b/qemu/roms/u-boot/board/ti/am3517crane/Makefile
deleted file mode 100644
index 9da795de9..000000000
--- a/qemu/roms/u-boot/board/ti/am3517crane/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Author: Srinath R <srinath@mistralsolutions.com>
-#
-# Based on logicpd/am3517evm/Makefile
-#
-# Copyright (C) 2011 Mistral Solutions Pvt Ltd
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := am3517crane.o
diff --git a/qemu/roms/u-boot/board/ti/am3517crane/am3517crane.c b/qemu/roms/u-boot/board/ti/am3517crane/am3517crane.c
deleted file mode 100644
index a64969725..000000000
--- a/qemu/roms/u-boot/board/ti/am3517crane/am3517crane.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * am3517crane.c - board file for AM3517 CraneBoard
- *
- * Author: Srinath.R <srinath@mistralsolutions.com>
- *
- * Based on logicpd/am3517evm/am3517evm.c
- *
- * Copyright (C) 2011 Mistral Solutions Pvt Ltd
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-types.h>
-#include <i2c.h>
-#include "am3517crane.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* board id for Linux */
- gd->bd->bi_arch_number = MACH_TYPE_CRANEBOARD;
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- return 0;
-}
-
-/*
- * Routine: misc_init_r
- * Description: Init i2c, ethernet, etc... (done here so udelay works)
- */
-int misc_init_r(void)
-{
-#ifdef CONFIG_SYS_I2C_OMAP34XX
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-#endif
-
- dieid_num_r();
-
- return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_AM3517CRANE();
-}
-
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
diff --git a/qemu/roms/u-boot/board/ti/am3517crane/am3517crane.h b/qemu/roms/u-boot/board/ti/am3517crane/am3517crane.h
deleted file mode 100644
index e131c8fb9..000000000
--- a/qemu/roms/u-boot/board/ti/am3517crane/am3517crane.h
+++ /dev/null
@@ -1,344 +0,0 @@
-/*
- * am3517crane.h - Header file for the AM3517 CraneBoard.
- *
- * Author: Srinath R <srinath@mistralsolutions.com>
- *
- * Based on logicpd/am3517evm/am3517evm.h
- *
- * Copyright (C) 2011 Mistral Solutions Pvt Ltd
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _AM3517CRANE_H_
-#define _AM3517CRANE_H_
-
-const omap3_sysinfo sysinfo = {
- DDR_DISCRETE,
- "CraneBoard",
- "NAND",
-};
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_AM3517CRANE()\
- /*SDRC*/\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_CKE0), (M0))\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0))\
- MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0))\
- MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0))\
- MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0))\
- MUX_VAL(CP(SDRC_CKE0), (M0))\
- MUX_VAL(CP(SDRC_CKE1), (M0))\
- /*sdrc_strben_dly0*/\
- MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0))\
- /*sdrc_strben_dly1*/\
- MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0))\
- /*GPMC*/\
- MUX_VAL(CP(GPMC_A1), (M7))\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTU | DIS | M4))\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M4))\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M4))\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M4))\
- MUX_VAL(CP(GPMC_A6), (M7))\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M4))\
- MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(GPMC_A9), (M7))\
- MUX_VAL(CP(GPMC_A10), (M7))\
- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M4))\
- MUX_VAL(CP(GPMC_NCS2), (M7))\
- MUX_VAL(CP(GPMC_NCS3), (M7))\
- MUX_VAL(CP(GPMC_NCS4), (M7))\
- MUX_VAL(CP(GPMC_NCS5), (M7))\
- MUX_VAL(CP(GPMC_NCS6), (M7))\
- MUX_VAL(CP(GPMC_NCS7), (M7))\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0))/*TP*/\
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_NBE1), (M7))\
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_WAIT1), (M7))\
- MUX_VAL(CP(GPMC_WAIT2), (M7))\
- MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4))/*GPIO_65*/\
- /*DSS*/\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0))\
- /*MMC1*/\
- MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0))\
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0))\
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0))\
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0))\
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0))\
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | DIS | M0))\
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | DIS | M0))\
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | DIS | M0))\
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M0))\
- /*MMC2*/\
- MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0))\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | DIS | M0))\
- /*McBSP*/\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0))\
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0))\
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0))\
- \
- MUX_VAL(CP(MCBSP2_FSX), (M7))\
- MUX_VAL(CP(MCBSP2_CLKX), (M7))\
- MUX_VAL(CP(MCBSP2_DR), (M7))\
- MUX_VAL(CP(MCBSP2_DX), (M7))\
- \
- MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0))\
- \
- MUX_VAL(CP(MCBSP4_CLKX), (M7))\
- MUX_VAL(CP(MCBSP4_DR), (M7))\
- MUX_VAL(CP(MCBSP4_DX), (M7))\
- MUX_VAL(CP(MCBSP4_FSX), (M7))\
- /*UART*/\
- MUX_VAL(CP(UART1_TX), (M7))\
- MUX_VAL(CP(UART1_RTS), (M7))\
- MUX_VAL(CP(UART1_CTS), (M7))\
- MUX_VAL(CP(UART1_RX), (M7))\
- \
- MUX_VAL(CP(UART2_CTS), (M7))\
- MUX_VAL(CP(UART2_RTS), (M7))\
- MUX_VAL(CP(UART2_TX), (M7))\
- MUX_VAL(CP(UART2_RX), (M7))\
- \
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0))\
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0))\
- /*I2C 1, 2, 3*/\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\
- /*McSPI*/\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4))/*GPIO_171 TP*/\
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4))/*GPIO_172 TP*/\
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTU | EN | M4))/*GPIO_173 TP*/\
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTU | EN | M4))/*GPIO_174 TP*/\
- MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4))/*GPIO_175 TP*/\
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4))/*GPIO_176 TP*/\
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4))/*GPIO_176 TP*/\
- \
- MUX_VAL(CP(MCSPI2_CLK), (M7))\
- MUX_VAL(CP(MCSPI2_SIMO), (M7))\
- MUX_VAL(CP(MCSPI2_SOMI), (M7))\
- MUX_VAL(CP(MCSPI2_CS0), (M7))\
- MUX_VAL(CP(MCSPI2_CS1), (M7))\
- /*CCDC*/\
- MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1))/*CCDC_DATA8*/\
- MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1))/*CCDC_DATA9 */\
- MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0))\
- /*RMII*/\
- MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0))\
- MUX_VAL(CP(RMII_MDIO_CLK), (M0))\
- MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0))\
- MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0))\
- MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0))\
- MUX_VAL(CP(RMII_RXER), (PTD | M0))\
- MUX_VAL(CP(RMII_TXD0), (PTD | M0))\
- MUX_VAL(CP(RMII_TXD1), (PTD | M0))\
- MUX_VAL(CP(RMII_TXEN), (PTD | M0))\
- MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0))\
- /*HECC*/\
- MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0))\
- /*HSUSB*/\
- MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0))\
- /*HDQ*/\
- MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4))\
- /*Control and debug*/\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M4))/*GPIO_1 TPS_SLEEP*/\
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0))\
- /*SYS_nRESWARM*/\
- MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | EN | M0))/*GPIO_30 ToExp*/\
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0))\
- MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0))\
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))/*GPIO_10 TP*/\
- MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0))\
- /*JTAG*/\
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0))\
- /*ETK (ES2 onwards)*/\
- MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M3))\
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3))\
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M3))\
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M3))\
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3))\
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M3))\
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M3))\
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M3))\
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M3))\
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M3))\
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M3))\
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M3))\
- MUX_VAL(CP(ETK_D10_ES2), (M7))\
- MUX_VAL(CP(ETK_D11_ES2), (M7))\
- MUX_VAL(CP(ETK_D12_ES2), (M7))\
- MUX_VAL(CP(ETK_D13_ES2), (M7))\
- MUX_VAL(CP(ETK_D14_ES2), (M7))\
- MUX_VAL(CP(ETK_D15_ES2), (M7))\
- /*Die to Die*/\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0))\
-
-#endif /* _AM3517CRANE_H_ */
diff --git a/qemu/roms/u-boot/board/ti/am43xx/Makefile b/qemu/roms/u-boot/board/ti/am43xx/Makefile
deleted file mode 100644
index cb5fe8890..000000000
--- a/qemu/roms/u-boot/board/ti/am43xx/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Makefile
-#
-# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-y := mux.o
-endif
-
-obj-y += board.o
diff --git a/qemu/roms/u-boot/board/ti/am43xx/board.c b/qemu/roms/u-boot/board/ti/am43xx/board.c
deleted file mode 100644
index d7449770a..000000000
--- a/qemu/roms/u-boot/board/ti/am43xx/board.c
+++ /dev/null
@@ -1,502 +0,0 @@
-/*
- * board.c
- *
- * Board functions for TI AM43XX based boards
- *
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/errno.h>
-#include <spl.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/gpio.h>
-#include <asm/emif.h>
-#include "board.h"
-#include <miiphy.h>
-#include <cpsw.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-/*
- * Read header information from EEPROM into global structure.
- */
-static int read_eeprom(struct am43xx_board_id *header)
-{
- /* Check if baseboard eeprom is available */
- if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
- printf("Could not probe the EEPROM at 0x%x\n",
- CONFIG_SYS_I2C_EEPROM_ADDR);
- return -ENODEV;
- }
-
- /* read the eeprom using i2c */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
- sizeof(struct am43xx_board_id))) {
- printf("Could not read the EEPROM\n");
- return -EIO;
- }
-
- if (header->magic != 0xEE3355AA) {
- /*
- * read the eeprom using i2c again,
- * but use only a 1 byte address
- */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
- sizeof(struct am43xx_board_id))) {
- printf("Could not read the EEPROM at 0x%x\n",
- CONFIG_SYS_I2C_EEPROM_ADDR);
- return -EIO;
- }
-
- if (header->magic != 0xEE3355AA) {
- printf("Incorrect magic number (0x%x) in EEPROM\n",
- header->magic);
- return -EINVAL;
- }
- }
-
- strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
- am43xx_board_name[sizeof(header->name)] = 0;
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-
-#define NUM_OPPS 6
-
-const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
- { /* 19.2 MHz */
- {-1, -1, -1, -1, -1, -1, -1}, /* OPP 50 */
- {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
- {-1, -1, -1, -1, -1, -1, -1}, /* OPP 100 */
- {-1, -1, -1, -1, -1, -1, -1}, /* OPP 120 */
- {-1, -1, -1, -1, -1, -1, -1}, /* OPP TB */
- {-1, -1, -1, -1, -1, -1, -1} /* OPP NT */
- },
- { /* 24 MHz */
- {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
- {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
- {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
- {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
- {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
- {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
- },
- { /* 25 MHz */
- {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
- {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
- {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
- {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
- {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
- {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
- },
- { /* 26 MHz */
- {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
- {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
- {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
- {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
- {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
- {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
- },
-};
-
-const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
- {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
- {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
- {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
-};
-
-const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
- {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {960, 23, 5, -1, -1, -1, -1}, /* 24 MHz */
- {960, 24, 5, -1, -1, -1, -1}, /* 25 MHz */
- {960, 25, 5, -1, -1, -1, -1} /* 26 MHz */
-};
-
-const struct dpll_params epos_evm_dpll_ddr = {
- 266, 24, 1, -1, 1, -1, -1};
-
-const struct dpll_params gp_evm_dpll_ddr = {
- 400, 23, 1, -1, 1, -1, -1};
-
-const struct ctrl_ioregs ioregs_lpddr2 = {
- .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
- .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
- .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
- .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
- .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
- .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
- .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
- .emif_sdram_config_ext = 0x1,
-};
-
-const struct emif_regs emif_regs_lpddr2 = {
- .sdram_config = 0x808012BA,
- .ref_ctrl = 0x0000040D,
- .sdram_tim1 = 0xEA86B411,
- .sdram_tim2 = 0x103A094A,
- .sdram_tim3 = 0x0F6BA37F,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x50074BE4,
- .temp_alert_config = 0x0,
- .emif_rd_wr_lvl_rmp_win = 0x0,
- .emif_rd_wr_lvl_rmp_ctl = 0x0,
- .emif_rd_wr_lvl_ctl = 0x0,
- .emif_ddr_phy_ctlr_1 = 0x0E084006,
- .emif_rd_wr_exec_thresh = 0x00000405,
- .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
- .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
- .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
- .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
- .emif_ddr_ext_phy_ctrl_5 = 0x00500050
-};
-
-const u32 ext_phy_ctrl_const_base_lpddr2[] = {
- 0x00500050,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x40001000,
- 0x08102040
-};
-
-const struct ctrl_ioregs ioregs_ddr3 = {
- .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
- .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
- .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
- .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
- .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
- .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
- .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
- .emif_sdram_config_ext = 0x0143,
-};
-
-const struct emif_regs ddr3_emif_regs_400Mhz = {
- .sdram_config = 0x638413B2,
- .ref_ctrl = 0x00000C30,
- .sdram_tim1 = 0xEAAAD4DB,
- .sdram_tim2 = 0x266B7FDA,
- .sdram_tim3 = 0x107F8678,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x50074BE4,
- .temp_alert_config = 0x0,
- .emif_ddr_phy_ctlr_1 = 0x0E004008,
- .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
- .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
- .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
- .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
- .emif_ddr_ext_phy_ctrl_5 = 0x00400040,
- .emif_rd_wr_lvl_rmp_win = 0x0,
- .emif_rd_wr_lvl_rmp_ctl = 0x0,
- .emif_rd_wr_lvl_ctl = 0x0,
- .emif_rd_wr_exec_thresh = 0x00000405
-};
-
-const u32 ext_phy_ctrl_const_base_ddr3[] = {
- 0x00400040,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00350035,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00340034,
- 0x00340034,
- 0x00340034,
- 0x00340034,
- 0x00340034,
- 0x0,
- 0x0,
- 0x40000000,
- 0x08102040
-};
-
-void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
-{
- if (board_is_eposevm()) {
- *regs = ext_phy_ctrl_const_base_lpddr2;
- *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
- } else if (board_is_gpevm()) {
- *regs = ext_phy_ctrl_const_base_ddr3;
- *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
- }
-
- return;
-}
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
- struct am43xx_board_id header;
-
- enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
- if (read_eeprom(&header) < 0)
- puts("Could not get board ID.\n");
-
- if (board_is_eposevm())
- return &epos_evm_dpll_ddr;
- else if (board_is_gpevm())
- return &gp_evm_dpll_ddr;
-
- puts(" Board not supported\n");
- return NULL;
-}
-
-/*
- * get_sys_clk_index : returns the index of the sys_clk read from
- * ctrl status register. This value is either
- * read from efuse or sysboot pins.
- */
-static u32 get_sys_clk_index(void)
-{
- struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
- u32 ind = readl(&ctrl->statusreg), src;
-
- src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
- if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
- return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
- CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
- else /* Value read from SYS BOOT pins */
- return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
- CTRL_SYSBOOT_15_14_SHIFT);
-}
-
-/*
- * get_opp_offset:
- * Returns the index for safest OPP of the device to boot.
- * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
- * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
- * This data is read from dev_attribute register which is e-fused.
- * A'1' in bit indicates OPP disabled and not available, a '0' indicates
- * OPP available. Lowest OPP starts with min_off. So returning the
- * bit with rightmost '0'.
- */
-static int get_opp_offset(int max_off, int min_off)
-{
- struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
- int opp = readl(&ctrl->dev_attr), offset, i;
-
- for (i = max_off; i >= min_off; i--) {
- offset = opp & (1 << i);
- if (!offset)
- return i;
- }
-
- return min_off;
-}
-
-const struct dpll_params *get_dpll_mpu_params(void)
-{
- int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
- u32 ind = get_sys_clk_index();
-
- return &dpll_mpu[ind][opp];
-}
-
-const struct dpll_params *get_dpll_core_params(void)
-{
- int ind = get_sys_clk_index();
-
- return &dpll_core[ind];
-}
-
-const struct dpll_params *get_dpll_per_params(void)
-{
- int ind = get_sys_clk_index();
-
- return &dpll_per[ind];
-}
-
-void set_uart_mux_conf(void)
-{
- enable_uart0_pin_mux();
-}
-
-void set_mux_conf_regs(void)
-{
- enable_board_pin_mux();
-}
-
-static void enable_vtt_regulator(void)
-{
- u32 temp;
-
- /* enable module */
- writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
-
- /* enable output for GPIO5_7 */
- writel(GPIO_SETDATAOUT(7),
- AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
- temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
- temp = temp & ~(GPIO_OE_ENABLE(7));
- writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
-}
-
-void sdram_init(void)
-{
- /*
- * EPOS EVM has 1GB LPDDR2 connected to EMIF.
- * GP EMV has 1GB DDR3 connected to EMIF
- * along with VTT regulator.
- */
- if (board_is_eposevm()) {
- config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
- } else if (board_is_gpevm()) {
- enable_vtt_regulator();
- config_ddr(0, &ioregs_ddr3, NULL, NULL,
- &ddr3_emif_regs_400Mhz, 0);
- }
-}
-#endif
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- char safe_string[HDR_NAME_LEN + 1];
- struct am43xx_board_id header;
-
- if (read_eeprom(&header) < 0)
- puts("Could not get board ID.\n");
-
- /* Now set variables based on the header. */
- strncpy(safe_string, (char *)header.name, sizeof(header.name));
- safe_string[sizeof(header.name)] = 0;
- setenv("board_name", safe_string);
-
- strncpy(safe_string, (char *)header.version, sizeof(header.version));
- safe_string[sizeof(header.version)] = 0;
- setenv("board_rev", safe_string);
-#endif
- return 0;
-}
-#endif
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-
-static void cpsw_control(int enabled)
-{
- /* Additional controls can be added here */
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 16,
- },
- {
- .slave_reg_ofs = 0x308,
- .sliver_reg_ofs = 0xdc0,
- .phy_addr = 1,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 1,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-
-int board_eth_init(bd_t *bis)
-{
- int rv;
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
-
- /* try reading mac address from efuse */
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (!getenv("ethaddr")) {
- puts("<ethaddr> not set. Validating first E-fuse MAC\n");
- if (is_valid_ether_addr(mac_addr))
- eth_setenv_enetaddr("ethaddr", mac_addr);
- }
-
- mac_lo = readl(&cdev->macid1l);
- mac_hi = readl(&cdev->macid1h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (!getenv("eth1addr")) {
- if (is_valid_ether_addr(mac_addr))
- eth_setenv_enetaddr("eth1addr", mac_addr);
- }
-
- if (board_is_eposevm()) {
- writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
- cpsw_slaves[0].phy_addr = 16;
- } else {
- writel(RGMII_MODE_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
- cpsw_slaves[0].phy_addr = 0;
- }
-
- rv = cpsw_register(&cpsw_data);
- if (rv < 0)
- printf("Error %d registering CPSW switch\n", rv);
-
- return rv;
-}
-#endif
diff --git a/qemu/roms/u-boot/board/ti/am43xx/board.h b/qemu/roms/u-boot/board/ti/am43xx/board.h
deleted file mode 100644
index 091162ee2..000000000
--- a/qemu/roms/u-boot/board/ti/am43xx/board.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * board.h
- *
- * TI AM437x boards information header
- * Derived from AM335x board.
- *
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-#include <asm/arch/omap.h>
-
-static char *const am43xx_board_name = (char *)AM4372_BOARD_NAME_START;
-
-/*
- * TI AM437x EVMs define a system EEPROM that defines certain sub-fields.
- * We use these fields to in turn see what board we are on, and what
- * that might require us to set or not set.
- */
-#define HDR_NO_OF_MAC_ADDR 3
-#define HDR_ETH_ALEN 6
-#define HDR_NAME_LEN 8
-
-#define DEV_ATTR_MAX_OFFSET 5
-#define DEV_ATTR_MIN_OFFSET 0
-
-struct am43xx_board_id {
- unsigned int magic;
- char name[HDR_NAME_LEN];
- char version[4];
- char serial[12];
- char config[32];
- char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
-};
-
-static inline int board_is_eposevm(void)
-{
- return !strncmp(am43xx_board_name, "AM43EPOS", HDR_NAME_LEN);
-}
-
-static inline int board_is_gpevm(void)
-{
- return !strncmp(am43xx_board_name, "AM43__GP", HDR_NAME_LEN);
-}
-
-void enable_uart0_pin_mux(void);
-void enable_board_pin_mux(void);
-void enable_i2c0_pin_mux(void);
-#endif
diff --git a/qemu/roms/u-boot/board/ti/am43xx/mux.c b/qemu/roms/u-boot/board/ti/am43xx/mux.c
deleted file mode 100644
index 77c53d2e9..000000000
--- a/qemu/roms/u-boot/board/ti/am43xx/mux.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * mux.c
- *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mux.h>
-#include "board.h"
-
-static struct module_pin_mux rmii1_pin_mux[] = {
- {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
- {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TD1 */
- {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TD0 */
- {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RD1 */
- {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RD0 */
- {OFFSET(mii1_rxdv), MODE(1) | RXACTIVE}, /* RMII1_RXDV */
- {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */
- {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
- {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_refclk */
- {-1},
-};
-
-static struct module_pin_mux rgmii1_pin_mux[] = {
- {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
- {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
- {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
- {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
- {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
- {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
- {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
- {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
- {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
- {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
- {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
- {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
- {-1},
-};
-
-static struct module_pin_mux mdio_pin_mux[] = {
- {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
- {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
- {-1},
-};
-
-static struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
- {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
- {-1},
-};
-
-static struct module_pin_mux mmc0_pin_mux[] = {
- {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* MMC0_CLK */
- {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_CMD */
- {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT0 */
- {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT1 */
- {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT2 */
- {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT3 */
- {-1},
-};
-
-static struct module_pin_mux i2c0_pin_mux[] = {
- {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
- {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
- {-1},
-};
-
-static struct module_pin_mux gpio5_7_pin_mux[] = {
- {OFFSET(spi0_cs0), (MODE(7) | PULLUP_EN)}, /* GPIO5_7 */
- {-1},
-};
-
-static struct module_pin_mux qspi_pin_mux[] = {
- {OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
- {OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
- {OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */
- {OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */
- {OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */
- {OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */
- {-1},
-};
-
-void enable_uart0_pin_mux(void)
-{
- configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_board_pin_mux(void)
-{
- configure_module_pin_mux(mmc0_pin_mux);
- configure_module_pin_mux(i2c0_pin_mux);
- configure_module_pin_mux(mdio_pin_mux);
-
- if (board_is_gpevm()) {
- configure_module_pin_mux(gpio5_7_pin_mux);
- configure_module_pin_mux(rgmii1_pin_mux);
- } else if (board_is_eposevm()) {
- configure_module_pin_mux(rmii1_pin_mux);
- configure_module_pin_mux(qspi_pin_mux);
- }
-}
-
-void enable_i2c0_pin_mux(void)
-{
- configure_module_pin_mux(i2c0_pin_mux);
-}
diff --git a/qemu/roms/u-boot/board/ti/beagle/Makefile b/qemu/roms/u-boot/board/ti/beagle/Makefile
deleted file mode 100644
index 7a858be5e..000000000
--- a/qemu/roms/u-boot/board/ti/beagle/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := beagle.o
-obj-$(CONFIG_STATUS_LED) += led.o
diff --git a/qemu/roms/u-boot/board/ti/beagle/beagle.c b/qemu/roms/u-boot/board/ti/beagle/beagle.c
deleted file mode 100644
index 0674afdc0..000000000
--- a/qemu/roms/u-boot/board/ti/beagle/beagle.c
+++ /dev/null
@@ -1,553 +0,0 @@
-/*
- * (C) Copyright 2004-2011
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Sunil Kumar <sunilsaini05@gmail.com>
- * Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#ifdef CONFIG_STATUS_LED
-#include <status_led.h>
-#endif
-#include <twl4030.h>
-#include <linux/mtd/nand.h>
-#include <asm/io.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/omap_musb.h>
-#include <asm/errno.h>
-#include <linux/usb/ch9.h>
-#include <linux/usb/gadget.h>
-#include <linux/usb/musb.h>
-#include "beagle.h"
-#include <command.h>
-
-#ifdef CONFIG_USB_EHCI
-#include <usb.h>
-#include <asm/ehci-omap.h>
-#endif
-
-#define TWL4030_I2C_BUS 0
-#define EXPANSION_EEPROM_I2C_BUS 1
-#define EXPANSION_EEPROM_I2C_ADDRESS 0x50
-
-#define TINCANTOOLS_ZIPPY 0x01000100
-#define TINCANTOOLS_ZIPPY2 0x02000100
-#define TINCANTOOLS_TRAINER 0x04000100
-#define TINCANTOOLS_SHOWDOG 0x03000100
-#define KBADC_BEAGLEFPGA 0x01000600
-#define LW_BEAGLETOUCH 0x01000700
-#define BRAINMUX_LCDOG 0x01000800
-#define BRAINMUX_LCDOGTOUCH 0x02000800
-#define BBTOYS_WIFI 0x01000B00
-#define BBTOYS_VGA 0x02000B00
-#define BBTOYS_LCD 0x03000B00
-#define BCT_BRETTL3 0x01000F00
-#define BCT_BRETTL4 0x02000F00
-#define LSR_COM6L_ADPT 0x01001300
-#define BEAGLE_NO_EEPROM 0xffffffff
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct {
- unsigned int device_vendor;
- unsigned char revision;
- unsigned char content;
- char fab_revision[8];
- char env_var[16];
- char env_setting[64];
-} expansion_config;
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* board id for Linux */
- gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE;
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
- status_led_set (STATUS_LED_BOOT, STATUS_LED_ON);
-#endif
-
- return 0;
-}
-
-/*
- * Routine: get_board_revision
- * Description: Detect if we are running on a Beagle revision Ax/Bx,
- * C1/2/3, C4, xM Ax/Bx or xM Cx. This can be done by reading
- * the level of GPIO173, GPIO172 and GPIO171. This should
- * result in
- * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
- * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
- * GPIO173, GPIO172, GPIO171: 1 0 1 => C4
- * GPIO173, GPIO172, GPIO171: 0 1 0 => xM Cx
- * GPIO173, GPIO172, GPIO171: 0 0 0 => xM Ax/Bx
- */
-static int get_board_revision(void)
-{
- int revision;
-
- if (!gpio_request(171, "") &&
- !gpio_request(172, "") &&
- !gpio_request(173, "")) {
-
- gpio_direction_input(171);
- gpio_direction_input(172);
- gpio_direction_input(173);
-
- revision = gpio_get_value(173) << 2 |
- gpio_get_value(172) << 1 |
- gpio_get_value(171);
- } else {
- printf("Error: unable to acquire board revision GPIOs\n");
- revision = -1;
- }
-
- return revision;
-}
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * Routine: get_board_mem_timings
- * Description: If we use SPL then there is no x-loader nor config header
- * so we have to setup the DDR timings ourself on both banks.
- */
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
- int pop_mfr, pop_id;
-
- /*
- * We need to identify what PoP memory is on the board so that
- * we know what timings to use. If we can't identify it then
- * we know it's an xM. To map the ID values please see nand_ids.c
- */
- identify_nand_chip(&pop_mfr, &pop_id);
-
- timings->mr = MICRON_V_MR_165;
- switch (get_board_revision()) {
- case REVISION_C4:
- if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
- /* 512MB DDR */
- timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
- timings->ctrla = NUMONYX_V_ACTIMA_165;
- timings->ctrlb = NUMONYX_V_ACTIMB_165;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- break;
- } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) {
- /* Beagleboard Rev C4, 512MB Nand/256MB DDR*/
- timings->mcfg = MICRON_V_MCFG_165(128 << 20);
- timings->ctrla = MICRON_V_ACTIMA_165;
- timings->ctrlb = MICRON_V_ACTIMB_165;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- break;
- } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) {
- /* Beagleboard Rev C5, 256MB DDR */
- timings->mcfg = MICRON_V_MCFG_200(256 << 20);
- timings->ctrla = MICRON_V_ACTIMA_200;
- timings->ctrlb = MICRON_V_ACTIMB_200;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
- break;
- }
- case REVISION_XM_AB:
- case REVISION_XM_C:
- if (pop_mfr == 0) {
- /* 256MB DDR */
- timings->mcfg = MICRON_V_MCFG_200(256 << 20);
- timings->ctrla = MICRON_V_ACTIMA_200;
- timings->ctrlb = MICRON_V_ACTIMB_200;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
- } else {
- /* 512MB DDR */
- timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
- timings->ctrla = NUMONYX_V_ACTIMA_165;
- timings->ctrlb = NUMONYX_V_ACTIMB_165;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- }
- break;
- default:
- /* Assume 128MB and Micron/165MHz timings to be safe */
- timings->mcfg = MICRON_V_MCFG_165(128 << 20);
- timings->ctrla = MICRON_V_ACTIMA_165;
- timings->ctrlb = MICRON_V_ACTIMB_165;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- }
-}
-#endif
-
-/*
- * Routine: get_expansion_id
- * Description: This function checks for expansion board by checking I2C
- * bus 1 for the availability of an AT24C01B serial EEPROM.
- * returns the device_vendor field from the EEPROM
- */
-static unsigned int get_expansion_id(void)
-{
- i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
-
- /* return BEAGLE_NO_EEPROM if eeprom doesn't respond */
- if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) {
- i2c_set_bus_num(TWL4030_I2C_BUS);
- return BEAGLE_NO_EEPROM;
- }
-
- /* read configuration data */
- i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
- sizeof(expansion_config));
-
- /* retry reading configuration data with 16bit addressing */
- if ((expansion_config.device_vendor == 0xFFFFFF00) ||
- (expansion_config.device_vendor == 0xFFFFFFFF)) {
- printf("EEPROM is blank or 8bit addressing failed: retrying with 16bit:\n");
- i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 2, (u8 *)&expansion_config,
- sizeof(expansion_config));
- }
-
- i2c_set_bus_num(TWL4030_I2C_BUS);
-
- return expansion_config.device_vendor;
-}
-
-#ifdef CONFIG_VIDEO_OMAP3
-/*
- * Configure DSS to display background color on DVID
- * Configure VENC to display color bar on S-Video
- */
-static void beagle_display_init(void)
-{
- omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH);
- switch (get_board_revision()) {
- case REVISION_AXBX:
- case REVISION_CX:
- case REVISION_C4:
- omap3_dss_panel_config(&dvid_cfg);
- break;
- case REVISION_XM_AB:
- case REVISION_XM_C:
- default:
- omap3_dss_panel_config(&dvid_cfg_xm);
- break;
- }
-}
-
-/*
- * Enable DVI power
- */
-static void beagle_dvi_pup(void)
-{
- uchar val;
-
- switch (get_board_revision()) {
- case REVISION_AXBX:
- case REVISION_CX:
- case REVISION_C4:
- gpio_request(170, "");
- gpio_direction_output(170, 0);
- gpio_set_value(170, 1);
- break;
- case REVISION_XM_AB:
- case REVISION_XM_C:
- default:
- #define GPIODATADIR1 (TWL4030_BASEADD_GPIO+3)
- #define GPIODATAOUT1 (TWL4030_BASEADD_GPIO+6)
-
- i2c_read(TWL4030_CHIP_GPIO, GPIODATADIR1, 1, &val, 1);
- val |= 4;
- i2c_write(TWL4030_CHIP_GPIO, GPIODATADIR1, 1, &val, 1);
-
- i2c_read(TWL4030_CHIP_GPIO, GPIODATAOUT1, 1, &val, 1);
- val |= 4;
- i2c_write(TWL4030_CHIP_GPIO, GPIODATAOUT1, 1, &val, 1);
- break;
- }
-}
-#endif
-
-#ifdef CONFIG_USB_MUSB_OMAP2PLUS
-static struct musb_hdrc_config musb_config = {
- .multipoint = 1,
- .dyn_fifo = 1,
- .num_eps = 16,
- .ram_bits = 12,
-};
-
-static struct omap_musb_board_data musb_board_data = {
- .interface_type = MUSB_INTERFACE_ULPI,
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_MUSB_HOST)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_MUSB_GADGET)
- .mode = MUSB_PERIPHERAL,
-#else
-#error "Please define either CONFIG_MUSB_HOST or CONFIG_MUSB_GADGET"
-#endif
- .config = &musb_config,
- .power = 100,
- .platform_ops = &omap2430_ops,
- .board_data = &musb_board_data,
-};
-#endif
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
- struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
- struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
- struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE;
- bool generate_fake_mac = false;
-
- /* Enable i2c2 pullup resisters */
- writel(~(PRG_I2C2_PULLUPRESX), &prog_io_base->io1);
-
- switch (get_board_revision()) {
- case REVISION_AXBX:
- printf("Beagle Rev Ax/Bx\n");
- setenv("beaglerev", "AxBx");
- break;
- case REVISION_CX:
- printf("Beagle Rev C1/C2/C3\n");
- setenv("beaglerev", "Cx");
- MUX_BEAGLE_C();
- break;
- case REVISION_C4:
- printf("Beagle Rev C4\n");
- setenv("beaglerev", "C4");
- MUX_BEAGLE_C();
- /* Set VAUX2 to 1.8V for EHCI PHY */
- twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
- TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
- TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
- TWL4030_PM_RECEIVER_DEV_GRP_P1);
- break;
- case REVISION_XM_AB:
- printf("Beagle xM Rev A/B\n");
- setenv("beaglerev", "xMAB");
- MUX_BEAGLE_XM();
- /* Set VAUX2 to 1.8V for EHCI PHY */
- twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
- TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
- TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
- TWL4030_PM_RECEIVER_DEV_GRP_P1);
- generate_fake_mac = true;
- break;
- case REVISION_XM_C:
- printf("Beagle xM Rev C\n");
- setenv("beaglerev", "xMC");
- MUX_BEAGLE_XM();
- /* Set VAUX2 to 1.8V for EHCI PHY */
- twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
- TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
- TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
- TWL4030_PM_RECEIVER_DEV_GRP_P1);
- generate_fake_mac = true;
- break;
- default:
- printf("Beagle unknown 0x%02x\n", get_board_revision());
- MUX_BEAGLE_XM();
- /* Set VAUX2 to 1.8V for EHCI PHY */
- twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
- TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
- TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
- TWL4030_PM_RECEIVER_DEV_GRP_P1);
- generate_fake_mac = true;
- }
-
- switch (get_expansion_id()) {
- case TINCANTOOLS_ZIPPY:
- printf("Recognized Tincantools Zippy board (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- MUX_TINCANTOOLS_ZIPPY();
- setenv("buddy", "zippy");
- break;
- case TINCANTOOLS_ZIPPY2:
- printf("Recognized Tincantools Zippy2 board (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- MUX_TINCANTOOLS_ZIPPY();
- setenv("buddy", "zippy2");
- break;
- case TINCANTOOLS_TRAINER:
- printf("Recognized Tincantools Trainer board (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- MUX_TINCANTOOLS_ZIPPY();
- MUX_TINCANTOOLS_TRAINER();
- setenv("buddy", "trainer");
- break;
- case TINCANTOOLS_SHOWDOG:
- printf("Recognized Tincantools Showdow board (rev %d %s)\n",
- expansion_config.revision,
- expansion_config.fab_revision);
- /* Place holder for DSS2 definition for showdog lcd */
- setenv("defaultdisplay", "showdoglcd");
- setenv("buddy", "showdog");
- break;
- case KBADC_BEAGLEFPGA:
- printf("Recognized KBADC Beagle FPGA board\n");
- MUX_KBADC_BEAGLEFPGA();
- setenv("buddy", "beaglefpga");
- break;
- case LW_BEAGLETOUCH:
- printf("Recognized Liquidware BeagleTouch board\n");
- setenv("buddy", "beagletouch");
- break;
- case BRAINMUX_LCDOG:
- printf("Recognized Brainmux LCDog board\n");
- setenv("buddy", "lcdog");
- break;
- case BRAINMUX_LCDOGTOUCH:
- printf("Recognized Brainmux LCDog Touch board\n");
- setenv("buddy", "lcdogtouch");
- break;
- case BBTOYS_WIFI:
- printf("Recognized BeagleBoardToys WiFi board\n");
- MUX_BBTOYS_WIFI()
- setenv("buddy", "bbtoys-wifi");
- break;;
- case BBTOYS_VGA:
- printf("Recognized BeagleBoardToys VGA board\n");
- break;;
- case BBTOYS_LCD:
- printf("Recognized BeagleBoardToys LCD board\n");
- break;;
- case BCT_BRETTL3:
- printf("Recognized bct electronic GmbH brettl3 board\n");
- break;
- case BCT_BRETTL4:
- printf("Recognized bct electronic GmbH brettl4 board\n");
- break;
- case LSR_COM6L_ADPT:
- printf("Recognized LSR COM6L Adapter Board\n");
- MUX_BBTOYS_WIFI()
- setenv("buddy", "lsr-com6l-adpt");
- break;
- case BEAGLE_NO_EEPROM:
- printf("No EEPROM on expansion board\n");
- setenv("buddy", "none");
- break;
- default:
- printf("Unrecognized expansion board: %x\n",
- expansion_config.device_vendor);
- setenv("buddy", "unknown");
- }
-
- if (expansion_config.content == 1)
- setenv(expansion_config.env_var, expansion_config.env_setting);
-
- twl4030_power_init();
- switch (get_board_revision()) {
- case REVISION_XM_AB:
- twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
- break;
- default:
- twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
- break;
- }
-
- /* Set GPIO states before they are made outputs */
- writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1,
- &gpio6_base->setdataout);
- writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
- GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
-
- /* Configure GPIOs to output */
- writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
- writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
- GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
-
- dieid_num_r();
-
-#ifdef CONFIG_VIDEO_OMAP3
- beagle_dvi_pup();
- beagle_display_init();
- omap3_dss_enable();
-#endif
-
-#ifdef CONFIG_USB_MUSB_OMAP2PLUS
- musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
-#endif
-
- if (generate_fake_mac) {
- u32 id[4];
-
- get_dieid(id);
- usb_fake_mac_from_die_id(id);
- }
-
- return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_BEAGLE();
-}
-
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
-/* Call usb_stop() before starting the kernel */
-void show_boot_progress(int val)
-{
- if (val == BOOTSTAGE_ID_RUN_OS)
- usb_stop();
-}
-
-static struct omap_usbhs_board_data usbhs_bdata = {
- .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
-}
-
-int ehci_hcd_stop(int index)
-{
- return omap_ehci_hcd_stop();
-}
-
-#endif /* CONFIG_USB_EHCI */
-
-#if defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)
-int board_eth_init(bd_t *bis)
-{
- return usb_eth_initialize(bis);
-}
-#endif
diff --git a/qemu/roms/u-boot/board/ti/beagle/beagle.h b/qemu/roms/u-boot/board/ti/beagle/beagle.h
deleted file mode 100644
index 6dd2ffe55..000000000
--- a/qemu/roms/u-boot/board/ti/beagle/beagle.h
+++ /dev/null
@@ -1,546 +0,0 @@
-/*
- * (C) Copyright 2008
- * Dirk Behme <dirk.behme@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _BEAGLE_H_
-#define _BEAGLE_H_
-
-#include <asm/arch/dss.h>
-
-const omap3_sysinfo sysinfo = {
- DDR_STACKED,
- "OMAP3 Beagle board",
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
- "OneNAND",
-#else
- "NAND",
-#endif
-};
-
-/* BeagleBoard revisions */
-#define REVISION_AXBX 0x7
-#define REVISION_CX 0x6
-#define REVISION_C4 0x5
-#define REVISION_XM_AB 0x0
-#define REVISION_XM_C 0x2
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_BEAGLE() \
- /*SDRC*/\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
- /*GPMC*/\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
- MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
- MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
- MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
- MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
- MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
- MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
- MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
- MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
- MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
- MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
- MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
- MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
- MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
- MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
- MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
- MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
- MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
- /*DSS*/\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
- MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
- MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
- MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
- /*CAMERA*/\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
- MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
- MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
- MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
- MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
- MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
- MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
- MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
- MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
- MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
- MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
- MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
- MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
- MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
- MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
- MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
- MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
- /*Audio Interface */\
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
- MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
- /*Expansion card */\
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
- /*Wireless LAN */\
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
- MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
- MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
- MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
- /*Bluetooth*/\
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
- MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
- MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
- MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144*/\
- MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
- MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
- /*Modem Interface */\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
- MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
- MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
- MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
- MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
- MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
- MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
- MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
- MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
- MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
- MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
- /*Serial Interface*/\
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
- MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTU | EN | M4)) /*GPIO_173*/\
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
- MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
- MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
- /* USB EHCI (port 2) */\
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)) /*HSUSB2_DATA2*/\
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)) /*HSUSB2_DATA7*/\
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)) /*HSUSB2_DATA4*/\
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)) /*HSUSB2_DATA5*/\
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)) /*HSUSB2_DATA6*/\
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)) /*HSUSB2_DATA3*/\
- MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
- MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DIR*/\
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_NXT*/\
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DATA0*/\
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DATA1*/\
- /*Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
- MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
- MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
- MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
- MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
- MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
- MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
- MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
- MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
- MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
- MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
- MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
- MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
- MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
- MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
- MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
- MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
- MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
- MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
- MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
- MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
- MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
- MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
- MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
- MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
- MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
- MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
- MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
- MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
- MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
- MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
- MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
- MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
- MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
- MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
- MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
-
-#define MUX_BEAGLE_C() \
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
- MUX_VAL(CP(UART2_RX), (IDIS | PTU | EN | M4)) /*GPIO_147*/
-
-#define MUX_BEAGLE_XM() \
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | EN | M4)) /*GPIO_56*/\
- MUX_VAL(CP(GPMC_WAIT0), (IDIS | PTU | EN | M4)) /*GPIO_63*/\
- MUX_VAL(CP(MMC1_DAT7), (IDIS | PTU | EN | M4)) /*GPIO_129*/\
- MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
- MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
- MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
- MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
- MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
- MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
- MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/
-
-#define MUX_TINCANTOOLS_ZIPPY() \
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
- MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
- MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
- MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | EN | M1)) /*MCSPI4_CLK*/\
- MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\
- MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | EN | M1)) /*MCSPI4_SIMO*/\
- MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)) /*MCSPI4_SOMI*/\
- MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M1)) /*MCSPI4_CS0*/\
- MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_162*/\
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/
-
-#define MUX_TINCANTOOLS_TRAINER() \
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
- MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
- MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
- MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) /*GPIO_140*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) /*GPIO_141*/\
- MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | EN | M4)) /*GPIO_162*/
-
-#define MUX_KBADC_BEAGLEFPGA() \
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | DIS | M1)) /*MCSPI4_CLK*/\
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTU | DIS | M1)) /*MCSPI4_SIMO*/\
- MUX_VAL(CP(MCBSP1_DR), (IEN | PTU | EN | M1)) /*MCSPI4_SOMI*/\
- MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTU | DIS | M1)) /*MCSPI4_CS0*/
-
-#define MUX_BBTOYS_WIFI() \
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
- MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) /*GPIO_136 FM_EN/BT_WU*/\
- MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137 WLAN_IRQ*/\
- MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) /*GPIO_138 BT_EN*/\
- MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) /*GPIO_139 WLAN_EN*/
-
-/*
- * Display Configuration
- */
-
-#define DVI_BEAGLE_ORANGE_COL 0x00FF8000
-#define VENC_HEIGHT 0x00ef
-#define VENC_WIDTH 0x027f
-
-/*
- * Configure VENC in DSS for Beagle to generate Color Bar
- *
- * Kindly refer to OMAP TRM for definition of these values.
- */
-static const struct venc_regs venc_config_std_tv = {
- .status = 0x0000001B,
- .f_control = 0x00000040,
- .vidout_ctrl = 0x00000000,
- .sync_ctrl = 0x00008000,
- .llen = 0x00008359,
- .flens = 0x0000020C,
- .hfltr_ctrl = 0x00000000,
- .cc_carr_wss_carr = 0x043F2631,
- .c_phase = 0x00000024,
- .gain_u = 0x00000130,
- .gain_v = 0x00000198,
- .gain_y = 0x000001C0,
- .black_level = 0x0000006A,
- .blank_level = 0x0000005C,
- .x_color = 0x00000000,
- .m_control = 0x00000001,
- .bstamp_wss_data = 0x0000003F,
- .s_carr = 0x21F07C1F,
- .line21 = 0x00000000,
- .ln_sel = 0x00000015,
- .l21__wc_ctl = 0x00001400,
- .htrigger_vtrigger = 0x00000000,
- .savid__eavid = 0x069300F4,
- .flen__fal = 0x0016020C,
- .lal__phase_reset = 0x00060107,
- .hs_int_start_stop_x = 0x008D034E,
- .hs_ext_start_stop_x = 0x000F0359,
- .vs_int_start_x = 0x01A00000,
- .vs_int_stop_x__vs_int_start_y = 0x020501A0,
- .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
- .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
- .vs_ext_stop_y = 0x00000006,
- .avid_start_stop_x = 0x03480079,
- .avid_start_stop_y = 0x02040024,
- .fid_int_start_x__fid_int_start_y = 0x0001008A,
- .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
- .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
- .tvdetgp_int_start_stop_x = 0x00140001,
- .tvdetgp_int_start_stop_y = 0x00010001,
- .gen_ctrl = 0x00FF0000,
- .output_control = 0x0000000D,
- .dac_b__dac_c = 0x00000000
-};
-
-/*
- * Configure Timings for DVI D
- */
-static const struct panel_config dvid_cfg = {
- .timing_h = 0x0ff03f31, /* Horizontal timing */
- .timing_v = 0x01400504, /* Vertical timing */
- .pol_freq = 0x00007028, /* Pol Freq */
- .divisor = 0x00010006, /* 72Mhz Pixel Clock */
- .lcd_size = 0x02ff03ff, /* 1024x768 */
- .panel_type = 0x01, /* TFT */
- .data_lines = 0x03, /* 24 Bit RGB */
- .load_mode = 0x02, /* Frame Mode */
- .panel_color = DVI_BEAGLE_ORANGE_COL, /* ORANGE */
- .gfx_format = GFXFORMAT_RGB24_UNPACKED,
-};
-
-static const struct panel_config dvid_cfg_xm = {
- .timing_h = 0x1a4024c9, /* Horizontal timing */
- .timing_v = 0x02c00509, /* Vertical timing */
- .pol_freq = 0x00007028, /* Pol Freq */
- .divisor = 0x00010001, /* 96MHz Pixel Clock */
- .lcd_size = 0x02ff03ff, /* 1024x768 */
- .panel_type = 0x01, /* TFT */
- .data_lines = 0x03, /* 24 Bit RGB */
- .load_mode = 0x02, /* Frame Mode */
- .panel_color = DVI_BEAGLE_ORANGE_COL, /* ORANGE */
- .gfx_format = GFXFORMAT_RGB24_UNPACKED,
-};
-#endif
diff --git a/qemu/roms/u-boot/board/ti/beagle/led.c b/qemu/roms/u-boot/board/ti/beagle/led.c
deleted file mode 100644
index 89b8dd3c3..000000000
--- a/qemu/roms/u-boot/board/ti/beagle/led.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright (c) 2010 Texas Instruments, Inc.
- * Jason Kridner <jkridner@beagleboard.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <status_led.h>
-#include <asm/arch/cpu.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-
-/* GPIO pins for the LEDs */
-#define BEAGLE_LED_USR0 150
-#define BEAGLE_LED_USR1 149
-
-#ifdef STATUS_LED_GREEN
-void green_led_off(void)
-{
- __led_set (STATUS_LED_GREEN, 0);
-}
-
-void green_led_on(void)
-{
- __led_set (STATUS_LED_GREEN, 1);
-}
-#endif
-
-void __led_init (led_id_t mask, int state)
-{
- __led_set (mask, state);
-}
-
-void __led_toggle (led_id_t mask)
-{
- int state, toggle_gpio = 0;
-#ifdef STATUS_LED_BIT
- if (!toggle_gpio && STATUS_LED_BIT & mask)
- toggle_gpio = BEAGLE_LED_USR0;
-#endif
-#ifdef STATUS_LED_BIT1
- if (!toggle_gpio && STATUS_LED_BIT1 & mask)
- toggle_gpio = BEAGLE_LED_USR1;
-#endif
- if (toggle_gpio) {
- if (!gpio_request(toggle_gpio, "")) {
- gpio_direction_output(toggle_gpio, 0);
- state = gpio_get_value(toggle_gpio);
- gpio_set_value(toggle_gpio, !state);
- }
- }
-}
-
-void __led_set (led_id_t mask, int state)
-{
-#ifdef STATUS_LED_BIT
- if (STATUS_LED_BIT & mask) {
- if (!gpio_request(BEAGLE_LED_USR0, "")) {
- gpio_direction_output(BEAGLE_LED_USR0, 0);
- gpio_set_value(BEAGLE_LED_USR0, state);
- }
- }
-#endif
-#ifdef STATUS_LED_BIT1
- if (STATUS_LED_BIT1 & mask) {
- if (!gpio_request(BEAGLE_LED_USR1, "")) {
- gpio_direction_output(BEAGLE_LED_USR1, 0);
- gpio_set_value(BEAGLE_LED_USR1, state);
- }
- }
-#endif
-}
diff --git a/qemu/roms/u-boot/board/ti/dra7xx/Makefile b/qemu/roms/u-boot/board/ti/dra7xx/Makefile
deleted file mode 100644
index 434e8d128..000000000
--- a/qemu/roms/u-boot/board/ti/dra7xx/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2013
-# Texas Instruments, <www.ti.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := evm.o
diff --git a/qemu/roms/u-boot/board/ti/dra7xx/README b/qemu/roms/u-boot/board/ti/dra7xx/README
deleted file mode 100644
index 533da01a3..000000000
--- a/qemu/roms/u-boot/board/ti/dra7xx/README
+++ /dev/null
@@ -1,26 +0,0 @@
-Summary
-=======
-
-This document covers various features of the 'dra7xx_evm' build and some
-related uses.
-
-eMMC boot partition use
-=======================
-
-It is possible, depending on SYSBOOT configuration to boot from the eMMC
-boot partitions using (name depending on documentation referenced)
-Alternative Boot operation mode or Boot Sequence Option 1/2. In this
-example we load MLO and u-boot.img from the build into DDR and then use
-'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to
-set boot0 as the boot device.
-U-Boot # setenv autoload no
-U-Boot # usb start
-U-Boot # dhcp
-U-Boot # mmc dev 1 1
-U-Boot # tftp ${loadaddr} dra7xx/MLO
-U-Boot # mmc write ${loadaddr} 0 100
-U-Boot # tftp ${loadaddr} dra7xx/u-boot.img
-U-Boot # mmc write ${loadaddr} 300 400
-U-Boot # mmc bootbus 1 2 0 2
-U-Boot # mmc partconf 1 1 1 0
-U-Boot # mmc rst-function 1 1
diff --git a/qemu/roms/u-boot/board/ti/dra7xx/evm.c b/qemu/roms/u-boot/board/ti/dra7xx/evm.c
deleted file mode 100644
index 073d15127..000000000
--- a/qemu/roms/u-boot/board/ti/dra7xx/evm.c
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * (C) Copyright 2013
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * Lokesh Vutla <lokeshvutla@ti.com>
- *
- * Based on previous work by:
- * Aneesh V <aneesh@ti.com>
- * Steve Sakoman <steve@sakoman.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <palmas.h>
-#include <sata.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sata.h>
-#include <environment.h>
-
-#include "mux_data.h"
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-#include <cpsw.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const struct omap_sysinfo sysinfo = {
- "Board: DRA7xx\n"
-};
-
-/*
- * Adjust I/O delays on the Tx control and data lines of each MAC port. This
- * is a workaround in order to work properly with the DP83865 PHYs on the EVM.
- * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we
- * essentially need to counteract the DRA7xx internal delay, and we do this
- * by delaying the control and data lines. If not using this PHY, you probably
- * don't need to do this stuff!
- */
-static void dra7xx_adj_io_delay(const struct io_delay *io_dly)
-{
- int i = 0;
- u32 reg_val;
- u32 delta;
- u32 coarse;
- u32 fine;
-
- writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK);
-
- while(io_dly[i].addr) {
- writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK,
- io_dly[i].addr);
- delta = io_dly[i].dly;
- reg_val = readl(io_dly[i].addr) & 0x3ff;
- coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
- coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
- fine = (reg_val & 0x1F) + (delta & 0x1F);
- fine = (fine > 0x1F) ? (0x1F) : (fine);
- reg_val = CFG_IO_DELAY_ACCESS_PATTERN |
- CFG_IO_DELAY_LOCK_MASK |
- ((coarse << 5) | (fine));
- writel(reg_val, io_dly[i].addr);
- i++;
- }
-
- writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK);
-}
-
-/**
- * @brief board_init
- *
- * @return 0
- */
-int board_init(void)
-{
- gpmc_init();
- gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
-
- return 0;
-}
-
-int board_late_init(void)
-{
- init_sata(0);
- return 0;
-}
-
-/**
- * @brief misc_init_r - Configure EVM board specific configurations
- * such as power configurations, ethernet initialization as phase2 of
- * boot sequence
- *
- * @return 0
- */
-int misc_init_r(void)
-{
- return 0;
-}
-
-static void do_set_mux32(u32 base,
- struct pad_conf_entry const *array, int size)
-{
- int i;
- struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
-
- for (i = 0; i < size; i++, pad++)
- writel(pad->val, base + pad->offset);
-}
-
-void set_muxconf_regs_essential(void)
-{
- do_set_mux32((*ctrl)->control_padconf_core_base,
- core_padconf_array_essential,
- sizeof(core_padconf_array_essential) /
- sizeof(struct pad_conf_entry));
-}
-
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
-int board_mmc_init(bd_t *bis)
-{
- omap_mmc_init(0, 0, 0, -1, -1);
- omap_mmc_init(1, 0, 0, -1, -1);
- return 0;
-}
-#endif
-
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
-int spl_start_uboot(void)
-{
- /* break into full u-boot on 'c' */
- if (serial_tstc() && serial_getc() == 'c')
- return 1;
-
-#ifdef CONFIG_SPL_ENV_SUPPORT
- env_init();
- env_relocate_spec();
- if (getenv_yesno("boot_os") != 1)
- return 1;
-#endif
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-
-/* Delay value to add to calibrated value */
-#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
-#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
-#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
-#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
-#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
-#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
-#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
-#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
-#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
-#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
-
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
-
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 2,
- },
- {
- .slave_reg_ofs = 0x308,
- .sliver_reg_ofs = 0xdc0,
- .phy_addr = 3,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 1,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-
-int board_eth_init(bd_t *bis)
-{
- int ret;
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
- uint32_t ctrl_val;
- const struct io_delay io_dly[] = {
- {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL},
- {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL},
- {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL},
- {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL},
- {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL},
- {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL},
- {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL},
- {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL},
- {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL},
- {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL},
- {0}
- };
-
- /* Adjust IO delay for RGMII tx path */
- dra7xx_adj_io_delay(io_dly);
-
- /* try reading mac address from efuse */
- mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
- mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
- mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = mac_hi & 0xFF;
- mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
- mac_addr[4] = (mac_lo & 0xFF00) >> 8;
- mac_addr[5] = mac_lo & 0xFF;
-
- if (!getenv("ethaddr")) {
- printf("<ethaddr> not set. Validating first E-fuse MAC\n");
-
- if (is_valid_ether_addr(mac_addr))
- eth_setenv_enetaddr("ethaddr", mac_addr);
- }
-
- mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
- mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
- mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = mac_hi & 0xFF;
- mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
- mac_addr[4] = (mac_lo & 0xFF00) >> 8;
- mac_addr[5] = mac_lo & 0xFF;
-
- if (!getenv("eth1addr")) {
- if (is_valid_ether_addr(mac_addr))
- eth_setenv_enetaddr("eth1addr", mac_addr);
- }
-
- ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
- ctrl_val |= 0x22;
- writel(ctrl_val, (*ctrl)->control_core_control_io1);
-
- ret = cpsw_register(&cpsw_data);
- if (ret < 0)
- printf("Error %d registering CPSW switch\n", ret);
-
- return ret;
-}
-#endif
diff --git a/qemu/roms/u-boot/board/ti/dra7xx/mux_data.h b/qemu/roms/u-boot/board/ti/dra7xx/mux_data.h
deleted file mode 100644
index 38de9d5a8..000000000
--- a/qemu/roms/u-boot/board/ti/dra7xx/mux_data.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * (C) Copyright 2013
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * Sricharan R <r.sricharan@ti.com>
- * Nishant Kamat <nskamat@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _MUX_DATA_DRA7XX_H_
-#define _MUX_DATA_DRA7XX_H_
-
-#include <asm/arch/mux_dra7xx.h>
-
-const struct pad_conf_entry core_padconf_array_essential[] = {
- {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */
- {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */
- {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */
- {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */
- {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */
- {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
- {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
- {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
- {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */
- {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */
- {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */
- {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */
- {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */
- {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */
- {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */
- {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
- {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
- {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
- {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */
- {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */
- {UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */
- {UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */
- {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */
- {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
- {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
- {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */
- {RGMII0_TXC, (M0) },
- {RGMII0_TXCTL, (M0) },
- {RGMII0_TXD3, (M0) },
- {RGMII0_TXD2, (M0) },
- {RGMII0_TXD1, (M0) },
- {RGMII0_TXD0, (M0) },
- {RGMII0_RXC, (IEN | M0) },
- {RGMII0_RXCTL, (IEN | M0) },
- {RGMII0_RXD3, (IEN | M0) },
- {RGMII0_RXD2, (IEN | M0) },
- {RGMII0_RXD1, (IEN | M0) },
- {RGMII0_RXD0, (IEN | M0) },
- {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
- {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
- {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
- {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
- {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
- {GPMC_A18, (M1)}, /* QSPI1_SCLK */
- {GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */
- {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
- {GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */
- {GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/
- {USB2_DRVVBUS, (M0 | IEN | FSC) },
-};
-#endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/qemu/roms/u-boot/board/ti/evm/Makefile b/qemu/roms/u-boot/board/ti/evm/Makefile
deleted file mode 100644
index b88ab8f51..000000000
--- a/qemu/roms/u-boot/board/ti/evm/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := evm.o
diff --git a/qemu/roms/u-boot/board/ti/evm/evm.c b/qemu/roms/u-boot/board/ti/evm/evm.c
deleted file mode 100644
index 81dd081d7..000000000
--- a/qemu/roms/u-boot/board/ti/evm/evm.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/*
- * (C) Copyright 2004-2011
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Manikandan Pillai <mani.pillai@ti.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/gpio.h>
-#include <i2c.h>
-#include <asm/mach-types.h>
-#include <linux/mtd/nand.h>
-#include "evm.h"
-
-#define OMAP3EVM_GPIO_ETH_RST_GEN1 64
-#define OMAP3EVM_GPIO_ETH_RST_GEN2 7
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static u32 omap3_evm_version;
-
-u32 get_omap3_evm_rev(void)
-{
- return omap3_evm_version;
-}
-
-static void omap3_evm_get_revision(void)
-{
-#if defined(CONFIG_CMD_NET)
- /*
- * Board revision can be ascertained only by identifying
- * the Ethernet chipset.
- */
- unsigned int smsc_id;
-
- /* Ethernet PHY ID is stored at ID_REV register */
- smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
- printf("Read back SMSC id 0x%x\n", smsc_id);
-
- switch (smsc_id) {
- /* SMSC9115 chipset */
- case 0x01150000:
- omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
- break;
- /* SMSC 9220 chipset */
- case 0x92200000:
- default:
- omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
- }
-#else
-#if defined(CONFIG_STATIC_BOARD_REV)
- /*
- * Look for static defintion of the board revision
- */
- omap3_evm_version = CONFIG_STATIC_BOARD_REV;
-#else
- /*
- * Fallback to the default above.
- */
- omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
-#endif
-#endif /* CONFIG_CMD_NET */
-}
-
-#ifdef CONFIG_USB_OMAP3
-/*
- * MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
- */
-u8 omap3_evm_need_extvbus(void)
-{
- u8 retval = 0;
-
- if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
- retval = 1;
-
- return retval;
-}
-#endif
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* board id for Linux */
- gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * Routine: get_board_mem_timings
- * Description: If we use SPL then there is no x-loader nor config header
- * so we have to setup the DDR timings ourself on the first bank. This
- * provides the timing values back to the function that configures
- * the memory.
- */
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
- int pop_mfr, pop_id;
-
- /*
- * We need to identify what PoP memory is on the board so that
- * we know what timings to use. To map the ID values please see
- * nand_ids.c
- */
- identify_nand_chip(&pop_mfr, &pop_id);
-
- if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
- /* 256MB DDR */
- timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
- timings->ctrla = HYNIX_V_ACTIMA_200;
- timings->ctrlb = HYNIX_V_ACTIMB_200;
- } else {
- /* 128MB DDR */
- timings->mcfg = MICRON_V_MCFG_165(128 << 20);
- timings->ctrla = MICRON_V_ACTIMA_165;
- timings->ctrlb = MICRON_V_ACTIMB_165;
- }
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- timings->mr = MICRON_V_MR_165;
-}
-#endif
-
-/*
- * Routine: misc_init_r
- * Description: Init ethernet (done here so udelay works)
- */
-int misc_init_r(void)
-{
-
-#ifdef CONFIG_SYS_I2C_OMAP34XX
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-#endif
-
-#if defined(CONFIG_CMD_NET)
- setup_net_chip();
-#endif
- omap3_evm_get_revision();
-
-#if defined(CONFIG_CMD_NET)
- reset_net_chip();
-#endif
- dieid_num_r();
-
- return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_EVM();
-}
-
-#ifdef CONFIG_CMD_NET
-/*
- * Routine: setup_net_chip
- * Description: Setting up the configuration GPMC registers specific to the
- * Ethernet hardware.
- */
-static void setup_net_chip(void)
-{
- struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
-
- /* Configure GPMC registers */
- writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
- writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
- writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
- writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
- writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
- writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
- writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
-
- /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
- writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
- /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
- /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
- &ctrl_base->gpmc_nadv_ale);
-}
-
-/**
- * Reset the ethernet chip.
- */
-static void reset_net_chip(void)
-{
- int ret;
- int rst_gpio;
-
- if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) {
- rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1;
- } else {
- rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2;
- }
-
- ret = gpio_request(rst_gpio, "");
- if (ret < 0) {
- printf("Unable to get GPIO %d\n", rst_gpio);
- return ;
- }
-
- /* Configure as output */
- gpio_direction_output(rst_gpio, 0);
-
- /* Send a pulse on the GPIO pin */
- gpio_set_value(rst_gpio, 1);
- udelay(1);
- gpio_set_value(rst_gpio, 0);
- udelay(1);
- gpio_set_value(rst_gpio, 1);
-}
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC911X
-#define STR_ENV_ETHADDR "ethaddr"
-
- struct eth_device *dev;
- uchar eth_addr[6];
-
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-
- if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
- dev = eth_get_dev_by_index(0);
- if (dev) {
- eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
- } else {
- printf("omap3evm: Couldn't get eth device\n");
- rc = -1;
- }
- }
-#endif
- return rc;
-}
-#endif /* CONFIG_CMD_NET */
-
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
diff --git a/qemu/roms/u-boot/board/ti/evm/evm.h b/qemu/roms/u-boot/board/ti/evm/evm.h
deleted file mode 100644
index f50193d99..000000000
--- a/qemu/roms/u-boot/board/ti/evm/evm.h
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- * (C) Copyright 2008
- * Nishanth Menon <menon.nishanth@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _EVM_H_
-#define _EVM_H_
-
-const omap3_sysinfo sysinfo = {
- DDR_DISCRETE,
- "OMAP3 EVM board",
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
- "OneNAND",
-#else
- "NAND",
-#endif
-};
-
-/*
- * OMAP35x EVM revision
- * Run time detection of EVM revision is done by reading Ethernet
- * PHY ID -
- * GEN_1 = 0x01150000
- * GEN_2 = 0x92200000
- */
-enum {
- OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */
- OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */
-};
-
-u32 get_omap3_evm_rev(void);
-
-#if defined(CONFIG_CMD_NET)
-static void setup_net_chip(void);
-static void reset_net_chip(void);
-#endif
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_EVM() \
- /*SDRC*/\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
- /*GPMC*/\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\
- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
- MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) /*GPMC_nCS4*/\
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) /*GPMC_nBE0_CLE*/\
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) /*GPMC_nBE1*/\
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
- /* - ETH_nRESET*/\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
- /*DSS*/\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
- MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
- MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
- MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
- /*CAMERA*/\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
- MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
- MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
- /* - CAM_RESET*/\
- MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
- MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
- MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
- MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
- MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
- MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
- MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
- MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
- MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
- MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
- MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
- MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
- MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
- MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
- /*Audio Interface */\
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
- MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
- /*Expansion card */\
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
- /*Wireless LAN */\
- MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) /*MMC2_CLK*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
- MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M0)) /*MMC2_DAT4*/\
- MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M0)) /*MMC2_DAT5*/\
- MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M0)) /*MMC2_DAT6 */\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)) /*MMC2_DAT7*/\
- /*Bluetooth*/\
- MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) /*McBSP3_DR*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /*McBSP3_CLKX */\
- MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /*McBSP3_FSX*/\
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /*UART2_RX*/\
- /*Modem Interface */\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
- MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
- /* - LCD_INI*/\
- MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
- /* - LCD_ENVDD */\
- MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
- /* - LCD_QVGA/nVGA */\
- MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\
- /* - LCD_RESB */\
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /*MCBSP1_CLKR */\
- MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) /*MCBSP1_FSR*/\
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) /*MCBSP1_DX*/\
- MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /*MCBSP1_DR*/\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*MCBSP_CLKS */\
- MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) /*MCBSP1_FSX*/\
- MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) /*MCBSP1_CLKX */\
- /*Serial Interface*/\
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_*/\
- /* RCTX*/\
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
- MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) /*HDQ_SIO*/\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
- MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
- /* TS_PEN_IRQ */\
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\
- /* - LAN_INTR*/\
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) /*McSPI1_CS3*/\
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\
- /*Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
- /* - PEN_IRQ */\
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
- MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
- /* - VIO_1V8*/\
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
- MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) /*SYS_CLKOUT2*/\
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
- MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
- MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
- MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) /*ETK_CLK*/\
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) /*ETK_CTL*/\
- MUX_VAL(CP(ETK_D0_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D0*/\
- MUX_VAL(CP(ETK_D1_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D1*/\
- MUX_VAL(CP(ETK_D2_ES2 ), (IEN | PTD | EN | M0)) /*ETK_D2*/\
- MUX_VAL(CP(ETK_D3_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D3*/\
- MUX_VAL(CP(ETK_D4_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D4*/\
- MUX_VAL(CP(ETK_D5_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D5*/\
- MUX_VAL(CP(ETK_D6_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D6*/\
- MUX_VAL(CP(ETK_D7_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D7*/\
- MUX_VAL(CP(ETK_D8_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D8*/\
- MUX_VAL(CP(ETK_D9_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D9*/\
- MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) /*ETK_D10*/\
- MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) /*ETK_D11*/\
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) /*ETK_D12*/\
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) /*ETK_D13*/\
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) /*ETK_D14*/\
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) /*ETK_D15*/\
- /*Die to Die */\
- MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
- MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
- MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
- MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
- MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
- MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
- MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
- MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
- MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
- MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
- MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
- MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
- MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
- MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
- MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
- MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
- MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
- MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
- MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
- MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
- MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
- MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
- MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
- MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
- MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
- MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
- MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
- MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
- MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
- MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
- MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
- MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
- MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/\
-
-#endif
diff --git a/qemu/roms/u-boot/board/ti/k2hk_evm/Makefile b/qemu/roms/u-boot/board/ti/k2hk_evm/Makefile
deleted file mode 100644
index 3645f2feb..000000000
--- a/qemu/roms/u-boot/board/ti/k2hk_evm/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# K2HK-EVM: board Makefile
-# (C) Copyright 2012-2014
-# Texas Instruments Incorporated, <www.ti.com>
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += board.o
-obj-y += ddr3.o
diff --git a/qemu/roms/u-boot/board/ti/k2hk_evm/README b/qemu/roms/u-boot/board/ti/k2hk_evm/README
deleted file mode 100644
index bfeb05b4a..000000000
--- a/qemu/roms/u-boot/board/ti/k2hk_evm/README
+++ /dev/null
@@ -1,122 +0,0 @@
-U-Boot port for Texas Instruments XTCIEVMK2X
-============================================
-
-Author: Murali Karicheri <m-karicheri2@ti.com>
-
-This README has information on the u-boot port for XTCIEVMK2X EVM board.
-Documentation for this board can be found at
- http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx
-
-The board is based on Texas Instruments Keystone2 family of SoCs : K2H, K2K.
-More details on these SoCs are available at company websites
- K2K: http://www.ti.com/product/tci6638k2k
- K2H: http://www.ti.com/product/tci6638k2h
-
-Board configuration:
-====================
-
-Some of the peripherals that are configured by u-boot are:-
-
-1. 2GB DDR3 (can support 8GB SO DIMM as well)
-2. 512M NAND (over ti emif16 bus)
-3. 6MB MSM SRAM (part of the SoC)
-4. two 1GBit Ethernet ports (SoC supports upto 4)
-5. two UART ports
-6. three i2c interfaces
-7. three spi interfaces (only 1 interface supported in driver)
-
-There are seperate PLLs to drive clocks to Tetris ARM and Peripherals.
-To bring up SMP Linux on this board, there is a boot monitor
-code that will be installed in MSMC SRAM. There is command available
-to install this image from u-boot.
-
-The port related files can be found at following folders
- keystone2 SoC related files: arch/arm/cpu/armv7/keystone/
- K2HK evm board files: board/ti/k2hk_evm/
-
-board configuration file: include/configs/k2hk_evm.h
-
-Supported boot modes:
- - SPI NOR boot
-
-Supported image formats:-
- - u-boot.bin: for loading and running u-boot.bin through Texas instruments
- code composure studio (CCS)
- - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot
-
-Build instructions:
-===================
-
-To build u-boot.bin
- >make k2hk_evm_config
- >make u-boot-spi.gph
-
-To build u-boot-spi.gph
- >make k2hk_evm_config
- >make u-boot-spi.gph
-
-Load and Run U-Boot on K2HK EVM using CCS
-=========================================
-
-Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin
-on EVM. See instructions at below link for installing CCS on a Windows PC.
-http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started#
-Installing_Code_Composer_Studio
-Use u-boot.bin from the build folder for loading annd running u-boot binary
-on EVM. Follow instructions at
-http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup
-to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode"
-and Power ON the EVM. Follow instructions to connect serial port of EVM to
-PC and start TeraTerm or Hyper Terminal.
-
-Start CCS on a Windows machine and Launch Target
-configuration as instructed at http://processors.wiki.ti.com/index.php/
-MCSDK_UG_Chapter_Exploring#Loading_and_Running_U-Boot_on_EVM_through_CCS.
-The instructions provided in the above link uses a script for
-loading the u-boot binary on the target EVM. Instead do the following:-
-
-1. Right click to "Texas Instruments XDS2xx USB Emulator_0/CortexA15_1 core (D
- isconnected: Unknown)" at the debug window (This is created once Target
- configuration is launched) and select "Connect Target".
-2. Once target connect is successful, choose Tools->Load Memory option from the
- top level menu. At the Load Memory window, choose the file u-boot.bin
- through "Browse" button and click "next >" button. In the next window, enter
- Start address as 0xc001000, choose Type-size "32 bits" and click "Finish"
- button.
-3. Click View -> Registers from the top level menu to view registers window.
-4. From Registers, window expand "Core Registers" to view PC. Edit PC value
- to be 0xc001000. From the "Run" top level menu, select "Free Run"
-5. The U-Boot prompt is shown at the Tera Term/ Hyper terminal console as
- below and type any key to stop autoboot as instructed :=
-
-U-Boot 2014.04-rc1-00201-gc215b5a (Mar 21 2014 - 12:47:59)
-
-I2C: ready
-Detected SO-DIMM [SQR-SD3T-2G1333SED]
-DRAM: 1.1 GiB
-NAND: 512 MiB
-Net: K2HK_EMAC
-Warning: K2HK_EMAC using MAC address from net device
-, K2HK_EMAC1, K2HK_EMAC2, K2HK_EMAC3
-Hit any key to stop autoboot: 0
-
-SPI NOR Flash programming instructions
-======================================
-U-Boot image can be flashed to first 512KB of the NOR flash using following
-instructions:-
-
-1. Start CCS and run U-boot as described above.
-2. Suspend Target. Select Run -> Suspend from top level menu
- CortexA15_1 (Free Running)"
-3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000
- through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM
- using CCS", but using address 0x87000000.
-4. Free Run the target as desribed earlier (step 4) to get u-boot prompt
-5. At the U-Boot console type following to setup u-boot environment variables.
- setenv addr_uboot 0x87000000
- setenv filesize <size in hex of u-boot-spi.gph rounded to hex 0x10000>
- run burn_uboot
- Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
- to "SPI Little Endian Boot mode" as per instruction at
- http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup.
-6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash.
diff --git a/qemu/roms/u-boot/board/ti/k2hk_evm/board.c b/qemu/roms/u-boot/board/ti/k2hk_evm/board.c
deleted file mode 100644
index dc3913956..000000000
--- a/qemu/roms/u-boot/board/ti/k2hk_evm/board.c
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * K2HK EVM : Board initialization
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <exports.h>
-#include <fdt_support.h>
-#include <libfdt.h>
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/clock.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
-#include <asm/arch/nand_defs.h>
-#include <asm/arch/emac_defs.h>
-#include <asm/arch/psc_defs.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 device_big_endian;
-
-unsigned int external_clk[ext_clk_count] = {
- [sys_clk] = 122880000,
- [alt_core_clk] = 125000000,
- [pa_clk] = 122880000,
- [tetris_clk] = 125000000,
- [ddr3a_clk] = 100000000,
- [ddr3b_clk] = 100000000,
- [mcm_clk] = 312500000,
- [pcie_clk] = 100000000,
- [sgmii_srio_clk] = 156250000,
- [xgmii_clk] = 156250000,
- [usb_clk] = 100000000,
- [rp1_clk] = 123456789 /* TODO: cannot find
- what is that */
-};
-
-static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = {
- { /* CS0 */
- .mode = ASYNC_EMIF_MODE_NAND,
- .wr_setup = 0xf,
- .wr_strobe = 0x3f,
- .wr_hold = 7,
- .rd_setup = 0xf,
- .rd_strobe = 0x3f,
- .rd_hold = 7,
- .turn_around = 3,
- .width = ASYNC_EMIF_8,
- },
-
-};
-
-static struct pll_init_data pll_config[] = {
- CORE_PLL_1228,
- PASS_PLL_983,
- TETRIS_PLL_1200,
-};
-
-int dram_init(void)
-{
- init_ddr3();
-
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_MAX_RAM_BANK_SIZE);
- init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config);
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
-struct eth_priv_t eth_priv_cfg[] = {
- {
- .int_name = "K2HK_EMAC",
- .rx_flow = 22,
- .phy_addr = 0,
- .slave_port = 1,
- .sgmii_link_type = SGMII_LINK_MAC_PHY,
- },
- {
- .int_name = "K2HK_EMAC1",
- .rx_flow = 23,
- .phy_addr = 1,
- .slave_port = 2,
- .sgmii_link_type = SGMII_LINK_MAC_PHY,
- },
- {
- .int_name = "K2HK_EMAC2",
- .rx_flow = 24,
- .phy_addr = 2,
- .slave_port = 3,
- .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
- },
- {
- .int_name = "K2HK_EMAC3",
- .rx_flow = 25,
- .phy_addr = 3,
- .slave_port = 4,
- .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
- },
-};
-
-int get_eth_env_param(char *env_name)
-{
- char *env;
- int res = -1;
-
- env = getenv(env_name);
- if (env)
- res = simple_strtol(env, NULL, 0);
-
- return res;
-}
-
-int board_eth_init(bd_t *bis)
-{
- int j;
- int res;
- char link_type_name[32];
-
- for (j = 0; j < (sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t));
- j++) {
- sprintf(link_type_name, "sgmii%d_link_type", j);
- res = get_eth_env_param(link_type_name);
- if (res >= 0)
- eth_priv_cfg[j].sgmii_link_type = res;
-
- keystone2_emac_initialize(&eth_priv_cfg[j]);
- }
-
- return 0;
-}
-#endif
-
-/* Byte swap the 32-bit data if the device is BE */
-int cpu_to_bus(u32 *ptr, u32 length)
-{
- u32 i;
-
- if (device_big_endian)
- for (i = 0; i < length; i++, ptr++)
- *ptr = __swab32(*ptr);
-
- return 0;
-}
-
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
-int board_early_init_f(void)
-{
- init_plls(ARRAY_SIZE(pll_config), pll_config);
- return 0;
-}
-#endif
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-#define K2_DDR3_START_ADDR 0x80000000
-void ft_board_setup(void *blob, bd_t *bd)
-{
- u64 start[2];
- u64 size[2];
- char name[32], *env, *endp;
- int lpae, nodeoffset;
- u32 ddr3a_size;
- int nbanks;
-
- env = getenv("mem_lpae");
- lpae = env && simple_strtol(env, NULL, 0);
-
- ddr3a_size = 0;
- if (lpae) {
- env = getenv("ddr3a_size");
- if (env)
- ddr3a_size = simple_strtol(env, NULL, 10);
- if ((ddr3a_size != 8) && (ddr3a_size != 4))
- ddr3a_size = 0;
- }
-
- nbanks = 1;
- start[0] = bd->bi_dram[0].start;
- size[0] = bd->bi_dram[0].size;
-
- /* adjust memory start address for LPAE */
- if (lpae) {
- start[0] -= K2_DDR3_START_ADDR;
- start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
- }
-
- if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
- size[1] = ((u64)ddr3a_size - 2) << 30;
- start[1] = 0x880000000;
- nbanks++;
- }
-
- /* reserve memory at start of bank */
- sprintf(name, "mem_reserve_head");
- env = getenv(name);
- if (env) {
- start[0] += ustrtoul(env, &endp, 0);
- size[0] -= ustrtoul(env, &endp, 0);
- }
-
- sprintf(name, "mem_reserve");
- env = getenv(name);
- if (env)
- size[0] -= ustrtoul(env, &endp, 0);
-
- fdt_fixup_memory_banks(blob, start, size, nbanks);
-
- /* Fix up the initrd */
- if (lpae) {
- u64 initrd_start, initrd_end;
- u32 *prop1, *prop2;
- int err;
- nodeoffset = fdt_path_offset(blob, "/chosen");
- if (nodeoffset >= 0) {
- prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
- "linux,initrd-start", NULL);
- prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
- "linux,initrd-end", NULL);
- if (prop1 && prop2) {
- initrd_start = __be32_to_cpu(*prop1);
- initrd_start -= K2_DDR3_START_ADDR;
- initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
- initrd_start = __cpu_to_be64(initrd_start);
- initrd_end = __be32_to_cpu(*prop2);
- initrd_end -= K2_DDR3_START_ADDR;
- initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
- initrd_end = __cpu_to_be64(initrd_end);
-
- err = fdt_delprop(blob, nodeoffset,
- "linux,initrd-start");
- if (err < 0)
- puts("error deleting initrd-start\n");
-
- err = fdt_delprop(blob, nodeoffset,
- "linux,initrd-end");
- if (err < 0)
- puts("error deleting initrd-end\n");
-
- err = fdt_setprop(blob, nodeoffset,
- "linux,initrd-start",
- &initrd_start,
- sizeof(initrd_start));
- if (err < 0)
- puts("error adding initrd-start\n");
-
- err = fdt_setprop(blob, nodeoffset,
- "linux,initrd-end",
- &initrd_end,
- sizeof(initrd_end));
- if (err < 0)
- puts("error adding linux,initrd-end\n");
- }
- }
- }
-}
-
-void ft_board_setup_ex(void *blob, bd_t *bd)
-{
- int lpae;
- char *env;
- u64 *reserve_start, size;
-
- env = getenv("mem_lpae");
- lpae = env && simple_strtol(env, NULL, 0);
-
- if (lpae) {
- /*
- * the initrd and other reserved memory areas are
- * embedded in in the DTB itslef. fix up these addresses
- * to 36 bit format
- */
- reserve_start = (u64 *)((char *)blob +
- fdt_off_mem_rsvmap(blob));
- while (1) {
- *reserve_start = __cpu_to_be64(*reserve_start);
- size = __cpu_to_be64(*(reserve_start + 1));
- if (size) {
- *reserve_start -= K2_DDR3_START_ADDR;
- *reserve_start +=
- CONFIG_SYS_LPAE_SDRAM_BASE;
- *reserve_start =
- __cpu_to_be64(*reserve_start);
- } else {
- break;
- }
- reserve_start += 2;
- }
- }
-}
-#endif
diff --git a/qemu/roms/u-boot/board/ti/k2hk_evm/ddr3.c b/qemu/roms/u-boot/board/ti/k2hk_evm/ddr3.c
deleted file mode 100644
index 6092eb8fe..000000000
--- a/qemu/roms/u-boot/board/ti/k2hk_evm/ddr3.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * Keystone2: DDR3 initialization
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <i2c.h>
-
-/************************* *****************************/
-static struct ddr3_phy_config ddr3phy_1600_64A = {
- .pllcr = 0x0001C000ul,
- .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
- .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
- .ptr0 = 0x42C21590ul,
- .ptr1 = 0xD05612C0ul,
- .ptr2 = 0, /* not set in gel */
- .ptr3 = 0x0D861A80ul,
- .ptr4 = 0x0C827100ul,
- .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
- .dcr_val = ((1 << 10) | (1 << 27)),
- .dtpr0 = 0xA19DBB66ul,
- .dtpr1 = 0x12868300ul,
- .dtpr2 = 0x50035200ul,
- .mr0 = 0x00001C70ul,
- .mr1 = 0x00000006ul,
- .mr2 = 0x00000018ul,
- .dtcr = 0x730035C7ul,
- .pgcr2 = 0x00F07A12ul,
- .zq0cr1 = 0x0000005Dul,
- .zq1cr1 = 0x0000005Bul,
- .zq2cr1 = 0x0000005Bul,
- .pir_v1 = 0x00000033ul,
- .pir_v2 = 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1600_64 = {
- .sdcfg = 0x6200CE6aul,
- .sdtim1 = 0x16709C55ul,
- .sdtim2 = 0x00001D4Aul,
- .sdtim3 = 0x435DFF54ul,
- .sdtim4 = 0x553F0CFFul,
- .zqcfg = 0xF0073200ul,
- .sdrfc = 0x00001869ul,
-};
-
-static struct ddr3_phy_config ddr3phy_1600_32 = {
- .pllcr = 0x0001C000ul,
- .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
- .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
- .ptr0 = 0x42C21590ul,
- .ptr1 = 0xD05612C0ul,
- .ptr2 = 0, /* not set in gel */
- .ptr3 = 0x0D861A80ul,
- .ptr4 = 0x0C827100ul,
- .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
- .dcr_val = ((1 << 10) | (1 << 27)),
- .dtpr0 = 0xA19DBB66ul,
- .dtpr1 = 0x12868300ul,
- .dtpr2 = 0x50035200ul,
- .mr0 = 0x00001C70ul,
- .mr1 = 0x00000006ul,
- .mr2 = 0x00000018ul,
- .dtcr = 0x730035C7ul,
- .pgcr2 = 0x00F07A12ul,
- .zq0cr1 = 0x0000005Dul,
- .zq1cr1 = 0x0000005Bul,
- .zq2cr1 = 0x0000005Bul,
- .pir_v1 = 0x00000033ul,
- .pir_v2 = 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1600_32 = {
- .sdcfg = 0x6200DE6aul,
- .sdtim1 = 0x16709C55ul,
- .sdtim2 = 0x00001D4Aul,
- .sdtim3 = 0x435DFF54ul,
- .sdtim4 = 0x553F0CFFul,
- .zqcfg = 0x70073200ul,
- .sdrfc = 0x00001869ul,
-};
-
-/************************* *****************************/
-static struct ddr3_phy_config ddr3phy_1333_64A = {
- .pllcr = 0x0005C000ul,
- .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
- .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
- .ptr0 = 0x42C21590ul,
- .ptr1 = 0xD05612C0ul,
- .ptr2 = 0, /* not set in gel */
- .ptr3 = 0x0B4515C2ul,
- .ptr4 = 0x0A6E08B4ul,
- .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
- NOSRA_MASK | UDIMM_MASK),
- .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)),
- .dtpr0 = 0x8558AA55ul,
- .dtpr1 = 0x12857280ul,
- .dtpr2 = 0x5002C200ul,
- .mr0 = 0x00001A60ul,
- .mr1 = 0x00000006ul,
- .mr2 = 0x00000010ul,
- .dtcr = 0x710035C7ul,
- .pgcr2 = 0x00F065B8ul,
- .zq0cr1 = 0x0000005Dul,
- .zq1cr1 = 0x0000005Bul,
- .zq2cr1 = 0x0000005Bul,
- .pir_v1 = 0x00000033ul,
- .pir_v2 = 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1333_64 = {
- .sdcfg = 0x62008C62ul,
- .sdtim1 = 0x125C8044ul,
- .sdtim2 = 0x00001D29ul,
- .sdtim3 = 0x32CDFF43ul,
- .sdtim4 = 0x543F0ADFul,
- .zqcfg = 0xF0073200ul,
- .sdrfc = 0x00001457ul,
-};
-
-static struct ddr3_phy_config ddr3phy_1333_32 = {
- .pllcr = 0x0005C000ul,
- .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
- .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
- .ptr0 = 0x42C21590ul,
- .ptr1 = 0xD05612C0ul,
- .ptr2 = 0, /* not set in gel */
- .ptr3 = 0x0B4515C2ul,
- .ptr4 = 0x0A6E08B4ul,
- .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK |
- NOSRA_MASK | UDIMM_MASK),
- .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)),
- .dtpr0 = 0x8558AA55ul,
- .dtpr1 = 0x12857280ul,
- .dtpr2 = 0x5002C200ul,
- .mr0 = 0x00001A60ul,
- .mr1 = 0x00000006ul,
- .mr2 = 0x00000010ul,
- .dtcr = 0x710035C7ul,
- .pgcr2 = 0x00F065B8ul,
- .zq0cr1 = 0x0000005Dul,
- .zq1cr1 = 0x0000005Bul,
- .zq2cr1 = 0x0000005Bul,
- .pir_v1 = 0x00000033ul,
- .pir_v2 = 0x0000FF81ul,
-};
-
-static struct ddr3_emif_config ddr3_1333_32 = {
- .sdcfg = 0x62009C62ul,
- .sdtim1 = 0x125C8044ul,
- .sdtim2 = 0x00001D29ul,
- .sdtim3 = 0x32CDFF43ul,
- .sdtim4 = 0x543F0ADFul,
- .zqcfg = 0xf0073200ul,
- .sdrfc = 0x00001457ul,
-};
-
-/************************* *****************************/
-static struct ddr3_phy_config ddr3phy_1333_64 = {
- .pllcr = 0x0005C000ul,
- .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
- .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
- .ptr0 = 0x42C21590ul,
- .ptr1 = 0xD05612C0ul,
- .ptr2 = 0, /* not set in gel */
- .ptr3 = 0x0B4515C2ul,
- .ptr4 = 0x0A6E08B4ul,
- .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
- .dcr_val = ((1 << 10) | (1 << 27)),
- .dtpr0 = 0x8558AA55ul,
- .dtpr1 = 0x12857280ul,
- .dtpr2 = 0x5002C200ul,
- .mr0 = 0x00001A60ul,
- .mr1 = 0x00000006ul,
- .mr2 = 0x00000010ul,
- .dtcr = 0x710035C7ul,
- .pgcr2 = 0x00F065B8ul,
- .zq0cr1 = 0x0000005Dul,
- .zq1cr1 = 0x0000005Bul,
- .zq2cr1 = 0x0000005Bul,
- .pir_v1 = 0x00000033ul,
- .pir_v2 = 0x0000FF81ul,
-};
-/******************************************************/
-int get_dimm_params(char *dimm_name)
-{
- u8 spd_params[256];
- int ret;
- int old_bus;
-
- i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
-
- old_bus = i2c_get_bus_num();
- i2c_set_bus_num(1);
-
- ret = i2c_read(0x53, 0, 1, spd_params, 256);
-
- i2c_set_bus_num(old_bus);
-
- dimm_name[0] = '\0';
-
- if (ret) {
- puts("Cannot read DIMM params\n");
- return 1;
- }
-
- /*
- * We need to convert spd data to dimm parameters
- * and to DDR3 EMIF and PHY regirsters values.
- * For now we just return DIMM type string value.
- * Caller may use this value to choose appropriate
- * a pre-set DDR3 configuration
- */
-
- strncpy(dimm_name, (char *)&spd_params[0x80], 18);
- dimm_name[18] = '\0';
-
- return 0;
-}
-
-struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
-struct pll_init_data ddr3b_333 = DDR3_PLL_333(B);
-struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
-struct pll_init_data ddr3b_400 = DDR3_PLL_400(B);
-
-void init_ddr3(void)
-{
- char dimm_name[32];
-
- get_dimm_params(dimm_name);
-
- printf("Detected SO-DIMM [%s]\n", dimm_name);
-
- if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
- init_pll(&ddr3a_400);
- if (cpu_revision() > 0) {
- init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_64A);
- init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_64);
- printf("DRAM: Capacity 8 GiB (includes reported below)\n");
- } else {
- init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_32);
- init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_32);
- printf("DRAM: Capacity 4 GiB (includes reported below)\n");
- }
- } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
- init_pll(&ddr3a_333);
- if (cpu_revision() > 0) {
- init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_64A);
- init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_64);
- } else {
- init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_32);
- init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_32);
- }
- } else {
- printf("Unknown SO-DIMM. Cannot configure DDR3\n");
- while (1)
- ;
- }
-
- init_pll(&ddr3b_333);
- init_ddrphy(K2HK_DDR3B_DDRPHYC, &ddr3phy_1333_64);
- init_ddremif(K2HK_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64);
-}
diff --git a/qemu/roms/u-boot/board/ti/omap5912osk/Makefile b/qemu/roms/u-boot/board/ti/omap5912osk/Makefile
deleted file mode 100644
index d7c0ebd72..000000000
--- a/qemu/roms/u-boot/board/ti/omap5912osk/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := omap5912osk.o
-obj-y += lowlevel_init.o
diff --git a/qemu/roms/u-boot/board/ti/omap5912osk/config.mk b/qemu/roms/u-boot/board/ti/omap5912osk/config.mk
deleted file mode 100644
index 5b8d952ba..000000000
--- a/qemu/roms/u-boot/board/ti/omap5912osk/config.mk
+++ /dev/null
@@ -1,30 +0,0 @@
-#
-# (C) Copyright 2002-2004
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# (C) Copyright 2003
-# Texas Instruments, <www.ti.com>
-# Kshitij Gupta <Kshitij@ti.com>
-#
-# (C) Copyright 2004
-# Texas Instruments, <www.ti.com>
-# Rishi Bhattacharya <rishi@ti.com>
-#
-# TI OSK board with OMAP5912 (ARM925EJS) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# OSK has 1 bank of 32 MB SDRAM
-# Physical Address:
-# 1000'0000 to 1200'0000
-#
-#
-# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
-# (mem base + reserved)
-#
-# When running from RAM use address 1108'0000, otherwise when
-# booting from NOR flash link to address 0000'0000.
-#
-
-CONFIG_SYS_TEXT_BASE = 0x00000000
-#CONFIG_SYS_TEXT_BASE = 0x11080000
diff --git a/qemu/roms/u-boot/board/ti/omap5912osk/lowlevel_init.S b/qemu/roms/u-boot/board/ti/omap5912osk/lowlevel_init.S
deleted file mode 100644
index e05a1c7b5..000000000
--- a/qemu/roms/u-boot/board/ti/omap5912osk/lowlevel_init.S
+++ /dev/null
@@ -1,477 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
- *
- * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-
-#if defined(CONFIG_OMAP1610)
-#include <./configs/omap1510.h>
-#endif
-
-.globl lowlevel_init
-lowlevel_init:
-
- /*------------------------------------------------------*
- * Ensure i-cache is enabled *
- * To configure TC regs without fetching instruction *
- *------------------------------------------------------*/
- mrc p15, 0, r0, c1, c0
- orr r0, r0, #0x1000
- mcr p15, 0, r0, c1, c0
-
- /*------------------------------------------------------*
- *mask all IRQs by setting all bits in the INTMR default*
- *------------------------------------------------------*/
- mov r1, #0xffffffff
- ldr r0, =REG_IHL1_MIR
- str r1, [r0]
- ldr r0, =REG_IHL2_MIR
- str r1, [r0]
-
- /*------------------------------------------------------*
- * Set up ARM CLM registers (IDLECT1) *
- *------------------------------------------------------*/
- ldr r0, REG_ARM_IDLECT1
- ldr r1, VAL_ARM_IDLECT1
- str r1, [r0]
-
- /*------------------------------------------------------*
- * Set up ARM CLM registers (IDLECT2) *
- *------------------------------------------------------*/
- ldr r0, REG_ARM_IDLECT2
- ldr r1, VAL_ARM_IDLECT2
- str r1, [r0]
-
- /*------------------------------------------------------*
- * Set up ARM CLM registers (IDLECT3) *
- *------------------------------------------------------*/
- ldr r0, REG_ARM_IDLECT3
- ldr r1, VAL_ARM_IDLECT3
- str r1, [r0]
-
- mov r1, #0x01 /* PER_EN bit */
- ldr r0, REG_ARM_RSTCT2
- strh r1, [r0] /* CLKM; Peripheral reset. */
-
- /* Set CLKM to Sync-Scalable */
- mov r1, #0x1000
- ldr r0, REG_ARM_SYSST
-
- mov r2, #0
-1: cmp r2, #1
- streqh r1, [r0]
- add r2, r2, #1
- cmp r2, #0x100 /* wait for any bubbles to finish */
- bne 1b
-
- ldr r1, VAL_ARM_CKCTL
- ldr r0, REG_ARM_CKCTL
- strh r1, [r0]
-
- /* a few nops to let settle */
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
- /* setup DPLL 1 */
- /* Ramp up the clock to 96Mhz */
- ldr r1, VAL_DPLL1_CTL
- ldr r0, REG_DPLL1_CTL
- strh r1, [r0]
- ands r1, r1, #0x10 /* Check if PLL is enabled. */
- beq lock_end /* Do not look for lock if BYPASS selected */
-2:
- ldrh r1, [r0]
- ands r1, r1, #0x01 /* Check the LOCK bit.*/
- beq 2b /* loop until bit goes hi. */
-lock_end:
-
- /*------------------------------------------------------*
- * Turn off the watchdog during init... *
- *------------------------------------------------------*/
- ldr r0, REG_WATCHDOG
- ldr r1, WATCHDOG_VAL1
- str r1, [r0]
- ldr r1, WATCHDOG_VAL2
- str r1, [r0]
- ldr r0, REG_WSPRDOG
- ldr r1, WSPRDOG_VAL1
- str r1, [r0]
- ldr r0, REG_WWPSDOG
-
-watch1Wait:
- ldr r1, [r0]
- tst r1, #0x10
- bne watch1Wait
-
- ldr r0, REG_WSPRDOG
- ldr r1, WSPRDOG_VAL2
- str r1, [r0]
- ldr r0, REG_WWPSDOG
-watch2Wait:
- ldr r1, [r0]
- tst r1, #0x10
- bne watch2Wait
-
- /* Set memory timings corresponding to the new clock speed */
- ldr r3, VAL_SDRAM_CONFIG_SDF0
-
- /* Check execution location to determine current execution location
- * and branch to appropriate initialization code.
- */
- mov r0, #0x10000000 /* Load physical SDRAM base. */
- mov r1, pc /* Get current execution location. */
- cmp r1, r0 /* Compare. */
- bge skip_sdram /* Skip over EMIF-fast initialization if running from SDRAM. */
-
- /* identify the device revision, -- TMX or TMP(TMS) */
- ldr r0, REG_DEVICE_ID
- ldr r1, [r0]
-
- ldr r0, VAL_DEVICE_ID_TMP
- mov r1, r1, lsl #15
- mov r1, r1, lsr #16
- cmp r0, r1
- bne skip_TMP_Patch
-
- /* Enable TMP/TMS device new features */
- mov r0, #1
- ldr r1, REG_TC_EMIFF_DOUBLER
- str r0, [r1]
-
- /* Enable new ac parameters */
- mov r0, #0x0b
- ldr r1, REG_SDRAM_CONFIG2
- str r0, [r1]
-
- ldr r3, VAL_SDRAM_CONFIG_SDF1
-
-skip_TMP_Patch:
-
- /*
- * Delay for SDRAM initialization.
- */
- mov r0, #0x1800 /* value should be checked */
-3:
- subs r0, r0, #0x1 /* Decrement count */
- bne 3b
-
- /*
- * Set SDRAM control values. Disable refresh before MRS command.
- */
-
- /* mobile ddr operation */
- ldr r0, REG_SDRAM_OPERATION
- mov r2, #07
- str r2, [r0]
-
- /* config register */
- ldr r0, REG_SDRAM_CONFIG
- str r3, [r0]
-
- /* manual command register */
- ldr r0, REG_SDRAM_MANUAL_CMD
-
- /* issue set cke high */
- mov r1, #CMD_SDRAM_CKE_SET_HIGH
- str r1, [r0]
-
- /* issue nop */
- mov r1, #CMD_SDRAM_NOP
- str r1, [r0]
-
- mov r2, #0x0100
-waitMDDR1:
- subs r2, r2, #1
- bne waitMDDR1 /* delay loop */
-
- /* issue precharge */
- mov r1, #CMD_SDRAM_PRECHARGE
- str r1, [r0]
-
- /* issue autorefresh x 2 */
- mov r1, #CMD_SDRAM_AUTOREFRESH
- str r1, [r0]
- str r1, [r0]
-
- /* mrs register ddr mobile */
- ldr r0, REG_SDRAM_MRS
- mov r1, #0x33
- str r1, [r0]
-
- /* emrs1 low-power register */
- ldr r0, REG_SDRAM_EMRS1
- /* self refresh on all banks */
- mov r1, #0
- str r1, [r0]
-
- ldr r0, REG_DLL_URD_CONTROL
- ldr r1, DLL_URD_CONTROL_VAL
- str r1, [r0]
-
- ldr r0, REG_DLL_LRD_CONTROL
- ldr r1, DLL_LRD_CONTROL_VAL
- str r1, [r0]
-
- ldr r0, REG_DLL_WRT_CONTROL
- ldr r1, DLL_WRT_CONTROL_VAL
- str r1, [r0]
-
- /* delay loop */
- mov r0, #0x0100
-waitMDDR2:
- subs r0, r0, #1
- bne waitMDDR2
-
- /*
- * Delay for SDRAM initialization.
- */
- mov r0, #0x1800
-4:
- subs r0, r0, #1 /* Decrement count. */
- bne 4b
- b common_tc
-
-skip_sdram:
- ldr r0, REG_SDRAM_CONFIG
- str r3, [r0]
-
-common_tc:
- /* slow interface */
- ldr r1, VAL_TC_EMIFS_CS0_CONFIG
- ldr r0, REG_TC_EMIFS_CS0_CONFIG
- str r1, [r0] /* Chip Select 0 */
-
- ldr r1, VAL_TC_EMIFS_CS1_CONFIG
- ldr r0, REG_TC_EMIFS_CS1_CONFIG
- str r1, [r0] /* Chip Select 1 */
-
- ldr r1, VAL_TC_EMIFS_CS3_CONFIG
- ldr r0, REG_TC_EMIFS_CS3_CONFIG
- str r1, [r0] /* Chip Select 3 */
-
- ldr r1, VAL_TC_EMIFS_DWS
- ldr r0, REG_TC_EMIFS_DWS
- str r1, [r0] /* Enable EMIFS.RDY for CS1 (ether) */
-
-#ifdef CONFIG_H2_OMAP1610
- /* inserting additional 2 clock cycle hold time for LAN */
- ldr r0, REG_TC_EMIFS_CS1_ADVANCED
- ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
- str r1, [r0]
-#endif
- /* Start MPU Timer 1 */
- ldr r0, REG_MPU_LOAD_TIMER
- ldr r1, VAL_MPU_LOAD_TIMER
- str r1, [r0]
-
- ldr r0, REG_MPU_CNTL_TIMER
- ldr r1, VAL_MPU_CNTL_TIMER
- str r1, [r0]
-
- /*
- * Setup a temporary stack
- */
- ldr sp, SRAM_STACK
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
-
- /*
- * Save the old lr(passed in ip) and the current lr to stack
- */
- push {ip, lr}
-
- /*
- * go setup pll, mux, memory
- */
- bl s_init
- pop {ip, pc}
-
- /* back to arch calling code */
- mov pc, lr
-
- /* the literal pools origin */
- .ltorg
-
-REG_DEVICE_ID: /* 32 bits */
- .word 0xfffe2004
-REG_TC_EMIFS_CONFIG:
- .word 0xfffecc0c
-REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
- .word 0xfffecc10
-REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
- .word 0xfffecc14
-REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
- .word 0xfffecc18
-REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
- .word 0xfffecc1c
-REG_TC_EMIFS_DWS: /* 32 bits */
- .word 0xfffecc40
-#ifdef CONFIG_H2_OMAP1610
-REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
- .word 0xfffecc54
-#endif
-
-/* MPU clock/reset/power mode control registers */
-REG_ARM_CKCTL: /* 16 bits */
- .word 0xfffece00
-REG_ARM_IDLECT3: /* 16 bits */
- .word 0xfffece24
-REG_ARM_IDLECT2: /* 16 bits */
- .word 0xfffece08
-REG_ARM_IDLECT1: /* 16 bits */
- .word 0xfffece04
-REG_ARM_RSTCT2: /* 16 bits */
- .word 0xfffece14
-REG_ARM_SYSST: /* 16 bits */
- .word 0xfffece18
-
-/* DPLL control registers */
-REG_DPLL1_CTL: /* 16 bits */
- .word 0xfffecf00
-
-/* Watch Dog register */
-/* secure watchdog stop */
-REG_WSPRDOG:
- .word 0xfffeb048
-/* watchdog write pending */
-REG_WWPSDOG:
- .word 0xfffeb034
-
-WSPRDOG_VAL1:
- .word 0x0000aaaa
-WSPRDOG_VAL2:
- .word 0x00005555
-
-/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
- counter @8192 rows, 10 ns, 8 burst */
-REG_SDRAM_CONFIG:
- .word 0xfffecc20
-REG_SDRAM_CONFIG2:
- .word 0xfffecc3c
-REG_TC_EMIFF_DOUBLER: /* 32 bits */
- .word 0xfffecc60
-
-/* Operation register */
-REG_SDRAM_OPERATION:
- .word 0xfffecc80
-
-/* Manual command register */
-REG_SDRAM_MANUAL_CMD:
- .word 0xfffecc84
-
-/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
-REG_SDRAM_MRS:
- .word 0xfffecc70
-
-/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
-REG_SDRAM_EMRS1:
- .word 0xfffecc78
-
-/* WRT DLL register */
-REG_DLL_WRT_CONTROL:
- .word 0xfffecc68
-DLL_WRT_CONTROL_VAL:
- .word 0x03f00002 /* Phase of 72deg, write offset +31 */
-
-/* URD DLL register */
-REG_DLL_URD_CONTROL:
- .word 0xfffeccc0
-DLL_URD_CONTROL_VAL:
- .word 0x00800002 /* Phase of 72deg, read offset +31 */
-
-/* LRD DLL register */
-REG_DLL_LRD_CONTROL:
- .word 0xfffecccc
-DLL_LRD_CONTROL_VAL:
- .word 0x00800002 /* read offset +31 */
-
-REG_WATCHDOG:
- .word 0xfffec808
-WATCHDOG_VAL1:
- .word 0x000000f5
-WATCHDOG_VAL2:
- .word 0x000000a0
-
-REG_MPU_LOAD_TIMER:
- .word 0xfffec504
-REG_MPU_CNTL_TIMER:
- .word 0xfffec500
-VAL_MPU_LOAD_TIMER:
- .word 0xffffffff
-VAL_MPU_CNTL_TIMER:
- .word 0xffffffa1
-
-/* 96 MHz Samsung Mobile DDR */
-/* Original setting for TMX device */
-VAL_SDRAM_CONFIG_SDF0:
- .word 0x0014e6fe
-
-/* NEW_SYS_FREQ mode (valid only TMP/TMS devices) */
-VAL_SDRAM_CONFIG_SDF1:
- .word 0x0114e6fe
-
-VAL_ARM_CKCTL:
- .word 0x2000 /* was: 0x3000, now use CLK_REF for timer input */
-VAL_DPLL1_CTL:
- .word 0x2830
-
-#ifdef CONFIG_OSK_OMAP5912
-VAL_TC_EMIFS_CS0_CONFIG:
- .word 0x002130b0
-VAL_TC_EMIFS_CS1_CONFIG:
- .word 0x00001133
-VAL_TC_EMIFS_CS2_CONFIG:
- .word 0x000055f0
-VAL_TC_EMIFS_CS3_CONFIG:
- .word 0x88013141
-VAL_TC_EMIFS_DWS: /* Enable EMIFS.RDY for CS1 access (ether) */
- .word 0x000000c0
-VAL_DEVICE_ID_TMP: /* TMP/TMS=0xb65f, TMX=0xb58c */
- .word 0xb65f
-#endif
-
-#ifdef CONFIG_H2_OMAP1610
-VAL_TC_EMIFS_CS0_CONFIG:
- .word 0x00203331
-VAL_TC_EMIFS_CS1_CONFIG:
- .word 0x8180fff3
-VAL_TC_EMIFS_CS2_CONFIG:
- .word 0xf800f22a
-VAL_TC_EMIFS_CS3_CONFIG:
- .word 0x88013141
-VAL_TC_EMIFS_CS1_ADVANCED:
- .word 0x00000022
-#endif
-
-VAL_ARM_IDLECT1:
- .word 0x00000400
-VAL_ARM_IDLECT2:
- .word 0x00000886
-VAL_ARM_IDLECT3:
- .word 0x00000015
-
-SRAM_STACK:
- .word CONFIG_SYS_INIT_SP_ADDR
-
-/* command values */
-.equ CMD_SDRAM_NOP, 0x00000000
-.equ CMD_SDRAM_PRECHARGE, 0x00000001
-.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
-.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007
diff --git a/qemu/roms/u-boot/board/ti/omap5912osk/omap5912osk.c b/qemu/roms/u-boot/board/ti/omap5912osk/omap5912osk.c
deleted file mode 100644
index 88a7310ce..000000000
--- a/qemu/roms/u-boot/board/ti/omap5912osk/omap5912osk.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Rishi Bhattacharya <rishi@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#if defined(CONFIG_OMAP1610)
-#include <./configs/omap1510.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void flash__init (void);
-void ether__init (void);
-void set_muxconf_regs (void);
-void peripheral_power_enable (void);
-
-#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
-
-static inline void delay (unsigned long loops)
-{
- __asm__ volatile ("1:\n"
- "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0" (loops));
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
- gd->bd->bi_arch_number = MACH_TYPE_OMAP_OSK;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x10000100;
-
- flash__init();
- ether__init();
-
- return 0;
-}
-
-void s_init(void)
-{
- /* Configure MUX settings */
- set_muxconf_regs ();
- peripheral_power_enable ();
-
-/* this speeds up your boot a quite a bit. However to make it
- * work, you need make sure your kernel startup flush bug is fixed.
- * ... rkw ...
- */
- icache_enable ();
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-void flash__init (void)
-{
-#define EMIFS_GlB_Config_REG 0xfffecc0c
- unsigned int regval;
- regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
- /* Turn off write protection for flash devices. */
- regval = regval | 0x0001;
- *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
-}
-/*************************************************************
- Routine:ether__init
- Description: take the Ethernet controller out of reset and wait
- for the EEPROM load to complete.
-*************************************************************/
-void ether__init (void)
-{
-#define ETH_CONTROL_REG 0x0480000b
- int i;
-
- *((volatile unsigned short *) 0xfffece08) = 0x03FF;
- *((volatile unsigned short *) 0xfffb3824) = 0x8000;
- *((volatile unsigned short *) 0xfffb3830) = 0x0000;
- *((volatile unsigned short *) 0xfffb3834) = 0x0009;
- *((volatile unsigned short *) 0xfffb3838) = 0x0009;
- *((volatile unsigned short *) 0xfffb3818) = 0x0002;
- *((volatile unsigned short *) 0xfffb382C) = 0x0048;
- *((volatile unsigned short *) 0xfffb3824) = 0x8603;
- udelay (3);
- for (i=0;i<2000;i++);
- *((volatile unsigned short *) 0xfffb381C) = 0x6610;
- udelay (30);
- for (i=0;i<10000;i++);
-
- *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
- udelay (3);
-
-
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
-
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-/******************************************************
- Routine: set_muxconf_regs
- Description: Setting up the configuration Mux registers
- specific to the hardware
-*******************************************************/
-void set_muxconf_regs (void)
-{
- volatile unsigned int *MuxConfReg;
- /* set each registers to its reset value; */
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
- /* setup for UART1 */
- *MuxConfReg &= ~(0x02000000); /* bit 25 */
- /* setup for UART2 */
- *MuxConfReg &= ~(0x01000000); /* bit 24 */
- /* Disable Uwire CS Hi-Z */
- *MuxConfReg |= 0x08000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6);
- /*setup mux for UART3 */
- *MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */
- *MuxConfReg &= ~0x0000003e;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8);
- /* Disable Uwire CS Hi-Z */
- *MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9);
- /* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */
- /* hardware will actually use TX and RTS based on bit 25 in */
- /* FUNC_MUX_CTRL_0. I told you this thing was screwy! */
- *MuxConfReg |= 0x00201000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C);
- /* setup for UART2 */
- /* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */
- /* hardware will actually use TX and RTS based on bit 24 in */
- /* FUNC_MUX_CTRL_0. */
- *MuxConfReg |= 0x09000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_D);
- *MuxConfReg |= 0x00000020;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1);
- *MuxConfReg = 0x00000000;
- /* mux setup for SD/MMC driver */
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2);
- *MuxConfReg &= 0xFFFE0FFF;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
- /* bit 13 for MMC2 XOR_CLK */
- *MuxConfReg &= ~(0x00002000);
- /* bit 29 for UART 1 */
- *MuxConfReg &= ~(0x00002000);
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
- /* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */
- *MuxConfReg |= 0x000C0000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL);
- *MuxConfReg &= ~(0x00000070);
- *MuxConfReg &= ~(0x00000008);
- *MuxConfReg |= 0x00000003;
- *MuxConfReg |= 0x00000180;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
- /* bit 17, software controls VBUS */
- *MuxConfReg &= ~(0x00020000);
- /* Enable USB 48 and 12M clocks */
- *MuxConfReg |= 0x00000200;
- *MuxConfReg &= ~(0x00000180);
- /*2.75V for MMCSDIO1 */
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0);
- *MuxConfReg = 0x00001FE7;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PU_PD_SEL_0);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PU_PD_SEL_1);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PU_PD_SEL_3);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PU_PD_SEL_4);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4);
- *MuxConfReg = 0x00000000;
- /* Turn on UART2 48 MHZ clock */
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
- *MuxConfReg |= 0x40000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) USB_OTG_CTRL);
- /* setup for USB VBus detection OMAP161x */
- *MuxConfReg |= 0x00040000; /* bit 18 */
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
- /* PullUps for SD/MMC driver */
- *MuxConfReg |= ~(0xFFFE0FFF);
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0);
- *MuxConfReg = COMP_MODE_ENABLE;
-}
-
-/******************************************************
- Routine: peripheral_power_enable
- Description: Enable the power for UART1
-*******************************************************/
-void peripheral_power_enable (void)
-{
-#define UART1_48MHZ_ENABLE ((unsigned short)0x0200)
-#define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834)
-
- *SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;
-}
-
-/*
- * Check Board Identity
- */
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- puts("Board: OSK5912");
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return (0);
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_LAN91C96
- rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
-#endif
- return rc;
-}
-#endif
diff --git a/qemu/roms/u-boot/board/ti/omap5_uevm/Makefile b/qemu/roms/u-boot/board/ti/omap5_uevm/Makefile
deleted file mode 100644
index b88ab8f51..000000000
--- a/qemu/roms/u-boot/board/ti/omap5_uevm/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := evm.o
diff --git a/qemu/roms/u-boot/board/ti/omap5_uevm/README b/qemu/roms/u-boot/board/ti/omap5_uevm/README
deleted file mode 100644
index 970e2eceb..000000000
--- a/qemu/roms/u-boot/board/ti/omap5_uevm/README
+++ /dev/null
@@ -1,25 +0,0 @@
-Summary
-=======
-
-This document covers various features of the 'omap5_uevm' build and some
-related uses.
-
-eMMC boot partition use
-=======================
-
-It is possible, depending on SYSBOOT configuration to boot from the eMMC
-boot partitions using (name depending on documentation referenced)
-Alternative Boot operation mode or Boot Sequence Option 1/2. In this
-example we load MLO and u-boot.img from the build into DDR and then use
-'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to
-set boot0 as the boot device.
-U-Boot # setenv autoload no
-U-Boot # usb start
-U-Boot # dhcp
-U-Boot # mmc dev 1 1
-U-Boot # tftp ${loadaddr} omap5uevm/MLO
-U-Boot # mmc write ${loadaddr} 0 100
-U-Boot # tftp ${loadaddr} omap5uevm/u-boot.img
-U-Boot # mmc write ${loadaddr} 300 400
-U-Boot # mmc bootbus 1 2 0 2
-U-Boot # mmc partconf 1 1 1 0
diff --git a/qemu/roms/u-boot/board/ti/omap5_uevm/evm.c b/qemu/roms/u-boot/board/ti/omap5_uevm/evm.c
deleted file mode 100644
index 4666b38a7..000000000
--- a/qemu/roms/u-boot/board/ti/omap5_uevm/evm.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments Incorporated, <www.ti.com>
- * Aneesh V <aneesh@ti.com>
- * Steve Sakoman <steve@sakoman.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <palmas.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mmc_host_def.h>
-#include <tca642x.h>
-
-#include "mux_data.h"
-
-#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
-#include <sata.h>
-#include <usb.h>
-#include <asm/gpio.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/ehci.h>
-#include <asm/ehci-omap.h>
-#include <asm/arch/sata.h>
-
-#define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
-#define DIE_ID_REG_OFFSET 0x200
-
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const struct omap_sysinfo sysinfo = {
- "Board: OMAP5432 uEVM\n"
-};
-
-/**
- * @brief tca642x_init - uEVM default values for the GPIO expander
- * input reg, output reg, polarity reg, configuration reg
- */
-struct tca642x_bank_info tca642x_init[] = {
- { .input_reg = 0x00,
- .output_reg = 0x04,
- .polarity_reg = 0x00,
- .configuration_reg = 0x80 },
- { .input_reg = 0x00,
- .output_reg = 0x00,
- .polarity_reg = 0x00,
- .configuration_reg = 0xff },
- { .input_reg = 0x00,
- .output_reg = 0x00,
- .polarity_reg = 0x00,
- .configuration_reg = 0x40 },
-};
-
-/**
- * @brief board_init
- *
- * @return 0
- */
-int board_init(void)
-{
- gpmc_init();
- gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
- gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
-
- tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init);
-
- return 0;
-}
-
-int board_late_init(void)
-{
- init_sata(0);
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- return 0;
-}
-
-#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
-static void enable_host_clocks(void)
-{
- int auxclk;
- int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
- OPTFCLKEN_HSIC480M_P3_CLK |
- OPTFCLKEN_HSIC60M_P2_CLK |
- OPTFCLKEN_HSIC480M_P2_CLK |
- OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
-
- /* Enable port 2 and 3 clocks*/
- setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
-
- /* Enable port 2 and 3 usb host ports tll clocks*/
- setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
- (OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
-#ifdef CONFIG_USB_XHCI_OMAP
- /* Enable the USB OTG Super speed clocks */
- setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
- (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW));
-#endif
-
- auxclk = readl((*prcm)->scrm_auxclk1);
- /* Request auxilary clock */
- auxclk |= AUXCLK_ENABLE_MASK;
- writel(auxclk, (*prcm)->scrm_auxclk1);
-}
-#endif
-
-/**
- * @brief misc_init_r - Configure EVM board specific configurations
- * such as power configurations, ethernet initialization as phase2 of
- * boot sequence
- *
- * @return 0
- */
-int misc_init_r(void)
-{
- int reg;
- u32 id[4];
-
-#ifdef CONFIG_PALMAS_POWER
- palmas_init_settings();
-#endif
-
- reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
-
- id[0] = readl(reg);
- id[1] = readl(reg + 0x8);
- id[2] = readl(reg + 0xC);
- id[3] = readl(reg + 0x10);
- usb_fake_mac_from_die_id(id);
-
- return 0;
-}
-
-void set_muxconf_regs_essential(void)
-{
- do_set_mux((*ctrl)->control_padconf_core_base,
- core_padconf_array_essential,
- sizeof(core_padconf_array_essential) /
- sizeof(struct pad_conf_entry));
-
- do_set_mux((*ctrl)->control_padconf_wkup_base,
- wkup_padconf_array_essential,
- sizeof(wkup_padconf_array_essential) /
- sizeof(struct pad_conf_entry));
-}
-
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
-int board_mmc_init(bd_t *bis)
-{
- omap_mmc_init(0, 0, 0, -1, -1);
- omap_mmc_init(1, 0, 0, -1, -1);
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_EHCI
-static struct omap_usbhs_board_data usbhs_bdata = {
- .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
- .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
- .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- int ret;
-
- enable_host_clocks();
-
- ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
- if (ret < 0) {
- puts("Failed to initialize ehci\n");
- return ret;
- }
-
- return 0;
-}
-
-int ehci_hcd_stop(void)
-{
- int ret;
-
- ret = omap_ehci_hcd_stop();
- return ret;
-}
-
-void usb_hub_reset_devices(int port)
-{
- /* The LAN9730 needs to be reset after the port power has been set. */
- if (port == 3) {
- gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
- udelay(10);
- gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
- }
-}
-#endif
-
-#ifdef CONFIG_USB_XHCI_OMAP
-/**
- * @brief board_usb_init - Configure EVM board specific configurations
- * for the LDO's and clocks for the USB blocks.
- *
- * @return 0
- */
-int board_usb_init(int index, enum usb_init_type init)
-{
- int ret;
-#ifdef CONFIG_PALMAS_USB_SS_PWR
- ret = palmas_enable_ss_ldo();
-#endif
-
- enable_host_clocks();
-
- return 0;
-}
-#endif
diff --git a/qemu/roms/u-boot/board/ti/omap5_uevm/mux_data.h b/qemu/roms/u-boot/board/ti/omap5_uevm/mux_data.h
deleted file mode 100644
index de7ce9fe0..000000000
--- a/qemu/roms/u-boot/board/ti/omap5_uevm/mux_data.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * Sricharan R <r.sricharan@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _EVM5430_MUX_DATA_H
-#define _EVM5430_MUX_DATA_H
-
-#include <asm/arch/mux_omap5.h>
-
-const struct pad_conf_entry core_padconf_array_essential[] = {
-
- {EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */
- {EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */
- {EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */
- {EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */
- {EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */
- {EMMC_DATA3, (PTU | IEN | M0)}, /* EMMC_DATA3 */
- {EMMC_DATA4, (PTU | IEN | M0)}, /* EMMC_DATA4 */
- {EMMC_DATA5, (PTU | IEN | M0)}, /* EMMC_DATA5 */
- {EMMC_DATA6, (PTU | IEN | M0)}, /* EMMC_DATA6 */
- {EMMC_DATA7, (PTU | IEN | M0)}, /* EMMC_DATA7 */
- {SDCARD_CLK, (PTU | IEN | M0)}, /* SDCARD_CLK */
- {SDCARD_CMD, (PTU | IEN | M0)}, /* SDCARD_CMD */
- {SDCARD_DATA0, (PTU | IEN | M0)}, /* SDCARD_DATA0*/
- {SDCARD_DATA1, (PTU | IEN | M0)}, /* SDCARD_DATA1*/
- {SDCARD_DATA2, (PTU | IEN | M0)}, /* SDCARD_DATA2*/
- {SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3*/
- {UART3_RX_IRRX, (PTU | IEN | M0)}, /* UART3_RX_IRRX */
- {UART3_TX_IRTX, (M0)}, /* UART3_TX_IRTX */
- {USBB1_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB1_HSIC_STROBE */
- {USBB1_HSIC_DATA, (PTU | IEN | M0)}, /* USBB1_HSIC_DATA */
- {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */
- {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */
- {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE*/
- {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */
- {USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */
- {USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */
- {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */
- {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */
- {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */
- {HSI2_ACWAKE, (PTU | M6)}, /* HSI2_ACWAKE */
- {HSI2_CAFLAG, (PTU | M6)}, /* HSI2_CAFLAG */
-};
-
-const struct pad_conf_entry wkup_padconf_array_essential[] = {
-
- {SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */
- {SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */
- {SYS_32K, (IEN | M0)}, /* SYS_32K */
- {FREF_CLK1_OUT, (PTD | IEN | M0)}, /* FREF_CLK1_OUT */
-
-};
-
-#endif /* _EVM4430_MUX_DATA_H */
diff --git a/qemu/roms/u-boot/board/ti/panda/Makefile b/qemu/roms/u-boot/board/ti/panda/Makefile
deleted file mode 100644
index c89f80d80..000000000
--- a/qemu/roms/u-boot/board/ti/panda/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := panda.o
diff --git a/qemu/roms/u-boot/board/ti/panda/panda.c b/qemu/roms/u-boot/board/ti/panda/panda.c
deleted file mode 100644
index 16368cbb0..000000000
--- a/qemu/roms/u-boot/board/ti/panda/panda.c
+++ /dev/null
@@ -1,323 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments Incorporated, <www.ti.com>
- * Steve Sakoman <steve@sakoman.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/gpio.h>
-
-#include "panda_mux_data.h"
-
-#ifdef CONFIG_USB_EHCI
-#include <usb.h>
-#include <asm/arch/ehci.h>
-#include <asm/ehci-omap.h>
-#endif
-
-#define PANDA_ULPI_PHY_TYPE_GPIO 182
-#define PANDA_BOARD_ID_1_GPIO 101
-#define PANDA_ES_BOARD_ID_1_GPIO 48
-#define PANDA_BOARD_ID_2_GPIO 171
-#define PANDA_ES_BOARD_ID_3_GPIO 3
-#define PANDA_ES_BOARD_ID_4_GPIO 2
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const struct omap_sysinfo sysinfo = {
- "Board: OMAP4 Panda\n"
-};
-
-struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
-
-/**
- * @brief board_init
- *
- * @return 0
- */
-int board_init(void)
-{
- gpmc_init();
-
- gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA;
- gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
-
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- return 0;
-}
-
-/*
-* Routine: get_board_revision
-* Description: Detect if we are running on a panda revision A1-A6,
-* or an ES panda board. This can be done by reading
-* the level of GPIOs and checking the processor revisions.
-* This should result in:
-* Panda 4430:
-* GPIO171, GPIO101, GPIO182: 0 1 1 => A1-A5
-* GPIO171, GPIO101, GPIO182: 1 0 1 => A6
-* Panda ES:
-* GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 => B1/B2
-* GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 => B3
-*/
-int get_board_revision(void)
-{
- int board_id0, board_id1, board_id2;
- int board_id3, board_id4;
- int board_id;
-
- int processor_rev = omap_revision();
-
- /* Setup the mux for the common board ID pins (gpio 171 and 182) */
- writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0);
- writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT);
-
- board_id0 = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
- board_id2 = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
-
- if ((processor_rev >= OMAP4460_ES1_0 &&
- processor_rev <= OMAP4460_ES1_1)) {
- /*
- * Setup the mux for the ES specific board ID pins (gpio 101,
- * 2 and 3.
- */
- writew((IEN | M3), (*ctrl)->control_padconf_core_base +
- GPMC_A24);
- writew((IEN | M3), (*ctrl)->control_padconf_core_base +
- UNIPRO_RY0);
- writew((IEN | M3), (*ctrl)->control_padconf_core_base +
- UNIPRO_RX1);
-
- board_id1 = gpio_get_value(PANDA_ES_BOARD_ID_1_GPIO);
- board_id3 = gpio_get_value(PANDA_ES_BOARD_ID_3_GPIO);
- board_id4 = gpio_get_value(PANDA_ES_BOARD_ID_4_GPIO);
-
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es"));
-#endif
- board_id = ((board_id4 << 4) | (board_id3 << 3) |
- (board_id2 << 2) | (board_id1 << 1) | (board_id0));
- } else {
- /* Setup the mux for the Ax specific board ID pins (gpio 101) */
- writew((IEN | M3), (*ctrl)->control_padconf_core_base +
- FREF_CLK2_OUT);
-
- board_id1 = gpio_get_value(PANDA_BOARD_ID_1_GPIO);
- board_id = ((board_id2 << 2) | (board_id1 << 1) | (board_id0));
-
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- if ((board_id >= 0x3) && (processor_rev == OMAP4430_ES2_3))
- setenv("board_name", strcat(CONFIG_SYS_BOARD, "-a4"));
-#endif
- }
-
- return board_id;
-}
-
-/**
- * is_panda_es_rev_b3() - Detect if we are running on rev B3 of panda board ES
- *
- *
- * Detect if we are running on B3 version of ES panda board,
- * This can be done by reading the level of GPIO 171 and checking the
- * processor revisions.
- * GPIO171: 1 => Panda ES Rev B3
- *
- * Return : return 1 if Panda ES Rev B3 , else return 0
- */
-u8 is_panda_es_rev_b3(void)
-{
- int processor_rev = omap_revision();
- int ret = 0;
-
- if ((processor_rev >= OMAP4460_ES1_0 &&
- processor_rev <= OMAP4460_ES1_1)) {
-
- /* Setup the mux for the common board ID pins (gpio 171) */
- writew((IEN | M3),
- (*ctrl)->control_padconf_core_base + UNIPRO_TX0);
-
- /* if processor_rev is panda ES and GPIO171 is 1,it is rev b3 */
- ret = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
- }
- return ret;
-}
-
-#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-/*
- * emif_get_reg_dump() - emif_get_reg_dump strong function
- *
- * @emif_nr - emif base
- * @regs - reg dump of timing values
- *
- * Strong function to override emif_get_reg_dump weak function in sdram_elpida.c
- */
-void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
-{
- u32 omap4_rev = omap_revision();
-
- /* Same devices and geometry on both EMIFs */
- if (omap4_rev == OMAP4430_ES1_0)
- *regs = &emif_regs_elpida_380_mhz_1cs;
- else if (omap4_rev == OMAP4430_ES2_0)
- *regs = &emif_regs_elpida_200_mhz_2cs;
- else if (omap4_rev == OMAP4430_ES2_3)
- *regs = &emif_regs_elpida_400_mhz_1cs;
- else if (omap4_rev < OMAP4470_ES1_0) {
- if(is_panda_es_rev_b3())
- *regs = &emif_regs_elpida_400_mhz_1cs;
- else
- *regs = &emif_regs_elpida_400_mhz_2cs;
- }
- else
- *regs = &emif_regs_elpida_400_mhz_1cs;
-}
-#endif
-
-/**
- * @brief misc_init_r - Configure Panda board specific configurations
- * such as power configurations, ethernet initialization as phase2 of
- * boot sequence
- *
- * @return 0
- */
-int misc_init_r(void)
-{
- int phy_type;
- u32 auxclk, altclksrc;
- u32 id[4];
-
- /* EHCI is not supported on ES1.0 */
- if (omap_revision() == OMAP4430_ES1_0)
- return 0;
-
- get_board_revision();
-
- gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
- phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
-
- if (phy_type == 1) {
- /* ULPI PHY supplied by auxclk3 derived from sys_clk */
- debug("ULPI PHY supplied by auxclk3\n");
-
- auxclk = readl(&scrm->auxclk3);
- /* Select sys_clk */
- auxclk &= ~AUXCLK_SRCSELECT_MASK;
- auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
- /* Set the divisor to 2 */
- auxclk &= ~AUXCLK_CLKDIV_MASK;
- auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
- /* Request auxilary clock #3 */
- auxclk |= AUXCLK_ENABLE_MASK;
-
- writel(auxclk, &scrm->auxclk3);
- } else {
- /* ULPI PHY supplied by auxclk1 derived from PER dpll */
- debug("ULPI PHY supplied by auxclk1\n");
-
- auxclk = readl(&scrm->auxclk1);
- /* Select per DPLL */
- auxclk &= ~AUXCLK_SRCSELECT_MASK;
- auxclk |= AUXCLK_SRCSELECT_PER_DPLL << AUXCLK_SRCSELECT_SHIFT;
- /* Set the divisor to 16 */
- auxclk &= ~AUXCLK_CLKDIV_MASK;
- auxclk |= AUXCLK_CLKDIV_16 << AUXCLK_CLKDIV_SHIFT;
- /* Request auxilary clock #3 */
- auxclk |= AUXCLK_ENABLE_MASK;
-
- writel(auxclk, &scrm->auxclk1);
- }
-
- altclksrc = readl(&scrm->altclksrc);
-
- /* Activate alternate system clock supplier */
- altclksrc &= ~ALTCLKSRC_MODE_MASK;
- altclksrc |= ALTCLKSRC_MODE_ACTIVE;
-
- /* enable clocks */
- altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
-
- writel(altclksrc, &scrm->altclksrc);
-
- id[0] = readl(STD_FUSE_DIE_ID_0);
- id[1] = readl(STD_FUSE_DIE_ID_1);
- id[2] = readl(STD_FUSE_DIE_ID_2);
- id[3] = readl(STD_FUSE_DIE_ID_3);
- usb_fake_mac_from_die_id(id);
-
- return 0;
-}
-
-void set_muxconf_regs_essential(void)
-{
- do_set_mux((*ctrl)->control_padconf_core_base,
- core_padconf_array_essential,
- sizeof(core_padconf_array_essential) /
- sizeof(struct pad_conf_entry));
-
- do_set_mux((*ctrl)->control_padconf_wkup_base,
- wkup_padconf_array_essential,
- sizeof(wkup_padconf_array_essential) /
- sizeof(struct pad_conf_entry));
-
- if (omap_revision() >= OMAP4460_ES1_0)
- do_set_mux((*ctrl)->control_padconf_wkup_base,
- wkup_padconf_array_essential_4460,
- sizeof(wkup_padconf_array_essential_4460) /
- sizeof(struct pad_conf_entry));
-}
-
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#ifdef CONFIG_USB_EHCI
-
-static struct omap_usbhs_board_data usbhs_bdata = {
- .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
- .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- int ret;
- unsigned int utmi_clk;
-
- /* Now we can enable our port clocks */
- utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
- utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
- setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk);
-
- ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
- if (ret < 0)
- return ret;
-
- return 0;
-}
-
-int ehci_hcd_stop(int index)
-{
- return omap_ehci_hcd_stop();
-}
-#endif
-
-/*
- * get_board_rev() - get board revision
- */
-u32 get_board_rev(void)
-{
- return 0x20;
-}
diff --git a/qemu/roms/u-boot/board/ti/panda/panda_mux_data.h b/qemu/roms/u-boot/board/ti/panda/panda_mux_data.h
deleted file mode 100644
index 53c708097..000000000
--- a/qemu/roms/u-boot/board/ti/panda/panda_mux_data.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * Balaji Krishnamoorthy <balajitk@ti.com>
- * Aneesh V <aneesh@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _PANDA_MUX_DATA_H_
-#define _PANDA_MUX_DATA_H_
-
-#include <asm/arch/mux_omap4.h>
-
-
-const struct pad_conf_entry core_padconf_array_essential[] = {
-
-{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
-{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
-{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
-{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
-{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
-{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
-{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
-{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
-{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
-{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
-{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */
-{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
-{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
-{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
-{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
-{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
-{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
-{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
-{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
-{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
-{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
-{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
-{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
-{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
-{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
-{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */
-{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */
-{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */
-{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
-{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
-{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */
-{UART3_TX_IRTX, (M0)}, /* uart3_tx */
-{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
-{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */
-{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */
-{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */
-{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */
-{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */
-{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */
-{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */
-{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
-{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
-{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */
-{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */
-{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */
-{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */
-{USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */
-{USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */
-{UNIPRO_TY2, (PTU | IEN | M3)}, /* gpio_1 */
-{GPMC_WAIT1, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_62 */
-{FREF_CLK2_OUT, (PTU | IEN | M3)}, /* gpio_182 */
-
-};
-
-const struct pad_conf_entry wkup_padconf_array_essential[] = {
-
-{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
-{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
-{PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */
-{PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
-
-};
-
-const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
-
-{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */
-
-};
-
-#endif /* _PANDA_MUX_DATA_H_ */
diff --git a/qemu/roms/u-boot/board/ti/sdp3430/Makefile b/qemu/roms/u-boot/board/ti/sdp3430/Makefile
deleted file mode 100644
index 753f09979..000000000
--- a/qemu/roms/u-boot/board/ti/sdp3430/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := sdp.o
diff --git a/qemu/roms/u-boot/board/ti/sdp3430/config.mk b/qemu/roms/u-boot/board/ti/sdp3430/config.mk
deleted file mode 100644
index e4d9be13e..000000000
--- a/qemu/roms/u-boot/board/ti/sdp3430/config.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# (C) Copyright 2006-2009
-# Texas Instruments Incorporated, <www.ti.com>
-#
-# OMAP 3430 SDP uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/qemu/roms/u-boot/board/ti/sdp3430/sdp.c b/qemu/roms/u-boot/board/ti/sdp3430/sdp.c
deleted file mode 100644
index 957940d53..000000000
--- a/qemu/roms/u-boot/board/ti/sdp3430/sdp.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * (C) Copyright 2004-2009
- * Texas Instruments Incorporated, <www.ti.com>
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <netdev.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-types.h>
-#include "sdp.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const omap3_sysinfo sysinfo = {
- DDR_DISCRETE,
- "OMAP3 SDP3430 board",
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
- "OneNAND",
-#elif defined(CONFIG_ENV_IS_IN_NAND)
- "NAND",
-#else
- "NOR",
-#endif
-};
-
-/* Timing definitions for GPMC controller for Sibley NOR */
-static const u32 gpmc_sdp_nor[] = {
- SDP3430_NOR_GPMC_CONF1,
- SDP3430_NOR_GPMC_CONF2,
- SDP3430_NOR_GPMC_CONF3,
- SDP3430_NOR_GPMC_CONF4,
- SDP3430_NOR_GPMC_CONF5,
- SDP3430_NOR_GPMC_CONF6,
- /*CONF7- computed as params */
-};
-
-/*
- * Timing definitions for GPMC controller for Debug Board
- * Debug board contains access to ethernet and DIP Switch setting
- * information etc.
- */
-static const u32 gpmc_sdp_debug[] = {
- SDP3430_DEBUG_GPMC_CONF1,
- SDP3430_DEBUG_GPMC_CONF2,
- SDP3430_DEBUG_GPMC_CONF3,
- SDP3430_DEBUG_GPMC_CONF4,
- SDP3430_DEBUG_GPMC_CONF5,
- SDP3430_DEBUG_GPMC_CONF6,
- /*CONF7- computed as params */
-};
-
-/* Timing defintions for GPMC OneNAND */
-static const u32 gpmc_sdp_onenand[] = {
- SDP3430_ONENAND_GPMC_CONF1,
- SDP3430_ONENAND_GPMC_CONF2,
- SDP3430_ONENAND_GPMC_CONF3,
- SDP3430_ONENAND_GPMC_CONF4,
- SDP3430_ONENAND_GPMC_CONF5,
- SDP3430_ONENAND_GPMC_CONF6,
- /*CONF7- computed as params */
-};
-
-/* GPMC definitions for GPMC NAND */
-static const u32 gpmc_sdp_nand[] = {
- SDP3430_NAND_GPMC_CONF1,
- SDP3430_NAND_GPMC_CONF2,
- SDP3430_NAND_GPMC_CONF3,
- SDP3430_NAND_GPMC_CONF4,
- SDP3430_NAND_GPMC_CONF5,
- SDP3430_NAND_GPMC_CONF6,
- /*CONF7- computed as params */
-};
-
-/* gpmc_cfg is initialized by gpmc_init and we use it here */
-extern struct gpmc *gpmc_cfg;
-
-/**
- * @brief board_init - gpmc and basic setup as phase1 of boot sequence
- *
- * @return 0
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* TODO: Dynamically pop out CS mapping and program accordingly */
- /* Configure devices for default ON ON ON settings */
- enable_gpmc_cs_config(gpmc_sdp_nor, &gpmc_cfg->cs[0],
- CONFIG_SYS_FLASH_BASE, GPMC_SIZE_128M);
- enable_gpmc_cs_config(gpmc_sdp_nand, &gpmc_cfg->cs[1], 0x28000000,
- GPMC_SIZE_16M);
- enable_gpmc_cs_config(gpmc_sdp_onenand, &gpmc_cfg->cs[2], 0x20000000,
- GPMC_SIZE_16M);
- enable_gpmc_cs_config(gpmc_sdp_debug, &gpmc_cfg->cs[3], DEBUG_BASE,
- GPMC_SIZE_16M);
- /* board id for Linux */
- gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430SDP;
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- return 0;
-}
-
-#define LAN_RESET_REGISTER (CONFIG_LAN91C96_BASE + 0x01c)
-#define ETH_CONTROL_REG (CONFIG_LAN91C96_BASE + 0x30b)
-
-/**
- * @brief board_eth_init Take the Ethernet controller out of reset and wait
- * for the EEPROM load to complete.
- */
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_LAN91C96
- int cnt = 20;
-
- writew(0x0, LAN_RESET_REGISTER);
- do {
- writew(0x1, LAN_RESET_REGISTER);
- udelay(100);
- if (cnt == 0)
- goto reset_err_out;
- --cnt;
- } while (readw(LAN_RESET_REGISTER) != 0x1);
-
- cnt = 20;
-
- do {
- writew(0x0, LAN_RESET_REGISTER);
- udelay(100);
- if (cnt == 0)
- goto reset_err_out;
- --cnt;
- } while (readw(LAN_RESET_REGISTER) != 0x0000);
- udelay(1000);
-
- writeb(readb(ETH_CONTROL_REG) & ~0x1, ETH_CONTROL_REG);
- udelay(1000);
- rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
-reset_err_out:
-
-#endif
- return rc;
-}
-
-/**
- * @brief misc_init_r - Configure SDP board specific configurations
- * such as power configurations, ethernet initialization as phase2 of
- * boot sequence
- *
- * @return 0
- */
-int misc_init_r(void)
-{
- /* Partial setup:
- * VAUX3 - 2.8V for DVI
- * VPLL1 - 1.8V
- * VDAC - 1.8V
- * and turns on LEDA/LEDB (not needed ... NOP?)
- */
- twl4030_power_init();
-
- /* FIXME finish setup:
- * VAUX1 - 2.8V for mainboard I/O
- * VAUX2 - 2.8V for camera
- * VAUX4 - 1.8V for OMAP3 CSI
- * VMMC1 - 3.15V (init, variable) for MMC1
- * VMMC2 - 1.85V for MMC2
- * VSIM - off (init, variable) for MMC1.DAT[3..7], SIM
- * VPLL2 - 1.8V
- */
-
- return 0;
-}
-
-/**
- * @brief set_muxconf_regs Setting up the configuration Mux registers
- * specific to the hardware. Many pins need to be moved from protect
- * to primary mode.
- */
-void set_muxconf_regs(void)
-{
- /* platform specific muxes */
- MUX_SDP3430();
-}
-
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
diff --git a/qemu/roms/u-boot/board/ti/sdp3430/sdp.h b/qemu/roms/u-boot/board/ti/sdp3430/sdp.h
deleted file mode 100644
index 2acb30259..000000000
--- a/qemu/roms/u-boot/board/ti/sdp3430/sdp.h
+++ /dev/null
@@ -1,401 +0,0 @@
-/*
- * (C) Copyright 2004-2009
- * Texas Instruments Incorporated
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _BOARD_SDP_H_
-#define _BOARD_SDP_H_
-
-#define OFF_IN_PD 0
-#define OFF_OUT_PD 0
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_SDP3430()\
- /*SDRC*/\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\
- /*GPMC*/\
- MUX_VAL(CP(GPMC_A1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_A10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D12), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D13), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D14), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_D15), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NCS0), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_NCS1), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_NCS2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_NCS3), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_NCS4), (OFF_IN_PD | IEN | PTU | EN | M4)) /*G55-F_DIS*/\
- MUX_VAL(CP(GPMC_NCS5), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G56T_EN*/\
- MUX_VAL(CP(GPMC_NCS6), (OFF_IN_PD | IEN | PTD | DIS | M4))/*G57-AGPSP*/\
- MUX_VAL(CP(GPMC_NCS7), (OFF_IN_PD | IEN | PTU | EN | M4))/*G58-WLNIQ*/\
- MUX_VAL(CP(GPMC_CLK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NADV_ALE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NOE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NWE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NBE0_CLE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_NBE1), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*G61-BTST*/\
- MUX_VAL(CP(GPMC_NWP), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(GPMC_WAIT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_WAIT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(GPMC_WAIT2), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_64*/\
- MUX_VAL(CP(GPMC_WAIT3), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_65*/\
- /*DSS*/\
- MUX_VAL(CP(DSS_PCLK), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_HSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_VSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_ACBIAS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA0), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA11), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA12), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA13), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA14), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA15), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA16), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA17), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA18), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA19), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA20), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA21), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA22), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA23), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- /*CAMERA*/\
- MUX_VAL(CP(CAM_HS), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(CAM_VS), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(CAM_XCLKA), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_PCLK), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(CAM_FLD), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G98-C_RST*/\
- MUX_VAL(CP(CAM_D0), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D0 */\
- MUX_VAL(CP(CAM_D1), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D1 */\
- MUX_VAL(CP(CAM_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_XCLKB), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(CAM_WEN), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*GPIO_167*/\
- MUX_VAL(CP(CAM_STROBE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(CSI2_DX0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CSI2_DY0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CSI2_DX1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(CSI2_DY1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- /*Audio InterfACe */\
- MUX_VAL(CP(MCBSP2_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP2_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP2_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP2_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- /*Expansion Card */\
- MUX_VAL(CP(MMC1_CLK), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT4), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT5), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT6), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC1_DAT7), (OFF_IN_PD | IEN | PTU | EN | M0))\
- /*Wireless LAN */\
- MUX_VAL(CP(MMC2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MMC2_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC2_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC2_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC2_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC2_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MMC2_DAT4), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD0*/\
- MUX_VAL(CP(MMC2_DAT5), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD1*/\
- MUX_VAL(CP(MMC2_DAT6), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DCMD*/\
- MUX_VAL(CP(MMC2_DAT7), (OFF_IN_PD | IEN | PTU | EN | M1))/*CLKIN*/\
- /*Bluetooth*/\
- MUX_VAL(CP(MCBSP3_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP3_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP3_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP3_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(UART2_CTS), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(UART2_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(UART2_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(UART2_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- /*Modem Interface */\
- MUX_VAL(CP(UART1_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(UART1_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(UART1_CTS), (OFF_IN_PD | IEN | PTU | DIS | M0))\
- MUX_VAL(CP(UART1_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP4_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1DRX*/\
- MUX_VAL(CP(MCBSP4_DR), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1FLGRX*/\
- MUX_VAL(CP(MCBSP4_DX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1RDYRX*/\
- MUX_VAL(CP(MCBSP4_FSX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1WAKE*/\
- MUX_VAL(CP(MCBSP1_CLKR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP1_FSR), (OFF_OUT_PD | IDIS | PTU | EN | M4))/*G157BWP*/\
- MUX_VAL(CP(MCBSP1_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP1_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP_CLKS), (OFF_IN_PD | IEN | PTU | DIS | M0))\
- MUX_VAL(CP(MCBSP1_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCBSP1_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- /*Serial Interface*/\
- MUX_VAL(CP(UART3_CTS_RCTX), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(UART3_RTS_SD), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(UART3_RX_IRRX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(UART3_TX_IRTX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_STP), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
- MUX_VAL(CP(HSUSB0_DIR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_NXT), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(HSUSB0_DATA7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- /* NOTE db: removed off-mode from I2C 1/2/3 ... external pullups!! */\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0))\
- MUX_VAL(CP(HDQ_SIO), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(MCSPI1_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCSPI1_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCSPI1_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCSPI1_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(MCSPI1_CS1), (OFF_OUT_PD | IDIS | PTD | EN | M0))\
- MUX_VAL(CP(MCSPI1_CS2), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G176*/\
- MUX_VAL(CP(MCSPI1_CS3), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(MCSPI2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCSPI2_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCSPI2_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(MCSPI2_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(MCSPI2_CS1), (OFF_IN_PD | IEN | PTD | EN | M0))\
- /*Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SYS_NIRQ), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(SYS_BOOT0), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G2PENIRQ*/\
- MUX_VAL(CP(SYS_BOOT1), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*GPIO_3 */\
- MUX_VAL(CP(SYS_BOOT2), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G4MMC1WP*/\
- MUX_VAL(CP(SYS_BOOT3), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G5LCDENV*/\
- MUX_VAL(CP(SYS_BOOT4), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G6LANINT*/\
- MUX_VAL(CP(SYS_BOOT5), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G7MMC2WP*/\
- MUX_VAL(CP(SYS_BOOT6), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G8ENBKL*/\
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M4))/*GPIO_186*/\
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\
- MUX_VAL(CP(JTAG_EMU0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(JTAG_EMU1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_CLK_ES2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
- MUX_VAL(CP(ETK_CTL_ES2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D0_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD0*/\
- MUX_VAL(CP(ETK_D1_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SPI3_CS0*/\
- MUX_VAL(CP(ETK_D2_ES2), (OFF_IN_PD | IEN | PTD | EN | M1))/*USB1TLD2*/\
- MUX_VAL(CP(ETK_D3_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD7*/\
- MUX_VAL(CP(ETK_D4_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D5_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D6_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D7_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D8_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D9_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D10_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D11_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D12_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D13_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D14_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(ETK_D15_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- /*Die to Die */\
- MUX_VAL(CP(D2D_MCAD0), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD1), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD2), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD3), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD4), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD5), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD6), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD7), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD8), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD9), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD10), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD11), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD12), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD13), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD14), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD15), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD16), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD17), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD18), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD19), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD20), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD21), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD22), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD23), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD24), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD25), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD26), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD27), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD28), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD29), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD30), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD31), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD32), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD33), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD34), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD35), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_MCAD36), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_CLK26MI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_NRESPWRON), (OFF_OUT_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_NRESWARM), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(D2D_ARM9NIRQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_UMA2P6FIQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_SPINT), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_FRINT), (OFF_IN_PD | IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_DMAREQ0), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_DMAREQ1), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_DMAREQ2), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_DMAREQ3), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GTRST), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GTDI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GTDO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GTMS), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GTCK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_N3GRTCK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_MSTDBY), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\
- MUX_VAL(CP(D2D_IDLEREQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_IDLEACK), (OFF_IN_PD | IEN | PTU | EN | M0))\
- MUX_VAL(CP(D2D_MWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_SWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_MREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_SREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_MBUSFLAG), (OFF_IN_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(D2D_SBUSFLAG), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0))\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*SDRC_CKE1 NOT USED*/
-
-/*
- * GPMC Timing definitions for SDP3430
- * at L3 = 166Mhz
- */
-
-/* Timing definitions for GPMC controller for Sibley NOR */
-#define SDP3430_NOR_GPMC_CONF1 0x00001200
-#define SDP3430_NOR_GPMC_CONF2 0x001F1F00
-#define SDP3430_NOR_GPMC_CONF3 0x00080802
-#define SDP3430_NOR_GPMC_CONF4 0x1C091C09
-#define SDP3430_NOR_GPMC_CONF5 0x01131F1F
-#define SDP3430_NOR_GPMC_CONF6 0x1F0F03C2
-
-/*
- * Timing definitions for GPMC controller for Debug Board
- * Debug board contains access to ethernet and DIP Switch setting
- * information etc.
- */
-#define SDP3430_DEBUG_GPMC_CONF1 0x00611200
-#define SDP3430_DEBUG_GPMC_CONF2 0x001F1F01
-#define SDP3430_DEBUG_GPMC_CONF3 0x00080803
-#define SDP3430_DEBUG_GPMC_CONF4 0x1D091D09
-#define SDP3430_DEBUG_GPMC_CONF5 0x041D1F1F
-#define SDP3430_DEBUG_GPMC_CONF6 0x1D0904C4
-
-/* Timing defintions for GPMC OneNAND */
-#define SDP3430_ONENAND_GPMC_CONF1 0x00001200
-#define SDP3430_ONENAND_GPMC_CONF2 0x000F0F01
-#define SDP3430_ONENAND_GPMC_CONF3 0x00030301
-#define SDP3430_ONENAND_GPMC_CONF4 0x0F040F04
-#define SDP3430_ONENAND_GPMC_CONF5 0x010F1010
-#define SDP3430_ONENAND_GPMC_CONF6 0x1F060000
-
-/* GPMC definitions for GPMC NAND */
-#define SDP3430_NAND_GPMC_CONF1 0x00000800
-#define SDP3430_NAND_GPMC_CONF2 0x00141400
-#define SDP3430_NAND_GPMC_CONF3 0x00141400
-#define SDP3430_NAND_GPMC_CONF4 0x0F010F01
-#define SDP3430_NAND_GPMC_CONF5 0x010C1414
-#define SDP3430_NAND_GPMC_CONF6 0x1F040A80
-
-#endif /* _BOARD_SDP_H_ */
diff --git a/qemu/roms/u-boot/board/ti/sdp4430/Makefile b/qemu/roms/u-boot/board/ti/sdp4430/Makefile
deleted file mode 100644
index 79e67b6e9..000000000
--- a/qemu/roms/u-boot/board/ti/sdp4430/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := sdp.o
-
-ifndef CONFIG_SPL_BUILD
-obj-y += cmd_bat.o
-endif
diff --git a/qemu/roms/u-boot/board/ti/sdp4430/cmd_bat.c b/qemu/roms/u-boot/board/ti/sdp4430/cmd_bat.c
deleted file mode 100644
index 7e8dbb1b0..000000000
--- a/qemu/roms/u-boot/board/ti/sdp4430/cmd_bat.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2010 Texas Instruments
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-
-#ifdef CONFIG_CMD_BAT
-#include <twl6030.h>
-
-int do_vbat(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if (argc == 2) {
- if (strncmp(argv[1], "startcharge", 12) == 0)
- twl6030_start_usb_charging();
- else if (strncmp(argv[1], "stopcharge", 11) == 0)
- twl6030_stop_usb_charging();
- else if (strncmp(argv[1], "status", 7) == 0) {
- twl6030_get_battery_voltage();
- twl6030_get_battery_current();
- } else {
- goto bat_cmd_usage;
- }
- } else {
- goto bat_cmd_usage;
- }
- return 0;
-
-bat_cmd_usage:
- return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD(
- bat, 2, 1, do_vbat,
- "battery charging, voltage/current measurements",
- "status - display battery voltage and current\n"
- "bat startcharge - start charging via USB\n"
- "bat stopcharge - stop charging\n"
-);
-#endif /* CONFIG_BAT_CMD */
diff --git a/qemu/roms/u-boot/board/ti/sdp4430/sdp.c b/qemu/roms/u-boot/board/ti/sdp4430/sdp.c
deleted file mode 100644
index 1e9ef9e38..000000000
--- a/qemu/roms/u-boot/board/ti/sdp4430/sdp.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments Incorporated, <www.ti.com>
- * Aneesh V <aneesh@ti.com>
- * Steve Sakoman <steve@sakoman.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <twl6030.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mmc_host_def.h>
-
-#include "sdp4430_mux_data.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const struct omap_sysinfo sysinfo = {
- "Board: OMAP4430 SDP\n"
-};
-
-/**
- * @brief board_init
- *
- * @return 0
- */
-int board_init(void)
-{
- gpmc_init();
-
- gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
-
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- return 0;
-}
-
-/**
- * @brief misc_init_r - Configure SDP board specific configurations
- * such as power configurations, ethernet initialization as phase2 of
- * boot sequence
- *
- * @return 0
- */
-int misc_init_r(void)
-{
-#ifdef CONFIG_TWL6030_POWER
- twl6030_init_battery_charging();
-#endif
- return 0;
-}
-
-void set_muxconf_regs_essential(void)
-{
- do_set_mux((*ctrl)->control_padconf_core_base,
- core_padconf_array_essential,
- sizeof(core_padconf_array_essential) /
- sizeof(struct pad_conf_entry));
-
- do_set_mux((*ctrl)->control_padconf_wkup_base,
- wkup_padconf_array_essential,
- sizeof(wkup_padconf_array_essential) /
- sizeof(struct pad_conf_entry));
-
- if ((omap_revision() >= OMAP4460_ES1_0) &&
- (omap_revision() < OMAP4470_ES1_0))
- do_set_mux((*ctrl)->control_padconf_wkup_base,
- wkup_padconf_array_essential_4460,
- sizeof(wkup_padconf_array_essential_4460) /
- sizeof(struct pad_conf_entry));
-}
-
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
-int board_mmc_init(bd_t *bis)
-{
- omap_mmc_init(0, 0, 0, -1, -1);
- omap_mmc_init(1, 0, 0, -1, -1);
- return 0;
-}
-#endif
-
-/*
- * get_board_rev() - get board revision
- */
-u32 get_board_rev(void)
-{
- return 0x20;
-}
diff --git a/qemu/roms/u-boot/board/ti/sdp4430/sdp4430_mux_data.h b/qemu/roms/u-boot/board/ti/sdp4430/sdp4430_mux_data.h
deleted file mode 100644
index 9a9efe7a5..000000000
--- a/qemu/roms/u-boot/board/ti/sdp4430/sdp4430_mux_data.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * Balaji Krishnamoorthy <balajitk@ti.com>
- * Aneesh V <aneesh@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _SDP4430_MUX_DATA_H
-#define _SDP4430_MUX_DATA_H
-
-#include <asm/arch/mux_omap4.h>
-
-const struct pad_conf_entry core_padconf_array_essential[] = {
-
-{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
-{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
-{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
-{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
-{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
-{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
-{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
-{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
-{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
-{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
-{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */
-{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
-{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
-{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
-{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
-{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
-{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
-{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
-{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
-{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
-{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
-{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
-{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */
-{UART3_TX_IRTX, (M0)}, /* uart3_tx */
-{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
-{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
-{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */
-{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */
-{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */
-{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */
-{USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */
-{USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */
-{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */
-{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */
-{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */
-};
-
-const struct pad_conf_entry wkup_padconf_array_essential[] = {
-
-{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
-{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
-{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */
-
-};
-
-const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
-
-{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */
-
-};
-
-#endif /* _SDP4430_MUX_DATA_H */
diff --git a/qemu/roms/u-boot/board/ti/ti814x/Makefile b/qemu/roms/u-boot/board/ti/ti814x/Makefile
deleted file mode 100644
index 93155de53..000000000
--- a/qemu/roms/u-boot/board/ti/ti814x/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Makefile
-#
-# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-y := mux.o
-endif
-
-obj-y += evm.o
diff --git a/qemu/roms/u-boot/board/ti/ti814x/evm.c b/qemu/roms/u-boot/board/ti/ti814x/evm.c
deleted file mode 100644
index 54b3dfb82..000000000
--- a/qemu/roms/u-boot/board/ti/ti814x/evm.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * evm.c
- *
- * Board functions for TI814x EVM
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <cpsw.h>
-#include <errno.h>
-#include <spl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include "evm.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-/* UART Defines */
-#ifdef CONFIG_SPL_BUILD
-static const struct cmd_control evm_ddr2_cctrl_data = {
- .cmd0csratio = 0x80,
- .cmd0iclkout = 0x00,
-
- .cmd1csratio = 0x80,
- .cmd1iclkout = 0x00,
-
- .cmd2csratio = 0x80,
- .cmd2iclkout = 0x00,
-};
-
-static const struct emif_regs evm_ddr2_emif0_regs = {
- .sdram_config = 0x40801ab2,
- .ref_ctrl = 0x10000c30,
- .sdram_tim1 = 0x0aaaf552,
- .sdram_tim2 = 0x043631d2,
- .sdram_tim3 = 0x00000327,
- .emif_ddr_phy_ctlr_1 = 0x00000007
-};
-
-static const struct emif_regs evm_ddr2_emif1_regs = {
- .sdram_config = 0x40801ab2,
- .ref_ctrl = 0x10000c30,
- .sdram_tim1 = 0x0aaaf552,
- .sdram_tim2 = 0x043631d2,
- .sdram_tim3 = 0x00000327,
- .emif_ddr_phy_ctlr_1 = 0x00000007
-};
-
-const struct dmm_lisa_map_regs evm_lisa_map_regs = {
- .dmm_lisa_map_0 = 0x00000000,
- .dmm_lisa_map_1 = 0x00000000,
- .dmm_lisa_map_2 = 0x806c0300,
- .dmm_lisa_map_3 = 0x806c0300,
-};
-
-static const struct ddr_data evm_ddr2_data = {
- .datardsratio0 = ((0x35<<10) | (0x35<<0)),
- .datawdsratio0 = ((0x20<<10) | (0x20<<0)),
- .datawiratio0 = ((0<<10) | (0<<0)),
- .datagiratio0 = ((0<<10) | (0<<0)),
- .datafwsratio0 = ((0x90<<10) | (0x90<<0)),
- .datawrsratio0 = ((0x50<<10) | (0x50<<0)),
-};
-
-void set_uart_mux_conf(void)
-{
- /* Set UART pins */
- enable_uart0_pin_mux();
-}
-
-void set_mux_conf_regs(void)
-{
- /* Set MMC pins */
- enable_mmc1_pin_mux();
-
- /* Set Ethernet pins */
- enable_enet_pin_mux();
-}
-
-void sdram_init(void)
-{
- config_dmm(&evm_lisa_map_regs);
-
- config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
- &evm_ddr2_emif0_regs, 0);
- config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
- &evm_ddr2_emif1_regs, 1);
-}
-#endif
-
-/*
- * Basic board specific setup. Pinmux has been handled already.
- */
-int board_init(void)
-{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- return 0;
-}
-
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
-int board_mmc_init(bd_t *bis)
-{
- omap_mmc_init(1, 0, 0, -1, -1);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
-
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x50,
- .sliver_reg_ofs = 0x700,
- .phy_addr = 1,
- },
- {
- .slave_reg_ofs = 0x90,
- .sliver_reg_ofs = 0x740,
- .phy_addr = 0,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x100,
- .slaves = 1,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0x600,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x28,
- .hw_stats_reg_ofs = 0x400,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_1,
-};
-#endif
-
-int board_eth_init(bd_t *bis)
-{
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
-
- if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
- printf("<ethaddr> not set. Reading from E-fuse\n");
- /* try reading mac address from efuse */
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (is_valid_ether_addr(mac_addr))
- eth_setenv_enetaddr("ethaddr", mac_addr);
- else
- printf("Unable to read MAC address. Set <ethaddr>\n");
- }
-
- return cpsw_register(&cpsw_data);
-}
diff --git a/qemu/roms/u-boot/board/ti/ti814x/evm.h b/qemu/roms/u-boot/board/ti/ti814x/evm.h
deleted file mode 100644
index 6aebec62d..000000000
--- a/qemu/roms/u-boot/board/ti/ti814x/evm.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _EVM_H
-#define _EVM_H
-
-void enable_uart0_pin_mux(void);
-void enable_mmc1_pin_mux(void);
-void enable_enet_pin_mux(void);
-
-#endif /* _EVM_H */
diff --git a/qemu/roms/u-boot/board/ti/ti814x/mux.c b/qemu/roms/u-boot/board/ti/ti814x/mux.c
deleted file mode 100644
index fd9f36451..000000000
--- a/qemu/roms/u-boot/board/ti/ti814x/mux.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * mux.c
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include <i2c.h>
-#include "evm.h"
-
-static struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(pincntl70), PULLUP_EN | MODE(0x01)}, /* UART0_RXD */
- {OFFSET(pincntl71), PULLUP_EN | MODE(0x01)}, /* UART0_TXD */
- {-1},
-};
-
-static struct module_pin_mux mmc1_pin_mux[] = {
- {OFFSET(pincntl1), PULLUP_EN | MODE(0x01)}, /* SD1_CLK */
- {OFFSET(pincntl2), PULLUP_EN | MODE(0x01)}, /* SD1_CMD */
- {OFFSET(pincntl3), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[0] */
- {OFFSET(pincntl4), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[1] */
- {OFFSET(pincntl5), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[2] */
- {OFFSET(pincntl6), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[3] */
- {OFFSET(pincntl74), PULLUP_EN | MODE(0x40)}, /* SD1_POW */
- {OFFSET(pincntl75), MODE(0x40)}, /* SD1_SDWP */
- {OFFSET(pincntl80), PULLUP_EN | MODE(0x02)}, /* SD1_SDCD */
- {-1},
-};
-
-static struct module_pin_mux enet_pin_mux[] = {
- {OFFSET(pincntl232), MODE(0x01)}, /* EMAC_RMREFCLK */
- {OFFSET(pincntl233), PULLUP_EN | MODE(0x01)}, /* MDCLK */
- {OFFSET(pincntl234), PULLUP_EN | MODE(0x01)}, /* MDIO */
- {OFFSET(pincntl235), MODE(0x01)}, /* EMAC[0]_MTCLK */
- {OFFSET(pincntl236), MODE(0x01)}, /* EMAC[0]_MCOL */
- {OFFSET(pincntl237), MODE(0x01)}, /* EMAC[0]_MCRS */
- {OFFSET(pincntl238), MODE(0x01)}, /* EMAC[0]_MRXER */
- {OFFSET(pincntl239), MODE(0x01)}, /* EMAC[0]_MRCLK */
- {OFFSET(pincntl240), MODE(0x01)}, /* EMAC[0]_MRXD[0] */
- {OFFSET(pincntl241), MODE(0x01)}, /* EMAC[0]_MRXD[1] */
- {OFFSET(pincntl242), MODE(0x01)}, /* EMAC[0]_MRXD[2] */
- {OFFSET(pincntl243), MODE(0x01)}, /* EMAC[0]_MRXD[3] */
- {OFFSET(pincntl244), MODE(0x01)}, /* EMAC[0]_MRXD[4] */
- {OFFSET(pincntl245), MODE(0x01)}, /* EMAC[0]_MRXD[5] */
- {OFFSET(pincntl246), MODE(0x01)}, /* EMAC[0]_MRXD[6] */
- {OFFSET(pincntl247), MODE(0x01)}, /* EMAC[0]_MRXD[7] */
- {OFFSET(pincntl248), MODE(0x01)}, /* EMAC[0]_MRXDV */
- {OFFSET(pincntl249), MODE(0x01)}, /* EMAC[0]_GMTCLK */
- {OFFSET(pincntl250), MODE(0x01)}, /* EMAC[0]_MTXD[0] */
- {OFFSET(pincntl251), MODE(0x01)}, /* EMAC[0]_MTXD[1] */
- {OFFSET(pincntl252), MODE(0x01)}, /* EMAC[0]_MTXD[2] */
- {OFFSET(pincntl253), MODE(0x01)}, /* EMAC[0]_MTXD[3] */
- {OFFSET(pincntl254), MODE(0x01)}, /* EMAC[0]_MTXD[4] */
- {OFFSET(pincntl255), MODE(0x01)}, /* EMAC[0]_MTXD[5] */
- {OFFSET(pincntl256), MODE(0x01)}, /* EMAC[0]_MTXD[6] */
- {OFFSET(pincntl257), MODE(0x01)}, /* EMAC[0]_MTXD[7] */
- {OFFSET(pincntl258), MODE(0x01)}, /* EMAC[0]_MTXEN */
-};
-
-void enable_uart0_pin_mux(void)
-{
- configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_mmc1_pin_mux(void)
-{
- configure_module_pin_mux(mmc1_pin_mux);
-}
-
-void enable_enet_pin_mux(void)
-{
- configure_module_pin_mux(enet_pin_mux);
-}
diff --git a/qemu/roms/u-boot/board/ti/ti816x/Makefile b/qemu/roms/u-boot/board/ti/ti816x/Makefile
deleted file mode 100644
index f1cc3d561..000000000
--- a/qemu/roms/u-boot/board/ti/ti816x/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
-# Antoine Tenart, <atenart@adeneo-embedded.com>
-#
-# Based on TI-PSP-04.00.02.14 :
-#
-# Copyright (C) 2009, Texas Instruments, Incorporated
-#
-# SPDX-License-Identifier: GPL-2.0
-#
-
-obj-y := evm.o
diff --git a/qemu/roms/u-boot/board/ti/ti816x/evm.c b/qemu/roms/u-boot/board/ti/ti816x/evm.c
deleted file mode 100644
index b6bf16236..000000000
--- a/qemu/roms/u-boot/board/ti/ti816x/evm.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * evm.c
- *
- * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
- * Antoine Tenart, <atenart@adeneo-embedded.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <asm/cache.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-
-static struct module_pin_mux mmc_pin_mux[] = {
- { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
- { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
- { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
- { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
- { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
- { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
- { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
- { -1 },
-};
-
-const struct dmm_lisa_map_regs evm_lisa_map_regs = {
- .dmm_lisa_map_0 = 0x00000000,
- .dmm_lisa_map_1 = 0x00000000,
- .dmm_lisa_map_2 = 0x80640300,
- .dmm_lisa_map_3 = 0xC0640320,
-};
-
-/*
- * DDR2 related definitions
- */
-#ifdef CONFIG_TI816X_EVM_DDR2
-static struct ddr_data ddr2_data = {
- .datardsratio0 = ((0x40<<10) | (0x40<<0)),
- .datawdsratio0 = ((0x4A<<10) | (0x4A<<0)),
- .datawiratio0 = ((0x0<<10) | (0x0<<0)),
- .datagiratio0 = ((0x0<<10) | (0x0<<0)),
- .datafwsratio0 = ((0x13A<<10) | (0x13A<<0)),
- .datawrsratio0 = ((0x8A<<10) | (0x8A<<0)),
-};
-
-static struct cmd_control ddr2_ctrl = {
- .cmd0csratio = 0x80,
- .cmd0iclkout = 0x00,
-
- .cmd1csratio = 0x80,
- .cmd1iclkout = 0x00,
-
- .cmd2csratio = 0x80,
- .cmd2iclkout = 0x00,
-
-};
-
-static struct emif_regs ddr2_emif0_regs = {
- .sdram_config = 0x43801A3A,
- .ref_ctrl = 0x10000C30,
- .sdram_tim1 = 0x0AAB15E2,
- .sdram_tim2 = 0x423631D2,
- .sdram_tim3 = 0x0080032F,
- .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */
-};
-
-static struct emif_regs ddr2_emif1_regs = {
- .sdram_config = 0x43801A3A,
- .ref_ctrl = 0x10000C30,
- .sdram_tim1 = 0x0AAB15E2,
- .sdram_tim2 = 0x423631D2,
- .sdram_tim3 = 0x0080032F,
- .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */
-};
-#endif
-
-/*
- * DDR3 related definitions
- */
-
-#if defined(CONFIG_TI816X_DDR_PLL_400)
-#define RD_DQS 0x03B
-#define WR_DQS 0x0A6
-#define RD_DQS_GATE 0x12A
-#define EMIF_SDCFG 0x62A41032
-#define EMIF_SDREF 0x10000C30
-#define EMIF_TIM1 0x0CCCE524
-#define EMIF_TIM2 0x30308023
-#define EMIF_TIM3 0x009F82CF
-#define EMIF_PHYCFG 0x0000010B
-#elif defined(CONFIG_TI816X_DDR_PLL_531)
-#define RD_DQS 0x039
-#define WR_DQS 0x0B4
-#define RD_DQS_GATE 0x13D
-#define EMIF_SDCFG 0x62A51832
-#define EMIF_SDREF 0x1000102E
-#define EMIF_TIM1 0x0EF136AC
-#define EMIF_TIM2 0x30408063
-#define EMIF_TIM3 0x009F83AF
-#define EMIF_PHYCFG 0x0000010C
-#elif defined(CONFIG_TI816X_DDR_PLL_675)
-#define RD_DQS 0x039
-#define WR_DQS 0x091
-#define RD_DQS_GATE 0x196
-#define EMIF_SDCFG 0x62A63032
-#define EMIF_SDREF 0x10001491
-#define EMIF_TIM1 0x13358875
-#define EMIF_TIM2 0x5051806C
-#define EMIF_TIM3 0x009F84AF
-#define EMIF_PHYCFG 0x0000010F
-#elif defined(CONFIG_TI816X_DDR_PLL_796)
-#define RD_DQS 0x035
-#define WR_DQS 0x093
-#define RD_DQS_GATE 0x1B3
-#define EMIF_SDCFG 0x62A73832
-#define EMIF_SDREF 0x10001841
-#define EMIF_TIM1 0x1779C9FE
-#define EMIF_TIM2 0x50608074
-#define EMIF_TIM3 0x009F857F
-#define EMIF_PHYCFG 0x00000110
-#endif
-
-static struct ddr_data ddr3_data = {
- .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)),
- .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)),
- .datawiratio0 = ((0x20<<10) | 0x20<<0),
- .datagiratio0 = ((0x20<<10) | 0x20<<0),
- .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
- .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
-};
-
-static const struct cmd_control ddr3_ctrl = {
- .cmd0csratio = 0x100,
- .cmd0iclkout = 0x001,
-
- .cmd1csratio = 0x100,
- .cmd1iclkout = 0x001,
-
- .cmd2csratio = 0x100,
- .cmd2iclkout = 0x001,
-};
-
-static const struct emif_regs ddr3_emif0_regs = {
- .sdram_config = EMIF_SDCFG,
- .ref_ctrl = EMIF_SDREF,
- .sdram_tim1 = EMIF_TIM1,
- .sdram_tim2 = EMIF_TIM2,
- .sdram_tim3 = EMIF_TIM3,
- .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
-};
-
-static const struct emif_regs ddr3_emif1_regs = {
- .sdram_config = EMIF_SDCFG,
- .ref_ctrl = EMIF_SDREF,
- .sdram_tim1 = EMIF_TIM1,
- .sdram_tim2 = EMIF_TIM2,
- .sdram_tim3 = EMIF_TIM3,
- .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
-};
-
-void set_uart_mux_conf(void) {}
-
-void set_mux_conf_regs(void)
-{
- configure_module_pin_mux(mmc_pin_mux);
-}
-
-void sdram_init(void)
-{
- config_dmm(&evm_lisa_map_regs);
-
-#ifdef CONFIG_TI816X_EVM_DDR2
- if (CONFIG_TI816X_USE_EMIF0) {
- ddr2_emif0_regs.emif_ddr_phy_ctlr_1 =
- (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
- config_ddr(0, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs,
- 0);
- }
-
- if (CONFIG_TI816X_USE_EMIF1) {
- ddr2_emif1_regs.emif_ddr_phy_ctlr_1 =
- (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
- config_ddr(1, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs,
- 1);
- }
-#endif
-
-#ifdef CONFIG_TI816X_EVM_DDR3
- if (CONFIG_TI816X_USE_EMIF0)
- config_ddr(0, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs,
- 0);
-
- if (CONFIG_TI816X_USE_EMIF1)
- config_ddr(1, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs,
- 1);
-#endif
-}
-#endif /* CONFIG_SPL_BUILD */
diff --git a/qemu/roms/u-boot/board/ti/tnetv107xevm/Makefile b/qemu/roms/u-boot/board/ti/tnetv107xevm/Makefile
deleted file mode 100644
index 0a6128f85..000000000
--- a/qemu/roms/u-boot/board/ti/tnetv107xevm/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += sdb_board.o
diff --git a/qemu/roms/u-boot/board/ti/tnetv107xevm/config.mk b/qemu/roms/u-boot/board/ti/tnetv107xevm/config.mk
deleted file mode 100644
index 51c2886b3..000000000
--- a/qemu/roms/u-boot/board/ti/tnetv107xevm/config.mk
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0x83FC0000
diff --git a/qemu/roms/u-boot/board/ti/tnetv107xevm/sdb_board.c b/qemu/roms/u-boot/board/ti/tnetv107xevm/sdb_board.c
deleted file mode 100644
index a95434b5e..000000000
--- a/qemu/roms/u-boot/board/ti/tnetv107xevm/sdb_board.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * TNETV107X-EVM: Board initialization
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <linux/mtd/nand.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clock.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
-#include <asm/arch/nand_defs.h>
-#include <asm/arch/mux.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = {
- { /* CS0 */
- .mode = ASYNC_EMIF_MODE_NAND,
- .wr_setup = 5,
- .wr_strobe = 5,
- .wr_hold = 2,
- .rd_setup = 5,
- .rd_strobe = 5,
- .rd_hold = 2,
- .turn_around = 5,
- .width = ASYNC_EMIF_8,
- },
- { /* CS1 */
- .mode = ASYNC_EMIF_MODE_NOR,
- .wr_setup = 2,
- .wr_strobe = 27,
- .wr_hold = 4,
- .rd_setup = 2,
- .rd_strobe = 27,
- .rd_hold = 4,
- .turn_around = 2,
- .width = ASYNC_EMIF_PRESERVE,
- },
- { /* CS2 */
- .mode = ASYNC_EMIF_MODE_NOR,
- .wr_setup = 2,
- .wr_strobe = 27,
- .wr_hold = 4,
- .rd_setup = 2,
- .rd_strobe = 27,
- .rd_hold = 4,
- .turn_around = 2,
- .width = ASYNC_EMIF_PRESERVE,
- },
- { /* CS3 */
- .mode = ASYNC_EMIF_MODE_NOR,
- .wr_setup = 1,
- .wr_strobe = 90,
- .wr_hold = 3,
- .rd_setup = 1,
- .rd_strobe = 26,
- .rd_hold = 3,
- .turn_around = 1,
- .width = ASYNC_EMIF_8,
- },
-};
-
-static struct pll_init_data pll_config[] = {
- {
- .pll = ETH_PLL,
- .internal_osc = 1,
- .pll_freq = 500000000,
- .div_freq = {
- 5000000, 50000000, 125000000, 250000000, 25000000,
- },
- },
-};
-
-static const short sdio1_pins[] = {
- TNETV107X_PIN_SDIO1_CLK_1, TNETV107X_PIN_SDIO1_CMD_1,
- TNETV107X_PIN_SDIO1_DATA0_1, TNETV107X_PIN_SDIO1_DATA1_1,
- TNETV107X_PIN_SDIO1_DATA2_1, TNETV107X_PIN_SDIO1_DATA3_1,
- -1
-};
-
-static const short uart1_pins[] = {
- TNETV107X_PIN_UART1_RD, TNETV107X_PIN_UART1_TD, -1
-};
-
-static const short ssp_pins[] = {
- TNETV107X_PIN_SSP0_0, TNETV107X_PIN_SSP0_1, TNETV107X_PIN_SSP0_2,
- TNETV107X_PIN_SSP1_0, TNETV107X_PIN_SSP1_1, TNETV107X_PIN_SSP1_2,
- TNETV107X_PIN_SSP1_3, -1
-};
-
-int board_init(void)
-{
-#ifndef CONFIG_USE_IRQ
- __raw_writel(0, INTC_GLB_EN); /* Global disable */
- __raw_writel(0, INTC_HINT_EN); /* Disable host ints */
- __raw_writel(0, INTC_EN_CLR0 + 0); /* Clear enable */
- __raw_writel(0, INTC_EN_CLR0 + 4); /* Clear enable */
- __raw_writel(0, INTC_EN_CLR0 + 8); /* Clear enable */
-#endif
-
- gd->bd->bi_arch_number = MACH_TYPE_TNETV107X;
- gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
- init_plls(ARRAY_SIZE(pll_config), pll_config);
-
- init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config);
-
- mux_select_pin(TNETV107X_PIN_ASR_CS3);
- mux_select_pins(sdio1_pins);
- mux_select_pins(uart1_pins);
- mux_select_pins(ssp_pins);
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
-}
-
-#ifdef CONFIG_NAND_DAVINCI
-int board_nand_init(struct nand_chip *nand)
-{
- davinci_nand_init(nand);
-
- return 0;
-}
-#endif