15 files changed, 0 insertions, 1140 deletions

diff --git a/qemu/roms/u-boot/board/spear/common/Makefile b/qemu/roms/u-boot/board/spear/common/Makefile
deleted file mode 100644
index b0ba32048..000000000
--- a/qemu/roms/u-boot/board/spear/common/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-# necessary to create built-in.o
-obj- := __dummy__.o
-else
-obj-y	:= spr_misc.o
-obj-y	+= spr_lowlevel_init.o
-endif
diff --git a/qemu/roms/u-boot/board/spear/common/spr_lowlevel_init.S b/qemu/roms/u-boot/board/spear/common/spr_lowlevel_init.S
deleted file mode 100644
index 23a0369cb..000000000
--- a/qemu/roms/u-boot/board/spear/common/spr_lowlevel_init.S
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * (C) Copyright 2006
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-
-/*
- * platform specific initializations are already done in Xloader
- * Initializations already done include
- * DDR, PLLs, IP's clock enable and reset release etc
- */
-.globl lowlevel_init
-lowlevel_init:
-	/* By default, U-Boot switches CPU to low-vector */
-	/* Revert this as we work in high vector even in U-Boot */
-	mrc	p15, 0, r0, c1, c0, 0
-	orr	r0, r0, #0x00002000
-	mcr	p15, 0, r0, c1, c0, 0
-	mov	pc, lr
-
-/* void setfreq(unsigned int device, unsigned int frequency) */
-.global setfreq
-setfreq:
-	stmfd 	sp!,{r14}
-	stmfd 	sp!,{r0-r12}
-
-	mov  	r8,sp
-	ldr 	sp,SRAM_STACK_V
-
-	/* Saving the function arguements for later use */
-	mov  	r4,r0
-	mov  	r5,r1
-
-	/* Putting DDR into self refresh */
-	ldr 	r0,DDR_07_V
-	ldr	r1,[r0]
-	ldr	r2,DDR_ACTIVE_V
-	bic	r1, r1, r2
-	str	r1,[r0]
-	ldr 	r0,DDR_57_V
-	ldr	r1,[r0]
-	ldr	r2,CYCLES_MASK_V
-	bic	r1, r1, r2
-	ldr	r2,REFRESH_CYCLES_V
-	orr	r1, r1, r2, lsl #16
-	str	r1,[r0]
-	ldr 	r0,DDR_07_V
-	ldr	r1,[r0]
-	ldr	r2,SREFRESH_MASK_V
-	orr	r1, r1, r2
-	str	r1,[r0]
-
-	/* flush pipeline */
-	b	flush
-	.align 5
-flush:
-	/* Delay to ensure self refresh mode */
-	ldr	r0,SREFRESH_DELAY_V
-delay:
-	sub	r0,r0,#1
-	cmp	r0,#0
-	bne	delay
-
-	/* Putting system in slow mode */
-	ldr	r0,SCCTRL_V
-	mov	r1,#2
-	str	r1,[r0]
-
-	/* Changing PLL(1/2) frequency */
-	mov	r0,r4
-	mov	r1,r5
-
-	cmp	r4,#0
-	beq	pll1_freq
-
-	/* Change PLL2 (DDR frequency) */
-	ldr	r6,PLL2_FREQ_V
-	ldr	r7,PLL2_CNTL_V
-	b	pll2_freq
-
-pll1_freq:
-	/* Change PLL1 (CPU frequency) */
-	ldr	r6,PLL1_FREQ_V
-	ldr	r7,PLL1_CNTL_V
-
-pll2_freq:
-	mov	r0,r6
-	ldr	r1,[r0]
-	ldr	r2,PLLFREQ_MASK_V
-	bic	r1,r1,r2
-	mov	r2,r5,lsr#1
-	orr	r1,r1,r2,lsl#24
-	str	r1,[r0]
-
-	mov	r0,r7
-	ldr	r1,P1C0A_V
-	str	r1,[r0]
-	ldr	r1,P1C0E_V
-	str	r1,[r0]
-	ldr	r1,P1C06_V
-	str	r1,[r0]
-	ldr	r1,P1C0E_V
-	str	r1,[r0]
-
-lock:
-	ldr	r1,[r0]
-	and	r1,r1,#1
-	cmp	r1,#0
-	beq	lock
-
-	/* Putting system back to normal mode */
-	ldr	r0,SCCTRL_V
-	mov	r1,#4
-	str	r1,[r0]
-
-	/* Putting DDR back to normal */
-	ldr	r0,DDR_07_V
-	ldr	r1,[R0]
-	ldr	r2,SREFRESH_MASK_V
-	bic	r1, r1, r2
-	str	r1,[r0]
-	ldr	r2,DDR_ACTIVE_V
-	orr	r1, r1, r2
-	str	r1,[r0]
-
-	/* Delay to ensure self refresh mode */
-	ldr	r0,SREFRESH_DELAY_V
-1:
-	sub	r0,r0,#1
-	cmp	r0,#0
-	bne	1b
-
-	mov	sp,r8
-	/* Resuming back to code */
-	ldmia	sp!,{r0-r12}
-	ldmia	sp!,{pc}
-
-SCCTRL_V:
-	.word 0xfca00000
-PLL1_FREQ_V:
-	.word 0xfca8000C
-PLL1_CNTL_V:
-	.word 0xfca80008
-PLL2_FREQ_V:
-	.word 0xfca80018
-PLL2_CNTL_V:
-	.word 0xfca80014
-PLLFREQ_MASK_V:
-	.word 0xff000000
-P1C0A_V:
-	.word 0x1C0A
-P1C0E_V:
-	.word 0x1C0E
-P1C06_V:
-	.word 0x1C06
-
-SREFRESH_DELAY_V:
-	.word 0x9999
-SRAM_STACK_V:
-	.word 0xD2800600
-DDR_07_V:
-	.word 0xfc60001c
-DDR_ACTIVE_V:
-	.word 0x01000000
-DDR_57_V:
-	.word 0xfc6000e4
-CYCLES_MASK_V:
-	.word 0xffff0000
-REFRESH_CYCLES_V:
-	.word 0xf0f0
-SREFRESH_MASK_V:
-	.word 0x00010000
-
-.global setfreq_sz
-setfreq_sz:
-	.word setfreq_sz - setfreq
diff --git a/qemu/roms/u-boot/board/spear/common/spr_misc.c b/qemu/roms/u-boot/board/spear/common/spr_misc.c
deleted file mode 100644
index bc92cd6f4..000000000
--- a/qemu/roms/u-boot/board/spear/common/spr_misc.c
+++ /dev/null
@@ -1,247 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <i2c.h>
-#include <net.h>
-#include <linux/mtd/st_smi.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_emi.h>
-#include <asm/arch/spr_defs.h>
-
-#define CPU		0
-#define DDR		1
-#define SRAM_REL	0xD2801000
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET)
-static int i2c_read_mac(uchar *buffer);
-#endif
-
-int dram_init(void)
-{
-	/* Store complete RAM size and return */
-	gd->ram_size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_MAXSIZE);
-
-	return 0;
-}
-
-void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = gd->ram_size;
-}
-
-int board_early_init_f()
-{
-#if defined(CONFIG_ST_SMI)
-	smi_init();
-#endif
-	return 0;
-}
-int misc_init_r(void)
-{
-#if defined(CONFIG_CMD_NET)
-	uchar mac_id[6];
-
-	if (!eth_getenv_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))
-		eth_setenv_enetaddr("ethaddr", mac_id);
-#endif
-	setenv("verify", "n");
-
-#if defined(CONFIG_SPEAR_USBTTY)
-	setenv("stdin", "usbtty");
-	setenv("stdout", "usbtty");
-	setenv("stderr", "usbtty");
-
-#ifndef CONFIG_SYS_NO_DCACHE
-	dcache_enable();
-#endif
-#endif
-	return 0;
-}
-
-#ifdef CONFIG_SPEAR_EMI
-struct cust_emi_para {
-	unsigned int tap;
-	unsigned int tsdp;
-	unsigned int tdpw;
-	unsigned int tdpr;
-	unsigned int tdcs;
-};
-
-/* EMI timing setting of m28w640hc of linux kernel */
-const struct cust_emi_para emi_timing_m28w640hc = {
-	.tap = 0x10,
-	.tsdp = 0x05,
-	.tdpw = 0x0a,
-	.tdpr = 0x0a,
-	.tdcs = 0x05,
-};
-
-/* EMI timing setting of bootrom */
-const struct cust_emi_para emi_timing_bootrom = {
-	.tap = 0xf,
-	.tsdp = 0x0,
-	.tdpw = 0xff,
-	.tdpr = 0x111,
-	.tdcs = 0x02,
-};
-
-void spear_emi_init(void)
-{
-	const struct cust_emi_para *p = &emi_timing_m28w640hc;
-	struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE;
-	unsigned int cs;
-	unsigned int val, tmp;
-
-	val = readl(CONFIG_SPEAR_RASBASE);
-
-	if (val & EMI_ACKMSK)
-		tmp = 0x3f;
-	else
-		tmp = 0x0;
-
-	writel(tmp, &emi_regs_p->ack);
-
-	for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) {
-		writel(p->tap, &emi_regs_p->bank_regs[cs].tap);
-		writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp);
-		writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw);
-		writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr);
-		writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs);
-		writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3),
-		       &emi_regs_p->bank_regs[cs].control);
-	}
-}
-#endif
-
-int spear_board_init(ulong mach_type)
-{
-	gd->bd->bi_arch_number = mach_type;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
-
-#ifdef CONFIG_SPEAR_EMI
-	spear_emi_init();
-#endif
-	return 0;
-}
-
-#if defined(CONFIG_CMD_NET)
-static int i2c_read_mac(uchar *buffer)
-{
-	u8 buf[2];
-
-	i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
-
-	/* Check if mac in i2c memory is valid */
-	if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
-		/* Valid mac address is saved in i2c eeprom */
-		i2c_read(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, buffer, MAC_LEN);
-		return 0;
-	}
-
-	return -1;
-}
-
-static int write_mac(uchar *mac)
-{
-	u8 buf[2];
-
-	buf[0] = (u8)MAGIC_BYTE0;
-	buf[1] = (u8)MAGIC_BYTE1;
-	i2c_write(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
-
-	buf[0] = (u8)~MAGIC_BYTE0;
-	buf[1] = (u8)~MAGIC_BYTE1;
-
-	i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
-
-	/* check if valid MAC address is saved in I2C EEPROM or not? */
-	if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
-		i2c_write(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, mac, MAC_LEN);
-		puts("I2C EEPROM written with mac address \n");
-		return 0;
-	}
-
-	puts("I2C EEPROM writing failed\n");
-	return -1;
-}
-#endif
-
-int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	void (*sram_setfreq) (unsigned int, unsigned int);
-	unsigned int frequency;
-#if defined(CONFIG_CMD_NET)
-	unsigned char mac[6];
-#endif
-
-	if ((argc > 3) || (argc < 2))
-		return cmd_usage(cmdtp);
-
-	if ((!strcmp(argv[1], "cpufreq")) || (!strcmp(argv[1], "ddrfreq"))) {
-
-		frequency = simple_strtoul(argv[2], NULL, 0);
-
-		if (frequency > 333) {
-			printf("Frequency is limited to 333MHz\n");
-			return 1;
-		}
-
-		sram_setfreq = memcpy((void *)SRAM_REL, setfreq, setfreq_sz);
-
-		if (!strcmp(argv[1], "cpufreq")) {
-			sram_setfreq(CPU, frequency);
-			printf("CPU frequency changed to %u\n", frequency);
-		} else {
-			sram_setfreq(DDR, frequency);
-			printf("DDR frequency changed to %u\n", frequency);
-		}
-
-		return 0;
-
-#if defined(CONFIG_CMD_NET)
-	} else if (!strcmp(argv[1], "ethaddr")) {
-
-		u32 reg;
-		char *e, *s = argv[2];
-		for (reg = 0; reg < 6; ++reg) {
-			mac[reg] = s ? simple_strtoul(s, &e, 16) : 0;
-			if (s)
-				s = (*e) ? e + 1 : e;
-		}
-		write_mac(mac);
-
-		return 0;
-#endif
-	} else if (!strcmp(argv[1], "print")) {
-#if defined(CONFIG_CMD_NET)
-		if (!i2c_read_mac(mac)) {
-			printf("Ethaddr (from i2c mem) = %pM\n", mac);
-		} else {
-			printf("Ethaddr (from i2c mem) = Not set\n");
-		}
-#endif
-		return 0;
-	}
-
-	return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD(chip_config, 3, 1, do_chip_config,
-	   "configure chip",
-	   "chip_config cpufreq/ddrfreq frequency\n"
-#if defined(CONFIG_CMD_NET)
-	   "chip_config ethaddr XX:XX:XX:XX:XX:XX\n"
-#endif
-	   "chip_config print");
diff --git a/qemu/roms/u-boot/board/spear/spear300/Makefile b/qemu/roms/u-boot/board/spear/spear300/Makefile
deleted file mode 100644
index 84d05e332..000000000
--- a/qemu/roms/u-boot/board/spear/spear300/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= spear300.o
diff --git a/qemu/roms/u-boot/board/spear/spear300/spear300.c b/qemu/roms/u-boot/board/spear/spear300/spear300.c
deleted file mode 100644
index 6b6bd9f29..000000000
--- a/qemu/roms/u-boot/board/spear/spear300/spear300.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <linux/mtd/fsmc_nand.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_defs.h>
-#include <asm/arch/spr_misc.h>
-
-static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-
-int board_init(void)
-{
-	return spear_board_init(MACH_TYPE_SPEAR300);
-}
-
-/*
- * board_nand_init - Board specific NAND initialization
- * @nand:	mtd private chip structure
- *
- * Called by nand_init_chip to initialize the board specific functions
- */
-
-void board_nand_init()
-{
-	struct misc_regs *const misc_regs_p =
-	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	struct nand_chip *nand = &nand_chip[0];
-
-#if defined(CONFIG_NAND_FSMC)
-	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
-	     MISC_SOCCFG30) ||
-	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
-	     MISC_SOCCFG31)) {
-
-		fsmc_nand_init(nand);
-	}
-#endif
-	return;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	int ret = 0;
-
-#if defined(CONFIG_DESIGNWARE_ETH)
-	u32 interface = PHY_INTERFACE_MODE_MII;
-	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
-		ret++;
-#endif
-	return ret;
-}
diff --git a/qemu/roms/u-boot/board/spear/spear310/Makefile b/qemu/roms/u-boot/board/spear/spear310/Makefile
deleted file mode 100644
index 3a2e3ac08..000000000
--- a/qemu/roms/u-boot/board/spear/spear310/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= spear310.o
diff --git a/qemu/roms/u-boot/board/spear/spear310/spear310.c b/qemu/roms/u-boot/board/spear/spear310/spear310.c
deleted file mode 100644
index a4c6a8edb..000000000
--- a/qemu/roms/u-boot/board/spear/spear310/spear310.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * (C) Copyright 2009
- * Ryan Chen, ST Micoelectronics, ryan.chen@st.com.
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <linux/mtd/fsmc_nand.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_defs.h>
-#include <asm/arch/spr_misc.h>
-
-static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-
-int board_init(void)
-{
-	return spear_board_init(MACH_TYPE_SPEAR310);
-}
-
-/*
- * board_nand_init - Board specific NAND initialization
- * @nand:	mtd private chip structure
- *
- * Called by nand_init_chip to initialize the board specific functions
- */
-
-void board_nand_init()
-{
-	struct misc_regs *const misc_regs_p =
-	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	struct nand_chip *nand = &nand_chip[0];
-
-#if defined(CONFIG_NAND_FSMC)
-	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
-	     MISC_SOCCFG30) ||
-	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
-	     MISC_SOCCFG31)) {
-
-		fsmc_nand_init(nand);
-	}
-#endif
-	return;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	int ret = 0;
-
-#if defined(CONFIG_DESIGNWARE_ETH)
-	u32 interface = PHY_INTERFACE_MODE_MII;
-	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
-		ret++;
-#endif
-#if defined(CONFIG_MACB)
-	if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE,
-				CONFIG_MACB0_PHY) >= 0)
-		ret++;
-
-	if (macb_eth_initialize(1, (void *)CONFIG_SYS_MACB1_BASE,
-				CONFIG_MACB1_PHY) >= 0)
-		ret++;
-
-	if (macb_eth_initialize(2, (void *)CONFIG_SYS_MACB2_BASE,
-				CONFIG_MACB2_PHY) >= 0)
-		ret++;
-
-	if (macb_eth_initialize(3, (void *)CONFIG_SYS_MACB3_BASE,
-				CONFIG_MACB3_PHY) >= 0)
-		ret++;
-#endif
-	return ret;
-}
diff --git a/qemu/roms/u-boot/board/spear/spear320/Makefile b/qemu/roms/u-boot/board/spear/spear320/Makefile
deleted file mode 100644
index f01116e6b..000000000
--- a/qemu/roms/u-boot/board/spear/spear320/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= spear320.o
diff --git a/qemu/roms/u-boot/board/spear/spear320/spear320.c b/qemu/roms/u-boot/board/spear/spear320/spear320.c
deleted file mode 100644
index ab732a724..000000000
--- a/qemu/roms/u-boot/board/spear/spear320/spear320.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * (C) Copyright 2009
- * Ryan Chen, ST Micoelectronics, ryan.chen@st.com.
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <linux/mtd/fsmc_nand.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_defs.h>
-#include <asm/arch/spr_misc.h>
-
-#define PLGPIO_SEL_36	0xb3000028
-#define PLGPIO_IO_36	0xb3000038
-
-static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-
-static void spear_phy_reset(void)
-{
-	writel(0x10, PLGPIO_IO_36);
-	writel(0x10, PLGPIO_SEL_36);
-}
-
-int board_init(void)
-{
-	spear_phy_reset();
-	return spear_board_init(MACH_TYPE_SPEAR320);
-}
-
-/*
- * board_nand_init - Board specific NAND initialization
- * @nand:	mtd private chip structure
- *
- * Called by nand_init_chip to initialize the board specific functions
- */
-
-void board_nand_init()
-{
-	struct misc_regs *const misc_regs_p =
-	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	struct nand_chip *nand = &nand_chip[0];
-
-#if defined(CONFIG_NAND_FSMC)
-	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
-	     MISC_SOCCFG30) ||
-	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
-	     MISC_SOCCFG31)) {
-
-		fsmc_nand_init(nand);
-	}
-#endif
-
-	return;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	int ret = 0;
-
-#if defined(CONFIG_DESIGNWARE_ETH)
-	u32 interface = PHY_INTERFACE_MODE_MII;
-	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
-		ret++;
-#endif
-#if defined(CONFIG_MACB)
-	if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE,
-				CONFIG_MACB0_PHY) >= 0)
-		ret++;
-#endif
-	return ret;
-}
diff --git a/qemu/roms/u-boot/board/spear/spear600/Makefile b/qemu/roms/u-boot/board/spear/spear600/Makefile
deleted file mode 100644
index 7abfb9ad5..000000000
--- a/qemu/roms/u-boot/board/spear/spear600/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifndef CONFIG_SPL_BUILD
-obj-y	:= spear600.o
-endif
diff --git a/qemu/roms/u-boot/board/spear/spear600/spear600.c b/qemu/roms/u-boot/board/spear/spear600/spear600.c
deleted file mode 100644
index 8472002f7..000000000
--- a/qemu/roms/u-boot/board/spear/spear600/spear600.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <linux/mtd/fsmc_nand.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_defs.h>
-#include <asm/arch/spr_misc.h>
-
-static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-
-int board_init(void)
-{
-	return spear_board_init(MACH_TYPE_SPEAR600);
-}
-
-/*
- * board_nand_init - Board specific NAND initialization
- * @nand:	mtd private chip structure
- *
- * Called by nand_init_chip to initialize the board specific functions
- */
-
-void board_nand_init()
-{
-	struct misc_regs *const misc_regs_p =
-	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	struct nand_chip *nand = &nand_chip[0];
-
-#if defined(CONFIG_NAND_FSMC)
-	if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
-		fsmc_nand_init(nand);
-#endif
-	return;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	int ret = 0;
-
-#if defined(CONFIG_DESIGNWARE_ETH)
-	u32 interface = PHY_INTERFACE_MODE_MII;
-#if defined(CONFIG_DW_AUTONEG)
-	interface = PHY_INTERFACE_MODE_GMII;
-#endif
-	if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
-		ret++;
-#endif
-	return ret;
-}
diff --git a/qemu/roms/u-boot/board/spear/x600/Makefile b/qemu/roms/u-boot/board/spear/x600/Makefile
deleted file mode 100644
index 18d3dd2e6..000000000
--- a/qemu/roms/u-boot/board/spear/x600/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-# necessary to create built-in.o
-obj- := __dummy__.o
-else
-obj-y	:= fpga.o x600.o
-endif
diff --git a/qemu/roms/u-boot/board/spear/x600/fpga.c b/qemu/roms/u-boot/board/spear/x600/fpga.c
deleted file mode 100644
index b256222e1..000000000
--- a/qemu/roms/u-boot/board/spear/x600/fpga.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- * Copyright (C) 2012 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <spartan3.h>
-#include <command.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_misc.h>
-#include <asm/arch/spr_ssp.h>
-
-/*
- * FPGA program pin configuration on X600:
- *
- * Only PROG and DONE are connected to GPIOs. INIT is not connected to the
- * SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use
- * 16bit serial writes via this SSP port to write the data bits into the
- * FPGA.
- */
-#define CONFIG_SYS_FPGA_PROG		2
-#define CONFIG_SYS_FPGA_DONE		3
-
-/*
- * Set the active-low FPGA reset signal.
- */
-static void fpga_reset(int assert)
-{
-	/*
-	 * On x600 we have no means to toggle the FPGA reset signal
-	 */
-	debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert);
-}
-
-/*
- * Set the FPGA's active-low SelectMap program line to the specified level
- */
-static int fpga_pgm_fn(int assert, int flush, int cookie)
-{
-	debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert);
-
-	gpio_set_value(CONFIG_SYS_FPGA_PROG, assert);
-
-	return assert;
-}
-
-/*
- * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
- * asserted (low).
- */
-static int fpga_init_fn(int cookie)
-{
-	static int state;
-
-	debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state);
-
-	/*
-	 * On x600, the FPGA INIT signal is not connected to the SoC.
-	 * We can't read the INIT status. Let's return the "correct"
-	 * INIT signal state generated via a local state-machine.
-	 */
-	if (++state == 1) {
-		return 1;
-	} else {
-		state = 0;
-		return 0;
-	}
-}
-
-/*
- * Test the state of the active-high FPGA DONE pin
- */
-static int fpga_done_fn(int cookie)
-{
-	struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
-
-	/*
-	 * Wait for Tx-FIFO to become empty before looking for DONE
-	 */
-	while (!(readl(&ssp->sspsr) & SSPSR_TFE))
-		;
-
-	if (gpio_get_value(CONFIG_SYS_FPGA_DONE))
-		return 1;
-	else
-		return 0;
-}
-
-/*
- * FPGA pre-configuration function. Just make sure that
- * FPGA reset is asserted to keep the FPGA from starting up after
- * configuration.
- */
-static int fpga_pre_config_fn(int cookie)
-{
-	debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
-	fpga_reset(true);
-
-	return 0;
-}
-
-/*
- * FPGA post configuration function. Blip the FPGA reset line and then see if
- * the FPGA appears to be running.
- */
-static int fpga_post_config_fn(int cookie)
-{
-	int rc = 0;
-
-	debug("%s:%d: FPGA post configuration\n", __func__, __LINE__);
-
-	fpga_reset(true);
-	udelay(100);
-	fpga_reset(false);
-	udelay(100);
-
-	return rc;
-}
-
-static int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
-	/*
-	 * No dedicated clock signal on x600 (data & clock generated)
-	 * in SSP interface. So we don't have to do anything here.
-	 */
-	return assert_clk;
-}
-
-static int fpga_wr_fn(int assert_write, int flush, int cookie)
-{
-	struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
-	static int count;
-	static u16 data;
-
-	/*
-	 * First collect 16 bits of data
-	 */
-	data = data << 1;
-	if (assert_write)
-		data |= 1;
-
-	/*
-	 * If 16 bits are not available, return for more bits
-	 */
-	count++;
-	if (count != 16)
-		return assert_write;
-
-	count = 0;
-
-	/*
-	 * Wait for Tx-FIFO to become ready
-	 */
-	while (!(readl(&ssp->sspsr) & SSPSR_TNF))
-		;
-
-	/* Send 16 bits to FPGA via SSP bus */
-	writel(data, &ssp->sspdr);
-
-	return assert_write;
-}
-
-static xilinx_spartan3_slave_serial_fns x600_fpga_fns = {
-	fpga_pre_config_fn,
-	fpga_pgm_fn,
-	fpga_clk_fn,
-	fpga_init_fn,
-	fpga_done_fn,
-	fpga_wr_fn,
-	fpga_post_config_fn,
-};
-
-static xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
-	XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0)
-};
-
-/*
- * Initialize the SelectMap interface.  We assume that the mode and the
- * initial state of all of the port pins have already been set!
- */
-static void fpga_serialslave_init(void)
-{
-	debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__);
-	fpga_pgm_fn(false, false, 0);	/* make sure program pin is inactive */
-}
-
-static int expi_setup(int freq)
-{
-	struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	int pll2_m, pll2_n, pll2_p, expi_x, expi_y;
-
-	pll2_m = (freq * 2) / 1000;
-	pll2_n = 15;
-	pll2_p = 1;
-	expi_x = 1;
-	expi_y = 2;
-
-	/*
-	 * Disable reset, Low compression, Disable retiming, Enable Expi,
-	 * Enable soft reset, DMA, PLL2, Internal
-	 */
-	writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST |
-	       EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 |
-	       EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24),
-	       &misc->expi_clk_cfg);
-
-	/*
-	 * 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters,
-	 * Enable PLL2, Disable reset
-	 */
-	writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq);
-	writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE |
-	       PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl);
-
-	/*
-	 * Disable soft reset
-	 */
-	clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST);
-
-	return 0;
-}
-
-/*
- * Initialize the fpga
- */
-int x600_init_fpga(void)
-{
-	struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
-	struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-
-	/* Enable SSP2 clock */
-	writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB,
-	       &misc->periph1_clken);
-
-	/* Set EXPI clock to 45 MHz */
-	expi_setup(45000);
-
-	/* Configure GPIO directions */
-	gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0);
-	gpio_direction_input(CONFIG_SYS_FPGA_DONE);
-
-	writel(SSPCR0_DSS_16BITS, &ssp->sspcr0);
-	writel(SSPCR1_SSE, &ssp->sspcr1);
-
-	/*
-	 * Set lowest prescale divisor value (CPSDVSR) of 2 for max download
-	 * speed.
-	 *
-	 * Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1))
-	 * With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz.
-	 */
-	writel(2, &ssp->sspcpsr);
-
-	fpga_init();
-	fpga_serialslave_init();
-
-	debug("%s:%d: Adding fpga 0\n", __func__, __LINE__);
-	fpga_add(fpga_xilinx, &fpga[0]);
-
-	return 0;
-}
diff --git a/qemu/roms/u-boot/board/spear/x600/fpga.h b/qemu/roms/u-boot/board/spear/x600/fpga.h
deleted file mode 100644
index 3d519a5a7..000000000
--- a/qemu/roms/u-boot/board/spear/x600/fpga.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Copyright (C) 2012 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-int x600_init_fpga(void);
diff --git a/qemu/roms/u-boot/board/spear/x600/x600.c b/qemu/roms/u-boot/board/spear/x600/x600.c
deleted file mode 100644
index b8edfcd07..000000000
--- a/qemu/roms/u-boot/board/spear/x600/x600.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * Copyright (C) 2012 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <nand.h>
-#include <netdev.h>
-#include <phy.h>
-#include <rtc.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_defs.h>
-#include <asm/arch/spr_misc.h>
-#include <linux/mtd/fsmc_nand.h>
-#include "fpga.h"
-
-static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-
-int board_init(void)
-{
-	/*
-	 * X600 is equipped with an M41T82 RTC. This RTC has the
-	 * HT bit (Halt Update), which needs to be cleared upon
-	 * power-up. Otherwise the RTC is halted.
-	 */
-	rtc_reset();
-
-	return spear_board_init(MACH_TYPE_SPEAR600);
-}
-
-int board_late_init(void)
-{
-	/*
-	 * Monitor and env protection on by default
-	 */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE +
-		      CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN +
-		      2 * CONFIG_ENV_SECT_SIZE - 1,
-		      &flash_info[0]);
-
-	/* Init FPGA subsystem */
-	x600_init_fpga();
-
-	return 0;
-}
-
-/*
- * board_nand_init - Board specific NAND initialization
- * @nand:	mtd private chip structure
- *
- * Called by nand_init_chip to initialize the board specific functions
- */
-
-void board_nand_init(void)
-{
-	struct misc_regs *const misc_regs_p =
-		(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
-	struct nand_chip *nand = &nand_chip[0];
-
-	if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
-		fsmc_nand_init(nand);
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
-	/* Extended PHY control 1, select GMII */
-	phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
-
-	/* Software reset necessary after GMII mode selction */
-	phy_reset(phydev);
-
-	/* Enable extended page register access */
-	phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
-
-	/* 17e: Enhanced LED behavior, needs to be written twice */
-	phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
-	phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
-
-	/* 16e: Enhanced LED method select */
-	phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
-
-	/* Disable extended page register access */
-	phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
-
-	/* Enable clock output pin */
-	phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
-
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	int ret = 0;
-
-	if (designware_initialize(CONFIG_SPEAR_ETHBASE,
-				  PHY_INTERFACE_MODE_GMII) >= 0)
-		ret++;
-
-	return ret;
-}