diff options
Diffstat (limited to 'qemu/roms/u-boot/board/mpl/pip405')
| -rw-r--r-- | qemu/roms/u-boot/board/mpl/pip405/Makefile | 14 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/mpl/pip405/README | 375 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/mpl/pip405/cmd_pip405.c | 53 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/mpl/pip405/init.S | 197 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/mpl/pip405/pip405.c | 956 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/mpl/pip405/pip405.h | 131 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/mpl/pip405/u-boot.lds.debug | 121 |
7 files changed, 1847 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/board/mpl/pip405/Makefile b/qemu/roms/u-boot/board/mpl/pip405/Makefile new file mode 100644 index 000000000..0a3d059e9 --- /dev/null +++ b/qemu/roms/u-boot/board/mpl/pip405/Makefile @@ -0,0 +1,14 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = pip405.o cmd_pip405.o \ + ../common/pci.o \ + ../common/isa.o \ + ../common/kbd.o \ + ../common/usb_uhci.o \ + ../common/common_util.o +obj-y += init.o diff --git a/qemu/roms/u-boot/board/mpl/pip405/README b/qemu/roms/u-boot/board/mpl/pip405/README new file mode 100644 index 000000000..012db1c5f --- /dev/null +++ b/qemu/roms/u-boot/board/mpl/pip405/README @@ -0,0 +1,375 @@ +U-Boot Changes due to PIP405 Port: +=================================== + +Changed files: +============== +- MAKEALL added PIP405 +- makefile added PIP405 +- common/Makefile added Floppy disk and SCSI support +- common/board.c added PIP405, SCSI support, get_PCI_freq() +- common/bootm.c added IH_OS_U_BOOT, IH_TYPE_FIRMWARE +- common/cmd_i2c.c added "defined(CONFIG_PIP405)" +- common/cmd_ide.c changed div. functions to work with block device + description + added ATAPI support +- common/command.c added SCSI and Floppy support +- common/console.c replaced // with /* comments + added console settings from environment +- common/devices.c added ISA keyboard init +- common/main.c corrected the read of bootdelay +- arch/powerpc/cpu/ppc4xx/405gp_pci.c excluded file from PIP405 +- arch/powerpc/cpu/ppc4xx/i2c.c added 16bit read write I2C support + added page write +- arch/powerpc/cpu/ppc4xx/speed.c added get_PCI_freq +- arch/powerpc/cpu/ppc4xx/start.S added CONFIG_IDENT_STRING +- disk/Makefile added part_iso for CD support +- disk/part.c changed to work with block device description + added ISO CD support + added dev_print (was ide_print in cmd_ide.c) +- disk/part_dos.c changed to work with block device description +- disk/part_mac.c changed to work with block device description +- include/ata.h added ATAPI commands +- include/cmd_bsp.h added PIP405 commands definitions +- include/cmd_condefs.h added Floppy and SCSI support +- include/cmd_disk.h changed to work with block device description +- include/config_LANTEC.h excluded CONFIG_CMD_FDC and CONFIG_CMD_SCSI +- include/config_hymod.h excluded CONFIG_CMD_FDC and CONFIG_CMD_SCSI +- include/flash.h added INTEL_ID_28F320C3T 0x88C488C4 +- include/i2c.h added "defined(CONFIG_PIP405)" +- include/image.h added IH_OS_U_BOOT, IH_TYPE_FIRMWARE +- include/u-boot.h moved partitions functions definitions to part.h + added "defined(CONFIG_PIP405)" + added get_PCI_freq() definition +- rtc/Makefile added MC146818 RTC support +- tools/mkimage.c added IH_OS_U_BOOT, IH_TYPE_FIRMWARE + +Added files: +============ +- board/pip405 directory for PIP405 +- board/pip405/cmd_pip405.c board specific commands +- board/pip405/config.mk config make +- board/pip405/flash.c flash support +- board/pip405/init.s start-up +- board/pip405/kbd.c keyboard support +- board/pip405/kbd.h keyboard support +- board/pip405/Makefile Makefile +- board/pip405/pci_piix4.h southbridge definitions +- board/pip405/pci_pip405.c PCI support for PIP405 +- board/pip405/pci_pip405.h PCI support for PIP405 +- board/pip405/pip405.c PIP405 board init +- board/pip405/pip405.h PIP405 board init +- board/pip405/pip405_isa.c ISA support +- board/pip405/pip405_isa.h ISA support +- board/pip405/u-boot.lds Linker description +- board/pip405/u-boot.lds.debugLinker description debug +- board/pip405/sym53c8xx.c SYM53C810A support +- board/pip405/sym53c8xx_defs.h SYM53C810A definitions +- board/pip405/vga_table.h definitions of tables for VGA +- board/pip405/video.c CT69000 support +- board/pip405/video.h CT69000 support +- common/cmd_fdc.c Floppy disk support +- common/cmd_scsi.c SCSI support +- disk/part_iso.c ISO CD ROM support +- disk/part_iso.h ISO CD ROM support +- include/cmd_fdc.h command forFloppy disk support +- include/cmd_scsi.h command for SCSI support +- include/part.h partitions functions definitions + (was part of u-boot.h) +- include/scsi.h SCSI support +- rtc/mc146818.c MC146818 RTC support + + +New Config Switches: +==================== +For detailed description, refer to the corresponding paragraph in the +section "Changes". + +New Commands: +------------- +CONFIG_CMD_SCSI SCSI Support +CONFIG_CMF_FDC Floppy disk support + +IDE additions: +-------------- +CONFIG_IDE_RESET_ROUTINE defines that instead of a reset Pin, + the routine ide_set_reset(int idereset) is used. +ATAPI support (experimental) +---------------------------- +CONFIG_ATAPI enables ATAPI Support + +SCSI support (experimental) only SYM53C8xx supported +---------------------------------------------------- +CONFIG_SCSI_SYM53C8XX type of SCSI controller +CONFIG_SYS_SCSI_MAX_LUN 8 number of supported LUNs +CONFIG_SYS_SCSI_MAX_SCSI_ID 7 maximum SCSI ID (0..6) +CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN + maximum of Target devices (multiple LUN support + for boot) + +ISO (CD-Boot) partition support (Experimental) +---------------------------------------------- +CONFIG_ISO_PARTITION CD-boot support + +RTC +---- +CONFIG_RTC_MC146818 MC146818 RTC support + +Keyboard: +--------- +CONFIG_ISA_KEYBOARD Standard (PC-Style) Keyboard support + +Video: +------ +CONFIG_VIDEO_CT69000 Enable Chips & Technologies 69000 Video chip + CONFIG_VIDEO must be defined also + +External peripheral base address: +--------------------------------- +CONFIG_SYS_ISA_IO_BASE_ADDRESS address of all ISA-bus related parts + _must_ be defined for ISA-bus parts + +Identify: +--------- +CONFIG_IDENT_STRING added to the U_BOOT_VERSION String + +Environment / Console: +---------------------- + +CONFIG_SYS_CONSOLE_IS_IN_ENV if defined, stdin, stdout and stderr used from + the values stored in the evironment. + +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE if defined, console_overwrite() decides if the + values stored in the environment or the standard + serial in/out put should be assigned to the console. + +CONFIG_SYS_CONSOLE_ENV_OVERWRITE if defined, the start-up console switching + are stored in the environment. + +PIP405 specific: +---------------- +CONFIG_PORT_ADDR address used to read boot configuration +MULTI_PURPOSE_SOCKET_ADDR address of the multi purpose socked +SDRAM_EEPROM_WRITE_ADDRESS addresses of the serial presence detect +SDRAM_EEPROM_READ_ADDRESS EEPROM on the SDRAM module. + + +Changes: +======== + +Added Devices: +============== + +Floppy support: +--------------- +Support of a standard floppy disk controller at address CONFIG_SYS_ISA_IO_BASE_ADDRESS ++ 0x3F0. Enabled with define CONFIG_CMD_FDC. Reads a unformated floppy disk +with a image header (see: mkimage). No interrupts and no DMA are used for this. +Added files: +- common/cmd_fdc.c +- include/cmd_fdc.h + +SCSI support: +------------- +Support for Symbios SYM53C810A chip. Implemented as follows: +- without disconnect +- only asynchrounous +- multiple LUN support (caution, needs a lot of RAM. define CONFIG_SYS_SCSI_MAX_LUN 1 to + save RAM) +- multiple SCSI ID support +- no write support +- analyses the MAC, DOS and ISO pratition similar to the IDE support +- allows booting from SCSI devices similar to the IDE support. +The device numbers are not assigned like they are within the IDE support. The first +device found will get the number 0, the next 1 etc. If all SCSI IDs (0..6) and all +LUNs (8) are enabled, 56 boot devices are possible. This uses a lot of RAM since the +device descriptors are not yet dynamically allocated. 56 boot devices are overkill +anyway. Please refer to the section "Todo" chapter "block device support enhancement". +The SYM53C810A uses 1 Interrupt and must be able of mastering the PCI bus. +Added files: +- common/cmd_scsi.c +- common/board.c +- include/cmd_scsi.h +- include/scsi.h +- board/pip405/sym53c8xx.c +- board/pip405/sym53c8xx_defs.h + +ATAPI support (IDE changes): +---------------------------- +Added ATAPI support (with CONFIG_ATAPI) in the file cmd_ide.c. +To support a hardreset, when the IDE reset pin is not connected to the +CONFIG_SYS_PC_IDE_RESET pin, the switch CONFIG_IDE_RESET_ROUTINE has been added. When +this switch is enabled the routine void ide_set_reset(int idereset) must be +within the board specific files. +Only read from ATAPI devices are supported. +Found out that the function trim_trail cuts off the last character if the whole +string is filled. Added function cpy_ident instead, which trims also leading +spaces and copies the string in the buffer. +Changed files: +- common/cmd_ide.c +- include/ata.h + +ISO partition support: +---------------------- +Added CD boot support for El-Torito bootable ISO CDs. The bootfile image must contain +the U-Boot image header. Since CDs do not have "partitions", the boot partition is 0. +The bootcatalog feature has not been tested so far. CD Boot is supported for ATAPI +("diskboot") and SCSI ("scsiboot") devices. +Added files: +- disk/iso_part.c +- disk/iso_part.h + +Block device changes: +--------------------- +To allow the use of dos_part.c, mac_part.c and iso_part.c, the parameter +block_dev_desc will be used when accessing the functions in these files. The block +device descriptor (block_dev_desc) contains a pointer to the read routine of the +device, which will be used to read blocks from the device. +Renamed function ide_print to dev_print and moved it to the file disk/part.c to use +it for IDE ATAPI and SCSI devices. +Please refer to the section "Todo" chapter "block device support enhancement". +Added files: +- include/part.h +changed files: +- disk/dos_part.c +- disk/dos_part.h +- disk/mac_part.c +- disk/mac_part.h +- disk/part.c +- common/cmd_ide.c +- include/u-boot.h + + +MC146818 RTC support: +--------------------- +Added support for MC146818 RTC with defining CONFIG_RTC_MC146818. The ISA bus IO +base address must be defined with CONFIG_SYS_ISA_IO_BASE_ADDRESS. +Added files: +- rtc/mc146818.c + +Standard ISA bus Keyboard support: +---------------------------------- +Added support for the standard PC kyeboard controller. For the PIP405 the superIO +controller must be set up previously. The keyboard uses the standard ISA IRQ, so +the ISA PIC must also be set up. +Added files: +- board/pip405/kbd.c +- board/pip405/kbd.h +- board/pip405/pip405_isa.c +- board/pip405/pip405_isa.h + +Chips and Technologie 69000 VGA controller support: +--------------------------------------------------- +Added support for the CT69000 VGA controller. +Added files: +- board/pip405/video.c +- board/pip405/video.h +- board/pip405/vga_table.h + + +Changed Items: +============== + +Identify: +--------- +Added the config variable CONFIG_IDENT_STRING which will be added to the +"U_BOOT_VERSION __TIME__ DATE___ " String, to allows to identify intermidiate +and custom versions. +Changed files: +- arch/powerpc/cpu/ppc4xx/start.s + +Firmware Image: +--------------- +Added IH_OS_U_BOOT and IH_TYPE_FIRMWARE to the image definitions to allows the +U-Boot update with prior CRC check. +Changed files: +- include/image.h +- tools/mkimage.c +- common/cmd_bootm.c + +Correct PCI Frequency for PPC405: +--------------------------------- +Added function (in arch/powerpc/cpu/ppc4xx/speed.c) to get the PCI frequency for PPC405 CPU. +The PCI Frequency will now be set correct in the board description in common/board.c. +(was set to the busfreq before). +Changed files: +- arch/powerpc/cpu/ppc4xx/speed.c +- common/board.c + +I2C Stuff: +---------- +Added defined(CONFIG_PIP405) at several points in common/cmd_i2c.c. +Added 16bit read/write support for I2C (PPC405), and page write to +I2C EEPROM if defined CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE. +Changed files: +- arch/powerpc/cpu/ppc4xx/i2c.c +- common/cmd_i2c.c + +Environment / Console: +---------------------- +Although in README.console described, the U-Boot has not assinged the values +found in the environment to the console. Corrected this behavior, but only if +CONFIG_SYS_CONSOLE_IS_IN_ENV is defined. +If CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE is defined, console_overwrite() decides if the +values stored in the environment or the standard serial in/output should be +assigned to the console. This is useful if the environment values are not correct. +If CONFIG_SYS_CONSOLE_ENV_OVERWRITE is defined the devices assigned to the console at +start-up time will be written to the environment. This means that if the +environment values are overwritten by the overwrite_console() routine, they will be +stored in the environment. +Changed files: +- common/console.c + +Correct bootdelay intepretation: +-------------------------------- +Changed bootdelay read from the environment from simple_strtoul (unsigned) to +simple_strtol (signed), to be able to get a bootdelay of -1. +Changed files: +- common/main.c + +Todo: +===== + +Block device support enhancement: +--------------------------------- +Consider to unify the block device handling. Instead of using diskboot for IDE, +scsiboot for SCSI and fdcboot for floppy disks, it would make sense to use only +one command ("devboot" ???) with a parameter of the desired device ("hda1", "sda1", +"fd0" ???) to boot from. The other ide commands can be handled in the same way +("dev hda read.." instead of "ide read.." or "dev sda read.." instead of +"scsi read..."). Todo this, a common way of assign a block device to its name +(first found ide device = hda, second found hdb etc., or hda is device 0 on bus 0, +hdb is device 1 on bus 0 etc.) as well as the names (hdx for ide, sdx for scsi, fx for +floppy ???) must be defined. +Maybe there are better ideas to do this. + +Console assingment: +------------------- +Consider to initialize and assign the console stdin, stdout and stderr as soon as +possible to see the boot messages also on an other console than serial. + + +Todo for PIP405: +================ + +LCD support for VGA: +-------------------- +Add LCD support for the CT69000 + +Default environment: +-------------------- +Consider to write a default environment to the OTP part of the EEPROM and use it +if the normal environment is not valid. Useful for serial# and ethaddr values. + +Watchdog: +--------- +Implement Watchdog. + +Files clean-up: +--------------- +Following files needs to be cleaned up: +- cmd_pip405.c +- flash.c +- pci_pip405.c +- pip405.c +- pip405_isa.c +Consider to split up the files in their functions. diff --git a/qemu/roms/u-boot/board/mpl/pip405/cmd_pip405.c b/qemu/roms/u-boot/board/mpl/pip405/cmd_pip405.c new file mode 100644 index 000000000..43b182e57 --- /dev/null +++ b/qemu/roms/u-boot/board/mpl/pip405/cmd_pip405.c @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * SPDX-License-Identifier: GPL-2.0+ + * + * hacked for PIP405 + */ + +#include <common.h> +#include <command.h> +#include "pip405.h" +#include "../common/common_util.h" + + +extern void print_pip405_info(void); +extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); + + +/* ------------------------------------------------------------------------- */ + +int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + + ulong led_on,led_nr; + + if (strcmp(argv[1], "info") == 0) + { + print_pip405_info(); + return 0; + } + if (strcmp(argv[1], "led") == 0) + { + led_nr = (ulong)simple_strtoul(argv[2], NULL, 10); + led_on = (ulong)simple_strtoul(argv[3], NULL, 10); + if(!led_nr) + user_led0(led_on); + else + user_led1(led_on); + return 0; + } + + return (do_mplcommon(cmdtp, flag, argc, argv)); +} +U_BOOT_CMD( + pip405, 6, 1, do_pip405, + "PIP405 specific Cmds", + "flash mem [SrcAddr] - updates U-Boot with image in memory\n" + "pip405 flash floppy [SrcAddr] - updates U-Boot with image from floppy\n" + "pip405 flash mps - updates U-Boot with image from MPS" +); + +/* ------------------------------------------------------------------------- */ diff --git a/qemu/roms/u-boot/board/mpl/pip405/init.S b/qemu/roms/u-boot/board/mpl/pip405/init.S new file mode 100644 index 000000000..292393ec4 --- /dev/null +++ b/qemu/roms/u-boot/board/mpl/pip405/init.S @@ -0,0 +1,197 @@ +/* + * SPDX-License-Identifier: GPL-2.0 IBM-pibs + */ +/*----------------------------------------------------------------------------- + * Function: ext_bus_cntlr_init + * Description: Initializes the External Bus Controller for the external + * peripherals. IMPORTANT: For pass1 this code must run from + * cache since you can not reliably change a peripheral banks + * timing register (pbxap) while running code from that bank. + * For ex., since we are running from ROM on bank 0, we can NOT + * execute the code that modifies bank 0 timings from ROM, so + * we run it from cache. + * Bank 0 - Flash or Multi Purpose Socket + * Bank 1 - Multi Purpose Socket or Flash + * Bank 2 - not used + * Bank 3 - not used + * Bank 4 - not used + * Bank 5 - not used + * Bank 6 - used to switch on the 12V for the Multipurpose socket + * Bank 7 - Config Register + *-----------------------------------------------------------------------------*/ + +#include <configs/PIP405.h> +#include <ppc_asm.tmpl> +#include <ppc_defs.h> + +#include <asm/cache.h> +#include <asm/mmu.h> +#include <asm/ppc4xx.h> +#include "pip405.h" + + .globl ext_bus_cntlr_init + ext_bus_cntlr_init: + mflr r4 /* save link register */ + mfdcr r3,CPC0_PSR /* get strapping reg */ + andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */ + bnelr /* jump back if PCI boot */ + + bl ..getAddr +..getAddr: + mflr r3 /* get address of ..getAddr */ + mtlr r4 /* restore link register */ + addi r4,0,14 /* set ctr to 14; used to prefetch */ + mtctr r4 /* 14 cache lines to fit this function */ + /* in cache (gives us 8x14=112 instrctns) */ +..ebcloop: + icbt r0,r3 /* prefetch cache line for addr in r3 */ + addi r3,r3,32 /* move to next cache line */ + bdnz ..ebcloop /* continue for 14 cache lines */ + + /*------------------------------------------------------------------- + * Delay to ensure all accesses to ROM are complete before changing + * bank 0 timings. + *------------------------------------------------------------------- */ + addis r3,0,0x0 + ori r3,r3,0xA000 + mtctr r3 +..spinlp: + bdnz ..spinlp /* spin loop */ + + /*----------------------------------------------------------------------- + * decide boot up mode + *----------------------------------------------------------------------- */ + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 + mfdcr r4,EBC0_CFGDATA + + andi. r0, r4, 0x2000 /* mask out irrelevant bits */ + beq 0f /* jump if 8 bit bus width */ + + /* setup 16 bit things + *----------------------------------------------------------------------- + * Memory Bank 0 (16 Bit Flash) initialization + *---------------------------------------------------------------------- */ + + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 + addis r4,0,(FLASH_AP_B)@h + ori r4,r4,(FLASH_AP_B)@l + mtdcr EBC0_CFGDATA,r4 + + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 + /* BS=0x010(4MB),BU=0x3(R/W), */ + addis r4,0,(FLASH_CR_B)@h + ori r4,r4,(FLASH_CR_B)@l + mtdcr EBC0_CFGDATA,r4 + b 1f + +0: + /* 8Bit boot mode: */ + /*----------------------------------------------------------------------- + * Memory Bank 0 Multi Purpose Socket initialization + *----------------------------------------------------------------------- */ + /* 0x7F8FFE80 slowest boot */ + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 + addis r4,0,(MPS_AP_B)@h + ori r4,r4,(MPS_AP_B)@l + mtdcr EBC0_CFGDATA,r4 + + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 + /* BS=0x010(4MB),BU=0x3(R/W), */ + addis r4,0,(MPS_CR_B)@h + ori r4,r4,(MPS_CR_B)@l + mtdcr EBC0_CFGDATA,r4 + + +1: + /*----------------------------------------------------------------------- + * Memory Bank 2-3-4-5-6 (not used) initialization + *-----------------------------------------------------------------------*/ + addi r4,0,PB1CR + mtdcr EBC0_CFGADDR,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr EBC0_CFGDATA,r4 + + addi r4,0,PB2CR + mtdcr EBC0_CFGADDR,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr EBC0_CFGDATA,r4 + + addi r4,0,PB3CR + mtdcr EBC0_CFGADDR,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr EBC0_CFGDATA,r4 + + addi r4,0,PB4CR + mtdcr EBC0_CFGADDR,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr EBC0_CFGDATA,r4 + + addi r4,0,PB5CR + mtdcr EBC0_CFGADDR,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr EBC0_CFGDATA,r4 + + addi r4,0,PB6CR + mtdcr EBC0_CFGADDR,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr EBC0_CFGDATA,r4 + + addi r4,0,PB7CR + mtdcr EBC0_CFGADDR,r4 + addis r4,0,0x0000 + ori r4,r4,0x0000 + mtdcr EBC0_CFGDATA,r4 + nop /* pass2 DCR errata #8 */ + blr + +#if defined(CONFIG_BOOT_PCI) + .section .bootpg,"ax" + .globl _start_pci +/******************************************* + */ + +_start_pci: + /* first handle errata #68 / PCI_18 */ + iccci r0, r0 /* invalidate I-cache */ + lis r31, 0 + mticcr r31 /* ICCR = 0 (all uncachable) */ + isync + + mfccr0 r28 /* set CCR0[24] = 1 */ + ori r28, r28, 0x0080 + mtccr0 r28 + + /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */ + lis r28, 0xEF40 + addi r28, r28, 0x0004 + stw r31, 0x0C(r28) /* clear PMM0PCIHA */ + lis r29, 0xFFF8 /* open 512 kByte */ + addi r29, r29, 0x0001/* and enable this region */ + stwbrx r29, r0, r28 /* write PMM0MA */ + + lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */ + addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */ + + lis r31, 0x8000 /* set en bit bus 0 */ + ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */ + stwbrx r31, r0, r28 /* write it */ + + lwbrx r31, r0, r29 /* load XBCS register */ + oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */ + stwbrx r31, r0, r29 /* write back XBCS register */ + + nop + nop + b _start /* normal start */ +#endif diff --git a/qemu/roms/u-boot/board/mpl/pip405/pip405.c b/qemu/roms/u-boot/board/mpl/pip405/pip405.c new file mode 100644 index 000000000..7c7690ff5 --- /dev/null +++ b/qemu/roms/u-boot/board/mpl/pip405/pip405.c @@ -0,0 +1,956 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * SPDX-License-Identifier: GPL-2.0+ + * + * TODO: clean-up + */ + +#include <common.h> +#include "pip405.h" +#include <asm/processor.h> +#include <i2c.h> +#include <stdio_dev.h> +#include "../common/isa.h" +#include "../common/common_util.h" + +DECLARE_GLOBAL_DATA_PTR; + +#undef SDRAM_DEBUG + +/* stdlib.h causes some compatibility problems; should fixe these! -- wd */ +#ifndef __ldiv_t_defined +typedef struct { + long int quot; /* Quotient */ + long int rem; /* Remainder */ +} ldiv_t; +extern ldiv_t ldiv (long int __numer, long int __denom); + +# define __ldiv_t_defined 1 +#endif + + +typedef enum { + SDRAM_NO_ERR, + SDRAM_SPD_COMM_ERR, + SDRAM_SPD_CHKSUM_ERR, + SDRAM_UNSUPPORTED_ERR, + SDRAM_UNKNOWN_ERR +} SDRAM_ERR; + +typedef struct { + const unsigned char mode; + const unsigned char row; + const unsigned char col; + const unsigned char bank; +} SDRAM_SETUP; + +static const SDRAM_SETUP sdram_setup_table[] = { + {1, 11, 9, 2}, + {1, 11, 10, 2}, + {2, 12, 9, 4}, + {2, 12, 10, 4}, + {3, 13, 9, 4}, + {3, 13, 10, 4}, + {3, 13, 11, 4}, + {4, 12, 8, 2}, + {4, 12, 8, 4}, + {5, 11, 8, 2}, + {5, 11, 8, 4}, + {6, 13, 8, 2}, + {6, 13, 8, 4}, + {7, 13, 9, 2}, + {7, 13, 10, 2}, + {0, 0, 0, 0} +}; + +static const unsigned char cal_indextable[] = { + 9, 23, 25 +}; + + +/* + * translate ns.ns/10 coding of SPD timing values + * into 10 ps unit values + */ + +unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version) +{ + unsigned short ns, ns10; + + /* isolate upper nibble */ + ns = (spd_byte >> 4) & 0x0F; + /* isolate lower nibble */ + ns10 = (spd_byte & 0x0F); + + return (ns * 100 + ns10 * 10); +} + +/* + * translate ns.ns/4 coding of SPD timing values + * into 10 ps unit values + */ + +unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version) +{ + unsigned short ns, ns4; + + /* isolate upper 6 bits */ + ns = (spd_byte >> 2) & 0x3F; + /* isloate lower 2 bits */ + ns4 = (spd_byte & 0x03); + + return (ns * 100 + ns4 * 25); +} + +/* + * translate ns coding of SPD timing values + * into 10 ps unit values + */ + +unsigned short NSto10PS (unsigned char spd_byte) +{ + return (spd_byte * 100); +} + +void SDRAM_err (const char *s) +{ +#ifndef SDRAM_DEBUG + (void) get_clocks (); + gd->baudrate = 9600; + serial_init (); +#endif + serial_puts ("\n"); + serial_puts (s); + serial_puts ("\n enable SDRAM_DEBUG for more info\n"); + for (;;); +} + + +#ifdef SDRAM_DEBUG + +void write_hex (unsigned char i) +{ + char cc; + + cc = i >> 4; + cc &= 0xf; + if (cc > 9) + serial_putc (cc + 55); + else + serial_putc (cc + 48); + cc = i & 0xf; + if (cc > 9) + serial_putc (cc + 55); + else + serial_putc (cc + 48); +} + +void write_4hex (unsigned long val) +{ + write_hex ((unsigned char) (val >> 24)); + write_hex ((unsigned char) (val >> 16)); + write_hex ((unsigned char) (val >> 8)); + write_hex ((unsigned char) val); +} + +#endif + +int board_early_init_f (void) +{ + unsigned char datain[128]; + unsigned long sdram_size = 0; + SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table; + unsigned long memclk; + unsigned long tmemclk = 0; + unsigned long tmp, bank, baseaddr, bank_size; + unsigned short i; + unsigned char rows, cols, banks, sdram_banks, density; + unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks, + trc_clocks; + unsigned char cal_index, cal_val, spd_version, spd_chksum; + unsigned char buf[8]; +#ifdef SDRAM_DEBUG + unsigned char tctp_clocks; +#endif + + /* set up the config port */ + mtdcr (EBC0_CFGADDR, PB7AP); + mtdcr (EBC0_CFGDATA, CONFIG_PORT_AP); + mtdcr (EBC0_CFGADDR, PB7CR); + mtdcr (EBC0_CFGDATA, CONFIG_PORT_CR); + + memclk = get_bus_freq (tmemclk); + tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ + +#ifdef SDRAM_DEBUG + (void) get_clocks (); + gd->baudrate = 9600; + serial_init (); + serial_puts ("\nstart SDRAM Setup\n"); +#endif + + /* Read Serial Presence Detect Information */ + i2c_set_bus_num(0); + for (i = 0; i < 128; i++) + datain[i] = 127; + i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128); +#ifdef SDRAM_DEBUG + serial_puts ("\ni2c_read returns "); + write_hex (i); + serial_puts ("\n"); +#endif + +#ifdef SDRAM_DEBUG + for (i = 0; i < 128; i++) { + write_hex (datain[i]); + serial_puts (" "); + if (((i + 1) % 16) == 0) + serial_puts ("\n"); + } + serial_puts ("\n"); +#endif + spd_chksum = 0; + for (i = 0; i < 63; i++) { + spd_chksum += datain[i]; + } /* endfor */ + if (datain[63] != spd_chksum) { +#ifdef SDRAM_DEBUG + serial_puts ("SPD chksum: 0x"); + write_hex (datain[63]); + serial_puts (" != calc. chksum: 0x"); + write_hex (spd_chksum); + serial_puts ("\n"); +#endif + SDRAM_err ("SPD checksum Error"); + } + /* SPD seems to be ok, use it */ + + /* get SPD version */ + spd_version = datain[62]; + + /* do some sanity checks on the kind of RAM */ + if ((datain[0] < 0x80) || /* less than 128 valid bytes in SPD */ + (datain[2] != 0x04) || /* if not SDRAM */ + (!((datain[6] == 0x40) || (datain[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */ + (datain[7] != 0x00) || (datain[8] != 0x01) || /* or not LVTTL signal levels */ + (datain[126] == 0x66)) /* or a 66MHz modules */ + SDRAM_err ("unsupported SDRAM"); +#ifdef SDRAM_DEBUG + serial_puts ("SDRAM sanity ok\n"); +#endif + + /* get number of rows/cols/banks out of byte 3+4+5 */ + rows = datain[3]; + cols = datain[4]; + banks = datain[5]; + + /* get number of SDRAM banks out of byte 17 and + supported CAS latencies out of byte 18 */ + sdram_banks = datain[17]; + supported_cal = datain[18] & ~0x81; + + while (t->mode != 0) { + if ((t->row == rows) && (t->col == cols) + && (t->bank == sdram_banks)) + break; + t++; + } /* endwhile */ + +#ifdef SDRAM_DEBUG + serial_puts ("rows: "); + write_hex (rows); + serial_puts (" cols: "); + write_hex (cols); + serial_puts (" banks: "); + write_hex (banks); + serial_puts (" mode: "); + write_hex (t->mode); + serial_puts ("\n"); +#endif + if (t->mode == 0) + SDRAM_err ("unsupported SDRAM"); + /* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */ +#ifdef SDRAM_DEBUG + serial_puts ("tRP: "); + write_hex (datain[27]); + serial_puts ("\ntRCD: "); + write_hex (datain[29]); + serial_puts ("\ntRAS: "); + write_hex (datain[30]); + serial_puts ("\n"); +#endif + + trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk; + trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk; + tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk; + density = datain[31]; + + /* trc_clocks is sum of trp_clocks + tras_clocks */ + trc_clocks = trp_clocks + tras_clocks; + +#ifdef SDRAM_DEBUG + /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ + tctp_clocks = + ((NSto10PS (datain[30]) - NSto10PS (datain[29])) + + (tmemclk - 1)) / tmemclk; + + serial_puts ("c_RP: "); + write_hex (trp_clocks); + serial_puts ("\nc_RCD: "); + write_hex (trcd_clocks); + serial_puts ("\nc_RAS: "); + write_hex (tras_clocks); + serial_puts ("\nc_RC: (RP+RAS): "); + write_hex (trc_clocks); + serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): "); + write_hex (tctp_clocks); + serial_puts ("\nt_CTP: RAS - RCD: "); + write_hex ((unsigned + char) ((NSto10PS (datain[30]) - + NSto10PS (datain[29])) >> 8)); + write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29]))); + serial_puts ("\ntmemclk: "); + write_hex ((unsigned char) (tmemclk >> 8)); + write_hex ((unsigned char) (tmemclk)); + serial_puts ("\n"); +#endif + + + cal_val = 255; + for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) { + /* is this CAS latency supported ? */ + if ((supported_cal >> i) & 0x01) { + buf[0] = datain[cal_indextable[cal_index]]; + if (cal_index < 2) { + if (NS10to10PS (buf[0], spd_version) <= tmemclk) + cal_val = i; + } else { + /* SPD bytes 25+26 have another format */ + if (NS4to10PS (buf[0], spd_version) <= tmemclk) + cal_val = i; + } /* endif */ + cal_index++; + } /* endif */ + } /* endfor */ +#ifdef SDRAM_DEBUG + serial_puts ("CAL: "); + write_hex (cal_val + 1); + serial_puts ("\n"); +#endif + + if (cal_val == 255) + SDRAM_err ("unsupported SDRAM"); + + /* get SDRAM timing register */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); + tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; + /* insert CASL value */ +/* tmp |= ((unsigned long)cal_val) << 23; */ + tmp |= ((unsigned long) cal_val) << 23; + /* insert PTA value */ + tmp |= ((unsigned long) (trp_clocks - 1)) << 18; + /* insert CTP value */ +/* tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */ + tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16; + /* insert LDF (always 01) */ + tmp |= ((unsigned long) 0x01) << 14; + /* insert RFTA value */ + tmp |= ((unsigned long) (trc_clocks - 4)) << 2; + /* insert RCD value */ + tmp |= ((unsigned long) (trcd_clocks - 1)) << 0; + +#ifdef SDRAM_DEBUG + serial_puts ("sdtr: "); + write_4hex (tmp); + serial_puts ("\n"); +#endif + + /* write SDRAM timing register */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); + mtdcr (SDRAM0_CFGDATA, tmp); + baseaddr = CONFIG_SYS_SDRAM_BASE; + bank_size = (((unsigned long) density) << 22) / 2; + /* insert AM value */ + tmp = ((unsigned long) t->mode - 1) << 13; + /* insert SZ value; */ + switch (bank_size) { + case 0x00400000: + tmp |= ((unsigned long) 0x00) << 17; + break; + case 0x00800000: + tmp |= ((unsigned long) 0x01) << 17; + break; + case 0x01000000: + tmp |= ((unsigned long) 0x02) << 17; + break; + case 0x02000000: + tmp |= ((unsigned long) 0x03) << 17; + break; + case 0x04000000: + tmp |= ((unsigned long) 0x04) << 17; + break; + case 0x08000000: + tmp |= ((unsigned long) 0x05) << 17; + break; + case 0x10000000: + tmp |= ((unsigned long) 0x06) << 17; + break; + default: + SDRAM_err ("unsupported SDRAM"); + } /* endswitch */ + /* get SDRAM bank 0 register */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); + bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; + bank |= (baseaddr | tmp | 0x01); +#ifdef SDRAM_DEBUG + serial_puts ("bank0: baseaddr: "); + write_4hex (baseaddr); + serial_puts (" banksize: "); + write_4hex (bank_size); + serial_puts (" mb0cf: "); + write_4hex (bank); + serial_puts ("\n"); +#endif + baseaddr += bank_size; + sdram_size += bank_size; + + /* write SDRAM bank 0 register */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); + mtdcr (SDRAM0_CFGDATA, bank); + + /* get SDRAM bank 1 register */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); + bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; + sdram_size = 0; + +#ifdef SDRAM_DEBUG + serial_puts ("bank1: baseaddr: "); + write_4hex (baseaddr); + serial_puts (" banksize: "); + write_4hex (bank_size); +#endif + if (banks == 2) { + bank |= (baseaddr | tmp | 0x01); + baseaddr += bank_size; + sdram_size += bank_size; + } /* endif */ +#ifdef SDRAM_DEBUG + serial_puts (" mb1cf: "); + write_4hex (bank); + serial_puts ("\n"); +#endif + /* write SDRAM bank 1 register */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); + mtdcr (SDRAM0_CFGDATA, bank); + + /* get SDRAM bank 2 register */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); + bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; + + bank |= (baseaddr | tmp | 0x01); + +#ifdef SDRAM_DEBUG + serial_puts ("bank2: baseaddr: "); + write_4hex (baseaddr); + serial_puts (" banksize: "); + write_4hex (bank_size); + serial_puts (" mb2cf: "); + write_4hex (bank); + serial_puts ("\n"); +#endif + + baseaddr += bank_size; + sdram_size += bank_size; + + /* write SDRAM bank 2 register */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); + mtdcr (SDRAM0_CFGDATA, bank); + + /* get SDRAM bank 3 register */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); + bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; + +#ifdef SDRAM_DEBUG + serial_puts ("bank3: baseaddr: "); + write_4hex (baseaddr); + serial_puts (" banksize: "); + write_4hex (bank_size); +#endif + + if (banks == 2) { + bank |= (baseaddr | tmp | 0x01); + baseaddr += bank_size; + sdram_size += bank_size; + } + /* endif */ +#ifdef SDRAM_DEBUG + serial_puts (" mb3cf: "); + write_4hex (bank); + serial_puts ("\n"); +#endif + + /* write SDRAM bank 3 register */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); + mtdcr (SDRAM0_CFGDATA, bank); + + + /* get SDRAM refresh interval register */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); + tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; + + if (tmemclk < NSto10PS (16)) + tmp |= 0x05F00000; + else + tmp |= 0x03F80000; + + /* write SDRAM refresh interval register */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); + mtdcr (SDRAM0_CFGDATA, tmp); + + /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); + tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000; + mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); + mtdcr (SDRAM0_CFGDATA, tmp); + + + /*-------------------------------------------------------------------------+ + | Interrupt controller setup for the PIP405 board. + | Note: IRQ 0-15 405GP internally generated; active high; level sensitive + | IRQ 16 405GP internally generated; active low; level sensitive + | IRQ 17-24 RESERVED + | IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive + | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive + | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive + | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive + | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive + | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive + | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive + | Note for PIP405 board: + | An interrupt taken for the SouthBridge (IRQ 25) indicates that + | the Interrupt Controller in the South Bridge has caused the + | interrupt. The IC must be read to determine which device + | caused the interrupt. + | + +-------------------------------------------------------------------------*/ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */ + mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + + return 0; +} + +int board_early_init_r(void) +{ + int mode; + + /* + * since we are relocated, we can finally enable i-cache + * and set up the flash CS correctly + */ + icache_enable(); + setup_cs_reloc(); + /* get and display boot mode */ + mode = get_boot_mode(); + if (mode & BOOT_PCI) + printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ? + "MPS" : "Flash"); + else + printf("%s Boot\n", (mode & BOOT_MPS) ? + "MPS" : "Flash"); + + return 0; +} +/* ------------------------------------------------------------------------- */ + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + char s[50]; + unsigned char bc; + int i; + backup_t *b = (backup_t *) s; + + puts ("Board: "); + + i = getenv_f("serial#", (char *)s, 32); + if ((i == 0) || strncmp ((char *)s, "PIP405", 6)) { + get_backup_values (b); + if (strncmp (b->signature, "MPL\0", 4) != 0) { + puts ("### No HW ID - assuming PIP405"); + } else { + b->serial_name[6] = 0; + printf ("%s SN: %s", b->serial_name, + &b->serial_name[7]); + } + } else { + s[6] = 0; + printf ("%s SN: %s", s, &s[7]); + } + bc = in8 (CONFIG_PORT_ADDR); + printf (" Boot Config: 0x%x\n", bc); + return (0); +} + + +/* ------------------------------------------------------------------------- */ +/* ------------------------------------------------------------------------- */ +/* + initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of + the necessary info for SDRAM controller configuration +*/ +/* ------------------------------------------------------------------------- */ +/* ------------------------------------------------------------------------- */ +static int test_dram (unsigned long ramsize); + +phys_size_t initdram (int board_type) +{ + unsigned long bank_reg[4], tmp, bank_size; + int i, ds; + unsigned long TotalSize; + + ds = 0; + /* since the DRAM controller is allready set up, + * calculate the size with the bank registers + */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); + bank_reg[0] = mfdcr (SDRAM0_CFGDATA); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); + bank_reg[1] = mfdcr (SDRAM0_CFGDATA); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); + bank_reg[2] = mfdcr (SDRAM0_CFGDATA); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); + bank_reg[3] = mfdcr (SDRAM0_CFGDATA); + TotalSize = 0; + for (i = 0; i < 4; i++) { + if ((bank_reg[i] & 0x1) == 0x1) { + tmp = (bank_reg[i] >> 17) & 0x7; + bank_size = 4 << tmp; + TotalSize += bank_size; + } else + ds = 1; + } + if (ds == 1) + printf ("single-sided DIMM "); + else + printf ("double-sided DIMM "); + test_dram (TotalSize * 1024 * 1024); + /* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */ + (void) get_clocks(); + if (gd->cpu_clk > 220000000) + TotalSize /= 2; + return (TotalSize * 1024 * 1024); +} + +/* ------------------------------------------------------------------------- */ + + +static int test_dram (unsigned long ramsize) +{ + /* not yet implemented */ + return (1); +} + +int misc_init_r (void) +{ + /* adjust flash start and size as well as the offset */ + gd->bd->bi_flashstart=0-flash_info[0].size; + gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN; + gd->bd->bi_flashoffset=0; + + /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ + if (mfdcr(CPC0_PSR) & PSR_ROM_LOC) + mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80)); + + return (0); +} + +/*************************************************************************** + * some helping routines + */ + +int overwrite_console (void) +{ + /* return true if console should be overwritten */ + return in8(CONFIG_PORT_ADDR) & 0x1; +} + + +extern int isa_init (void); + + +void print_pip405_rev (void) +{ + unsigned char part, vers, cfg; + + part = in8 (PLD_PART_REG); + vers = in8 (PLD_VERS_REG); + cfg = in8 (PLD_BOARD_CFG_REG); + printf ("Rev: PIP405-%d Rev %c PLD%d %d PLD%d %d\n", + 16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf, + vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf); +} + +extern void check_env(void); + + +int last_stage_init (void) +{ + print_pip405_rev (); + isa_init (); + stdio_print_current_devices (); + check_env(); + return 0; +} + +/************************************************************************ +* Print PIP405 Info +************************************************************************/ +void print_pip405_info (void) +{ + unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr, + compwr, nicvga, scsirst; + + part = in8 (PLD_PART_REG); + vers = in8 (PLD_VERS_REG); + cfg = in8 (PLD_BOARD_CFG_REG); + ledu = in8 (PLD_LED_USER_REG); + sysman = in8 (PLD_SYS_MAN_REG); + flashcom = in8 (PLD_FLASH_COM_REG); + can = in8 (PLD_CAN_REG); + serpwr = in8 (PLD_SER_PWR_REG); + compwr = in8 (PLD_COM_PWR_REG); + nicvga = in8 (PLD_NIC_VGA_REG); + scsirst = in8 (PLD_SCSI_RST_REG); + printf ("PLD Part %d version %d\n", + part & 0xf, vers & 0xf); + printf ("PLD Part %d version %d\n", + (part >> 4) & 0xf, (vers >> 4) & 0xf); + printf ("Board Revision %c\n", (cfg & 0xf) + 'A'); + printf ("Population Options %d %d %d %d\n", + (cfg >> 4) & 0x1, (cfg >> 5) & 0x1, + (cfg >> 6) & 0x1, (cfg >> 7) & 0x1); + printf ("User LED0 %s User LED1 %s\n", + ((ledu & 0x1) == 0x1) ? "on" : "off", + ((ledu & 0x2) == 0x2) ? "on" : "off"); + printf ("Additionally Options %d %d\n", + (ledu >> 2) & 0x1, (ledu >> 3) & 0x1); + printf ("User Config Switch %d %d %d %d\n", + (ledu >> 4) & 0x1, (ledu >> 5) & 0x1, + (ledu >> 6) & 0x1, (ledu >> 7) & 0x1); + switch (sysman & 0x3) { + case 0: + printf ("PCI Clocks are running\n"); + break; + case 1: + printf ("PCI Clocks are stopped in POS State\n"); + break; + case 2: + printf ("PCI Clocks are stopped when PCI_STP# is asserted\n"); + break; + case 3: + printf ("PCI Clocks are stopped\n"); + break; + } + switch ((sysman >> 2) & 0x3) { + case 0: + printf ("Main Clocks are running\n"); + break; + case 1: + printf ("Main Clocks are stopped in POS State\n"); + break; + case 2: + case 3: + printf ("PCI Clocks are stopped\n"); + break; + } + printf ("INIT asserts %sINT2# (SMI)\n", + ((sysman & 0x10) == 0x10) ? "" : "not "); + printf ("INIT asserts %sINT1# (NMI)\n", + ((sysman & 0x20) == 0x20) ? "" : "not "); + printf ("INIT occured %d\n", (sysman >> 6) & 0x1); + printf ("SER1 is routed to %s\n", + ((flashcom & 0x1) == 0x1) ? "RS485" : "RS232"); + printf ("COM2 is routed to %s\n", + ((flashcom & 0x2) == 0x2) ? "RS485" : "RS232"); + printf ("RS485 is configured as %s duplex\n", + ((flashcom & 0x4) == 0x4) ? "full" : "half"); + printf ("RS485 is connected to %s\n", + ((flashcom & 0x8) == 0x8) ? "COM1" : "COM2"); + printf ("SER1 uses handshakes %s\n", + ((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS"); + printf ("Bootflash is %swriteprotected\n", + ((flashcom & 0x20) == 0x20) ? "not " : ""); + printf ("Bootflash VPP is %s\n", + ((flashcom & 0x40) == 0x40) ? "on" : "off"); + printf ("Bootsector is %swriteprotected\n", + ((flashcom & 0x80) == 0x80) ? "not " : ""); + switch ((can) & 0x3) { + case 0: + printf ("CAN Controller is on address 0x1000..0x10FF\n"); + break; + case 1: + printf ("CAN Controller is on address 0x8000..0x80FF\n"); + break; + case 2: + printf ("CAN Controller is on address 0xE000..0xE0FF\n"); + break; + case 3: + printf ("CAN Controller is disabled\n"); + break; + } + switch ((can >> 2) & 0x3) { + case 0: + printf ("CAN Controller Reset is ISA Reset\n"); + break; + case 1: + printf ("CAN Controller Reset is ISA Reset and POS State\n"); + break; + case 2: + case 3: + printf ("CAN Controller is in reset\n"); + break; + } + if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13)) + printf ("CAN Interrupt is disabled\n"); + else + printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf); + switch (serpwr & 0x3) { + case 0: + printf ("SER0 Drivers are enabled\n"); + break; + case 1: + printf ("SER0 Drivers are disabled in the POS state\n"); + break; + case 2: + case 3: + printf ("SER0 Drivers are disabled\n"); + break; + } + switch ((serpwr >> 2) & 0x3) { + case 0: + printf ("SER1 Drivers are enabled\n"); + break; + case 1: + printf ("SER1 Drivers are disabled in the POS state\n"); + break; + case 2: + case 3: + printf ("SER1 Drivers are disabled\n"); + break; + } + switch (compwr & 0x3) { + case 0: + printf ("COM1 Drivers are enabled\n"); + break; + case 1: + printf ("COM1 Drivers are disabled in the POS state\n"); + break; + case 2: + case 3: + printf ("COM1 Drivers are disabled\n"); + break; + } + switch ((compwr >> 2) & 0x3) { + case 0: + printf ("COM2 Drivers are enabled\n"); + break; + case 1: + printf ("COM2 Drivers are disabled in the POS state\n"); + break; + case 2: + case 3: + printf ("COM2 Drivers are disabled\n"); + break; + } + switch ((nicvga) & 0x3) { + case 0: + printf ("PHY is running\n"); + break; + case 1: + printf ("PHY is in Power save mode in POS state\n"); + break; + case 2: + case 3: + printf ("PHY is in Power save mode\n"); + break; + } + switch ((nicvga >> 2) & 0x3) { + case 0: + printf ("VGA is running\n"); + break; + case 1: + printf ("VGA is in Power save mode in POS state\n"); + break; + case 2: + case 3: + printf ("VGA is in Power save mode\n"); + break; + } + printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not "); + printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not "); + printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1, + (nicvga >> 7) & 0x1); + switch ((scsirst) & 0x3) { + case 0: + printf ("SCSI Controller is running\n"); + break; + case 1: + printf ("SCSI Controller is in Power save mode in POS state\n"); + break; + case 2: + case 3: + printf ("SCSI Controller is in Power save mode\n"); + break; + } + printf ("SCSI termination is %s\n", + ((scsirst & 0x4) == 0x4) ? "disabled" : "enabled"); + printf ("SCSI Controller is %sreseted\n", + ((scsirst & 0x10) == 0x10) ? "" : "not "); + printf ("IDE disks are %sreseted\n", + ((scsirst & 0x20) == 0x20) ? "" : "not "); + printf ("ISA Bus is %sreseted\n", + ((scsirst & 0x40) == 0x40) ? "" : "not "); + printf ("Super IO is %sreseted\n", + ((scsirst & 0x80) == 0x80) ? "" : "not "); +} + +void user_led0 (unsigned char on) +{ + if (on == true) + out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1)); + else + out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe)); +} + +void user_led1 (unsigned char on) +{ + if (on == true) + out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2)); + else + out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd)); +} + +void ide_set_reset (int idereset) +{ + /* if reset = 1 IDE reset will be asserted */ + unsigned char resreg; + + resreg = in8 (PLD_SCSI_RST_REG); + if (idereset == 1) + resreg |= 0x20; + else { + udelay(10000); + resreg &= 0xdf; + } + out8 (PLD_SCSI_RST_REG, resreg); +} diff --git a/qemu/roms/u-boot/board/mpl/pip405/pip405.h b/qemu/roms/u-boot/board/mpl/pip405/pip405.h new file mode 100644 index 000000000..1f07d792a --- /dev/null +++ b/qemu/roms/u-boot/board/mpl/pip405/pip405.h @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch + * + * SPDX-License-Identifier: GPL-2.0+ + */ + /**************************************************************************** + * Global routines used for PIP405 + *****************************************************************************/ + +#ifndef __ASSEMBLY__ + +extern int mem_test(unsigned long start, unsigned long ramsize,int mode); + +void print_pip405_info(void); + +void user_led0(unsigned char on); +void user_led1(unsigned char on); + + +#define PLD_BASE_ADDRESS CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x800 +#define PLD_PART_REG PLD_BASE_ADDRESS + 0 +#define PLD_VERS_REG PLD_BASE_ADDRESS + 1 +#define PLD_BOARD_CFG_REG PLD_BASE_ADDRESS + 2 +#define PLD_LED_USER_REG PLD_BASE_ADDRESS + 3 +#define PLD_SYS_MAN_REG PLD_BASE_ADDRESS + 4 +#define PLD_FLASH_COM_REG PLD_BASE_ADDRESS + 5 +#define PLD_CAN_REG PLD_BASE_ADDRESS + 6 +#define PLD_SER_PWR_REG PLD_BASE_ADDRESS + 7 +#define PLD_COM_PWR_REG PLD_BASE_ADDRESS + 8 +#define PLD_NIC_VGA_REG PLD_BASE_ADDRESS + 9 +#define PLD_SCSI_RST_REG PLD_BASE_ADDRESS + 0xA + +#define PIIX4_VENDOR_ID 0x8086 +#define PIIX4_IDE_DEV_ID 0x7111 + +#endif + +/* timings */ + +/* CS Config register (CS7) */ +#define CONFIG_PORT_BME 0 /* Burst disable */ +#define CONFIG_PORT_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */ +#define CONFIG_PORT_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ +#define CONFIG_PORT_OEN 1 /* Cycles from CS low to OE low */ +#define CONFIG_PORT_WBN 1 /* Cycles from CS low to WE low */ +#define CONFIG_PORT_WBF 1 /* Cycles from WE high to CS high */ +#define CONFIG_PORT_TH 2 /* Number of hold cycles after transfer */ +#define CONFIG_PORT_RE 0 /* Ready disabled */ +#define CONFIG_PORT_SOR 1 /* Sample on Ready disabled */ +#define CONFIG_PORT_BEM 0 /* Byte Write only active on Write cycles */ +#define CONFIG_PORT_PEN 0 /* Parity disable */ +#define CONFIG_PORT_AP ((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \ + (CONFIG_PORT_WBF << 12) + (CONFIG_PORT_TH << 9) + (CONFIG_PORT_RE << 8) + (CONFIG_PORT_SOR << 7) + (CONFIG_PORT_BEM << 6) + (CONFIG_PORT_PEN << 5)) + +/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ +#define CONFIG_PORT_BS 0 /* 1 MByte */ +/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ +#define CONFIG_PORT_BU 3 /* R/W */ +/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ +#define CONFIG_PORT_BW 0 /* 16Bit */ +#define CONFIG_PORT_CR ((CONFIG_PORT_ADDR & 0xfff00000) + (CONFIG_PORT_BS << 17) + (CONFIG_PORT_BU << 15) + (CONFIG_PORT_BW << 13)) + +/* Flash CS0 or CS 1 */ +/* 0x7F8FFE80 slowest timing at all... */ +#define FLASH_BME_B 1 /* Burst enable */ +#define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */ +#define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ +#define FLASH_BME 0 /* Burst disable */ +#define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ +#define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ +#define FLASH_OEN 1 /* Cycles from CS low to OE low */ +#define FLASH_WBN 1 /* Cycles from CS low to WE low */ +#define FLASH_WBF 1 /* Cycles from WE high to CS high */ +#define FLASH_TH 2 /* Number of hold cycles after transfer */ +#define FLASH_RE 0 /* Ready disabled */ +#define FLASH_SOR 1 /* Sample on Ready disabled */ +#define FLASH_BEM 0 /* Byte Write only active on Write cycles */ +#define FLASH_PEN 0 /* Parity disable */ +/* Access Parameter Register for non Boot */ +#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ + (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) +/* Access Parameter Register for Boot */ +#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ + (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) + +/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ +#define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */ +/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ +#define FLASH_BU 3 /* R/W */ +/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ +#define FLASH_BW 1 /* 16Bit */ +/* CR register for Boot */ +#define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) +/* CR register for non Boot */ +#define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) + +/* MPS CS1 or CS0 */ +/* Boot CS: */ +#define MPS_BME_B 1 /* Burst enable */ +#define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */ +#define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ +#define MPS_BME 0 /* Burst disable */ +#define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ +#define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ +#define MPS_OEN 1 /* Cycles from CS low to OE low */ +#define MPS_WBN 1 /* Cycles from CS low to WE low */ +#define MPS_WBF 1 /* Cycles from WE high to CS high */ +#define MPS_TH 2 /* Number of hold cycles after transfer */ +#define MPS_RE 0 /* Ready disabled */ +#define MPS_SOR 1 /* Sample on Ready disabled */ +#define MPS_BEM 0 /* Byte Write only active on Write cycles */ +#define MPS_PEN 0 /* Parity disable */ +/* Access Parameter Register for non Boot */ +#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ + (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) +/* Access Parameter Register for Boot */ +#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ + (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) + +/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ +#define MPS_BS 2 /* 4 MByte */ +#define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */ +/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ +#define MPS_BU 3 /* R/W */ +/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ +#define MPS_BW 0 /* 8Bit */ +/* CR register for Boot */ +#define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13)) +/* CR register for non Boot */ +#define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13)) diff --git a/qemu/roms/u-boot/board/mpl/pip405/u-boot.lds.debug b/qemu/roms/u-boot/board/mpl/pip405/u-boot.lds.debug new file mode 100644 index 000000000..890f592e9 --- /dev/null +++ b/qemu/roms/u-boot/board/mpl/pip405/u-boot.lds.debug @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib/vsprintf.o (.text) + lib/crc32.o (.text) + arch/powerpc/lib/extable.o (.text) + + common/env_embedded.o(.text) + + *(.text) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + __bss_end = . ; + PROVIDE (end = .); +} |