diff options
Diffstat (limited to 'qemu/roms/u-boot/board/mcc200')
| -rw-r--r-- | qemu/roms/u-boot/board/mcc200/Makefile | 8 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/mcc200/auto_update.c | 526 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/mcc200/lcd.c | 200 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/mcc200/mcc200.c | 314 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/mcc200/mt46v16m16-75.h | 16 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/mcc200/mt48lc16m16a2-75.h | 14 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/mcc200/mt48lc16m32s2-75.h | 14 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/mcc200/mt48lc8m32b2-6-7.h | 12 |
8 files changed, 1104 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/board/mcc200/Makefile b/qemu/roms/u-boot/board/mcc200/Makefile new file mode 100644 index 000000000..db3b39646 --- /dev/null +++ b/qemu/roms/u-boot/board/mcc200/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mcc200.o lcd.o auto_update.o diff --git a/qemu/roms/u-boot/board/mcc200/auto_update.c b/qemu/roms/u-boot/board/mcc200/auto_update.c new file mode 100644 index 000000000..2f622b084 --- /dev/null +++ b/qemu/roms/u-boot/board/mcc200/auto_update.c @@ -0,0 +1,526 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <image.h> +#include <asm/byteorder.h> +#include <usb.h> +#include <part.h> + +#ifdef CONFIG_SYS_HUSH_PARSER +#include <hush.h> +#endif + + +#ifdef CONFIG_AUTO_UPDATE + +#ifndef CONFIG_USB_OHCI +#error "must define CONFIG_USB_OHCI" +#endif + +#ifndef CONFIG_USB_STORAGE +#error "must define CONFIG_USB_STORAGE" +#endif + +#ifndef CONFIG_SYS_HUSH_PARSER +#error "must define CONFIG_SYS_HUSH_PARSER" +#endif + +#if !defined(CONFIG_CMD_FAT) +#error "must define CONFIG_CMD_FAT" +#endif + +#undef AU_DEBUG + +#undef debug +#ifdef AU_DEBUG +#define debug(fmt,args...) printf (fmt ,##args) +#else +#define debug(fmt,args...) +#endif /* AU_DEBUG */ + +/* possible names of files on the USB stick. */ +#define AU_FIRMWARE "u-boot.img" +#define AU_KERNEL "kernel.img" +#define AU_ROOTFS "rootfs.img" + +struct flash_layout { + long start; + long end; +}; + +/* layout of the FLASH. ST = start address, ND = end address. */ +#define AU_FL_FIRMWARE_ST 0xfC000000 +#define AU_FL_FIRMWARE_ND 0xfC03FFFF +#define AU_FL_KERNEL_ST 0xfC0C0000 +#define AU_FL_KERNEL_ND 0xfC1BFFFF +#define AU_FL_ROOTFS_ST 0xFC1C0000 +#define AU_FL_ROOTFS_ND 0xFCFBFFFF + +static int au_usb_stor_curr_dev; /* current device */ + +/* index of each file in the following arrays */ +#define IDX_FIRMWARE 0 +#define IDX_KERNEL 1 +#define IDX_ROOTFS 2 + +/* max. number of files which could interest us */ +#define AU_MAXFILES 3 + +/* pointers to file names */ +char *aufile[AU_MAXFILES] = { + AU_FIRMWARE, + AU_KERNEL, + AU_ROOTFS +}; + +/* sizes of flash areas for each file */ +long ausize[AU_MAXFILES] = { + (AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST, + (AU_FL_KERNEL_ND + 1) - AU_FL_KERNEL_ST, + (AU_FL_ROOTFS_ND + 1) - AU_FL_ROOTFS_ST, +}; + +/* array of flash areas start and end addresses */ +struct flash_layout aufl_layout[AU_MAXFILES] = { + { AU_FL_FIRMWARE_ST, AU_FL_FIRMWARE_ND, }, + { AU_FL_KERNEL_ST, AU_FL_KERNEL_ND, }, + { AU_FL_ROOTFS_ST, AU_FL_ROOTFS_ND, }, +}; + +ulong totsize; + +/* where to load files into memory */ +#define LOAD_ADDR ((unsigned char *)0x00200000) + +/* the root file system is the largest image */ +#define MAX_LOADSZ ausize[IDX_ROOTFS] + +/*i2c address of the keypad status*/ +#define I2C_PSOC_KEYPAD_ADDR 0x53 + +/* keypad mask */ +#define KEYPAD_ROW 2 +#define KEYPAD_COL 2 +#define KEYPAD_MASK_LO ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))&0xFF) +#define KEYPAD_MASK_HI ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))>>8) + +/* externals */ +extern int fat_register_device(block_dev_desc_t *, int); +extern int file_fat_detectfs(void); +extern long file_fat_read(const char *, void *, unsigned long); +extern int i2c_read (unsigned char, unsigned int, int , unsigned char* , int); +extern int flash_sect_erase(ulong, ulong); +extern int flash_sect_protect (int, ulong, ulong); +extern int flash_write (char *, ulong, ulong); +extern int u_boot_hush_start(void); +#ifdef CONFIG_PROGRESSBAR +extern void show_progress(int, int); +extern void lcd_puts (char *); +extern void lcd_enable(void); +#endif + +int au_check_cksum_valid(int idx, long nbytes) +{ + image_header_t *hdr; + + hdr = (image_header_t *)LOAD_ADDR; +#if defined(CONFIG_FIT) + if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { + puts ("Non legacy image format not supported\n"); + return -1; + } +#endif + + if (nbytes != image_get_image_size (hdr)) { + printf ("Image %s bad total SIZE\n", aufile[idx]); + return -1; + } + /* check the data CRC */ + if (!image_check_dcrc (hdr)) { + printf ("Image %s bad data checksum\n", aufile[idx]); + return -1; + } + return 0; +} + +int au_check_header_valid(int idx, long nbytes) +{ + image_header_t *hdr; + unsigned long checksum, fsize; + + hdr = (image_header_t *)LOAD_ADDR; +#if defined(CONFIG_FIT) + if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { + puts ("Non legacy image format not supported\n"); + return -1; + } +#endif + + /* check the easy ones first */ +#undef CHECK_VALID_DEBUG +#ifdef CHECK_VALID_DEBUG + printf("magic %#x %#x ", image_get_magic (hdr), IH_MAGIC); + printf("arch %#x %#x ", image_get_arch (hdr), IH_ARCH_ARM); + printf("size %#x %#lx ", image_get_data_size (hdr), nbytes); + printf("type %#x %#x ", image_get_type (hdr), IH_TYPE_KERNEL); +#endif + if (nbytes < image_get_header_size ()) { + printf ("Image %s bad header SIZE\n", aufile[idx]); + ausize[idx] = 0; + return -1; + } + if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_PPC)) { + printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]); + ausize[idx] = 0; + return -1; + } + /* check the hdr CRC */ + if (!image_check_hcrc (hdr)) { + printf ("Image %s bad header checksum\n", aufile[idx]); + ausize[idx] = 0; + return -1; + } + /* check the type - could do this all in one gigantic if() */ + if ((idx == IDX_FIRMWARE) && !image_check_type (hdr, IH_TYPE_FIRMWARE)) { + printf ("Image %s wrong type\n", aufile[idx]); + ausize[idx] = 0; + return -1; + } + if ((idx == IDX_KERNEL) && !image_check_type (hdr, IH_TYPE_KERNEL)) { + printf ("Image %s wrong type\n", aufile[idx]); + ausize[idx] = 0; + return -1; + } + if ((idx == IDX_ROOTFS) && + (!image_check_type (hdr, IH_TYPE_RAMDISK) && + !image_check_type (hdr, IH_TYPE_FILESYSTEM))) { + printf ("Image %s wrong type\n", aufile[idx]); + ausize[idx] = 0; + return -1; + } + /* recycle checksum */ + checksum = image_get_data_size (hdr); + + fsize = checksum + image_get_header_size (); + /* for kernel and ramdisk the image header must also fit into flash */ + if (idx == IDX_KERNEL || image_check_type (hdr, IH_TYPE_RAMDISK)) + checksum += image_get_header_size (); + + /* check the size does not exceed space in flash. HUSH scripts */ + if ((ausize[idx] != 0) && (ausize[idx] < checksum)) { + printf ("Image %s is bigger than FLASH\n", aufile[idx]); + ausize[idx] = 0; + return -1; + } + /* Update with the real filesize */ + ausize[idx] = fsize; + + return checksum; /* return size to be written to flash */ +} + +int au_do_update(int idx, long sz) +{ + image_header_t *hdr; + char *addr; + long start, end; + int off, rc; + uint nbytes; + + hdr = (image_header_t *)LOAD_ADDR; +#if defined(CONFIG_FIT) + if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { + puts ("Non legacy image format not supported\n"); + return -1; + } +#endif + + /* execute a script */ + if (image_check_type (hdr, IH_TYPE_SCRIPT)) { + addr = (char *)((char *)hdr + image_get_header_size ()); + /* stick a NULL at the end of the script, otherwise */ + /* parse_string_outer() runs off the end. */ + addr[image_get_data_size (hdr)] = 0; + addr += 8; + parse_string_outer(addr, FLAG_PARSE_SEMICOLON); + return 0; + } + + start = aufl_layout[idx].start; + end = aufl_layout[idx].end; + + /* unprotect the address range */ + /* this assumes that ONLY the firmware is protected! */ + if (idx == IDX_FIRMWARE) { +#undef AU_UPDATE_TEST +#ifdef AU_UPDATE_TEST + /* erase it where Linux goes */ + start = aufl_layout[1].start; + end = aufl_layout[1].end; +#endif + flash_sect_protect(0, start, end); + } + + /* + * erase the address range. + */ + debug ("flash_sect_erase(%lx, %lx);\n", start, end); + flash_sect_erase(start, end); + mdelay(100); +#ifdef CONFIG_PROGRESSBAR + show_progress(end - start, totsize); +#endif + + /* strip the header - except for the kernel and ramdisk */ + if (image_check_type (hdr, IH_TYPE_KERNEL) || + image_check_type (hdr, IH_TYPE_RAMDISK)) { + addr = (char *)hdr; + off = image_get_header_size (); + nbytes = image_get_image_size (hdr); + } else { + addr = (char *)((char *)hdr + image_get_header_size ()); +#ifdef AU_UPDATE_TEST + /* copy it to where Linux goes */ + if (idx == IDX_FIRMWARE) + start = aufl_layout[1].start; +#endif + off = 0; + nbytes = image_get_data_size (hdr); + } + + /* copy the data from RAM to FLASH */ + debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes); + rc = flash_write(addr, start, nbytes); + if (rc != 0) { + printf("Flashing failed due to error %d\n", rc); + return -1; + } + +#ifdef CONFIG_PROGRESSBAR + show_progress(nbytes, totsize); +#endif + + /* check the data CRC of the copy */ + if (crc32 (0, (uchar *)(start + off), image_get_data_size (hdr)) != + image_get_dcrc (hdr)) { + printf ("Image %s Bad Data Checksum after COPY\n", aufile[idx]); + return -1; + } + + /* protect the address range */ + /* this assumes that ONLY the firmware is protected! */ + if (idx == IDX_FIRMWARE) + flash_sect_protect(1, start, end); + return 0; +} + +/* + * this is called from board_init() after the hardware has been set up + * and is usable. That seems like a good time to do this. + * Right now the return value is ignored. + */ +int do_auto_update(void) +{ + block_dev_desc_t *stor_dev; + long sz; + int i, res = 0, cnt, old_ctrlc; + char *env; + long start, end; + +#if 0 /* disable key-press detection to speed up boot-up time */ + uchar keypad_status1[2] = {0,0}, keypad_status2[2] = {0,0}; + + /* + * Read keypad status + */ + i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status1, 2); + mdelay(500); + i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status2, 2); + + /* + * Check keypad + */ + if ( !(keypad_status1[1] & KEYPAD_MASK_LO) || + (keypad_status1[1] != keypad_status2[1])) { + return 0; + } + +#endif + au_usb_stor_curr_dev = -1; + /* start USB */ + if (usb_stop() < 0) { + debug ("usb_stop failed\n"); + return -1; + } + if (usb_init() < 0) { + debug ("usb_init failed\n"); + return -1; + } + /* + * check whether a storage device is attached (assume that it's + * a USB memory stick, since nothing else should be attached). + */ + au_usb_stor_curr_dev = usb_stor_scan(0); + if (au_usb_stor_curr_dev == -1) { + debug ("No device found. Not initialized?\n"); + res = -1; + goto xit; + } + /* check whether it has a partition table */ + stor_dev = get_dev("usb", 0); + if (stor_dev == NULL) { + debug ("uknown device type\n"); + res = -1; + goto xit; + } + if (fat_register_device(stor_dev, 1) != 0) { + debug ("Unable to use USB %d:%d for fatls\n", + au_usb_stor_curr_dev, 1); + res = -1; + goto xit; + } + if (file_fat_detectfs() != 0) { + debug ("file_fat_detectfs failed\n"); + } + + /* + * now check whether start and end are defined using environment + * variables. + */ + start = -1; + end = 0; + env = getenv("firmware_st"); + if (env != NULL) + start = simple_strtoul(env, NULL, 16); + env = getenv("firmware_nd"); + if (env != NULL) + end = simple_strtoul(env, NULL, 16); + if (start >= 0 && end && end > start) { + ausize[IDX_FIRMWARE] = (end + 1) - start; + aufl_layout[IDX_FIRMWARE].start = start; + aufl_layout[IDX_FIRMWARE].end = end; + } + start = -1; + end = 0; + env = getenv("kernel_st"); + if (env != NULL) + start = simple_strtoul(env, NULL, 16); + env = getenv("kernel_nd"); + if (env != NULL) + end = simple_strtoul(env, NULL, 16); + if (start >= 0 && end && end > start) { + ausize[IDX_KERNEL] = (end + 1) - start; + aufl_layout[IDX_KERNEL].start = start; + aufl_layout[IDX_KERNEL].end = end; + } + start = -1; + end = 0; + env = getenv("rootfs_st"); + if (env != NULL) + start = simple_strtoul(env, NULL, 16); + env = getenv("rootfs_nd"); + if (env != NULL) + end = simple_strtoul(env, NULL, 16); + if (start >= 0 && end && end > start) { + ausize[IDX_ROOTFS] = (end + 1) - start; + aufl_layout[IDX_ROOTFS].start = start; + aufl_layout[IDX_ROOTFS].end = end; + } + + /* make certain that HUSH is runnable */ + u_boot_hush_start(); + /* make sure that we see CTRL-C and save the old state */ + old_ctrlc = disable_ctrlc(0); + + /* validate the images first */ + for (i = 0; i < AU_MAXFILES; i++) { + ulong imsize; + /* just read the header */ + sz = file_fat_read(aufile[i], LOAD_ADDR, image_get_header_size ()); + debug ("read %s sz %ld hdr %d\n", + aufile[i], sz, image_get_header_size ()); + if (sz <= 0 || sz < image_get_header_size ()) { + debug ("%s not found\n", aufile[i]); + ausize[i] = 0; + continue; + } + /* au_check_header_valid() updates ausize[] */ + if ((imsize = au_check_header_valid(i, sz)) < 0) { + debug ("%s header not valid\n", aufile[i]); + continue; + } + /* totsize accounts for image size and flash erase size */ + totsize += (imsize + (aufl_layout[i].end - aufl_layout[i].start)); + } + +#ifdef CONFIG_PROGRESSBAR + if (totsize) { + lcd_puts(" Update in progress\n"); + lcd_enable(); + } +#endif + + /* just loop thru all the possible files */ + for (i = 0; i < AU_MAXFILES && totsize; i++) { + if (!ausize[i]) { + continue; + } + sz = file_fat_read(aufile[i], LOAD_ADDR, ausize[i]); + + debug ("read %s sz %ld hdr %d\n", + aufile[i], sz, image_get_header_size ()); + + if (sz != ausize[i]) { + printf ("%s: size %ld read %ld?\n", aufile[i], ausize[i], sz); + continue; + } + + if (sz <= 0 || sz <= image_get_header_size ()) { + debug ("%s not found\n", aufile[i]); + continue; + } + if (au_check_cksum_valid(i, sz) < 0) { + debug ("%s checksum not valid\n", aufile[i]); + continue; + } + /* this is really not a good idea, but it's what the */ + /* customer wants. */ + cnt = 0; + do { + res = au_do_update(i, sz); + /* let the user break out of the loop */ + if (ctrlc() || had_ctrlc()) { + clear_ctrlc(); + break; + } + cnt++; +#ifdef AU_TEST_ONLY + } while (res < 0 && cnt < (AU_MAXFILES + 1)); + if (cnt < (AU_MAXFILES + 1)) +#else + } while (res < 0); +#endif + } + + /* restore the old state */ + disable_ctrlc(old_ctrlc); +#ifdef CONFIG_PROGRESSBAR + if (totsize) { + if (!res) { + lcd_puts("\n Update completed\n"); + } else { + lcd_puts("\n Update error\n"); + } + lcd_enable(); + } +#endif + xit: + usb_stop(); + return res; +} +#endif /* CONFIG_AUTO_UPDATE */ diff --git a/qemu/roms/u-boot/board/mcc200/lcd.c b/qemu/roms/u-boot/board/mcc200/lcd.c new file mode 100644 index 000000000..c911445d9 --- /dev/null +++ b/qemu/roms/u-boot/board/mcc200/lcd.c @@ -0,0 +1,200 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <lcd.h> +#include <mpc5xxx.h> +#include <malloc.h> + +#ifdef CONFIG_LCD + +#undef SWAPPED_LCD /* For the previous h/w version */ +/* + * The name of the device used for communication + * with the PSoC. + */ +#define PSOC_PSC MPC5XXX_PSC2 +#define PSOC_BAUD 230400UL + +#define RTS_ASSERT 1 +#define RTS_NEGATE 0 +#define CTS_ASSERT 1 +#define CTS_NEGATE 0 + +/* + * Dimensions in pixels + */ +#define LCD_WIDTH 160 +#define LCD_HEIGHT 100 + +/* + * Dimensions in bytes + */ +#define LCD_BUF_SIZE ((LCD_WIDTH*LCD_HEIGHT)>>3) + +#if LCD_BPP != LCD_MONOCHROME +#error "MCC200 support only monochrome displays (1 bpp)!" +#endif + +#define PSOC_RETRIES 10 /* each of PSOC_WAIT_TIME */ +#define PSOC_WAIT_TIME 10 /* usec */ + +#include <video_font.h> +#define FONT_WIDTH VIDEO_FONT_WIDTH + +DECLARE_GLOBAL_DATA_PTR; + +/* + * LCD information + */ +vidinfo_t panel_info = { + LCD_WIDTH, LCD_HEIGHT, LCD_BPP +}; + + +/* + * The device we use to communicate with PSoC + */ +int serial_inited = 0; + +/* + * Imported functions to support the PSoC protocol + */ +extern int serial_init_dev (unsigned long dev_base); +extern void serial_setrts_dev (unsigned long dev_base, int s); +extern int serial_getcts_dev (unsigned long dev_base); +extern void serial_putc_raw_dev(unsigned long dev_base, const char c); + +/* + * Just stubs for our driver, needed for compiling compabilty with + * the common LCD driver code. + */ +void lcd_initcolregs (void) +{ +} + +void lcd_ctrl_init (void *lcdbase) +{ +} + +/* + * Function sends the contents of the frame-buffer to the LCD + */ +void lcd_enable (void) +{ + int i, retries, fb_size; + + if (!serial_inited) { + unsigned long baud; + + baud = gd->baudrate; + gd->baudrate = PSOC_BAUD; + serial_init_dev(PSOC_PSC); + gd->baudrate = baud; + serial_setrts_dev (PSOC_PSC, RTS_ASSERT); + serial_inited = 1; + } + + /* + * Implement PSoC communication protocol: + * 1. Assert RTS, wait CTS assertion + * 2. Transmit data + * 3. Negate RTS, wait CTS negation + */ + + /* 1 */ + serial_setrts_dev (PSOC_PSC, RTS_ASSERT); + for (retries = PSOC_RETRIES; retries; retries--) { + if (serial_getcts_dev(PSOC_PSC) == CTS_ASSERT) + break; + udelay (PSOC_WAIT_TIME); + } + if (!retries) { + printf ("%s Error: PSoC doesn't respond on " + "RTS ASSERT\n", __FUNCTION__); + } + + /* 2 */ + fb_size = panel_info.vl_row * (panel_info.vl_col >> 3); + +#if !defined(SWAPPED_LCD) + for (i=0; i<fb_size; i++) { + serial_putc_raw_dev(PSOC_PSC, ((char *)gd->fb_base)[i]); + } +#else + { + int x, y, pwidth; + char *p = (char *)gd->fb_base; + + pwidth = ((panel_info.vl_col+7) >> 3); + for (y=0; y<panel_info.vl_row; y++) { + i = y * pwidth; + for (x=0; x<pwidth; x+=5) { + serial_putc_raw_dev (PSOC_PSC, (p[i+x+2]<<4 & 0xF0) | (p[i+x+3]>>4 & 0x0F)); + serial_putc_raw_dev (PSOC_PSC, (p[i+x+3]<<4 & 0xF0) | (p[i+x+4]>>4 & 0x0F)); + serial_putc_raw_dev (PSOC_PSC, (p[i+x+4]<<4 & 0xF0) | (p[i+x]>>4 & 0x0F)); + serial_putc_raw_dev (PSOC_PSC, (p[i+x]<<4 & 0xF0) | (p[i+x+1]>>4 & 0x0F)); + serial_putc_raw_dev (PSOC_PSC, (p[i+x+1]<<4 & 0xF0) | (p[i+x+2]>>4 & 0x0F)); + } + } + } +#endif + + /* 3 */ + serial_setrts_dev (PSOC_PSC, RTS_NEGATE); + for (retries = PSOC_RETRIES; retries; retries--) { + if (serial_getcts_dev(PSOC_PSC) == CTS_NEGATE) + break; + udelay (PSOC_WAIT_TIME); + } + + return; +} +#ifdef CONFIG_PROGRESSBAR + +void show_progress (int size, int tot) +{ + int cnt; + int i; + static int rc = 0; + + rc += size; + + cnt = ((LCD_WIDTH/FONT_WIDTH) * rc) / tot; + + rc -= (cnt * tot) / (LCD_WIDTH/FONT_WIDTH); + + for (i = 0; i < cnt; i++) { + lcd_putc(0xdc); + } + + if (cnt) { + lcd_enable(); /* MCC200-specific - send the framebuffer to PSoC */ + } +} + +#endif + +int bmp_display(ulong addr, int x, int y) +{ + int ret; + bmp_image_t *bmp = (bmp_image_t *)addr; + + if (!bmp) { + printf("There is no valid bmp file at the given address\n"); + return 1; + } + + ret = lcd_display_bitmap((ulong)bmp, x, y); + + if ((unsigned long)bmp != addr) + free(bmp); + + return ret; +} + +#endif /* CONFIG_LCD */ diff --git a/qemu/roms/u-boot/board/mcc200/mcc200.c b/qemu/roms/u-boot/board/mcc200/mcc200.c new file mode 100644 index 000000000..706886b84 --- /dev/null +++ b/qemu/roms/u-boot/board/mcc200/mcc200.c @@ -0,0 +1,314 @@ +/* + * (C) Copyright 2003-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mpc5xxx.h> +#include <pci.h> +#include <asm/processor.h> + +/* Two MT48LC8M32B2 for 32 MB */ +/* #include "mt48lc8m32b2-6-7.h" */ + +/* One MT48LC16M32S2 for 64 MB */ +/* #include "mt48lc16m32s2-75.h" */ +#if defined (CONFIG_MCC200_SDRAM) +#include "mt48lc16m16a2-75.h" +#else +#include "mt46v16m16-75.h" +#endif + +DECLARE_GLOBAL_DATA_PTR; + +extern flash_info_t flash_info[]; /* FLASH chips info */ + +extern int do_auto_update(void); +ulong flash_get_size (ulong base, int banknum); + +#ifndef CONFIG_SYS_RAMBOOT +static void sdram_start (int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set mode register: extended mode */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); +#endif + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); + + udelay(10); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE + * is something else than 0x00000000. + */ + +phys_size_t initdram (int board_type) +{ + ulong dramsize = 0; + ulong dramsize2 = 0; + uint svr, pvr; +#ifndef CONFIG_SYS_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set tap delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; + } else { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + } + + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ + + /* find RAM size using SDRAM CS1 only */ + if (!dramsize) + sdram_start(0); + test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); + if (!dramsize) { + sdram_start(1); + test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); + } + if (test1 > test2) { + sdram_start(0); + dramsize2 = test1; + } else { + dramsize2 = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize2 < (1 << 20)) { + dramsize2 = 0; + } + + /* set SDRAM CS1 size according to the amount of RAM found */ + if (dramsize2 > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); + } else { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + } + +#else /* CONFIG_SYS_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) { + dramsize = (1 << (dramsize - 0x13)) << 20; + } else { + dramsize = 0; + } + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) { + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + } else { + dramsize2 = 0; + } + +#endif /* CONFIG_SYS_RAMBOOT */ + + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + } + + return dramsize + dramsize2; +} + +int checkboard (void) +{ +#if defined(CONFIG_PRS200) + puts ("Board: PRS200\n"); +#else + puts ("Board: MCC200\n"); +#endif + return 0; +} + +int misc_init_r (void) +{ + ulong flash_sup_end, snum; + + /* + * Adjust flash start and offset to detected values + */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* + * Check if boot FLASH isn't max size + */ + if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH_BASE)) { + /* adjust mapping */ + *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = + START_REG(gd->bd->bi_flashstart); + *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = + STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize); + + /* + * Re-check to get correct base address + */ + flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1); + + /* + * Re-do flash protection upon new addresses + */ + flash_protect (FLAG_PROTECT_CLEAR, + gd->bd->bi_flashstart, 0xffffffff, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); + + /* Monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); + + /* Environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); + + /* Redundant environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); + } + + if (gd->bd->bi_flashsize > (32 << 20)) { + /* Unprotect the upper bank of the Flash */ + *(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6); + flash_protect (FLAG_PROTECT_CLEAR, + flash_info[0].start[0] + flash_info[0].size / 2, + (flash_info[0].start[0] - 1) + flash_info[0].size, + &flash_info[0]); + *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6); + printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n"); + flash_info[0].size = 32 << 20; + for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20); + flash_info[0].start[snum] < flash_sup_end; + snum++); + flash_info[0].sector_count = snum; + } + +#ifdef CONFIG_AUTO_UPDATE + do_auto_update(); +#endif + return (0); +} + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif + +#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) + +void init_ide_reset (void) +{ + debug ("init_ide_reset\n"); + +} + +void ide_set_reset (int idereset) +{ + debug ("ide_reset(%d)\n", idereset); + +} +#endif + +#if defined(CONFIG_CMD_DOC) +void doc_init (void) +{ + doc_probe (CONFIG_SYS_DOC_BASE); +} +#endif diff --git a/qemu/roms/u-boot/board/mcc200/mt46v16m16-75.h b/qemu/roms/u-boot/board/mcc200/mt46v16m16-75.h new file mode 100644 index 000000000..9068fbf36 --- /dev/null +++ b/qemu/roms/u-boot/board/mcc200/mt46v16m16-75.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define SDRAM_DDR 1 /* is DDR */ + +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 diff --git a/qemu/roms/u-boot/board/mcc200/mt48lc16m16a2-75.h b/qemu/roms/u-boot/board/mcc200/mt48lc16m16a2-75.h new file mode 100644 index 000000000..0133eaa2c --- /dev/null +++ b/qemu/roms/u-boot/board/mcc200/mt48lc16m16a2-75.h @@ -0,0 +1,14 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define SDRAM_DDR 0 /* is SDR */ + +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x00CD0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xD2322800 +#define SDRAM_CONFIG2 0x8AD70000 diff --git a/qemu/roms/u-boot/board/mcc200/mt48lc16m32s2-75.h b/qemu/roms/u-boot/board/mcc200/mt48lc16m32s2-75.h new file mode 100644 index 000000000..0133eaa2c --- /dev/null +++ b/qemu/roms/u-boot/board/mcc200/mt48lc16m32s2-75.h @@ -0,0 +1,14 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define SDRAM_DDR 0 /* is SDR */ + +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x00CD0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xD2322800 +#define SDRAM_CONFIG2 0x8AD70000 diff --git a/qemu/roms/u-boot/board/mcc200/mt48lc8m32b2-6-7.h b/qemu/roms/u-boot/board/mcc200/mt48lc8m32b2-6-7.h new file mode 100644 index 000000000..13aebbd8a --- /dev/null +++ b/qemu/roms/u-boot/board/mcc200/mt48lc8m32b2-6-7.h @@ -0,0 +1,12 @@ +/* + * Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform + */ + +#define SDRAM_DDR 0 /* is SDR */ + +/* Settings for XLB = 132 MHz */ + +#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */ +#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */ +#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */ +#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */ |