diff options
Diffstat (limited to 'qemu/roms/u-boot/board/keymile')
36 files changed, 0 insertions, 4586 deletions
diff --git a/qemu/roms/u-boot/board/keymile/common/common.c b/qemu/roms/u-boot/board/keymile/common/common.c deleted file mode 100644 index f941e44e8..000000000 --- a/qemu/roms/u-boot/board/keymile/common/common.c +++ /dev/null @@ -1,373 +0,0 @@ -/* - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * (C) Copyright 2011 - * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <command.h> -#include <malloc.h> -#include <hush.h> -#include <net.h> -#include <netdev.h> -#include <asm/io.h> -#include <linux/ctype.h> - -#if defined(CONFIG_POST) -#include "post.h" -#endif -#include "common.h" -#include <i2c.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Set Keymile specific environment variables - * Currently only some memory layout variables are calculated here - * ... ------------------------------------------------ - * ... |@rootfsaddr |@pnvramaddr |@varaddr |@reserved |@END_OF_RAM - * ... |<------------------- pram ------------------->| - * ... ------------------------------------------------ - * @END_OF_RAM: denotes the RAM size - * @pnvramaddr: Startadress of pseudo non volatile RAM in hex - * @pram : preserved ram size in k - * @varaddr : startadress for /var mounted into RAM - */ -int set_km_env(void) -{ - uchar buf[32]; - unsigned int pnvramaddr; - unsigned int pram; - unsigned int varaddr; - unsigned int kernelmem; - char *p; - unsigned long rootfssize = 0; - - pnvramaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - - CONFIG_KM_PNVRAM; - sprintf((char *)buf, "0x%x", pnvramaddr); - setenv("pnvramaddr", (char *)buf); - - /* try to read rootfssize (ram image) from envrionment */ - p = getenv("rootfssize"); - if (p != NULL) - strict_strtoul(p, 16, &rootfssize); - pram = (rootfssize + CONFIG_KM_RESERVED_PRAM + CONFIG_KM_PHRAM + - CONFIG_KM_PNVRAM) / 0x400; - sprintf((char *)buf, "0x%x", pram); - setenv("pram", (char *)buf); - - varaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM; - sprintf((char *)buf, "0x%x", varaddr); - setenv("varaddr", (char *)buf); - - kernelmem = gd->ram_size - 0x400 * pram; - sprintf((char *)buf, "0x%x", kernelmem); - setenv("kernelmem", (char *)buf); - - return 0; -} - -#if defined(CONFIG_SYS_I2C_INIT_BOARD) -static void i2c_write_start_seq(void) -{ - set_sda(1); - udelay(DELAY_HALF_PERIOD); - set_scl(1); - udelay(DELAY_HALF_PERIOD); - set_sda(0); - udelay(DELAY_HALF_PERIOD); - set_scl(0); - udelay(DELAY_HALF_PERIOD); -} - -/* - * I2C is a synchronous protocol and resets of the processor in the middle - * of an access can block the I2C Bus until a powerdown of the full unit is - * done. This function toggles the SCL until the SCL and SCA line are - * released, but max. 16 times, after this a I2C start-sequence is sent. - * This I2C Deblocking mechanism was developed by Keymile in association - * with Anatech and Atmel in 1998. - */ -int i2c_make_abort(void) -{ - int scl_state = 0; - int sda_state = 0; - int i = 0; - int ret = 0; - - if (!get_sda()) { - ret = -1; - while (i < 16) { - i++; - set_scl(0); - udelay(DELAY_ABORT_SEQ); - set_scl(1); - udelay(DELAY_ABORT_SEQ); - scl_state = get_scl(); - sda_state = get_sda(); - if (scl_state && sda_state) { - ret = 0; - break; - } - } - } - if (ret == 0) - for (i = 0; i < 5; i++) - i2c_write_start_seq(); - - /* respect stop setup time */ - udelay(DELAY_ABORT_SEQ); - set_scl(1); - udelay(DELAY_ABORT_SEQ); - set_sda(1); - get_sda(); - - return ret; -} - -/** - * i2c_init_board - reset i2c bus. When the board is powercycled during a - * bus transfer it might hang; for details see doc/I2C_Edge_Conditions. - */ -void i2c_init_board(void) -{ - /* Now run the AbortSequence() */ - i2c_make_abort(); -} -#endif - -#if defined(CONFIG_KM_COMMON_ETH_INIT) -int board_eth_init(bd_t *bis) -{ - if (ethernet_present()) - return cpu_eth_init(bis); - - return -1; -} -#endif - -/* - * do_setboardid command - * read out the board id and the hw key from the intventory EEPROM and set - * this values as environment variables. - */ -static int do_setboardid(cmd_tbl_t *cmdtp, int flag, int argc, - char *const argv[]) -{ - unsigned char buf[32]; - char *p; - - p = get_local_var("IVM_BoardId"); - if (p == NULL) { - printf("can't get the IVM_Boardid\n"); - return 1; - } - sprintf((char *)buf, "%s", p); - setenv("boardid", (char *)buf); - printf("set boardid=%s\n", buf); - - p = get_local_var("IVM_HWKey"); - if (p == NULL) { - printf("can't get the IVM_HWKey\n"); - return 1; - } - sprintf((char *)buf, "%s", p); - setenv("hwkey", (char *)buf); - printf("set hwkey=%s\n", buf); - printf("Execute manually saveenv for persistent storage.\n"); - - return 0; -} - -U_BOOT_CMD(km_setboardid, 1, 0, do_setboardid, "setboardid", "read out bid and " - "hwkey from IVM and set in environment"); - -/* - * command km_checkbidhwk - * if "boardid" and "hwkey" are not already set in the environment, do: - * if a "boardIdListHex" exists in the environment: - * - read ivm data for boardid and hwkey - * - compare each entry of the boardIdListHex with the - * IVM data: - * if match: - * set environment variables boardid, boardId, - * hwkey, hwKey to the found values - * both (boardid and boardId) are set because - * they might be used differently in the - * application and in the init scripts (?) - * return 0 in case of match, 1 if not match or error - */ -static int do_checkboardidhwk(cmd_tbl_t *cmdtp, int flag, int argc, - char *const argv[]) -{ - unsigned long ivmbid = 0, ivmhwkey = 0; - unsigned long envbid = 0, envhwkey = 0; - char *p; - int verbose = argc > 1 && *argv[1] == 'v'; - int rc = 0; - - /* - * first read out the real inventory values, these values are - * already stored in the local hush variables - */ - p = get_local_var("IVM_BoardId"); - if (p == NULL) { - printf("can't get the IVM_Boardid\n"); - return 1; - } - rc = strict_strtoul(p, 16, &ivmbid); - - p = get_local_var("IVM_HWKey"); - if (p == NULL) { - printf("can't get the IVM_HWKey\n"); - return 1; - } - rc = strict_strtoul(p, 16, &ivmhwkey); - - if (!ivmbid || !ivmhwkey) { - printf("Error: IVM_BoardId and/or IVM_HWKey not set!\n"); - return rc; - } - - /* now try to read values from environment if available */ - p = getenv("boardid"); - if (p != NULL) - rc = strict_strtoul(p, 16, &envbid); - p = getenv("hwkey"); - if (p != NULL) - rc = strict_strtoul(p, 16, &envhwkey); - - if (rc != 0) { - printf("strict_strtoul returns error: %d", rc); - return rc; - } - - if (!envbid || !envhwkey) { - /* - * BoardId/HWkey not available in the environment, so try the - * environment variable for BoardId/HWkey list - */ - char *bidhwklist = getenv("boardIdListHex"); - - if (bidhwklist) { - int found = 0; - char *rest = bidhwklist; - char *endp; - - if (verbose) { - printf("IVM_BoardId: %ld, IVM_HWKey=%ld\n", - ivmbid, ivmhwkey); - printf("boardIdHwKeyList: %s\n", - bidhwklist); - } - while (!found) { - /* loop over each bid/hwkey pair in the list */ - unsigned long bid = 0; - unsigned long hwkey = 0; - - while (*rest && !isxdigit(*rest)) - rest++; - /* - * use simple_strtoul because we need &end and - * we know we got non numeric char at the end - */ - bid = simple_strtoul(rest, &endp, 16); - /* BoardId and HWkey are separated with a "_" */ - if (*endp == '_') { - rest = endp + 1; - /* - * use simple_strtoul because we need - * &end - */ - hwkey = simple_strtoul(rest, &endp, 16); - rest = endp; - while (*rest && !isxdigit(*rest)) - rest++; - } - if ((!bid) || (!hwkey)) { - /* end of list */ - break; - } - if (verbose) { - printf("trying bid=0x%lX, hwkey=%ld\n", - bid, hwkey); - } - /* - * Compare the values of the found entry in the - * list with the valid values which are stored - * in the inventory eeprom. If they are equal - * set the values in environment variables. - */ - if ((bid == ivmbid) && (hwkey == ivmhwkey)) { - char buf[10]; - - found = 1; - envbid = bid; - envhwkey = hwkey; - sprintf(buf, "%lx", bid); - setenv("boardid", buf); - sprintf(buf, "%lx", hwkey); - setenv("hwkey", buf); - } - } /* end while( ! found ) */ - } - } - - /* compare now the values */ - if ((ivmbid == envbid) && (ivmhwkey == envhwkey)) { - printf("boardid=0x%3lX, hwkey=%ld\n", envbid, envhwkey); - rc = 0; /* match */ - } else { - printf("Error: env boardid=0x%3lX, hwkey=%ld\n", envbid, - envhwkey); - printf(" IVM bId=0x%3lX, hwKey=%ld\n", ivmbid, ivmhwkey); - rc = 1; /* don't match */ - } - return rc; -} - -U_BOOT_CMD(km_checkbidhwk, 2, 0, do_checkboardidhwk, - "check boardid and hwkey", - "[v]\n - check environment parameter "\ - "\"boardIdListHex\" against stored boardid and hwkey "\ - "from the IVM\n v: verbose output" -); - -/* - * command km_checktestboot - * if the testpin of the board is asserted, return 1 - * * else return 0 - */ -static int do_checktestboot(cmd_tbl_t *cmdtp, int flag, int argc, - char *const argv[]) -{ - int testpin = 0; - char *s = NULL; - int testboot = 0; - int verbose = argc > 1 && *argv[1] == 'v'; - -#if defined(CONFIG_POST) - testpin = post_hotkeys_pressed(); - s = getenv("test_bank"); -#endif - /* when test_bank is not set, act as if testpin is not asserted */ - testboot = (testpin != 0) && (s); - if (verbose) { - printf("testpin = %d\n", testpin); - printf("test_bank = %s\n", s ? s : "not set"); - printf("boot test app : %s\n", (testboot) ? "yes" : "no"); - } - /* return 0 means: testboot, therefore we need the inversion */ - return !testboot; -} - -U_BOOT_CMD(km_checktestboot, 2, 0, do_checktestboot, - "check if testpin is asserted", - "[v]\n v - verbose output" -); diff --git a/qemu/roms/u-boot/board/keymile/common/common.h b/qemu/roms/u-boot/board/keymile/common/common.h deleted file mode 100644 index e075f4687..000000000 --- a/qemu/roms/u-boot/board/keymile/common/common.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __KEYMILE_COMMON_H -#define __KEYMILE_COMMON_H - -#define WRG_RESET 0x80 -#define H_OPORTS_14 0x40 -#define WRG_LED 0x02 -#define WRL_BOOT 0x01 - -#define OPRTL_XBUFENA 0x20 - -#define H_OPORTS_SCC4_ENA 0x10 -#define H_OPORTS_SCC4_FD_ENA 0x04 -#define H_OPORTS_FCC1_PW_DWN 0x01 - -#define PIGGY_PRESENT 0x80 - -struct km_bec_fpga { - unsigned char id; - unsigned char rev; - unsigned char oprth; - unsigned char oprtl; - unsigned char res1[3]; - unsigned char bprth; - unsigned char bprtl; - unsigned char gprt3; - unsigned char gprt2; - unsigned char gprt1; - unsigned char gprt0; - unsigned char res2[2]; - unsigned char prst; - unsigned char res3[0xfff0]; - unsigned char pgy_id; - unsigned char pgy_rev; - unsigned char pgy_outputs; - unsigned char pgy_eth; -}; - -#define BFTICU_DIPSWITCH_MASK 0x0f - -/* - * BFTICU FPGA iomap - * BFTICU is used on mgcoge and mgocge3ne - */ -struct bfticu_iomap { - u8 xi_ena; /* General defect enable */ - u8 pack1[3]; - u8 en_csn; - u8 pack2; - u8 safe_mem; - u8 pack3; - u8 id; - u8 pack4; - u8 rev; - u8 build; - u8 p_frc; - u8 p_msk; - u8 pack5[2]; - u8 xg_int; - u8 pack6[15]; - u8 s_conf; - u8 pack7; - u8 dmx_conf12; - u8 pack8; - u8 s_clkslv; - u8 pack9[11]; - u8 d_conf; - u8 d_mask_ca; - u8 d_pll_del; - u8 pack10[16]; - u8 t_conf_ca; - u8 t_mask_ca; - u8 pack11[13]; - u8 m_def0; - u8 m_def1; - u8 m_def2; - u8 m_def3; - u8 m_def4; - u8 m_def5; - u8 m_def_trap0; - u8 m_def_trap1; - u8 m_def_trap2; - u8 m_def_trap3; - u8 m_def_trap4; - u8 m_def_trap5; - u8 m_mask_def0; - u8 m_mask_def1; - u8 m_mask_def2; - u8 m_mask_def3; - u8 m_mask_def4; - u8 m_mask_def5; - u8 m_def_mask0; - u8 m_def_mask1; - u8 m_def_mask2; - u8 m_def_mask3; - u8 m_def_mask4; - u8 m_def_mask5; - u8 m_def_pri; - u8 pack12[11]; - u8 hw_status; - u8 pack13; - u8 hw_control1; - u8 hw_control2; - u8 hw_control3; - u8 pack14[7]; - u8 led_on; /* Leds */ - u8 pack15; - u8 sfp_control; /* SFP modules */ - u8 pack16; - u8 alarm_control; /* Alarm output */ - u8 pack17; - u8 icps; /* ICN clock pulse shaping */ - u8 mswitch; /* Read mode switch */ - u8 pack18[6]; - u8 pb_dbug; -}; - -#if !defined(CONFIG_PIGGY_MAC_ADRESS_OFFSET) -#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 0 -#endif - -int ethernet_present(void); -int ivm_read_eeprom(void); - -int trigger_fpga_config(void); -int wait_for_fpga_config(void); -int fpga_reset(void); -int toggle_eeprom_spi_bus(void); - -int set_km_env(void); -int fdt_set_node_and_value(void *blob, - char *nodename, - char *regname, - void *var, - int size); -int fdt_get_node_and_value(void *blob, - char *nodename, - char *propname, - void **var); - -#define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */ -#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000)) - -int i2c_soft_read_pin(void); -int i2c_make_abort(void); -#endif /* __KEYMILE_COMMON_H */ diff --git a/qemu/roms/u-boot/board/keymile/common/ivm.c b/qemu/roms/u-boot/board/keymile/common/ivm.c deleted file mode 100644 index f0e91bbdf..000000000 --- a/qemu/roms/u-boot/board/keymile/common/ivm.c +++ /dev/null @@ -1,316 +0,0 @@ -/* - * (C) Copyright 2011 - * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <hush.h> -#include <i2c.h> -#include "common.h" - -static int ivm_calc_crc(unsigned char *buf, int len) -{ - const unsigned short crc_tab[16] = { - 0x0000, 0xCC01, 0xD801, 0x1400, - 0xF001, 0x3C00, 0x2800, 0xE401, - 0xA001, 0x6C00, 0x7800, 0xB401, - 0x5000, 0x9C01, 0x8801, 0x4400}; - - unsigned short crc = 0; /* final result */ - unsigned short r1 = 0; /* temp */ - unsigned char byte = 0; /* input buffer */ - int i; - - /* calculate CRC from array data */ - for (i = 0; i < len; i++) { - byte = buf[i]; - - /* lower 4 bits */ - r1 = crc_tab[crc & 0xF]; - crc = ((crc) >> 4) & 0x0FFF; - crc = crc ^ r1 ^ crc_tab[byte & 0xF]; - - /* upper 4 bits */ - r1 = crc_tab[crc & 0xF]; - crc = (crc >> 4) & 0x0FFF; - crc = crc ^ r1 ^ crc_tab[(byte >> 4) & 0xF]; - } - return crc; -} - -static int ivm_set_value(char *name, char *value) -{ - char tempbuf[256]; - - if (value != NULL) { - sprintf(tempbuf, "%s=%s", name, value); - return set_local_var(tempbuf, 0); - } else { - unset_local_var(name); - } - return 0; -} - -static int ivm_get_value(unsigned char *buf, int len, char *name, int off, - int check) -{ - unsigned short val; - unsigned char valbuf[30]; - - if ((buf[off + 0] != buf[off + 2]) && - (buf[off + 2] != buf[off + 4])) { - printf("%s Error corrupted %s\n", __func__, name); - val = -1; - } else { - val = buf[off + 0] + (buf[off + 1] << 8); - if ((val == 0) && (check == 1)) - val = -1; - } - sprintf((char *)valbuf, "%x", val); - ivm_set_value(name, (char *)valbuf); - return val; -} - -#define INV_BLOCKSIZE 0x100 -#define INV_DATAADDRESS 0x21 -#define INVENTORYDATASIZE (INV_BLOCKSIZE - INV_DATAADDRESS - 3) - -#define IVM_POS_SHORT_TEXT 0 -#define IVM_POS_MANU_ID 1 -#define IVM_POS_MANU_SERIAL 2 -#define IVM_POS_PART_NUMBER 3 -#define IVM_POS_BUILD_STATE 4 -#define IVM_POS_SUPPLIER_PART_NUMBER 5 -#define IVM_POS_DELIVERY_DATE 6 -#define IVM_POS_SUPPLIER_BUILD_STATE 7 -#define IVM_POS_CUSTOMER_ID 8 -#define IVM_POS_CUSTOMER_PROD_ID 9 -#define IVM_POS_HISTORY 10 -#define IVM_POS_SYMBOL_ONLY 11 - -static char convert_char(char c) -{ - return (c < ' ' || c > '~') ? '.' : c; -} - -static int ivm_findinventorystring(int type, - unsigned char *const string, - unsigned long maxlen, - unsigned char *buf) -{ - int xcode = 0; - unsigned long cr = 0; - unsigned long addr = INV_DATAADDRESS; - unsigned long size = 0; - unsigned long nr = type; - int stop = 0; /* stop on semicolon */ - - memset(string, '\0', maxlen); - switch (type) { - case IVM_POS_SYMBOL_ONLY: - nr = 0; - stop = 1; - break; - default: - nr = type; - stop = 0; - } - - /* Look for the requested number of CR. */ - while ((cr != nr) && (addr < INVENTORYDATASIZE)) { - if ((buf[addr] == '\r')) - cr++; - addr++; - } - - /* - * the expected number of CR was found until the end of the IVM - * content --> fill string - */ - if (addr < INVENTORYDATASIZE) { - /* Copy the IVM string in the corresponding string */ - for (; (buf[addr] != '\r') && - ((buf[addr] != ';') || (!stop)) && - (size < (maxlen - 1) && - (addr < INVENTORYDATASIZE)); addr++) { - size += sprintf((char *)string + size, "%c", - convert_char (buf[addr])); - } - - /* - * copy phase is done: check if everything is ok. If not, - * the inventory data is most probably corrupted: tell - * the world there is a problem! - */ - if (addr == INVENTORYDATASIZE) { - xcode = -1; - printf("Error end of string not found\n"); - } else if ((size > (maxlen - 1)) && - (buf[addr] != '\r')) { - xcode = -1; - printf("string too long till next CR\n"); - } - } else { - /* - * some CR are missing... - * the inventory data is most probably corrupted - */ - xcode = -1; - printf("not enough cr found\n"); - } - return xcode; -} - -#define GET_STRING(name, which, len) \ - if (ivm_findinventorystring(which, valbuf, len, buf) == 0) { \ - ivm_set_value(name, (char *)valbuf); \ - } - -static int ivm_check_crc(unsigned char *buf, int block) -{ - unsigned long crc; - unsigned long crceeprom; - - crc = ivm_calc_crc(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2); - crceeprom = (buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 1] + \ - buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2] * 256); - if (crc != crceeprom) { - if (block == 0) - printf("Error CRC Block: %d EEprom: calculated: \ - %lx EEprom: %lx\n", block, crc, crceeprom); - return -1; - } - return 0; -} - -static int calculate_mac_offset(unsigned char *valbuf, unsigned char *buf, - int offset) -{ - unsigned long val = (buf[4] << 16) + (buf[5] << 8) + buf[6]; - - if (offset == 0) - return 0; - - val += offset; - buf[4] = (val >> 16) & 0xff; - buf[5] = (val >> 8) & 0xff; - buf[6] = val & 0xff; - sprintf((char *)valbuf, "%pM", buf + 1); - return 0; -} - -static int ivm_analyze_block2(unsigned char *buf, int len) -{ - unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN]; - unsigned long count; - - /* IVM_MAC Adress begins at offset 1 */ - sprintf((char *)valbuf, "%pM", buf + 1); - ivm_set_value("IVM_MacAddress", (char *)valbuf); - /* if an offset is defined, add it */ - calculate_mac_offset(buf, valbuf, CONFIG_PIGGY_MAC_ADRESS_OFFSET); -#ifdef MACH_TYPE_KM_KIRKWOOD - setenv((char *)"ethaddr", (char *)valbuf); -#else - if (getenv("ethaddr") == NULL) - setenv((char *)"ethaddr", (char *)valbuf); -#endif -#ifdef CONFIG_KMVECT1 -/* KMVECT1 has two ethernet interfaces */ - if (getenv("eth1addr") == NULL) { - calculate_mac_offset(buf, valbuf, 1); - setenv((char *)"eth1addr", (char *)valbuf); - } -#endif - /* IVM_MacCount */ - count = (buf[10] << 24) + - (buf[11] << 16) + - (buf[12] << 8) + - buf[13]; - if (count == 0xffffffff) - count = 1; - sprintf((char *)valbuf, "%lx", count); - ivm_set_value("IVM_MacCount", (char *)valbuf); - return 0; -} - -static int ivm_analyze_eeprom(unsigned char *buf, int len) -{ - unsigned short val; - unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN]; - unsigned char *tmp; - - if (ivm_check_crc(buf, 0) != 0) - return -1; - - ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, - "IVM_BoardId", 0, 1); - val = ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, - "IVM_HWKey", 6, 1); - if (val != 0xffff) { - sprintf((char *)valbuf, "%x", ((val / 100) % 10)); - ivm_set_value("IVM_HWVariant", (char *)valbuf); - sprintf((char *)valbuf, "%x", (val % 100)); - ivm_set_value("IVM_HWVersion", (char *)valbuf); - } - ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, - "IVM_Functions", 12, 0); - - GET_STRING("IVM_Symbol", IVM_POS_SYMBOL_ONLY, 8) - GET_STRING("IVM_DeviceName", IVM_POS_SHORT_TEXT, 64) - tmp = (unsigned char *) getenv("IVM_DeviceName"); - if (tmp) { - int len = strlen((char *)tmp); - int i = 0; - - while (i < len) { - if (tmp[i] == ';') { - ivm_set_value("IVM_ShortText", - (char *)&tmp[i + 1]); - break; - } - i++; - } - if (i >= len) - ivm_set_value("IVM_ShortText", NULL); - } else { - ivm_set_value("IVM_ShortText", NULL); - } - GET_STRING("IVM_ManufacturerID", IVM_POS_MANU_ID, 32) - GET_STRING("IVM_ManufacturerSerialNumber", IVM_POS_MANU_SERIAL, 20) - GET_STRING("IVM_ManufacturerPartNumber", IVM_POS_PART_NUMBER, 32) - GET_STRING("IVM_ManufacturerBuildState", IVM_POS_BUILD_STATE, 32) - GET_STRING("IVM_SupplierPartNumber", IVM_POS_SUPPLIER_PART_NUMBER, 32) - GET_STRING("IVM_DelieveryDate", IVM_POS_DELIVERY_DATE, 32) - GET_STRING("IVM_SupplierBuildState", IVM_POS_SUPPLIER_BUILD_STATE, 32) - GET_STRING("IVM_CustomerID", IVM_POS_CUSTOMER_ID, 32) - GET_STRING("IVM_CustomerProductID", IVM_POS_CUSTOMER_PROD_ID, 32) - - if (ivm_check_crc(&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], 2) != 0) - return 0; - ivm_analyze_block2(&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], - CONFIG_SYS_IVM_EEPROM_PAGE_LEN); - - return 0; -} - -int ivm_read_eeprom(void) -{ - uchar i2c_buffer[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; - int ret; - - i2c_set_bus_num(CONFIG_KM_IVM_BUS); - /* add deblocking here */ - i2c_make_abort(); - - ret = i2c_read(CONFIG_SYS_IVM_EEPROM_ADR, 0, 1, i2c_buffer, - CONFIG_SYS_IVM_EEPROM_MAX_LEN); - if (ret != 0) { - printf("Error reading EEprom\n"); - return -2; - } - - return ivm_analyze_eeprom(i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN); -} diff --git a/qemu/roms/u-boot/board/keymile/km82xx/Makefile b/qemu/roms/u-boot/board/keymile/km82xx/Makefile deleted file mode 100644 index 20f193ab1..000000000 --- a/qemu/roms/u-boot/board/keymile/km82xx/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := km82xx.o ../common/common.o ../common/ivm.o diff --git a/qemu/roms/u-boot/board/keymile/km82xx/km82xx.c b/qemu/roms/u-boot/board/keymile/km82xx/km82xx.c deleted file mode 100644 index dfbfab813..000000000 --- a/qemu/roms/u-boot/board/keymile/km82xx/km82xx.c +++ /dev/null @@ -1,467 +0,0 @@ -/* - * (C) Copyright 2007 - 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8260.h> -#include <ioports.h> -#include <malloc.h> -#include <asm/io.h> - -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#endif - -#include <i2c.h> -#include "../common/common.h" - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A */ - { /* conf ppar psor pdir podr pdat */ - { 0, 0, 0, 0, 0, 0 }, /* PA31 */ - { 0, 0, 0, 0, 0, 0 }, /* PA30 */ - { 0, 0, 0, 0, 0, 0 }, /* PA29 */ - { 0, 0, 0, 0, 0, 0 }, /* PA28 */ - { 0, 0, 0, 0, 0, 0 }, /* PA27 */ - { 0, 0, 0, 0, 0, 0 }, /* PA26 */ - { 0, 0, 0, 0, 0, 0 }, /* PA25 */ - { 0, 0, 0, 0, 0, 0 }, /* PA24 */ - { 0, 0, 0, 0, 0, 0 }, /* PA23 */ - { 0, 0, 0, 0, 0, 0 }, /* PA22 */ - { 0, 0, 0, 0, 0, 0 }, /* PA21 */ - { 0, 0, 0, 0, 0, 0 }, /* PA20 */ - { 0, 0, 0, 0, 0, 0 }, /* PA19 */ - { 0, 0, 0, 0, 0, 0 }, /* PA18 */ - { 0, 0, 0, 0, 0, 0 }, /* PA17 */ - { 0, 0, 0, 0, 0, 0 }, /* PA16 */ - { 0, 0, 0, 0, 0, 0 }, /* PA15 */ - { 0, 0, 0, 0, 0, 0 }, /* PA14 */ - { 0, 0, 0, 0, 0, 0 }, /* PA13 */ - { 0, 0, 0, 0, 0, 0 }, /* PA12 */ - { 0, 0, 0, 0, 0, 0 }, /* PA11 */ - { 0, 0, 0, 0, 0, 0 }, /* PA10 */ - { 1, 1, 0, 1, 0, 0 }, /* PA9 SMC2 TxD */ - { 1, 1, 0, 0, 0, 0 }, /* PA8 SMC2 RxD */ - { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - { 0, 0, 0, 0, 0, 0 }, /* PA6 */ - { 0, 0, 0, 0, 0, 0 }, /* PA5 */ - { 0, 0, 0, 0, 0, 0 }, /* PA4 */ - { 0, 0, 0, 0, 0, 0 }, /* PA3 */ - { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - { 0, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B */ - { /* conf ppar psor pdir podr pdat */ - { 0, 0, 0, 0, 0, 0 }, /* PB31 */ - { 0, 0, 0, 0, 0, 0 }, /* PB30 */ - { 0, 0, 0, 0, 0, 0 }, /* PB29 */ - { 0, 0, 0, 0, 0, 0 }, /* PB28 */ - { 0, 0, 0, 0, 0, 0 }, /* PB27 */ - { 0, 0, 0, 0, 0, 0 }, /* PB26 */ - { 0, 0, 0, 0, 0, 0 }, /* PB25 */ - { 0, 0, 0, 0, 0, 0 }, /* PB24 */ - { 0, 0, 0, 0, 0, 0 }, /* PB23 */ - { 0, 0, 0, 0, 0, 0 }, /* PB22 */ - { 0, 0, 0, 0, 0, 0 }, /* PB21 */ - { 0, 0, 0, 0, 0, 0 }, /* PB20 */ - { 0, 0, 0, 0, 0, 0 }, /* PB19 */ - { 0, 0, 0, 0, 0, 0 }, /* PB18 */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 } /* non-existent */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - { 0, 0, 0, 0, 0, 0 }, /* PC29 */ - { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - { 1, 1, 0, 0, 0, 0 }, /* PC25 RxClk */ - { 1, 1, 0, 0, 0, 0 }, /* PC24 TxClk */ - { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - { 0, 0, 0, 0, 0, 0 }, /* PC22 */ - { 0, 0, 0, 0, 0, 0 }, /* PC21 */ - { 0, 0, 0, 0, 0, 0 }, /* PC20 */ - { 0, 0, 0, 0, 0, 0 }, /* PC19 */ - { 0, 0, 0, 0, 0, 0 }, /* PC18 */ - { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - { 1, 1, 0, 0, 0, 0 }, /* PC9 SCC4: CTS */ - { 1, 1, 0, 0, 0, 0 }, /* PC8 SCC4: CD */ - { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - { 0, 0, 0, 0, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - { 0, 0, 0, 0, 0, 0 }, /* PD31 */ - { 0, 0, 0, 0, 0, 0 }, /* PD30 */ - { 0, 0, 0, 0, 0, 0 }, /* PD29 */ - { 0, 0, 0, 0, 0, 0 }, /* PD28 */ - { 0, 0, 0, 0, 0, 0 }, /* PD27 */ - { 0, 0, 0, 0, 0, 0 }, /* PD26 */ - { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - { 1, 1, 0, 0, 0, 0 }, /* PD22 SCC4: RXD */ - { 1, 1, 0, 1, 0, 0 }, /* PD21 SCC4: TXD */ - { 1, 1, 0, 1, 0, 0 }, /* PD20 SCC4: RTS */ - { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - { 0, 0, 0, 0, 0, 0 }, /* PD17 */ - { 0, 0, 0, 0, 0, 0 }, /* PD16 */ -#if defined(CONFIG_HARD_I2C) - { 1, 1, 1, 0, 1, 0 }, /* PD15 I2C SDA */ - { 1, 1, 1, 0, 1, 0 }, /* PD14 I2C SCL */ -#else - { 1, 0, 0, 0, 1, 1 }, /* PD15 */ - { 1, 0, 0, 1, 1, 1 }, /* PD14 */ -#endif - { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - { 0, 0, 0, 0, 0, 0 }, /* PD9 */ - { 0, 0, 0, 0, 0, 0 }, /* PD8 */ - { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - { 0, 0, 0, 0, 0, 0 }, /* PD6 */ - { 0, 0, 0, 0, 0, 0 }, /* PD5 */ - { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 } /* non-existent */ - } -}; - -/* - * Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init(memctl8260_t *memctl, ulong sdmr, - ulong orx, uchar *base) -{ - uchar c = 0xff; - ulong maxsize, size; - int i; - - /* - * We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff))/* / 2*/; - - out_be32(&memctl->memc_or1, orx); - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address - * CONFIG_SYS_SDRAM_BASE. - */ - - out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_PREA); - out_8(base, c); - - out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_CBRR); - for (i = 0; i < 8; i++) - out_8(base, c); - - out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_MRW); - /* setting MR on address lines */ - out_8((uchar *)(base + CONFIG_SYS_MRS_OFFS), c); - - out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_NORM | PSDMR_RFEN); - out_8(base, c); - - size = get_ram_size((long *)base, maxsize); - out_be32(&memctl->memc_or1, orx | ~(size - 1)); - - return size; -} - -#ifdef CONFIG_SYS_SDRAM_LIST - -/* - * If CONFIG_SYS_SDRAM_LIST is defined, we cycle through all SDRAM - * configurations therein (should be from high to lower) to find the - * one actually matching the current configuration. - * CONFIG_SYS_PSDMR and CONFIG_SYS_OR1 will contain the base values which are - * common among all possible configurations; values in CONFIG_SYS_SDRAM_LIST - * (defined as the initialization value for the array of struct sdram_conf_s) - * will then be ORed with such base values. - */ - -struct sdram_conf_s { - ulong size; - int or1; - int psdmr; -}; - -static struct sdram_conf_s sdram_conf[] = CONFIG_SYS_SDRAM_LIST; - -static long probe_sdram(memctl8260_t *memctl) -{ - int n = 0; - long psize = 0; - - for (n = 0; n < ARRAY_SIZE(sdram_conf); psize = 0, n++) { - psize = try_init(memctl, - CONFIG_SYS_PSDMR | sdram_conf[n].psdmr, - CONFIG_SYS_OR1 | sdram_conf[n].or1, - (uchar *) CONFIG_SYS_SDRAM_BASE); - debug("Probing %ld bytes returned %ld\n", - sdram_conf[n].size, psize); - if (psize == sdram_conf[n].size) - break; - } - return psize; -} - -#else /* CONFIG_SYS_SDRAM_LIST */ - -static long probe_sdram(memctl8260_t *memctl) -{ - return try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1, - (uchar *) CONFIG_SYS_SDRAM_BASE); -} -#endif /* CONFIG_SYS_SDRAM_LIST */ - - -phys_size_t initdram(int board_type) -{ - immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - memctl8260_t *memctl = &immap->im_memctl; - - long psize; - - out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT); - out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); - -#ifndef CONFIG_SYS_RAMBOOT - /* 60x SDRAM setup: - */ - psize = probe_sdram(memctl); -#endif /* CONFIG_SYS_RAMBOOT */ - - icache_enable(); - - return psize; -} - -int checkboard(void) -{ -#if defined(CONFIG_MGCOGE) - puts("Board: Keymile mgcoge"); -#else - puts("Board: Keymile mgcoge3ne"); -#endif - if (ethernet_present()) - puts(" with PIGGY."); - puts("\n"); - return 0; -} - -int last_stage_init(void) -{ - struct bfticu_iomap *base = - (struct bfticu_iomap *)CONFIG_SYS_FPGA_BASE; - u8 dip_switch; - - dip_switch = in_8(&base->mswitch); - dip_switch &= BFTICU_DIPSWITCH_MASK; - /* dip switch 'full reset' or 'db erase' */ - if (dip_switch & 0x1 || dip_switch & 0x2) { - /* start bootloader */ - puts("DIP: Enabled\n"); - setenv("actual_bank", "0"); - } - set_km_env(); - return 0; -} - -#ifdef CONFIG_MGCOGE3NE -static void set_pin(int state, unsigned long mask); - -/* - * For mgcoge3ne boards, the mgcoge3un control is controlled from - * a GPIO line on the PPC CPU. If bobcatreset is set the line - * will toggle once what forces the mgocge3un part to restart - * immediately. - */ -static void handle_mgcoge3un_reset(void) -{ - char *bobcatreset = getenv("bobcatreset"); - if (bobcatreset) { - if (strcmp(bobcatreset, "true") == 0) { - puts("Forcing bobcat reset\n"); - set_pin(0, 0x00000004); /* clear PD29 to reset arm */ - udelay(1000); - set_pin(1, 0x00000004); - } else - set_pin(1, 0x00000004); /* set PD29 to not reset arm */ - } -} -#endif - -int ethernet_present(void) -{ - struct km_bec_fpga *base = - (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; - - return in_8(&base->bprth) & PIGGY_PRESENT; -} - -/* - * Early board initalization. - */ -int board_early_init_r(void) -{ - struct km_bec_fpga *base = - (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; - - /* setup the UPIOx */ - /* General Unit Reset disabled, Flash Bank enabled, UnitLed on */ - out_8(&base->oprth, (WRG_RESET | H_OPORTS_14 | WRG_LED)); - /* SCC4 enable, halfduplex, FCC1 powerdown */ - out_8(&base->oprtl, (H_OPORTS_SCC4_ENA | H_OPORTS_SCC4_FD_ENA | - H_OPORTS_FCC1_PW_DWN)); - -#ifdef CONFIG_MGCOGE3NE - handle_mgcoge3un_reset(); -#endif - return 0; -} - -int hush_init_var(void) -{ - ivm_read_eeprom(); - return 0; -} - -#define SDA_MASK 0x00010000 -#define SCL_MASK 0x00020000 - -static void set_pin(int state, unsigned long mask) -{ - ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3); - - if (state) - setbits_be32(&iop->pdat, mask); - else - clrbits_be32(&iop->pdat, mask); - - setbits_be32(&iop->pdir, mask); -} - -static int get_pin(unsigned long mask) -{ - ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3); - - clrbits_be32(&iop->pdir, mask); - return 0 != (in_be32(&iop->pdat) & mask); -} - -void set_sda(int state) -{ - set_pin(state, SDA_MASK); -} - -void set_scl(int state) -{ - set_pin(state, SCL_MASK); -} - -int get_sda(void) -{ - return get_pin(SDA_MASK); -} - -int get_scl(void) -{ - return get_pin(SCL_MASK); -} - -#if defined(CONFIG_HARD_I2C) -static void setports(int gpio) -{ - ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3); - - if (gpio) { - clrbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK)); - clrbits_be32(&iop->podr, (SDA_MASK | SCL_MASK)); - } else { - setbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK)); - clrbits_be32(&iop->pdir, (SDA_MASK | SCL_MASK)); - setbits_be32(&iop->podr, (SDA_MASK | SCL_MASK)); - } -} -#endif -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -} -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/qemu/roms/u-boot/board/keymile/km83xx/Makefile b/qemu/roms/u-boot/board/keymile/km83xx/Makefile deleted file mode 100644 index 6c3268853..000000000 --- a/qemu/roms/u-boot/board/keymile/km83xx/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += km83xx.o ../common/common.o ../common/ivm.o km83xx_i2c.o diff --git a/qemu/roms/u-boot/board/keymile/km83xx/README.kmeter1 b/qemu/roms/u-boot/board/keymile/km83xx/README.kmeter1 deleted file mode 100644 index 7f4fc999f..000000000 --- a/qemu/roms/u-boot/board/keymile/km83xx/README.kmeter1 +++ /dev/null @@ -1,91 +0,0 @@ -Keymile kmeter1 Board ------------------------------------------ -1. Alternative Boot EEPROM - - Upon the kmeter1 startup the I2C_1 controller is used to fetch the boot - configuration from a serial EEPROM. During the development and debugging - phase it might be helpful to apply an alternative boot configuration in - a simple way. Therefore it is an alternative boot eeprom on the PIGGY, - which can be activated by setting the "ST" jumper on the PIGGY board. - -2. Memory Map - - BaseAddr PortSz Size Device - ----------- ------ ----- ------ - 0x0000_0000 64 bit 256MB DDR - 0x8000_0000 8 bit 256KB GPIO/PIGGY on CS1 - 0xa000_0000 8 bit 256MB PAXE on CS3 - 0xe000_0000 2MB Int Mem Reg Space - 0xf000_0000 16 bit 256MB FLASH on CS0 - - - DDR-SDRAM: - The current realization is made with four 16-bits memory devices. - Mounting options have been foreseen for device architectures from - 4Mx16 to 512Mx16. The kmeter1 is equipped with four 32Mx16 devices - thus resulting in a total capacity of 256MBytes. - -3. Compilation - - Assuming you're using BASH shell: - - export CROSS_COMPILE=your-cross-compile-prefix - cd u-boot - make distclean - make kmeter1_config - make - -4. Downloading and Flashing Images - -4.0 Download over serial line using Kermit: - - loadb - [Drop to kermit: - ^\c - send <u-boot-bin-image> - c - ] - - - Or via tftp: - - tftp 10000 u-boot.bin - => run load - Using UEC0 device - TFTP from server 192.168.1.1; our IP address is 192.168.205.4 - Filename '/tftpboot/kmeter1/u-boot.bin'. - Load address: 0x200000 - Loading: ############## - done - Bytes transferred = 204204 (31dac hex) - => - -4.1 Reflash U-boot Image using U-boot - - => run update - ..... done - Un-Protected 5 sectors - - ..... done - Erased 5 sectors - Copy to Flash... done - ..... done - Protected 5 sectors - Total of 204204 bytes were the same - Saving Environment to Flash... - . done - Un-Protected 1 sectors - . done - Un-Protected 1 sectors - Erasing Flash... - . done - Erased 1 sectors - Writing to Flash... done - . done - Protected 1 sectors - . done - Protected 1 sectors - => - -5. Notes - 1) The console baudrate for kmeter1 is 115200bps. diff --git a/qemu/roms/u-boot/board/keymile/km83xx/km83xx.c b/qemu/roms/u-boot/board/keymile/km83xx/km83xx.c deleted file mode 100644 index 0543483d5..000000000 --- a/qemu/roms/u-boot/board/keymile/km83xx/km83xx.c +++ /dev/null @@ -1,410 +0,0 @@ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu <daveliu@freescale.com> - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada <peterb@logicpd.com> - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov <avorontsov@ru.mvista.com> - * - * (C) Copyright 2008 - 2010 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc83xx.h> -#include <i2c.h> -#include <miiphy.h> -#include <asm/io.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <pci.h> -#include <libfdt.h> -#include <post.h> - -#include "../common/common.h" - -const qe_iop_conf_t qe_iop_conf_tab[] = { - /* port pin dir open_drain assign */ -#if defined(CONFIG_MPC8360) - /* MDIO */ - {0, 1, 3, 0, 2}, /* MDIO */ - {0, 2, 1, 0, 1}, /* MDC */ - - /* UCC4 - UEC */ - {1, 14, 1, 0, 1}, /* TxD0 */ - {1, 15, 1, 0, 1}, /* TxD1 */ - {1, 20, 2, 0, 1}, /* RxD0 */ - {1, 21, 2, 0, 1}, /* RxD1 */ - {1, 18, 1, 0, 1}, /* TX_EN */ - {1, 26, 2, 0, 1}, /* RX_DV */ - {1, 27, 2, 0, 1}, /* RX_ER */ - {1, 24, 2, 0, 1}, /* COL */ - {1, 25, 2, 0, 1}, /* CRS */ - {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */ - {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */ - - /* DUART - UART2 */ - {5, 0, 1, 0, 2}, /* UART2_SOUT */ - {5, 2, 1, 0, 1}, /* UART2_RTS */ - {5, 3, 2, 0, 2}, /* UART2_SIN */ - {5, 1, 2, 0, 3}, /* UART2_CTS */ -#elif !defined(CONFIG_MPC8309) - /* Local Bus */ - {0, 16, 1, 0, 3}, /* LA00 */ - {0, 17, 1, 0, 3}, /* LA01 */ - {0, 18, 1, 0, 3}, /* LA02 */ - {0, 19, 1, 0, 3}, /* LA03 */ - {0, 20, 1, 0, 3}, /* LA04 */ - {0, 21, 1, 0, 3}, /* LA05 */ - {0, 22, 1, 0, 3}, /* LA06 */ - {0, 23, 1, 0, 3}, /* LA07 */ - {0, 24, 1, 0, 3}, /* LA08 */ - {0, 25, 1, 0, 3}, /* LA09 */ - {0, 26, 1, 0, 3}, /* LA10 */ - {0, 27, 1, 0, 3}, /* LA11 */ - {0, 28, 1, 0, 3}, /* LA12 */ - {0, 29, 1, 0, 3}, /* LA13 */ - {0, 30, 1, 0, 3}, /* LA14 */ - {0, 31, 1, 0, 3}, /* LA15 */ - - /* MDIO */ - {3, 4, 3, 0, 2}, /* MDIO */ - {3, 5, 1, 0, 2}, /* MDC */ - - /* UCC4 - UEC */ - {1, 18, 1, 0, 1}, /* TxD0 */ - {1, 19, 1, 0, 1}, /* TxD1 */ - {1, 22, 2, 0, 1}, /* RxD0 */ - {1, 23, 2, 0, 1}, /* RxD1 */ - {1, 26, 2, 0, 1}, /* RxER */ - {1, 28, 2, 0, 1}, /* Rx_DV */ - {1, 30, 1, 0, 1}, /* TxEN */ - {1, 31, 2, 0, 1}, /* CRS */ - {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */ -#endif - - /* END of table */ - {0, 0, 0, 0, QE_IOP_TAB_END}, -}; - -#if defined(CONFIG_SUVD3) -const uint upma_table[] = { - 0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */ - 0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */ - 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */ - 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */ - 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */ - 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */ - 0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */ - 0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */ - 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */ - 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */ - 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */ - 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */ - 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */ - 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */ - 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */ - 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */ -}; -#endif - -static int piggy_present(void) -{ - struct km_bec_fpga __iomem *base = - (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE; - - return in_8(&base->bprth) & PIGGY_PRESENT; -} - -#if defined(CONFIG_KMVECT1) -int ethernet_present(void) -{ - /* ethernet port connected to simple switch without piggy */ - return 1; -} -#else -int ethernet_present(void) -{ - return piggy_present(); -} -#endif - - -int board_early_init_r(void) -{ - struct km_bec_fpga *base = - (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; -#if defined(CONFIG_SUVD3) - immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - fsl_lbc_t *lbc = &immap->im_lbc; - u32 *mxmr = &lbc->mamr; -#endif - -#if defined(CONFIG_MPC8360) - unsigned short svid; - /* - * Because of errata in the UCCs, we have to write to the reserved - * registers to slow the clocks down. - */ - svid = SVR_REV(mfspr(SVR)); - switch (svid) { - case 0x0020: - /* - * MPC8360ECE.pdf QE_ENET10 table 4: - * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) - * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) - */ - setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000); - break; - case 0x0021: - /* - * MPC8360ECE.pdf QE_ENET10 table 4: - * IMMR + 0x14AC[24:27] = 1010 - */ - clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac), - 0x00000050, 0x000000a0); - break; - } -#endif - - /* enable the PHY on the PIGGY */ - setbits_8(&base->pgy_eth, 0x01); - /* enable the Unit LED (green) */ - setbits_8(&base->oprth, WRL_BOOT); - /* enable Application Buffer */ - setbits_8(&base->oprtl, OPRTL_XBUFENA); - -#if defined(CONFIG_SUVD3) - /* configure UPMA for APP1 */ - upmconfig(UPMA, (uint *) upma_table, - sizeof(upma_table) / sizeof(uint)); - out_be32(mxmr, CONFIG_SYS_MAMR); -#endif - return 0; -} - -int misc_init_r(void) -{ - return 0; -} - -#if defined(CONFIG_KMVECT1) -#include <mv88e6352.h> -/* Marvell MV88E6122 switch configuration */ -static struct mv88e_sw_reg extsw_conf[] = { - /* port 1, FRONT_MDI, autoneg */ - { PORT(1), PORT_PHY, NO_SPEED_FOR }, - { PORT(1), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, - { PHY(1), PHY_1000_CTRL, NO_ADV }, - { PHY(1), PHY_SPEC_CTRL, AUTO_MDIX_EN }, - { PHY(1), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST | - FULL_DUPLEX }, - /* port 2, unused */ - { PORT(2), PORT_CTRL, PORT_DIS }, - { PHY(2), PHY_CTRL, PHY_PWR_DOWN }, - { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, - /* port 3, BP_MII (CPU), PHY mode, 100BASE */ - { PORT(3), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, - /* port 4, ESTAR to slot 11, SerDes, 1000BASE-X */ - { PORT(4), PORT_STATUS, NO_PHY_DETECT }, - { PORT(4), PORT_PHY, SPEED_1000_FOR }, - { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, - /* port 5, ESTAR to slot 13, SerDes, 1000BASE-X */ - { PORT(5), PORT_STATUS, NO_PHY_DETECT }, - { PORT(5), PORT_PHY, SPEED_1000_FOR }, - { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, - /* - * Errata Fix: 1.9V Output from Internal 1.8V Regulator, - * acc . MV-S300889-00D.pdf , clause 4.5 - */ - { PORT(5), 0x1A, 0xADB1 }, - /* port 6, unused, this port has no phy */ - { PORT(6), PORT_CTRL, PORT_DIS }, - /* - * Errata Fix: 1.9V Output from Internal 1.8V Regulator, - * acc . MV-S300889-00D.pdf , clause 4.5 - */ - { PORT(5), 0x1A, 0xADB1 }, -}; -#endif - -int last_stage_init(void) -{ -#if defined(CONFIG_KMVECT1) - struct km_bec_fpga __iomem *base = - (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE; - u8 tmp_reg; - - /* Release mv88e6122 from reset */ - tmp_reg = in_8(&base->res1[0]) | 0x10; /* DIRECT3 register */ - out_8(&base->res1[0], tmp_reg); /* GP28 as output */ - tmp_reg = in_8(&base->gprt3) | 0x10; /* GP28 to high */ - out_8(&base->gprt3, tmp_reg); - - /* configure MV88E6122 switch */ - char *name = "UEC2"; - - if (miiphy_set_current_dev(name)) - return 0; - - mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf, - ARRAY_SIZE(extsw_conf)); - - mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR); - - if (piggy_present()) { - setenv("ethact", "UEC2"); - setenv("netdev", "eth1"); - puts("using PIGGY for network boot\n"); - } else { - setenv("netdev", "eth0"); - puts("using frontport for network boot\n"); - } -#endif - -#if defined(CONFIG_KMCOGE5NE) - struct bfticu_iomap *base = - (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE; - u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK; - - if (dip_switch != 0) { - /* start bootloader */ - puts("DIP: Enabled\n"); - setenv("actual_bank", "0"); - } -#endif - set_km_env(); - return 0; -} - -static int fixed_sdram(void) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e)); - out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f); - out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); - out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); - out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); - out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); - out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); - out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); - out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); - out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); - out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); - udelay(200); - setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); - - msize = CONFIG_SYS_DDR_SIZE << 20; - disable_addr_trans(); - msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize); - enable_addr_trans(); - msize /= (1024 * 1024); - if (CONFIG_SYS_DDR_SIZE != msize) { - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); - ddr_size = ddr_size >> 1, ddr_size_log2++) - if (ddr_size & 1) - return -1; - out_be32(&im->sysconf.ddrlaw[0].ar, - (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE))); - out_be32(&im->ddr.csbnds[0].csbnds, - (((msize / 16) - 1) & 0xff)); - } - - return msize; -} - -phys_size_t initdram(int board_type) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = 0; - - if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) - return -1; - - out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_DDR_BASE & LAWBAR_BAR); - msize = fixed_sdram(); - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize DDR ECC byte - */ - ddr_enable_ecc(msize * 1024 * 1024); -#endif - - /* return total bus SDRAM size(bytes) -- DDR */ - return msize * 1024 * 1024; -} - -int checkboard(void) -{ - puts("Board: Keymile " CONFIG_KM_BOARD_NAME); - - if (piggy_present()) - puts(" with PIGGY."); - puts("\n"); - return 0; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -} -#endif - -#if defined(CONFIG_HUSH_INIT_VAR) -int hush_init_var(void) -{ - ivm_read_eeprom(); - return 0; -} -#endif - -#if defined(CONFIG_POST) -int post_hotkeys_pressed(void) -{ - int testpin = 0; - struct km_bec_fpga *base = - (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; - int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG); - testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0; - debug("post_hotkeys_pressed: %d\n", !testpin); - return testpin; -} - -ulong post_word_load(void) -{ - void* addr = (ulong *) (CPM_POST_WORD_ADDR); - debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr)); - return in_le32(addr); - -} -void post_word_store(ulong value) -{ - void* addr = (ulong *) (CPM_POST_WORD_ADDR); - debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value); - out_le32(addr, value); -} - -int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) -{ - *vstart = CONFIG_SYS_MEMTEST_START; - *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START; - debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size); - - return 0; -} -#endif diff --git a/qemu/roms/u-boot/board/keymile/km83xx/km83xx_i2c.c b/qemu/roms/u-boot/board/keymile/km83xx/km83xx_i2c.c deleted file mode 100644 index c96193753..000000000 --- a/qemu/roms/u-boot/board/keymile/km83xx/km83xx_i2c.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * (C) Copyright 2011 - * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <i2c.h> -#include <asm/io.h> -#include <linux/ctype.h> -#include "../common/common.h" - -static void i2c_write_start_seq(void) -{ - struct fsl_i2c *dev; - dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); - udelay(DELAY_ABORT_SEQ); - out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA)); - udelay(DELAY_ABORT_SEQ); - out_8(&dev->cr, (I2C_CR_MEN)); -} - -int i2c_make_abort(void) -{ - struct fsl_i2c *dev; - dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); - uchar last; - int nbr_read = 0; - int i = 0; - int ret = 0; - - /* wait after each operation to finsh with a delay */ - out_8(&dev->cr, (I2C_CR_MSTA)); - udelay(DELAY_ABORT_SEQ); - out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA)); - udelay(DELAY_ABORT_SEQ); - in_8(&dev->dr); - udelay(DELAY_ABORT_SEQ); - last = in_8(&dev->dr); - nbr_read++; - - /* - * do read until the last bit is 1, but stop if the full eeprom is - * read. - */ - while (((last & 0x01) != 0x01) && - (nbr_read < CONFIG_SYS_IVM_EEPROM_MAX_LEN)) { - udelay(DELAY_ABORT_SEQ); - last = in_8(&dev->dr); - nbr_read++; - } - if ((last & 0x01) != 0x01) - ret = -2; - if ((last != 0xff) || (nbr_read > 1)) - printf("[INFO] i2c abort after %d bytes (0x%02x)\n", - nbr_read, last); - udelay(DELAY_ABORT_SEQ); - out_8(&dev->cr, (I2C_CR_MEN)); - udelay(DELAY_ABORT_SEQ); - /* clear status reg */ - out_8(&dev->sr, 0); - - for (i = 0; i < 5; i++) - i2c_write_start_seq(); - if (ret != 0) - printf("[ERROR] i2c abort failed after %d bytes (0x%02x)\n", - nbr_read, last); - - return ret; -} diff --git a/qemu/roms/u-boot/board/keymile/km_arm/Makefile b/qemu/roms/u-boot/board/keymile/km_arm/Makefile deleted file mode 100644 index a17d8d963..000000000 --- a/qemu/roms/u-boot/board/keymile/km_arm/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Prafulla Wadaskar <prafulla@marvell.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := km_arm.o ../common/common.o ../common/ivm.o - -ifdef CONFIG_KM_FPGA_CONFIG -obj-y += fpga_config.o -endif diff --git a/qemu/roms/u-boot/board/keymile/km_arm/fpga_config.c b/qemu/roms/u-boot/board/keymile/km_arm/fpga_config.c deleted file mode 100644 index 51a3cfe64..000000000 --- a/qemu/roms/u-boot/board/keymile/km_arm/fpga_config.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * (C) Copyright 2012 - * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <i2c.h> -#include <asm/errno.h> - -/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */ -#define KM_XLX_PROGRAM_B_PIN 39 - -#define BOCO_ADDR 0x10 - -#define ID_REG 0x00 -#define BOCO2_ID 0x5b - -static int check_boco2(void) -{ - int ret; - u8 id; - - ret = i2c_read(BOCO_ADDR, ID_REG, 1, &id, 1); - if (ret) { - printf("%s: error reading the BOCO id !!\n", __func__); - return ret; - } - - return (id == BOCO2_ID); -} - -static int boco_clear_bits(u8 reg, u8 flags) -{ - int ret; - u8 regval; - - /* give access to the EEPROM from FPGA */ - ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1); - if (ret) { - printf("%s: error reading the BOCO @%#x !!\n", - __func__, reg); - return ret; - } - regval &= ~flags; - ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1); - if (ret) { - printf("%s: error writing the BOCO @%#x !!\n", - __func__, reg); - return ret; - } - - return 0; -} - -static int boco_set_bits(u8 reg, u8 flags) -{ - int ret; - u8 regval; - - /* give access to the EEPROM from FPGA */ - ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1); - if (ret) { - printf("%s: error reading the BOCO @%#x !!\n", - __func__, reg); - return ret; - } - regval |= flags; - ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1); - if (ret) { - printf("%s: error writing the BOCO @%#x !!\n", - __func__, reg); - return ret; - } - - return 0; -} - -#define SPI_REG 0x06 -#define CFG_EEPROM 0x02 -#define FPGA_PROG 0x04 -#define FPGA_INIT_B 0x10 -#define FPGA_DONE 0x20 - -static int fpga_done(void) -{ - int ret = 0; - u8 regval; - - /* this is only supported with the boco2 design */ - if (!check_boco2()) - return 0; - - ret = i2c_read(BOCO_ADDR, SPI_REG, 1, ®val, 1); - if (ret) { - printf("%s: error reading the BOCO @%#x !!\n", - __func__, SPI_REG); - return 0; - } - - return regval & FPGA_DONE ? 1 : 0; -} - -int skip; - -int trigger_fpga_config(void) -{ - int ret = 0; - - /* if the FPGA is already configured, we do not want to - * reconfigure it */ - skip = 0; - if (fpga_done()) { - printf("PCIe FPGA config: skipped\n"); - skip = 1; - return 0; - } - - if (check_boco2()) { - /* we have a BOCO2, this has to be triggered here */ - - /* make sure the FPGA_can access the EEPROM */ - ret = boco_clear_bits(SPI_REG, CFG_EEPROM); - if (ret) - return ret; - - /* trigger the config start */ - ret = boco_clear_bits(SPI_REG, FPGA_PROG | FPGA_INIT_B); - if (ret) - return ret; - - /* small delay for the pulse */ - udelay(10); - - /* up signal for pulse end */ - ret = boco_set_bits(SPI_REG, FPGA_PROG); - if (ret) - return ret; - - /* finally, raise INIT_B to remove the config delay */ - ret = boco_set_bits(SPI_REG, FPGA_INIT_B); - if (ret) - return ret; - - } else { - /* we do it the old way, with the gpio pin */ - kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1); - kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0); - /* small delay for the pulse */ - udelay(10); - kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN); - } - - return 0; -} - -int wait_for_fpga_config(void) -{ - int ret = 0; - u8 spictrl; - u32 timeout = 20000; - - if (skip) - return 0; - - if (!check_boco2()) { - /* we do not have BOCO2, this is not really used */ - return 0; - } - - printf("PCIe FPGA config:"); - do { - ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &spictrl, 1); - if (ret) { - printf("%s: error reading the BOCO spictrl !!\n", - __func__); - return ret; - } - if (timeout-- == 0) { - printf(" FPGA_DONE timeout\n"); - return -EFAULT; - } - udelay(10); - } while (!(spictrl & FPGA_DONE)); - - printf(" done\n"); - - return 0; -} - -#if defined(KM_PCIE_RESET_MPP7) - -#define KM_PEX_RST_GPIO_PIN 7 -int fpga_reset(void) -{ - if (!check_boco2()) { - /* we do not have BOCO2, this is not really used */ - return 0; - } - - printf("PCIe reset through GPIO7: "); - /* apply PCIe reset via GPIO */ - kw_gpio_set_valid(KM_PEX_RST_GPIO_PIN, 1); - kw_gpio_direction_output(KM_PEX_RST_GPIO_PIN, 1); - kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 0); - udelay(1000*10); - kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 1); - - printf(" done\n"); - - return 0; -} - -#else - -#define PRST1 0x4 -#define PCIE_RST 0x10 -#define TRAFFIC_RST 0x04 - -int fpga_reset(void) -{ - int ret = 0; - u8 resets; - - if (!check_boco2()) { - /* we do not have BOCO2, this is not really used */ - return 0; - } - - /* if we have skipped, we only want to reset the PCIe part */ - resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST; - - ret = boco_clear_bits(PRST1, resets); - if (ret) - return ret; - - /* small delay for the pulse */ - udelay(10); - - ret = boco_set_bits(PRST1, resets); - if (ret) - return ret; - - return 0; -} -#endif - -/* the FPGA was configured, we configure the BOCO2 so that the EEPROM - * is available from the Bobcat SPI bus */ -int toggle_eeprom_spi_bus(void) -{ - int ret = 0; - - if (!check_boco2()) { - /* we do not have BOCO2, this is not really used */ - return 0; - } - - ret = boco_set_bits(SPI_REG, CFG_EEPROM); - if (ret) - return ret; - - return 0; -} diff --git a/qemu/roms/u-boot/board/keymile/km_arm/km_arm.c b/qemu/roms/u-boot/board/keymile/km_arm/km_arm.c deleted file mode 100644 index 35402c800..000000000 --- a/qemu/roms/u-boot/board/keymile/km_arm/km_arm.c +++ /dev/null @@ -1,495 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Prafulla Wadaskar <prafulla@marvell.com> - * - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2010 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <i2c.h> -#include <nand.h> -#include <netdev.h> -#include <miiphy.h> -#include <spi.h> -#include <asm/io.h> -#include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> -#include <asm/arch/mpp.h> - -#include "../common/common.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * BOCO FPGA definitions - */ -#define BOCO 0x10 -#define REG_CTRL_H 0x02 -#define MASK_WRL_UNITRUN 0x01 -#define MASK_RBX_PGY_PRESENT 0x40 -#define REG_IRQ_CIRQ2 0x2d -#define MASK_RBI_DEFECT_16 0x01 - -/* Multi-Purpose Pins Functionality configuration */ -static const u32 kwmpp_config[] = { - MPP0_NF_IO2, - MPP1_NF_IO3, - MPP2_NF_IO4, - MPP3_NF_IO5, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP6_SYSRST_OUTn, -#if defined(KM_PCIE_RESET_MPP7) - MPP7_GPO, -#else - MPP7_PEX_RST_OUTn, -#endif -#if defined(CONFIG_SYS_I2C_SOFT) - MPP8_GPIO, /* SDA */ - MPP9_GPIO, /* SCL */ -#endif -#if defined(CONFIG_HARD_I2C) - MPP8_TW_SDA, - MPP9_TW_SCK, -#endif - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_GPO, /* Reserved */ - MPP13_UART1_TXD, - MPP14_UART1_RXD, - MPP15_GPIO, /* Not used */ - MPP16_GPIO, /* Not used */ - MPP17_GPIO, /* Reserved */ - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP20_GPIO, - MPP21_GPIO, - MPP22_GPIO, - MPP23_GPIO, - MPP24_GPIO, - MPP25_GPIO, - MPP26_GPIO, - MPP27_GPIO, - MPP28_GPIO, - MPP29_GPIO, - MPP30_GPIO, - MPP31_GPIO, - MPP32_GPIO, - MPP33_GPIO, - MPP34_GPIO, /* CDL1 (input) */ - MPP35_GPIO, /* CDL2 (input) */ - MPP36_GPIO, /* MAIN_IRQ (input) */ - MPP37_GPIO, /* BOARD_LED */ - MPP38_GPIO, /* Piggy3 LED[1] */ - MPP39_GPIO, /* Piggy3 LED[2] */ - MPP40_GPIO, /* Piggy3 LED[3] */ - MPP41_GPIO, /* Piggy3 LED[4] */ - MPP42_GPIO, /* Piggy3 LED[5] */ - MPP43_GPIO, /* Piggy3 LED[6] */ - MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */ - MPP45_GPIO, /* Piggy3 LED[8] */ - MPP46_GPIO, /* Reserved */ - MPP47_GPIO, /* Reserved */ - MPP48_GPIO, /* Reserved */ - MPP49_GPIO, /* SW_INTOUTn */ - 0 -}; - -#if defined(CONFIG_KM_MGCOGE3UN) -/* - * Wait for startup OK from mgcoge3ne - */ -static int startup_allowed(void) -{ - unsigned char buf; - - /* - * Read CIRQ16 bit (bit 0) - */ - if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0) - printf("%s: Error reading Boco\n", __func__); - else - if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16) - return 1; - return 0; -} -#endif - -#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352)) -/* - * All boards with PIGGY4 connected via a simple switch have ethernet always - * present. - */ -int ethernet_present(void) -{ - return 1; -} -#else -int ethernet_present(void) -{ - uchar buf; - int ret = 0; - - if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { - printf("%s: Error reading Boco\n", __func__); - return -1; - } - if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT) - ret = 1; - - return ret; -} -#endif - -static int initialize_unit_leds(void) -{ - /* - * Init the unit LEDs per default they all are - * ok apart from bootstat - */ - uchar buf; - - if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { - printf("%s: Error reading Boco\n", __func__); - return -1; - } - buf |= MASK_WRL_UNITRUN; - if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { - printf("%s: Error writing Boco\n", __func__); - return -1; - } - return 0; -} - -static void set_bootcount_addr(void) -{ - uchar buf[32]; - unsigned int bootcountaddr; - bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR; - sprintf((char *)buf, "0x%x", bootcountaddr); - setenv("bootcountaddr", (char *)buf); -} - -int misc_init_r(void) -{ -#if defined(CONFIG_KM_MGCOGE3UN) - char *wait_for_ne; - wait_for_ne = getenv("waitforne"); - if (wait_for_ne != NULL) { - if (strcmp(wait_for_ne, "true") == 0) { - int cnt = 0; - int abort = 0; - puts("NE go: "); - while (startup_allowed() == 0) { - if (tstc()) { - (void) getc(); /* consume input */ - abort = 1; - break; - } - udelay(200000); - cnt++; - if (cnt == 5) - puts("wait\b\b\b\b"); - if (cnt == 10) { - cnt = 0; - puts(" \b\b\b\b"); - } - } - if (abort == 1) - printf("\nAbort waiting for ne\n"); - else - puts("OK\n"); - } - } -#endif - - initialize_unit_leds(); - set_km_env(); - set_bootcount_addr(); - return 0; -} - -int board_early_init_f(void) -{ -#if defined(CONFIG_SYS_I2C_SOFT) - u32 tmp; - - /* set the 2 bitbang i2c pins as output gpios */ - tmp = readl(KW_GPIO0_BASE + 4); - writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4); -#endif - /* adjust SDRAM size for bank 0 */ - kw_sdram_size_adjust(0); - kirkwood_mpp_conf(kwmpp_config, NULL); - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; - - /* - * The KM_FLASH_GPIO_PIN switches between using a - * NAND or a SPI FLASH. Set this pin on start - * to NAND mode. - */ - kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1); - kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1); - -#if defined(CONFIG_SYS_I2C_SOFT) - /* - * Reinit the GPIO for I2C Bitbang driver so that the now - * available gpio framework is consistent. The calls to - * direction output in are not necessary, they are already done in - * board_early_init_f - */ - kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); - kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1); -#endif - -#if defined(CONFIG_SYS_EEPROM_WREN) - kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); - kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); -#endif - -#if defined(CONFIG_KM_FPGA_CONFIG) - trigger_fpga_config(); -#endif - - return 0; -} - -int board_late_init(void) -{ -#if defined(CONFIG_KMCOGE5UN) -/* I/O pin to erase flash RGPP09 = MPP43 */ -#define KM_FLASH_ERASE_ENABLE 43 - u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE); - - /* if pin 1 do full erase */ - if (dip_switch != 0) { - /* start bootloader */ - puts("DIP: Enabled\n"); - setenv("actual_bank", "0"); - } -#endif - -#if defined(CONFIG_KM_FPGA_CONFIG) - wait_for_fpga_config(); - fpga_reset(); - toggle_eeprom_spi_bus(); -#endif - return 0; -} - -int board_spi_claim_bus(struct spi_slave *slave) -{ - kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0); - - return 0; -} - -void board_spi_release_bus(struct spi_slave *slave) -{ - kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1); -} - -#if (defined(CONFIG_KM_PIGGY4_88E6061)) - -#define PHY_LED_SEL_REG 0x18 -#define PHY_LED0_LINK (0x5) -#define PHY_LED1_ACT (0x8<<4) -#define PHY_LED2_INT (0xe<<8) -#define PHY_SPEC_CTRL_REG 0x1c -#define PHY_RGMII_CLK_STABLE (0x1<<10) -#define PHY_CLSA (0x1<<1) - -/* Configure and enable MV88E3018 PHY */ -void reset_phy(void) -{ - char *name = "egiga0"; - unsigned short reg; - - if (miiphy_set_current_dev(name)) - return; - - /* RGMII clk transition on data stable */ - if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®)) - printf("Error reading PHY spec ctrl reg\n"); - if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, - reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) - printf("Error writing PHY spec ctrl reg\n"); - - /* leds setup */ - if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, - PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) - printf("Error writing PHY LED reg\n"); - - /* reset the phy */ - miiphy_reset(name, CONFIG_PHY_BASE_ADR); -} -#elif defined(CONFIG_KM_PIGGY4_88E6352) - -#include <mv88e6352.h> - -#if defined(CONFIG_KM_NUSA) -struct mv88e_sw_reg extsw_conf[] = { - /* - * port 0, PIGGY4, autoneg - * first the fix for the 1000Mbits Autoneg, this is from - * a Marvell errata, the regs are undocumented - */ - { PHY(0), PHY_PAGE, AN1000FIX_PAGE }, - { PHY(0), PHY_STATUS, AN1000FIX }, - { PHY(0), PHY_PAGE, 0 }, - /* now the real port and phy configuration */ - { PORT(0), PORT_PHY, NO_SPEED_FOR }, - { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, - { PHY(0), PHY_1000_CTRL, NO_ADV }, - { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN }, - { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST | - FULL_DUPLEX }, - /* port 1, unused */ - { PORT(1), PORT_CTRL, PORT_DIS }, - { PHY(1), PHY_CTRL, PHY_PWR_DOWN }, - { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, - /* port 2, unused */ - { PORT(2), PORT_CTRL, PORT_DIS }, - { PHY(2), PHY_CTRL, PHY_PWR_DOWN }, - { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, - /* port 3, unused */ - { PORT(3), PORT_CTRL, PORT_DIS }, - { PHY(3), PHY_CTRL, PHY_PWR_DOWN }, - { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, - /* port 4, ICNEV, SerDes, SGMII */ - { PORT(4), PORT_STATUS, NO_PHY_DETECT }, - { PORT(4), PORT_PHY, SPEED_1000_FOR }, - { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, - { PHY(4), PHY_CTRL, PHY_PWR_DOWN }, - { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, - /* port 5, CPU_RGMII */ - { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN | - FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX | - FULL_DPX_FOR | SPEED_1000_FOR }, - { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, - /* port 6, unused, this port has no phy */ - { PORT(6), PORT_CTRL, PORT_DIS }, -}; -#else -struct mv88e_sw_reg extsw_conf[] = {}; -#endif - -void reset_phy(void) -{ -#if defined(CONFIG_KM_MVEXTSW_ADDR) - char *name = "egiga0"; - - if (miiphy_set_current_dev(name)) - return; - - mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf, - ARRAY_SIZE(extsw_conf)); - mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR); -#endif -} - -#else -/* Configure and enable MV88E1118 PHY on the piggy*/ -void reset_phy(void) -{ - char *name = "egiga0"; - - if (miiphy_set_current_dev(name)) - return; - - /* reset the phy */ - miiphy_reset(name, CONFIG_PHY_BASE_ADR); -} -#endif - - -#if defined(CONFIG_HUSH_INIT_VAR) -int hush_init_var(void) -{ - ivm_read_eeprom(); - return 0; -} -#endif - -#if defined(CONFIG_SYS_I2C_SOFT) -void set_sda(int state) -{ - I2C_ACTIVE; - I2C_SDA(state); -} - -void set_scl(int state) -{ - I2C_SCL(state); -} - -int get_sda(void) -{ - I2C_TRISTATE; - return I2C_READ; -} - -int get_scl(void) -{ - return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0; -} -#endif - -#if defined(CONFIG_POST) - -#define KM_POST_EN_L 44 -#define POST_WORD_OFF 8 - -int post_hotkeys_pressed(void) -{ -#if defined(CONFIG_KM_COGE5UN) - return kw_gpio_get_value(KM_POST_EN_L); -#else - return !kw_gpio_get_value(KM_POST_EN_L); -#endif -} - -ulong post_word_load(void) -{ - void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); - return in_le32(addr); - -} -void post_word_store(ulong value) -{ - void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); - out_le32(addr, value); -} - -int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) -{ - *vstart = CONFIG_SYS_SDRAM_BASE; - - /* we go up to relocation plus a 1 MB margin */ - *size = CONFIG_SYS_TEXT_BASE - (1<<20); - - return 0; -} -#endif - -#if defined(CONFIG_SYS_EEPROM_WREN) -int eeprom_write_enable(unsigned dev_addr, int state) -{ - kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state); - - return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP); -} -#endif diff --git a/qemu/roms/u-boot/board/keymile/km_arm/kwbimage-memphis.cfg b/qemu/roms/u-boot/board/keymile/km_arm/kwbimage-memphis.cfg deleted file mode 100644 index e910f4216..000000000 --- a/qemu/roms/u-boot/board/keymile/km_arm/kwbimage-memphis.cfg +++ /dev/null @@ -1,181 +0,0 @@ -# -# (C) Copyright 2010 -# Heiko Schocher, DENX Software Engineering, hs@denx.de. -# -# (C) Copyright 2011 -# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM spi # Boot from SPI flash - -DATA 0xFFD10000 0x01112222 # MPP Control 0 Register -# bit 3-0: MPPSel0 2, NF_IO[2] -# bit 7-4: MPPSel1 2, NF_IO[3] -# bit 12-8: MPPSel2 2, NF_IO[4] -# bit 15-12: MPPSel3 2, NF_IO[5] -# bit 19-16: MPPSel4 1, NF_IO[6] -# bit 23-20: MPPSel5 1, NF_IO[7] -# bit 27-24: MPPSel6 1, SYSRST_O -# bit 31-28: MPPSel7 0, GPO[7] - -DATA 0xFFD10004 0x03303300 - -DATA 0xFFD10008 0x00001100 # MPP Control 2 Register -# bit 3-0: MPPSel16 0, GPIO[16] -# bit 7-4: MPPSel17 0, GPIO[17] -# bit 12-8: MPPSel18 1, NF_IO[0] -# bit 15-12: MPPSel19 1, NF_IO[1] -# bit 19-16: MPPSel20 0, GPIO[20] -# bit 23-20: MPPSel21 0, GPIO[21] -# bit 27-24: MPPSel22 0, GPIO[22] -# bit 31-28: MPPSel23 0, GPIO[23] - -DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register -DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register -DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register - -# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! -# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage - -#Dram initalization -DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register -# bit13-0: 0x4E0 (DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01 - -DATA 0xFFD01404 0x38543000 # DDR Controller Control Low -# bit 3-0: 0 reserved -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 8= CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay - -DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1) -# bit3-0: TRAS lsbs -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP - -DATA 0xFFD0140C 0x00000A3E # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required - -DATA 0xFFD01410 0x00000001 # DDR Address Control -# bit1-0: 01, Cs0width=x16 -# bit3-2: 00, Cs0size=2Gb -# bit5-4: 00, Cs2width=nonexistent -# bit7-6: 00, Cs1size =nonexistent -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required - -DATA 0xFFD0141C 0x00000652 # DDR Mode -DATA 0xFFD01420 0x00000006 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 1, DDR drive strenght reduced -# bit2: 1, DDR ODT control lsd disabled -# bit5-3: 000, required -# bit6: 0, DDR ODT control msb disabled -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required - -DATA 0xFFD01424 0x0000F17F # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 0 -# bit8 : 1 , add a sample stage -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required - -DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low -# bit3-0 : 0000, required -# bit7-4 : 0010, M_ODT assertion 2 cycles after read -# bit11-8 : 0101, M_ODT de-assertion 5 cycles after read -# bit15-12: 0100, internal ODT assertion 4 cycles after read -# bit19-16: 1000, internal ODT de-assertion 8 cycles after read -# bit31-20: 0 , required - -DATA 0xFFD0147c 0x00008451 # DDR2 SDRAM Timing High -# bit3-0 : 0001, M_ODT assertion same cycle as write -# bit7-4 : 0101, M_ODT de-assertion x cycles after write -# bit11-8 : 0100, internal ODT assertion x cycles after write -# bit15-12: 1000, internal ODT de-assertion x cycles after write - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x0F, Size (i.e. 256MB) - -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) -# bit3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 -# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 - -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above -# bit3-2: 00, ODT1 controlled by register -# bit31-4: zero, required - -DATA 0xFFD0149C 0x0000F801 # CPU ODT Control -# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 -# bit7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0 -# bit9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr -# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm -# bit13-12:3, STARTBURST ODT buffer selected, 50 ohm -# bit14 :1, STARTBURST ODT enabled -# bit15 :1, Use ODT Block - -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -# bit0=1, enable DDR init upon this register write - -# End of Header extension -DATA 0x0 0x0 diff --git a/qemu/roms/u-boot/board/keymile/km_arm/kwbimage.cfg b/qemu/roms/u-boot/board/keymile/km_arm/kwbimage.cfg deleted file mode 100644 index ce2c3e29d..000000000 --- a/qemu/roms/u-boot/board/keymile/km_arm/kwbimage.cfg +++ /dev/null @@ -1,163 +0,0 @@ -# -# (C) Copyright 2010 -# Heiko Schocher, DENX Software Engineering, hs@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM spi # Boot from SPI flash - -DATA 0xFFD10000 0x01112222 # MPP Control 0 Register -# bit 3-0: MPPSel0 2, NF_IO[2] -# bit 7-4: MPPSel1 2, NF_IO[3] -# bit 12-8: MPPSel2 2, NF_IO[4] -# bit 15-12: MPPSel3 2, NF_IO[5] -# bit 19-16: MPPSel4 1, NF_IO[6] -# bit 23-20: MPPSel5 1, NF_IO[7] -# bit 27-24: MPPSel6 1, SYSRST_O -# bit 31-28: MPPSel7 0, GPO[7] - -DATA 0xFFD10004 0x03303300 - -DATA 0xFFD10008 0x00001100 # MPP Control 2 Register -# bit 3-0: MPPSel16 0, GPIO[16] -# bit 7-4: MPPSel17 0, GPIO[17] -# bit 12-8: MPPSel18 1, NF_IO[0] -# bit 15-12: MPPSel19 1, NF_IO[1] -# bit 19-16: MPPSel20 0, GPIO[20] -# bit 23-20: MPPSel21 0, GPIO[21] -# bit 27-24: MPPSel22 0, GPIO[22] -# bit 31-28: MPPSel23 0, GPIO[23] - -DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register -DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register -DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register - -# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! -# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage - -#Dram initalization -DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register -# bit13-0: 0x400 (DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01 - -DATA 0xFFD01404 0x39543000 # DDR Controller Control Low -# bit 3-0: 0 reserved -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay - -DATA 0xFFD01408 0x34136552 # DDR Timing (Low) (active cycles value +1) -# bit3-0: TRAS lsbs -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP - -DATA 0xFFD0140C 0x00000033 # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required - -DATA 0xFFD01410 0x0000000D # DDR Address Control -# bit1-0: 01, Cs0width=x16 -# bit3-2: 11, Cs0size=1Gb -# bit5-4: 00, Cs2width=nonexistent -# bit7-6: 00, Cs1size =nonexistent -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required - -DATA 0xFFD0141C 0x00000652 # DDR Mode -DATA 0xFFD01420 0x00000044 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 0, DDR drive strenght normal -# bit2: 1, DDR ODT control lsd disabled -# bit5-3: 000, required -# bit6: 1, DDR ODT control msb, enabled -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required - -DATA 0xFFD01424 0x0000F07F # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 0 -# bit8 : 0 , no sample stage -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required -DATA 0xFFD01428 0x00074510 -DATA 0xFFD0147c 0x00007451 - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x07, Size (i.e. 128MB) - -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low) -# bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0 -# bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0 - -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above -# bit3-2: 00, ODT1 controlled by register -# bit31-4: zero, required - -DATA 0xFFD0149C 0x0000FC11 # CPU ODT Control -# bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0 -# bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0 -# bit9-8: 1, ODTEn, never active -# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm - -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -# bit0=1, enable DDR init upon this register write - -# End of Header extension -DATA 0x0 0x0 diff --git a/qemu/roms/u-boot/board/keymile/km_arm/kwbimage_128M16_1.cfg b/qemu/roms/u-boot/board/keymile/km_arm/kwbimage_128M16_1.cfg deleted file mode 100644 index 71e3609cf..000000000 --- a/qemu/roms/u-boot/board/keymile/km_arm/kwbimage_128M16_1.cfg +++ /dev/null @@ -1,257 +0,0 @@ -# -# (C) Copyright 2010 -# Heiko Schocher, DENX Software Engineering, hs@denx.de. -# -# (C) Copyright 2012 -# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com -# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com -# -# (C) Copyright 2012 -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM spi # Boot from SPI flash - -DATA 0xFFD10000 0x01112222 # MPP Control 0 Register -# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) -# bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3]) -# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) -# bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5]) -# bit 19-16: 1, MPPSel4 NF_IO[6] -# bit 23-20: 1, MPPSel5 NF_IO[7] -# bit 27-24: 1, MPPSel6 SYSRST_O -# bit 31-28: 0, MPPSel7 GPO[7] - -DATA 0xFFD10004 0x03303300 # MPP Control 1 Register -# bit 3-0: 0, MPPSel8 GPIO[8] -# bit 7-4: 0, MPPSel9 GPIO[9] -# bit 12-8: 3, MPPSel10 UA0_TXD -# bit 15-12: 3, MPPSel11 UA0_RXD -# bit 19-16: 0, MPPSel12 not connected -# bit 23-20: 3, MPPSel13 UA1_TXD -# bit 27-24: 3, MPPSel14 UA1_RXD -# bit 31-28: 0, MPPSel15 GPIO[15] - -DATA 0xFFD10008 0x00001100 # MPP Control 2 Register -# bit 3-0: 0, MPPSel16 GPIO[16] -# bit 7-4: 0, MPPSel17 not connected -# bit 12-8: 1, MPPSel18 NF_IO[0] -# bit 15-12: 1, MPPSel19 NF_IO[1] -# bit 19-16: 0, MPPSel20 GPIO[20] -# bit 23-20: 0, MPPSel21 GPIO[21] -# bit 27-24: 0, MPPSel22 GPIO[22] -# bit 31-28: 0, MPPSel23 GPIO[23] - -# MPP Control 3-6 Register untouched (MPP24-49) - -DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register -# bit 2-0: 3, Reserved -# bit 5-3: 3, Reserved -# bit 6: 0, Reserved -# bit 7: 0, RGMII-pads voltage = 3.3V -# bit 10-8: 3, Reserved -# bit 13-11: 3, Reserved -# bit 14: 0, Reserved -# bit 15: 0, MPP RGMII-pads voltage = 3.3V -# bit 31-16 0x1B1B, Reserved - -DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register -# bit 0-1: 2, Tag RAM RTC RAM0 -# bit 3-2: 1, Tag RAM WTC RAM0 -# bit 7-4: 6, Reserve -# bit 9-8: 2, Valid RAM RTC RAM -# bit 11-10: 1, Valid RAM WTC RAM -# bit 13-12: 2, Dirty RAM RTC RAM -# bit 15-14: 1, Dirty RAM WTC RAM -# bit 17-16: 2, Data RAM RTC RAM0 -# bit 19-18: 1, Data RAM WTC RAM0 -# bit 21-20: 2, Data RAM RTC RAM1 -# bit 23-22: 1, Data RAM WTC RAM1 -# bit 25-24: 2, Data RAM RTC RAM2 -# bit 27-26: 1, Data RAM WTC RAM2 -# bit 29-28: 2, Data RAM RTC RAM3 -# bit 31-30: 1, Data RAM WTC RAM4 - -DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register -# bit 15-0: ???, Reserve -# bit 17-16: 2, ECC RAM RTC RAM0 -# bit 19-18: 1, ECC RAM WTC RAM0 -# bit 31-20: ???,Reserve - -# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! -# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage - -# SDRAM initalization -DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register -# bit 13-0: 0x4E0, DDR2 clks refresh rate -# bit 14: 0, reserved -# bit 15: 0, reserved -# bit 16: 0, CPU to Dram Write buffer policy -# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic -# bit 19-18: 0, reserved -# bit 23-20: 0, reserved -# bit 24: 1, enable exit self refresh mode on DDR access -# bit 25: 1, required -# bit 29-26: 0, reserved -# bit 31-30: 1, reserved - -DATA 0xFFD01404 0x36543000 # DDR Controller Control Low -# bit 3-0: 0, reserved -# bit 4: 0, 2T mode =addr/cmd in same cycle -# bit 5: 0, clk is driven during self refresh, we don't care for APX -# bit 6: 0, use recommended falling edge of clk for addr/cmd -# bit 7-11: 0, reserved -# bit 12-13: 1, reserved, required 1 -# bit 14: 0, input buffer always powered up -# bit 17-15: 0, reserved -# bit 18: 1, cpu lock transaction enabled -# bit 19: 0, reserved -# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 -# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM -# bit 30-28: 3, required -# bit 31: 0,no additional STARTBURST delay - -DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1) -# bit 3-0: 0xE, TRAS, 15 clk (45 ns) -# bit 7-4: 0x4, TRCD, 5 clk (15 ns) -# bit 11-8: 0x4, TRP, 5 clk (15 ns) -# bit 15-12: 0x4, TWR, 5 clk (15 ns) -# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns) -# bit 20: 0, extended TRAS msb -# bit 23-21: 0, reserved -# bit 27-24: 0x3, TRRD, 4 clk (10 ns) -# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns) - -DATA 0xFFD0140C 0x0000003e # DDR Timing (High) -# bit 6-0: 0x3E, TRFC, 63 clk (195 ns) -# bit 8-7: 0, TR2R -# bit 10-9: 0, TR2W -# bit 12-11: 0, TW2W -# bit 31-13: 0, reserved - -DATA 0xFFD01410 0x00000001 # DDR Address Control -# bit 1-0: 1, Cs0width=x16 -# bit 3-2: 0, Cs0size=2Gb -# bit 5-4: 0, Cs1width=nonexistent -# bit 7-6: 0, Cs1size =nonexistent -# bit 9-8: 0, Cs2width=nonexistent -# bit 11-10: 0, Cs2size =nonexistent -# bit 13-12: 0, Cs3width=nonexistent -# bit 15-14: 0, Cs3size =nonexistent -# bit 16: 0, Cs0AddrSel -# bit 17: 0, Cs1AddrSel -# bit 18: 0, Cs2AddrSel -# bit 19: 0, Cs3AddrSel -# bit 31-20: 0, required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit 0: 0, OpenPage enabled -# bit 31-1: 0, required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit 3-0: 0, DDR cmd -# bit 31-4: 0, required - -DATA 0xFFD0141C 0x00000652 # DDR Mode -# bit 2-0: 2, Burst Length = 4 -# bit 3: 0, Burst Type -# bit 6-4: 5, CAS Latency = 5 -# bit 7: 0, Test mode -# bit 8: 0, DLL Reset -# bit 11-9: 3, Write recovery for auto-precharge must be 3 -# bit 12: 0, Active power down exit time, fast exit -# bit 14-13: 0, reserved -# bit 31-15: 0, reserved - -DATA 0xFFD01420 0x00000006 # DDR Extended Mode -# bit 0: 0, DDR DLL enabled -# bit 1: 1, DDR drive strength reduced -# bit 2: 1, DDR ODT control lsb, 75 ohm termination [RTT0] -# bit 5-3: 0, required -# bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1] -# bit 9-7: 0, required -# bit 10: 0, differential DQS enabled -# bit 11: 0, required -# bit 12: 0, DDR output buffer enabled -# bit 31-13: 0 required - -DATA 0xFFD01424 0x0000F17F # DDR Controller Control High -# bit 2-0: 7, required -# bit 3: 1, MBUS Burst Chop disabled -# bit 6-4: 7, required -# bit 7: 0, reserved -# bit 8: 1, add sample stage required for f > 266 MHz -# bit 9: 0, no half clock cycle addition to dataout -# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals -# bit 11: 0, 1/4 clock cycle skew disabled for write mesh -# bit 15-12:0xf, required -# bit 31-16: 0, required - -DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low -# bit 3-0: 0, required -# bit 7-4: 2, M_ODT assertion 2 cycles after read start command -# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command -# (ODT turn off delay 2,5 clk cycles) -# bit 15-12: 4, internal ODT time based on bit 7-4 -# with the considered SDRAM internal delay -# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 -# with the considered SDRAM internal delay -# bit 31-20: 0, required - -DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High -# bit 3-0: 2, M_ODT assertion same as bit 11-8 -# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 -# bit 11-8: 4, internal ODT assertion 2 cycles after write start command -# with the considered SDRAM internal delay -# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command -# with the considered SDRAM internal delay - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -# bit 23-0: 0, reserved -# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24] - -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size -# bit 0: 1, Window enabled -# bit 1: 0, Write Protect disabled -# bit 3-2: 0, CS0 hit selected -# bit 23-4:ones, required -# bit 31-24: 0x0F, Size (i.e. 256MB) - -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) -# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 -# bit 7-4: 0, ODT0Rd, MODT[1] not asserted -# bit 11-8: 0, required -# big 15-11: 0, required -# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 -# bit 23-20: 0, ODT0Wr, MODT[1] not asserted -# bit 27-24: 0, required -# bit 31-28: 0, required - -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above -# bit 3-2: 0, ODT1 controlled by register -# bit 31-4: 0, required - -DATA 0xFFD0149C 0x0000E801 # CPU ODT Control -# bit 3-0: 1, ODTRd, Internal ODT asserted during read from DRAM bank0 -# bit 7-4: 0, ODTWr, Internal ODT not asserted during write to DRAM -# bit 9-8: 0, ODTEn, controlled by ODTRd and ODTWr -# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm -# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm -# bit 14: 1, STARTBURST ODT enabled -# bit 15: 1, Use ODT Block - -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -# bit 0: 1, enable DDR init upon this register write -# bit 31-1: 0, reserved - -# End of Header extension -DATA 0x0 0x0 diff --git a/qemu/roms/u-boot/board/keymile/km_arm/kwbimage_256M8_1.cfg b/qemu/roms/u-boot/board/keymile/km_arm/kwbimage_256M8_1.cfg deleted file mode 100644 index 393413814..000000000 --- a/qemu/roms/u-boot/board/keymile/km_arm/kwbimage_256M8_1.cfg +++ /dev/null @@ -1,259 +0,0 @@ -# -# (C) Copyright 2012 -# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com -# Norbert Mayer, Keymile AG, norbert.mayer@keymile.com -# Deepak Patel, XENTECH Limited, deepak.patel@xentech.co.uk -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# -# This configuration applies to COGE5 design (ARM-part) -# Two 8-Bit devices are connected on the 16-Bit bus on the same -# chip-select. The supported devices are -# MT47H256M8EB-3IT:C -# MT47H256M8EB-25EIT:C - -# Boot Media configurations -BOOT_FROM spi # Boot from SPI flash - -DATA 0xFFD10000 0x01112222 # MPP Control 0 Register -# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) -# bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3]) -# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) -# bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5]) -# bit 19-16: 1, MPPSel4 NF_IO[6] -# bit 23-20: 1, MPPSel5 NF_IO[7] -# bit 27-24: 1, MPPSel6 SYSRST_O -# bit 31-28: 0, MPPSel7 GPO[7] - -DATA 0xFFD10004 0x03303300 # MPP Control 1 Register -# bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged -# bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged -# bit 12-8: 3, MPPSel10 UA0_TXD -# bit 15-12: 3, MPPSel11 UA0_RXD -# bit 19-16: 0, MPPSel12 not connected -# bit 23-20: 3, MPPSel13 GPIO[14] -# bit 27-24: 3, MPPSel14 GPIO[15] -# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal) - -DATA 0xFFD10008 0x00001100 # MPP Control 2 Register -# bit 3-0: 0, MPPSel16 GPIO[16] -# bit 7-4: 0, MPPSel17 not connected -# bit 11-8: 1, MPPSel18 NF_IO[0] -# bit 15-12: 1, MPPSel19 NF_IO[1] -# bit 19-16: 0, MPPSel20 GPIO[20] -# bit 23-20: 0, MPPSel21 GPIO[21] -# bit 27-24: 0, MPPSel22 GPIO[22] -# bit 31-28: 0, MPPSel23 GPIO[23] - -# MPP Control 3-6 Register untouched (MPP24-49) - -DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register -# bit 2-0: 3, Reserved -# bit 5-3: 3, Reserved -# bit 6: 0, Reserved -# bit 7: 0, RGMII-pads voltage = 3.3V -# bit 10-8: 3, Reserved -# bit 13-11: 3, Reserved -# bit 14: 0, Reserved -# bit 15: 0, MPP RGMII-pads voltage = 3.3V -# bit 31-16 0x1B1B, Reserved - -DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register -# bit 0-1: 2, Tag RAM RTC RAM0 -# bit 3-2: 1, Tag RAM WTC RAM0 -# bit 7-4: 6, Reserved -# bit 9-8: 2, Valid RAM RTC RAM -# bit 11-10: 1, Valid RAM WTC RAM -# bit 13-12: 2, Dirty RAM RTC RAM -# bit 15-14: 1, Dirty RAM WTC RAM -# bit 17-16: 2, Data RAM RTC RAM0 -# bit 19-18: 1, Data RAM WTC RAM0 -# bit 21-20: 2, Data RAM RTC RAM1 -# bit 23-22: 1, Data RAM WTC RAM1 -# bit 25-24: 2, Data RAM RTC RAM2 -# bit 27-26: 1, Data RAM WTC RAM2 -# bit 29-28: 2, Data RAM RTC RAM3 -# bit 31-30: 1, Data RAM WTC RAM4 - -DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register -# bit 15-0: ?, Reserved -# bit 17-16: 2, ECC RAM RTC RAM0 -# bit 19-18: 1, ECC RAM WTC RAM0 -# bit 31-20: ?,Reserved - -# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! -# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage - -# SDRAM initalization -DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register -# bit 13-0: 0x4E0, DDR2 clks refresh rate -# bit 14: 0, reserved -# bit 15: 0, reserved -# bit 16: 0, CPU to Dram Write buffer policy -# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic -# bit 19-18: 0, reserved -# bit 23-20: 0, reserved -# bit 24: 1, enable exit self refresh mode on DDR access -# bit 25: 1, required -# bit 29-26: 0, reserved -# bit 31-30: 1, reserved - -DATA 0xFFD01404 0x36543000 # DDR Controller Control Low -# bit 3-0: 0, reserved -# bit 4: 0, 2T mode =addr/cmd in same cycle -# bit 5: 0, clk is driven during self refresh, we don't care for APX -# bit 6: 0, use recommended falling edge of clk for addr/cmd -# bit 7-11: 0, reserved -# bit 12-13: 1, reserved, required 1 -# bit 14: 0, input buffer always powered up -# bit 17-15: 0, reserved -# bit 18: 1, cpu lock transaction enabled -# bit 19: 0, reserved -# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 -# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM -# bit 30-28: 3, required -# bit 31: 0, no additional STARTBURST delay - -DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1) -# bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles -# bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles -# bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles -# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles -# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles -# bit 20: 0, extended TRAS msb -# bit 23-21: 0, reserved -# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles -# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles - -DATA 0xFFD0140C 0x0000003E # DDR Timing (High) -# bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles -# bit 8-7: 0, TR2R -# bit 10-9: 0, TR2W -# bit 12-11: 0, TW2W -# bit 31-13: 0, reserved - -DATA 0xFFD01410 0x00000000 # DDR Address Control -# bit 1-0: 0, Cs0width=x8 (2 devices) -# bit 3-2: 0, Cs0size=2Gb -# bit 5-4: 0, Cs1width=nonexistent -# bit 7-6: 0, Cs1size =nonexistent -# bit 9-8: 0, Cs2width=nonexistent -# bit 11-10: 0, Cs2size =nonexistent -# bit 13-12: 0, Cs3width=nonexistent -# bit 15-14: 0, Cs3size =nonexistent -# bit 16: 0, Cs0AddrSel -# bit 17: 0, Cs1AddrSel -# bit 18: 0, Cs2AddrSel -# bit 19: 0, Cs3AddrSel -# bit 31-20: 0, required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit 0: 0, OpenPage enabled -# bit 31-1: 0, required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit 3-0: 0, DDR cmd -# bit 31-4: 0, required - -DATA 0xFFD0141C 0x00000652 # DDR Mode -# bit 2-0: 2, Burst Length = 4 -# bit 3: 0, Burst Type -# bit 6-4: 5, CAS Latency = 5 -# bit 7: 0, Test mode -# bit 8: 0, DLL Reset -# bit 11-9: 3, Write recovery for auto-precharge must be 3 -# bit 12: 0, Active power down exit time, fast exit -# bit 14-13: 0, reserved -# bit 31-15: 0, reserved - -DATA 0xFFD01420 0x00000006 # DDR Extended Mode -# bit 0: 0, DDR DLL enabled -# bit 1: 1, DDR drive strenght reduced -# bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0] -# bit 5-3: 0, required -# bit 6: 0, DDR ODT control msb, 75ohm termination [RTT1] -# bit 9-7: 0, required -# bit 10: 0, differential DQS enabled -# bit 11: 0, required -# bit 12: 0, DDR output buffer enabled -# bit 31-13: 0 required - -DATA 0xFFD01424 0x0000F17F # DDR Controller Control High -# bit 2-0: 7, required -# bit 3: 1, MBUS Burst Chop disabled -# bit 6-4: 7, required -# bit 7: 0, reserved -# bit 8: 1, add sample stage required for > 266Mhz -# bit 9: 0, no half clock cycle addition to dataout -# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals -# bit 11: 0, 1/4 clock cycle skew disabled for write mesh -# bit 15-12:0xf, required -# bit 31-16: 0, required - -DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low -# bit 3-0: 0, required -# bit 7-4: 2, M_ODT assertion 2 cycles after read start command -# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command -# (ODT turn off delay 2,5 clk cycles) -# bit 15-12: 4, internal ODT time based on bit 7-4 -# with the considered SDRAM internal delay -# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 -# with the considered SDRAM internal delay -# bit 31-20: 0, required - -DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High -# bit 3-0: 2, M_ODT assertion same as bit 11-8 -# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 -# bit 11-8: 4, internal ODT assertion 2 cycles after write start command -# with the considered SDRAM internal delay -# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command -# with the considered SDRAM internal delay - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -# bit 23-0: 0, reserved -# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24] - -DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size -# bit 0: 1, Window enabled -# bit 1: 0, Write Protect disabled -# bit 3-2: 0, CS0 hit selected -# bit 23-4:ones, required -# bit 31-24:0x1F, Size (i.e. 512MB) - -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) -# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 -# bit 7-4: 0, ODT0Rd, MODT[1] not asserted -# bit 11-8: 0, required -# big 15-11: 0, required -# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 -# bit 23-20: 0, ODT0Wr, MODT[1] not asserted -# bit 27-24: 0, required -# bit 31-28: 0, required - -DATA 0xFFD01498 0x00000004 # DDR ODT Control (High) -# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above -# bit 3-2: 1, ODT1 never active -# bit 31-4: 0, required - -DATA 0xFFD0149C 0x0000E801 # CPU ODT Control -# bit 3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 -# bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0 -# bit 9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr -# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm -# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm -# bit 14: 1, STARTBURST ODT enabled -# bit 15: 1, Use ODT Block - -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -# bit 0: 1, enable DDR init upon this register write -# bit 31-1: 0, reserved - -# End of Header extension -DATA 0x0 0x0 diff --git a/qemu/roms/u-boot/board/keymile/kmp204x/Makefile b/qemu/roms/u-boot/board/keymile/kmp204x/Makefile deleted file mode 100644 index c57ca08e1..000000000 --- a/qemu/roms/u-boot/board/keymile/kmp204x/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2001-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := kmp204x.o ddr.o eth.o tlb.o pci.o law.o qrio.o \ - ../common/common.o ../common/ivm.o diff --git a/qemu/roms/u-boot/board/keymile/kmp204x/ddr.c b/qemu/roms/u-boot/board/keymile/kmp204x/ddr.c deleted file mode 100644 index 34ac6979b..000000000 --- a/qemu/roms/u-boot/board/keymile/kmp204x/ddr.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * (C) Copyright 2013 Keymile AG - * Valentin Longchamp <valentin.longchamp@keymile.com> - * - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <i2c.h> -#include <hwconfig.h> -#include <asm/mmu.h> -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - if (ctrl_num) { - printf("Wrong parameter for controller number %d", ctrl_num); - return; - } - - /* automatic calibration for nb of cycles between read and DQS pre */ - popts->cpo_override = 0xFF; - - /* 1/2 clk delay between wr command and data strobe */ - popts->write_data_delay = 4; - /* clk lauched 1/2 applied cylcle after address command */ - popts->clk_adjust = 4; - /* 1T timing: command/address held for only 1 cycle */ - popts->twot_en = 0; - - /* we have only one module, half str should be OK */ - popts->half_strength_driver_enable = 1; - - /* wrlvl values overriden as recommended by ddr init func */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - popts->wrlvl_start = 0x6; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* DHC_EN =1, ODT = 75 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm; -} - -phys_size_t initdram(int board_type) -{ - phys_size_t dram_size = 0; - - puts("Initializing with SPD\n"); - - dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - debug(" DDR: "); - return dram_size; -} diff --git a/qemu/roms/u-boot/board/keymile/kmp204x/eth.c b/qemu/roms/u-boot/board/keymile/kmp204x/eth.c deleted file mode 100644 index a0731055a..000000000 --- a/qemu/roms/u-boot/board/keymile/kmp204x/eth.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * (C) Copyright 2013 Keymile AG - * Valentin Longchamp <valentin.longchamp@keymile.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <phy.h> - -int board_eth_init(bd_t *bis) -{ - int ret = 0; -#ifdef CONFIG_FMAN_ENET - struct fsl_pq_mdio_info dtsec_mdio_info; - - printf("Initializing Fman\n"); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - /* DTESC1/2 don't have a PHY, they are temporarily disabled - * so that u-boot doesn't try to unsuccessfuly enable them */ - fm_disable_port(FM1_DTSEC1); - fm_disable_port(FM1_DTSEC2); - - /* - * Program RGMII DTSEC5 (FM1 MAC5) on the EC2 physical itf - * This is the debug interface, the only one used in u-boot - */ - fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); - fm_info_set_mdio(FM1_DTSEC5, - miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); - - ret = cpu_eth_init(bis); - - /* reenable DTSEC1/2 for later (kernel) */ - fm_enable_port(FM1_DTSEC1); - fm_enable_port(FM1_DTSEC2); -#endif - - return ret; -} - -#if defined(CONFIG_PHYLIB) && defined(CONFIG_PHY_MARVELL) - -#define mv88E1118_PAGE_REG 22 - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->addr == CONFIG_SYS_FM1_DTSEC5_PHY_ADDR) { - /* driver config is good */ - if (phydev->drv->config) - phydev->drv->config(phydev); - - /* but we still need to fix the LEDs */ - phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0003); - phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x0840); - phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0000); - } - - return 0; -} -#endif diff --git a/qemu/roms/u-boot/board/keymile/kmp204x/kmp204x.c b/qemu/roms/u-boot/board/keymile/kmp204x/kmp204x.c deleted file mode 100644 index 6bc8eb85e..000000000 --- a/qemu/roms/u-boot/board/keymile/kmp204x/kmp204x.c +++ /dev/null @@ -1,287 +0,0 @@ -/* - * (C) Copyright 2013 Keymile AG - * Valentin Longchamp <valentin.longchamp@keymile.com> - * - * Copyright 2011,2012 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <netdev.h> -#include <linux/compiler.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> -#include <fm_eth.h> - -#include "../common/common.h" -#include "kmp204x.h" - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - printf("Board: Keymile %s\n", CONFIG_KM_BOARD_NAME); - - return 0; -} - -/* I2C deblocking uses the algorithm defined in board/keymile/common/common.c - * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines - * For I2C only the low state is activly driven and high state is pulled-up - * by a resistor. Therefore the deblock GPIOs are used - * -> as an active output to drive a low state - * -> as an open-drain input to have a pulled-up high state - */ - -/* QRIO GPIOs used for deblocking */ -#define DEBLOCK_PORT1 GPIO_A -#define DEBLOCK_SCL1 20 -#define DEBLOCK_SDA1 21 - -/* By default deblock GPIOs are floating */ -static void i2c_deblock_gpio_cfg(void) -{ - /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */ - qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1); - qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1); - - qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0); - qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0); -} - -void set_sda(int state) -{ - qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state); -} - -void set_scl(int state) -{ - qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state); -} - -int get_sda(void) -{ - return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1); -} - -int get_scl(void) -{ - return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1); -} - - -#define ZL30158_RST 8 -#define BFTIC4_RST 0 - -int board_early_init_f(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */ - setbits_be32(&gur->ddrclkdr, 0x001f000f); - - /* set the BFTIC's prstcfg to reset at power-up and unit reset only */ - qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST); - /* and enable WD on it */ - qrio_wdmask(BFTIC4_RST, true); - - /* set the ZL30138's prstcfg to reset at power-up and unit reset only */ - qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_UNIT_RST); - /* and take it out of reset as soon as possible (needed for Hooper) */ - qrio_prst(ZL30158_RST, false, false); - - return 0; -} - -int board_early_init_r(void) -{ - int ret = 0; - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - set_liodns(); - setup_portals(); - - ret = trigger_fpga_config(); - if (ret) - printf("error triggering PCIe FPGA config\n"); - - /* enable the Unit LED (red) & Boot LED (on) */ - qrio_set_leds(); - - /* enable Application Buffer */ - qrio_enable_app_buffer(); - - return ret; -} - -unsigned long get_board_sys_clk(unsigned long dummy) -{ - return 66666666; -} - -#define ETH_FRONT_PHY_RST 15 -#define QSFP2_RST 11 -#define QSFP1_RST 10 -#define ZL30343_RST 9 - -int misc_init_f(void) -{ - /* configure QRIO pis for i2c deblocking */ - i2c_deblock_gpio_cfg(); - - /* configure the front phy's prstcfg and take it out of reset */ - qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST); - qrio_prst(ETH_FRONT_PHY_RST, false, false); - - /* set the ZL30343 prstcfg to reset at power-up and unit reset only */ - qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_UNIT_RST); - /* and enable the WD on it */ - qrio_wdmask(ZL30343_RST, true); - - /* set the QSFPs' prstcfg to reset at power-up and unit rst only */ - qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST); - qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST); - - /* and enable the WD on them */ - qrio_wdmask(QSFP1_RST, true); - qrio_wdmask(QSFP2_RST, true); - - return 0; -} - -#define NUM_SRDS_BANKS 2 - -int misc_init_r(void) -{ - serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; - u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100, - SRDS_PLLCR0_RFCK_SEL_125}; - unsigned int i; - - /* check SERDES reference clocks */ - for (i = 0; i < NUM_SRDS_BANKS; i++) { - u32 actual = in_be32(®s->bank[i].pllcr0); - actual &= SRDS_PLLCR0_RFCK_SEL_MASK; - if (actual != expected[i]) { - printf("Warning: SERDES bank %u expects reference \ - clock %sMHz, but actual is %sMHz\n", i + 1, - serdes_clock_to_string(expected[i]), - serdes_clock_to_string(actual)); - } - } - - return 0; -} - -#if defined(CONFIG_HUSH_INIT_VAR) -int hush_init_var(void) -{ - ivm_read_eeprom(); - return 0; -} -#endif - -#if defined(CONFIG_LAST_STAGE_INIT) - -int last_stage_init(void) -{ -#if defined(CONFIG_KMCOGE4) - /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */ - struct bfticu_iomap *bftic4 = - (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE; - u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK; - - if (dip_switch != 0) { - /* start bootloader */ - puts("DIP: Enabled\n"); - setenv("actual_bank", "0"); - } -#endif - set_km_env(); - - return 0; -} -#endif - -#ifdef CONFIG_SYS_DPAA_FMAN -void fdt_fixup_fman_mac_addresses(void *blob) -{ - int node, i, ret; - char *tmp, *end; - unsigned char mac_addr[6]; - - /* get the mac addr from env */ - tmp = getenv("ethaddr"); - if (!tmp) { - printf("ethaddr env variable not defined\n"); - return; - } - for (i = 0; i < 6; i++) { - mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; - if (tmp) - tmp = (*end) ? end+1 : end; - } - - /* find the correct fdt ethernet path and correct it */ - node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000"); - if (node < 0) { - printf("no /soc/fman/ethernet path offset\n"); - return; - } - ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6); - if (ret) { - printf("error setting local-mac-address property\n"); - return; - } -} -#endif - -void ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = getenv_bootm_low(); - size = getenv_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) - fdt_fixup_dr_usb(blob, bd); -#endif - -#ifdef CONFIG_PCI - pci_of_setup(blob, bd); -#endif - - fdt_fixup_liodn(blob); -#ifdef CONFIG_SYS_DPAA_FMAN - fdt_fixup_fman_ethernet(blob); - fdt_fixup_fman_mac_addresses(blob); -#endif -} - -#if defined(CONFIG_POST) - -/* DIC26_SELFTEST GPIO used to start factory test sw */ -#define SELFTEST_PORT GPIO_A -#define SELFTEST_PIN 31 - -int post_hotkeys_pressed(void) -{ - qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN); - return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN); -} -#endif diff --git a/qemu/roms/u-boot/board/keymile/kmp204x/kmp204x.h b/qemu/roms/u-boot/board/keymile/kmp204x/kmp204x.h deleted file mode 100644 index afede994f..000000000 --- a/qemu/roms/u-boot/board/keymile/kmp204x/kmp204x.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2013 Keymile AG - * Valentin Longchamp <valentin.longchamp@keymile.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* QRIO GPIO ports */ -#define GPIO_A 0x40 -#define GPIO_B 0x60 - -int qrio_get_gpio(u8 port_off, u8 gpio_nr); -void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val); -void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value); -void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value); -void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr); - -#define PRSTCFG_POWUP_UNIT_CORE_RST 0x0 -#define PRSTCFG_POWUP_UNIT_RST 0x1 -#define PRSTCFG_POWUP_RST 0x3 - -void qrio_prst(u8 bit, bool en, bool wden); -void qrio_wdmask(u8 bit, bool wden); -void qrio_prstcfg(u8 bit, u8 mode); -void qrio_set_leds(void); -void qrio_enable_app_buffer(void); - -void pci_of_setup(void *blob, bd_t *bd); diff --git a/qemu/roms/u-boot/board/keymile/kmp204x/law.c b/qemu/roms/u-boot/board/keymile/kmp204x/law.c deleted file mode 100644 index 75d69e8b4..000000000 --- a/qemu/roms/u-boot/board/keymile/kmp204x/law.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2013 Keymile AG - * Valentin Longchamp <valentin.longchamp@keymile.com> - * - * Copyright 2008-2011 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -struct law_entry law_table[] = { -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), -#endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), -#endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), -#endif -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), -#endif - SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS - SET_LAW(CONFIG_SYS_LBAPP1_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -#endif -#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS - SET_LAW(CONFIG_SYS_LBAPP2_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/qemu/roms/u-boot/board/keymile/kmp204x/pbi.cfg b/qemu/roms/u-boot/board/keymile/kmp204x/pbi.cfg deleted file mode 100644 index 1e0a171d8..000000000 --- a/qemu/roms/u-boot/board/keymile/kmp204x/pbi.cfg +++ /dev/null @@ -1,76 +0,0 @@ -# -# Copyright 2012 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer docs/README.pblimage for more details about how-to configure -# and create PBL boot image -# - -#PBI commands -#Configure ALTCBAR for DCSR -> DCSR@89000000 -091380c0 000009C4 -09000010 00000000 -091380c0 000009C4 -09000014 00000000 -091380c0 000009C4 -09000018 81d00000 -#Workaround for A-004849 -091380c0 000009C4 -890B0050 00000002 -091380c0 000009C4 -890B0054 00000002 -091380c0 000009C4 -890B0058 00000002 -091380c0 000009C4 -890B005C 00000002 -091380c0 000009C4 -890B0090 00000002 -091380c0 000009C4 -890B0094 00000002 -091380c0 000009C4 -890B0098 00000002 -091380c0 000009C4 -890B009C 00000002 -091380c0 000009C4 -890B0108 00000012 -091380c0 000009C4 -#Workaround for A-006559 needed for rev 2.0 of P2041 silicon -89021008 0000f000 -091380c0 000009C4 -89021028 0000f000 -091380c0 000009C4 -89021048 0000f000 -091380c0 000009C4 -89021068 0000f000 -091380c0 000009C4 -#Flush PBL data -09138000 00000000 -#Disable ALTCBAR -09000018 00000000 -091380c0 000009C4 -#Initialize CPC1 as 1MB SRAM -09010000 00200400 -09138000 00000000 -091380c0 00000100 -09010100 00000000 -09010104 fff0000b -09010f00 08000000 -09010000 80000000 -#Configure LAW for CPC1 -09000d00 00000000 -09000d04 fff00000 -09000d08 81000013 -09000010 00000000 -09000014 ff000000 -09000018 81000000 -#Initialize eSPI controller, default configuration is slow for eSPI to -#load data, this configuration comes from u-boot eSPI driver. -09110000 80000403 -09110020 27170008 -09110024 00100008 -09110028 00100008 -0911002c 00100008 -#Flush PBL data -09138000 00000000 -091380c0 00000000 diff --git a/qemu/roms/u-boot/board/keymile/kmp204x/pci.c b/qemu/roms/u-boot/board/keymile/kmp204x/pci.c deleted file mode 100644 index 2b0b054a1..000000000 --- a/qemu/roms/u-boot/board/keymile/kmp204x/pci.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * (C) Copyright 2013 Keymile AG - * Valentin Longchamp <valentin.longchamp@keymile.com> - * - * Copyright 2007-2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <pci.h> -#include <asm/fsl_pci.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <asm/fsl_serdes.h> -#include <asm/errno.h> - -#include "kmp204x.h" - -#define PROM_SEL_L 11 -/* control the PROM_SEL_L signal*/ -static void toggle_fpga_eeprom_bus(bool cpu_own) -{ - qrio_gpio_direction_output(GPIO_A, PROM_SEL_L, !cpu_own); -} - -#define CONF_SEL_L 10 -#define FPGA_PROG_L 19 -#define FPGA_DONE 18 -#define FPGA_INIT_L 17 - -int trigger_fpga_config(void) -{ - int ret = 0, init_l; - /* approx 10ms */ - u32 timeout = 10000; - - /* make sure the FPGA_can access the EEPROM */ - toggle_fpga_eeprom_bus(false); - - /* assert CONF_SEL_L to be able to drive FPGA_PROG_L */ - qrio_gpio_direction_output(GPIO_A, CONF_SEL_L, 0); - - /* trigger the config start */ - qrio_gpio_direction_output(GPIO_A, FPGA_PROG_L, 0); - - /* small delay for INIT_L line */ - udelay(10); - - /* wait for FPGA_INIT to be asserted */ - do { - init_l = qrio_get_gpio(GPIO_A, FPGA_INIT_L); - if (timeout-- == 0) { - printf("FPGA_INIT timeout\n"); - ret = -EFAULT; - break; - } - udelay(10); - } while (init_l); - - /* deassert FPGA_PROG, config should start */ - qrio_set_gpio(GPIO_A, FPGA_PROG_L, 1); - - return ret; -} - -/* poll the FPGA_DONE signal and give the EEPROM back to the QorIQ */ -static int wait_for_fpga_config(void) -{ - int ret = 0, done; - /* approx 5 s */ - u32 timeout = 500000; - - printf("PCIe FPGA config:"); - do { - done = qrio_get_gpio(GPIO_A, FPGA_DONE); - if (timeout-- == 0) { - printf(" FPGA_DONE timeout\n"); - ret = -EFAULT; - goto err_out; - } - udelay(10); - } while (!done); - - printf(" done\n"); - -err_out: - /* deactive CONF_SEL and give the CPU conf EEPROM access */ - qrio_set_gpio(GPIO_A, CONF_SEL_L, 1); - toggle_fpga_eeprom_bus(true); - - return ret; -} - -#define PCIE_SW_RST 14 -#define PEXHC_RST 13 -#define HOOPER_RST 12 - -void pci_init_board(void) -{ - qrio_prstcfg(PCIE_SW_RST, PRSTCFG_POWUP_UNIT_CORE_RST); - qrio_prstcfg(PEXHC_RST, PRSTCFG_POWUP_UNIT_CORE_RST); - qrio_prstcfg(HOOPER_RST, PRSTCFG_POWUP_UNIT_CORE_RST); - - /* wait for the PCIe FPGA to be configured - * it has been triggered earlier in board_early_init_r */ - if (wait_for_fpga_config()) - printf("error finishing PCIe FPGA config\n"); - - qrio_prst(PCIE_SW_RST, false, false); - qrio_prst(PEXHC_RST, false, false); - qrio_prst(HOOPER_RST, false, false); - /* Hooper is not direcly PCIe capable */ - mdelay(50); - - fsl_pcie_init_board(0); -} - -void pci_of_setup(void *blob, bd_t *bd) -{ - FT_FSL_PCI_SETUP; -} diff --git a/qemu/roms/u-boot/board/keymile/kmp204x/qrio.c b/qemu/roms/u-boot/board/keymile/kmp204x/qrio.c deleted file mode 100644 index b6ba93ada..000000000 --- a/qemu/roms/u-boot/board/keymile/kmp204x/qrio.c +++ /dev/null @@ -1,175 +0,0 @@ -/* - * (C) Copyright 2013 Keymile AG - * Valentin Longchamp <valentin.longchamp@keymile.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#include "../common/common.h" -#include "kmp204x.h" - -/* QRIO GPIO register offsets */ -#define DIRECT_OFF 0x18 -#define GPRT_OFF 0x1c - -int qrio_get_gpio(u8 port_off, u8 gpio_nr) -{ - u32 gprt; - - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - gprt = in_be32(qrio_base + port_off + GPRT_OFF); - - return (gprt >> gpio_nr) & 1U; -} - -void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value) -{ - u32 gprt, mask; - - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - mask = 1U << gpio_nr; - - gprt = in_be32(qrio_base + port_off + GPRT_OFF); - if (value) - gprt |= mask; - else - gprt &= ~mask; - - out_be32(qrio_base + port_off + GPRT_OFF, gprt); -} - -void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value) -{ - u32 direct, mask; - - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - mask = 1U << gpio_nr; - - direct = in_be32(qrio_base + port_off + DIRECT_OFF); - direct |= mask; - out_be32(qrio_base + port_off + DIRECT_OFF, direct); - - qrio_set_gpio(port_off, gpio_nr, value); -} - -void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr) -{ - u32 direct, mask; - - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - mask = 1U << gpio_nr; - - direct = in_be32(qrio_base + port_off + DIRECT_OFF); - direct &= ~mask; - out_be32(qrio_base + port_off + DIRECT_OFF, direct); -} - -void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val) -{ - u32 direct, mask; - - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - mask = 1U << gpio_nr; - - direct = in_be32(qrio_base + port_off + DIRECT_OFF); - if (val == 0) - /* set to output -> GPIO drives low */ - direct |= mask; - else - /* set to input -> GPIO floating */ - direct &= ~mask; - - out_be32(qrio_base + port_off + DIRECT_OFF, direct); -} - -#define WDMASK_OFF 0x16 - -void qrio_wdmask(u8 bit, bool wden) -{ - u16 wdmask; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - wdmask = in_be16(qrio_base + WDMASK_OFF); - - if (wden) - wdmask |= (1 << bit); - else - wdmask &= ~(1 << bit); - - out_be16(qrio_base + WDMASK_OFF, wdmask); -} - -#define PRST_OFF 0x1a - -void qrio_prst(u8 bit, bool en, bool wden) -{ - u16 prst; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - qrio_wdmask(bit, wden); - - prst = in_be16(qrio_base + PRST_OFF); - - if (en) - prst &= ~(1 << bit); - else - prst |= (1 << bit); - - out_be16(qrio_base + PRST_OFF, prst); -} - -#define PRSTCFG_OFF 0x1c - -void qrio_prstcfg(u8 bit, u8 mode) -{ - u32 prstcfg; - u8 i; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - prstcfg = in_be32(qrio_base + PRSTCFG_OFF); - - for (i = 0; i < 2; i++) { - if (mode & (1<<i)) - set_bit(2*bit+i, &prstcfg); - else - clear_bit(2*bit+i, &prstcfg); - } - - out_be32(qrio_base + PRSTCFG_OFF, prstcfg); -} - -#define CTRLH_OFF 0x02 -#define CTRLH_WRL_BOOT 0x01 -#define CTRLH_WRL_UNITRUN 0x02 - -void qrio_set_leds(void) -{ - u8 ctrlh; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - /* set UNIT LED to RED and BOOT LED to ON */ - ctrlh = in_8(qrio_base + CTRLH_OFF); - ctrlh |= (CTRLH_WRL_BOOT | CTRLH_WRL_UNITRUN); - out_8(qrio_base + CTRLH_OFF, ctrlh); -} - -#define CTRLL_OFF 0x03 -#define CTRLL_WRB_BUFENA 0x20 - -void qrio_enable_app_buffer(void) -{ - u8 ctrll; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - - /* enable application buffer */ - ctrll = in_8(qrio_base + CTRLL_OFF); - ctrll |= (CTRLL_WRB_BUFENA); - out_8(qrio_base + CTRLL_OFF, ctrll); -} diff --git a/qemu/roms/u-boot/board/keymile/kmp204x/rcw_kmp204x.cfg b/qemu/roms/u-boot/board/keymile/kmp204x/rcw_kmp204x.cfg deleted file mode 100644 index 236d5138b..000000000 --- a/qemu/roms/u-boot/board/keymile/kmp204x/rcw_kmp204x.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# -# Default RCW for kmp204x boards -# - -#PBL preamble and RCW header -aa55aa55 010e0100 -#64 bytes RCW data -14600000 00000000 28200000 00000000 -148E70CF CFC02000 58000000 41000000 -00000000 00000000 00000000 F0428816 -00000000 00000000 00000000 00000000 diff --git a/qemu/roms/u-boot/board/keymile/kmp204x/tlb.c b/qemu/roms/u-boot/board/keymile/kmp204x/tlb.c deleted file mode 100644 index d03ca802a..000000000 --- a/qemu/roms/u-boot/board/keymile/kmp204x/tlb.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * (C) Copyright 2013 Keymile AG - * Valentin Longchamp <valentin.longchamp@keymile.com> - * - * Copyright 2008-2011 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - /* TLB 1 */ - /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the - * SRAM is at 0xfff00000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_16M, 1), - /* QRIO */ - SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_64K, 1), - /* *I*G* - PCI1 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_512M, 1), - /* *I*G* - PCI3 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_512M, 1), - /* *I*G* - PCI1&3 I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_128K, 1), -#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS - /* LBAPP1 */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP1_BASE, CONFIG_SYS_LBAPP1_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256M, 1), -#endif -#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS - /* LBAPP2 */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP2_BASE, CONFIG_SYS_LBAPP2_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_256M, 1), -#endif - /* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, - MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_1M, 1), -#endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, - MAS3_SW|MAS3_SR, 0, - 0, 11, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 12, BOOKE_PAGESZ_1M, 1), -#endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 13, BOOKE_PAGESZ_4M, 1), -#endif -#ifdef CONFIG_SYS_NAND_BASE - /* - * *I*G - NAND - * entry 14 and 15 has been used hard coded, they will be disabled - * in cpu_init_f, so we use entry 16 for nand. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 16, BOOKE_PAGESZ_32K, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/qemu/roms/u-boot/board/keymile/scripts/README b/qemu/roms/u-boot/board/keymile/scripts/README deleted file mode 100644 index dd935b2c6..000000000 --- a/qemu/roms/u-boot/board/keymile/scripts/README +++ /dev/null @@ -1,31 +0,0 @@ -These scripts are needed for our development usecases. Copy this directory -into your tftp root directory to be able to use this scripts. -cp -r <u-boot-repo>/board/keymile/scripts <your_tftp_root>/ - -To load and configure these usecase, two environment variables in the u-boot -default environment must be parsed: -run develop : setup environment to configure for rootfs via nfs -run ramfs : setup environment to configure for rootfs in ram - -Last change: 24.11.2011 - -develop-common.txt -============================ -This file defines variables for working with rootfs via nfs for powerpc and -arm. - -develop-<arch>.txt -============================ -This file defines architecture specific variables for working with rootfs via -nfs arm. - - -ramfs-common.txt -============================ -This file defines variables for working with rootfs inside the ram for powerpc -and arm. - -ramfs-<arch>.txt -============================ -This file defines architecture specific variables for working with rootfs inside -ram. diff --git a/qemu/roms/u-boot/board/keymile/scripts/develop-arm.txt b/qemu/roms/u-boot/board/keymile/scripts/develop-arm.txt deleted file mode 100644 index d3c974f1f..000000000 --- a/qemu/roms/u-boot/board/keymile/scripts/develop-arm.txt +++ /dev/null @@ -1 +0,0 @@ -setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure diff --git a/qemu/roms/u-boot/board/keymile/scripts/develop-common.txt b/qemu/roms/u-boot/board/keymile/scripts/develop-common.txt deleted file mode 100644 index a80812a5d..000000000 --- a/qemu/roms/u-boot/board/keymile/scripts/develop-common.txt +++ /dev/null @@ -1,10 +0,0 @@ -altbootcmd=run ${subbootcmds} -bootcmd=run ${subbootcmds} -configure=run set_uimage; km_setboardid && saveenv && reset -subbootcmds=tftpfdt tftpkernel nfsargs add_default boot -nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${toolchain}/${arch} -tftpfdt=if run set_fdthigh || test ${arch} != arm; then tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb; else true; fi -tftpkernel=tftpboot ${load_addr_r} ${hostname}/${uimage} -toolchain=/opt/eldk -rootfssize=0 -set_uimage=printenv uimage || setenv uimage uImage diff --git a/qemu/roms/u-boot/board/keymile/scripts/develop-ppc_82xx.txt b/qemu/roms/u-boot/board/keymile/scripts/develop-ppc_82xx.txt deleted file mode 100644 index d3c974f1f..000000000 --- a/qemu/roms/u-boot/board/keymile/scripts/develop-ppc_82xx.txt +++ /dev/null @@ -1 +0,0 @@ -setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure diff --git a/qemu/roms/u-boot/board/keymile/scripts/develop-ppc_8xx.txt b/qemu/roms/u-boot/board/keymile/scripts/develop-ppc_8xx.txt deleted file mode 100644 index d3c974f1f..000000000 --- a/qemu/roms/u-boot/board/keymile/scripts/develop-ppc_8xx.txt +++ /dev/null @@ -1 +0,0 @@ -setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure diff --git a/qemu/roms/u-boot/board/keymile/scripts/ramfs-arm.txt b/qemu/roms/u-boot/board/keymile/scripts/ramfs-arm.txt deleted file mode 100644 index 87e984e17..000000000 --- a/qemu/roms/u-boot/board/keymile/scripts/ramfs-arm.txt +++ /dev/null @@ -1 +0,0 @@ -setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure diff --git a/qemu/roms/u-boot/board/keymile/scripts/ramfs-common.txt b/qemu/roms/u-boot/board/keymile/scripts/ramfs-common.txt deleted file mode 100644 index d79ad2e21..000000000 --- a/qemu/roms/u-boot/board/keymile/scripts/ramfs-common.txt +++ /dev/null @@ -1,13 +0,0 @@ -addramfs=setenv bootargs "${bootargs} phram.phram=rootfs${boot_bank},${rootfsaddr},${rootfssize}" -boot_bank=-1 -altbootcmd=run ${subbootcmds} -bootcmd=run ${subbootcmds} -subbootcmds=tftpfdt tftpkernel setrootfsaddr tftpramfs flashargs add_default addpanic addramfs boot -nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} -configure=run set_uimage; km_setboardid && saveenv && reset -rootfsfile=${hostname}/rootfsImage -setrootfsaddr=setexpr value ${pnvramaddr} - ${rootfssize} && setenv rootfsaddr 0x${value} -tftpfdt=if run set_fdthigh || test ${arch} != arm; then tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb; else true; fi -tftpkernel=tftpboot ${load_addr_r} ${hostname}/${uimage} -tftpramfs=tftpboot ${rootfsaddr} ${hostname}/rootfsImage -set_uimage=printenv uimage || setenv uimage uImage diff --git a/qemu/roms/u-boot/board/keymile/scripts/ramfs-ppc_82xx.txt b/qemu/roms/u-boot/board/keymile/scripts/ramfs-ppc_82xx.txt deleted file mode 100644 index 87e984e17..000000000 --- a/qemu/roms/u-boot/board/keymile/scripts/ramfs-ppc_82xx.txt +++ /dev/null @@ -1 +0,0 @@ -setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure diff --git a/qemu/roms/u-boot/board/keymile/scripts/ramfs-ppc_8xx.txt b/qemu/roms/u-boot/board/keymile/scripts/ramfs-ppc_8xx.txt deleted file mode 100644 index 87e984e17..000000000 --- a/qemu/roms/u-boot/board/keymile/scripts/ramfs-ppc_8xx.txt +++ /dev/null @@ -1 +0,0 @@ -setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure |