diff options
Diffstat (limited to 'qemu/roms/u-boot/board/freescale/t208xrdb')
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/t208xrdb/Makefile | 18 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/t208xrdb/README | 264 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/t208xrdb/cpld.c | 71 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/t208xrdb/cpld.h | 42 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/t208xrdb/ddr.c | 114 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/t208xrdb/ddr.h | 47 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/t208xrdb/eth_t208xrdb.c | 106 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/t208xrdb/law.c | 34 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/t208xrdb/pci.c | 23 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/t208xrdb/spl.c | 107 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/t208xrdb/t2080_pbi.cfg | 41 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/t208xrdb/t2080_rcw.cfg | 8 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/t208xrdb/t208xrdb.c | 124 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/t208xrdb/t208xrdb.h | 13 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/t208xrdb/tlb.c | 153 |
15 files changed, 0 insertions, 1165 deletions
diff --git a/qemu/roms/u-boot/board/freescale/t208xrdb/Makefile b/qemu/roms/u-boot/board/freescale/t208xrdb/Makefile deleted file mode 100644 index 9605f8b60..000000000 --- a/qemu/roms/u-boot/board/freescale/t208xrdb/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright 2014 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -obj-y += spl.o -else -obj-$(CONFIG_T2080RDB) += t208xrdb.o -obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o -obj-$(CONFIG_T2080RDB) += cpld.o -obj-$(CONFIG_PCI) += pci.o -endif - -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/qemu/roms/u-boot/board/freescale/t208xrdb/README b/qemu/roms/u-boot/board/freescale/t208xrdb/README deleted file mode 100644 index 24484cd0f..000000000 --- a/qemu/roms/u-boot/board/freescale/t208xrdb/README +++ /dev/null @@ -1,264 +0,0 @@ -T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC. -It can work in two mode: standalone mode and PCIe endpoint mode. - -T2080 SoC Overview ------------------- -The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power -Architecture processor cores with high-performance datapath acceleration -logic and network and peripheral bus interfaces required for networking, -telecom/datacom, wireless infrastructure, and mil/aerospace applications. - -T2080 includes the following functions and features: - - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - - Hierarchical interconnect fabric - - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - - Data Path Acceleration Architecture (DPAA) incorporating acceleration - - 16 SerDes lanes up to 10.3125 GHz - - 8 Ethernet interfaces, supporting combinations of the following: - - Up to four 10 Gbps Ethernet MACs - - Up to eight 1 Gbps Ethernet MACs - - Up to four 2.5 Gbps Ethernet MACs - - High-speed peripheral interfaces - - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - - Additional peripheral interfaces - - Two serial ATA (SATA 2.0) controllers - - Two high-speed USB 2.0 controllers with integrated PHY - - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - - Enhanced serial peripheral interface (eSPI) - - Four I2C controllers - - Four 2-pin UARTs or two 4-pin UARTs - - Integrated Flash Controller supporting NAND and NOR flash - - Three eight-channel DMA engines - - Support for hardware virtualization and partitioning enforcement - - QorIQ Platform's Trust Architecture 2.0 - -Differences between T2080 and T2081 ------------------------------------ - Feature T2080 T2081 - 1G Ethernet numbers: 8 6 - 10G Ethernet numbers: 4 2 - SerDes lanes: 16 8 - Serial RapidIO,RMan: 2 no - SATA Controller: 2 no - Aurora: yes no - SoC Package: 896-pins 780-pins - - -T2080PCIe-RDB board Overview ----------------------------- - - SERDES Configuration - - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10) - - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) - - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3) - - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2) - - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2) - - SerDes-2 Lane G-H: to SATA1 & SATA2 - - Ethernet - - Two on-board 10M/100M/1G RGMII ethernet ports - - Two on-board 10Gbps XFI fiber ports - - Two on-board 10Gbps Base-T copper ports - - DDR Memory - - Supports 72bit 4GB DDR3-LP SODIMM - - PCIe - - One PCIe x4 gold-finger - - One PCIe x4 connector - - One PCIe x2 end-point device (C293 Crypto co-processor) - - IFC/Local Bus - - NOR: 128MB 16-bit NOR Flash - - NAND: 1GB 8-bit NAND flash - - CPLD: for system controlling with programable header on-board - - SATA - - Two SATA 2.0 onnectors on-board - - USB - - Supports two USB 2.0 ports with integrated PHYs - - Two type A ports with 5V@1.5A per port. - - SDHC - - one TF-card connector on-board - - SPI - - On-board 64MB SPI flash - - Other - - Two Serial ports - - Four I2C ports - - -System Memory map ------------------ -Start Address End Address Description Size -0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB -0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB -0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB -0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB -0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB -0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB -0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB -0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB -0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB -0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB -0xF_0000_0000 0xF_003F_FFFF DCSR 4MB -0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB -0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB -0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB -0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB -0x0_0000_0000 0x0_ffff_ffff DDR 4GB - - -128M NOR Flash memory Map -------------------------- -Start Address End Address Definition Max size -0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB -0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB -0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB -0xEFE00000 0xEFE3FFFF PHY CS4315 firmware 256KB -0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB -0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB -0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB -0xEC000000 0xEC01FFFF RCW (alt bank) 128KB -0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB -0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB -0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB -0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB -0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB -0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB -0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB -0xE8000000 0xE801FFFF RCW (current bank) 128KB - - -T2080PCIe-RDB Ethernet Port Map -------------------------------- -Label In Uboot In Linux FMan Address Comments PHY -ETH0 FM1@GTEC1 fm1-mac9 0xfe4f0000 10G SFP+ (CS4315) -ETH1 FM1@GTEC2 fm1-mac10 0xfe4f2000 10G SFP+ (CS4315) -ETH2 FM1@GTEC3 fm1-mac1 0xfe4e0000 10G Base-T (AQ1202) -ETH3 FM1@GTEC4 fm1-mac2 0xfe4e2000 10G Base-T (AQ1202) -ETH4 FM1@DTSEC3 fm1-mac3 0xfe4e4000 1G RGMII (RTL8211E) -ETH5 FM1@DTSEC4 fm1-mac4 0xfe4e6000 1G RGMII (RTL8211E) - - -T2080PCIe-RDB Default DIP-Switch setting ----------------------------------------- -SW1[1:8] = '00010011' -SW2[1:8] = '10111111' -SW3[1:8] = '11100001' - -Software configurations and board settings ------------------------------------------- -1. NOR boot: - a. build NOR boot image - $ make T2080RDB_config - $ make - b. program u-boot.bin image to NOR flash - => tftp 1000000 u-boot.bin - => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize - set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot - - Switching between default bank and alternate bank on NOR flash - To change boot source to vbank4: - via software: run command 'cpld reset altbank' in u-boot. - via DIP-switch: set SW3[5:7] = '100' - - To change boot source to vbank0: - via software: run command 'cpld reset' in u-boot. - via DIP-Switch: set SW3[5:7] = '000' - -2. NAND Boot: - a. build PBL image for NAND boot - $ make T2080RDB_NAND_config - $ make - b. program u-boot-with-spl-pbl.bin to NAND flash - => tftp 1000000 u-boot-with-spl-pbl.bin - => nand erase 0 d0000 - => nand write 1000000 0 $filesize - set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot - -3. SPI Boot: - a. build PBL image for SPI boot - $ make T2080RDB_SPIFLASH_config - $ make - b. program u-boot-with-spl-pbl.bin to SPI flash - => tftp 1000000 u-boot-with-spl-pbl.bin - => sf probe 0 - => sf erase 0 d0000 - => sf write 1000000 0 $filesize - set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot - -4. SD Boot: - a. build PBL image for SD boot - $ make T2080RDB_SDCARD_config - $ make - b. program u-boot-with-spl-pbl.bin to micro-SD/TF card - => tftp 1000000 u-boot-with-spl-pbl.bin - => mmc write 1000000 8 0x800 - set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot - - -2-stage NAND/SPI/SD boot loader -------------------------------- -PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. -SPL further initializes DDR using SPD and environment variables -and copy u-boot(768 KB) from NAND/SPI/SD device to DDR. -Finally SPL transers control to u-boot for futher booting. - -SPL has following features: - - Executes within 256K - - No relocation required - -Run time view of SPL framework -------------------------------------------------- -|Area | Address | -------------------------------------------------- -|SecureBoot header | 0xFFFC0000 (32KB) | -------------------------------------------------- -|GD, BD | 0xFFFC8000 (4KB) | -------------------------------------------------- -|ENV | 0xFFFC9000 (8KB) | -------------------------------------------------- -|HEAP | 0xFFFCB000 (50KB) | -------------------------------------------------- -|STACK | 0xFFFD8000 (22KB) | -------------------------------------------------- -|U-boot SPL | 0xFFFD8000 (160KB) | -------------------------------------------------- - -NAND Flash memory Map on T2080RDB --------------------------------------------------------------- -Start End Definition Size -0x000000 0x0FFFFF u-boot img 1MB (2 blocks) -0x100000 0x17FFFF u-boot env 512KB (1 block) -0x180000 0x1FFFFF FMAN ucode 512KB (1 block) -0x200000 0x27FFFF CS4315 ucode 512KB (1 block) - - -Micro SD Card memory Map on T2080RDB ----------------------------------------------------- -Block #blocks Definition Size -0x008 2048 u-boot img 1MB -0x800 0016 u-boot env 8KB -0x820 0128 FMAN ucode 64KB -0x8a0 0512 CS4315 ucode 256KB - - -SPI Flash memory Map on T2080RDB ----------------------------------------------------- -Start End Definition Size -0x000000 0x0FFFFF u-boot img 1MB -0x100000 0x101FFF u-boot env 8KB -0x110000 0x11FFFF FMAN ucode 64KB -0x120000 0x15FFFF CS4315 ucode 256KB - - -How to update the ucode of Cortina CS4315/CS4340 10G PHY --------------------------------------------------------- -=> tftp 1000000 CS4315-CS4340-PHY-ucode.txt -=> pro off all;era 0xefe00000 0xefefffff;cp.b 1000000 0xefe00000 $filesize - - -How to update the ucode of Freescale FMAN ------------------------------------------ -=> tftp 1000000 fsl_fman_ucode_t2080_r1.0.bin -=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize - - -For more details, please refer to T2080PCIe-RDB User Guide and access -website www.freescale.com and Freescale QorIQ SDK Infocenter document. diff --git a/qemu/roms/u-boot/board/freescale/t208xrdb/cpld.c b/qemu/roms/u-boot/board/freescale/t208xrdb/cpld.c deleted file mode 100644 index 4aa126be5..000000000 --- a/qemu/roms/u-boot/board/freescale/t208xrdb/cpld.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Freescale T2080RDB board-specific CPLD controlling supports. - */ - -#include <common.h> -#include <command.h> -#include "cpld.h" - -u8 cpld_read(unsigned int reg) -{ - void *p = (void *)CONFIG_SYS_CPLD_BASE; - - return in_8(p + reg); -} - -void cpld_write(unsigned int reg, u8 value) -{ - void *p = (void *)CONFIG_SYS_CPLD_BASE; - - out_8(p + reg, value); -} - -/* Set the boot bank to the alternate bank */ -void cpld_set_altbank(void) -{ - u8 reg = CPLD_READ(flash_csr); - - reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; - CPLD_WRITE(flash_csr, reg); - CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET); -} - -/* Set the boot bank to the default bank */ -void cpld_set_defbank(void) -{ - u8 reg = CPLD_READ(flash_csr); - - reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; - CPLD_WRITE(flash_csr, reg); - CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET); -} - -int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int rc = 0; - - if (argc <= 1) - return cmd_usage(cmdtp); - - if (strcmp(argv[1], "reset") == 0) { - if (strcmp(argv[2], "altbank") == 0) - cpld_set_altbank(); - else - cpld_set_defbank(); - } else { - rc = cmd_usage(cmdtp); - } - - return rc; -} - -U_BOOT_CMD( - cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, - "Reset the board or alternate bank", - "reset: reset to default bank\n" - "cpld reset altbank: reset to alternate bank\n" -); diff --git a/qemu/roms/u-boot/board/freescale/t208xrdb/cpld.h b/qemu/roms/u-boot/board/freescale/t208xrdb/cpld.h deleted file mode 100644 index 3f1533888..000000000 --- a/qemu/roms/u-boot/board/freescale/t208xrdb/cpld.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * CPLD register set of T2080RDB board-specific. - */ -struct cpld_data { - u8 chip_id1; /* 0x00 - Chip ID1 register */ - u8 chip_id2; /* 0x01 - Chip ID2 register */ - u8 hw_ver; /* 0x02 - Hardware Revision Register */ - u8 sw_ver; /* 0x03 - Software Revision register */ - u8 res0[12]; /* 0x04 - 0x0F - not used */ - u8 reset_ctl; /* 0x10 - Reset control Register */ - u8 flash_csr; /* 0x11 - Flash control and status register */ - u8 thermal_csr; /* 0x12 - Thermal control and status register */ - u8 led_csr; /* 0x13 - LED control and status register */ - u8 sfp_csr; /* 0x14 - SFP+ control and status register */ - u8 misc_csr; /* 0x15 - Misc control and status register */ - u8 boot_or; /* 0x16 - Boot config override register */ - u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */ - u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */ -} cpld_data_t; - -u8 cpld_read(unsigned int reg); -void cpld_write(unsigned int reg, u8 value); - -#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) -#define CPLD_WRITE(reg, value) \ - cpld_write(offsetof(struct cpld_data, reg), value) - -/* CPLD on IFC */ -#define CPLD_LBMAP_MASK 0x3F -#define CPLD_BANK_SEL_MASK 0x07 -#define CPLD_BANK_OVERRIDE 0x40 -#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ -#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */ -#define CPLD_LBMAP_RESET 0xFF -#define CPLD_LBMAP_SHIFT 0x03 -#define CPLD_BOOT_SEL 0x80 diff --git a/qemu/roms/u-boot/board/freescale/t208xrdb/ddr.c b/qemu/roms/u-boot/board/freescale/t208xrdb/ddr.c deleted file mode 100644 index 8a2627627..000000000 --- a/qemu/roms/u-boot/board/freescale/t208xrdb/ddr.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 or later as published by the Free Software Foundation. - */ - -#include <common.h> -#include <i2c.h> -#include <hwconfig.h> -#include <asm/mmu.h> -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> -#include <asm/fsl_law.h> -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 1) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - pbsp = udimms[0]; - - /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks && - (pdimm->rank_density >> 30) >= pbsp->rank_gb) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found"); - printf("for data rate %lu MT/s\n", ddr_freq); - printf("Trying to use the highest speed (%u) parameters\n", - pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" - "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " - "wrlvl_ctrl_3 0x%x\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, - pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, - pbsp->wrlvl_ctl_3); - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* DHC_EN =1, ODT = 75 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); -} - -phys_size_t initdram(int board_type) -{ - phys_size_t dram_size; - -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) - puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - /* DDR has been initialised by first stage boot loader */ - dram_size = fsl_ddr_sdram_size(); -#endif - return dram_size; -} diff --git a/qemu/roms/u-boot/board/freescale/t208xrdb/ddr.h b/qemu/roms/u-boot/board/freescale/t208xrdb/ddr.h deleted file mode 100644 index b6d406219..000000000 --- a/qemu/roms/u-boot/board/freescale/t208xrdb/ddr.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __DDR_H__ -#define __DDR_H__ -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ - -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | - */ - {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, - {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, - {2, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a}, - {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, - {2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, - {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, - {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, - {1, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a}, - {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, - {1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c}, - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; -#endif diff --git a/qemu/roms/u-boot/board/freescale/t208xrdb/eth_t208xrdb.c b/qemu/roms/u-boot/board/freescale/t208xrdb/eth_t208xrdb.c deleted file mode 100644 index cbbc62583..000000000 --- a/qemu/roms/u-boot/board/freescale/t208xrdb/eth_t208xrdb.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * Shengzhou Liu <Shengzhou.Liu@freescale.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <netdev.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> -#include <malloc.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <miiphy.h> -#include <phy.h> -#include <asm/fsl_dtsec.h> -#include <asm/fsl_serdes.h> - -int board_eth_init(bd_t *bis) -{ -#if defined(CONFIG_FMAN_ENET) - int i, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - switch (srds_s1) { - case 0x66: - case 0x6b: - fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1); - fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2); - fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR); - break; - default: - printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n", - srds_s1); - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_RGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} - -void fdt_fixup_board_enet(void *fdt) -{ - return; -} diff --git a/qemu/roms/u-boot/board/freescale/t208xrdb/law.c b/qemu/roms/u-boot/board/freescale/t208xrdb/law.c deleted file mode 100644 index eb82431e2..000000000 --- a/qemu/roms/u-boot/board/freescale/t208xrdb/law.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright 2008-2014 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), -#endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), -#endif -#ifdef CONFIG_SYS_CPLD_BASE_PHYS - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), -#endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), -#endif -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/qemu/roms/u-boot/board/freescale/t208xrdb/pci.c b/qemu/roms/u-boot/board/freescale/t208xrdb/pci.c deleted file mode 100644 index ba7041af9..000000000 --- a/qemu/roms/u-boot/board/freescale/t208xrdb/pci.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright 2007-2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <pci.h> -#include <asm/fsl_pci.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <asm/fsl_serdes.h> - -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} - -void pci_of_setup(void *blob, bd_t *bd) -{ - FT_FSL_PCI_SETUP; -} diff --git a/qemu/roms/u-boot/board/freescale/t208xrdb/spl.c b/qemu/roms/u-boot/board/freescale/t208xrdb/spl.c deleted file mode 100644 index 9ae2b1e86..000000000 --- a/qemu/roms/u-boot/board/freescale/t208xrdb/spl.c +++ /dev/null @@ -1,107 +0,0 @@ -/* Copyright 2013 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <malloc.h> -#include <ns16550.h> -#include <nand.h> -#include <i2c.h> -#include <mmc.h> -#include <fsl_esdhc.h> -#include <spi_flash.h> - -DECLARE_GLOBAL_DATA_PTR; - -phys_size_t get_effective_memsize(void) -{ - return CONFIG_SYS_L3_SIZE; -} - -unsigned long get_board_sys_clk(void) -{ - return CONFIG_SYS_CLK_FREQ; -} - -unsigned long get_board_ddr_clk(void) -{ - return CONFIG_DDR_CLK_FREQ; -} - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio, sys_clk, ccb_clk; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - - /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ - memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); - - /* Update GD pointer */ - gd = (gd_t *)(CONFIG_SPL_GD_ADDR); - - console_init_f(); - - /* initialize selected port with appropriate baud rate */ - sys_clk = get_board_sys_clk(); - plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; - ccb_clk = sys_clk * plat_ratio / 2; - - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - ccb_clk / 16 / CONFIG_BAUDRATE); - -#if defined(CONFIG_SPL_MMC_BOOT) - puts("\nSD boot...\n"); -#elif defined(CONFIG_SPL_SPI_BOOT) - puts("\nSPI boot...\n"); -#elif defined(CONFIG_SPL_NAND_BOOT) - puts("\nNAND boot...\n"); -#endif - - relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - bd_t *bd; - - bd = (bd_t *)(gd + sizeof(gd_t)); - memset(bd, 0, sizeof(bd_t)); - gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; - bd->bi_memsize = CONFIG_SYS_L3_SIZE; - - probecpu(); - get_clocks(); - mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, - CONFIG_SPL_RELOC_MALLOC_SIZE); - -#ifdef CONFIG_SPL_NAND_BOOT - nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)CONFIG_ENV_ADDR); -#endif -#ifdef CONFIG_SPL_MMC_BOOT - mmc_initialize(bd); - mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)CONFIG_ENV_ADDR); -#endif -#ifdef CONFIG_SPL_SPI_BOOT - spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)CONFIG_ENV_ADDR); -#endif - - gd->env_addr = (ulong)(CONFIG_ENV_ADDR); - gd->env_valid = 1; - - i2c_init_all(); - - gd->ram_size = initdram(0); - -#ifdef CONFIG_SPL_MMC_BOOT - mmc_boot(); -#elif defined(CONFIG_SPL_SPI_BOOT) - spi_boot(); -#elif defined(CONFIG_SPL_NAND_BOOT) - nand_boot(); -#endif -} diff --git a/qemu/roms/u-boot/board/freescale/t208xrdb/t2080_pbi.cfg b/qemu/roms/u-boot/board/freescale/t208xrdb/t2080_pbi.cfg deleted file mode 100644 index e200d926f..000000000 --- a/qemu/roms/u-boot/board/freescale/t208xrdb/t2080_pbi.cfg +++ /dev/null @@ -1,41 +0,0 @@ -# -# Copyright 2013 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer doc/README.pblimage for more details about how-to configure -# and create PBL boot image -# - -#PBI commands -#Initialize CPC1 -09010000 00200400 -09138000 00000000 -091380c0 00000100 -#512KB SRAM -09010100 00000000 -09010104 fff80009 -09010f00 08000000 -#enable CPC1 -09010000 80000000 -#Configure LAW for CPC1 -09000d00 00000000 -09000d04 fff80000 -09000d08 81000012 -#Initialize eSPI controller, default configuration is slow for eSPI to -#load data, this configuration comes from u-boot eSPI driver. -09110000 80000403 -09110020 2d170008 -09110024 00100008 -09110028 00100008 -0911002c 00100008 -#Errata for slowing down the MDC clock to make it <= 2.5 MHZ -094fc030 00008148 -094fd030 00008148 -#Configure alternate space -09000010 00000000 -09000014 ff000000 -09000018 81000000 -#Flush PBL data -09138000 00000000 -091380c0 00000000 diff --git a/qemu/roms/u-boot/board/freescale/t208xrdb/t2080_rcw.cfg b/qemu/roms/u-boot/board/freescale/t208xrdb/t2080_rcw.cfg deleted file mode 100644 index cd62cc864..000000000 --- a/qemu/roms/u-boot/board/freescale/t208xrdb/t2080_rcw.cfg +++ /dev/null @@ -1,8 +0,0 @@ -#PBL preamble and RCW header for T2080RDB -aa55aa55 010e0100 -#SerDes Protocol: 0x66_0x16 -#Core/DDR: 1533Mhz/1600MT/s -120c0017 15000000 00000000 00000000 -66160002 00008400 ec104000 c1000000 -00000000 00000000 00000000 000307fc -00000000 00000000 00000000 00000004 diff --git a/qemu/roms/u-boot/board/freescale/t208xrdb/t208xrdb.c b/qemu/roms/u-boot/board/freescale/t208xrdb/t208xrdb.c deleted file mode 100644 index 265c1f97d..000000000 --- a/qemu/roms/u-boot/board/freescale/t208xrdb/t208xrdb.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright 2009-2013 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <i2c.h> -#include <netdev.h> -#include <linux/compiler.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> -#include <fm_eth.h> -#include "t208xrdb.h" -#include "cpld.h" - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - struct cpu_type *cpu = gd->arch.cpu; - static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; - - printf("Board: %sRDB, ", cpu->name); - printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ", - CPLD_READ(hw_ver), CPLD_READ(sw_ver)); - -#ifdef CONFIG_SDCARD - puts("SD/MMC\n"); -#elif CONFIG_SPIFLASH - puts("SPI\n"); -#else - u8 reg; - - reg = CPLD_READ(flash_csr); - - if (reg & CPLD_BOOT_SEL) { - puts("NAND\n"); - } else { - reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); - printf("NOR vBank%d\n", reg); - } -#endif - - puts("SERDES Reference Clocks:\n"); - printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); - printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]); - - return 0; -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); - - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - - return 0; -} - -unsigned long get_board_sys_clk(void) -{ - return CONFIG_SYS_CLK_FREQ; -} - -unsigned long get_board_ddr_clk(void) -{ - return CONFIG_DDR_CLK_FREQ; -} - -int misc_init_r(void) -{ - return 0; -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = getenv_bootm_low(); - size = getenv_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_PCI - pci_of_setup(blob, bd); -#endif - - fdt_fixup_liodn(blob); - fdt_fixup_dr_usb(blob, bd); - -#ifdef CONFIG_SYS_DPAA_FMAN - fdt_fixup_fman_ethernet(blob); - fdt_fixup_board_enet(blob); -#endif -} diff --git a/qemu/roms/u-boot/board/freescale/t208xrdb/t208xrdb.h b/qemu/roms/u-boot/board/freescale/t208xrdb/t208xrdb.h deleted file mode 100644 index 13380d02a..000000000 --- a/qemu/roms/u-boot/board/freescale/t208xrdb/t208xrdb.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CORENET_DS_H__ -#define __CORENET_DS_H__ - -void fdt_fixup_board_enet(void *blob); -void pci_of_setup(void *blob, bd_t *bd); - -#endif diff --git a/qemu/roms/u-boot/board/freescale/t208xrdb/tlb.c b/qemu/roms/u-boot/board/freescale/t208xrdb/tlb.c deleted file mode 100644 index 2ebea36a5..000000000 --- a/qemu/roms/u-boot/board/freescale/t208xrdb/tlb.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright 2008-2014 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) - /* - * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the - * SRAM is at 0xfff00000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) - /* - * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the - * space is at 0xfff00000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), -#else - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), -#endif - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_16M, 1), - - /* *I*G* - Flash, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - -#ifndef CONFIG_SPL_BUILD - /* *I*G* - PCIe 1, 0x80000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_512M, 1), - - /* *I*G* - PCIe 2, 0xa0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCIe 3, 0xb0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - - - /* *I*G* - PCIe 4, 0xc0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256K, 1), - - /* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_16M, 1), -#endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 11, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 12, BOOKE_PAGESZ_16M, 1), -#endif -#endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 13, BOOKE_PAGESZ_32M, 1), -#endif -#ifdef CONFIG_SYS_NAND_BASE - /* - * *I*G - NAND - * entry 14 and 15 has been used hard coded, they will be disabled - * in cpu_init_f, so we use entry 16 for nand. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 16, BOOKE_PAGESZ_64K, 1), -#endif -#ifdef CONFIG_SYS_CPLD_BASE - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 17, BOOKE_PAGESZ_4K, 1), -#endif -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE - /* - * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for - * fetching ucode and ENV from master - */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, - 0, 18, BOOKE_PAGESZ_1M, 1), -#endif -#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 19, BOOKE_PAGESZ_2G, 1) -#endif - -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); |