diff options
Diffstat (limited to 'qemu/roms/u-boot/board/freescale/p1023rds')
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/p1023rds/Makefile | 9 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/p1023rds/README | 101 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/p1023rds/bcsr.h | 49 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/p1023rds/law.c | 19 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/p1023rds/p1023rds.c | 196 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/p1023rds/tlb.c | 102 |
6 files changed, 476 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/board/freescale/p1023rds/Makefile b/qemu/roms/u-boot/board/freescale/p1023rds/Makefile new file mode 100644 index 000000000..fdbf365ea --- /dev/null +++ b/qemu/roms/u-boot/board/freescale/p1023rds/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2010-2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += p1023rds.o +obj-y += law.o +obj-y += tlb.o diff --git a/qemu/roms/u-boot/board/freescale/p1023rds/README b/qemu/roms/u-boot/board/freescale/p1023rds/README new file mode 100644 index 000000000..d382551c4 --- /dev/null +++ b/qemu/roms/u-boot/board/freescale/p1023rds/README @@ -0,0 +1,101 @@ +Overview +-------- +The P1023 process includes a performance optimized implementation of the +QorIQ data Path Acceleration Architecture (DPAA). This architecture +provides the infrastructure to support simplified sharing of networking +interfaces and accelerators by multiple CPU cores. P1023 is an e500 based +dual core SOC. + +P1023RDS board is a Low End Dual core platform supporting the P1023 +processor of QorIQ series. + +Building U-boot +--------------- +To build the u-boot for P1023RDS: +Configure to NOR boot: + make P1023RDS_config +Configure to NAND boot: + make P1023RDS_NAND_config +Build: + make + +Board Switches +-------------- +Most switches on the board should not be changed. The most frequent +user-settable switches on the board are used to configure +the flash banks. + +J4: all open + +Default NOR flash boot switch setting: + Sw3[1:8]: off on on off on on off off + Sw4[1:8]: off off off on off off off off + Sw6[1:8]: off on off on off on on off + Sw7[1:8]: off on off off on off off off + Sw8[1:8]: on off off off off off off off + +For NAND flash boot,set +Sw4[1:4]: off on on on + +The default native ethernet setting is for RGMII mode. +To use SGMII mode, set +SW8[1:2]: OFF OFF +SW7[6:7]: ON ON + +Memory Map +---------- +0x0000_0000 0x7fff_ffff DDR 2G Cacheable +0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable +0xc000_0000 0xdfff_ffff PCI 512M non-cacheable +0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable + +0xe000_0000 0xe003_ffff BCSR 256K BCSR +0xee00_0000 0xefff_ffff NOR flash 32M NOR flash +0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M +0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable +0xffa0_0000 0xffaf_ffff NAND FLASH 1M non-cacheable +0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 + +Flashing u-boot Images +--------------- +To program the image in the boot flash bank: +NOR flash boot: + => tftp 1000000 u-boot.bin + => protect off all + => erase eff40000 efffffff + => cp.b 1000000 eff40000 c0000 + +NAND flash boot: + => tftp 1000000 u-boot-nand.bin + => nand erase 0 80000 + => nand write 1000000 0 80000 + +Firmware ucode location +--------------------------------- +Microcode(ucode) to FMAN's IRAM is needed to make FMAN Ethernet work. +u-boot loads ucode FLASH. The location for ucode: +NOR Flash: 0xfe000000 +NAND Flash: 0x1f00000 + +Using the Device Tree Source File +--------------------------------- +To create the DTB (Device Tree Binary) image file, +use a command similar to this: + + dtc -b 0 -f -I dts -O dtb p1023rds.dts > p1023rds.dtb + +Likely, that .dts file will come from here; + + linux-2.6/arch/powerpc/boot/dts/p1023rds.dts +or + make p1023rds.dtb ARCH=powerpc +in linux-2.6 directory. + +Booting Linux +------------- +Place a linux uImage in the TFTP disk area. + + tftp 1000000 uImage + tftp 2000000 rootfs.ext2.gz.uboot + tftp c00000 p1023rds.dtb + bootm 1000000 2000000 c00000 diff --git a/qemu/roms/u-boot/board/freescale/p1023rds/bcsr.h b/qemu/roms/u-boot/board/freescale/p1023rds/bcsr.h new file mode 100644 index 000000000..a9deb72f7 --- /dev/null +++ b/qemu/roms/u-boot/board/freescale/p1023rds/bcsr.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * Authors: Chunhe Lan <b25806@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BCSR_H_ +#define __BCSR_H_ + +#include <common.h> + +/* + * BCSR Bit definitions + * BCSR 15 * + 0 device insertion oriention + 1 stack processor present + 2 power supply shut down/normal operation + 3 I2C bus0 drive enable + 4 reserved + 5:7 I2C bus0 select + 5 - I2C_BUS_0_SS0 + 6 - I2C_BUS_0_SS1 + 7 - I2C_BUS_0_SS2 +*/ + +/* BCSR register base address is 0xFX000020 */ +#define BCSR_BASE_REG_OFFSET 0x20 +#define BCSR_ACCESS_REG_ADDR (CONFIG_SYS_BCSR_BASE + BCSR_BASE_REG_OFFSET) + +#define BCSR15_DEV_INS_ORI 0x80 +#define BCSR15_STACK_PRO_PRE 0x40 +#define BCSR15_POWER_SUPPLY 0x20 +#define BCSR15_I2C_BUS0_EN 0x10 +#define BCSR15_I2C_BUS0_SEG0 0x00 +#define BCSR15_I2C_BUS0_SEG1 0x04 +#define BCSR15_I2C_BUS0_SEG2 0x02 +#define BCSR15_I2C_BUS0_SEG3 0x06 +#define BCSR15_I2C_BUS0_SEG4 0x01 +#define BCSR15_I2C_BUS0_SEG5 0x05 +#define BCSR15_I2C_BUS0_SEG6 0x03 +#define BCSR15_I2C_BUS0_SEG7 0x07 +#define BCSR15_I2C_BUS0_SEG_CLR 0x07 +#define BCSR19_SGMII_SEL_L 0x01 + +/*BCSR Utils functions*/ +void fixup_i2c_bus0_sel_seg0(void); +#endif /* __BCSR_H_ */ diff --git a/qemu/roms/u-boot/board/freescale/p1023rds/law.c b/qemu/roms/u-boot/board/freescale/p1023rds/law.c new file mode 100644 index 000000000..92f5a3fcb --- /dev/null +++ b/qemu/roms/u-boot/board/freescale/p1023rds/law.c @@ -0,0 +1,19 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_4M, + LAW_TRGT_IF_DPAA_SWP_SRAM), + /* The LAW 0xe0000000 ~ 0xefffffff for BCSR and NOR flash */ + SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/qemu/roms/u-boot/board/freescale/p1023rds/p1023rds.c b/qemu/roms/u-boot/board/freescale/p1023rds/p1023rds.c new file mode 100644 index 000000000..d8c87458e --- /dev/null +++ b/qemu/roms/u-boot/board/freescale/p1023rds/p1023rds.c @@ -0,0 +1,196 @@ +/* + * Copyright 2010-2012 Freescale Semiconductor, Inc. + * + * Authors: Roy Zang <tie-fei.zang@freescale.com> + * Chunhe Lan <b25806@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/io.h> +#include <asm/cache.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_pci.h> +#include <fsl_ddr_sdram.h> +#include <asm/fsl_portals.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <netdev.h> +#include <malloc.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <miiphy.h> +#include <phy.h> +#include <asm/fsl_dtsec.h> + +#include "bcsr.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + fsl_lbc_t *lbc = LBC_BASE_ADDR; + + /* Set ABSWP to implement conversion of addresses in the LBC */ + setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); + + return 0; +} + +int checkboard(void) +{ + u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR; + + printf("Board: P1023 RDS\n"); + + clrbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG_CLR); + setbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG0); + + return 0; +} + +/* Fixed sdram init -- doesn't use serial presence detect. */ +phys_size_t fixed_sdram(void) +{ +#ifndef CONFIG_SYS_RAMBOOT + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; + + set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); + + out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); + out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); + out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS); + out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG); + out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); + out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); + out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); + out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); + out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2); + out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1); + out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2); + out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL); + out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); + out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL); + out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); + out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); + out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); + out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); + out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1); + out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2); + out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); +#endif + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024ul; +} + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} +#endif + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_BCSR_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + BCSR region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + bcsr */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_BCSR_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + setup_portals(); + + return 0; +} + +unsigned long get_board_sys_clk(ulong dummy) +{ + return gd->bus_clk; +} + +unsigned long get_board_ddr_clk(ulong dummy) +{ + return gd->mem_clk; +} + +int board_eth_init(bd_t *bis) +{ + u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR; + ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + struct fsl_pq_mdio_info dtsec_mdio_info; + + /* + * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting + * is not correct. + */ + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1); + + dtsec_mdio_info.regs = + (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fsl_pq_mdio_init(bis, &dtsec_mdio_info); + + fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); + + fm_info_set_mdio(FM1_DTSEC1, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + fm_info_set_mdio(FM1_DTSEC2, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + + /* Make SERDES connected to SGMII by cleaing bcsr19[7] */ + if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII) + clrbits_8(&bcsr[19], BCSR19_SGMII_SEL_L); + +#ifdef CONFIG_FMAN_ENET + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + /* By default NOR is on, and NAND is disabled */ +#ifdef CONFIG_NAND_U_BOOT + do_fixup_by_path_string(blob, "nor_flash", "status", "disabled"); + do_fixup_by_path_string(blob, "nand_flash", "status", "okay"); +#endif +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + + fdt_fixup_fman_ethernet(blob); +} +#endif diff --git a/qemu/roms/u-boot/board/freescale/p1023rds/tlb.c b/qemu/roms/u-boot/board/freescale/p1023rds/tlb.c new file mode 100644 index 000000000..8b2bf5079 --- /dev/null +++ b/qemu/roms/u-boot/board/freescale/p1023rds/tlb.c @@ -0,0 +1,102 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_4M, 1), + +#ifndef CONFIG_NAND_SPL + /* *W*G* - BCSR and NOR flash on local bus*/ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, + 0, 9, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_1M, 1), +#endif + + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 11, BOOKE_PAGESZ_1M, 1), + +#ifdef CONFIG_SYS_RAMBOOT + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, + CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 12, BOOKE_PAGESZ_1G, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 13, BOOKE_PAGESZ_1G, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); |