diff options
Diffstat (limited to 'qemu/roms/u-boot/board/freescale/p1010rdb')
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/p1010rdb/Makefile | 30 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/p1010rdb/README.P1010RDB-PA | 208 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/p1010rdb/README.P1010RDB-PB | 188 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/p1010rdb/ddr.c | 235 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/p1010rdb/law.c | 17 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/p1010rdb/p1010rdb.c | 564 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/p1010rdb/spl.c | 108 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/p1010rdb/spl_minimal.c | 65 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/freescale/p1010rdb/tlb.c | 91 |
9 files changed, 0 insertions, 1506 deletions
diff --git a/qemu/roms/u-boot/board/freescale/p1010rdb/Makefile b/qemu/roms/u-boot/board/freescale/p1010rdb/Makefile deleted file mode 100644 index 660d1bbc2..000000000 --- a/qemu/roms/u-boot/board/freescale/p1010rdb/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright 2010-2011 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -MINIMAL= - -ifdef CONFIG_SPL_BUILD -ifdef CONFIG_SPL_INIT_MINIMAL -MINIMAL=y -endif -endif - -ifdef MINIMAL - -obj-y += spl_minimal.o tlb.o law.o - -else - -ifdef CONFIG_SPL_BUILD -obj-y += spl.o -endif - -obj-y += p1010rdb.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o - -endif diff --git a/qemu/roms/u-boot/board/freescale/p1010rdb/README.P1010RDB-PA b/qemu/roms/u-boot/board/freescale/p1010rdb/README.P1010RDB-PA deleted file mode 100644 index cde246dde..000000000 --- a/qemu/roms/u-boot/board/freescale/p1010rdb/README.P1010RDB-PA +++ /dev/null @@ -1,208 +0,0 @@ -Overview -========= -The P1010RDB is a Freescale reference design board that hosts the P1010 SoC. - -The P1010 is a cost-effective, low-power, highly integrated host processor -based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz), -that addresses the requirements of several routing, gateways, storage, consumer, -and industrial applications. Applications of interest include the main CPUs and -I/O processors in network attached storage (NAS), the voice over IP (VoIP) -router/gateway, and wireless LAN (WLAN) and industrial controllers. - -The P1010RDB board features are as follows: -Memory subsystem: - - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) - - 32 Mbyte NOR flash single-chip memory - - 32 Mbyte NAND flash memory - - 256 Kbit M24256 I2C EEPROM - - 16 Mbyte SPI memory - - I2C Board EEPROM 128x8 bit memory - - SD/MMC connector to interface with the SD memory card -Interfaces: - - PCIe: - - Lane0: x1 mini-PCIe slot - - Lane1: x1 PCIe standard slot - - SATA: - - 1 internal SATA connector to 2.5” 160G SATA2 HDD - - 1 eSATA connector to rear panel - - 10/100/1000 BaseT Ethernet ports: - - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO - - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221 - - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221 - - USB 2.0 port: - - x1 USB2.0 port via an external ULPI PHY to micro-AB connector - - x1 USB2.0 port via an internal UTMI PHY to micro-AB connector - - FlexCAN ports: - - 2 DB-9 female connectors for FlexCAN bus(revision 2.0B) - interface; - - DUART interface: - - DUART interface: supports two UARTs up to 115200 bps for - console display - - RJ45 connectors are used for these 2 UART ports. - - TDM - - 2 FXS ports connected via an external SLIC to the TDM interface. - SLIC is controllled via SPI. - - 1 FXO port connected via a relay to FXS for switchover to POTS -Board connectors: - - Mini-ITX power supply connector - - JTAG/COP for debugging -IEEE Std. 1588 signals for test and measurement -Real-time clock on I2C bus -POR - - support critical POR setting changed via switch on board -PCB - - 6-layer routing (4-layer signals, 2-layer power and ground) - - -Physical Memory Map on P1010RDB -=============================== -Address Start Address End Memory type Attributes -0x0000_0000 0x3fff_ffff DDR 1G Cacheable -0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable -0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable -0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable -0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable -0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable -0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0 -0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - - -Serial Port Configuration on P1010RDB -===================================== -Configure the serial port of the attached computer with the following values: - -Data rate: 115200 bps - -Number of data bits: 8 - -Parity: None - -Number of Stop bits: 1 - -Flow Control: Hardware/None - - -Settings of DIP-switch -====================== - SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash - SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash - SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash -Note: 1 stands for 'on', 0 stands for 'off' - - -Setting of hwconfig -=================== -If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or -"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example: -setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi" -By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection -is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM -instead of to CAN/UART1. - - -Build and burn u-boot to NOR flash -================================== -1. Build u-boot.bin image - export ARCH=powerpc - export CROSS_COMPILE=/your_path/powerpc-linux-gnu- - make P1010RDB_NOR - -2. Burn u-boot.bin into NOR flash - => tftp $loadaddr $uboot - => protect off eff40000 +$filesize - => erase eff40000 +$filesize - => cp.b $loadaddr eff40000 $filesize - -3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on. - - -Alternate NOR bank -================== -1. Burn u-boot.bin into alternate NOR bank - => tftp $loadaddr $uboot - => protect off eef40000 +$filesize - => erase eef40000 +$filesize - => cp.b $loadaddr eef40000 $filesize - -2. Switch to alternate NOR bank - => mw.b ffb00009 1 - => reset - or set SW1[8]= ON - -SW1[8]= OFF: Upper bank used for booting start -SW1[8]= ON: Lower bank used for booting start -CPLD NOR bank selection register address 0xFFB00009 Bit[0]: -0 - boot from upper 4 sectors -1 - boot from lower 4 sectors - - -Build and burn u-boot to NAND flash -=================================== -1. Build u-boot.bin image - export ARCH=powerpc - export CROSS_COMPILE=/your_path/powerpc-linux-gnu- - make P1010RDB_NAND - -2. Burn u-boot-nand.bin into NAND flash - => tftp $loadaddr $uboot-nand - => nand erase 0 $filesize - => nand write $loadaddr 0 $filesize - -3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on. - - -Build and burn u-boot to SPI flash -================================== -1. Build u-boot-spi.bin image - make P1010RDB_SPIFLASH_config; make - Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb - Download u-boot.bin to linux and you can find some config files - under /usr/share such as config_xx.dat. Do below command: - boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \ - u-boot-spi.bin - to generate u-boot-spi.bin. - -2. Burn u-boot-spi.bin into SPI flash - => tftp $loadaddr $uboot-spi - => sf erase 0 100000 - => sf write $loadaddr 0 $filesize - -3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on. - - -CPLD POR setting registers -========================== -1. Set POR switch selection register (addr 0xFFB00011) to 0. -2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with - proper values. - If change boot ROM location to NOR or NAND flash, need write the IFC_CS0 - switch command by I2C. -3. Send reset command. - After reset, the new POR setting will be implemented. - -Two examples are given in below: -Switch from NOR to NAND boot with default frequency: - => i2c dev 0 - => i2c mw 18 1 f9 - => i2c mw 18 3 f0 - => mw.b ffb00011 0 - => mw.b ffb00017 1 - => reset -Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz): - => i2c dev 0 - => i2c mw 18 1 f1 - => i2c mw 18 3 f0 - => mw.b ffb00011 0 - => mw.b ffb00014 2 - => mw.b ffb00015 5 - => mw.b ffb00016 3 - => mw.b ffb00017 f - => reset - - -Boot Linux from network using TFTP on P1010RDB -============================================== -Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area. - => tftp 1000000 uImage - => tftp 2000000 p1010rdb.dtb - => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb - => bootm 1000000 3000000 2000000 - - -For more details, please refer to P1010RDB User Guide and access website -www.freescale.com diff --git a/qemu/roms/u-boot/board/freescale/p1010rdb/README.P1010RDB-PB b/qemu/roms/u-boot/board/freescale/p1010rdb/README.P1010RDB-PB deleted file mode 100644 index c5d141944..000000000 --- a/qemu/roms/u-boot/board/freescale/p1010rdb/README.P1010RDB-PB +++ /dev/null @@ -1,188 +0,0 @@ -Overview -========= -The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC. -P1010RDB-PB is a variation of previous P1010RDB-PA board. - -The P1010 is a cost-effective, low-power, highly integrated host processor -based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that -addresses the requirements of several routing, gateways, storage, consumer, -and industrial applications. Applications of interest include the main CPUs and -I/O processors in network attached storage (NAS), the voice over IP (VoIP) -router/gateway, and wireless LAN (WLAN) and industrial controllers. - -The P1010RDB-PB board features are as following: -Memory subsystem: - - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus) - - 32M bytes NOR flash single-chip memory - - 2G bytes NAND flash memory - - 16M bytes SPI memory - - 256K bit M24256 I2C EEPROM - - I2C Board EEPROM 128x8 bit memory - - SD/MMC connector to interface with the SD memory card -Interfaces: - - Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII) - - PCIe 2.0: two x1 mini-PCIe slots - - SATA 2.0: two SATA interfaces - - USB 2.0: one USB interface - - FlexCAN: two FlexCAN interfaces (revision 2.0B) - - UART: one USB-to-Serial interface - - TDM: 2 FXS ports connected via an external SLIC to the TDM interface. - 1 FXO port connected via a relay to FXS for switchover to POTS - -Board connectors: - - Mini-ITX power supply connector - - JTAG/COP for debugging - -POR: support critical POR setting changed via switch on board -PCB: 6-layer routing (4-layer signals, 2-layer power and ground) - -Physical Memory Map on P1010RDB -=============================== -Address Start Address End Memory type Attributes -0x0000_0000 0x3fff_ffff DDR 1G Cacheable -0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable -0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable -0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable -0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable -0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable -0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0 -0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - - -Serial Port Configuration on P1010RDB -===================================== -Configure the serial port of the attached computer with the following values: - -Data rate: 115200 bps - -Number of data bits: 8 - -Parity: None - -Number of Stop bits: 1 - -Flow Control: Hardware/None - - -P1010RDB-PB default DIP-switch settings -======================================= -SW1[1:8]= 10101010 -SW2[1:8]= 11011000 -SW3[1:8]= 10010000 -SW4[1:4]= 1010 -SW5[1:8]= 11111010 - - -P1010RDB-PB boot mode settings via DIP-switch -============================================= -SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot -SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot -SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot -SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot -Note: 1 stands for 'on', 0 stands for 'off' - - -Switch P1010RDB-PB boot mode via software without setting DIP-switch -==================================================================== -=> run boot_bank0 (boot from NOR bank0) -=> run boot_bank1 (boot from NOR bank1) -=> run boot_nand (boot from NAND flash) -=> run boot_spi (boot from SPI flash) -=> run boot_sd (boot from SD card) - - -Frequency combination support on P1010RDB-PB -============================================= -SW1[4:7] SW5[1] SW5[5:8] SW2[2] Core(MHz) Platform(MHz) DDR(MT/s) -0101 1 1010 0 800 400 800 -1001 1 1010 0 800 400 667 -1010 1 1100 0 667 333 667 -1000 0 1010 0 533 266 667 -0101 1 1010 1 1000 400 800 -1001 1 1010 1 1000 400 667 - - -Setting of pin mux -================== -Since pins multiplexing, TDM and CAN are muxed with SPI flash. -SDHC is muxed with IFC. IFC and SPI flash are enabled by default. - -To enable TDM: -=> setenv hwconfig fsl_p1010mux:tdm_can=tdm -=> save;reset - -To enable FlexCAN: -=> setenv hwconfig fsl_p1010mux:tdm_can=can -=> save;reset - -To enable SDHC in case of NOR/NAND/SPI boot - a) For temporary use case in runtime without reboot system - run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC. - - b) For long-term use case - set 'esdhc' in hwconfig and save it. - -To enable IFC in case of SD boot - a) For temporary use case in runtime without reboot system - run 'mux ifc' in u-boot to validate IFC with invalidating SDHC. - - b) For long-term use case - set 'ifc' in hwconfig and save it. - - -Build images for different boot mode -==================================== -First setup cross compile environment on build host - $ export ARCH=powerpc - $ export CROSS_COMPILE=<your-compiler-path>/powerpc-linux-gnu- - -1. For NOR boot - $ make P1010RDB-PB_NOR - -2. For NAND boot - $ make P1010RDB-PB_NAND - -3. For SPI boot - $ make P1010RDB-PB_SPIFLASH - -4. For SD boot - $ make P1010RDB-PB_SDCARD - - -Steps to program images to flash for different boot mode -======================================================== -1. NOR boot - => tftp 1000000 u-boot.bin - For bank0 - => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize - set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board - - For bank1 - => pro off all;era eef40000 eeffffff;cp.b 1000000 eef40000 $filesize - set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board - -2. NAND boot - => tftp 1000000 u-boot-nand.bin - => nand erase 0 $filesize; nand write $loadaddr 0 $filesize - Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board - -3. SPI boot - 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-spi-combined.bin - 2) => tftp 1000000 u-boot-spi-combined.bin - 3) => sf probe 0; sf erase 0 100000; sf write 1000000 0 100000 - set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board - -4. SD boot - 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-sd-combined.bin - 2) => tftp 1000000 u-boot-sd-combined.bin - 3) => mux sdhc - 4) => mmc write 1000000 0 1050 - set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board - - -Boot Linux from network using TFTP on P1010RDB-PB -================================================= -Place uImage, p1010rdb.dtb and rootfs files in the TFTP download path. - => tftp 1000000 uImage - => tftp 2000000 p1010rdb.dtb - => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb - => bootm 1000000 3000000 2000000 - - -For more details, please refer to P1010RDB-PB User Guide and access website -www.freescale.com and Freescale QorIQ SDK Infocenter document. diff --git a/qemu/roms/u-boot/board/freescale/p1010rdb/ddr.c b/qemu/roms/u-boot/board/freescale/p1010rdb/ddr.c deleted file mode 100644 index b0d95ea00..000000000 --- a/qemu/roms/u-boot/board/freescale/p1010rdb/ddr.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> -#include <asm/immap_85xx.h> -#include <asm/processor.h> -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> -#include <asm/io.h> -#include <asm/fsl_law.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_SYS_DRAM_SIZE 1024 - -fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_667, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {750, 850, &ddr_cfg_regs_800}, - {607, 749, &ddr_cfg_regs_667}, - {0, 0, NULL} -}; - -unsigned long get_sdram_size(void) -{ - struct cpu_type *cpu; - phys_size_t ddr_size; - - cpu = gd->arch.cpu; - /* P1014 and it's derivatives support max 16it DDR width */ - if (cpu->soc_ver == SVR_P1014) - ddr_size = (CONFIG_SYS_DRAM_SIZE / 2); - else - ddr_size = CONFIG_SYS_DRAM_SIZE; - - return ddr_size; -} - -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ -phys_size_t fixed_sdram(void) -{ - int i; - char buf[32]; - fsl_ddr_cfg_regs_t ddr_cfg_regs; - phys_size_t ddr_size; - ulong ddr_freq, ddr_freq_mhz; - struct cpu_type *cpu; - -#if defined(CONFIG_SYS_RAMBOOT) - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -#endif - - ddr_freq = get_ddr_freq(0); - ddr_freq_mhz = ddr_freq / 1000000; - - printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { - if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && - (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { - memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, - sizeof(ddr_cfg_regs)); - break; - } - } - - if (fixed_ddr_parm_0[i].max_freq == 0) - panic("Unsupported DDR data rate %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - cpu = gd->arch.cpu; - /* P1014 and it's derivatives support max 16bit DDR width */ - if (cpu->soc_ver == SVR_P1014) { - ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK; - ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE; - /* divide SA and EA by two and then mask the rest so we don't - * write to reserved fields */ - ddr_cfg_regs.cs[0].bnds = (CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff; - } - - ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); - - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, - LAW_TRGT_IF_DDR_1) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } - - return ddr_size; -} - -#else /* CONFIG_SYS_DDR_RAW_TIMING */ -/* - * Samsung K4B2G0846C-HCF8 - * The following timing are for "downshift" - * i.e. to use CL9 part as CL7 - * otherwise, tAA, tRCD, tRP will be 13500ps - * and tRC will be 49500ps - */ -dimm_params_t ddr_raw_timing = { - .n_ranks = 1, - .rank_density = 1073741824u, - .capacity = 1073741824u, - .primary_sdram_width = 32, - .ec_sdram_width = 0, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 15, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 0, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 1875, - .caslat_x = 0x1e << 4, /* 5,6,7,8 */ - .taa_ps = 13125, - .twr_ps = 15000, - .trcd_ps = 13125, - .trrd_ps = 7500, - .trp_ps = 13125, - .tras_ps = 37500, - .trc_ps = 50625, - .trfc_ps = 160000, - .twtr_ps = 7500, - .trtp_ps = 7500, - .refresh_rate_ps = 7800000, - .tfaw_ps = 37500, -}; - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - const char dimm_model[] = "Fixed DDR on board"; - - if ((controller_number == 0) && (dimm_number == 0)) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - struct cpu_type *cpu; - int i; - popts->clk_adjust = 6; - popts->cpo_override = 0x1f; - popts->write_data_delay = 2; - popts->half_strength_driver_enable = 1; - /* Write leveling override */ - popts->wrlvl_en = 1; - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - popts->wrlvl_start = 0x8; - popts->trwt_override = 1; - popts->trwt = 0; - - cpu = gd->arch.cpu; - /* P1014 and it's derivatives support max 16it DDR width */ - if (cpu->soc_ver == SVR_P1014) - popts->data_bus_width = DDR_DATA_BUS_WIDTH_16; - - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; - popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; - } -} - -#endif /* CONFIG_SYS_DDR_RAW_TIMING */ diff --git a/qemu/roms/u-boot/board/freescale/p1010rdb/law.c b/qemu/roms/u-boot/board/freescale/p1010rdb/law.c deleted file mode 100644 index ed41a056c..000000000 --- a/qemu/roms/u-boot/board/freescale/p1010rdb/law.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/qemu/roms/u-boot/board/freescale/p1010rdb/p1010rdb.c b/qemu/roms/u-boot/board/freescale/p1010rdb/p1010rdb.c deleted file mode 100644 index 62caf676c..000000000 --- a/qemu/roms/u-boot/board/freescale/p1010rdb/p1010rdb.c +++ /dev/null @@ -1,564 +0,0 @@ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/io.h> -#include <miiphy.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <fsl_mdio.h> -#include <tsec.h> -#include <mmc.h> -#include <netdev.h> -#include <pci.h> -#include <asm/fsl_serdes.h> -#include <fsl_ifc.h> -#include <asm/fsl_pci.h> -#include <hwconfig.h> -#include <i2c.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define GPIO4_PCIE_RESET_SET 0x08000000 -#define MUX_CPLD_CAN_UART 0x00 -#define MUX_CPLD_TDM 0x01 -#define MUX_CPLD_SPICS0_FLASH 0x00 -#define MUX_CPLD_SPICS0_SLIC 0x02 -#define PMUXCR1_IFC_MASK 0x00ffff00 -#define PMUXCR1_SDHC_MASK 0x00fff000 -#define PMUXCR1_SDHC_ENABLE 0x00555000 - -enum { - MUX_TYPE_IFC, - MUX_TYPE_SDHC, - MUX_TYPE_SPIFLASH, - MUX_TYPE_TDM, - MUX_TYPE_CAN, - MUX_TYPE_CS0_NOR, - MUX_TYPE_CS0_NAND, -}; - -enum { - I2C_READ_BANK, - I2C_READ_PCB_VER, -}; - -static uint sd_ifc_mux; - -struct cpld_data { - u8 cpld_ver; /* cpld revision */ -#if defined(CONFIG_P1010RDB_PA) - u8 pcba_ver; /* pcb revision number */ - u8 twindie_ddr3; - u8 res1[6]; - u8 bank_sel; /* NOR Flash bank */ - u8 res2[5]; - u8 usb2_sel; - u8 res3[1]; - u8 porsw_sel; - u8 tdm_can_sel; - u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */ - u8 por0; /* POR Options */ - u8 por1; /* POR Options */ - u8 por2; /* POR Options */ - u8 por3; /* POR Options */ -#elif defined(CONFIG_P1010RDB_PB) - u8 rom_loc; -#endif -}; - -int board_early_init_f(void) -{ - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR; - - /* Clock configuration to access CPLD using IFC(GPCM) */ - setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); - /* - * Reset PCIe slots via GPIO4 - */ - setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET); - setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET); - - return 0; -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_16M, 1); - - set_tlb(1, flashbase + 0x1000000, - CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel+1, BOOKE_PAGESZ_16M, 1); - return 0; -} - -#ifdef CONFIG_PCI -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} -#endif /* ifdef CONFIG_PCI */ - -int config_board_mux(int ctrl_type) -{ - ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u8 tmp; - -#if defined(CONFIG_P1010RDB_PA) - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); - - switch (ctrl_type) { - case MUX_TYPE_IFC: - i2c_set_bus_num(I2C_PCA9557_BUS_NUM); - tmp = 0xf0; - i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1); - tmp = 0x01; - i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1); - sd_ifc_mux = MUX_TYPE_IFC; - clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); - break; - case MUX_TYPE_SDHC: - i2c_set_bus_num(I2C_PCA9557_BUS_NUM); - tmp = 0xf0; - i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1); - tmp = 0x05; - i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1); - sd_ifc_mux = MUX_TYPE_SDHC; - clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, - PMUXCR1_SDHC_ENABLE); - break; - case MUX_TYPE_SPIFLASH: - out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); - break; - case MUX_TYPE_TDM: - out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); - out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); - break; - case MUX_TYPE_CAN: - out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); - break; - default: - break; - } -#elif defined(CONFIG_P1010RDB_PB) - uint orig_bus = i2c_get_bus_num(); - i2c_set_bus_num(I2C_PCA9557_BUS_NUM); - - switch (ctrl_type) { - case MUX_TYPE_IFC: - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); - clrbits_8(&tmp, 0x04); - i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); - i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - clrbits_8(&tmp, 0x04); - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - sd_ifc_mux = MUX_TYPE_IFC; - clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK); - break; - case MUX_TYPE_SDHC: - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); - setbits_8(&tmp, 0x04); - i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); - i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - clrbits_8(&tmp, 0x04); - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - sd_ifc_mux = MUX_TYPE_SDHC; - clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK, - PMUXCR1_SDHC_ENABLE); - break; - case MUX_TYPE_SPIFLASH: - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); - clrbits_8(&tmp, 0x80); - i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); - i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - clrbits_8(&tmp, 0x80); - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - break; - case MUX_TYPE_TDM: - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); - setbits_8(&tmp, 0x82); - i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); - i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - clrbits_8(&tmp, 0x82); - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - break; - case MUX_TYPE_CAN: - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); - clrbits_8(&tmp, 0x02); - i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); - i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - clrbits_8(&tmp, 0x02); - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - break; - case MUX_TYPE_CS0_NOR: - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); - clrbits_8(&tmp, 0x08); - i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); - i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - clrbits_8(&tmp, 0x08); - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - break; - case MUX_TYPE_CS0_NAND: - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1); - setbits_8(&tmp, 0x08); - i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1); - i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - clrbits_8(&tmp, 0x08); - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1); - break; - default: - break; - } - i2c_set_bus_num(orig_bus); -#endif - return 0; -} - -#ifdef CONFIG_P1010RDB_PB -int i2c_pca9557_read(int type) -{ - u8 val; - - i2c_set_bus_num(I2C_PCA9557_BUS_NUM); - i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1); - - switch (type) { - case I2C_READ_BANK: - val = (val & 0x10) >> 4; - break; - case I2C_READ_PCB_VER: - val = ((val & 0x60) >> 5) + 1; - break; - default: - break; - } - - return val; -} -#endif - -int checkboard(void) -{ - struct cpu_type *cpu; - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); - u8 val; - - cpu = gd->arch.cpu; -#if defined(CONFIG_P1010RDB_PA) - printf("Board: %sRDB-PA, ", cpu->name); -#elif defined(CONFIG_P1010RDB_PB) - printf("Board: %sRDB-PB, ", cpu->name); - i2c_set_bus_num(I2C_PCA9557_BUS_NUM); - i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE); - val = 0x0; /* no polarity inversion */ - i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1); -#endif - -#ifdef CONFIG_SDCARD - /* switch to IFC to read info from CPLD */ - config_board_mux(MUX_TYPE_IFC); -#endif - -#if defined(CONFIG_P1010RDB_PA) - val = (in_8(&cpld_data->pcba_ver) & 0xf); - printf("PCB: v%x.0\n", val); -#elif defined(CONFIG_P1010RDB_PB) - val = in_8(&cpld_data->cpld_ver); - printf("CPLD: v%x.%x, ", val >> 4, val & 0xf); - printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER)); - val = in_8(&cpld_data->rom_loc) & 0xf; - puts("Boot from: "); - switch (val) { - case 0xf: - config_board_mux(MUX_TYPE_CS0_NOR); - printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK)); - break; - case 0xe: - puts("SDHC\n"); - val = 0x60; /* set pca9557 pin input/output */ - i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1); - break; - case 0x5: - config_board_mux(MUX_TYPE_IFC); - config_board_mux(MUX_TYPE_CS0_NAND); - puts("NAND\n"); - break; - case 0x6: - config_board_mux(MUX_TYPE_IFC); - puts("SPI\n"); - break; - default: - puts("unknown\n"); - break; - } -#endif - return 0; -} - -#ifdef CONFIG_TSEC_ENET -int board_eth_init(bd_t *bis) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - struct cpu_type *cpu; - int num = 0; - - cpu = gd->arch.cpu; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - num++; -#endif -#ifdef CONFIG_TSEC3 - /* P1014 and it's derivatives do not support eTSEC3 */ - if (cpu->soc_ver != SVR_P1014) { - SET_STD_TSEC_INFO(tsec_info[num], 3); - num++; - } -#endif - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); - - return pci_eth_init(bis); -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -void fdt_del_flexcan(void *blob) -{ - int nodeoff = 0; - - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "fsl,p1010-flexcan")) >= 0) { - fdt_del_node(blob, nodeoff); - } -} - -void fdt_del_spi_flash(void *blob) -{ - int nodeoff = 0; - - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "spansion,s25sl12801")) >= 0) { - fdt_del_node(blob, nodeoff); - } -} - -void fdt_del_spi_slic(void *blob) -{ - int nodeoff = 0; - - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "zarlink,le88266")) >= 0) { - fdt_del_node(blob, nodeoff); - } -} - -void fdt_del_tdm(void *blob) -{ - int nodeoff = 0; - - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "fsl,starlite-tdm")) >= 0) { - fdt_del_node(blob, nodeoff); - } -} - -void fdt_del_sdhc(void *blob) -{ - int nodeoff = 0; - - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "fsl,esdhc")) >= 0) { - fdt_del_node(blob, nodeoff); - } -} - -void fdt_del_ifc(void *blob) -{ - int nodeoff = 0; - - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "fsl,ifc")) >= 0) { - fdt_del_node(blob, nodeoff); - } -} - -void fdt_disable_uart1(void *blob) -{ - int nodeoff; - - nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550", - CONFIG_SYS_NS16550_COM2); - - if (nodeoff > 0) { - fdt_status_disabled(blob, nodeoff); - } else { - printf("WARNING unable to set status for fsl,ns16550 " - "uart1: %s\n", fdt_strerror(nodeoff)); - } -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - struct cpu_type *cpu; - - cpu = gd->arch.cpu; - - ft_cpu_setup(blob, bd); - - base = getenv_bootm_low(); - size = getenv_bootm_size(); - -#if defined(CONFIG_PCI) - FT_FSL_PCI_SETUP; -#endif - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#if defined(CONFIG_HAS_FSL_DR_USB) - fdt_fixup_dr_usb(blob, bd); -#endif - - /* P1014 and it's derivatives don't support CAN and eTSEC3 */ - if (cpu->soc_ver == SVR_P1014) { - fdt_del_flexcan(blob); - fdt_del_node_and_alias(blob, "ethernet2"); - } - - /* Delete IFC node as IFC pins are multiplexing with SDHC */ - if (sd_ifc_mux != MUX_TYPE_IFC) - fdt_del_ifc(blob); - else - fdt_del_sdhc(blob); - - if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { - fdt_del_tdm(blob); - fdt_del_spi_slic(blob); - } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { - fdt_del_flexcan(blob); - fdt_del_spi_flash(blob); - fdt_disable_uart1(blob); - } else { - /* - * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm" - * explicitly, defaultly spi_cs_sel to spi-flash instead of - * to tdm/slic. - */ - fdt_del_tdm(blob); - fdt_del_flexcan(blob); - fdt_disable_uart1(blob); - } -} -#endif - -#ifdef CONFIG_SDCARD -int board_mmc_init(bd_t *bis) -{ - config_board_mux(MUX_TYPE_SDHC); - return -1; -} -#else -void board_reset(void) -{ - /* mux to IFC to enable CPLD for reset */ - if (sd_ifc_mux != MUX_TYPE_IFC) - config_board_mux(MUX_TYPE_IFC); -} -#endif - - -int misc_init_r(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { - clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM | - MPC85xx_PMUXCR_CAN1_UART | - MPC85xx_PMUXCR_CAN2_TDM | - MPC85xx_PMUXCR_CAN2_UART); - config_board_mux(MUX_TYPE_CAN); - } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { - clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART | - MPC85xx_PMUXCR_CAN1_UART); - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM | - MPC85xx_PMUXCR_CAN1_TDM); - clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO); - setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM); - config_board_mux(MUX_TYPE_TDM); - } else { - /* defaultly spi_cs_sel to flash */ - config_board_mux(MUX_TYPE_SPIFLASH); - } - - if (hwconfig("esdhc")) - config_board_mux(MUX_TYPE_SDHC); - else if (hwconfig("ifc")) - config_board_mux(MUX_TYPE_IFC); - -#ifdef CONFIG_P1010RDB_PB - setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); -#endif - return 0; -} - -static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) -{ - if (argc < 2) - return CMD_RET_USAGE; - if (strcmp(argv[1], "ifc") == 0) - config_board_mux(MUX_TYPE_IFC); - else if (strcmp(argv[1], "sdhc") == 0) - config_board_mux(MUX_TYPE_SDHC); - else - return CMD_RET_USAGE; - return 0; -} - -U_BOOT_CMD( - mux, 2, 0, pin_mux_cmd, - "configure multiplexing pin for IFC/SDHC bus in runtime", - "bus_type (e.g. mux sdhc)" -); diff --git a/qemu/roms/u-boot/board/freescale/p1010rdb/spl.c b/qemu/roms/u-boot/board/freescale/p1010rdb/spl.c deleted file mode 100644 index 11bd9cfcc..000000000 --- a/qemu/roms/u-boot/board/freescale/p1010rdb/spl.c +++ /dev/null @@ -1,108 +0,0 @@ -/* Copyright 2013 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ns16550.h> -#include <malloc.h> -#include <mmc.h> -#include <nand.h> -#include <i2c.h> -#include <fsl_esdhc.h> -#include <spi_flash.h> - -DECLARE_GLOBAL_DATA_PTR; - -phys_size_t get_effective_memsize(void) -{ - return CONFIG_SYS_L2_SIZE; -} - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR; - - console_init_f(); - - /* Clock configuration to access CPLD using IFC(GPCM) */ - setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); - -#ifdef CONFIG_P1010RDB_PB - setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); -#endif - - /* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - plat_ratio >>= 1; - gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; - - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - gd->bus_clk / 16 / CONFIG_BAUDRATE); - -#ifdef CONFIG_SPL_MMC_BOOT - puts("\nSD boot...\n"); -#elif defined(CONFIG_SPL_SPI_BOOT) - puts("\nSPI Flash boot...\n"); -#endif - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *)CONFIG_SPL_GD_ADDR; - bd_t *bd; - - memset(gd, 0, sizeof(gd_t)); - bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); - memset(bd, 0, sizeof(bd_t)); - gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; - bd->bi_memsize = CONFIG_SYS_L2_SIZE; - - probecpu(); - get_clocks(); - mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, - CONFIG_SPL_RELOC_MALLOC_SIZE); - -#ifndef CONFIG_SPL_NAND_BOOT - env_init(); -#endif -#ifdef CONFIG_SPL_MMC_BOOT - mmc_initialize(bd); -#endif - - /* relocate environment function pointers etc. */ -#ifdef CONFIG_SPL_NAND_BOOT - nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)CONFIG_ENV_ADDR); - gd->env_addr = (ulong)(CONFIG_ENV_ADDR); - gd->env_valid = 1; -#else - env_relocate(); -#endif - - i2c_init_all(); - - gd->ram_size = initdram(0); -#ifdef CONFIG_SPL_NAND_BOOT - puts("\nTertiary program loader running in sram..."); -#else - puts("\nSecond program loader running in sram..."); -#endif - -#ifdef CONFIG_SPL_MMC_BOOT - mmc_boot(); -#elif defined(CONFIG_SPL_SPI_BOOT) - spi_boot(); -#elif defined(CONFIG_SPL_NAND_BOOT) - nand_boot(); -#endif -} diff --git a/qemu/roms/u-boot/board/freescale/p1010rdb/spl_minimal.c b/qemu/roms/u-boot/board/freescale/p1010rdb/spl_minimal.c deleted file mode 100644 index 607957003..000000000 --- a/qemu/roms/u-boot/board/freescale/p1010rdb/spl_minimal.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <mpc85xx.h> -#include <asm/io.h> -#include <ns16550.h> -#include <nand.h> -#include <asm/mmu.h> -#include <asm/immap_85xx.h> -#include <fsl_ddr_sdram.h> -#include <asm/fsl_law.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - -#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) - set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); - set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); -#endif - - /* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - plat_ratio >>= 1; - gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; - - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - gd->bus_clk / 16 / CONFIG_BAUDRATE); - - puts("\nNAND boot... "); - - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - - relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - puts("\nSecond program loader running in sram..."); - nand_boot(); -} - -void putc(char c) -{ - if (c == '\n') - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); - - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); -} - -void puts(const char *str) -{ - while (*str) - putc(*str++); -} diff --git a/qemu/roms/u-boot/board/freescale/p1010rdb/tlb.c b/qemu/roms/u-boot/board/freescale/p1010rdb/tlb.c deleted file mode 100644 index af40f979d..000000000 --- a/qemu/roms/u-boot/board/freescale/p1010rdb/tlb.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SPL_NAND_BOOT - SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_4K, 1), -#endif - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - -#ifndef CONFIG_SPL_BUILD - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_16M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, - CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 3, BOOKE_PAGESZ_16M, 1), - -#ifdef CONFIG_PCI - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256K, 1), -#endif -#endif - - /* *I*G - Board CPLD */ - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256K, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_1M, 1), - -#if defined(CONFIG_SYS_RAMBOOT) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_1G, 1), -#endif - -#ifdef CONFIG_SYS_INIT_L2_ADDR - /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, - 0, 11, BOOKE_PAGESZ_256K, 1) -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); |