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-rw-r--r--qemu/roms/u-boot/board/freescale/m5275evb/Makefile8
-rw-r--r--qemu/roms/u-boot/board/freescale/m5275evb/config.mk9
-rw-r--r--qemu/roms/u-boot/board/freescale/m5275evb/m5275evb.c100
-rw-r--r--qemu/roms/u-boot/board/freescale/m5275evb/u-boot.lds85
4 files changed, 202 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/board/freescale/m5275evb/Makefile b/qemu/roms/u-boot/board/freescale/m5275evb/Makefile
new file mode 100644
index 000000000..d285c1459
--- /dev/null
+++ b/qemu/roms/u-boot/board/freescale/m5275evb/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = m5275evb.o
diff --git a/qemu/roms/u-boot/board/freescale/m5275evb/config.mk b/qemu/roms/u-boot/board/freescale/m5275evb/config.mk
new file mode 100644
index 000000000..1af25e158
--- /dev/null
+++ b/qemu/roms/u-boot/board/freescale/m5275evb/config.mk
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CONFIG_SYS_TEXT_BASE = 0xffe00000
diff --git a/qemu/roms/u-boot/board/freescale/m5275evb/m5275evb.c b/qemu/roms/u-boot/board/freescale/m5275evb/m5275evb.c
new file mode 100644
index 000000000..16083d1bc
--- /dev/null
+++ b/qemu/roms/u-boot/board/freescale/m5275evb/m5275evb.c
@@ -0,0 +1,100 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#define PERIOD 13 /* system bus period in ns */
+#define SDRAM_TREFI 7800 /* in ns */
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale MCF5275 EVB\n");
+ return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+ sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
+ gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
+
+ /* Enable SDRAM */
+ out_be16(&gpio_reg->par_sdram, 0x3FF);
+
+ /* Set up chip select */
+ out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
+ out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V);
+
+ /* Set up timing */
+ out_be32(&sdp->sdcfg1, 0x83711630);
+ out_be32(&sdp->sdcfg2, 0x46770000);
+
+ /* Enable clock */
+ out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE);
+
+ /* Set precharge */
+ setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
+
+ /* Dummy write to start SDRAM */
+ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+ /* Send LEMR */
+ setbits_be32(&sdp->sdmr,
+ MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) |
+ MCF_SDRAMC_SDMR_CMD);
+ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+ /* Send LMR */
+ out_be32(&sdp->sdmr, 0x058d0000);
+ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+ /* Stop sending commands */
+ clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
+
+ /* Set precharge */
+ setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
+ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+ /* Stop manual precharge, send 2 IREF */
+ clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
+ setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
+ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+
+ out_be32(&sdp->sdmr, 0x018d0000);
+ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+ /* Stop sending commands */
+ clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
+ clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN);
+
+ /* Turn on auto refresh, lock SDMR */
+ out_be32(&sdp->sdcr,
+ MCF_SDRAMC_SDCR_CKE
+ | MCF_SDRAMC_SDCR_REF
+ | MCF_SDRAMC_SDCR_MUX(1)
+ /* 1 added to round up */
+ | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
+ | MCF_SDRAMC_SDCR_DQS_OE(0x3));
+
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+};
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
diff --git a/qemu/roms/u-boot/board/freescale/m5275evb/u-boot.lds b/qemu/roms/u-boot/board/freescale/m5275evb/u-boot.lds
new file mode 100644
index 000000000..3112cbe4e
--- /dev/null
+++ b/qemu/roms/u-boot/board/freescale/m5275evb/u-boot.lds
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ .text :
+ {
+ arch/m68k/cpu/mcf52x2/start.o (.text*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}