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-rw-r--r--qemu/roms/u-boot/board/esd/ocrtc/Makefile8
-rw-r--r--qemu/roms/u-boot/board/esd/ocrtc/cmd_ocrtc.c68
-rw-r--r--qemu/roms/u-boot/board/esd/ocrtc/flash.c140
-rw-r--r--qemu/roms/u-boot/board/esd/ocrtc/ocrtc.c78
-rw-r--r--qemu/roms/u-boot/board/esd/ocrtc/ocrtc.h28
5 files changed, 322 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/board/esd/ocrtc/Makefile b/qemu/roms/u-boot/board/esd/ocrtc/Makefile
new file mode 100644
index 000000000..44b7d5d07
--- /dev/null
+++ b/qemu/roms/u-boot/board/esd/ocrtc/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = ocrtc.o flash.o ../common/misc.o cmd_ocrtc.o
diff --git a/qemu/roms/u-boot/board/esd/ocrtc/cmd_ocrtc.c b/qemu/roms/u-boot/board/esd/ocrtc/cmd_ocrtc.c
new file mode 100644
index 000000000..6dcbd8b24
--- /dev/null
+++ b/qemu/roms/u-boot/board/esd/ocrtc/cmd_ocrtc.c
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <pci_ids.h>
+#include <asm/4xx_pci.h>
+
+
+#if defined(CONFIG_CMD_BSP)
+
+/*
+ * Set device number on pci board
+ */
+int do_setdevice(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int idx = 1; /* start at 1 (skip device 0) */
+ pci_dev_t bdf = 0;
+ u32 addr;
+
+ while (bdf >= 0) {
+ if ((bdf = pci_find_device(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_405GP, idx++)) < 0) {
+ break;
+ }
+ printf("Found device nr %d at %x!\n", idx-1, bdf);
+ pci_read_config_dword(bdf, PCI_BASE_ADDRESS_1, &addr);
+ addr &= ~0xf;
+ *(u32 *)addr = (bdf & 0x0000f800) >> 11;
+ printf("Wrote %x at %x!\n", (bdf & 0x0000f800) >> 11, addr);
+ }
+
+ return 0;
+}
+U_BOOT_CMD(
+ setdevice, 1, 1, do_setdevice,
+ "Set device number on pci adapter boards",
+ ""
+);
+
+
+/*
+ * Get device number on pci board
+ */
+int do_getdevice(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ u32 device;
+ char str[32];
+
+ device = *(u32 *)0x0;
+ device = 0x16 - device; /* calculate vxworks bp slot id */
+ sprintf(str, "%d", device);
+ setenv("slot", str);
+ printf("Variabel slot set to %x\n", device);
+
+ return 0;
+}
+U_BOOT_CMD(
+ getdevice, 1, 1, do_getdevice,
+ "Get device number and set slot env variable",
+ ""
+);
+
+#endif
diff --git a/qemu/roms/u-boot/board/esd/ocrtc/flash.c b/qemu/roms/u-boot/board/esd/ocrtc/flash.c
new file mode 100644
index 000000000..279746e57
--- /dev/null
+++ b/qemu/roms/u-boot/board/esd/ocrtc/flash.c
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0, size_b1;
+ int i;
+ uint pbcr;
+ unsigned long base_b0, base_b1;
+ int size_val = 0;
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ base_b0 = FLASH_BASE0_PRELIM;
+ size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 << 20);
+ }
+
+ base_b1 = FLASH_BASE1_PRELIM;
+ size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+ /* Re-do sizing to get full correct info */
+
+ if (size_b1) {
+ mtdcr (EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr (EBC0_CFGDATA);
+ mtdcr (EBC0_CFGADDR, PB0CR);
+ base_b1 = -size_b1;
+ switch (size_b1) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | base_b1 | (size_val << 17);
+ mtdcr (EBC0_CFGDATA, pbcr);
+ /* printf("PB1CR = %x\n", pbcr); */
+ }
+
+ if (size_b0) {
+ mtdcr (EBC0_CFGADDR, PB1CR);
+ pbcr = mfdcr (EBC0_CFGDATA);
+ mtdcr (EBC0_CFGADDR, PB1CR);
+ base_b0 = base_b1 - size_b0;
+ switch (size_b1) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+ mtdcr (EBC0_CFGDATA, pbcr);
+ /* printf("PB0CR = %x\n", pbcr); */
+ }
+
+ size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+ flash_get_offsets (base_b0, &flash_info[0]);
+
+ /* monitor protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ base_b0 + size_b0 - monitor_flash_len,
+ base_b0 + size_b0 - 1, &flash_info[0]);
+
+ if (size_b1) {
+ /* Re-do sizing to get full correct info */
+ size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+ flash_get_offsets (base_b1, &flash_info[1]);
+
+ /* monitor protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ base_b1 + size_b1 - monitor_flash_len,
+ base_b1 + size_b1 - 1, &flash_info[1]);
+ /* monitor protection OFF by default (one is enough) */
+ flash_protect (FLAG_PROTECT_CLEAR,
+ base_b0 + size_b0 - monitor_flash_len,
+ base_b0 + size_b0 - 1, &flash_info[0]);
+ } else {
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[1].sector_count = -1;
+ }
+
+ flash_info[0].size = size_b0;
+ flash_info[1].size = size_b1;
+
+ return (size_b0 + size_b1);
+}
diff --git a/qemu/roms/u-boot/board/esd/ocrtc/ocrtc.c b/qemu/roms/u-boot/board/esd/ocrtc/ocrtc.c
new file mode 100644
index 000000000..b81596135
--- /dev/null
+++ b/qemu/roms/u-boot/board/esd/ocrtc/ocrtc.c
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include "ocrtc.h"
+#include <asm/processor.h>
+#include <i2c.h>
+#include <command.h>
+
+
+extern void lxt971_no_sleep(void);
+
+
+int board_early_init_f (void)
+{
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
+ mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */
+ mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: clear EBTC -> high-Z ebc signals between
+ * transfers, set device-paced timeout to 256 cycles
+ */
+ mtebc (EBC0_CFG, 0x20400000);
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof (str));
+
+ puts ("Board: ");
+
+ if (i == -1) {
+#ifdef CONFIG_OCRTC
+ puts ("### No HW ID - assuming OCRTC");
+#endif
+#ifdef CONFIG_ORSG
+ puts ("### No HW ID - assuming ORSG");
+#endif
+ } else {
+ puts (str);
+ }
+
+ putc ('\n');
+
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+
+ return (0);
+}
diff --git a/qemu/roms/u-boot/board/esd/ocrtc/ocrtc.h b/qemu/roms/u-boot/board/esd/ocrtc/ocrtc.h
new file mode 100644
index 000000000..029e27efa
--- /dev/null
+++ b/qemu/roms/u-boot/board/esd/ocrtc/ocrtc.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ * Start Address Length
+ * +-----------------------+ 0x4000_0000 Start of Flash -----------------
+ * | MON8xx code | 0x4000_0100 Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused) |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses | 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) | 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address | 0x04
+ * +-----------------------+ 0x4001_FFC0 ^
+ * | Hardware Information | 0x40 | MON8xx
+ * +=======================+ 0x4002_0000 (sector border) -----------------
+ * | Autostart Header | | Applications
+ * | ... | v
+ *
+ *****************************************************************************/