diff options
Diffstat (limited to 'qemu/roms/u-boot/board/esd/du405')
| -rw-r--r-- | qemu/roms/u-boot/board/esd/du405/Makefile | 8 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/esd/du405/du405.c | 187 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/esd/du405/du405.h | 28 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/esd/du405/flash.c | 107 | ||||
| -rw-r--r-- | qemu/roms/u-boot/board/esd/du405/fpgadata.c | 1405 |
5 files changed, 1735 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/board/esd/du405/Makefile b/qemu/roms/u-boot/board/esd/du405/Makefile new file mode 100644 index 000000000..7914eab35 --- /dev/null +++ b/qemu/roms/u-boot/board/esd/du405/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = du405.o flash.o ../common/misc.o diff --git a/qemu/roms/u-boot/board/esd/du405/du405.c b/qemu/roms/u-boot/board/esd/du405/du405.c new file mode 100644 index 000000000..8f5f4d02a --- /dev/null +++ b/qemu/roms/u-boot/board/esd/du405/du405.c @@ -0,0 +1,187 @@ +/* + * (C) Copyright 2000, 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include "du405.h" +#include <asm/processor.h> +#include <asm/ppc4xx.h> +#include <asm/ppc4xx-i2c.h> +#include <command.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern void lxt971_no_sleep(void); + + +#if 0 +#define FPGA_DEBUG +#endif + +#if 0 +#define FPGA_DEBUG2 +#endif + +/* fpga configuration data - generated by bin2cc */ +const unsigned char fpgadata[] = { +#include "fpgadata.c" +}; + +/* + * include common fpga code (for esd boards) + */ +#include "../common/fpga.c" + + +int board_early_init_f (void) +{ + int index, len, i; + int status; + +#ifdef FPGA_DEBUG + /* set up serial port with default baudrate */ + (void) get_clocks (); + gd->baudrate = CONFIG_BAUDRATE; + serial_init (); + console_init_f (); +#endif + + /* + * Boot onboard FPGA + */ + status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); + if (status != 0) { + /* booting FPGA failed */ +#ifndef FPGA_DEBUG + /* set up serial port with default baudrate */ + (void) get_clocks (); + gd->baudrate = CONFIG_BAUDRATE; + serial_init (); + console_init_f (); +#endif + printf ("\nFPGA: Booting failed "); + switch (status) { + case ERROR_FPGA_PRG_INIT_LOW: + printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_INIT_HIGH: + printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + break; + case ERROR_FPGA_PRG_DONE: + printf ("(Timeout: DONE not high after programming FPGA)\n "); + break; + } + + /* display infos on fpgaimage */ + index = 15; + for (i = 0; i < 4; i++) { + len = fpgadata[index]; + printf ("FPGA: %s\n", &(fpgadata[index + 1])); + index += len + 3; + } + putc ('\n'); + /* delayed reboot */ + for (i = 20; i > 0; i--) { + printf ("Rebooting in %2d seconds \r", i); + for (index = 0; index < 1000; index++) + udelay (1000); + } + putc ('\n'); + do_reset (NULL, 0, 0, NULL); + } + + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) DUART_A; active high; level sensitive + * IRQ 27 (EXT IRQ 2) DUART_B; active high; level sensitive + * IRQ 28 (EXT IRQ 3) unused; active low; level sensitive + * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive + * IRQ 30 (EXT IRQ 5) unused; active low; level sensitive + * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive + */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFFB1); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + + /* + * EBC Configuration Register: set ready timeout to 100 us + */ + mtebc (EBC0_CFG, 0xb8400000); + + return 0; +} + + +int misc_init_r (void) +{ + unsigned long CPC0_CR0Reg; + + /* + * Setup UART1 handshaking: use CTS instead of DSR + */ + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); + + return (0); +} + + +/* + * Check Board Identity: + */ +int checkboard (void) +{ + int index; + int len; + char str[64]; + int i = getenv_f("serial#", str, sizeof (str)); + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming DU405"); + } else { + puts (str); + } + + puts ("\nFPGA: "); + + /* display infos on fpgaimage */ + index = 15; + for (i = 0; i < 4; i++) { + len = fpgadata[index]; + printf ("%s ", &(fpgadata[index + 1])); + index += len + 3; + } + + putc ('\n'); + + /* + * Reset external DUART via FPGA + */ + out_8((void *)FPGA_MODE_REG, 0xff); /* reset high active */ + out_8((void *)FPGA_MODE_REG, 0x00); /* low again */ + + return 0; +} + +void reset_phy(void) +{ +#if defined(CONFIG_LXT971_NO_SLEEP) + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); +#endif +} diff --git a/qemu/roms/u-boot/board/esd/du405/du405.h b/qemu/roms/u-boot/board/esd/du405/du405.h new file mode 100644 index 000000000..292f19630 --- /dev/null +++ b/qemu/roms/u-boot/board/esd/du405/du405.h @@ -0,0 +1,28 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/**************************************************************************** + * FLASH Memory Map as used by TQ Monitor: + * + * Start Address Length + * +-----------------------+ 0x4000_0000 Start of Flash ----------------- + * | MON8xx code | 0x4000_0100 Reset Vector + * +-----------------------+ 0x400?_???? + * | (unused) | + * +-----------------------+ 0x4001_FF00 + * | Ethernet Addresses | 0x78 + * +-----------------------+ 0x4001_FF78 + * | (Reserved for MON8xx) | 0x44 + * +-----------------------+ 0x4001_FFBC + * | Lock Address | 0x04 + * +-----------------------+ 0x4001_FFC0 ^ + * | Hardware Information | 0x40 | MON8xx + * +=======================+ 0x4002_0000 (sector border) ----------------- + * | Autostart Header | | Applications + * | ... | v + * + *****************************************************************************/ diff --git a/qemu/roms/u-boot/board/esd/du405/flash.c b/qemu/roms/u-boot/board/esd/du405/flash.c new file mode 100644 index 000000000..5650e5eaf --- /dev/null +++ b/qemu/roms/u-boot/board/esd/du405/flash.c @@ -0,0 +1,107 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/ppc4xx.h> +#include <asm/processor.h> + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long * addr, flash_info_t * info); +static void flash_get_offsets (ulong base, flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0, size_b1; + int i; + uint pbcr; + unsigned long base_b0, base_b1; + + /* Init: no FLASHes known */ + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here - FIXME XXX */ + + base_b0 = FLASH_BASE0_PRELIM; + size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 << 20); + } + + base_b1 = FLASH_BASE1_PRELIM; + size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); + + /* Re-do sizing to get full correct info */ + + if (size_b1) { + mtdcr (EBC0_CFGADDR, PB0CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB0CR); + base_b1 = -size_b1; + pbcr = (pbcr & 0x0001ffff) | base_b1 | + (((size_b1 / 1024 / 1024) - 1) << 17); + mtdcr (EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ + } + + if (size_b0) { + mtdcr (EBC0_CFGADDR, PB1CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB1CR); + base_b0 = base_b1 - size_b0; + pbcr = (pbcr & 0x0001ffff) | base_b0 | + (((size_b0 / 1024 / 1024) - 1) << 17); + mtdcr (EBC0_CFGDATA, pbcr); + /* printf("PB0CR = %x\n", pbcr); */ + } + + size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); + + flash_get_offsets (base_b0, &flash_info[0]); + + /* monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + base_b0 + size_b0 - monitor_flash_len, + base_b0 + size_b0 - 1, &flash_info[0]); + + if (size_b1) { + /* Re-do sizing to get full correct info */ + size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); + + flash_get_offsets (base_b1, &flash_info[1]); + + /* monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + base_b1 + size_b1 - monitor_flash_len, + base_b1 + size_b1 - 1, &flash_info[1]); + /* monitor protection OFF by default (one is enough) */ + flash_protect (FLAG_PROTECT_CLEAR, + base_b0 + size_b0 - monitor_flash_len, + base_b0 + size_b0 - 1, &flash_info[0]); + } else { + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + } + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + + return (size_b0 + size_b1); +} diff --git a/qemu/roms/u-boot/board/esd/du405/fpgadata.c b/qemu/roms/u-boot/board/esd/du405/fpgadata.c new file mode 100644 index 000000000..262f2ca22 --- /dev/null +++ b/qemu/roms/u-boot/board/esd/du405/fpgadata.c @@ -0,0 +1,1405 @@ +0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, +0x0f, 0xf0, 0x00, 0x00, 0x01, 0x61, 0x00, 0x0d, +0x64, 0x75, 0x72, 0x61, 0x67, 0x34, 0x30, 0x35, +0x2e, 0x6e, 0x63, 0x64, 0x00, 0x62, 0x00, 0x0b, +0x73, 0x32, 0x30, 0x78, 0x6c, 0x74, 0x71, 0x31, +0x34, 0x34, 0x00, 0x63, 0x00, 0x0b, 0x32, 0x30, +0x30, 0x32, 0x2f, 0x30, 0x32, 0x2f, 0x32, 0x31, +0x00, 0x64, 0x00, 0x09, 0x31, 0x32, 0x3a, 0x35, +0x31, 0x3a, 0x30, 0x38, 0x00, 0x65, 0xe2, 0x01, +0x00, 0x00, 0x2b, 0x98, 0xff, 0x30, 0xe6, 0xe5, +0xe5, 0x02, 0x04, 0x01, 0xe6, 0x04, 0x01, 0x0d, +0x04, 0x04, 0x02, 0x01, 0x04, 0x04, 0x03, 0x07, +0x01, 0x03, 0x01, 0x04, 0x11, 0x01, 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