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-rw-r--r--qemu/roms/u-boot/board/denx/m28evk/Makefile12
-rw-r--r--qemu/roms/u-boot/board/denx/m28evk/README13
-rw-r--r--qemu/roms/u-boot/board/denx/m28evk/m28evk.c173
-rw-r--r--qemu/roms/u-boot/board/denx/m28evk/spl_boot.c206
-rw-r--r--qemu/roms/u-boot/board/denx/m53evk/Makefile8
-rw-r--r--qemu/roms/u-boot/board/denx/m53evk/imximage.cfg92
-rw-r--r--qemu/roms/u-boot/board/denx/m53evk/m53evk.c402
7 files changed, 0 insertions, 906 deletions
diff --git a/qemu/roms/u-boot/board/denx/m28evk/Makefile b/qemu/roms/u-boot/board/denx/m28evk/Makefile
deleted file mode 100644
index 5e890b1ea..000000000
--- a/qemu/roms/u-boot/board/denx/m28evk/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifndef CONFIG_SPL_BUILD
-obj-y := m28evk.o
-else
-obj-y := spl_boot.o
-endif
diff --git a/qemu/roms/u-boot/board/denx/m28evk/README b/qemu/roms/u-boot/board/denx/m28evk/README
deleted file mode 100644
index cb3ae20f8..000000000
--- a/qemu/roms/u-boot/board/denx/m28evk/README
+++ /dev/null
@@ -1,13 +0,0 @@
-DENX M28EVK
-===========
-
-Files of the M28/M28EVK port
-----------------------------
-
-arch/arm/cpu/arm926ejs/mxs/ - The CPU support code for the Freescale i.MX28
-arch/arm/include/asm/arch-mxs/ - Header files for the Freescale i.MX28
-board/denx/m28evk/ - M28EVK board specific files
-include/configs/m28evk.h - M28EVK configuration file
-
-Follow the instructions from doc/README.mxs to generate a bootable SD card or to
-boot from NAND flash.
diff --git a/qemu/roms/u-boot/board/denx/m28evk/m28evk.c b/qemu/roms/u-boot/board/denx/m28evk/m28evk.c
deleted file mode 100644
index 33d38cfc5..000000000
--- a/qemu/roms/u-boot/board/denx/m28evk/m28evk.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * DENX M28 module
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux-mx28.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <linux/mii.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <errno.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Functions
- */
-int board_early_init_f(void)
-{
- /* IO0 clock at 480MHz */
- mxs_set_ioclk(MXC_IOCLK0, 480000);
- /* IO1 clock at 480MHz */
- mxs_set_ioclk(MXC_IOCLK1, 480000);
-
- /* SSP0 clock at 96MHz */
- mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
- /* SSP2 clock at 160MHz */
- mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
-
-#ifdef CONFIG_CMD_USB
- mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
- mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 |
- MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
- gpio_direction_output(MX28_PAD_AUART3_TX__GPIO_3_13, 0);
-
- mxs_iomux_setup_pad(MX28_PAD_AUART3_RX__GPIO_3_12 |
- MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
- gpio_direction_output(MX28_PAD_AUART3_RX__GPIO_3_12, 0);
-#endif
-
- return 0;
-}
-
-int board_init(void)
-{
- /* Adress of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- return 0;
-}
-
-int dram_init(void)
-{
- return mxs_dram_init();
-}
-
-#ifdef CONFIG_CMD_MMC
-static int m28_mmc_wp(int id)
-{
- if (id != 0) {
- printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
- return 1;
- }
-
- return gpio_get_value(MX28_PAD_AUART2_CTS__GPIO_3_10);
-}
-
-int board_mmc_init(bd_t *bis)
-{
- /* Configure WP as input. */
- gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10);
- /* Turn on the power to the card. */
- gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
-
- return mxsmmc_initialize(bis, 0, m28_mmc_wp, NULL);
-}
-#endif
-
-#ifdef CONFIG_CMD_NET
-
-#define MII_OPMODE_STRAP_OVERRIDE 0x16
-#define MII_PHY_CTRL1 0x1e
-#define MII_PHY_CTRL2 0x1f
-
-int fecmxc_mii_postcall(int phy)
-{
-#if defined(CONFIG_DENX_M28_V11) || defined(CONFIG_DENX_M28_V10)
- /* KZ8031 PHY on old boards. */
- const uint32_t freq = 0x0080;
-#else
- /* KZ8021 PHY on new boards. */
- const uint32_t freq = 0x0000;
-#endif
-
- miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
- miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
- if (phy == 3)
- miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8100 | freq);
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- struct mxs_clkctrl_regs *clkctrl_regs =
- (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
- struct eth_device *dev;
- int ret;
-
- ret = cpu_eth_init(bis);
- if (ret)
- return ret;
-
- clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
- CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
- CLKCTRL_ENET_TIME_SEL_RMII_CLK);
-
-#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
- /* Reset the new PHY */
- gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0);
- udelay(10000);
- gpio_set_value(MX28_PAD_AUART2_RTS__GPIO_3_11, 1);
- udelay(10000);
-#endif
-
- ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
- if (ret) {
- printf("FEC MXS: Unable to init FEC0\n");
- return ret;
- }
-
- ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
- if (ret) {
- printf("FEC MXS: Unable to init FEC1\n");
- return ret;
- }
-
- dev = eth_get_dev_by_name("FEC0");
- if (!dev) {
- printf("FEC MXS: Unable to get FEC0 device entry\n");
- return -EINVAL;
- }
-
- ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
- if (ret) {
- printf("FEC MXS: Unable to register FEC0 mii postcall\n");
- return ret;
- }
-
- dev = eth_get_dev_by_name("FEC1");
- if (!dev) {
- printf("FEC MXS: Unable to get FEC1 device entry\n");
- return -EINVAL;
- }
-
- ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
- if (ret) {
- printf("FEC MXS: Unable to register FEC1 mii postcall\n");
- return ret;
- }
-
- return ret;
-}
-
-#endif
diff --git a/qemu/roms/u-boot/board/denx/m28evk/spl_boot.c b/qemu/roms/u-boot/board/denx/m28evk/spl_boot.c
deleted file mode 100644
index 5a1010e59..000000000
--- a/qemu/roms/u-boot/board/denx/m28evk/spl_boot.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * DENX M28 Boot setup
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include <asm/arch/iomux-mx28.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-
-#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
-#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
-#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
-#define MUX_CONFIG_GPMI (MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
-#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
-
-const iomux_cfg_t iomux_setup[] = {
- /* LED */
- MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED,
-
- /* framebuffer */
- MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
- MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
- MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
-
- /* UART1 */
-#ifdef CONFIG_DENX_M28_V10
- MX28_PAD_AUART0_CTS__DUART_RX,
- MX28_PAD_AUART0_RTS__DUART_TX,
-#else
- MX28_PAD_PWM0__DUART_RX,
- MX28_PAD_PWM1__DUART_TX,
-#endif
- MX28_PAD_AUART0_TX__DUART_RTS,
- MX28_PAD_AUART0_RX__DUART_CTS,
-
- /* UART2 */
- MX28_PAD_AUART1_RX__AUART1_RX,
- MX28_PAD_AUART1_TX__AUART1_TX,
- MX28_PAD_AUART1_RTS__AUART1_RTS,
- MX28_PAD_AUART1_CTS__AUART1_CTS,
-
- /* CAN */
- MX28_PAD_GPMI_RDY2__CAN0_TX,
- MX28_PAD_GPMI_RDY3__CAN0_RX,
-
- /* TSC2007 */
- MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MUX_CONFIG_TSC,
-
- /* MMC0 */
- MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
- MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
- (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
- MX28_PAD_SSP0_SCK__SSP0_SCK |
- (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
- MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0 |
- (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), /* Power */
- MX28_PAD_AUART2_CTS__GPIO_3_10, /* WP */
-
- /* GPMI NAND */
- MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_RDN__GPMI_RDN |
- (MXS_PAD_1V8 | MXS_PAD_8MA | MXS_PAD_PULLUP),
- MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
- MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
-
- /* FEC Ethernet */
- MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
- MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
-
- MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
- MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
-#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
- MX28_PAD_AUART2_RTS__GPIO_3_11, /* PHY reset */
-#endif
-
- /* I2C */
- MX28_PAD_I2C0_SCL__I2C0_SCL,
- MX28_PAD_I2C0_SDA__I2C0_SDA,
-
- /* EMI */
- MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
-
- MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
- MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
-
- /* SPI2 (for flash) */
- MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
- MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
- MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
- MX28_PAD_SSP2_SS0__SSP2_D3 |
- (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
-};
-
-void board_init_ll(const uint32_t arg, const uint32_t *resptr)
-{
- mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
-}
diff --git a/qemu/roms/u-boot/board/denx/m53evk/Makefile b/qemu/roms/u-boot/board/denx/m53evk/Makefile
deleted file mode 100644
index 19b8977ae..000000000
--- a/qemu/roms/u-boot/board/denx/m53evk/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# DENX M53EVK
-# Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := m53evk.o
diff --git a/qemu/roms/u-boot/board/denx/m53evk/imximage.cfg b/qemu/roms/u-boot/board/denx/m53evk/imximage.cfg
deleted file mode 100644
index 4cd002c87..000000000
--- a/qemu/roms/u-boot/board/denx/m53evk/imximage.cfg
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * DENX M53 DRAM init values
- * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Refer docs/README.imxmage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-#include <asm/imx-common/imximage.cfg>
-
-/* image version */
-IMAGE_VERSION 2
-
-
-/* Boot Offset 0x400, valid for both SD and NAND boot. */
-BOOT_OFFSET FLASH_OFFSET_STANDARD
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */
-DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */
-DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */
-DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */
-
-DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */
-DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */
-DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */
-
-DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */
-DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */
-DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */
-
-DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS */
-DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1 */
-DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */
-
-DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS */
-DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0 */
-DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */
-
-DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK_0 */
-DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK_1 */
-
-DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS */
-DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS */
-DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDDS */
-DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */
-
-DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */
-DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */
-
-/* ESDCTL */
-DATA 4 0x63fd9088 0x32383535
-DATA 4 0x63fd9090 0x40383538
-DATA 4 0x63fd907c 0x0136014d
-DATA 4 0x63fd9080 0x01510141
-
-DATA 4 0x63fd9018 0x00011740
-DATA 4 0x63fd9000 0xc3190000
-DATA 4 0x63fd900c 0x555952e3
-DATA 4 0x63fd9010 0xb68e8b63
-DATA 4 0x63fd9014 0x01ff00db
-DATA 4 0x63fd902c 0x000026d2
-DATA 4 0x63fd9030 0x009f0e21
-DATA 4 0x63fd9008 0x12273030
-DATA 4 0x63fd9004 0x0002002d
-DATA 4 0x63fd901c 0x00008032
-DATA 4 0x63fd901c 0x00008033
-DATA 4 0x63fd901c 0x00028031
-DATA 4 0x63fd901c 0x092080b0
-DATA 4 0x63fd901c 0x04008040
-DATA 4 0x63fd901c 0x0000803a
-DATA 4 0x63fd901c 0x0000803b
-DATA 4 0x63fd901c 0x00028039
-DATA 4 0x63fd901c 0x09208138
-DATA 4 0x63fd901c 0x04008048
-DATA 4 0x63fd9020 0x00001800
-DATA 4 0x63fd9040 0x04b80003
-DATA 4 0x63fd9058 0x00022227
-DATA 4 0x63fd901c 0x00000000
diff --git a/qemu/roms/u-boot/board/denx/m53evk/m53evk.c b/qemu/roms/u-boot/board/denx/m53evk/m53evk.c
deleted file mode 100644
index 74f95011a..000000000
--- a/qemu/roms/u-boot/board/denx/m53evk/m53evk.c
+++ /dev/null
@@ -1,402 +0,0 @@
-/*
- * DENX M53 module
- *
- * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/iomux-mx53.h>
-#include <asm/imx-common/mx5_video.h>
-#include <asm/arch/spl.h>
-#include <asm/errno.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <spl.h>
-#include <fsl_esdhc.h>
-#include <asm/gpio.h>
-#include <usb/ehci-fsl.h>
-#include <linux/fb.h>
-#include <ipu_pixfmt.h>
-
-/* Special MXCFB sync flags are here. */
-#include "../drivers/video/mxcfb.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static uint32_t mx53_dram_size[2];
-
-phys_size_t get_effective_memsize(void)
-{
- /*
- * WARNING: We must override get_effective_memsize() function here
- * to report only the size of the first DRAM bank. This is to make
- * U-Boot relocator place U-Boot into valid memory, that is, at the
- * end of the first DRAM bank. If we did not override this function
- * like so, U-Boot would be placed at the address of the first DRAM
- * bank + total DRAM size - sizeof(uboot), which in the setup where
- * each DRAM bank contains 512MiB of DRAM would result in placing
- * U-Boot into invalid memory area close to the end of the first
- * DRAM bank.
- */
- return mx53_dram_size[0];
-}
-
-int dram_init(void)
-{
- mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
- mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
-
- gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
-
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = mx53_dram_size[0];
-
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = mx53_dram_size[1];
-}
-
-static void setup_iomux_uart(void)
-{
- static const iomux_v3_cfg_t uart_pads[] = {
- MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
- MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
- };
-
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-}
-
-#ifdef CONFIG_USB_EHCI_MX5
-int board_ehci_hcd_init(int port)
-{
- if (port == 0) {
- /* USB OTG PWRON */
- imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
- gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
-
- /* USB OTG Over Current */
- imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13);
- } else if (port == 1) {
- /* USB Host PWRON */
- imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
- gpio_direction_output(IMX_GPIO_NR(1, 2), 0);
-
- /* USB Host Over Current */
- imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC);
- }
-
- return 0;
-}
-#endif
-
-static void setup_iomux_fec(void)
-{
- static const iomux_v3_cfg_t fec_pads[] = {
- /* MDIO pads */
- NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
- PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
- NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
-
- /* FEC 0 pads */
- NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
-
- /* FEC 1 pads */
- NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
- };
-
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-}
-
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg esdhc_cfg = {
- MMC_SDHC1_BASE_ADDR,
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
- gpio_direction_input(IMX_GPIO_NR(1, 1));
-
- return !gpio_get_value(IMX_GPIO_NR(1, 1));
-}
-
-#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
- PAD_CTL_PUS_100K_UP)
-#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
- PAD_CTL_DSE_HIGH)
-
-int board_mmc_init(bd_t *bis)
-{
- static const iomux_v3_cfg_t sd1_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
- MX53_PAD_EIM_DA13__GPIO3_13,
-
- MX53_PAD_EIM_EB3__GPIO2_31, /* SD power */
- };
-
- esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-
- imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
-
- /* GPIO 2_31 is SD power */
- gpio_direction_output(IMX_GPIO_NR(2, 31), 0);
-
- return fsl_esdhc_initialize(bis, &esdhc_cfg);
-}
-#endif
-
-#ifdef CONFIG_VIDEO
-static struct fb_videomode const ampire_wvga = {
- .name = "Ampire",
- .refresh = 60,
- .xres = 800,
- .yres = 480,
- .pixclock = 29851, /* picosecond (33.5 MHz) */
- .left_margin = 89,
- .right_margin = 164,
- .upper_margin = 23,
- .lower_margin = 10,
- .hsync_len = 10,
- .vsync_len = 10,
- .sync = FB_SYNC_CLK_LAT_FALL,
-};
-
-int board_video_skip(void)
-{
- int ret;
- ret = ipuv3_fb_init(&ampire_wvga, 1, IPU_PIX_FMT_RGB666);
- if (ret)
- printf("Ampire LCD cannot be configured: %d\n", ret);
- return ret;
-}
-#endif
-
-#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
-
-static void setup_iomux_i2c(void)
-{
- static const iomux_v3_cfg_t i2c_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
- };
-
- imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
-}
-
-static void setup_iomux_video(void)
-{
- static const iomux_v3_cfg_t lcd_pads[] = {
- MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0,
- MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1,
- MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2,
- MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3,
- MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4,
- MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5,
- MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6,
- MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7,
- MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8,
- MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9,
- MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10,
- MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11,
- MX53_PAD_EIM_A17__IPU_DISP1_DAT_12,
- MX53_PAD_EIM_A18__IPU_DISP1_DAT_13,
- MX53_PAD_EIM_A19__IPU_DISP1_DAT_14,
- MX53_PAD_EIM_A20__IPU_DISP1_DAT_15,
- MX53_PAD_EIM_A21__IPU_DISP1_DAT_16,
- MX53_PAD_EIM_A22__IPU_DISP1_DAT_17,
- MX53_PAD_EIM_A23__IPU_DISP1_DAT_18,
- MX53_PAD_EIM_A24__IPU_DISP1_DAT_19,
- MX53_PAD_EIM_D31__IPU_DISP1_DAT_20,
- MX53_PAD_EIM_D30__IPU_DISP1_DAT_21,
- MX53_PAD_EIM_D26__IPU_DISP1_DAT_22,
- MX53_PAD_EIM_D27__IPU_DISP1_DAT_23,
- MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK,
- MX53_PAD_EIM_DA13__IPU_DI1_D0_CS,
- MX53_PAD_EIM_DA14__IPU_DI1_D1_CS,
- MX53_PAD_EIM_DA15__IPU_DI1_PIN1,
- MX53_PAD_EIM_DA11__IPU_DI1_PIN2,
- MX53_PAD_EIM_DA12__IPU_DI1_PIN3,
- MX53_PAD_EIM_A25__IPU_DI1_PIN12,
- MX53_PAD_EIM_DA10__IPU_DI1_PIN15,
- };
-
- imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
-}
-
-static void setup_iomux_nand(void)
-{
- static const iomux_v3_cfg_t nand_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
- PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
- PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
- PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
- PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
- PAD_CTL_PUS_100K_UP),
- NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
- PAD_CTL_PUS_100K_UP),
- NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
- PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
- PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
- PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
- PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
- PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
- PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
- PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
- PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
- PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
- };
-
- imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
-}
-
-static void m53_set_clock(void)
-{
- int ret;
- const uint32_t ref_clk = MXC_HCLK;
- const uint32_t dramclk = 400;
- uint32_t cpuclk;
-
- imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
- PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
- gpio_direction_input(IMX_GPIO_NR(4, 0));
-
- /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
- cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
-
- ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
- if (ret)
- printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk);
-
- ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
- if (ret) {
- printf("CPU: Switch peripheral clock to %dMHz failed\n",
- dramclk);
- }
-
- ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
- if (ret)
- printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk);
-}
-
-static void m53_set_nand(void)
-{
- u32 i;
-
- /* NAND flash is muxed on ATA pins */
- setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
-
- /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
- for (i = 0x4; i < 0x94; i += 0x18) {
- clrbits_le32(WEIM_BASE_ADDR + i,
- WEIM_GCR2_MUX16_BYP_GRANT_MASK);
- }
-
- mxc_set_clock(0, 33, MXC_NFC_CLK);
- enable_nfc_clk(1);
-}
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
- setup_iomux_fec();
- setup_iomux_i2c();
- setup_iomux_nand();
- setup_iomux_video();
-
- m53_set_clock();
-
- mxc_set_sata_internal_clock();
-
- /* NAND clock @ 33MHz */
- m53_set_nand();
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: DENX M53EVK\n");
-
- return 0;
-}
-
-/*
- * NAND SPL
- */
-#ifdef CONFIG_SPL_BUILD
-void spl_board_init(void)
-{
- setup_iomux_nand();
- m53_set_clock();
- m53_set_nand();
-}
-
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_NAND;
-}
-#endif