diff options
Diffstat (limited to 'qemu/roms/u-boot/board/amcc')
97 files changed, 0 insertions, 15383 deletions
diff --git a/qemu/roms/u-boot/board/amcc/acadia/Makefile b/qemu/roms/u-boot/board/amcc/acadia/Makefile deleted file mode 100644 index 035f40727..000000000 --- a/qemu/roms/u-boot/board/amcc/acadia/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = acadia.o cmd_acadia.o memory.o pll.o diff --git a/qemu/roms/u-boot/board/amcc/acadia/acadia.c b/qemu/roms/u-boot/board/amcc/acadia/acadia.c deleted file mode 100644 index 2eb18df5e..000000000 --- a/qemu/roms/u-boot/board/amcc/acadia/acadia.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> - -extern void board_pll_init_f(void); - -static void acadia_gpio_init(void) -{ - /* - * GPIO0 setup (select GPIO or alternate function) - */ - out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL); - out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */ - out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L); - out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */ - out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL); - out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */ - out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */ - - /* - * Ultra (405EZ) was nice enough to add another GPIO controller - */ - out32(GPIO1_OSRH, CONFIG_SYS_GPIO1_OSRH); /* output select */ - out32(GPIO1_OSRL, CONFIG_SYS_GPIO1_OSRL); - out32(GPIO1_ISR1H, CONFIG_SYS_GPIO1_ISR1H); /* input select */ - out32(GPIO1_ISR1L, CONFIG_SYS_GPIO1_ISR1L); - out32(GPIO1_TSRH, CONFIG_SYS_GPIO1_TSRH); /* three-state select */ - out32(GPIO1_TSRL, CONFIG_SYS_GPIO1_TSRL); - out32(GPIO1_TCR, CONFIG_SYS_GPIO1_TCR); /* enable output driver for outputs */ -} - -int board_early_init_f(void) -{ - unsigned int reg; - - /* don't reinit PLL when booting via I2C bootstrap option */ - mfsdr(SDR0_PINSTP, reg); - if (reg != 0xf0000000) - board_pll_init_f(); - - acadia_gpio_init(); - - /* Configure 405EZ for NAND usage */ - mtsdr(SDR0_NAND0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN); - mfsdr(SDR0_ULTRA0, reg); - reg &= ~SDR_ULTRA0_CSN_MASK; - reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) | - SDR_ULTRA0_NDGPIOBP | - SDR_ULTRA0_EBCRDYEN | - SDR_ULTRA0_NFSRSTEN; - mtsdr(SDR0_ULTRA0, reg); - - /* USB Host core needs this bit set */ - mfsdr(SDR0_ULTRA1, reg); - mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE); - - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000010); - mtdcr(UIC0PR, 0xFE7FFFF0); /* set int polarities */ - mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - return 0; -} - -int misc_init_f(void) -{ - /* Set EPLD to take PHY out of reset */ - out8(CONFIG_SYS_CPLD_BASE + 0x05, 0x00); - udelay(100000); - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - u8 rev; - - rev = in8(CONFIG_SYS_CPLD_BASE + 0); - printf("Board: Acadia - AMCC PPC405EZ Evaluation Board, Rev. %X", rev); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} diff --git a/qemu/roms/u-boot/board/amcc/acadia/cmd_acadia.c b/qemu/roms/u-boot/board/amcc/acadia/cmd_acadia.c deleted file mode 100644 index e9df61b7b..000000000 --- a/qemu/roms/u-boot/board/amcc/acadia/cmd_acadia.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <i2c.h> - -static u8 boot_267_nor[] = { - 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8e, 0x00, - 0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; - -static u8 boot_267_nand[] = { - 0xd0, 0x38, 0xc3, 0x50, 0x13, 0x88, 0x8e, 0x00, - 0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; - -static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - u8 chip; - u8 *buf; - int cpu_freq; - - if (argc < 3) - return cmd_usage(cmdtp); - - cpu_freq = simple_strtol(argv[1], NULL, 10); - if (cpu_freq != 267) { - printf("Unsupported cpu-frequency - only 267 supported\n"); - return 1; - } - - /* use 0x50 as I2C EEPROM address for now */ - chip = 0x50; - - if ((strcmp(argv[2], "nor") != 0) && - (strcmp(argv[2], "nand") != 0)) { - printf("Unsupported boot-device - only nor|nand support\n"); - return 1; - } - - if (strcmp(argv[2], "nand") == 0) { - switch (cpu_freq) { - case 267: - buf = boot_267_nand; - break; - default: - break; - } - } else { - switch (cpu_freq) { - case 267: - buf = boot_267_nor; - break; - default: - break; - } - } - - if (i2c_write(chip, 0, 1, buf, 16) != 0) - printf("Error writing to EEPROM at address 0x%x\n", chip); - udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); - if (i2c_write(chip, 0x10, 1, buf+16, 4) != 0) - printf("Error2 writing to EEPROM at address 0x%x\n", chip); - - printf("Done\n"); - printf("Please power-cycle the board for the changes to take effect\n"); - - return 0; -} - -U_BOOT_CMD( - bootstrap, 3, 0, do_bootstrap, - "program the I2C bootstrap EEPROM", - "<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM" -); diff --git a/qemu/roms/u-boot/board/amcc/acadia/config.mk b/qemu/roms/u-boot/board/amcc/acadia/config.mk deleted file mode 100644 index 5350ec04d..000000000 --- a/qemu/roms/u-boot/board/amcc/acadia/config.mk +++ /dev/null @@ -1,14 +0,0 @@ -# -# (C) Copyright 2007-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# AMCC 405EZ Reference Platform (Acadia) board -# - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif diff --git a/qemu/roms/u-boot/board/amcc/acadia/memory.c b/qemu/roms/u-boot/board/amcc/acadia/memory.c deleted file mode 100644 index 967311885..000000000 --- a/qemu/roms/u-boot/board/amcc/acadia/memory.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* define DEBUG for debugging output (obviously ;-)) */ -#if 0 -#define DEBUG -#endif - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> - -extern void board_pll_init_f(void); - -static void cram_bcr_write(u32 wr_val) -{ - wr_val <<= 2; - - /* set CRAM_CRE to 1 */ - gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1); - - /* Write BCR to CRAM on CS1 */ - out32(wr_val + 0x00200000, 0); - debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000); - - /* Write BCR to CRAM on CS2 */ - out32(wr_val + 0x02200000, 0); - debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000); - - sync(); - eieio(); - - /* set CRAM_CRE back to 0 (normal operation) */ - gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0); - - return; -} - -phys_size_t initdram(int board_type) -{ - int i; - u32 val; - - /* 1. EBC need to program READY, CLK, ADV for ASync mode */ - gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); - gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); - gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); - gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG); - - /* 2. EBC in Async mode */ - mtebc(PB1AP, 0x078F1EC0); - mtebc(PB2AP, 0x078F1EC0); - mtebc(PB1CR, 0x000BC000); - mtebc(PB2CR, 0x020BC000); - - /* 3. Set CRAM in Sync mode */ - cram_bcr_write(0x7012); /* CRAM burst setting */ - - /* 4. EBC in Sync mode */ - mtebc(PB1AP, 0x9C0201C0); - mtebc(PB2AP, 0x9C0201C0); - - /* Set GPIO pins back to alternate function */ - gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); - gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); - - /* Config EBC to use RDY */ - mfsdr(SDR0_ULTRA0, val); - mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN); - - /* Wait a short while, since for NAND booting this is too fast */ - for (i=0; i<200000; i++) - ; - - return (CONFIG_SYS_MBYTES_RAM << 20); -} diff --git a/qemu/roms/u-boot/board/amcc/acadia/pll.c b/qemu/roms/u-boot/board/amcc/acadia/pll.c deleted file mode 100644 index d868582ba..000000000 --- a/qemu/roms/u-boot/board/amcc/acadia/pll.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/ppc405.h> - -/* test-only: move into cpu directory!!! */ - -#if defined(PLLMR0_200_133_66) -void board_pll_init_f(void) -{ - /* - * set PLL clocks based on input sysclk is 33M - * - * ---------------------------------- - * | CLK | FREQ (MHz) | DIV RATIO | - * ---------------------------------- - * | CPU | 200.0 | 4 (0x02)| - * | PLB | 133.3 | 6 (0x06)| - * | OPB | 66.6 | 12 (0x0C)| - * | EBC | 66.6 | 12 (0x0C)| - * | SPI | 66.6 | 12 (0x0C)| - * | UART0 | 10.0 | 40 (0x28)| - * | UART1 | 10.0 | 40 (0x28)| - * | DAC | 2.0 | 200 (0xC8)| - * | ADC | 2.0 | 200 (0xC8)| - * | PWM | 100.0 | 4 (0x04)| - * | EMAC | 25.0 | 16 (0x10)| - * ----------------------------------- - */ - - /* Initialize PLL */ - mtcpr(CPR0_PLLC, 0x0000033c); - mtcpr(CPR0_PLLD, 0x0c010200); - mtcpr(CPR0_PRIMAD, 0x04060c0c); - mtcpr(CPR0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */ - mtcpr(CPR0_CLKUPD, 0x40000000); -} - -#elif defined(PLLMR0_266_160_80) - -void board_pll_init_f(void) -{ - /* - * set PLL clocks based on input sysclk is 33M - * - * ---------------------------------- - * | CLK | FREQ (MHz) | DIV RATIO | - * ---------------------------------- - * | CPU | 266.64 | 3 | - * | PLB | 159.98 | 5 (0x05)| - * | OPB | 79.99 | 10 (0x0A)| - * | EBC | 79.99 | 10 (0x0A)| - * | SPI | 79.99 | 10 (0x0A)| - * | UART0 | 28.57 | 7 (0x07)| - * | UART1 | 28.57 | 7 (0x07)| - * | DAC | 28.57 | 7 (0xA7)| - * | ADC | 4 | 50 (0x32)| - * | PWM | 28.57 | 7 (0x07)| - * | EMAC | 4 | 50 (0x32)| - * ----------------------------------- - */ - - /* Initialize PLL */ - mtcpr(CPR0_PLLC, 0x20000238); - mtcpr(CPR0_PLLD, 0x03010400); - mtcpr(CPR0_PRIMAD, 0x03050a0a); - mtcpr(CPR0_PERC0, 0x00000000); - mtcpr(CPR0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */ - mtcpr(CPR0_PERD1, 0x07323200); - mtcpr(CPR0_CLKUP, 0x40000000); -} - -#elif defined(PLLMR0_333_166_83) - -void board_pll_init_f(void) -{ - /* - * set PLL clocks based on input sysclk is 33M - * - * ---------------------------------- - * | CLK | FREQ (MHz) | DIV RATIO | - * ---------------------------------- - * | CPU | 333.33 | 2 | - * | PLB | 166.66 | 4 (0x04)| - * | OPB | 83.33 | 8 (0x08)| - * | EBC | 83.33 | 8 (0x08)| - * | SPI | 83.33 | 8 (0x08)| - * | UART0 | 16.66 | 5 (0x05)| - * | UART1 | 16.66 | 5 (0x05)| - * | DAC | ???? | 166 (0xA6)| - * | ADC | ???? | 166 (0xA6)| - * | PWM | 41.66 | 3 (0x03)| - * | EMAC | ???? | 3 (0x03)| - * ----------------------------------- - */ - - /* Initialize PLL */ - mtcpr(CPR0_PLLC, 0x0000033C); - mtcpr(CPR0_PLLD, 0x0a010000); - mtcpr(CPR0_PRIMAD, 0x02040808); - mtcpr(CPR0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */ - mtcpr(CPR0_PERD1, 0xA6A60300); - mtcpr(CPR0_CLKUP, 0x40000000); -} - -#elif defined(PLLMR0_100_100_12) - -void board_pll_init_f(void) -{ - /* - * set PLL clocks based on input sysclk is 33M - * - * ---------------------- - * | CLK | FREQ (MHz) | - * ---------------------- - * | CPU | 100.00 | - * | PLB | 100.00 | - * | OPB | 12.00 | - * | EBC | 49.00 | - * ---------------------- - */ - - /* Initialize PLL */ - mtcpr(CPR0_PLLC, 0x000003BC); - mtcpr(CPR0_PLLD, 0x06060600); - mtcpr(CPR0_PRIMAD, 0x02020004); - mtcpr(CPR0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */ - mtcpr(CPR0_PERD1, 0xC8C81600); - mtcpr(CPR0_CLKUP, 0x40000000); -} -#endif /* CPU_<speed>_405EZ */ diff --git a/qemu/roms/u-boot/board/amcc/bamboo/Makefile b/qemu/roms/u-boot/board/amcc/bamboo/Makefile deleted file mode 100644 index 4c0a1253f..000000000 --- a/qemu/roms/u-boot/board/amcc/bamboo/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = bamboo.o flash.o -extra-y += init.o diff --git a/qemu/roms/u-boot/board/amcc/bamboo/README b/qemu/roms/u-boot/board/amcc/bamboo/README deleted file mode 100644 index e139c6d12..000000000 --- a/qemu/roms/u-boot/board/amcc/bamboo/README +++ /dev/null @@ -1,77 +0,0 @@ -The 2 important dipswitches are configured as shown below: - -SW1 (for 33MHz SysClk) ----------------------- -S1 S2 S3 S4 S5 S6 S7 S8 -OFF OFF OFF OFF OFF OFF OFF ON - -SW7 (for Op-Code Flash and Boot Option H) ------------------------------------------ -S1 S2 S3 S4 S5 S6 S7 S8 -OFF OFF OFF ON OFF OFF OFF OFF - -The EEPROM at location 0x52 is loaded with these 16 bytes: -C47042A6 05D7A190 40082350 0d050000 - -SDR0_SDSTP0[ENG]: 1 : PLL's VCO is the source for PLL forward divisors -SDR0_SDSTP0[SRC]: 1 : Feedback originates from PLLOUTB -SDR0_SDSTP0[SEL]: 0 : Feedback selection is PLL output -SDR0_SDSTP0[TUNE]: 1000111000 : 10 <= M <= 22, 600MHz < VCO <= 900MHz -SDR0_SDSTP0[FBDV]: 4 : PLL feedback divisor -SDR0_SDSTP0[FBDVA]: 2 : PLL forward divisor A -SDR0_SDSTP0[FBDVB]: 5 : PLL forward divisor B -SDR0_SDSTP0[PRBDV0]: 1 : PLL primary divisor B -SDR0_SDSTP0[OPBDV0]: 2 : OPB clock divisor -SDR0_SDSTP0[LFBDV]: 1 : PLL local feedback divisor -SDR0_SDSTP0[PERDV0]: 3 : Peripheral clock divisor 0 -SDR0_SDSTP0[MALDV0]: 2 : MAL clock divisor 0 -SDR0_SDSTP0[PCIDV0]: 2 : Sync PCI clock divisor 0 -SDR0_SDSTP0[PLLTIMER]: 7 : PLL locking timer -SDR0_SDSTP0[RW]: 1 : EBC ROM width: 16-bit -SDR0_SDSTP0[RL]: 0 : EBC ROM location: EBC -SDR0_SDSTP0[PAE]: 0 : PCI internal arbiter: disabled -SDR0_SDSTP0[PHCE]: 0 : PCI host configuration: disabled -SDR0_SDSTP0[ZM]: 3 : ZMII mode: RMII mode 100 -SDR0_SDSTP0[CTE]: 0 : CPU trace: disabled -SDR0_SDSTP0[Nto1]: 0 : CPU/PLB ratio N/P: not N to 1 -SDR0_SDSTP0[PAME]: 1 : PCI asynchronous mode: enabled -SDR0_SDSTP0[MEM]: 1 : Multiplex: EMAC -SDR0_SDSTP0[NE]: 0 : NDFC: disabled -SDR0_SDSTP0[NBW]: 0 : NDFC boot width: 8-bit -SDR0_SDSTP0[NBW]: 0 : NDFC boot page selection -SDR0_SDSTP0[NBAC]: 0 : NDFC boot address selection cycle: 3 Addr. Cycles, 1 Col. + 2 Row (512 page size) -SDR0_SDSTP0[NARE]: 0 : NDFC auto read : disabled -SDR0_SDSTP0[NRB]: 0 : NDFC Ready/Busy : Ready -SDR0_SDSTP0[NDRSC]: 33333 : NDFC device reset counter -SDR0_SDSTP0[NCG0]: 0 : NDFC/EBC chip select gating CS0 : EBC -SDR0_SDSTP0[NCG1]: 0 : NDFC/EBC chip select gating CS1 : EBC -SDR0_SDSTP0[NCG2]: 0 : NDFC/EBC chip select gating CS2 : EBC -SDR0_SDSTP0[NCG3]: 0 : NDFC/EBC chip select gating CS3 : EBC -SDR0_SDSTP0[NCRDC]: 3333 : NDFC device read count - -PPC440EP Clocking Configuration - -SysClk is 33.0MHz, M is 20, VCO is 660.0MHz, CPU is 330.0MHz, PLB is 132.0MHz -OPB is 66.0MHz, EBC is 44.0MHz, MAL is 66.0MHz, Sync PCI is 66.0MHz - -The above information is reported by Eugene O'Brien -<Eugene.O'Brien@advantechamt.com>. Thanks a lot. - -2007-08-06, Stefan Roese <sr@denx.de> ---------------------------------------------------------------------- - -The configuration for the AMCC 440EP eval board "Bamboo" was changed -to only use 384 kbytes of FLASH for the U-Boot image. This way the -redundant environment can be saved in the remaining 2 sectors of the -same flash chip. - -Caution: With an upgrade from an earlier U-Boot version the current -environment will be erased since the environment is now saved in -different sectors. By using the following command the environment can -be saved after upgrading the U-Boot image and *before* resetting the -board: - -setenv recover_env 'prot off FFF80000 FFF9FFFF;era FFF80000 FFF9FFFF;' \ - 'cp.b FFF60000 FFF80000 20000' - -2006-07-27, Stefan Roese <sr@denx.de> diff --git a/qemu/roms/u-boot/board/amcc/bamboo/bamboo.c b/qemu/roms/u-boot/board/amcc/bamboo/bamboo.c deleted file mode 100644 index c8d09636a..000000000 --- a/qemu/roms/u-boot/board/amcc/bamboo/bamboo.c +++ /dev/null @@ -1,1896 +0,0 @@ -/* - * (C) Copyright 2005-2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/ppc4xx-gpio.h> -#include <spd_sdram.h> -#include <asm/ppc440.h> -#include "bamboo.h" - -void ext_bus_cntlr_init(void); -void configure_ppc440ep_pins(void); -int is_nand_selected(void); - -/************************************************************************* - * - * Bamboo has one bank onboard sdram (plus DIMM) - * - * Fixed memory is composed of : - * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266, - * 13 row add bits, 10 column add bits (but 12 row used only). - * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266, - * 12 row add bits, 10 column add bits. - * Prepare a subset (only the used ones) of SPD data - * - * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of - * the corresponding bank is divided by 2 due to number of Row addresses - * 12 in the ECC module - * - * Assumes: 64 MB, ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -const unsigned char cfg_simulate_spd_eeprom[128] = { - 0x80, /* number of SPD bytes used: 128 */ - 0x08, /* total number bytes in SPD device = 256 */ - 0x07, /* DDR ram */ -#ifdef CONFIG_DDR_ECC - 0x0C, /* num Row Addr: 12 */ -#else - 0x0D, /* num Row Addr: 13 */ -#endif - 0x09, /* numColAddr: 9 */ - 0x01, /* numBanks: 1 */ - 0x20, /* Module data width: 32 bits */ - 0x00, /* Module data width continued: +0 */ - 0x04, /* 2.5 Volt */ - 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */ - 0x00, /* SDRAM Access from clock */ -#ifdef CONFIG_DDR_ECC - 0x02, /* ECC ON : 02 OFF : 00 */ -#else - 0x00, /* ECC ON : 02 OFF : 00 */ -#endif - 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */ - 0, - 0, - 0x01, /* wcsbc = 1 */ - 0, - 0, - 0x0C, /* casBit (2,2.5) */ - 0, - 0, - 0x00, /* not registered: 0 registered : 0x02*/ - 0, - 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */ - 0, - 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */ - 0, - 0x50, /* tRpNs = 20 ns */ - 0, - 0x50, /* tRcdNs = 20 ns */ - 45, /* tRasNs */ -#ifdef CONFIG_DDR_ECC - 0x08, /* bankSizeID: 32MB */ -#else - 0x10, /* bankSizeID: 64MB */ -#endif - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0 -}; - -#if 0 -{ /* GPIO Alternate1 Alternate2 Alternate3 */ - { - /* GPIO Core 0 */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */ - { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */ - { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */ - }, - { - /* GPIO Core 1 */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */ - } -}; -#endif - -/*----------------------------------------------------------------------------+ - | EBC Devices Characteristics - | Peripheral Bank Access Parameters - EBC0_BnAP - | Peripheral Bank Configuration Register - EBC0_BnCR - +----------------------------------------------------------------------------*/ -/* Small Flash */ -#define EBC0_BNAP_SMALL_FLASH \ - EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(6) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(1) | \ - EBC0_BNAP_WBN_ENCODE(1) | \ - EBC0_BNAP_WBF_ENCODE(3) | \ - EBC0_BNAP_TH_ENCODE(1) | \ - EBC0_BNAP_RE_ENABLED | \ - EBC0_BNAP_SOR_DELAYED | \ - EBC0_BNAP_BEM_WRITEONLY | \ - EBC0_BNAP_PEN_DISABLED - -#define EBC0_BNCR_SMALL_FLASH_CS0 \ - EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_8BIT - -#define EBC0_BNCR_SMALL_FLASH_CS4 \ - EBC0_BNCR_BAS_ENCODE(0x87F00000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_8BIT - -/* Large Flash or SRAM */ -#define EBC0_BNAP_LARGE_FLASH_OR_SRAM \ - EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(8) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(1) | \ - EBC0_BNAP_WBN_ENCODE(1) | \ - EBC0_BNAP_WBF_ENCODE(1) | \ - EBC0_BNAP_TH_ENCODE(2) | \ - EBC0_BNAP_SOR_DELAYED | \ - EBC0_BNAP_BEM_RW | \ - EBC0_BNAP_PEN_DISABLED - -#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \ - EBC0_BNCR_BAS_ENCODE(0xFF800000) | \ - EBC0_BNCR_BS_8MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_16BIT - - -#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \ - EBC0_BNCR_BAS_ENCODE(0x87800000) | \ - EBC0_BNCR_BS_8MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_16BIT - -/* NVRAM - FPGA */ -#define EBC0_BNAP_NVRAM_FPGA \ - EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(9) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(1) | \ - EBC0_BNAP_WBN_ENCODE(1) | \ - EBC0_BNAP_WBF_ENCODE(0) | \ - EBC0_BNAP_TH_ENCODE(2) | \ - EBC0_BNAP_RE_ENABLED | \ - EBC0_BNAP_SOR_DELAYED | \ - EBC0_BNAP_BEM_WRITEONLY | \ - EBC0_BNAP_PEN_DISABLED - -#define EBC0_BNCR_NVRAM_FPGA_CS5 \ - EBC0_BNCR_BAS_ENCODE(0x80000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_8BIT - -/* Nand Flash */ -#define EBC0_BNAP_NAND_FLASH \ - EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(3) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(0) | \ - EBC0_BNAP_WBN_ENCODE(0) | \ - EBC0_BNAP_WBF_ENCODE(0) | \ - EBC0_BNAP_TH_ENCODE(1) | \ - EBC0_BNAP_RE_ENABLED | \ - EBC0_BNAP_SOR_NOT_DELAYED | \ - EBC0_BNAP_BEM_RW | \ - EBC0_BNAP_PEN_DISABLED - - -#define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000 - -/* NAND0 */ -#define EBC0_BNCR_NAND_FLASH_CS1 \ - EBC0_BNCR_BAS_ENCODE(0x90000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_32BIT -/* NAND1 - Bank2 */ -#define EBC0_BNCR_NAND_FLASH_CS2 \ - EBC0_BNCR_BAS_ENCODE(0x94000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_32BIT - -/* NAND1 - Bank3 */ -#define EBC0_BNCR_NAND_FLASH_CS3 \ - EBC0_BNCR_BAS_ENCODE(0x94000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_32BIT - -int board_early_init_f(void) -{ - ext_bus_cntlr_init(); - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ - mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - /*-------------------------------------------------------------------- - * Setup the GPIO pins - *-------------------------------------------------------------------*/ - out32(GPIO0_OSRL, 0x00000400); - out32(GPIO0_OSRH, 0x00000000); - out32(GPIO0_TSRL, 0x00000400); - out32(GPIO0_TSRH, 0x00000000); - out32(GPIO0_ISR1L, 0x00000000); - out32(GPIO0_ISR1H, 0x00000000); - out32(GPIO0_ISR2L, 0x00000000); - out32(GPIO0_ISR2H, 0x00000000); - out32(GPIO0_ISR3L, 0x00000000); - out32(GPIO0_ISR3H, 0x00000000); - - out32(GPIO1_OSRL, 0x0C380000); - out32(GPIO1_OSRH, 0x00000000); - out32(GPIO1_TSRL, 0x0C380000); - out32(GPIO1_TSRH, 0x00000000); - out32(GPIO1_ISR1L, 0x0FC30000); - out32(GPIO1_ISR1H, 0x00000000); - out32(GPIO1_ISR2L, 0x0C010000); - out32(GPIO1_ISR2H, 0x00000000); - out32(GPIO1_ISR3L, 0x01400000); - out32(GPIO1_ISR3H, 0x00000000); - - configure_ppc440ep_pins(); - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: Bamboo - AMCC PPC440EP Evaluation Board"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} - - -phys_size_t initdram (int board_type) -{ - long dram_size; - - dram_size = spd_sdram(); - - return dram_size; -} - -/*----------------------------------------------------------------------------+ - | is_powerpc440ep_pass1. - +----------------------------------------------------------------------------*/ -int is_powerpc440ep_pass1(void) -{ - unsigned long pvr; - - pvr = get_pvr(); - - if (pvr == PVR_POWERPC_440EP_PASS1) - return true; - else if (pvr == PVR_POWERPC_440EP_PASS2) - return false; - else { - printf("brdutil error 3\n"); - for (;;) - ; - } - - return false; -} - -/*----------------------------------------------------------------------------+ - | is_nand_selected. - +----------------------------------------------------------------------------*/ -int is_nand_selected(void) -{ -#ifdef CONFIG_BAMBOO_NAND - return true; -#else - return false; -#endif -} - -/*----------------------------------------------------------------------------+ - | config_on_ebc_cs4_is_small_flash => from EPLD - +----------------------------------------------------------------------------*/ -unsigned char config_on_ebc_cs4_is_small_flash(void) -{ - /* Not implemented yet => returns constant value */ - return true; -} - -/*----------------------------------------------------------------------------+ - | Ext_bus_cntlr_init. - | Initialize the external bus controller - +----------------------------------------------------------------------------*/ -void ext_bus_cntlr_init(void) -{ - unsigned long sdr0_pstrp0, sdr0_sdstp1; - unsigned long bootstrap_settings, boot_selection, ebc_boot_size; - int computed_boot_device = BOOT_DEVICE_UNKNOWN; - unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0; - unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0; - unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0; - unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0; - unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0; - - - /*-------------------------------------------------------------------------+ - | - | PART 1 : Initialize EBC Bank 5 - | ============================== - | Bank5 is always associated to the NVRAM/EPLD. - | It has to be initialized prior to other banks settings computation since - | some board registers values may be needed - | - +-------------------------------------------------------------------------*/ - /* NVRAM - FPGA */ - mtebc(PB5AP, EBC0_BNAP_NVRAM_FPGA); - mtebc(PB5CR, EBC0_BNCR_NVRAM_FPGA_CS5); - - /*-------------------------------------------------------------------------+ - | - | PART 2 : Determine which boot device was selected - | ========================================= - | - | Read Pin Strap Register in PPC440EP - | In case of boot from IIC, read Serial Device Strap Register1 - | - | Result can either be : - | - Boot from EBC 8bits => SMALL FLASH - | - Boot from EBC 16bits => Large Flash or SRAM - | - Boot from NAND Flash - | - Boot from PCI - | - +-------------------------------------------------------------------------*/ - /* Read Pin Strap Register in PPC440EP */ - mfsdr(SDR0_PINSTP, sdr0_pstrp0); - bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK; - - /*-------------------------------------------------------------------------+ - | PPC440EP Pass1 - +-------------------------------------------------------------------------*/ - if (is_powerpc440ep_pass1() == true) { - switch(bootstrap_settings) { - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0: - /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */ - /* Boot from Small Flash */ - computed_boot_device = BOOT_FROM_SMALL_FLASH; - break; - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1: - /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */ - /* Boot from PCI */ - computed_boot_device = BOOT_FROM_PCI; - break; - - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2: - /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */ - /* Boot from Nand Flash */ - computed_boot_device = BOOT_FROM_NAND_FLASH0; - break; - - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3: - /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */ - /* Boot from Small Flash */ - computed_boot_device = BOOT_FROM_SMALL_FLASH; - break; - - case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN: - case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN: - /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */ - /* Read Serial Device Strap Register1 in PPC440EP */ - mfsdr(SDR0_SDSTP1, sdr0_sdstp1); - boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; - ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; - - switch(boot_selection) { - case SDR0_SDSTP1_BOOT_SEL_EBC: - switch(ebc_boot_size) { - case SDR0_SDSTP1_EBC_ROM_BS_16BIT: - computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; - break; - case SDR0_SDSTP1_EBC_ROM_BS_8BIT: - computed_boot_device = BOOT_FROM_SMALL_FLASH; - break; - } - break; - - case SDR0_SDSTP1_BOOT_SEL_PCI: - computed_boot_device = BOOT_FROM_PCI; - break; - - case SDR0_SDSTP1_BOOT_SEL_NDFC: - computed_boot_device = BOOT_FROM_NAND_FLASH0; - break; - } - break; - } - } - - /*-------------------------------------------------------------------------+ - | PPC440EP Pass2 - +-------------------------------------------------------------------------*/ - else { - switch(bootstrap_settings) { - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0: - /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */ - /* Boot from Small Flash */ - computed_boot_device = BOOT_FROM_SMALL_FLASH; - break; - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1: - /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */ - /* Boot from PCI */ - computed_boot_device = BOOT_FROM_PCI; - break; - - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2: - /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */ - /* Boot from Nand Flash */ - computed_boot_device = BOOT_FROM_NAND_FLASH0; - break; - - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3: - /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */ - /* Boot from Large Flash or SRAM */ - computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; - break; - - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4: - /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */ - /* Boot from Large Flash or SRAM */ - computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; - break; - - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6: - /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */ - /* Boot from PCI */ - computed_boot_device = BOOT_FROM_PCI; - break; - - case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN: - case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN: - /* Default Strap Settings 5-7 */ - /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */ - /* Read Serial Device Strap Register1 in PPC440EP */ - mfsdr(SDR0_SDSTP1, sdr0_sdstp1); - boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; - ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; - - switch(boot_selection) { - case SDR0_SDSTP1_BOOT_SEL_EBC: - switch(ebc_boot_size) { - case SDR0_SDSTP1_EBC_ROM_BS_16BIT: - computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; - break; - case SDR0_SDSTP1_EBC_ROM_BS_8BIT: - computed_boot_device = BOOT_FROM_SMALL_FLASH; - break; - } - break; - - case SDR0_SDSTP1_BOOT_SEL_PCI: - computed_boot_device = BOOT_FROM_PCI; - break; - - case SDR0_SDSTP1_BOOT_SEL_NDFC: - computed_boot_device = BOOT_FROM_NAND_FLASH0; - break; - } - break; - } - } - - /*-------------------------------------------------------------------------+ - | - | PART 3 : Compute EBC settings depending on selected boot device - | ====== ====================================================== - | - | Resulting EBC init will be among following configurations : - | - | - Boot from EBC 8bits => boot from SMALL FLASH selected - | EBC-CS0 = Small Flash - | EBC-CS1,2,3 = NAND Flash or - | Exp.Slot depending on Soft Config - | EBC-CS4 = SRAM/Large Flash or - | Large Flash/SRAM depending on jumpers - | EBC-CS5 = NVRAM / EPLD - | - | - Boot from EBC 16bits => boot from Large Flash or SRAM selected - | EBC-CS0 = SRAM/Large Flash or - | Large Flash/SRAM depending on jumpers - | EBC-CS1,2,3 = NAND Flash or - | Exp.Slot depending on Software Configuration - | EBC-CS4 = Small Flash - | EBC-CS5 = NVRAM / EPLD - | - | - Boot from NAND Flash - | EBC-CS0 = NAND Flash0 - | EBC-CS1,2,3 = NAND Flash1 - | EBC-CS4 = SRAM/Large Flash or - | Large Flash/SRAM depending on jumpers - | EBC-CS5 = NVRAM / EPLD - | - | - Boot from PCI - | EBC-CS0 = ... - | EBC-CS1,2,3 = NAND Flash or - | Exp.Slot depending on Software Configuration - | EBC-CS4 = SRAM/Large Flash or - | Large Flash/SRAM or - | Small Flash depending on jumpers - | EBC-CS5 = NVRAM / EPLD - | - +-------------------------------------------------------------------------*/ - - switch(computed_boot_device) { - /*------------------------------------------------------------------------- */ - case BOOT_FROM_SMALL_FLASH: - /*------------------------------------------------------------------------- */ - ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH; - ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0; - if ((is_nand_selected()) == true) { - /* NAND Flash */ - ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; - ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; - ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH; - ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2; - ebc0_cs3_bnap_value = 0; - ebc0_cs3_bncr_value = 0; - } else { - /* Expansion Slot */ - ebc0_cs1_bnap_value = 0; - ebc0_cs1_bncr_value = 0; - ebc0_cs2_bnap_value = 0; - ebc0_cs2_bncr_value = 0; - ebc0_cs3_bnap_value = 0; - ebc0_cs3_bncr_value = 0; - } - ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; - ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4; - - break; - - /*------------------------------------------------------------------------- */ - case BOOT_FROM_LARGE_FLASH_OR_SRAM: - /*------------------------------------------------------------------------- */ - ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; - ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0; - if ((is_nand_selected()) == true) { - /* NAND Flash */ - ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; - ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; - ebc0_cs2_bnap_value = 0; - ebc0_cs2_bncr_value = 0; - ebc0_cs3_bnap_value = 0; - ebc0_cs3_bncr_value = 0; - } else { - /* Expansion Slot */ - ebc0_cs1_bnap_value = 0; - ebc0_cs1_bncr_value = 0; - ebc0_cs2_bnap_value = 0; - ebc0_cs2_bncr_value = 0; - ebc0_cs3_bnap_value = 0; - ebc0_cs3_bncr_value = 0; - } - ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH; - ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4; - - break; - - /*------------------------------------------------------------------------- */ - case BOOT_FROM_NAND_FLASH0: - /*------------------------------------------------------------------------- */ - ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH; - ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; - - ebc0_cs1_bnap_value = 0; - ebc0_cs1_bncr_value = 0; - ebc0_cs2_bnap_value = 0; - ebc0_cs2_bncr_value = 0; - ebc0_cs3_bnap_value = 0; - ebc0_cs3_bncr_value = 0; - - /* Large Flash or SRAM */ - ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; - ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4; - - break; - - /*------------------------------------------------------------------------- */ - case BOOT_FROM_PCI: - /*------------------------------------------------------------------------- */ - ebc0_cs0_bnap_value = 0; - ebc0_cs0_bncr_value = 0; - - if ((is_nand_selected()) == true) { - /* NAND Flash */ - ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; - ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; - ebc0_cs2_bnap_value = 0; - ebc0_cs2_bncr_value = 0; - ebc0_cs3_bnap_value = 0; - ebc0_cs3_bncr_value = 0; - } else { - /* Expansion Slot */ - ebc0_cs1_bnap_value = 0; - ebc0_cs1_bncr_value = 0; - ebc0_cs2_bnap_value = 0; - ebc0_cs2_bncr_value = 0; - ebc0_cs3_bnap_value = 0; - ebc0_cs3_bncr_value = 0; - } - - if ((config_on_ebc_cs4_is_small_flash()) == true) { - /* Small Flash */ - ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH; - ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4; - } else { - /* Large Flash or SRAM */ - ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; - ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4; - } - - break; - - /*------------------------------------------------------------------------- */ - case BOOT_DEVICE_UNKNOWN: - /*------------------------------------------------------------------------- */ - /* Error */ - break; - - } - - - /*-------------------------------------------------------------------------+ - | Initialize EBC CONFIG - +-------------------------------------------------------------------------*/ - mtdcr(EBC0_CFGADDR, EBC0_CFG); - mtdcr(EBC0_CFGDATA, EBC0_CFG_EBTC_DRIVEN | - EBC0_CFG_PTD_ENABLED | - EBC0_CFG_RTC_2048PERCLK | - EBC0_CFG_EMPL_LOW | - EBC0_CFG_EMPH_LOW | - EBC0_CFG_CSTC_DRIVEN | - EBC0_CFG_BPF_ONEDW | - EBC0_CFG_EMS_8BIT | - EBC0_CFG_PME_DISABLED | - EBC0_CFG_PMT_ENCODE(0) ); - - /*-------------------------------------------------------------------------+ - | Initialize EBC Bank 0-4 - +-------------------------------------------------------------------------*/ - /* EBC Bank0 */ - mtebc(PB0AP, ebc0_cs0_bnap_value); - mtebc(PB0CR, ebc0_cs0_bncr_value); - /* EBC Bank1 */ - mtebc(PB1AP, ebc0_cs1_bnap_value); - mtebc(PB1CR, ebc0_cs1_bncr_value); - /* EBC Bank2 */ - mtebc(PB2AP, ebc0_cs2_bnap_value); - mtebc(PB2CR, ebc0_cs2_bncr_value); - /* EBC Bank3 */ - mtebc(PB3AP, ebc0_cs3_bnap_value); - mtebc(PB3CR, ebc0_cs3_bncr_value); - /* EBC Bank4 */ - mtebc(PB4AP, ebc0_cs4_bnap_value); - mtebc(PB4CR, ebc0_cs4_bncr_value); - - return; -} - - -/*----------------------------------------------------------------------------+ - | get_uart_configuration. - +----------------------------------------------------------------------------*/ -uart_config_nb_t get_uart_configuration(void) -{ - return (L4); -} - -/*----------------------------------------------------------------------------+ - | set_phy_configuration_through_fpga => to EPLD - +----------------------------------------------------------------------------*/ -void set_phy_configuration_through_fpga(zmii_config_t config) -{ - - unsigned long fpga_selection_reg; - - fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK; - - switch(config) - { - case ZMII_CONFIGURATION_IS_MII: - fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII; - break; - case ZMII_CONFIGURATION_IS_RMII: - fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII; - break; - case ZMII_CONFIGURATION_IS_SMII: - fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII; - break; - case ZMII_CONFIGURATION_UNKNOWN: - default: - break; - } - out8(FPGA_SELECTION_1_REG,fpga_selection_reg); - -} - -/*----------------------------------------------------------------------------+ - | scp_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void scp_selection_in_fpga(void) -{ - unsigned long fpga_selection_2_reg; - - fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK; - fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP; - out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); -} - -/*----------------------------------------------------------------------------+ - | iic1_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void iic1_selection_in_fpga(void) -{ - unsigned long fpga_selection_2_reg; - - fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK; - fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1; - out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); -} - -/*----------------------------------------------------------------------------+ - | dma_a_b_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void dma_a_b_selection_in_fpga(void) -{ - unsigned long fpga_selection_2_reg; - - fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B; - out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); -} - -/*----------------------------------------------------------------------------+ - | dma_a_b_unselect_in_fpga. - +----------------------------------------------------------------------------*/ -void dma_a_b_unselect_in_fpga(void) -{ - unsigned long fpga_selection_2_reg; - - fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B; - out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); -} - -/*----------------------------------------------------------------------------+ - | dma_c_d_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void dma_c_d_selection_in_fpga(void) -{ - unsigned long fpga_selection_2_reg; - - fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D; - out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); -} - -/*----------------------------------------------------------------------------+ - | dma_c_d_unselect_in_fpga. - +----------------------------------------------------------------------------*/ -void dma_c_d_unselect_in_fpga(void) -{ - unsigned long fpga_selection_2_reg; - - fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D; - out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); -} - -/*----------------------------------------------------------------------------+ - | usb2_device_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void usb2_device_selection_in_fpga(void) -{ - unsigned long fpga_selection_1_reg; - - fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL; - out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg); -} - -/*----------------------------------------------------------------------------+ - | usb2_device_reset_through_fpga. - +----------------------------------------------------------------------------*/ -void usb2_device_reset_through_fpga(void) -{ - /* Perform soft Reset pulse */ - unsigned long fpga_reset_reg; - int i; - - fpga_reset_reg = in8(FPGA_RESET_REG); - out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV); - for (i=0; i<500; i++) - udelay(1000); - out8(FPGA_RESET_REG,fpga_reset_reg); -} - -/*----------------------------------------------------------------------------+ - | usb2_host_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void usb2_host_selection_in_fpga(void) -{ - unsigned long fpga_selection_1_reg; - - fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL; - out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg); -} - -/*----------------------------------------------------------------------------+ - | ndfc_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void ndfc_selection_in_fpga(void) -{ - unsigned long fpga_selection_1_reg; - - fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK; - fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1; - fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2; - out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg); -} - -/*----------------------------------------------------------------------------+ - | uart_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void uart_selection_in_fpga(uart_config_nb_t uart_config) -{ - /* FPGA register */ - unsigned char fpga_selection_3_reg; - - /* Read FPGA Reagister */ - fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG); - - switch (uart_config) - { - case L1: - /* ----------------------------------------------------------------------- */ - /* L1 configuration: UART0 = 8 pins */ - /* ----------------------------------------------------------------------- */ - /* Configure FPGA */ - fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; - fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1; - out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); - - break; - - case L2: - /* ----------------------------------------------------------------------- */ - /* L2 configuration: UART0 = 4 pins */ - /* UART1 = 4 pins */ - /* ----------------------------------------------------------------------- */ - /* Configure FPGA */ - fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; - fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2; - out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); - - break; - - case L3: - /* ----------------------------------------------------------------------- */ - /* L3 configuration: UART0 = 4 pins */ - /* UART1 = 2 pins */ - /* UART2 = 2 pins */ - /* ----------------------------------------------------------------------- */ - /* Configure FPGA */ - fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; - fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3; - out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); - break; - - case L4: - /* Configure FPGA */ - fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; - fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4; - out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); - - break; - - default: - /* Unsupported UART configuration number */ - for (;;) - ; - break; - - } -} - - -/*----------------------------------------------------------------------------+ - | init_default_gpio - +----------------------------------------------------------------------------*/ -void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - int i; - - /* Init GPIO0 */ - for(i=0; i<GPIO_MAX; i++) - { - gpio_tab[GPIO0][i].add = GPIO0_BASE; - gpio_tab[GPIO0][i].in_out = GPIO_DIS; - gpio_tab[GPIO0][i].alt_nb = GPIO_SEL; - } - - /* Init GPIO1 */ - for(i=0; i<GPIO_MAX; i++) - { - gpio_tab[GPIO1][i].add = GPIO1_BASE; - gpio_tab[GPIO1][i].in_out = GPIO_DIS; - gpio_tab[GPIO1][i].alt_nb = GPIO_SEL; - } - - /* EBC_CS_N(5) - GPIO0_10 */ - gpio_tab[GPIO0][10].in_out = GPIO_OUT; - gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1; - - /* EBC_CS_N(4) - GPIO0_9 */ - gpio_tab[GPIO0][9].in_out = GPIO_OUT; - gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1; -} - -/*----------------------------------------------------------------------------+ - | update_uart_ios - +------------------------------------------------------------------------------ - | - | Set UART Configuration in PowerPC440EP - | - | +---------------------------------------------------------------------+ - | | Configuartion | Connector | Nb of pins | Pins | Associated | - | | Number | Port Name | available | naming | CORE | - | +-----------------+---------------+------------+--------+-------------+ - | | L1 | Port_A | 8 | UART | UART core 0 | - | +-----------------+---------------+------------+--------+-------------+ - | | L2 | Port_A | 4 | UART1 | UART core 0 | - | | (L2D) | Port_B | 4 | UART2 | UART core 1 | - | +-----------------+---------------+------------+--------+-------------+ - | | L3 | Port_A | 4 | UART1 | UART core 0 | - | | (L3D) | Port_B | 2 | UART2 | UART core 1 | - | | | Port_C | 2 | UART3 | UART core 2 | - | +-----------------+---------------+------------+--------+-------------+ - | | | Port_A | 2 | UART1 | UART core 0 | - | | L4 | Port_B | 2 | UART2 | UART core 1 | - | | (L4D) | Port_C | 2 | UART3 | UART core 2 | - | | | Port_D | 2 | UART4 | UART core 3 | - | +-----------------+---------------+------------+--------+-------------+ - | - | Involved GPIOs - | - | +------------------------------------------------------------------------------+ - | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O | - | +---------+------------------+-----+-----------------+-----+-------------+-----+ - | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O | - | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I | - | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I | - | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O | - | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA | - | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA | - | +------------------------------------------------------------------------------+ - | - | - +----------------------------------------------------------------------------*/ - -void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - switch (uart_config) - { - case L1: - /* ----------------------------------------------------------------------- */ - /* L1 configuration: UART0 = 8 pins */ - /* ----------------------------------------------------------------------- */ - /* Update GPIO Configuration Table */ - gpio_tab[GPIO1][2].in_out = GPIO_IN; - gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][3].in_out = GPIO_IN; - gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][4].in_out = GPIO_IN; - gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][5].in_out = GPIO_OUT; - gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][6].in_out = GPIO_OUT; - gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][7].in_out = GPIO_IN; - gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1; - - break; - - case L2: - /* ----------------------------------------------------------------------- */ - /* L2 configuration: UART0 = 4 pins */ - /* UART1 = 4 pins */ - /* ----------------------------------------------------------------------- */ - /* Update GPIO Configuration Table */ - gpio_tab[GPIO1][2].in_out = GPIO_IN; - gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO1][3].in_out = GPIO_OUT; - gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO1][4].in_out = GPIO_IN; - gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][5].in_out = GPIO_OUT; - gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][6].in_out = GPIO_OUT; - gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO1][7].in_out = GPIO_IN; - gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2; - - break; - - case L3: - /* ----------------------------------------------------------------------- */ - /* L3 configuration: UART0 = 4 pins */ - /* UART1 = 2 pins */ - /* UART2 = 2 pins */ - /* ----------------------------------------------------------------------- */ - /* Update GPIO Configuration Table */ - gpio_tab[GPIO1][2].in_out = GPIO_OUT; - gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3; - - gpio_tab[GPIO1][3].in_out = GPIO_IN; - gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3; - - gpio_tab[GPIO1][4].in_out = GPIO_IN; - gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][5].in_out = GPIO_OUT; - gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][6].in_out = GPIO_OUT; - gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO1][7].in_out = GPIO_IN; - gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2; - - break; - - case L4: - /* ----------------------------------------------------------------------- */ - /* L4 configuration: UART0 = 2 pins */ - /* UART1 = 2 pins */ - /* UART2 = 2 pins */ - /* UART3 = 2 pins */ - /* ----------------------------------------------------------------------- */ - /* Update GPIO Configuration Table */ - gpio_tab[GPIO1][2].in_out = GPIO_OUT; - gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3; - - gpio_tab[GPIO1][3].in_out = GPIO_IN; - gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3; - - gpio_tab[GPIO1][4].in_out = GPIO_IN; - gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3; - - gpio_tab[GPIO1][5].in_out = GPIO_OUT; - gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3; - - gpio_tab[GPIO1][6].in_out = GPIO_OUT; - gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO1][7].in_out = GPIO_IN; - gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2; - - break; - - default: - /* Unsupported UART configuration number */ - printf("ERROR - Unsupported UART configuration number.\n\n"); - for (;;) - ; - break; - - } - - /* Set input Selection Register on Alt_Receive for UART Input Core */ - out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000)); - out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000)); - out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000)); -} - -/*----------------------------------------------------------------------------+ - | update_ndfc_ios(void). - +----------------------------------------------------------------------------*/ -void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - /* Update GPIO Configuration Table */ - gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */ - gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */ - gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1; - -#if 0 - gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */ - gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1; -#endif -} - -/*----------------------------------------------------------------------------+ - | update_zii_ios(void). - +----------------------------------------------------------------------------*/ -void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - /* Update GPIO Configuration Table */ - gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */ - gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */ - gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */ - gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */ - gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */ - gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */ - gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */ - gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */ - gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */ - gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */ - gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */ - gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */ - gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */ - gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */ - gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1; - -} - -/*----------------------------------------------------------------------------+ - | update_uic_0_3_irq_ios(). - +----------------------------------------------------------------------------*/ -void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */ - gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */ - gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */ - gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */ - gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1; -} - -/*----------------------------------------------------------------------------+ - | update_uic_4_9_irq_ios(). - +----------------------------------------------------------------------------*/ -void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */ - gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */ - gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */ - gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */ - gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */ - gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1; -} - -/*----------------------------------------------------------------------------+ - | update_dma_a_b_ios(). - +----------------------------------------------------------------------------*/ -void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */ - gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */ - gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */ - gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */ - gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */ - gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2; -} - -/*----------------------------------------------------------------------------+ - | update_dma_c_d_ios(). - +----------------------------------------------------------------------------*/ -void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */ - gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */ - gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */ - gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */ - gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */ - gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */ - gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2; - -} - -/*----------------------------------------------------------------------------+ - | update_ebc_master_ios(). - +----------------------------------------------------------------------------*/ -void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */ - gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */ - gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */ - gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */ - gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1; -} - -/*----------------------------------------------------------------------------+ - | update_usb2_device_ios(). - +----------------------------------------------------------------------------*/ -void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */ - gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */ - gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */ - gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */ - gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */ - gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */ - gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */ - gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */ - gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1; - -} - -/*----------------------------------------------------------------------------+ - | update_pci_patch_ios(). - +----------------------------------------------------------------------------*/ -void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */ - gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1; -} - -/*----------------------------------------------------------------------------+ - | set_chip_gpio_configuration(unsigned char gpio_core, - | gpio_param_s (*gpio_tab)[GPIO_MAX]) - | Put the core impacted by clock modification and sharing in reset. - | Config the select registers to resolve the sharing depending of the config. - | Configure the GPIO registers. - | - +----------------------------------------------------------------------------*/ -void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - unsigned char i=0, j=0, reg_offset = 0; - unsigned long gpio_reg, gpio_core_add; - - /* GPIO config of the GPIOs 0 to 31 */ - for (i=0; i<GPIO_MAX; i++, j++) - { - if (i == GPIO_MAX/2) - { - reg_offset = 4; - j = i-16; - } - - gpio_core_add = gpio_tab[gpio_core][i].add; - - if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) || - (gpio_tab[gpio_core][i].in_out == GPIO_BI )) - { - switch (gpio_tab[gpio_core][i].alt_nb) - { - case GPIO_SEL: - break; - - case GPIO_ALT1: - gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); - out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg); - break; - - case GPIO_ALT2: - gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); - out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg); - break; - - case GPIO_ALT3: - gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); - out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg); - break; - } - } - if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) || - (gpio_tab[gpio_core][i].in_out == GPIO_BI )) - { - - switch (gpio_tab[gpio_core][i].alt_nb) - { - case GPIO_SEL: - break; - case GPIO_ALT1: - gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); - out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); - gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); - out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); - break; - case GPIO_ALT2: - gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); - out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); - gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); - out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); - break; - case GPIO_ALT3: - gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); - out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); - gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); - out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); - break; - } - } - } -} - -/*----------------------------------------------------------------------------+ - | force_bup_core_selection. - +----------------------------------------------------------------------------*/ -void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P) -{ - /* Pointer invalid */ - if (core_select_P == NULL) - { - printf("Configuration invalid pointer 1\n"); - for (;;) - ; - } - - /* L4 Selection */ - *(core_select_P+UART_CORE0) = CORE_SELECTED; - *(core_select_P+UART_CORE1) = CORE_SELECTED; - *(core_select_P+UART_CORE2) = CORE_SELECTED; - *(core_select_P+UART_CORE3) = CORE_SELECTED; - - /* RMII Selection */ - *(core_select_P+RMII_SEL) = CORE_SELECTED; - - /* External Interrupt 0-9 selection */ - *(core_select_P+UIC_0_3) = CORE_SELECTED; - *(core_select_P+UIC_4_9) = CORE_SELECTED; - - *(core_select_P+SCP_CORE) = CORE_SELECTED; - *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED; - *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED; - *(core_select_P+USB1_DEVICE) = CORE_SELECTED; - - if (is_nand_selected()) { - *(core_select_P+NAND_FLASH) = CORE_SELECTED; - } - - *config_val_P = CONFIG_IS_VALID; - -} - -/*----------------------------------------------------------------------------+ - | configure_ppc440ep_pins. - +----------------------------------------------------------------------------*/ -void configure_ppc440ep_pins(void) -{ - uart_config_nb_t uart_configuration; - config_validity_t config_val = CONFIG_IS_INVALID; - - /* Create Core Selection Table */ - core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] = - { - CORE_NOT_SELECTED, /* IIC_CORE, */ - CORE_NOT_SELECTED, /* SPC_CORE, */ - CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */ - CORE_NOT_SELECTED, /* UIC_4_9, */ - CORE_NOT_SELECTED, /* USB2_HOST, */ - CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */ - CORE_NOT_SELECTED, /* USB2_DEVICE, */ - CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */ - CORE_NOT_SELECTED, /* USB1_DEVICE, */ - CORE_NOT_SELECTED, /* EBC_MASTER, */ - CORE_NOT_SELECTED, /* NAND_FLASH, */ - CORE_NOT_SELECTED, /* UART_CORE0, */ - CORE_NOT_SELECTED, /* UART_CORE1, */ - CORE_NOT_SELECTED, /* UART_CORE2, */ - CORE_NOT_SELECTED, /* UART_CORE3, */ - CORE_NOT_SELECTED, /* MII_SEL, */ - CORE_NOT_SELECTED, /* RMII_SEL, */ - CORE_NOT_SELECTED, /* SMII_SEL, */ - CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */ - CORE_NOT_SELECTED, /* UIC_0_3 */ - CORE_NOT_SELECTED, /* USB1_HOST */ - CORE_NOT_SELECTED /* PCI_PATCH */ - }; - - gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX]; - - /* Table Default Initialisation + FPGA Access */ - init_default_gpio(gpio_tab); - set_chip_gpio_configuration(GPIO0, gpio_tab); - set_chip_gpio_configuration(GPIO1, gpio_tab); - - /* Update Table */ - force_bup_core_selection(ppc440ep_core_selection, &config_val); -#if 0 /* test-only */ - /* If we are running PIBS 1, force known configuration */ - update_core_selection_table(ppc440ep_core_selection, &config_val); -#endif - - /*----------------------------------------------------------------------------+ - | SDR + ios table update + fpga initialization - +----------------------------------------------------------------------------*/ - unsigned long sdr0_pfc1 = 0; - unsigned long sdr0_usb0 = 0; - unsigned long sdr0_mfr = 0; - - /* PCI Always selected */ - - /* I2C Selection */ - if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED) - { - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL; - iic1_selection_in_fpga(); - } - - /* SCP Selection */ - if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED) - { - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL; - scp_selection_in_fpga(); - } - - /* UIC 0:3 Selection */ - if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED) - { - update_uic_0_3_irq_ios(gpio_tab); - dma_a_b_unselect_in_fpga(); - } - - /* UIC 4:9 Selection */ - if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED) - { - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL; - update_uic_4_9_irq_ios(gpio_tab); - } - - /* DMA AB Selection */ - if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED) - { - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL; - update_dma_a_b_ios(gpio_tab); - dma_a_b_selection_in_fpga(); - } - - /* DMA CD Selection */ - if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED) - { - update_dma_c_d_ios(gpio_tab); - dma_c_d_selection_in_fpga(); - } - - /* EBC Master Selection */ - if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED) - { - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL; - update_ebc_master_ios(gpio_tab); - } - - /* PCI Patch Enable */ - if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED) - { - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL; - update_pci_patch_ios(gpio_tab); - } - - /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */ - if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED) - { - /* Not Implemented in PowerPC 440EP Pass1-Pass2 */ - printf("Invalid configuration => USB2 Host selected\n"); - for (;;) - ; - /*usb2_host_selection_in_fpga(); */ - } - - /* USB2.0 Device Selection */ - if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED) - { - update_usb2_device_ios(gpio_tab); - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE; - - mfsdr(SDR0_USB0, sdr0_usb0); - sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK; - sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL; - mtsdr(SDR0_USB0, sdr0_usb0); - - usb2_device_selection_in_fpga(); - } - - /* USB1.1 Device Selection */ - if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED) - { - mfsdr(SDR0_USB0, sdr0_usb0); - sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK; - sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL; - mtsdr(SDR0_USB0, sdr0_usb0); - } - - /* USB1.1 Host Selection */ - if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED) - { - mfsdr(SDR0_USB0, sdr0_usb0); - sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK; - sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE; - mtsdr(SDR0_USB0, sdr0_usb0); - } - - /* NAND Flash Selection */ - if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED) - { - update_ndfc_ios(gpio_tab); - mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL | - SDR0_CUST0_NDFC_ENABLE | - SDR0_CUST0_NDFC_BW_8_BIT | - SDR0_CUST0_NDFC_ARE_MASK | - SDR0_CUST0_CHIPSELGAT_EN1 | - SDR0_CUST0_CHIPSELGAT_EN2); - ndfc_selection_in_fpga(); - } - else - { - /* Set Mux on EMAC */ - mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_EMAC_SEL); - } - - /* MII Selection */ - if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED) - { - update_zii_ios(gpio_tab); - mfsdr(SDR0_MFR, sdr0_mfr); - sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII; - mtsdr(SDR0_MFR, sdr0_mfr); - - set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII); - } - - /* RMII Selection */ - if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED) - { - update_zii_ios(gpio_tab); - mfsdr(SDR0_MFR, sdr0_mfr); - sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; - mtsdr(SDR0_MFR, sdr0_mfr); - - set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII); - } - - /* SMII Selection */ - if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED) - { - update_zii_ios(gpio_tab); - mfsdr(SDR0_MFR, sdr0_mfr); - sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII; - mtsdr(SDR0_MFR, sdr0_mfr); - - set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII); - } - - /* UART Selection */ - uart_configuration = get_uart_configuration(); - switch (uart_configuration) - { - case L1: /* L1 Selection */ - /* UART0 8 pins Only */ - /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS; - break; - case L2: /* L2 Selection */ - /* UART0 and UART1 4 pins */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; - break; - case L3: /* L3 Selection */ - /* UART0 4 pins, UART1 and UART2 2 pins */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; - break; - case L4: /* L4 Selection */ - /* UART0, UART1, UART2 and UART3 2 pins */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; - break; - } - update_uart_ios(uart_configuration, gpio_tab); - - /* UART Selection in all cases */ - uart_selection_in_fpga(uart_configuration); - - /* Packet Reject Function Available */ - if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED) - { - /* Set UPR Bit in SDR0_PFC1 Register */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE; - } - - /* Packet Reject Function Enable */ - if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED) - { - mfsdr(SDR0_MFR, sdr0_mfr); - sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;; - mtsdr(SDR0_MFR, sdr0_mfr); - } - - /* Perform effective access to hardware */ - mtsdr(SDR0_PFC1, sdr0_pfc1); - set_chip_gpio_configuration(GPIO0, gpio_tab); - set_chip_gpio_configuration(GPIO1, gpio_tab); - - /* USB2.0 Device Reset must be done after GPIO setting */ - if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED) - usb2_device_reset_through_fpga(); - -} diff --git a/qemu/roms/u-boot/board/amcc/bamboo/bamboo.h b/qemu/roms/u-boot/board/amcc/bamboo/bamboo.h deleted file mode 100644 index 49f200aa0..000000000 --- a/qemu/roms/u-boot/board/amcc/bamboo/bamboo.h +++ /dev/null @@ -1,348 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*----------------------------------------------------------------------------+ - | FPGA registers and bit definitions - +----------------------------------------------------------------------------*/ -/* - * PowerPC 440EP Board FPGA is reached with physical address 0x80001FF0. - * TLB initialization makes it correspond to logical address 0x80001FF0. - * => Done init_chip.s in bootlib - */ -#define FPGA_BASE_ADDR 0x80002000 - -/*----------------------------------------------------------------------------+ - | Board Jumpers Setting Register - | Board Settings provided by jumpers - +----------------------------------------------------------------------------*/ -#define FPGA_SETTING_REG (FPGA_BASE_ADDR+0x3) -/* Boot from small flash */ -#define FPGA_SET_REG_BOOT_SMALL_FLASH 0x80 -/* Operational Flash versus SRAM position in Memory Map */ -#define FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK 0x40 -#define FPGA_SET_REG_OP_CODE_FLASH_ABOVE 0x40 -#define FPGA_SET_REG_SRAM_ABOVE 0x00 -/* Boot From NAND Flash */ -#define FPGA_SET_REG_BOOT_NAND_FLASH_MASK 0x40 -#define FPGA_SET_REG_BOOT_NAND_FLASH_SELECT 0x00 -/* On Board PCI Arbiter Select */ -#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK 0x10 -#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL 0x00 - -/*----------------------------------------------------------------------------+ - | Functions Selection Register 1 - +----------------------------------------------------------------------------*/ -#define FPGA_SELECTION_1_REG (FPGA_BASE_ADDR+0x4) -#define FPGA_SEL_1_REG_PHY_MASK 0xE0 -#define FPGA_SEL_1_REG_MII 0x80 -#define FPGA_SEL_1_REG_RMII 0x40 -#define FPGA_SEL_1_REG_SMII 0x20 -#define FPGA_SEL_1_REG_USB2_DEV_SEL 0x10 /* USB2 Device Selection */ -#define FPGA_SEL_1_REG_USB2_HOST_SEL 0x08 /* USB2 Host Selection */ -#define FPGA_SEL_1_REG_NF_SELEC_MASK 0x07 /* NF Selection Mask */ -#define FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04 /* NF0 Selected by NF_CS1 */ -#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02 /* NF1 Selected by NF_CS2 */ -#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01 /* NF1 Selected by NF_CS3 */ - -/*----------------------------------------------------------------------------+ - | Functions Selection Register 2 - +----------------------------------------------------------------------------*/ -#define FPGA_SELECTION_2_REG (FPGA_BASE_ADDR+0x5) -#define FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80 /* IIC1 / SCP Selection */ -#define FPGA_SEL2_REG_SEL_FRAM 0x80 /* FRAM on IIC1 bus selected - SCP Select */ -#define FPGA_SEL2_REG_SEL_SCP 0x80 /* Identical to SCP Selection */ -#define FPGA_SEL2_REG_SEL_IIC1 0x00 /* IIC1 Selection - Default Value */ -#define FPGA_SEL2_REG_SEL_DMA_A_B 0x40 /* DMA A & B channels selected */ -#define FPGA_SEL2_REG_SEL_DMA_C_D 0x20 /* DMA C & D channels selected */ -#define FPGA_SEL2_REG_DMA_EOT_TC_3_SEL 0x10 /* 0 = EOT - input to 440EP */ - /* 1 = TC - output from 440EP */ -#define FPGA_SEL2_REG_DMA_EOT_TC_2_SEL 0x08 /* 0 = EOT (input to 440EP) */ - /* 1 = TC (output from 440EP) */ -#define FPGA_SEL2_REG_SEL_GPIO_1 0x04 /* EBC_GPIO & USB2_GPIO selected */ -#define FPGA_SEL2_REG_SEL_GPIO_2 0x02 /* Ether._GPIO & UART_GPIO selected */ -#define FPGA_SEL2_REG_SEL_GPIO_3 0x01 /* DMA_GPIO & Trace_GPIO selected */ - -/*----------------------------------------------------------------------------+ - | Functions Selection Register 3 - +----------------------------------------------------------------------------*/ -#define FPGA_SELECTION_3_REG (FPGA_BASE_ADDR+0x6) -#define FPGA_SEL3_REG_EXP_SLOT_EN 0x80 /* Expansion Slot enabled */ -#define FPGA_SEL3_REG_SEL_UART_CONFIG_MASK 0x70 -#define FPGA_SEL3_REG_SEL_UART_CONFIG1 0x40 /* one 8_pin UART */ -#define FPGA_SEL3_REG_SEL_UART_CONFIG2 0x20 /* two 4_pin UARTs */ -#define FPGA_SEL3_REG_SEL_UART_CONFIG3 0x10 /* one 4_pin & two 2_pin UARTs */ -#define FPGA_SEL3_REG_SEL_UART_CONFIG4 0x08 /* four 2_pin UARTs */ -#define FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART 0x00 /* DTR/DSR mode for 4_pin_UART */ -#define FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART 0x04 /* RTS/CTS mode for 4_pin_UART */ - -/*----------------------------------------------------------------------------+ - | Soft Reset Register - +----------------------------------------------------------------------------*/ -#define FPGA_RESET_REG (FPGA_BASE_ADDR+0x7) -#define FPGA_RESET_REG_RESET_USB20_DEV 0x80 /* Hard Reset of the GT3200 */ -#define FPGA_RESET_REG_RESET_DISPLAY 0x40 /* Hard Reset on Display Device */ -#define FPGA_RESET_REG_STATUS_LED_0 0x08 /* 1 = Led On */ -#define FPGA_RESET_REG_STATUS_LED_1 0x04 /* 1 = Led On */ -#define FPGA_RESET_REG_STATUS_LED_2 0x02 /* 1 = Led On */ -#define FPGA_RESET_REG_STATUS_LED_3 0x01 /* 1 = Led On */ - - -/*----------------------------------------------------------------------------+ -| SDR Configuration registers -+----------------------------------------------------------------------------*/ -#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */ -#define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */ -#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */ -#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */ - -#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00001800 /* Boot device Selection Mask */ -#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */ -#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00000800 /* PCI */ -#define SDR0_SDSTP1_BOOT_SEL_NDFC 0x00001000 /* NDFC */ - -/* Serial Device Enabled - Addr = 0xA8 */ -#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 -/* Serial Device Enabled - Addr = 0xA4 */ -#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 - -/* Pin Straps Reg */ -#define SDR0_PSTRP0 0x0040 -#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */ - -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */ - -/*----------------------------------------------------------------------------+ -| EBC Configuration Register - EBC0_CFG -+----------------------------------------------------------------------------*/ -/* External Bus Three-State Control */ -#define EBC0_CFG_EBTC_DRIVEN 0x80000000 -/* Device-Paced Time-out Disable */ -#define EBC0_CFG_PTD_ENABLED 0x00000000 -/* Ready Timeout Count */ -#define EBC0_CFG_RTC_MASK 0x38000000 -#define EBC0_CFG_RTC_16PERCLK 0x00000000 -#define EBC0_CFG_RTC_32PERCLK 0x08000000 -#define EBC0_CFG_RTC_64PERCLK 0x10000000 -#define EBC0_CFG_RTC_128PERCLK 0x18000000 -#define EBC0_CFG_RTC_256PERCLK 0x20000000 -#define EBC0_CFG_RTC_512PERCLK 0x28000000 -#define EBC0_CFG_RTC_1024PERCLK 0x30000000 -#define EBC0_CFG_RTC_2048PERCLK 0x38000000 -/* External Master Priority Low */ -#define EBC0_CFG_EMPL_LOW 0x00000000 -#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000 -#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000 -#define EBC0_CFG_EMPL_HIGH 0x06000000 -/* External Master Priority High */ -#define EBC0_CFG_EMPH_LOW 0x00000000 -#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000 -#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000 -#define EBC0_CFG_EMPH_HIGH 0x01800000 -/* Chip Select Three-State Control */ -#define EBC0_CFG_CSTC_DRIVEN 0x00400000 -/* Burst Prefetch */ -#define EBC0_CFG_BPF_ONEDW 0x00000000 -#define EBC0_CFG_BPF_TWODW 0x00100000 -#define EBC0_CFG_BPF_FOURDW 0x00200000 -/* External Master Size */ -#define EBC0_CFG_EMS_8BIT 0x00000000 -/* Power Management Enable */ -#define EBC0_CFG_PME_DISABLED 0x00000000 -#define EBC0_CFG_PME_ENABLED 0x00020000 -/* Power Management Timer */ -#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) - -/*----------------------------------------------------------------------------+ -| Peripheral Bank Configuration Register - EBC0_BnCR -+----------------------------------------------------------------------------*/ -/* BAS - Base Address Select */ -#define EBC0_BNCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0) -/* BS - Bank Size */ -#define EBC0_BNCR_BS_MASK 0x000E0000 -#define EBC0_BNCR_BS_1MB 0x00000000 -#define EBC0_BNCR_BS_2MB 0x00020000 -#define EBC0_BNCR_BS_4MB 0x00040000 -#define EBC0_BNCR_BS_8MB 0x00060000 -#define EBC0_BNCR_BS_16MB 0x00080000 -#define EBC0_BNCR_BS_32MB 0x000A0000 -#define EBC0_BNCR_BS_64MB 0x000C0000 -#define EBC0_BNCR_BS_128MB 0x000E0000 -/* BU - Bank Usage */ -#define EBC0_BNCR_BU_MASK 0x00018000 -#define EBC0_BNCR_BU_RO 0x00008000 -#define EBC0_BNCR_BU_WO 0x00010000 -#define EBC0_BNCR_BU_RW 0x00018000 -/* BW - Bus Width */ -#define EBC0_BNCR_BW_MASK 0x00006000 -#define EBC0_BNCR_BW_8BIT 0x00000000 -#define EBC0_BNCR_BW_16BIT 0x00002000 -#define EBC0_BNCR_BW_32BIT 0x00004000 - -/*----------------------------------------------------------------------------+ -| Peripheral Bank Access Parameters - EBC0_BnAP -+----------------------------------------------------------------------------*/ -/* Burst Mode Enable */ -#define EBC0_BNAP_BME_ENABLED 0x80000000 -#define EBC0_BNAP_BME_DISABLED 0x00000000 -/* Transfert Wait */ -#define EBC0_BNAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) /* Bits 1:8 */ -/* Chip Select On Timing */ -#define EBC0_BNAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) /* Bits 12:13 */ -/* Output Enable On Timing */ -#define EBC0_BNAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) /* Bits 14:15 */ -/* Write Back Enable On Timing */ -#define EBC0_BNAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) /* Bits 16:17 */ -/* Write Back Enable Off Timing */ -#define EBC0_BNAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) /* Bits 18:19 */ -/* Transfert Hold */ -#define EBC0_BNAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) /* Bits 20:22 */ -/* PerReady Enable */ -#define EBC0_BNAP_RE_ENABLED 0x00000100 -#define EBC0_BNAP_RE_DISABLED 0x00000000 -/* Sample On Ready */ -#define EBC0_BNAP_SOR_DELAYED 0x00000000 -#define EBC0_BNAP_SOR_NOT_DELAYED 0x00000080 -/* Byte Enable Mode */ -#define EBC0_BNAP_BEM_WRITEONLY 0x00000000 -#define EBC0_BNAP_BEM_RW 0x00000040 -/* Parity Enable */ -#define EBC0_BNAP_PEN_DISABLED 0x00000000 -#define EBC0_BNAP_PEN_ENABLED 0x00000020 - -/*----------------------------------------------------------------------------+ -| Define Boot devices -+----------------------------------------------------------------------------*/ -/* */ -#define BOOT_FROM_SMALL_FLASH 0x00 -#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01 -#define BOOT_FROM_NAND_FLASH0 0x02 -#define BOOT_FROM_PCI 0x03 -#define BOOT_DEVICE_UNKNOWN 0x04 - - -#define PVR_POWERPC_440EP_PASS1 0x42221850 -#define PVR_POWERPC_440EP_PASS2 0x422218D3 - -#define GPIO0 0 -#define GPIO1 1 - -/*#define MAX_SELECTION_NB CORE_NB */ -#define MAX_CORE_SELECT_NB 22 - -/*----------------------------------------------------------------------------+ - | PPC440EP GPIOs addresses. - +----------------------------------------------------------------------------*/ -#define GPIO0_REAL 0xEF600B00 - -#define GPIO1_REAL 0xEF600C00 - -/* Offsets */ -#define GPIOx_OR 0x00 /* GPIO Output Register */ -#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */ -#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */ -#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */ -#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */ -#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */ -#define GPIOx_ODR 0x18 /* GPIO Open drain Register */ -#define GPIOx_IR 0x1C /* GPIO Input Register */ -#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */ -#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */ -#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */ -#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */ -#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */ -#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */ -#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */ -#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */ -#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */ - -/* GPIO0 */ -#define GPIO0_IS1L (GPIO0_BASE+GPIOx_IS1L) -#define GPIO0_IS1H (GPIO0_BASE+GPIOx_IS1H) -#define GPIO0_IS2L (GPIO0_BASE+GPIOx_IS2L) -#define GPIO0_IS2H (GPIO0_BASE+GPIOx_IS2H) -#define GPIO0_IS3L (GPIO0_BASE+GPIOx_IS3L) -#define GPIO0_IS3H (GPIO0_BASE+GPIOx_IS3L) - -/* GPIO1 */ -#define GPIO1_IS1L (GPIO1_BASE+GPIOx_IS1L) -#define GPIO1_IS1H (GPIO1_BASE+GPIOx_IS1H) -#define GPIO1_IS2L (GPIO1_BASE+GPIOx_IS2L) -#define GPIO1_IS2H (GPIO1_BASE+GPIOx_IS2H) -#define GPIO1_IS3L (GPIO1_BASE+GPIOx_IS3L) -#define GPIO1_IS3H (GPIO1_BASE+GPIOx_IS3L) - -#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */ -#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */ -#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */ -#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */ -#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */ - - -/*----------------------------------------------------------------------------+ - | XX XX - | - | XXXXXX XXX XX XXX XXX - | XX XX X XX XX XX - | XX XX X XX XX XX - | XX XX XX XX XX - | XXXXXX XXX XXX XXXX XXXX - +----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------+ - | Defines - +----------------------------------------------------------------------------*/ -typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN, - ZMII_CONFIGURATION_IS_MII, - ZMII_CONFIGURATION_IS_RMII, - ZMII_CONFIGURATION_IS_SMII -} zmii_config_t; - -/*----------------------------------------------------------------------------+ - | Declare Configuration values - +----------------------------------------------------------------------------*/ -typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t; -typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t; -typedef enum config_list { IIC_CORE, - SCP_CORE, - DMA_CHANNEL_AB, - UIC_4_9, - USB2_HOST, - DMA_CHANNEL_CD, - USB2_DEVICE, - PACKET_REJ_FUNC_AVAIL, - USB1_DEVICE, - EBC_MASTER, - NAND_FLASH, - UART_CORE0, - UART_CORE1, - UART_CORE2, - UART_CORE3, - MII_SEL, - RMII_SEL, - SMII_SEL, - PACKET_REJ_FUNC_EN, - UIC_0_3, - USB1_HOST, - PCI_PATCH, - CORE_NB -} core_list_t; - -typedef enum block3_value { B3_V1, B3_V2, B3_V3, B3_V4, B3_V5, - B3_V6, B3_V7, B3_V8, B3_V9, B3_V10, - B3_V11, B3_V12, B3_V13, B3_V14, B3_V15, - B3_V16, B3_VALUE_UNKNOWN -} block3_value_t; - -typedef enum config_validity { CONFIG_IS_VALID, - CONFIG_IS_INVALID -} config_validity_t; diff --git a/qemu/roms/u-boot/board/amcc/bamboo/config.mk b/qemu/roms/u-boot/board/amcc/bamboo/config.mk deleted file mode 100644 index 9cb071e45..000000000 --- a/qemu/roms/u-boot/board/amcc/bamboo/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2002-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/qemu/roms/u-boot/board/amcc/bamboo/flash.c b/qemu/roms/u-boot/board/amcc/bamboo/flash.c deleted file mode 100644 index 6dbe09f91..000000000 --- a/qemu/roms/u-boot/board/amcc/bamboo/flash.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * (C) Copyright 2004-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> - * Add support for Am29F016D and dynamic switch setting. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include <asm/ppc440.h> -#include "bamboo.h" - -#undef DEBUG - -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0 - */ -static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = { - {0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */ - {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */ - {0x87800001, 0x00000000, 0x00000000}, /* 0:boot from nand flash */ - {0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/ - {0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/ - {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */ - {0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */ - {0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */ - {0x87C00001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */ -}; - -/* - * include common flash code (for amcc boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_word(flash_info_t * info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - unsigned long total_b = 0; - unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; - unsigned short index = 0; - int i; - unsigned long val; - unsigned long ebc_boot_size; - unsigned long boot_selection; - - mfsdr(SDR0_PINSTP, val); - index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 29; - - if ((index == 5) || (index == 7)) { - /* - * Boot Settings in IIC EEprom address 0xA8 or 0xA4 - * Read Serial Device Strap Register1 in PPC440EP - */ - mfsdr(SDR0_SDSTP1, val); - boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK; - ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK; - - switch(boot_selection) { - case SDR0_SDSTP1_BOOT_SEL_EBC: - switch(ebc_boot_size) { - case SDR0_SDSTP1_EBC_ROM_BS_16BIT: - index = 3; - break; - case SDR0_SDSTP1_EBC_ROM_BS_8BIT: - index = 0; - break; - } - break; - - case SDR0_SDSTP1_BOOT_SEL_PCI: - index = 1; - break; - - case SDR0_SDSTP1_BOOT_SEL_NDFC: - index = 2; - break; - } - } else if (index == 0) { - if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE) { - index = 8; /* sram below op code flash -> new index 8 */ - } - } - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - - /* check whether the address is 0 */ - if (flash_addr_table[index][i] == 0) - continue; - - DEBUGF("Detection bank %d...\n", i); - /* call flash_get_size() to initialize sector address */ - size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], - &flash_info[i]); - flash_info[i].size = size_b[i]; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i] << 20); - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - } - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[i]); -#if defined(CONFIG_ENV_IS_IN_FLASH) - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[i]); -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR_REDUND) - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[i]); -#endif -#endif - - total_b += flash_info[i].size; - } - - return total_b; -} diff --git a/qemu/roms/u-boot/board/amcc/bamboo/init.S b/qemu/roms/u-boot/board/amcc/bamboo/init.S deleted file mode 100644 index 5c7c83907..000000000 --- a/qemu/roms/u-boot/board/amcc/bamboo/init.S +++ /dev/null @@ -1,55 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G) - - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G) - - /* PCI base & peripherals */ - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I) - tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_RWX | SA_W|SA_I) - - /* PCI */ - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG) - - /* USB 2.0 Device */ - tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG) - - tlbtab_end diff --git a/qemu/roms/u-boot/board/amcc/bluestone/Makefile b/qemu/roms/u-boot/board/amcc/bluestone/Makefile deleted file mode 100644 index 07320ce42..000000000 --- a/qemu/roms/u-boot/board/amcc/bluestone/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (c) 2010, Applied Micro Circuits Corporation -# Author: Tirumala R Marri <tmarri@apm.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := bluestone.o -extra-y += init.o diff --git a/qemu/roms/u-boot/board/amcc/bluestone/bluestone.c b/qemu/roms/u-boot/board/amcc/bluestone/bluestone.c deleted file mode 100644 index 6520f75c6..000000000 --- a/qemu/roms/u-boot/board/amcc/bluestone/bluestone.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Bluestone board support - * - * Copyright (c) 2010, Applied Micro Circuits Corporation - * Author: Tirumala R Marri <tmarri@apm.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/apm821xx.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <i2c.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/mmu.h> -#include <asm/ppc4xx-gpio.h> - -int board_early_init_f(void) -{ - /* - * Setup the interrupt controller polarities, triggers, etc. - */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(UIC2ER, 0x00000000); /* disable all */ - mtdcr(UIC2CR, 0x00000000); /* all non-critical */ - mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - mtdcr(UIC3ER, 0x00000000); /* disable all */ - mtdcr(UIC3CR, 0x00000000); /* all non-critical */ - mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - - /* - * Configure PFC (Pin Function Control) registers - * UART0: 2 pins - */ - mtsdr(SDR0_PFC1, 0x0000000); - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: Bluestone Evaluation Board"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -int misc_init_r(void) -{ - u32 sdr0_srst1 = 0; - - /* Setup PLB4-AHB bridge based on the system address map */ - mtdcr(AHB_TOP, 0x8000004B); - mtdcr(AHB_BOT, 0x8000004B); - - /* - * The AHB Bridge core is held in reset after power-on or reset - * so enable it now - */ - mfsdr(SDR0_SRST1, sdr0_srst1); - sdr0_srst1 &= ~SDR0_SRST1_AHB; - mtsdr(SDR0_SRST1, sdr0_srst1); - - return 0; -} diff --git a/qemu/roms/u-boot/board/amcc/bluestone/config.mk b/qemu/roms/u-boot/board/amcc/bluestone/config.mk deleted file mode 100644 index a947e82af..000000000 --- a/qemu/roms/u-boot/board/amcc/bluestone/config.mk +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (c) 2010, Applied Micro Circuits Corporation -# Author: Tirumala R Marri <tmarri@apm.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Applied Micro APM821XX Evaluation board. -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/qemu/roms/u-boot/board/amcc/bluestone/init.S b/qemu/roms/u-boot/board/amcc/bluestone/init.S deleted file mode 100644 index cf22ca634..000000000 --- a/qemu/roms/u-boot/board/amcc/bluestone/init.S +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2010, Applied Micro Circuits Corporation - * Author: Tirumala R Marri <tmarri@apm.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> -#include <asm/ppc4xx.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* TLB 0 */ - tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, - 4, AC_RWX | SA_G) - - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, - 0, AC_RWX | SA_G) - - /* TLB-entry for OCM */ - tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4, - AC_RWX | SA_I) - - /* TLB-entry for Local Configuration registers => peripherals */ - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, - CONFIG_SYS_PERIPHERAL_BASE, 4, AC_RWX | SA_IG) - tlbtab_end diff --git a/qemu/roms/u-boot/board/amcc/bubinga/Makefile b/qemu/roms/u-boot/board/amcc/bubinga/Makefile deleted file mode 100644 index 0e7ebcaed..000000000 --- a/qemu/roms/u-boot/board/amcc/bubinga/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = bubinga.o flash.o diff --git a/qemu/roms/u-boot/board/amcc/bubinga/bubinga.c b/qemu/roms/u-boot/board/amcc/bubinga/bubinga.c deleted file mode 100644 index 5c1e0717a..000000000 --- a/qemu/roms/u-boot/board/amcc/bubinga/bubinga.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> - -long int spd_sdram(void); - -int board_early_init_f(void) -{ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000010); - mtdcr(UIC0PR, 0xFFFF7FF0); /* set int polarities */ - mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * Configure CPC0_PCI to enable PerWE as output - * and enable the internal PCI arbiter if selected - */ - if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB) - mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); - else - mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN); - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: Bubinga - AMCC PPC405EP Evaluation Board"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- - initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of - the necessary info for SDRAM controller configuration - ------------------------------------------------------------------------- */ -phys_size_t initdram(int board_type) -{ - long int ret; - - ret = spd_sdram(); - return ret; -} diff --git a/qemu/roms/u-boot/board/amcc/bubinga/flash.c b/qemu/roms/u-boot/board/amcc/bubinga/flash.c deleted file mode 100644 index a9d0ed8d1..000000000 --- a/qemu/roms/u-boot/board/amcc/bubinga/flash.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -/* - * include common flash code (for amcc boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static void flash_get_offsets(ulong base, flash_info_t * info); - -unsigned long flash_init(void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = - flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - /* Only one bank */ - if (CONFIG_SYS_MAX_FLASH_BANKS == 1) { - /* Setup offsets */ - flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]); - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[0]); -#ifdef CONFIG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - size_b1 = 0; - flash_info[0].size = size_b0; - } - - /* 2 banks */ - else { - size_b1 = - flash_get_size((vu_long *) FLASH_BASE1_PRELIM, - &flash_info[1]); - - /* Re-do sizing to get full correct info */ - - if (size_b1) { - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB0CR); - base_b1 = -size_b1; - pbcr = (pbcr & 0x0001ffff) | base_b1 | - (((size_b1 / 1024 / 1024) - 1) << 17); - mtdcr(EBC0_CFGDATA, pbcr); - /* printf("PB1CR = %x\n", pbcr); */ - } - - if (size_b0) { - mtdcr(EBC0_CFGADDR, PB1CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB1CR); - base_b0 = base_b1 - size_b0; - pbcr = (pbcr & 0x0001ffff) | base_b0 | - (((size_b0 / 1024 / 1024) - 1) << 17); - mtdcr(EBC0_CFGDATA, pbcr); - /* printf("PB0CR = %x\n", pbcr); */ - } - - size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]); - - flash_get_offsets(base_b0, &flash_info[0]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - base_b0 + size_b0 - CONFIG_SYS_MONITOR_LEN, - base_b0 + size_b0 - 1, &flash_info[0]); - /* Also protect sector containing initial power-up instruction */ - /* (flash_protect() checks address range - other call ignored) */ - (void)flash_protect(FLAG_PROTECT_SET, - 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]); - (void)flash_protect(FLAG_PROTECT_SET, - 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[1]); - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = - flash_get_size((vu_long *) base_b1, &flash_info[1]); - - flash_get_offsets(base_b1, &flash_info[1]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - base_b1 + size_b1 - CONFIG_SYS_MONITOR_LEN, - base_b1 + size_b1 - 1, - &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - (void)flash_protect(FLAG_PROTECT_CLEAR, - base_b0 + size_b0 - CONFIG_SYS_MONITOR_LEN, - base_b0 + size_b0 - 1, - &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - } /* else 2 banks */ - return (size_b0 + size_b1); -} - -static void flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } -} diff --git a/qemu/roms/u-boot/board/amcc/canyonlands/Makefile b/qemu/roms/u-boot/board/amcc/canyonlands/Makefile deleted file mode 100644 index ba0765fe9..000000000 --- a/qemu/roms/u-boot/board/amcc/canyonlands/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2008 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := canyonlands.o -obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -extra-y += init.o diff --git a/qemu/roms/u-boot/board/amcc/canyonlands/canyonlands.c b/qemu/roms/u-boot/board/amcc/canyonlands/canyonlands.c deleted file mode 100644 index 79d4babe0..000000000 --- a/qemu/roms/u-boot/board/amcc/canyonlands/canyonlands.c +++ /dev/null @@ -1,519 +0,0 @@ -/* - * (C) Copyright 2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc440.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <i2c.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/mmu.h> -#include <asm/4xx_pcie.h> -#include <asm/ppc4xx-gpio.h> -#include <asm/errno.h> -#include <usb.h> - -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -DECLARE_GLOBAL_DATA_PTR; - -struct board_bcsr { - u8 board_id; - u8 cpld_rev; - u8 led_user; - u8 board_status; - u8 reset_ctrl; - u8 flash_ctrl; - u8 eth_ctrl; - u8 usb_ctrl; - u8 irq_ctrl; -}; - -#define BOARD_CANYONLANDS_PCIE 1 -#define BOARD_CANYONLANDS_SATA 2 -#define BOARD_GLACIER 3 -#define BOARD_ARCHES 4 - -/* - * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with - * board specific values. - */ -#if defined(CONFIG_ARCHES) -u32 ddr_wrdtr(u32 default_val) { - return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823); -} -#else -u32 ddr_wrdtr(u32 default_val) { - return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823); -} - -u32 ddr_clktr(u32 default_val) { - return (SDRAM_CLKTR_CLKP_90_DEG_ADV); -} -#endif - -#if defined(CONFIG_ARCHES) -/* - * FPGA read/write helper macros - */ -static inline int board_fpga_read(int offset) -{ - int data; - - data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset)); - - return data; -} - -static inline void board_fpga_write(int offset, int data) -{ - out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data); -} - -/* - * CPLD read/write helper macros - */ -static inline int board_cpld_read(int offset) -{ - int data; - - out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset); - data = in_8((void *)(CONFIG_SYS_CPLD_DATA)); - - return data; -} - -static inline void board_cpld_write(int offset, int data) -{ - out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset); - out_8((void *)(CONFIG_SYS_CPLD_DATA), data); -} -#else -static int pvr_460ex(void) -{ - u32 pvr = get_pvr(); - - if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) || - (pvr == PVR_460EX_RB)) - return 1; - - return 0; -} -#endif /* defined(CONFIG_ARCHES) */ - -int board_early_init_f(void) -{ -#if !defined(CONFIG_ARCHES) - u32 sdr0_cust0; - struct board_bcsr *bcsr_data = - (struct board_bcsr *)CONFIG_SYS_BCSR_BASE; - -#endif - - /* - * Setup the interrupt controller polarities, triggers, etc. - */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(UIC2ER, 0x00000000); /* disable all */ - mtdcr(UIC2CR, 0x00000000); /* all non-critical */ - mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - mtdcr(UIC3ER, 0x00000000); /* disable all */ - mtdcr(UIC3CR, 0x00000000); /* all non-critical */ - mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - -#if !defined(CONFIG_ARCHES) - /* SDR Setting - enable NDFC */ - mfsdr(SDR0_CUST0, sdr0_cust0); - sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | - SDR0_CUST0_NDFC_ENABLE | - SDR0_CUST0_NDFC_BW_8_BIT | - SDR0_CUST0_NDFC_ARE_MASK | - SDR0_CUST0_NDFC_BAC_ENCODE(3) | - (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); - mtsdr(SDR0_CUST0, sdr0_cust0); -#endif - - /* - * Configure PFC (Pin Function Control) registers - * UART0: 4 pins - */ - mtsdr(SDR0_PFC1, 0x00040000); - - /* Enable PCI host functionality in SDR0_PCI0 */ - mtsdr(SDR0_PCI0, 0xe0000000); - -#if !defined(CONFIG_ARCHES) - /* Enable ethernet and take out of reset */ - out_8(&bcsr_data->eth_ctrl, 0) ; - - /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */ - out_8(&bcsr_data->flash_ctrl, 0) ; - mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */ - - /* Setup PLB4-AHB bridge based on the system address map */ - mtdcr(AHB_TOP, 0x8000004B); - mtdcr(AHB_BOT, 0x8000004B); - -#endif - - return 0; -} - -#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) -int board_usb_init(int index, enum usb_init_type init) -{ - struct board_bcsr *bcsr_data = - (struct board_bcsr *)CONFIG_SYS_BCSR_BASE; - u8 val; - - /* Enable USB host & USB-OTG */ - val = in_8(&bcsr_data->usb_ctrl); - val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST); - out_8(&bcsr_data->usb_ctrl, val); - - /* - * Configure USB-STP pins as alternate and not GPIO - * It seems to be neccessary to configure the STP pins as GPIO - * input at powerup (perhaps while USB reset is asserted). So - * we configure those pins to their "real" function now. - */ - gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); - gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); - - return 0; -} - -int usb_board_stop(void) -{ - struct board_bcsr *bcsr_data = - (struct board_bcsr *)CONFIG_SYS_BCSR_BASE; - u8 val; - - /* Disable USB host & USB-OTG */ - val = in_8(&bcsr_data->usb_ctrl); - val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST); - out_8(&bcsr_data->usb_ctrl, val); - - /* Reconfigure USB-STP pins as input */ - gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0); - gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0); - - return 0; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return usb_board_stop(); -} -#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */ - -#if !defined(CONFIG_ARCHES) -static void canyonlands_sata_init(int board_type) -{ - u32 reg; - - if (board_type == BOARD_CANYONLANDS_SATA) { - /* Put SATA in reset */ - SDR_WRITE(SDR0_SRST1, 0x00020001); - - /* Set the phy for SATA, not PCI-E port 0 */ - reg = SDR_READ(PESDR0_PHY_CTL_RST); - SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001); - reg = SDR_READ(PESDR0_L0CLK); - SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007); - SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111); - SDR_WRITE(PESDR0_L0DRV, 0x00000104); - - /* Bring SATA out of reset */ - SDR_WRITE(SDR0_SRST1, 0x00000000); - } -} -#endif /* !defined(CONFIG_ARCHES) */ - -int get_cpu_num(void) -{ - int cpu = NA_OR_UNKNOWN_CPU; - -#if defined(CONFIG_ARCHES) - int cpu_num; - - cpu_num = board_fpga_read(0x3); - - /* sanity check; assume cpu numbering starts and increments from 0 */ - if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS)) - cpu = cpu_num; -#endif - - return cpu; -} - -#if !defined(CONFIG_ARCHES) -int checkboard(void) -{ - struct board_bcsr *bcsr_data = - (struct board_bcsr *)CONFIG_SYS_BCSR_BASE; - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - if (pvr_460ex()) { - printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board"); - if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE) - gd->board_type = BOARD_CANYONLANDS_PCIE; - else - gd->board_type = BOARD_CANYONLANDS_SATA; - } else { - printf("Board: Glacier - AMCC PPC460GT Evaluation Board"); - gd->board_type = BOARD_GLACIER; - } - - switch (gd->board_type) { - case BOARD_CANYONLANDS_PCIE: - case BOARD_GLACIER: - puts(", 2*PCIe"); - break; - - case BOARD_CANYONLANDS_SATA: - puts(", 1*PCIe/1*SATA"); - break; - } - - printf(", Rev. %X", in_8(&bcsr_data->cpld_rev)); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - canyonlands_sata_init(gd->board_type); - - return (0); -} - -#else /* defined(CONFIG_ARCHES) */ - -int checkboard(void) -{ - char *s = getenv("serial#"); - - printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n"); - printf(" Revision %02x.%02x ", - board_fpga_read(0x0), board_fpga_read(0x1)); - - gd->board_type = BOARD_ARCHES; - - /* Only CPU0 has access to CPLD registers */ - if (get_cpu_num() == 0) { - u8 cfg_sw = board_cpld_read(0x1); - printf("(FPGA=%02x, CPLD=%02x)\n", - board_fpga_read(0x2), board_cpld_read(0x0)); - printf(" Configuration Switch %d%d%d%d\n", - ((cfg_sw >> 3) & 0x01), - ((cfg_sw >> 2) & 0x01), - ((cfg_sw >> 1) & 0x01), - ((cfg_sw >> 0) & 0x01)); - } else - printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2)); - - - if (s != NULL) - printf(" Serial# %s\n", s); - - return 0; -} -#endif /* !defined(CONFIG_ARCHES) */ - -#if defined(CONFIG_PCI) -int board_pcie_first(void) -{ - /* - * Canyonlands with SATA enabled has only one PCIe slot - * (2nd one). - */ - if (gd->board_type == BOARD_CANYONLANDS_SATA) - return 1; - - return 0; -} -#endif /* CONFIG_PCI */ - -int board_early_init_r (void) -{ - /* - * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the - * boot EBC mapping only supports a maximum of 16MBytes - * (4.ff00.0000 - 4.ffff.ffff). - * To solve this problem, the FLASH has to get remapped to another - * EBC address which accepts bigger regions: - * - * 0xfc00.0000 -> 4.cc00.0000 - */ - - /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */ - mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); - - /* Remove TLB entry of boot EBC mapping */ - remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20); - - /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */ - program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE, - TLB_WORD2_I_ENABLE); - - /* - * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address - * 0xfc00.0000 is possible - */ - - /* - * Clear potential errors resulting from auto-calibration. - * If not done, then we could get an interrupt later on when - * exceptions are enabled. - */ - set_mcsr(get_mcsr()); - - return 0; -} - -#if !defined(CONFIG_ARCHES) -int misc_init_r(void) -{ - u32 sdr0_srst1 = 0; - u32 eth_cfg; - u8 val; - - /* - * Set EMAC mode/configuration (GMII, SGMII, RGMII...). - * This is board specific, so let's do it here. - */ - mfsdr(SDR0_ETH_CFG, eth_cfg); - /* disable SGMII mode */ - eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE | - SDR0_ETH_CFG_SGMII1_ENABLE | - SDR0_ETH_CFG_SGMII0_ENABLE); - /* Set the for 2 RGMII mode */ - /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ - eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL; - if (pvr_460ex()) - eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL; - else - eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL; - mtsdr(SDR0_ETH_CFG, eth_cfg); - - /* - * The AHB Bridge core is held in reset after power-on or reset - * so enable it now - */ - mfsdr(SDR0_SRST1, sdr0_srst1); - sdr0_srst1 &= ~SDR0_SRST1_AHB; - mtsdr(SDR0_SRST1, sdr0_srst1); - - /* - * RTC/M41T62: - * Disable square wave output: Batterie will be drained - * quickly, when this output is not disabled - */ - val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa); - val &= ~0x40; - i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val); - - return 0; -} - -#else /* defined(CONFIG_ARCHES) */ - -int misc_init_r(void) -{ - u32 eth_cfg = 0; - u32 eth_pll; - u32 reg; - - /* - * Set EMAC mode/configuration (GMII, SGMII, RGMII...). - * This is board specific, so let's do it here. - */ - - /* enable SGMII mode */ - eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE | - SDR0_ETH_CFG_SGMII1_ENABLE | - SDR0_ETH_CFG_SGMII2_ENABLE); - - /* Set EMAC for MDIO */ - eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0; - - /* bypass the TAHOE0/TAHOE1 cores for U-Boot */ - eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); - - mtsdr(SDR0_ETH_CFG, eth_cfg); - - /* reset all SGMII interfaces */ - mfsdr(SDR0_SRST1, reg); - reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2); - mtsdr(SDR0_SRST1, reg); - mtsdr(SDR0_ETH_STS, 0xFFFFFFFF); - mtsdr(SDR0_SRST1, 0x00000000); - - do { - mfsdr(SDR0_ETH_PLL, eth_pll); - } while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK)); - - return 0; -} -#endif /* !defined(CONFIG_ARCHES) */ - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -extern void __ft_board_setup(void *blob, bd_t *bd); - -void ft_board_setup(void *blob, bd_t *bd) -{ - __ft_board_setup(blob, bd); - - if (gd->board_type == BOARD_CANYONLANDS_SATA) { - /* - * When SATA is selected we need to disable the first PCIe - * node in the device tree, so that Linux doesn't initialize - * it. - */ - fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status", - "disabled", sizeof("disabled"), 1); - } - - if (gd->board_type == BOARD_CANYONLANDS_PCIE) { - /* - * When PCIe is selected we need to disable the SATA - * node in the device tree, so that Linux doesn't initialize - * it. - */ - fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status", - "disabled", sizeof("disabled"), 1); - } -} -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/qemu/roms/u-boot/board/amcc/canyonlands/chip_config.c b/qemu/roms/u-boot/board/amcc/canyonlands/chip_config.c deleted file mode 100644 index e48557098..000000000 --- a/qemu/roms/u-boot/board/amcc/canyonlands/chip_config.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * (C) Copyright 2008-2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx_config.h> - -struct ppc4xx_config ppc4xx_config_val[] = { - { - "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "800-nor", "NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "1000-nor", "NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "1066-nor", "NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88", - { - 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, -#if !defined(CONFIG_ARCHES) - { - "600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0, - 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0, - 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0, - 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "1066-nand", "NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88", - { - 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x90, 0x01, 0xa0, - 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, -#endif -}; - -int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/qemu/roms/u-boot/board/amcc/canyonlands/config.mk b/qemu/roms/u-boot/board/amcc/canyonlands/config.mk deleted file mode 100644 index 63b897370..000000000 --- a/qemu/roms/u-boot/board/amcc/canyonlands/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# (C) Copyright 2008-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# AMCC 460EX/460GT Evaluation Board (Canyonlands) board -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/qemu/roms/u-boot/board/amcc/canyonlands/init.S b/qemu/roms/u-boot/board/amcc/canyonlands/init.S deleted file mode 100644 index bf00bd6bc..000000000 --- a/qemu/roms/u-boot/board/amcc/canyonlands/init.S +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to - * use the speed up boot process. It is patched after relocation to - * enable SA_I - */ - tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */ - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - -#ifdef CONFIG_SYS_INIT_RAM_DCACHE - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G) -#endif - - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG) - - /* PCIe UTL register */ - tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_RW | SA_IG) - -#if !defined(CONFIG_ARCHES) - /* TLB-entry for NAND */ - tlbentry(CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 4, AC_RWX | SA_IG) - - /* TLB-entry for CPLD */ - tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_RW | SA_IG) -#else - /* TLB-entry for FPGA */ - tlbentry(CONFIG_SYS_FPGA_BASE, SZ_16M, CONFIG_SYS_FPGA_BASE, 4, AC_RW | SA_IG) -#endif - - /* TLB-entry for OCM */ - tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_RWX | SA_I) - - /* TLB-entry for Local Configuration registers => peripherals */ - tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG) - - /* AHB: Internal USB Peripherals (USB, SATA) */ - tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_RWX | SA_IG) - -#if defined(CONFIG_RAPIDIO) - /* TLB-entries for RapidIO (SRIO) */ - tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR, - 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR, - 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_SRGPL0_MNT_BAR, SZ_16M, CONFIG_SYS_SRGPL0_MNT_BAR, - 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_I2ODMA_BASE, SZ_1K, 0x00100000, - 0x4, AC_RW | SA_IG) -#endif - - tlbtab_end diff --git a/qemu/roms/u-boot/board/amcc/common/flash.c b/qemu/roms/u-boot/board/amcc/common/flash.c deleted file mode 100644 index 4b2300b2f..000000000 --- a/qemu/roms/u-boot/board/amcc/common/flash.c +++ /dev/null @@ -1,934 +0,0 @@ -/* - * (C) Copyright 2004-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> - * Add support for Am29F016D and dynamic switch setting. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word(flash_info_t * info, ulong dest, ulong data); -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -static int write_word_1(flash_info_t * info, ulong dest, ulong data); -static int write_word_2(flash_info_t * info, ulong dest, ulong data); -static int flash_erase_1(flash_info_t * info, int s_first, int s_last); -static int flash_erase_2(flash_info_t * info, int s_first, int s_last); -static ulong flash_get_size_1(vu_long * addr, flash_info_t * info); -static ulong flash_get_size_2(vu_long * addr, flash_info_t * info); -#endif - -void flash_print_info(flash_info_t * info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_STM: - printf("STM "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_SST: - printf("SST "); - break; - case FLASH_MAN_MX: - printf ("MACRONIX "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AMD016: - printf("AM29F016D (16 Mbit, uniform sector size)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AM033C: - printf("AM29LV033C (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST800A: - printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: - printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - case FLASH_STMW320DT: - printf ("M29W320DT (32 M, top sector)\n"); - break; - case FLASH_MXLV320T: - printf ("MXLV320T (32 Mbit, top sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s%s", - info->start[i], - erased ? " E" : " ", info->protect[i] ? "RO " : " "); - } - printf("\n"); - return; -} - - -/* - * The following code cannot be run from FLASH! - */ -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - /* bit 0 used for big flash marking */ - if ((ulong)addr & 0x1) { - return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info); - } else { - return flash_get_size_1(addr, info); - } -} - -static ulong flash_get_size_1(vu_long * addr, flash_info_t * info) -#else -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -#endif -{ - short i; - CONFIG_SYS_FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); - - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; - udelay(1000); - - value = addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 KiB */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 KiB */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 KiB */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D: - info->flash_id += FLASH_AMD016; - info->sector_count = 32; - info->size = 0x00200000; /* => 2 MiB */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C: - info->flash_id += FLASH_AMDLV033C; - info->sector_count = 64; - info->size = 0x00400000; /* => 4 MiB */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; /* => 512 KiB */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; /* => 512 KiB */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; /* => 1 MiB */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; /* => 1 MiB */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; /* => 2 MiB */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; /* => 2 MiB */ - break; - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - - /* For AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if (i == 32) { - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; - - return (info->size); -} - -static int wait_for_DQ7_1(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = - (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { - return flash_erase_2(info, s_first, s_last); - } else { - return flash_erase_1(info, s_first, s_last); - } -} - -static int flash_erase_1(flash_info_t * info, int s_first, int s_last) -#else -int flash_erase(flash_info_t * info, int s_first, int s_last) -#endif -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_1(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -static int write_word(flash_info_t * info, ulong dest, ulong data) -{ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { - return write_word_2(info, dest, data); - } else { - return write_word_1(info, dest, data); - } -} - -static int write_word_1(flash_info_t * info, ulong dest, ulong data) -#else -static int write_word(flash_info_t * info, ulong dest, ulong data) -#endif -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV - -#undef CONFIG_SYS_FLASH_WORD_SIZE -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) -{ - short i; - int n; - CONFIG_SYS_FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); - - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; - udelay(1000); - - value = addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) MX_MANUFACT: - info->flash_id = FLASH_MAN_MX; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MiB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MiB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT: - info->flash_id += FLASH_STMW320DT; - info->sector_count = 67; - info->size = 0x00400000; break; /* => 4 MiB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)MX_ID_LV320T: - info->flash_id += FLASH_MXLV320T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 4 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) { - /* set sector offsets for top boot block type */ - base += info->size; - i = info->sector_count; - /* 1 x 16k boot sector */ - base -= 16 << 10; - --i; - info->start[i] = base; - /* 2 x 8k boot sectors */ - for (n=0; n<2; ++n) { - base -= 8 << 10; - --i; - info->start[i] = base; - } - /* 1 x 32k boot sector */ - base -= 32 << 10; - --i; - info->start[i] = base; - - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) { - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000a000; - info->start[i--] = base + info->size - 0x0000c000; - info->start[i--] = base + info->size - 0x0000e000; - info->start[i--] = base + info->size - 0x00010000; - - for (; i >= 0; i--) - info->start[i] = base + i * 0x00010000; - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00002000; - info->start[2] = base + 0x00004000; - info->start[3] = base + 0x00006000; - info->start[4] = base + 0x00008000; - info->start[5] = base + 0x0000a000; - info->start[6] = base + 0x0000c000; - info->start[7] = base + 0x0000e000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = - base + ((i-7) * 0x00010000); - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000a000; - info->start[i--] = base + info->size - 0x0000c000; - info->start[i--] = base + info->size - 0x0000e000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - - /* For AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if (i == 32) { - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; - - return (info->size); -} - -static int wait_for_DQ7_2(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = - (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -static int flash_erase_2(flash_info_t * info, int s_first, int s_last) -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_2(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -static int write_word_2(flash_info_t * info, ulong dest, ulong data) -{ - ulong *data_ptr = &data; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} -#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */ diff --git a/qemu/roms/u-boot/board/amcc/ebony/Makefile b/qemu/roms/u-boot/board/amcc/ebony/Makefile deleted file mode 100644 index 5876486f5..000000000 --- a/qemu/roms/u-boot/board/amcc/ebony/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = ebony.o flash.o -extra-y += init.o diff --git a/qemu/roms/u-boot/board/amcc/ebony/README b/qemu/roms/u-boot/board/amcc/ebony/README deleted file mode 100644 index 4df00b356..000000000 --- a/qemu/roms/u-boot/board/amcc/ebony/README +++ /dev/null @@ -1,136 +0,0 @@ - AMCC Ebony Board - - Last Update: September 12, 2002 -======================================================================= - -This file contains some handy info regarding U-Boot and the AMCC -Ebony evaluation board. See the README.ppc440 for additional -information. - - -SWITCH SETTINGS & JUMPERS -========================== - -Here's what I've been using successfully. If you feel inclined to -change things ... please read the docs! - -DIPSW U46 U80 ------------------------- -SW 1 off on -SW 2 on on -SW 3 on on -SW 4 off on -SW 5 on off -SW 6 on on -SW 7 on off -SW 8 on off - -J41: strapped -J42: open - -All others are factory default. - - -I2C probe -===================== - -The i2c utilities have been tested on both Rev B. and Rev C. and -look good. The CONFIG_SYS_I2C_NOPROBES macro is defined to prevent -probing the CDCV850 clock controller at address 0x69 (since reading -it causes the i2c implementation to misbehave. The output of -'i2c probe' should look like this (assuming you are only using a single -SO-DIMM: - -=> i2c probe -Valid chip addresses: 50 53 54 -Excluded chip addresses: 69 - - -GETTING OUT OF I2C TROUBLE -=========================== - -If you're like me ... you may have screwed up your bootstrap serial -eeprom ... or worse, your SPD eeprom when experimenting with the -i2c commands. If so, here are some ideas on how to get out of -trouble: - -Serial bootstrap eeprom corruption: ------------------------------------ -Power down the board and set the following straps: - -J41 - open -J42 - strapped - -This will select the default sys0 and sys1 settings (the serial -eeproms are not used). Then power up the board and fix the serial -eeprom using the 'i2c mm' command. Here are the values I currently -use: - -=> i2c md 50 0 10 -0000: bf a2 04 01 ae 94 11 00 00 00 00 00 00 00 00 00 ................ - -=> i2c md 54 0 10 -0000: 8f b3 24 01 4d 14 11 00 00 00 00 00 00 00 00 00 ..$.M........... - -Once you have the eeproms set correctly change the -J41/J42 straps as you desire. - -SPD eeprom corruption: ------------------------- -I've corrupted the SPD eeprom several times ... perhaps too much coffee -and not enough presence of mind ;-). By default, the ebony code uses -the SPD to initialize the DDR SDRAM control registers. So if the SPD -eeprom is corrupted, U-Boot will never get into ram. Here's how I got -out of this situation: - -0. First, _before_ playing with the i2c utilities, do an 'i2c probe', then -use 'i2c md' to capture the various device contents to a file. Some day -you may be glad you did this ... trust me :-). Otherwise try the -following: - -1. In the include/configs/EBONY.h file find the line that defines -the CONFIG_SPD_EEPROM macro and undefine it. E.g: - -#undef CONFIG_SPD_EEPROM - -This will make the code use default SDRAM control register -settings without using the SPD eeprom. - -2. Rebuild U-Boot - -3. Load the new U-Boot image and reboot ebony. - -4. Repair the SPD eeprom using the 'i2c mm' command. Here's the eeprom -contents that work with the default SO-DIMM that comes with the -ebony board (micron 8VDDT164AG-265A1). Note: these are probably -_not_ the factory settings ... but they work. - -=> i2c md 53 0 10 80 -0000: 80 08 07 0c 0a 01 40 00 04 75 75 00 80 08 00 01 ......@..uu..... -0010: 0e 04 0c 01 02 20 00 a0 75 00 00 50 3c 50 2d 20 ..... ..u..P<P- -0020: 90 90 50 50 00 00 00 00 00 41 4b 34 32 75 00 00 ..PP.....AK42u.. -0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9c ................ -0040: 2c 00 00 00 00 00 00 00 08 38 56 44 44 54 31 36 ,........8VDDT16 -0050: 36 34 41 47 2d 32 36 35 41 31 20 01 00 01 2c 63 64AG-265A1 ...,c -0060: 22 25 ab 00 00 00 00 00 00 00 00 00 00 00 00 00 "%.............. -0070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ - - -PCI DOUBLE-ENUMERATION WOES -=========================== - -If you're not using PCI-X cards and are simply using 32-bit and/or -33 MHz cards via extenders and the like, you may notice that the -initial pci scan reports various devices twice ... and configuration -does not succeed (one or more devices are enumerated twice). To correct -this we replaced the 2K ohm resistor on the IDSEL line(s) with a -22 ohm resistor and the problem went away. This change hasn't broken -anything yet -- use at your own risk. - -We never tested anything other than 33 MHz/32-bit cards. If you have -the chance to do this, please let me know how things turn out :-) - - -Regards, ---Scott -<smcnutt@artesyncp.com> diff --git a/qemu/roms/u-boot/board/amcc/ebony/config.mk b/qemu/roms/u-boot/board/amcc/ebony/config.mk deleted file mode 100644 index f18b09710..000000000 --- a/qemu/roms/u-boot/board/amcc/ebony/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/qemu/roms/u-boot/board/amcc/ebony/ebony.c b/qemu/roms/u-boot/board/amcc/ebony/ebony.c deleted file mode 100644 index eb424489e..000000000 --- a/qemu/roms/u-boot/board/amcc/ebony/ebony.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <spd_sdram.h> - -#define BOOT_SMALL_FLASH 32 /* 00100000 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ - -DECLARE_GLOBAL_DATA_PTR; - -long int fixed_sdram(void); - -int board_early_init_f(void) -{ - uint reg; - unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE; - unsigned char status; - - /*-------------------------------------------------------------------- - * Setup the external bus controller/chip selects - *-------------------------------------------------------------------*/ - mtdcr(EBC0_CFGADDR, EBC0_CFG); - reg = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */ - - mtebc(PB1AP, 0x02815480); /* NVRAM/RTC */ - mtebc(PB1CR, 0x48018000); /* BA=0x480 1MB R/W 8-bit */ - mtebc(PB7AP, 0x01015280); /* FPGA registers */ - mtebc(PB7CR, 0x48318000); /* BA=0x483 1MB R/W 8-bit */ - - /* read FPGA_REG0 and set the bus controller */ - status = *fpga_base; - if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) { - mtebc(PB0AP, 0x9b015480); /* FLASH/SRAM */ - mtebc(PB0CR, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */ - mtebc(PB2AP, 0x9b015480); /* 4MB FLASH */ - mtebc(PB2CR, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */ - } else { - mtebc(PB0AP, 0x9b015480); /* 4MB FLASH */ - mtebc(PB0CR, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */ - - /* set CS2 if FLASH_ONBD_N == 0 */ - if (!(status & FLASH_ONBD_N)) { - mtebc(PB2AP, 0x9b015480); /* FLASH/SRAM */ - mtebc(PB2CR, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */ - } - } - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ - mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: Ebony - AMCC PPC440GP Evaluation Board"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} - -phys_size_t initdram(int board_type) -{ - long dram_size = 0; - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram(); -#else - dram_size = fixed_sdram(); -#endif - return dram_size; -} - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - * - * Assumes: 128 MB, non-ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -long int fixed_sdram(void) -{ - uint reg; - - /*-------------------------------------------------------------------- - * Setup some default - *------------------------------------------------------------------*/ - mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ - mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ - - /*-------------------------------------------------------------------- - * Setup for board-specific specific mem - *------------------------------------------------------------------*/ - /* - * Following for CAS Latency = 2.5 @ 133 MHz PLB - */ - mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram(SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ - /* RA=10 RD=3 */ - mtsdram(SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram(SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ - udelay(400); /* Delay 200 usecs (min) */ - - /*-------------------------------------------------------------------- - * Enable the controller, then wait for DCEN to complete - *------------------------------------------------------------------*/ - mtsdram(SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ - for (;;) { - mfsdram(SDRAM0_MCSTS, reg); - if (reg & 0x80000000) - break; - } - - return (128 * 1024 * 1024); /* 128 MB */ -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ diff --git a/qemu/roms/u-boot/board/amcc/ebony/flash.c b/qemu/roms/u-boot/board/amcc/ebony/flash.c deleted file mode 100644 index 5740a5623..000000000 --- a/qemu/roms/u-boot/board/amcc/ebony/flash.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> - * Add support for Am29F016D and dynamic switch setting. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include <asm/io.h> - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -#define BOOT_SMALL_FLASH 32 /* 00100000 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ - -#define BOOT_SMALL_FLASH_VAL 4 -#define FLASH_ONBD_N_VAL 2 -#define FLASH_SRAM_SEL_VAL 1 - -static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = { - {0xffc00000, 0xffe00000, 0xff880000}, /* 0:000: configuraton 3 */ - {0xffc00000, 0xffe00000, 0xff800000}, /* 1:001: configuraton 4 */ - {0xffc00000, 0xffe00000, 0x00000000}, /* 2:010: configuraton 7 */ - {0xffc00000, 0xffe00000, 0x00000000}, /* 3:011: configuraton 8 */ - {0xff800000, 0xffa00000, 0xfff80000}, /* 4:100: configuraton 1 */ - {0xff800000, 0xffa00000, 0xfff00000}, /* 5:101: configuraton 2 */ - {0xffc00000, 0xffe00000, 0x00000000}, /* 6:110: configuraton 5 */ - {0xffc00000, 0xffe00000, 0x00000000} /* 7:111: configuraton 6 */ -}; - -/* - * include common flash code (for amcc boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); - -/* - * Override the weak default mapping function with a board specific one - */ -u32 flash_get_bank_size(int cs, int idx) -{ - u8 reg = in_8((void *)CONFIG_SYS_FPGA_BASE); - - if ((reg & BOOT_SMALL_FLASH) && !(reg & FLASH_ONBD_N)) { - /* - * cs0: small flash (512KiB) - * cs2: 2 * big flash (2 * 2MiB) - */ - if (cs == 0) - return flash_info[2].size; - if (cs == 2) - return flash_info[0].size + flash_info[1].size; - } else { - /* - * cs0: 2 * big flash (2 * 2MiB) - * cs2: small flash (512KiB) - */ - if (cs == 0) - return flash_info[0].size + flash_info[1].size; - if (cs == 2) - return flash_info[2].size; - } - - return 0; -} - -unsigned long flash_init(void) -{ - unsigned long total_b = 0; - unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; - unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE; - unsigned char switch_status; - unsigned short index = 0; - int i; - - /* read FPGA base register FPGA_REG0 */ - switch_status = *fpga_base; - - /* check the bitmap of switch status */ - if (switch_status & BOOT_SMALL_FLASH) { - index += BOOT_SMALL_FLASH_VAL; - } - if (switch_status & FLASH_ONBD_N) { - index += FLASH_ONBD_N_VAL; - } - if (switch_status & FLASH_SRAM_SEL) { - index += FLASH_SRAM_SEL_VAL; - } - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - - /* check whether the address is 0 */ - if (flash_addr_table[index][i] == 0) { - continue; - } - - /* call flash_get_size() to initialize sector address */ - size_b[i] = flash_get_size((vu_long *) - flash_addr_table[index][i], - &flash_info[i]); - flash_info[i].size = size_b[i]; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i] << 20); - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - } - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[2]); -#ifdef CONFIG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[2]); - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[2]); -#endif - - total_b += flash_info[i].size; - } - - return total_b; -} diff --git a/qemu/roms/u-boot/board/amcc/ebony/init.S b/qemu/roms/u-boot/board/amcc/ebony/init.S deleted file mode 100644 index 904e64898..000000000 --- a/qemu/roms/u-boot/board/amcc/ebony/init.S +++ /dev/null @@ -1,41 +0,0 @@ -/* -* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> -#include <asm/ppc4xx.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX) - tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX) - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG) - tlbtab_end diff --git a/qemu/roms/u-boot/board/amcc/katmai/Makefile b/qemu/roms/u-boot/board/amcc/katmai/Makefile deleted file mode 100644 index b738defc1..000000000 --- a/qemu/roms/u-boot/board/amcc/katmai/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := katmai.o -obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -extra-y += init.o diff --git a/qemu/roms/u-boot/board/amcc/katmai/chip_config.c b/qemu/roms/u-boot/board/amcc/katmai/chip_config.c deleted file mode 100644 index 5e711c43b..000000000 --- a/qemu/roms/u-boot/board/amcc/katmai/chip_config.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx_config.h> - -struct ppc4xx_config ppc4xx_config_val[] = { - { - "400-133","CPU: 400 PLB: 133 OPB: 66 EBC: 66", - { 0x86, 0x78, 0xc2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 } - }, - { - "500-166","CPU: 500 PLB: 166 OPB: 83 EBC: 83", - { 0x87, 0x78, 0xf2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 } - }, - { - "533-133","CPU: 533 PLB: 133 OPB: 66 EBC: 66", - { 0x87, 0x79, 0x02, 0x52, 0x05, 0xa5, 0x04, 0xe1 } - }, - { - "667-133","CPU: 667 PLB: 133 OPB: 66 EBC: 66", - { 0x87, 0x79, 0x42, 0x56, 0x05, 0xa5, 0x04, 0xe1 } - }, - { - "667-166","CPU: 667 PLB: 166 OPB: 83 EBC: 83", - { 0x87, 0x79, 0x42, 0x06, 0x05, 0xa5, 0x04, 0xe1 } - }, - { - "800-160","CPU: 800 PLB: 160 OPB: 53 EBC: 17", - { 0x86, 0x79, 0x81, 0xa7, 0x07, 0xa5, 0x04, 0xe1 } - }, -}; - -int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/qemu/roms/u-boot/board/amcc/katmai/config.mk b/qemu/roms/u-boot/board/amcc/katmai/config.mk deleted file mode 100644 index 6108f7997..000000000 --- a/qemu/roms/u-boot/board/amcc/katmai/config.mk +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# AMCC 440SPe Evaluation (Katmai) board -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/qemu/roms/u-boot/board/amcc/katmai/init.S b/qemu/roms/u-boot/board/amcc/katmai/init.S deleted file mode 100644 index 32f26672e..000000000 --- a/qemu/roms/u-boot/board/amcc/katmai/init.S +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> -#include <asm/ppc4xx.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - -/************************************************************************** - * TLB table for revA - *************************************************************************/ - .globl tlbtabA -tlbtabA: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I) - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG) - tlbtab_end - -/************************************************************************** - * TLB table for revB - * - * Notice: revB of the 440SPe chip is very strict about PLB real addresses - * and ranges to be mapped for config space: it seems to only work with - * d_nnnn_nnnn range (hangs the core upon config transaction attempts when - * set otherwise) while revA uses c_nnnn_nnnn. - *************************************************************************/ - .globl tlbtabB -tlbtabB: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I) - - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG) - tlbtab_end diff --git a/qemu/roms/u-boot/board/amcc/katmai/katmai.c b/qemu/roms/u-boot/board/amcc/katmai/katmai.c deleted file mode 100644 index 6ae340ba1..000000000 --- a/qemu/roms/u-boot/board/amcc/katmai/katmai.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * (C) Copyright 2007-2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <i2c.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <netdev.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> -#include <asm/4xx_pcie.h> -#include <asm/errno.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f (void) -{ - unsigned long mfr; - - /*----------------------------------------------------------------------+ - * Interrupt controller setup for the Katmai 440SPe Evaluation board. - *-----------------------------------------------------------------------+ - *-----------------------------------------------------------------------+ - * Interrupt | Source | Pol. | Sensi.| Crit. | - *-----------+-----------------------------------+-------+-------+-------+ - * IRQ 00 | UART0 | High | Level | Non | - * IRQ 01 | UART1 | High | Level | Non | - * IRQ 02 | IIC0 | High | Level | Non | - * IRQ 03 | IIC1 | High | Level | Non | - * IRQ 04 | PCI0X0 MSG IN | High | Level | Non | - * IRQ 05 | PCI0X0 CMD Write | High | Level | Non | - * IRQ 06 | PCI0X0 Power Mgt | High | Level | Non | - * IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non | - * IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non | - * IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non | - * IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non | - * IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit | - * IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non | - * IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non | - * IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non | - * IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non | - * IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non | - * IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit | - * IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non | - * IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non | - * IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non | - * IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non | - * IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non | - * IRQ 23 | I2O Inbound Doorbell | High | Level | Non | - * IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non | - * IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non | - * IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non | - * IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non | - * IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non | - * IRQ 29 | GPT Down Count Timer | Rising| Edge | Non | - * IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non | - * IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. | - *------------------------------------------------------------------------ - * IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non | - * IRQ 33 | MAL Serr | High | Level | Non | - * IRQ 34 | MAL Txde | High | Level | Non | - * IRQ 35 | MAL Rxde | High | Level | Non | - * IRQ 36 | DMC CE or DMC UE | High | Level | Non | - * IRQ 37 | EBC or UART2 | High |Lvl Edg| Non | - * IRQ 38 | MAL TX EOB | High | Level | Non | - * IRQ 39 | MAL RX EOB | High | Level | Non | - * IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non | - * IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non | - * IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non | - * IRQ 43 | L2 Cache | Risin | Edge | Non | - * IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non | - * IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non | - * IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non | - * IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | - * IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | - * IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non | - * IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non | - * IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non | - * IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | - * IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non | - * IRQ 54 | DMA Error | High | Level | Non | - * IRQ 55 | DMA I2O Error | High | Level | Non | - * IRQ 56 | Serial ROM | High | Level | Non | - * IRQ 57 | PCIX0 Error | High | Edge | Non | - * IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non | - * IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non | - * IRQ 60 | EMAC0 Interrupt | High | Level | Non | - * IRQ 61 | EMAC0 Wake-up | High | Level | Non | - * IRQ 62 | Reserved | High | Level | Non | - * IRQ 63 | XOR | High | Level | Non | - *----------------------------------------------------------------------- - * IRQ 64 | PE0 AL | High | Level | Non | - * IRQ 65 | PE0 VPD Access | Risin | Edge | Non | - * IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | - * IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | - * IRQ 68 | PE0 TCR | High | Level | Non | - * IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | - * IRQ 70 | PE0 DCR Error | High | Level | Non | - * IRQ 71 | Reserved | N/A | N/A | Non | - * IRQ 72 | PE1 AL | High | Level | Non | - * IRQ 73 | PE1 VPD Access | Risin | Edge | Non | - * IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | - * IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | - * IRQ 76 | PE1 TCR | High | Level | Non | - * IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | - * IRQ 78 | PE1 DCR Error | High | Level | Non | - * IRQ 79 | Reserved | N/A | N/A | Non | - * IRQ 80 | PE2 AL | High | Level | Non | - * IRQ 81 | PE2 VPD Access | Risin | Edge | Non | - * IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | - * IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | - * IRQ 84 | PE2 TCR | High | Level | Non | - * IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | - * IRQ 86 | PE2 DCR Error | High | Level | Non | - * IRQ 87 | Reserved | N/A | N/A | Non | - * IRQ 88 | External IRQ(5) | Progr | Progr | Non | - * IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | - * IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | - * IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | - * IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | - * IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | - * IRQ 94 | Reserved | N/A | N/A | Non | - * IRQ 95 | Reserved | N/A | N/A | Non | - *----------------------------------------------------------------------- - * IRQ 96 | PE0 INTA | High | Level | Non | - * IRQ 97 | PE0 INTB | High | Level | Non | - * IRQ 98 | PE0 INTC | High | Level | Non | - * IRQ 99 | PE0 INTD | High | Level | Non | - * IRQ 100 | PE1 INTA | High | Level | Non | - * IRQ 101 | PE1 INTB | High | Level | Non | - * IRQ 102 | PE1 INTC | High | Level | Non | - * IRQ 103 | PE1 INTD | High | Level | Non | - * IRQ 104 | PE2 INTA | High | Level | Non | - * IRQ 105 | PE2 INTB | High | Level | Non | - * IRQ 106 | PE2 INTC | High | Level | Non | - * IRQ 107 | PE2 INTD | Risin | Edge | Non | - * IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non | - * IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non | - * IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non | - * IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non | - * IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non | - * IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non | - * IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non | - * IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non | - * IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non | - * IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non | - * IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non | - * IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non | - * IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non | - * IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non | - * IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non | - * IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non | - * IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non | - * IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non | - * IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non | - * IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non | - *-----------+-----------------------------------+-------+-------+-------+ */ - /*-------------------------------------------------------------------------+ - * Put UICs in PowerPC440SPemode. - * Initialise UIC registers. Clear all interrupts. Disable all interrupts. - * Set critical interrupt values. Set interrupt polarities. Set interrupt - * trigger levels. Make bit 0 High priority. Clear all interrupts again. - *------------------------------------------------------------------------*/ - mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */ - mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical interrupts: */ - mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/ - mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ - mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC3SR, 0x00000000); /* clear all interrupts*/ - mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts*/ - - - mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC2ER, 0x00000000); /* disable all interrupts*/ - mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts*/ - mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/ - mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ - mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ - - mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts*/ - mtdcr (UIC1ER, 0x00000000); /* disable all interrupts*/ - mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts*/ - mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/ - mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC1SR, 0x00000000); /* clear all interrupts*/ - mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts*/ - - mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted cascade to be checked */ - mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical interrupts*/ - mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/ - mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */ - mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC0SR, 0x00000000); /* clear all interrupts*/ - mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts*/ - - mfsdr(SDR0_MFR, mfr); - mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ - mtsdr(SDR0_MFR, mfr); - - mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0); - - out32(GPIO0_OR, CONFIG_SYS_GPIO_OR); - out32(GPIO0_ODR, CONFIG_SYS_GPIO_ODR); - out32(GPIO0_TCR, CONFIG_SYS_GPIO_TCR); - - return 0; -} - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: Katmai - AMCC 440SPe Evaluation Board"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -/* - * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with - * board specific values. - */ -u32 ddr_wrdtr(u32 default_val) { - return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823); -} - -u32 ddr_clktr(u32 default_val) { - return (SDRAM_CLKTR_CLKP_90_DEG_ADV); -} - -#if defined(CONFIG_PCI) -int board_pcie_card_present(int port) -{ - u32 val; - - val = in32(GPIO0_IR); - switch (port) { - case 0: - return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0)); - case 1: - return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1)); - case 2: - return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2)); - default: - return 0; - } -} -#endif /* defined(CONFIG_PCI) */ - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); - return pci_eth_init(bis); -} diff --git a/qemu/roms/u-boot/board/amcc/kilauea/Makefile b/qemu/roms/u-boot/board/amcc/kilauea/Makefile deleted file mode 100644 index 754dadc66..000000000 --- a/qemu/roms/u-boot/board/amcc/kilauea/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := kilauea.o -obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o diff --git a/qemu/roms/u-boot/board/amcc/kilauea/chip_config.c b/qemu/roms/u-boot/board/amcc/kilauea/chip_config.c deleted file mode 100644 index 7e9dd3b5c..000000000 --- a/qemu/roms/u-boot/board/amcc/kilauea/chip_config.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx_config.h> - -/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */ - -struct ppc4xx_config ppc4xx_config_val[] = { - { - "333-nor","NOR CPU: 333 PLB: 166 OPB: 83 EBC: 83", - { - 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66", - { - 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "400-nor", "NOR CPU: 400 PLB: 200 OPB: 100 EBC: 100", - { - 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "533-nor", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88", - { - 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "533-nand", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88", - { - 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", - { - 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "600-nand", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", - { - 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "666-nor", "NOR CPU: 666 PLB: 222 OPB: 111 EBC: 111", - { - 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, -}; - -int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/qemu/roms/u-boot/board/amcc/kilauea/config.mk b/qemu/roms/u-boot/board/amcc/kilauea/config.mk deleted file mode 100644 index 0dc15c138..000000000 --- a/qemu/roms/u-boot/board/amcc/kilauea/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2007-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif diff --git a/qemu/roms/u-boot/board/amcc/kilauea/kilauea.c b/qemu/roms/u-boot/board/amcc/kilauea/kilauea.c deleted file mode 100644 index abfaa1eee..000000000 --- a/qemu/roms/u-boot/board/amcc/kilauea/kilauea.c +++ /dev/null @@ -1,309 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/ppc405.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/errno.h> - -#if defined(CONFIG_PCI) -#include <pci.h> -#include <asm/4xx_pcie.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -static int board_cpld_version(void) -{ - u32 cpld; - - cpld = in_be32((void *)CONFIG_SYS_FPGA_FIFO_BASE); - if ((cpld & CONFIG_SYS_FPGA_MAGIC_MASK) != CONFIG_SYS_FPGA_MAGIC) { - /* - * Magic not found -> "old" CPLD revision which needs - * the "old" EBC configuration - */ - mtebc(PB2AP, EBC_BXAP_BME_ENABLED | EBC_BXAP_FWT_ENCODE(5) | - EBC_BXAP_BWT_ENCODE(0) | EBC_BXAP_BCE_DISABLE | - EBC_BXAP_BCT_2TRANS | EBC_BXAP_CSN_ENCODE(0) | - EBC_BXAP_OEN_ENCODE(0) | EBC_BXAP_WBN_ENCODE(3) | - EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_TH_ENCODE(4) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_SOR_DELAYED | - EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - - /* - * Return 0 for "old" CPLD version - */ - return 0; - } - - /* - * Magic found -> "new" CPLD revision which needs no new - * EBC configuration - */ - return (cpld & CONFIG_SYS_FPGA_VER_MASK) >> 8; -} - -/* - * Board early initialization function - */ -int board_early_init_f (void) -{ - u32 val; - - /*--------------------------------------------------------------------+ - | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board. - +--------------------------------------------------------------------+ - +---------------------------------------------------------------------+ - |Interrupt| Source | Pol. | Sensi.| Crit. | - +---------+-----------------------------------+-------+-------+-------+ - | IRQ 00 | UART0 | High | Level | Non | - | IRQ 01 | UART1 | High | Level | Non | - | IRQ 02 | IIC0 | High | Level | Non | - | IRQ 03 | TBD | High | Level | Non | - | IRQ 04 | TBD | High | Level | Non | - | IRQ 05 | EBM | High | Level | Non | - | IRQ 06 | BGI | High | Level | Non | - | IRQ 07 | IIC1 | Rising| Edge | Non | - | IRQ 08 | SPI | High | Lvl/ed| Non | - | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non | - | IRQ 10 | MAL TX EOB | High | Level | Non | - | IRQ 11 | MAL RX EOB | High | Level | Non | - | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non | - | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non | - | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non | - | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non | - | IRQ 16 | PCIE0 AL | high | Level | Non | - | IRQ 17 | PCIE0 VPD access | rising| Edge | Non | - | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non | - | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non | - | IRQ 20 | PCIE0 TCR | High | Level | Non | - | IRQ 21 | PCIE0 MSI level0 | High | Level | Non | - | IRQ 22 | PCIE0 MSI level1 | High | Level | Non | - | IRQ 23 | Security EIP-94 | High | Level | Non | - | IRQ 24 | EMAC0 interrupt | High | Level | Non | - | IRQ 25 | EMAC1 interrupt | High | Level | Non | - | IRQ 26 | PCIE0 MSI level2 | High | Level | Non | - | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non | - | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non | - | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. | - | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non | - | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. | - |---------------------------------------------------------------------- - | IRQ 32 | MAL Serr | High | Level | Non | - | IRQ 33 | MAL Txde | High | Level | Non | - | IRQ 34 | MAL Rxde | High | Level | Non | - | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non | - | IRQ 36 | PCIE0 DCR Error | High | Level | Non | - | IRQ 37 | EBC | High |Lvl Edg| Non | - | IRQ 38 | NDFC | High | Level | Non | - | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non | - | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non | - | IRQ 41 | PCIE1 AL | high | Level | Non | - | IRQ 42 | PCIE1 VPD access | rising| edge | Non | - | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non | - | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non | - | IRQ 45 | PCIE1 TCR | High | Level | Non | - | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non | - | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | - | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | - | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non | - | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non | - | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | - | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non | - | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non | - | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non | - | IRQ 55 | Serial ROM | High | Level | Non | - | IRQ 56 | GPT Decrement Pulse | High | Level | Non | - | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non | - | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non | - | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non | - | IRQ 60 | EMAC0 Wake-up | High | Level | Non | - | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non | - | IRQ 62 | EMAC1 Wake-up | High | Level | Non | - |---------------------------------------------------------------------- - | IRQ 64 | PE0 AL | High | Level | Non | - | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | - | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | - | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | - | IRQ 68 | PE0 TCR | High | Level | Non | - | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | - | IRQ 70 | PE0 DCR Error | High | Level | Non | - | IRQ 71 | Reserved | N/A | N/A | Non | - | IRQ 72 | PE1 AL | High | Level | Non | - | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | - | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | - | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | - | IRQ 76 | PE1 TCR | High | Level | Non | - | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | - | IRQ 78 | PE1 DCR Error | High | Level | Non | - | IRQ 79 | Reserved | N/A | N/A | Non | - | IRQ 80 | PE2 AL | High | Level | Non | - | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | - | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | - | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | - | IRQ 84 | PE2 TCR | High | Level | Non | - | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | - | IRQ 86 | PE2 DCR Error | High | Level | Non | - | IRQ 87 | Reserved | N/A | N/A | Non | - | IRQ 88 | External IRQ(5) | Progr | Progr | Non | - | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | - | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | - | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | - | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | - | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | - | IRQ 94 | Reserved | N/A | N/A | Non | - | IRQ 95 | Reserved | N/A | N/A | Non | - |--------------------------------------------------------------------- - +---------+-----------------------------------+-------+-------+------*/ - /*--------------------------------------------------------------------+ - | Initialise UIC registers. Clear all interrupts. Disable all - | interrupts. - | Set critical interrupt values. Set interrupt polarities. Set - | interrupt trigger levels. Make bit 0 High priority. Clear all - | interrupts again. - +-------------------------------------------------------------------*/ - - mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */ - mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */ - mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */ - mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ - - mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */ - mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */ - mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */ - mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */ - - mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */ - /* Except cascade UIC0 and UIC1 */ - mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */ - mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */ - mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */ - - /* - * Note: Some cores are still in reset when the chip starts, so - * take them out of reset - */ - mtsdr(SDR0_SRST, 0); - - /* Configure 405EX for NAND usage */ - val = SDR0_CUST0_MUX_NDFC_SEL | - SDR0_CUST0_NDFC_ENABLE | - SDR0_CUST0_NDFC_BW_8_BIT | - SDR0_CUST0_NRB_BUSY | - (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); - mtsdr(SDR0_CUST0, val); - - /* - * Configure PFC (Pin Function Control) registers - * -> Enable USB - */ - val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ; - mtsdr(SDR0_PFC1, val); - - /* - * The CPLD version detection has to be the first access to - * the CPLD, so we need to make this access this early and - * save the CPLD version for later. - */ - gd->board_type = board_cpld_version(); - - /* - * Configure FPGA register with PCIe reset - */ - out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */ - mdelay(50); - out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */ - - return 0; -} - -int misc_init_r(void) -{ -#ifdef CONFIG_ENV_IS_IN_FLASH - /* Monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); -#endif - - return 0; -} - -static int is_405exr(void) -{ - u32 pvr = get_pvr(); - - if (pvr & 0x00000004) - return 0; /* bit 2 set -> 405EX */ - - return 1; /* bit 2 cleared -> 405EXr */ -} - -int board_emac_count(void) -{ - /* - * 405EXr only has one EMAC interface, 405EX has two - */ - if (is_405exr()) - return 1; - else - return 2; -} - -/* - * Override the weak default implementation and return the - * last PCIe slot number (max number - 1). - */ -int board_pcie_last(void) -{ - /* - * 405EXr only has one EMAC interface, 405EX has two - */ - if (is_405exr()) - return 1 - 1; - else - return 2 - 1; -} - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - if (is_405exr()) - printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board"); - else - printf("Board: Kilauea - AMCC PPC405EX Evaluation Board"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - printf(" (CPLD rev. %ld)\n", gd->board_type); - - return (0); -} diff --git a/qemu/roms/u-boot/board/amcc/luan/Makefile b/qemu/roms/u-boot/board/amcc/luan/Makefile deleted file mode 100644 index 345ad564d..000000000 --- a/qemu/roms/u-boot/board/amcc/luan/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = luan.o flash.o -extra-y += init.o diff --git a/qemu/roms/u-boot/board/amcc/luan/config.mk b/qemu/roms/u-boot/board/amcc/luan/config.mk deleted file mode 100644 index f18b09710..000000000 --- a/qemu/roms/u-boot/board/amcc/luan/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/qemu/roms/u-boot/board/amcc/luan/epld.h b/qemu/roms/u-boot/board/amcc/luan/epld.h deleted file mode 100644 index 569d78c46..000000000 --- a/qemu/roms/u-boot/board/amcc/luan/epld.h +++ /dev/null @@ -1,85 +0,0 @@ -#define EPLD0_FSEL_FB2 0x80 -#define EPLD0_BOOT_SMALL_FLASH 0x40 /* 0 boot from large flash, 1 from small flash */ -#define EPLD0_RAW_CARD_BIT0 0x20 /* raw card EC level */ -#define EPLD0_RAW_CARD_BIT1 0x10 -#define EPLD0_RAW_CARD_BIT2 0x08 -#define EPLD0_EXT_ARB_SEL_N 0x04 /* 0 select on-board ext PCI-X, 1 internal arbiter */ -#define EPLD0_FLASH_ONBRD_N 0x02 /* 0 small flash/SRAM active, 1 block access */ -#define EPLD0_FLASH_SRAM_SEL_N 0x01 /* 0 SRAM at mem top, 1 small flash at mem top */ - -#define EPLD1_CLK_CNTL0 0x80 /* FSEL-FB1 of MPC9772 */ -#define EPLD1_PCIL0_CNTL1 0x40 /* S*0 of 9531 */ -#define EPLD1_PCIL0_CNTL2 0x20 /* S*1 of 9531 */ -#define EPLD1_CLK_CNTL3 0x10 /* FSEL-B1 of MPC9772 */ -#define EPLD1_CLK_CNTL4 0x08 /* FSEL-B0 of MPC9772 */ -#define EPLD1_MASTER_CLOCK6 0x04 /* clock source select 6 */ -#define EPLD1_MASTER_CLOCK7 0x02 /* clock source select 7 */ -#define EPLD1_MASTER_CLOCK8 0x01 /* clock source select 8 */ - -#define EPLD2_ETH_MODE_10 0x80 /* Ethernet mode 10 (default = 1) */ -#define EPLD2_ETH_MODE_100 0x40 /* Ethernet mode 100 (default = 1) */ -#define EPLD2_ETH_MODE_1000 0x20 /* Ethernet mode 1000 (default = 1) */ -#define EPLD2_ETH_DUPLEX_MODE 0x10 /* Ethernet force full duplex mode */ -#define EPLD2_RESET_ETH_N 0x08 /* Ethernet reset (default = 1) */ -#define EPLD2_ETH_AUTO_NEGO 0x04 /* Ethernet auto negotiation */ -#define EPLD2_DEFAULT_UART_N 0x01 /* 0 select DSR DTR for UART1 */ - -#define EPLD3_STATUS_LED4 0x08 /* status LED 8 (1 = LED on) */ -#define EPLD3_STATUS_LED3 0x04 /* status LED 4 (1 = LED on) */ -#define EPLD3_STATUS_LED2 0x02 /* status LED 2 (1 = LED on) */ -#define EPLD3_STATUS_LED1 0x01 /* status LED 1 (1 = LED on) */ - -#define EPLD4_PCIL0_VTH1 0x80 /* PCI-X 0 VTH1 status */ -#define EPLD4_PCIL0_VTH2 0x40 /* PCI-X 0 VTH2 status */ -#define EPLD4_PCIL0_VTH3 0x20 /* PCI-X 0 VTH3 status */ -#define EPLD4_PCIL0_VTH4 0x10 /* PCI-X 0 VTH4 status */ -#define EPLD4_PCIX1_VTH1 0x08 /* PCI-X 1 VTH1 status */ -#define EPLD4_PCIX1_VTH2 0x04 /* PCI-X 1 VTH2 status */ -#define EPLD4_PCIX1_VTH3 0x02 /* PCI-X 1 VTH3 status */ -#define EPLD4_PCIX1_VTH4 0x01 /* PCI-X 1 VTH4 status */ - -#define EPLD5_PCIL0_INT0 0x80 /* PCIX0 INT0 status, write 0 to reset */ -#define EPLD5_PCIL0_INT1 0x40 /* PCIX0 INT1 status, write 0 to reset */ -#define EPLD5_PCIL0_INT2 0x20 /* PCIX0 INT2 status, write 0 to reset */ -#define EPLD5_PCIL0_INT3 0x10 /* PCIX0 INT3 status, write 0 to reset */ -#define EPLD5_PCIX1_INT0 0x08 /* PCIX1 INT0 status, write 0 to reset */ -#define EPLD5_PCIX1_INT1 0x04 /* PCIX1 INT1 status, write 0 to reset */ -#define EPLD5_PCIX1_INT2 0x02 /* PCIX1 INT2 status, write 0 to reset */ -#define EPLD5_PCIX1_INT3 0x01 /* PCIX1 INT3 status, write 0 to reset */ - -#define EPLD6_PCIL0_RESET_CTL 0x80 /* 0=enable slot reset, 1=disable slot reset */ -#define EPLD6_PCIX1_RESET_CTL 0x40 /* 0=enable slot reset, 1=disable slot reset */ -#define EPLD6_ETH_INT_MODE 0x20 /* 0=IRQ5 recv's external eth int */ -#define EPLD6_PCIX2_RESET_CTL 0x10 /* 0=enable slot reset, 1=disable slot reset */ -#define EPLD6_PCI1_CLKCNTL1 0x80 /* PCI1 clock control S*0 of 9531 */ -#define EPLD6_PCI1_CLKCNTL2 0x40 /* PCI1 clock control S*1 of 9531 */ -#define EPLD6_PCI2_CLKCNTL1 0x20 /* PCI2 clock control S*0 of 9531 */ -#define EPLD6_PCI2_CLKCNTL2 0x10 /* PCI2 clock control S*1 of 9531 */ - -#define EPLD7_VTH1 0x80 /* PCI2 VTH1 status */ -#define EPLD7_VTH2 0x40 /* PCI2 VTH2 status */ -#define EPLD7_VTH3 0x20 /* PCI2 VTH3 status */ -#define EPLD7_VTH4 0x10 /* PCI2 VTH4 status */ -#define EPLD7_INTA_MODE 0x80 /* see S5 on SW2 for details */ -#define EPLD7_PCI_INT_MODE_N 0x40 /* see S1 on SW2 for details */ -#define EPLD7_WRITE_ENABLE_GPIO 0x20 /* see S2 on SW2 for details */ -#define EPLD7_WRITE_ENABLE_INT 0x10 /* see S3 on SW2 for details */ - - -typedef struct { - unsigned char status; /* misc status */ - unsigned char clock; /* clock status, PCI-X clock control */ - unsigned char ethuart; /* Ethernet, UART status */ - unsigned char leds; /* LED register */ - unsigned char vth01; /* PCI0, PCI1 VTH register */ - unsigned char pciints; /* PCI0, PCI1 interrupts */ - unsigned char pci2; /* PCI2 interrupts, clock control */ - unsigned char vth2; /* PCI2 VTH register */ - unsigned char filler1[4096-8]; - unsigned char gpio00; /* GPIO bits 0-7 */ - unsigned char gpio08; /* GPIO bits 8-15 */ - unsigned char gpio16; /* GPIO bits 16-23 */ - unsigned char gpio24; /* GPIO bits 24-31 */ - unsigned char filler2[4096-4]; - unsigned char version; /* EPLD version */ -} epld_t; diff --git a/qemu/roms/u-boot/board/amcc/luan/flash.c b/qemu/roms/u-boot/board/amcc/luan/flash.c deleted file mode 100644 index a242befb2..000000000 --- a/qemu/roms/u-boot/board/amcc/luan/flash.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> - * Add support for Am29F016D and dynamic switch setting. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -static unsigned long flash_addr_table[1][CONFIG_SYS_MAX_FLASH_BANKS] = { - {0xff900000, 0xff980000, 0xffc00000}, /* 0:000: configuraton 3 */ -}; - -/* - * include common flash code (for amcc boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); - -unsigned long flash_init(void) -{ - unsigned long total_b = 0; - unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; - unsigned short index = 0; - int i; - - /* read FPGA base register FPGA_REG0 */ - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - - /* check whether the address is 0 */ - if (flash_addr_table[index][i] == 0) { - continue; - } - - /* call flash_get_size() to initialize sector address */ - size_b[i] = flash_get_size((vu_long *) - flash_addr_table[index][i], - &flash_info[i]); - flash_info[i].size = size_b[i]; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i] << 20); - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - } - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[2]); -#ifdef CONFIG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[2]); - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[2]); -#endif - - total_b += flash_info[i].size; - } - - return total_b; -} diff --git a/qemu/roms/u-boot/board/amcc/luan/init.S b/qemu/roms/u-boot/board/amcc/luan/init.S deleted file mode 100644 index 0f4a78e1e..000000000 --- a/qemu/roms/u-boot/board/amcc/luan/init.S +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> -#include <asm/ppc4xx.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_RWX | SA_G) - - tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_RWX | SA_IG) - tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_RWX | SA_IG) - tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_RWX | SA_IG) - tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_RWX | SA_IG) - tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_RW | SA_IG) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - /* internal ram (l2 cache) */ - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_I) - - /* peripherals at f0000000 */ - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_RW | SA_IG) - - /* PCI */ - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_RW | SA_IG) - tlbtab_end diff --git a/qemu/roms/u-boot/board/amcc/luan/luan.c b/qemu/roms/u-boot/board/amcc/luan/luan.c deleted file mode 100644 index 774671db4..000000000 --- a/qemu/roms/u-boot/board/amcc/luan/luan.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * (C) Copyright 2005 - * John Otken, jotken@softadvances.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include <asm/ppc4xx-isram.h> -#include <spd_sdram.h> -#include "epld.h" - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -/************************************************************************* - * int board_early_init_f() - * - ************************************************************************/ -int board_early_init_f(void) -{ - u32 mfr; - - mtebc( PB0AP, 0x03800000 ); /* set chip selects */ - mtebc( PB0CR, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ - mtebc( PB1AP, 0x03800000 ); - mtebc( PB1CR, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */ - mtebc( PB2AP, 0x03800000 ); - mtebc( PB2CR, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */ - - mtdcr( UIC1SR, 0xffffffff ); /* Clear all interrupts */ - mtdcr( UIC1ER, 0x00000000 ); /* disable all interrupts */ - mtdcr( UIC1CR, 0x00000000 ); /* Set Critical / Non Critical interrupts */ - mtdcr( UIC1PR, 0x7fff83ff ); /* Set Interrupt Polarities */ - mtdcr( UIC1TR, 0x001f8000 ); /* Set Interrupt Trigger Levels */ - mtdcr( UIC1VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ - mtdcr( UIC1SR, 0x00000000 ); /* clear all interrupts */ - mtdcr( UIC1SR, 0xffffffff ); - - mtdcr( UIC0SR, 0xffffffff ); /* Clear all interrupts */ - mtdcr( UIC0ER, 0x00000000 ); /* disable all interrupts excepted cascade */ - mtdcr( UIC0CR, 0x00000001 ); /* Set Critical / Non Critical interrupts */ - mtdcr( UIC0PR, 0xffffffff ); /* Set Interrupt Polarities */ - mtdcr( UIC0TR, 0x01000004 ); /* Set Interrupt Trigger Levels */ - mtdcr( UIC0VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ - mtdcr( UIC0SR, 0x00000000 ); /* clear all interrupts */ - mtdcr( UIC0SR, 0xffffffff ); - - mfsdr(SDR0_MFR, mfr); - mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ - mtsdr(SDR0_MFR, mfr); - - return 0; -} - - -/************************************************************************* - * int misc_init_r() - * - ************************************************************************/ -int misc_init_r(void) -{ - volatile epld_t *x = (epld_t *) CONFIG_SYS_EPLD_BASE; - - /* set modes of operation */ - x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 | - EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE; - /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */ - x->ethuart &= ~EPLD2_ETH_AUTO_NEGO; - - /* put Ethernet+PHY in reset */ - x->ethuart &= ~EPLD2_RESET_ETH_N; - udelay(10000); - /* take Ethernet+PHY out of reset */ - x->ethuart |= EPLD2_RESET_ETH_N; - - return 0; -} - - -/************************************************************************* - * int checkboard() - * - ************************************************************************/ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: Luan - AMCC PPC440SP Evaluation Board"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -/* - * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with - * board specific values. - */ -u32 ddr_clktr(u32 default_val) { - return (SDRAM_CLKTR_CLKP_180_DEG_ADV); -} - -/************************************************************************* - * hw_watchdog_reset - * - * This routine is called to reset (keep alive) the watchdog timer - * - ************************************************************************/ -#if defined(CONFIG_HW_WATCHDOG) -void hw_watchdog_reset(void) -{ -} -#endif - - -/************************************************************************* - * int on_off() - * - ************************************************************************/ -static int on_off( const char *s ) -{ - if (strcmp(s, "on") == 0) { - return 1; - } else if (strcmp(s, "off") == 0) { - return 0; - } - return -1; -} - - -/************************************************************************* - * void l2cache_disable() - * - ************************************************************************/ -static void l2cache_disable(void) -{ - mtdcr( L2_CACHE_CFG, 0 ); -} - - -/************************************************************************* - * void l2cache_enable() - * - ************************************************************************/ -static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */ -{ - mtdcr( L2_CACHE_CFG, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */ - - mtdcr( L2_CACHE_ADDR, 0 ); /* set L2_ADDR with all zeros */ - - mtdcr( L2_CACHE_CMD, 0x80000000 ); /* issue HCLEAR command via L2_CMD */ - - while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 )) ;; /* poll L2_SR for completion */ - - mtdcr( L2_CACHE_CMD, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */ - - mtdcr( L2_CACHE_CMD, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */ - - mtdcr( L2_CACHE_SNP0, 0 ); /* snoop registers */ - mtdcr( L2_CACHE_SNP1, 0 ); - - __asm__ volatile ("sync"); /* msync */ - - mtdcr( L2_CACHE_CFG, 0xe0000000 ); /* inst and data use L2 */ - - __asm__ volatile ("sync"); -} - - -/************************************************************************* - * int l2cache_status() - * - ************************************************************************/ -static int l2cache_status(void) -{ - return (mfdcr( L2_CACHE_CFG ) & 0x60000000) != 0; -} - - -/************************************************************************* - * int do_l2cache() - * - ************************************************************************/ -int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] ) -{ - switch (argc) { - case 2: /* on / off */ - switch (on_off(argv[1])) { - case 0: l2cache_disable(); - break; - case 1: l2cache_enable(); - break; - } - /* FALL TROUGH */ - case 1: /* get status */ - printf ("L2 Cache is %s\n", - l2cache_status() ? "ON" : "OFF"); - return 0; - default: - return cmd_usage(cmdtp); - } - - return 0; -} - - -U_BOOT_CMD( - l2cache, 2, 1, do_l2cache, - "enable or disable L2 cache", - "[on, off]\n" - " - enable or disable L2 cache" -); diff --git a/qemu/roms/u-boot/board/amcc/makalu/Makefile b/qemu/roms/u-boot/board/amcc/makalu/Makefile deleted file mode 100644 index dcf162ca9..000000000 --- a/qemu/roms/u-boot/board/amcc/makalu/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = makalu.o cmd_pll.o -obj-y += init.o diff --git a/qemu/roms/u-boot/board/amcc/makalu/cmd_pll.c b/qemu/roms/u-boot/board/amcc/makalu/cmd_pll.c deleted file mode 100644 index f12655bea..000000000 --- a/qemu/roms/u-boot/board/amcc/makalu/cmd_pll.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * ehnus: change pll frequency. - * Wed Sep 5 11:45:17 CST 2007 - * hsun@udtech.com.cn - */ - - -#include <common.h> -#include <config.h> -#include <command.h> -#include <i2c.h> - -#ifdef CONFIG_CMD_EEPROM - -#define EEPROM_CONF_OFFSET 0 -#define EEPROM_TEST_OFFSET 16 -#define EEPROM_SDSTP_PARAM 16 - -#define PLL_NAME_MAX 12 -#define BUF_STEP 8 - -/* eeprom_wirtes 8Byte per op. */ -#define EEPROM_ALTER_FREQ(freq) \ - do { \ - int __i; \ - for (__i = 0; __i < 2; __i++) \ - eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, \ - EEPROM_CONF_OFFSET + __i*BUF_STEP, \ - pll_select[freq], \ - BUF_STEP + __i*BUF_STEP); \ - } while (0) - -#define PDEBUG -#ifdef PDEBUG -#define PLL_DEBUG pll_debug(EEPROM_CONF_OFFSET) -#else -#define PLL_DEBUG -#endif - -typedef enum { - PLL_ebc20, - PLL_333, - PLL_4001, - PLL_4002, - PLL_533, - PLL_600, - PLL_666, /* For now, kilauea can't support */ - RCONF, - WTEST, - PLL_TOTAL -} pll_freq_t; - -static const char -pll_name[][PLL_NAME_MAX] = { - "PLL_ebc20", - "PLL_333", - "PLL_400@1", - "PLL_400@2", - "PLL_533", - "PLL_600", - "PLL_666", - "RCONF", - "WTEST", - "" -}; - -/* - * ehnus: - */ -static uchar -pll_select[][EEPROM_SDSTP_PARAM] = { - /* 0: CPU 333MHz EBC 20MHz, for test only */ - { - 0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - }, - - /* 0: 333 */ - { - 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - }, - - /* 1: 400_266 */ - { - 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - }, - - /* 2: 400 */ - { - 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - }, - - /* 3: 533 */ - { - 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - }, - - /* 4: 600 */ - { - 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - }, - - /* 5: 666 */ - { - 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - }, - - {} -}; - -static uchar -testbuf[EEPROM_SDSTP_PARAM] = { - 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, - 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff -}; - -static void -pll_debug(int off) -{ - int i; - uchar buffer[EEPROM_SDSTP_PARAM]; - - memset(buffer, 0, sizeof(buffer)); - eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off, - buffer, EEPROM_SDSTP_PARAM); - - printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off); - for (i = 0; i < EEPROM_SDSTP_PARAM; i++) - printf("%02x ", buffer[i]); - printf("\n"); -} - -static void -test_write(void) -{ - printf("Debug: test eeprom_write ... "); - - /* - * Write twice, 8 bytes per write - */ - eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET, - testbuf, 8); - eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8, - testbuf, 16); - printf("done\n"); - - pll_debug(EEPROM_TEST_OFFSET); -} - -int -do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - char c = '\0'; - pll_freq_t pll_freq; - - if (argc < 2) - return cmd_usage(cmdtp); - - for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++) { - if (!strcmp(pll_name[pll_freq], argv[1])) - break; - } - - switch (pll_freq) { - case PLL_ebc20: - case PLL_333: - case PLL_4001: - case PLL_4002: - case PLL_533: - case PLL_600: - EEPROM_ALTER_FREQ(pll_freq); - break; - - case PLL_666: /* not support */ - printf("Choose this option will result in a boot failure." - "\nContinue? (Y/N): "); - - c = getc(); putc('\n'); - - if ((c == 'y') || (c == 'Y')) { - EEPROM_ALTER_FREQ(pll_freq); - break; - } - goto ret; - - case RCONF: - pll_debug(EEPROM_CONF_OFFSET); - goto ret; - case WTEST: - printf("DEBUG: write test\n"); - test_write(); - goto ret; - - default: - printf("Invalid options\n\n"); - return cmd_usage(cmdtp); - } - - printf("PLL set to %s, " - "reset the board to take effect\n", pll_name[pll_freq]); - - PLL_DEBUG; -ret: - return 0; -} - -U_BOOT_CMD( - pllalter, CONFIG_SYS_MAXARGS, 1, do_pll_alter, - "change pll frequence", - "pllalter <selection> - change pll frequence \n\n\ - ** New freq take effect after reset. ** \n\ - ----------------------------------------------\n\ - PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\ - \t Same as PLL_333 \n\ - \t except \n\ - \t EBC: 20 MHz \n\ - ----------------------------------------------\n\ - PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\ - \t VCO: 666 MHz \n\ - \t CPU: 333 MHz \n\ - \t PLB: 166 MHz \n\ - \t OPB: 83 MHz \n\ - \t DDR: 83 MHz \n\ - ------------------------------------------------\n\ - PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\ - \t VCO: 800 MHz \n\ - \t CPU: 400 MHz \n\ - \t PLB: 133 MHz \n\ - \t OPB: 66 MHz \n\ - \t DDR: 133 MHz \n\ - ------------------------------------------------\n\ - PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\ - \t VCO: 800 MHz \n\ - \t CPU: 400 MHz \n\ - \t PLB: 200 MHz \n\ - \t OPB: 100 MHz \n\ - \t DDR: 200 MHz \n\ - ----------------------------------------------\n\ - PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\ - \t VCO: 1066 MHz \n\ - \t CPU: 533 MHz \n\ - \t PLB: 177 MHz \n\ - \t OPB: 88 MHz \n\ - \t DDR: 177 MHz \n\ - ----------------------------------------------\n\ - PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\ - \t VCO: 1200 MHz \n\ - \t CPU: 600 MHz \n\ - \t PLB: 200 MHz \n\ - \t OPB: 100 MHz \n\ - \t DDR: 200 MHz \n\ - ----------------------------------------------\n\ - PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\ - \t VCO: 1333 MHz \n\ - \t CPU: 666 MHz \n\ - \t PLB: 166 MHz \n\ - \t OPB: 83 MHz \n\ - \t DDR: 166 MHz \n\ - -----------------------------------------------\n\ - RCONF: Read current eeprom configuration. \n\ - -----------------------------------------------\n\ - WTEST: Test EEPROM write with predefined values\n\ - -----------------------------------------------" -); - -#endif /* CONFIG_CMD_EEPROM */ diff --git a/qemu/roms/u-boot/board/amcc/makalu/init.S b/qemu/roms/u-boot/board/amcc/makalu/init.S deleted file mode 100644 index e15c62249..000000000 --- a/qemu/roms/u-boot/board/amcc/makalu/init.S +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2008 Nuovation System Designs, LLC - * Grant Erickson <gerickson@nuovations.com> - * - * (C) Copyright 2007-2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Originally based on code provided from Senao and AMCC - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - blr diff --git a/qemu/roms/u-boot/board/amcc/makalu/makalu.c b/qemu/roms/u-boot/board/amcc/makalu/makalu.c deleted file mode 100644 index a6ad2a1ba..000000000 --- a/qemu/roms/u-boot/board/amcc/makalu/makalu.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/ppc405.h> -#include <libfdt.h> -#include <asm/processor.h> -#include <asm/ppc4xx-gpio.h> -#include <asm/io.h> -#include <fdt_support.h> -#include <asm/errno.h> - -#if defined(CONFIG_PCI) -#include <pci.h> -#include <asm/4xx_pcie.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * Board early initialization function - */ -int board_early_init_f (void) -{ - u32 val; - - /*--------------------------------------------------------------------+ - | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board. - +--------------------------------------------------------------------+ - +---------------------------------------------------------------------+ - |Interrupt| Source | Pol. | Sensi.| Crit. | - +---------+-----------------------------------+-------+-------+-------+ - | IRQ 00 | UART0 | High | Level | Non | - | IRQ 01 | UART1 | High | Level | Non | - | IRQ 02 | IIC0 | High | Level | Non | - | IRQ 03 | TBD | High | Level | Non | - | IRQ 04 | TBD | High | Level | Non | - | IRQ 05 | EBM | High | Level | Non | - | IRQ 06 | BGI | High | Level | Non | - | IRQ 07 | IIC1 | Rising| Edge | Non | - | IRQ 08 | SPI | High | Lvl/ed| Non | - | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non | - | IRQ 10 | MAL TX EOB | High | Level | Non | - | IRQ 11 | MAL RX EOB | High | Level | Non | - | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non | - | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non | - | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non | - | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non | - | IRQ 16 | PCIE0 AL | high | Level | Non | - | IRQ 17 | PCIE0 VPD access | rising| Edge | Non | - | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non | - | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non | - | IRQ 20 | PCIE0 TCR | High | Level | Non | - | IRQ 21 | PCIE0 MSI level0 | High | Level | Non | - | IRQ 22 | PCIE0 MSI level1 | High | Level | Non | - | IRQ 23 | Security EIP-94 | High | Level | Non | - | IRQ 24 | EMAC0 interrupt | High | Level | Non | - | IRQ 25 | EMAC1 interrupt | High | Level | Non | - | IRQ 26 | PCIE0 MSI level2 | High | Level | Non | - | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non | - | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non | - | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. | - | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non | - | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. | - |---------------------------------------------------------------------- - | IRQ 32 | MAL Serr | High | Level | Non | - | IRQ 33 | MAL Txde | High | Level | Non | - | IRQ 34 | MAL Rxde | High | Level | Non | - | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non | - | IRQ 36 | PCIE0 DCR Error | High | Level | Non | - | IRQ 37 | EBC | High |Lvl Edg| Non | - | IRQ 38 | NDFC | High | Level | Non | - | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non | - | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non | - | IRQ 41 | PCIE1 AL | high | Level | Non | - | IRQ 42 | PCIE1 VPD access | rising| edge | Non | - | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non | - | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non | - | IRQ 45 | PCIE1 TCR | High | Level | Non | - | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non | - | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | - | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | - | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non | - | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non | - | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | - | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non | - | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non | - | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non | - | IRQ 55 | Serial ROM | High | Level | Non | - | IRQ 56 | GPT Decrement Pulse | High | Level | Non | - | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non | - | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non | - | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non | - | IRQ 60 | EMAC0 Wake-up | High | Level | Non | - | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non | - | IRQ 62 | EMAC1 Wake-up | High | Level | Non | - |---------------------------------------------------------------------- - | IRQ 64 | PE0 AL | High | Level | Non | - | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | - | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | - | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | - | IRQ 68 | PE0 TCR | High | Level | Non | - | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | - | IRQ 70 | PE0 DCR Error | High | Level | Non | - | IRQ 71 | Reserved | N/A | N/A | Non | - | IRQ 72 | PE1 AL | High | Level | Non | - | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | - | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | - | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | - | IRQ 76 | PE1 TCR | High | Level | Non | - | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | - | IRQ 78 | PE1 DCR Error | High | Level | Non | - | IRQ 79 | Reserved | N/A | N/A | Non | - | IRQ 80 | PE2 AL | High | Level | Non | - | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | - | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | - | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | - | IRQ 84 | PE2 TCR | High | Level | Non | - | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | - | IRQ 86 | PE2 DCR Error | High | Level | Non | - | IRQ 87 | Reserved | N/A | N/A | Non | - | IRQ 88 | External IRQ(5) | Progr | Progr | Non | - | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | - | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | - | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | - | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | - | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | - | IRQ 94 | Reserved | N/A | N/A | Non | - | IRQ 95 | Reserved | N/A | N/A | Non | - |--------------------------------------------------------------------- - +---------+-----------------------------------+-------+-------+------*/ - /*--------------------------------------------------------------------+ - | Initialise UIC registers. Clear all interrupts. Disable all - | interrupts. - | Set critical interrupt values. Set interrupt polarities. Set - | interrupt trigger levels. Make bit 0 High priority. Clear all - | interrupts again. - +-------------------------------------------------------------------*/ - - mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */ - mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */ - mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */ - mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ - - mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */ - mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */ - mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */ - mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */ - - mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */ - /* Except cascade UIC0 and UIC1 */ - mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */ - mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */ - mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */ - - /* - * Note: Some cores are still in reset when the chip starts, so - * take them out of reset - */ - mtsdr(SDR0_SRST, 0); - - /* Reset PCIe slots */ - gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 0); - udelay(100); - gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 1); - - /* - * Configure PFC (Pin Function Control) registers - * -> Enable USB - */ - val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ; - mtsdr(SDR0_PFC1, val); - - return 0; -} - -int misc_init_r(void) -{ -#ifdef CONFIG_ENV_IS_IN_FLASH - /* Monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); -#endif - - return 0; -} - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: Makalu - AMCC PPC405EX Evaluation Board"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} diff --git a/qemu/roms/u-boot/board/amcc/ocotea/Makefile b/qemu/roms/u-boot/board/amcc/ocotea/Makefile deleted file mode 100644 index 7646bbb96..000000000 --- a/qemu/roms/u-boot/board/amcc/ocotea/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = ocotea.o flash.o -extra-y += init.o diff --git a/qemu/roms/u-boot/board/amcc/ocotea/README.ocotea b/qemu/roms/u-boot/board/amcc/ocotea/README.ocotea deleted file mode 100644 index be79b03c8..000000000 --- a/qemu/roms/u-boot/board/amcc/ocotea/README.ocotea +++ /dev/null @@ -1,73 +0,0 @@ - AMCC Ocotea Board - - Last Update: March 2, 2004 -======================================================================= - -This file contains some handy info regarding U-Boot and the AMCC -Ocotea 440gx evaluation board. See the README.ppc440 for additional -information. - - -SWITCH SETTINGS & JUMPERS -========================== - -Here's what I've been using successfully. If you feel inclined to -change things ... please read the docs! - -DIPSW U46 U80 ------------------------- -SW 1 off off -SW 2 on off -SW 3 off off -SW 4 off off -SW 5 off off -SW 6 on on -SW 7 on off -SW 8 on off - -J41: strapped -J42: open - -All others are factory default. - - -I2C Information -===================== - -See README.ebony for information. - -PCI -=========================== - -Untested at the time of writing. - -PPC440GX Ethernet EMACs -=========================== - -All EMAC ports have been tested and are known to work -with EPS Group 4. - -Special note about the Cicada CIS8201: - The CIS8201 Gigabit PHY comes up in GMII mode by default. - One must hit an extended register to allow use of RGMII mode. - This has been done in the 440gx_enet.c file with a #ifdef/endif - pair. - -AMCC does not store the EMAC ethernet addresses within their PIBS bootloader. -The addresses contained in the config header file are from my particular -board and you _*should*_ change them to reflect your board either in the -config file and/or in your environment variables. I found the addresses on -labels on the bottom side of the board. - - -BDI2k or JTAG Debugging -=========================== - -For ease of debugging you can swap the small boot flash and external SRAM -by changing U46:3 to on. You can then use the sram as your boot flash by -loading the sram via the jtag debugger. - - -Regards, ---Travis -<tsawyer@sandburst.com> diff --git a/qemu/roms/u-boot/board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot b/qemu/roms/u-boot/board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot deleted file mode 100644 index 25dd2a237..000000000 --- a/qemu/roms/u-boot/board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot +++ /dev/null @@ -1,99 +0,0 @@ ------------------------------------------- -Installation of U-Boot using PIBS firmware ------------------------------------------- - -This document describes how to install U-Boot on the Ocotea PPC440GX -Evaluation Board. We do not erase the PIBS firmware but install U-Boot in the -soldered FLASH. After this you should be able to switch between PIBS and -U-Boot via the switch U46 SW1. Please check that SW1 is off (= open) before -continuing. - -Connect to the serial port 0 (J11 lower) of the Ocotea board using the cu -program. See the hints for configuring cu above. Make sure you can -communicate with the PIBS firmware: reset the board and hit ENTER a couple of -times until you see the PIBS prompt (PIBS $). Then proceed as follows: - - -Read MAC Addresses from PIBS ----------------------------- - -To read the configured MAC addresses available on your Ocotea board please use -the following commands: - -PIBS $ echo $hwdaddr0 -000173017FE3 -PIBS $ echo $hwdaddr1 -000173017FE4 -PIBS $ echo $hwdaddr2 -000173017FE1 -PIBS $ echo $hwdaddr3 -000173017FE2 - -In U-Boot this is stored in the following environment variables: - -* Ethernet Address 0: ethaddr = 000173017FE3 (==> 00:01:73:01:7F:E3) -* Ethernet Address 1: eth1addr = 000173017FE4 (==> 00:01:73:01:7F:E4) -* Ethernet Address 2: eth2addr = 000173017FE1 (==> 00:01:73:01:7F:E1) -* Ethernet Address 3: eth3addr = 000173017FE2 (==> 00:01:73:01:7F:E2) - - -Configure the network interface (ent0 == emac0) ------------------------------------------------ - -To download the U-Boot image we need to configure the ethernet interface with -the following commands: - -PIBS $ ifconfig ent0 192.168.160.142 netmask 255.255.0.0 up -PIBS $ set ipdstaddr0=192.168.1.1 -status: writing PIBS variable value to FLASH -PIBS $ set bootfilename=/tftpboot/ocotea/u-boot.bin -status: writing PIBS variable value to FLASH - -Please insert correct parameters for your configuration (ip-addresses and -file-location). - - -Program U-Boot into soldered User-FLASH ---------------------------------------- - -Please make sure to use a newer version of U-Boot (at least 1.1.3), since -older versions don't support running from user-FLASH. - -To program U-Boot into the soldered user-FLASH use the following command: - -PIBS $ storefile bin eth 0xffbc0000 - -This commands loads the file vis ethernet into ram and copies it into the -user-FLASH. - - -Switch to U-Boot ----------------- - -Now you can turn your board off and switch SW1 (U46) to on (= closed). After -powering the board you should see the following message: - -U-Boot 1.1.3 (Apr 5 2005 - 22:59:57) - -AMCC PowerPC 440 GX Rev. C -Board: AMCC 440GX Evaluation Board - VCO: 1066 MHz - CPU: 533 MHz - PLB: 152 MHz - OPB: 76 MHz - EPB: 76 MHz -I2C: ready -DRAM: 256 MB -FLASH: 5 MB -PCI: Bus Dev VenId DevId Class Int -In: serial -Out: serial -Err: serial -KGDB: kgdb ready -ready -Net: ppc_440x_eth0, ppc_440x_eth1, ppc_440x_eth2, ppc_440x_eth3 -BEDBUG:ready -=> - - -April 06 2005, Stefan Roese <sr@denx.de> diff --git a/qemu/roms/u-boot/board/amcc/ocotea/config.mk b/qemu/roms/u-boot/board/amcc/ocotea/config.mk deleted file mode 100644 index e19b561f9..000000000 --- a/qemu/roms/u-boot/board/amcc/ocotea/config.mk +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# AMCC 440GX Reference Platform (Ocotea) board -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/qemu/roms/u-boot/board/amcc/ocotea/flash.c b/qemu/roms/u-boot/board/amcc/ocotea/flash.c deleted file mode 100644 index a9bbf045d..000000000 --- a/qemu/roms/u-boot/board/amcc/ocotea/flash.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * (C) Copyright 2004-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> - * Add support for Am29F016D and dynamic switch setting. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -#undef DEBUG - -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -#define BOOT_SMALL_FLASH 0x40 /* 01000000 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ - -#define BOOT_SMALL_FLASH_VAL 4 -#define FLASH_ONBD_N_VAL 2 -#define FLASH_SRAM_SEL_VAL 1 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = { - {0xFF800000, 0xFF880000, 0xFFC00000}, /* 0:000: configuraton 4 */ - {0xFF900000, 0xFF980000, 0xFFC00000}, /* 1:001: configuraton 3 */ - {0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */ - {0x00000000, 0x00000000, 0x00000000}, /* 3:011: configuraton 7 */ - {0xFFE00000, 0xFFF00000, 0xFF800000}, /* 4:100: configuraton 2 */ - {0xFFF00000, 0xFFF80000, 0xFF800000}, /* 5:101: configuraton 1 */ - {0x00000000, 0x00000000, 0x00000000}, /* 6:110: configuraton 6 */ - {0x00000000, 0x00000000, 0x00000000} /* 7:111: configuraton 5 */ -}; - -/* - * include common flash code (for amcc boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_word(flash_info_t * info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - unsigned long total_b = 0; - unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; - unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE; - unsigned char switch_status; - unsigned short index = 0; - int i; - - /* read FPGA base register FPGA_REG0 */ - switch_status = *fpga_base; - - /* check the bitmap of switch status */ - if (switch_status & BOOT_SMALL_FLASH) { - index += BOOT_SMALL_FLASH_VAL; - } - if (switch_status & FLASH_ONBD_N) { - index += FLASH_ONBD_N_VAL; - } - if (switch_status & FLASH_SRAM_SEL) { - index += FLASH_SRAM_SEL_VAL; - } - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - - /* check whether the address is 0 */ - if (flash_addr_table[index][i] == 0) { - continue; - } - - /* call flash_get_size() to initialize sector address */ - size_b[i] = - flash_get_size((vu_long *) flash_addr_table[index][i], - &flash_info[i]); - flash_info[i].size = size_b[i]; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf - ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i] << 20); - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - } - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[i]); -#ifdef CONFIG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[i]); - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[i]); -#endif - - total_b += flash_info[i].size; - } - - return total_b; -} diff --git a/qemu/roms/u-boot/board/amcc/ocotea/init.S b/qemu/roms/u-boot/board/amcc/ocotea/init.S deleted file mode 100644 index 35085f0a0..000000000 --- a/qemu/roms/u-boot/board/amcc/ocotea/init.S +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> -#include <asm/ppc4xx.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX) - tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX) - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG) - tlbtab_end diff --git a/qemu/roms/u-boot/board/amcc/ocotea/ocotea.c b/qemu/roms/u-boot/board/amcc/ocotea/ocotea.c deleted file mode 100644 index 5f11f195e..000000000 --- a/qemu/roms/u-boot/board/amcc/ocotea/ocotea.c +++ /dev/null @@ -1,387 +0,0 @@ -/* - * Copyright (C) 2004 PaulReynolds@lhsolutions.com - * - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include "ocotea.h" -#include <asm/processor.h> -#include <spd_sdram.h> -#include <asm/ppc4xx-emac.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define BOOT_SMALL_FLASH 32 /* 00100000 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ - -long int fixed_sdram (void); -void fpga_init (void); - -int board_early_init_f (void) -{ - unsigned long mfr; - unsigned char *fpga_base = (unsigned char *) CONFIG_SYS_FPGA_BASE; - unsigned char switch_status; - unsigned long cs0_base; - unsigned long cs0_size; - unsigned long cs0_twt; - unsigned long cs2_base; - unsigned long cs2_size; - unsigned long cs2_twt; - - /*-------------------------------------------------------------------------+ - | Initialize EBC CONFIG - +-------------------------------------------------------------------------*/ - mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | - EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | - EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | - EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | - EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); - - /*-------------------------------------------------------------------------+ - | FPGA. Initialize bank 7 with default values. - +-------------------------------------------------------------------------*/ - mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| - EBC_BXAP_BCE_DISABLE| - EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| - EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| - EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| - EBC_BXAP_BEM_WRITEONLY| - EBC_BXAP_PEN_DISABLED); - mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)| - EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); - - /* read FPGA base register FPGA_REG0 */ - switch_status = *fpga_base; - - if (switch_status & 0x40) { - cs0_base = 0xFFE00000; - cs0_size = EBC_BXCR_BS_2MB; - cs0_twt = 8; - cs2_base = 0xFF800000; - cs2_size = EBC_BXCR_BS_4MB; - cs2_twt = 10; - } else { - cs0_base = 0xFFC00000; - cs0_size = EBC_BXCR_BS_4MB; - cs0_twt = 10; - cs2_base = 0xFF800000; - cs2_size = EBC_BXCR_BS_2MB; - cs2_twt = 8; - } - - /*-------------------------------------------------------------------------+ - | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values. - +-------------------------------------------------------------------------*/ - mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)| - EBC_BXAP_BCE_DISABLE| - EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| - EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| - EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| - EBC_BXAP_BEM_WRITEONLY| - EBC_BXAP_PEN_DISABLED); - mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(cs0_base)| - cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); - - /*-------------------------------------------------------------------------+ - | 8KB NVRAM/RTC. Initialize bank 1 with default values. - +-------------------------------------------------------------------------*/ - mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)| - EBC_BXAP_BCE_DISABLE| - EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| - EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| - EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| - EBC_BXAP_BEM_WRITEONLY| - EBC_BXAP_PEN_DISABLED); - mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000)| - EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); - - /*-------------------------------------------------------------------------+ - | 4 MB FLASH. Initialize bank 2 with default values. - +-------------------------------------------------------------------------*/ - mtebc(PB2AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)| - EBC_BXAP_BCE_DISABLE| - EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| - EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| - EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| - EBC_BXAP_BEM_WRITEONLY| - EBC_BXAP_PEN_DISABLED); - mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(cs2_base)| - cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); - - /*-------------------------------------------------------------------------+ - | FPGA. Initialize bank 7 with default values. - +-------------------------------------------------------------------------*/ - mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| - EBC_BXAP_BCE_DISABLE| - EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| - EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| - EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| - EBC_BXAP_BEM_WRITEONLY| - EBC_BXAP_PEN_DISABLED); - mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)| - EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - /* - * Because of the interrupt handling rework to handle 440GX interrupts - * with the common code, we needed to change names of the UIC registers. - * Here the new relationship: - * - * U-Boot name 440GX name - * ----------------------- - * UIC0 UICB0 - * UIC1 UIC0 - * UIC2 UIC1 - * UIC3 UIC2 - */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - mtdcr (UIC1ER, 0x00000000); /* disable all */ - mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */ - mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */ - mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - mtdcr (UIC2ER, 0x00000000); /* disable all */ - mtdcr (UIC2CR, 0x00000000); /* all non-critical */ - mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */ - mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */ - mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - mtdcr (UIC3ER, 0x00000000); /* disable all */ - mtdcr (UIC3CR, 0x00000000); /* all non-critical */ - mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */ - mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */ - mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - - mtdcr (UIC0SR, 0xfc000000); /* clear all */ - mtdcr (UIC0ER, 0x00000000); /* disable all */ - mtdcr (UIC0CR, 0x00000000); /* all non-critical */ - mtdcr (UIC0PR, 0xfc000000); /* */ - mtdcr (UIC0TR, 0x00000000); /* */ - mtdcr (UIC0VR, 0x00000001); /* */ - mfsdr (SDR0_MFR, mfr); - mfr &= ~SDR0_MFR_ECS_MASK; -/* mtsdr(SDR0_MFR, mfr); */ - fpga_init(); - - return 0; -} - - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc ('\n'); - - return (0); -} - - -phys_size_t initdram (int board_type) -{ - long dram_size = 0; - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (); -#else - dram_size = fixed_sdram (); -#endif - return dram_size; -} - - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - * - * Assumes: 128 MB, non-ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -long int fixed_sdram (void) -{ - uint reg; - - /*-------------------------------------------------------------------- - * Setup some default - *------------------------------------------------------------------*/ - mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ - mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ - - /*-------------------------------------------------------------------- - * Setup for board-specific specific mem - *------------------------------------------------------------------*/ - /* - * Following for CAS Latency = 2.5 @ 133 MHz PLB - */ - mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ - /* RA=10 RD=3 */ - mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ - udelay (400); /* Delay 200 usecs (min) */ - - /*-------------------------------------------------------------------- - * Enable the controller, then wait for DCEN to complete - *------------------------------------------------------------------*/ - mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ - for (;;) { - mfsdram (SDRAM0_MCSTS, reg); - if (reg & 0x80000000) - break; - } - - return (128 * 1024 * 1024); /* 128 MB */ -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - -void fpga_init(void) -{ - unsigned long group; - unsigned long sdr0_pfc0; - unsigned long sdr0_pfc1; - unsigned long sdr0_cust0; - unsigned long pvr; - - mfsdr (SDR0_PFC0, sdr0_pfc0); - mfsdr (SDR0_PFC1, sdr0_pfc1); - group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1); - pvr = get_pvr (); - - sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE; - if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) { - sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; - out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | - FPGA_REG2_EXT_INTFACE_ENABLE); - mtsdr (SDR0_PFC0, sdr0_pfc0); - mtsdr (SDR0_PFC1, sdr0_pfc1); - } else { - sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE; - switch (group) - { - case 0: - case 1: - case 2: - /* CPU trace A */ - out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | - FPGA_REG2_EXT_INTFACE_ENABLE); - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; - mtsdr (SDR0_PFC0, sdr0_pfc0); - mtsdr (SDR0_PFC1, sdr0_pfc1); - break; - case 3: - case 4: - case 5: - case 6: - /* CPU trace B - Over EBMI */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE; - mtsdr (SDR0_PFC0, sdr0_pfc0); - mtsdr (SDR0_PFC1, sdr0_pfc1); - out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | - FPGA_REG2_EXT_INTFACE_DISABLE); - break; - } - } - - /* Initialize the ethernet specific functions in the fpga */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - mfsdr(SDR0_CUST0, sdr0_cust0); - if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) && - ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) || - (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI))) - { - if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) - { - out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) | - FPGA_REG3_ENET_GROUP7); - } - else - { - if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) - { - out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | - FPGA_REG3_ENET_GROUP7); - } - else - { - out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | - FPGA_REG3_ENET_GROUP8); - } - } - } - else - { - if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) - { - out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) | - FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1))); - } - else - { - out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | - FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1))); - } - } - out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 | - FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 | - FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS); - - /* reset the gigabyte phy if necessary */ - if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3) - { - if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) - { - out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE); - udelay(10000); - out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE); - } - else - { - out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE); - udelay(10000); - out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE); - } - } - - /* - * new Ocotea with Rev. F (pass 3) chips has SMII PHY reset - */ - if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) { - out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE); - udelay(10000); - out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE); - } - - /* Turn off the LED's */ - out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) | - FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB | - FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB); - - return; -} diff --git a/qemu/roms/u-boot/board/amcc/ocotea/ocotea.h b/qemu/roms/u-boot/board/amcc/ocotea/ocotea.h deleted file mode 100644 index 853002f4b..000000000 --- a/qemu/roms/u-boot/board/amcc/ocotea/ocotea.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Board specific FPGA stuff ... */ -#define FPGA_REG0 (CONFIG_SYS_FPGA_BASE + 0x00) -#define FPGA_REG0_SSCG_MASK 0x80 -#define FPGA_REG0_SSCG_DISABLE 0x00 -#define FPGA_REG0_SSCG_ENABLE 0x80 -#define FPGA_REG0_BOOT_MASK 0x40 -#define FPGA_REG0_BOOT_LARGE_FLASH 0x00 -#define FPGA_REG0_BOOT_SMALL_FLASH 0x40 -#define FPGA_REG0_ECLS_MASK 0x38 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_0 0x20 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_1 0x10 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_2 0x08 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER1 0x00 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER3 0x08 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER4 0x10 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER5 0x18 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER2 0x20 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER6 0x28 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER7 0x30 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ECLS_VER8 0x38 /* New for Ocotea Rev 2 */ -#define FPGA_REG0_ARBITER_MASK 0x04 -#define FPGA_REG0_ARBITER_EXT 0x00 -#define FPGA_REG0_ARBITER_INT 0x04 -#define FPGA_REG0_ONBOARD_FLASH_MASK 0x02 -#define FPGA_REG0_ONBOARD_FLASH_ENABLE 0x00 -#define FPGA_REG0_ONBOARD_FLASH_DISABLE 0x02 -#define FPGA_REG0_FLASH 0x01 -#define FPGA_REG1 (CONFIG_SYS_FPGA_BASE + 0x01) -#define FPGA_REG1_9772_FSELFBX_MASK 0x80 -#define FPGA_REG1_9772_FSELFBX_6 0x00 -#define FPGA_REG1_9772_FSELFBX_10 0x80 -#define FPGA_REG1_9531_SX_MASK 0x60 -#define FPGA_REG1_9531_SX_33MHZ 0x00 -#define FPGA_REG1_9531_SX_100MHZ 0x20 -#define FPGA_REG1_9531_SX_66MHZ 0x40 -#define FPGA_REG1_9531_SX_133MHZ 0x60 -#define FPGA_REG1_9772_FSELBX_MASK 0x18 -#define FPGA_REG1_9772_FSELBX_4 0x00 -#define FPGA_REG1_9772_FSELBX_6 0x08 -#define FPGA_REG1_9772_FSELBX_8 0x10 -#define FPGA_REG1_9772_FSELBX_10 0x18 -#define FPGA_REG1_SOURCE_MASK 0x07 -#define FPGA_REG1_SOURCE_TC 0x00 -#define FPGA_REG1_SOURCE_66MHZ 0x01 -#define FPGA_REG1_SOURCE_50MHZ 0x02 -#define FPGA_REG1_SOURCE_33MHZ 0x03 -#define FPGA_REG1_SOURCE_25MHZ 0x04 -#define FPGA_REG1_SOURCE_SSDIV1 0x05 -#define FPGA_REG1_SOURCE_SSDIV2 0x06 -#define FPGA_REG1_SOURCE_SSDIV4 0x07 -#define FPGA_REG2 (CONFIG_SYS_FPGA_BASE + 0x02) -#define FPGA_REG2_TC0 0x80 -#define FPGA_REG2_TC1 0x40 -#define FPGA_REG2_TC2 0x20 -#define FPGA_REG2_TC3 0x10 -#define FPGA_REG2_GIGABIT_RESET_DISABLE 0x08 /*Use on Ocotea pass 2 boards*/ -#define FPGA_REG2_EXT_INTFACE_MASK 0x04 -#define FPGA_REG2_EXT_INTFACE_ENABLE 0x00 -#define FPGA_REG2_EXT_INTFACE_DISABLE 0x04 -#define FPGA_REG2_SMII_RESET_DISABLE 0x02 /*Use on Ocotea pass 3 boards*/ -#define FPGA_REG2_DEFAULT_UART1_N 0x01 -#define FPGA_REG3 (CONFIG_SYS_FPGA_BASE + 0x03) -#define FPGA_REG3_GIGABIT_RESET_DISABLE 0x80 /*Use on Ocotea pass 1 boards*/ -#define FPGA_REG3_ENET_MASK1 0x70 /*Use on Ocotea pass 1 boards*/ -#define FPGA_REG3_ENET_MASK2 0xF0 /*Use on Ocotea pass 2 boards*/ -#define FPGA_REG3_ENET_GROUP0 0x00 -#define FPGA_REG3_ENET_GROUP1 0x10 -#define FPGA_REG3_ENET_GROUP2 0x20 -#define FPGA_REG3_ENET_GROUP3 0x30 -#define FPGA_REG3_ENET_GROUP4 0x40 -#define FPGA_REG3_ENET_GROUP5 0x50 -#define FPGA_REG3_ENET_GROUP6 0x60 -#define FPGA_REG3_ENET_GROUP7 0x70 -#define FPGA_REG3_ENET_GROUP8 0x80 /*Use on Ocotea pass 2 boards*/ -#define FPGA_REG3_ENET_ENCODE1(n) ((((unsigned long)(n))&0x07)<<4) /*pass1*/ -#define FPGA_REG3_ENET_DECODE1(n) ((((unsigned long)(n))>>4)&0x07) /*pass1*/ -#define FPGA_REG3_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*pass2*/ -#define FPGA_REG3_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*pass2*/ -#define FPGA_REG3_STAT_MASK 0x0F -#define FPGA_REG3_STAT_LED8_ENAB 0x08 -#define FPGA_REG3_STAT_LED4_ENAB 0x04 -#define FPGA_REG3_STAT_LED2_ENAB 0x02 -#define FPGA_REG3_STAT_LED1_ENAB 0x01 -#define FPGA_REG3_STAT_LED8_DISAB 0x00 -#define FPGA_REG3_STAT_LED4_DISAB 0x00 -#define FPGA_REG3_STAT_LED2_DISAB 0x00 -#define FPGA_REG3_STAT_LED1_DISAB 0x00 -#define FPGA_REG4 (CONFIG_SYS_FPGA_BASE + 0x04) -#define FPGA_REG4_GPHY_MODE10 0x80 -#define FPGA_REG4_GPHY_MODE100 0x40 -#define FPGA_REG4_GPHY_MODE1000 0x20 -#define FPGA_REG4_GPHY_FRC_DPLX 0x10 -#define FPGA_REG4_GPHY_ANEG_DIS 0x08 -#define FPGA_REG4_CONNECT_PHYS 0x04 - - -#define SDR0_CUST0_ENET3_MASK 0x00000080 -#define SDR0_CUST0_ENET3_COPPER 0x00000000 -#define SDR0_CUST0_ENET3_FIBER 0x00000080 -#define SDR0_CUST0_RGMII3_MASK 0x00000070 -#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4) -#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07) -#define SDR0_CUST0_RGMII3_DISAB 0x00000000 -#define SDR0_CUST0_RGMII3_RTBI 0x00000040 -#define SDR0_CUST0_RGMII3_RGMII 0x00000050 -#define SDR0_CUST0_RGMII3_TBI 0x00000060 -#define SDR0_CUST0_RGMII3_GMII 0x00000070 -#define SDR0_CUST0_ENET2_MASK 0x00000008 -#define SDR0_CUST0_ENET2_COPPER 0x00000000 -#define SDR0_CUST0_ENET2_FIBER 0x00000008 -#define SDR0_CUST0_RGMII2_MASK 0x00000007 -#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) -#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07) -#define SDR0_CUST0_RGMII2_DISAB 0x00000000 -#define SDR0_CUST0_RGMII2_RTBI 0x00000004 -#define SDR0_CUST0_RGMII2_RGMII 0x00000005 -#define SDR0_CUST0_RGMII2_TBI 0x00000006 -#define SDR0_CUST0_RGMII2_GMII 0x00000007 diff --git a/qemu/roms/u-boot/board/amcc/redwood/Makefile b/qemu/roms/u-boot/board/amcc/redwood/Makefile deleted file mode 100644 index 2bc632b24..000000000 --- a/qemu/roms/u-boot/board/amcc/redwood/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2008 -# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = redwood.o -extra-y += init.o diff --git a/qemu/roms/u-boot/board/amcc/redwood/config.mk b/qemu/roms/u-boot/board/amcc/redwood/config.mk deleted file mode 100644 index 42b3e5f49..000000000 --- a/qemu/roms/u-boot/board/amcc/redwood/config.mk +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2008 -# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# AMCC 460SX Reference Platform (redwood) board -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/qemu/roms/u-boot/board/amcc/redwood/init.S b/qemu/roms/u-boot/board/amcc/redwood/init.S deleted file mode 100644 index fd0513087..000000000 --- a/qemu/roms/u-boot/board/amcc/redwood/init.S +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2008 - * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> -#include <asm/ppc4xx.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - /* Although 512 KB, map 256k at a time */ - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I) - tlbentry(CONFIG_SYS_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_RWX | SA_I) - - tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG) - - /* - * Peripheral base - */ - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_RW | SA_IG) - tlbtab_end diff --git a/qemu/roms/u-boot/board/amcc/redwood/redwood.c b/qemu/roms/u-boot/board/amcc/redwood/redwood.c deleted file mode 100644 index 15c38840d..000000000 --- a/qemu/roms/u-boot/board/amcc/redwood/redwood.c +++ /dev/null @@ -1,440 +0,0 @@ -/* - * This is the main board level file for the Redwood AMCC board. - * - * (C) Copyright 2008 - * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include "redwood.h" -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include <i2c.h> -#include <asm/io.h> - -int compare_to_true(char *str); -char *remove_l_w_space(char *in_str); -char *remove_t_w_space(char *in_str); -int get_console_port(void); - -static void early_init_EBC(void); -static int bootdevice_selected(void); -static void early_reinit_EBC(int); -static void early_init_UIC(void); - -/* - * Define Boot devices - */ -#define BOOT_FROM_8BIT_SRAM 0x00 -#define BOOT_FROM_16BIT_SRAM 0x01 -#define BOOT_FROM_32BIT_SRAM 0x02 -#define BOOT_FROM_8BIT_NAND 0x03 -#define BOOT_FROM_16BIT_NOR 0x04 -#define BOOT_DEVICE_UNKNOWN 0xff - -/* - * EBC Devices Characteristics - * Peripheral Bank Access Parameters - EBC_BxAP - * Peripheral Bank Configuration Register - EBC_BxCR - */ - -/* - * 8 bit width SRAM - * BU Value - * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 - * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000 - * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000 - */ -#define EBC_BXAP_8BIT_SRAM \ - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \ - EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \ - EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \ - EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \ - EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \ - EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \ - EBC_BXAP_PEN_DISABLED - -#define EBC_BXAP_16BIT_SRAM EBC_BXAP_8BIT_SRAM -#define EBC_BXAP_32BIT_SRAM EBC_BXAP_8BIT_SRAM - -/* - * NAND flash - * BU Value - * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 - * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000 - * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000 -*/ -#define EBC_BXAP_NAND \ - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \ - EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \ - EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \ - EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \ - EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \ - EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \ - EBC_BXAP_PEN_DISABLED - -/* - * NOR flash - * BU Value - * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 - * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000 - * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000 -*/ -#define EBC_BXAP_NOR \ - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \ - EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \ - EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \ - EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \ - EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \ - EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \ - EBC_BXAP_PEN_DISABLED - -/* - * FPGA - * BU value : - * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000 - * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000 - */ -#define EBC_BXAP_FPGA \ - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(11) | \ - EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \ - EBC_BXAP_CSN_ENCODE(10) | EBC_BXAP_OEN_ENCODE(1) | \ - EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) | \ - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_RE_DISABLED | \ - EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_RW | \ - EBC_BXAP_PEN_DISABLED - -#define EBC_BXCR_8BIT_SRAM_CS0 \ - EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_1MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT - -#define EBC_BXCR_32BIT_SRAM_CS0 \ - EBC_BXCR_BAS_ENCODE(0xFFC00000) | EBC_BXCR_BS_1MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT - -#define EBC_BXCR_NAND_CS0 \ - EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT - -#define EBC_BXCR_16BIT_SRAM_CS0 \ - EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_2MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT - -#define EBC_BXCR_NOR_CS0 \ - EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT - -#define EBC_BXCR_NOR_CS1 \ - EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT - -#define EBC_BXCR_NAND_CS1 \ - EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT - -#define EBC_BXCR_NAND_CS2 \ - EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_128MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT - -#define EBC_BXCR_SRAM_CS2 \ - EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_4MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT - -#define EBC_BXCR_LARGE_FLASH_CS2 \ - EBC_BXCR_BAS_ENCODE(0xE7000000) | EBC_BXCR_BS_16MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT - -#define EBC_BXCR_FPGA_CS3 \ - EBC_BXCR_BAS_ENCODE(0xE2000000) | EBC_BXCR_BS_1MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT - -/***************************************************************************** - * UBOOT initiated board specific function calls - ****************************************************************************/ - -int board_early_init_f(void) -{ - int computed_boot_device = BOOT_DEVICE_UNKNOWN; - - /* - * Initialise EBC - */ - early_init_EBC(); - - /* - * Determine which boot device was selected - */ - computed_boot_device = bootdevice_selected(); - - /* - * Reinit EBC based on selected boot device - */ - early_reinit_EBC(computed_boot_device); - - /* - * Setup for UIC on 460SX redwood board - */ - early_init_UIC(); - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: Redwood - AMCC 460SX Reference Board"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -static void early_init_EBC(void) -{ - /* - * Initialize EBC CONFIG - - * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC - * default value : - * 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 - */ - mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | - EBC_CFG_PTD_ENABLE | - EBC_CFG_RTC_16PERCLK | - EBC_CFG_ATC_PREVIOUS | - EBC_CFG_DTC_PREVIOUS | - EBC_CFG_CTC_PREVIOUS | - EBC_CFG_OEO_PREVIOUS | - EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_16); - - /* - * PART 1 : Initialize EBC Bank 3 - * ============================== - * Bank1 is always associated to the EPLD. - * It has to be initialized prior to other banks settings computation - * since some board registers values may be needed to determine the - * boot type - */ - mtebc(PB1AP, EBC_BXAP_FPGA); - mtebc(PB1CR, EBC_BXCR_FPGA_CS3); - -} - -static int bootdevice_selected(void) -{ - unsigned long sdr0_pinstp; - unsigned long bootstrap_settings; - int computed_boot_device = BOOT_DEVICE_UNKNOWN; - - /* - * Determine which boot device was selected - * ================================================= - * - * Read Pin Strap Register in PPC460SX - * Result can either be : - * - Boot strap = boot from EBC 8bits => Small Flash - * - Boot strap = boot from PCI - * - Boot strap = IIC - * In case of boot from IIC, read Serial Device Strap Register1 - * - * Result can either be : - * - Boot from EBC - EBC Bus Width = 8bits => Small Flash - * - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM - * - Boot from PCI - */ - - /* Read Pin Strap Register in PPC460SX */ - mfsdr(SDR0_PINSTP, sdr0_pinstp); - bootstrap_settings = sdr0_pinstp & SDR0_PSTRP0_BOOTSTRAP_MASK; - - switch (bootstrap_settings) { - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0: - /* - * Boot from SRAM, 8bit width - */ - computed_boot_device = BOOT_FROM_8BIT_SRAM; - break; - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1: - /* - * Boot from SRAM, 32bit width - */ - computed_boot_device = BOOT_FROM_32BIT_SRAM; - break; - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2: - /* - * Boot from NAND, 8bit width - */ - computed_boot_device = BOOT_FROM_8BIT_NAND; - break; - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4: - /* - * Boot from SRAM, 16bit width - * Boot setting in IIC EEPROM 0x50 - */ - computed_boot_device = BOOT_FROM_16BIT_SRAM; - break; - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS5: - /* - * Boot from NOR, 16bit width - * Boot setting in IIC EEPROM 0x54 - */ - computed_boot_device = BOOT_FROM_16BIT_NOR; - break; - default: - /* should not be */ - computed_boot_device = BOOT_DEVICE_UNKNOWN; - break; - } - - return computed_boot_device; -} - -static void early_reinit_EBC(int computed_boot_device) -{ - /* - * Compute EBC settings depending on selected boot device - * ====================================================== - * - * Resulting EBC init will be among following configurations : - * - * - Boot from EBC 8bits => boot from Small Flash selected - * EBC-CS0 = Small Flash - * EBC-CS2 = Large Flash and SRAM - * - * - Boot from EBC 16bits => boot from Large Flash or SRAM - * EBC-CS0 = Large Flash or SRAM - * EBC-CS2 = Small Flash - * - * - Boot from PCI - * EBC-CS0 = not initialized to avoid address contention - * EBC-CS2 = same as boot from Small Flash selected - */ - - unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0; - unsigned long ebc0_cs1_bxap_value = 0, ebc0_cs1_bxcr_value = 0; - unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0; - - switch (computed_boot_device) { - /*-------------------------------------------------------------------*/ - case BOOT_FROM_8BIT_SRAM: - /*-------------------------------------------------------------------*/ - ebc0_cs0_bxap_value = EBC_BXAP_8BIT_SRAM; - ebc0_cs0_bxcr_value = EBC_BXCR_8BIT_SRAM_CS0; - ebc0_cs1_bxap_value = EBC_BXAP_NOR; - ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1; - ebc0_cs2_bxap_value = EBC_BXAP_NAND; - ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2; - break; - - /*-------------------------------------------------------------------*/ - case BOOT_FROM_16BIT_SRAM: - /*-------------------------------------------------------------------*/ - ebc0_cs0_bxap_value = EBC_BXAP_16BIT_SRAM; - ebc0_cs0_bxcr_value = EBC_BXCR_16BIT_SRAM_CS0; - ebc0_cs1_bxap_value = EBC_BXAP_NOR; - ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1; - ebc0_cs2_bxap_value = EBC_BXAP_NAND; - ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2; - break; - - /*-------------------------------------------------------------------*/ - case BOOT_FROM_32BIT_SRAM: - /*-------------------------------------------------------------------*/ - ebc0_cs0_bxap_value = EBC_BXAP_32BIT_SRAM; - ebc0_cs0_bxcr_value = EBC_BXCR_32BIT_SRAM_CS0; - ebc0_cs1_bxap_value = EBC_BXAP_NOR; - ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1; - ebc0_cs2_bxap_value = EBC_BXAP_NAND; - ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2; - break; - - /*-------------------------------------------------------------------*/ - case BOOT_FROM_16BIT_NOR: - /*-------------------------------------------------------------------*/ - ebc0_cs0_bxap_value = EBC_BXAP_NOR; - ebc0_cs0_bxcr_value = EBC_BXCR_NOR_CS0; - ebc0_cs1_bxap_value = EBC_BXAP_NAND; - ebc0_cs1_bxcr_value = EBC_BXCR_NAND_CS1; - ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM; - ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2; - break; - - /*-------------------------------------------------------------------*/ - case BOOT_FROM_8BIT_NAND: - /*-------------------------------------------------------------------*/ - ebc0_cs0_bxap_value = EBC_BXAP_NAND; - ebc0_cs0_bxcr_value = EBC_BXCR_NAND_CS0; - ebc0_cs1_bxap_value = EBC_BXAP_NOR; - ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1; - ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM; - ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2; - break; - - /*-------------------------------------------------------------------*/ - default: - /*-------------------------------------------------------------------*/ - /* BOOT_DEVICE_UNKNOWN */ - break; - } - - mtebc(PB0AP, ebc0_cs0_bxap_value); - mtebc(PB0CR, ebc0_cs0_bxcr_value); - mtebc(PB1AP, ebc0_cs1_bxap_value); - mtebc(PB1CR, ebc0_cs1_bxcr_value); - mtebc(PB2AP, ebc0_cs2_bxap_value); - mtebc(PB2CR, ebc0_cs2_bxcr_value); -} - -static void early_init_UIC(void) -{ - /* - * Initialise UIC registers. Clear all interrupts. Disable all - * interrupts. - * Set critical interrupt values. Set interrupt polarities. Set - * interrupt trigger levels. Make bit 0 High priority. Clear all - * interrupts again. - */ - mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */ - mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */ - mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical - * interrupts */ - mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ - mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts */ - - mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */ - mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */ - mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical - * interrupts */ - mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities */ - mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */ - - mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */ - mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */ - mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical - * interrupts */ - mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr(UIC1TR, 0x001fc0ff); /* Set Interrupt Trigger Levels */ - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */ - - mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */ - mtdcr(UIC0ER, 0x00000000); /* disable all interrupts excepted - * cascade to be checked */ - mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical - * interrupts */ - mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr(UIC0TR, 0x000f003c); /* Set Interrupt Trigger Levels */ - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */ - -} diff --git a/qemu/roms/u-boot/board/amcc/redwood/redwood.h b/qemu/roms/u-boot/board/amcc/redwood/redwood.h deleted file mode 100644 index 9c36073c2..000000000 --- a/qemu/roms/u-boot/board/amcc/redwood/redwood.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2008 - * Feng Kan, Applied Micro Circuit Corp., fkan@amcc.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __REDWOOD_H_ -#define __REDWOOD_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/*----------------------------------------------------------------------------+ -| Defines -+----------------------------------------------------------------------------*/ -/* Pin Straps Reg */ -#define SDR0_PSTRP0 0x0040 -#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */ - -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */ - -#ifdef __cplusplus -} -#endif -#endif /* __REDWOOD_H_ */ diff --git a/qemu/roms/u-boot/board/amcc/sequoia/Makefile b/qemu/roms/u-boot/board/amcc/sequoia/Makefile deleted file mode 100644 index b4ab5daa8..000000000 --- a/qemu/roms/u-boot/board/amcc/sequoia/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = sequoia.o sdram.o -obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -extra-y += init.o diff --git a/qemu/roms/u-boot/board/amcc/sequoia/chip_config.c b/qemu/roms/u-boot/board/amcc/sequoia/chip_config.c deleted file mode 100644 index eef93165b..000000000 --- a/qemu/roms/u-boot/board/amcc/sequoia/chip_config.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx_config.h> - -struct ppc4xx_config ppc4xx_config_val[] = { - { - "333-133-nor", "NOR CPU: 333 PLB: 133 OPB: 66 EBC: 66", - { - 0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "333-166-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 55", - { - 0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "333-166-nand", "NAND CPU: 333 PLB: 166 OPB: 83 EBC: 55", - { - 0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xd0, 0x30, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66", - { - 0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "400-160-nor", "NOR CPU: 400 PLB: 160 OPB: 80 EBC: 53", - { - 0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "416-166-nor", "NOR CPU: 416 PLB: 166 OPB: 83 EBC: 55", - { - 0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "416-166-nand", "NAND CPU: 416 PLB: 166 OPB: 83 EBC: 55", - { - 0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xd0, 0x10, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "500-166-nor", "NOR CPU: 500 PLB: 166 OPB: 83 EBC: 55", - { - 0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "500-166-nand", "NAND CPU: 500 PLB: 166 OPB: 83 EBC: 55", - { - 0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xd0, 0x30, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "533-133-nor", "NOR CPU: 533 PLB: 133 OPB: 66 EBC: 66", - { - 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "667-133-nor", "NOR CPU: 667 PLB: 133 OPB: 66 EBC: 66", - { - 0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "667-166-nor", "NOR CPU: 667 PLB: 166 OPB: 83 EBC: 55", - { - 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "667-166-nand", "NAND CPU: 667 PLB: 166 OPB: 83 EBC: 55", - { - 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x30, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, -}; - -int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/qemu/roms/u-boot/board/amcc/sequoia/config.mk b/qemu/roms/u-boot/board/amcc/sequoia/config.mk deleted file mode 100644 index 824e78f75..000000000 --- a/qemu/roms/u-boot/board/amcc/sequoia/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# (C) Copyright 2002-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# AMCC 440EPx Reference Platform (Sequoia) board -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/qemu/roms/u-boot/board/amcc/sequoia/init.S b/qemu/roms/u-boot/board/amcc/sequoia/init.S deleted file mode 100644 index f876639d3..000000000 --- a/qemu/roms/u-boot/board/amcc/sequoia/init.S +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <asm/mmu.h> -#include <config.h> - -/* - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - */ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* vxWorks needs this as first entry for the Machine Check interrupt */ - tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG ) - - /* - * The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This - * entry is already configured for SDRAM via the JTAG debugger and mustn't - * be re-initialized by this RAM-booting U-Boot version. - */ -#ifndef CONFIG_SYS_RAMBOOT - /* TLB-entry for DDR SDRAM (Up to 2GB) */ -#ifdef CONFIG_4xx_DCACHE - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_G) -#else - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG ) -#endif -#endif /* CONFIG_SYS_RAMBOOT */ - - /* TLB-entry for EBC */ - tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_RWX | SA_IG ) - - /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G ) - -#ifdef CONFIG_SYS_INIT_RAM_DCACHE - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G ) -#endif - - /* TLB-entry for PCI Memory */ - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG ) - - /* TLB-entry for NAND */ - tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG ) - - /* TLB-entry for Internal Registers & OCM */ - tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I ) - - /*TLB-entry PCI registers*/ - tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG ) - - /* TLB-entry for peripherals */ - tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG) - - /* TLB-entry PCI IO Space - from sr@denx.de */ - tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG) - - tlbtab_end diff --git a/qemu/roms/u-boot/board/amcc/sequoia/sdram.c b/qemu/roms/u-boot/board/amcc/sequoia/sdram.c deleted file mode 100644 index 67640d7ed..000000000 --- a/qemu/roms/u-boot/board/amcc/sequoia/sdram.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * (C) Copyright 2006 - * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com - * - * (C) Copyright 2006-2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* define DEBUG for debug output */ -#undef DEBUG - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc440.h> - -/*-----------------------------------------------------------------------------+ - * Prototypes - *-----------------------------------------------------------------------------*/ -extern int denali_wait_for_dlllock(void); -extern void denali_core_search_data_eye(void); - -/************************************************************************* - * - * initdram -- 440EPx's DDR controller is a DENALI Core - * - ************************************************************************/ -phys_size_t initdram (int board_type) -{ -#if !defined(CONFIG_SYS_RAMBOOT) - ulong speed = get_bus_freq(0); - - mtsdram(DDR0_02, 0x00000000); - - mtsdram(DDR0_00, 0x0000190A); - mtsdram(DDR0_01, 0x01000000); - mtsdram(DDR0_03, 0x02030602); - mtsdram(DDR0_04, 0x0A020200); - mtsdram(DDR0_05, 0x02020308); - mtsdram(DDR0_06, 0x0102C812); - mtsdram(DDR0_07, 0x000D0100); - mtsdram(DDR0_08, 0x02430001); - mtsdram(DDR0_09, 0x00011D5F); - mtsdram(DDR0_10, 0x00000100); - mtsdram(DDR0_11, 0x0027C800); - mtsdram(DDR0_12, 0x00000003); - mtsdram(DDR0_14, 0x00000000); - mtsdram(DDR0_17, 0x19000000); - mtsdram(DDR0_18, 0x19191919); - mtsdram(DDR0_19, 0x19191919); - mtsdram(DDR0_20, 0x0B0B0B0B); - mtsdram(DDR0_21, 0x0B0B0B0B); - mtsdram(DDR0_22, 0x00267F0B); - mtsdram(DDR0_23, 0x00000000); - mtsdram(DDR0_24, 0x01010002); - if (speed > 133333334) - mtsdram(DDR0_26, 0x5B26050C); - else - mtsdram(DDR0_26, 0x5B260408); - mtsdram(DDR0_27, 0x0000682B); - mtsdram(DDR0_28, 0x00000000); - mtsdram(DDR0_31, 0x00000000); - mtsdram(DDR0_42, 0x01000006); - mtsdram(DDR0_43, 0x030A0200); - mtsdram(DDR0_44, 0x00000003); - mtsdram(DDR0_02, 0x00000001); - - denali_wait_for_dlllock(); -#endif /* #ifndef CONFIG_SYS_RAMBOOT */ - -#ifdef CONFIG_DDR_DATA_EYE - /* -----------------------------------------------------------+ - * Perform data eye search if requested. - * ----------------------------------------------------------*/ - denali_core_search_data_eye(); -#endif - - /* - * Clear possible errors resulting from data-eye-search. - * If not done, then we could get an interrupt later on when - * exceptions are enabled. - */ - set_mcsr(get_mcsr()); - - return (CONFIG_SYS_MBYTES_SDRAM << 20); -} diff --git a/qemu/roms/u-boot/board/amcc/sequoia/sequoia.c b/qemu/roms/u-boot/board/amcc/sequoia/sequoia.c deleted file mode 100644 index 53f9b3419..000000000 --- a/qemu/roms/u-boot/board/amcc/sequoia/sequoia.c +++ /dev/null @@ -1,412 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2006 - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <asm/ppc4xx.h> -#include <asm/ppc4xx-gpio.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/bitops.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if !defined(CONFIG_SYS_NO_FLASH) -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#endif - -extern void __ft_board_setup(void *blob, bd_t *bd); -ulong flash_get_size(ulong base, int banknum); - -static inline u32 get_async_pci_freq(void) -{ - if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & - CONFIG_SYS_BCSR5_PCI66EN) - return 66666666; - else - return 33333333; -} - -int board_early_init_f(void) -{ - u32 sdr0_cust0; - u32 sdr0_pfc1, sdr0_pfc2; - u32 reg; - - mtdcr(EBC0_CFGADDR, EBC0_CFG); - mtdcr(EBC0_CFGDATA, 0xb8400000); - - /* - * Setup the interrupt controller polarities, triggers, etc. - */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ - mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(UIC2ER, 0x00000000); /* disable all */ - mtdcr(UIC2CR, 0x00000000); /* all non-critical */ - mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - - /* Check and reconfigure the PCI sync clock if necessary */ - ppc4xx_pci_sync_clock_config(get_async_pci_freq()); - - /* 50MHz tmrclk */ - out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00); - - /* clear write protects */ - out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00); - - /* enable Ethernet */ - out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00); - - /* enable USB device */ - out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20); - - /* select Ethernet (and optionally IIC1) pins */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | - SDR0_PFC1_SELECT_CONFIG_4; -#ifdef CONFIG_I2C_MULTI_BUS - sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL); -#endif - /* Two UARTs, so we need 4-pin mode. Also, we want CTS/RTS mode. */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS; - - mfsdr(SDR0_PFC2, sdr0_pfc2); - sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | - SDR0_PFC2_SELECT_CONFIG_4; - mtsdr(SDR0_PFC2, sdr0_pfc2); - mtsdr(SDR0_PFC1, sdr0_pfc1); - - /* PCI arbiter enabled */ - mfsdr(SDR0_PCI0, reg); - mtsdr(SDR0_PCI0, 0x80000000 | reg); - - /* setup NAND FLASH */ - mfsdr(SDR0_CUST0, sdr0_cust0); - sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | - SDR0_CUST0_NDFC_ENABLE | - SDR0_CUST0_NDFC_BW_8_BIT | - SDR0_CUST0_NDFC_ARE_MASK | - (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); - mtsdr(SDR0_CUST0, sdr0_cust0); - - return 0; -} - -int misc_init_r(void) -{ -#if !defined(CONFIG_SYS_NO_FLASH) - uint pbcr; - int size_val = 0; -#endif -#ifdef CONFIG_440EPX - unsigned long usb2d0cr = 0; - unsigned long usb2phy0cr, usb2h0cr = 0; - unsigned long sdr0_pfc1; - char *act = getenv("usbact"); -#endif - u32 reg; - -#if !defined(CONFIG_SYS_NO_FLASH) - /* Re-do flash sizing to get full correct info */ - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - -#if defined(CONFIG_SYS_RAMBOOT) - mtdcr(EBC0_CFGADDR, PB3CR); -#else - mtdcr(EBC0_CFGADDR, PB0CR); -#endif - pbcr = mfdcr(EBC0_CFGDATA); - size_val = ffs(gd->bd->bi_flashsize) - 21; - pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); -#if defined(CONFIG_SYS_RAMBOOT) - mtdcr(EBC0_CFGADDR, PB3CR); -#else - mtdcr(EBC0_CFGADDR, PB0CR); -#endif - mtdcr(EBC0_CFGDATA, pbcr); - - /* - * Re-check to get correct base address - */ - flash_get_size(gd->bd->bi_flashstart, 0); - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - - /* Env protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif -#endif /* CONFIG_SYS_NO_FLASH */ - - /* - * USB suff... - */ -#ifdef CONFIG_440EPX - if (act == NULL || strcmp(act, "hostdev") == 0) { - /* SDR Setting */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - mfsdr(SDR0_USB2D0CR, usb2d0cr); - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mfsdr(SDR0_USB2H0CR, usb2h0cr); - - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; - - /* - * An 8-bit/60MHz interface is the only possible alternative - * when connecting the Device to the PHY - */ - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; - - /* - * To enable the USB 2.0 Device function - * through the UTMI interface - */ - usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; - usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; - - sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; - sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; - - mtsdr(SDR0_PFC1, sdr0_pfc1); - mtsdr(SDR0_USB2D0CR, usb2d0cr); - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mtsdr(SDR0_USB2H0CR, usb2h0cr); - - /*clear resets*/ - udelay (1000); - mtsdr(SDR0_SRST1, 0x00000000); - udelay (1000); - mtsdr(SDR0_SRST0, 0x00000000); - - printf("USB: Host(int phy) Device(ext phy)\n"); - - } else if (strcmp(act, "dev") == 0) { - /*-------------------PATCH-------------------------------*/ - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - - udelay (1000); - mtsdr(SDR0_SRST1, 0x672c6000); - - udelay (1000); - mtsdr(SDR0_SRST0, 0x00000080); - - udelay (1000); - mtsdr(SDR0_SRST1, 0x60206000); - - *(unsigned int *)(0xe0000350) = 0x00000001; - - udelay (1000); - mtsdr(SDR0_SRST1, 0x60306000); - /*-------------------PATCH-------------------------------*/ - - /* SDR Setting */ - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mfsdr(SDR0_USB2H0CR, usb2h0cr); - mfsdr(SDR0_USB2D0CR, usb2d0cr); - mfsdr(SDR0_PFC1, sdr0_pfc1); - - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; - - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; - - usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; - usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; - - sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; - sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; - - mtsdr(SDR0_USB2H0CR, usb2h0cr); - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mtsdr(SDR0_USB2D0CR, usb2d0cr); - mtsdr(SDR0_PFC1, sdr0_pfc1); - - /* clear resets */ - udelay (1000); - mtsdr(SDR0_SRST1, 0x00000000); - udelay (1000); - mtsdr(SDR0_SRST0, 0x00000000); - - printf("USB: Device(int phy)\n"); - } -#endif /* CONFIG_440EPX */ - - mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */ - reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0); - mtsdr(SDR0_SRST1, reg); - - /* - * Clear PLB4A0_ACR[WRP] - * This fix will make the MAL burst disabling patch for the Linux - * EMAC driver obsolete. - */ - reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; - mtdcr(PLB4A0_ACR, reg); - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - u8 rev; - u32 clock = get_async_pci_freq(); - -#ifdef CONFIG_440EPX - printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board"); -#else - printf("Board: Rainier - AMCC PPC440GRx Evaluation Board"); -#endif - - rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)); - printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - /* - * Reconfiguration of the PCI sync clock is already done, - * now check again if everything is in range: - */ - if (ppc4xx_pci_sync_clock_config(clock)) { - printf("ERROR: PCI clocking incorrect (async=%d " - "sync=%ld)!\n", clock, get_PCI_freq()); - } - - return (0); -} - -#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) -/* - * Assign interrupts to PCI devices. - */ -void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2); -} -#endif - -#if defined(CONFIG_SYS_RAMBOOT) -/* - * On NAND-booting sequoia, we need to patch the chips select numbers - * in the dtb (CS0 - NAND, CS3 - NOR) - */ -void ft_board_setup(void *blob, bd_t *bd) -{ - int rc; - int len; - int nodeoffset; - struct fdt_property *prop; - u32 *reg; - char path[32]; - - /* First do common fdt setup */ - __ft_board_setup(blob, bd); - - /* And now configure NOR chip select to 3 instead of 0 */ - strcpy(path, "/plb/opb/ebc/nor_flash@0,0"); - nodeoffset = fdt_path_offset(blob, path); - prop = fdt_get_property_w(blob, nodeoffset, "reg", &len); - if (prop == NULL) { - printf("Unable to update NOR chip select for NAND booting\n"); - return; - } - reg = (u32 *)&prop->data[0]; - reg[0] = 3; - rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1); - if (rc) { - printf("Unable to update property NOR mappings, err=%s\n", - fdt_strerror(rc)); - return; - } - - /* And now configure NAND chip select to 0 instead of 3 */ - strcpy(path, "/plb/opb/ebc/ndfc@3,0"); - nodeoffset = fdt_path_offset(blob, path); - prop = fdt_get_property_w(blob, nodeoffset, "reg", &len); - if (prop == NULL) { - printf("Unable to update NDFC chip select for NAND booting\n"); - return; - } - reg = (u32 *)&prop->data[0]; - reg[0] = 0; - rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1); - if (rc) { - printf("Unable to update property NDFC mappings, err=%s\n", - fdt_strerror(rc)); - return; - } -} -#endif /* CONFIG_SYS_RAMBOOT */ diff --git a/qemu/roms/u-boot/board/amcc/sequoia/u-boot-ram.lds b/qemu/roms/u-boot/board/amcc/sequoia/u-boot-ram.lds deleted file mode 100644 index ef08be8d5..000000000 --- a/qemu/roms/u-boot/board/amcc/sequoia/u-boot-ram.lds +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/ppc4xx/start.o (.text*) - board/amcc/sequoia/init.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - KEEP(*(.got)) - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/qemu/roms/u-boot/board/amcc/taihu/Makefile b/qemu/roms/u-boot/board/amcc/taihu/Makefile deleted file mode 100644 index 65606fe08..000000000 --- a/qemu/roms/u-boot/board/amcc/taihu/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = taihu.o flash.o lcd.o update.o diff --git a/qemu/roms/u-boot/board/amcc/taihu/flash.c b/qemu/roms/u-boot/board/amcc/taihu/flash.c deleted file mode 100644 index 078048888..000000000 --- a/qemu/roms/u-boot/board/amcc/taihu/flash.c +++ /dev/null @@ -1,1063 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -#define CONFIG_SYS_FLASH_CHAR_SIZE unsigned char -#define CONFIG_SYS_FLASH_CHAR_ADDR0 (0x0aaa) -#define CONFIG_SYS_FLASH_CHAR_ADDR1 (0x0555) -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static void flash_get_offsets(ulong base, flash_info_t * info); -static int write_word(flash_info_t * info, ulong dest, ulong data); -#ifdef FLASH_BASE1_PRELIM -static int write_word_1(flash_info_t * info, ulong dest, ulong data); -static int write_word_2(flash_info_t * info, ulong dest, ulong data); -static int flash_erase_1(flash_info_t * info, int s_first, int s_last); -static int flash_erase_2(flash_info_t * info, int s_first, int s_last); -static ulong flash_get_size_1(vu_long * addr, flash_info_t * info); -static ulong flash_get_size_2(vu_long * addr, flash_info_t * info); -#endif - -unsigned long flash_init(void) -{ - unsigned long size_b0, size_b1=0; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = - flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - if (size_b0) { - /* Setup offsets */ - flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]); - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[0]); -#ifdef CONFIG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - /* Also protect sector containing initial power-up instruction */ - /* (flash_protect() checks address range - other call ignored) */ - (void)flash_protect(FLAG_PROTECT_SET, - 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]); - - flash_info[0].size = size_b0; - } -#ifdef FLASH_BASE1_PRELIM - size_b1 = - flash_get_size((vu_long *) FLASH_BASE1_PRELIM, &flash_info[1])*2; - - if (flash_info[1].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", - size_b1, size_b1 << 20); - } - - if (size_b1) { - /* Setup offsets */ - flash_get_offsets(FLASH_BASE1_PRELIM, &flash_info[1]); - flash_info[1].size = size_b1; - } -#endif - return (size_b0 + size_b1); -} - -static void flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000*2); - } - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000*2); - } - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } -} - - -void flash_print_info(flash_info_t * info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_STM: - printf("STM "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_SST: - printf("SST "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AMD016: - printf("AM29F016D (16 Mbit, uniform sector size)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AM033C: - printf("AM29LV033C (32 Mbit, top boot sector)\n"); - break; - case FLASH_AMLV128U: - printf("AM29LV128U (128 Mbit * 2, top boot sector)\n"); - break; - case FLASH_SST800A: - printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: - printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - case FLASH_STMW320DT: - printf ("M29W320DT (32 M, top sector)\n"); - break; - case FLASH_S29GL128N: - printf ("S29GL128N (256 Mbit, uniform sector size)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s%s", - info->start[i], - erased ? " E" : " ", info->protect[i] ? "RO " : " "); - } - printf("\n"); - return; -} - - -/* - * The following code cannot be run from FLASH! - */ -#ifdef FLASH_BASE1_PRELIM -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - if ((ulong)addr == FLASH_BASE1_PRELIM) { - return flash_get_size_2(addr, info); - } else { - return flash_get_size_1(addr, info); - } -} - -static ulong flash_get_size_1(vu_long * addr, flash_info_t * info) -#else -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -#endif -{ - short i; - CONFIG_SYS_FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); - - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; - udelay(1000); - - value = addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return 0; /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D: - info->flash_id += FLASH_AMD016; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C: - info->flash_id += FLASH_AMDLV033C; - info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return 0; /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } - else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000 * 2); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - - /* For AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if (i == 32) { - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; - - return info->size; -} - -static int wait_for_DQ7_1(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = - (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -#ifdef FLASH_BASE1_PRELIM -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { - return flash_erase_2(info, s_first, s_last); - } else { - return flash_erase_1(info, s_first, s_last); - } -} - -static int flash_erase_1(flash_info_t * info, int s_first, int s_last) -#else -int flash_erase(flash_info_t * info, int s_first, int s_last) -#endif -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_1(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return rc; - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return rc; - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return 0; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -#ifdef FLASH_BASE1_PRELIM -static int write_word(flash_info_t * info, ulong dest, ulong data) -{ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { - return write_word_2(info, dest, data); - } else { - return write_word_1(info, dest, data); - } -} - -static int write_word_1(flash_info_t * info, ulong dest, ulong data) -#else -static int write_word(flash_info_t * info, ulong dest, ulong data) -#endif -{ - ulong *data_ptr = &data; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return 2; - } - - for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return 1; - } - } - } - - return 0; -} - -#ifdef FLASH_BASE1_PRELIM - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) -{ - short i; - CONFIG_SYS_FLASH_CHAR_SIZE value; - ulong base = (ulong) addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); - - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; - udelay(1000); - - value = (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CONFIG_SYS_FLASH_CHAR_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CONFIG_SYS_FLASH_CHAR_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CONFIG_SYS_FLASH_CHAR_SIZE) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return 0; /* no or unknown flash */ - } - - value = (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[2]; /* device ID */ - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_CHAR_SIZE) STM_ID_M29W040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_F016D: - info->flash_id += FLASH_AMD016; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV033C: - info->flash_id += FLASH_AMDLV033C; - info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_MIRROR: - if ((CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1c] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_LV128U_2 - && (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1e] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_LV128U_3) { - info->flash_id += FLASH_AMLV128U; - info->sector_count = 256; - info->size = 0x01000000; - } else if ((CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1c] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_GL128N_2 - && (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1e] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_GL128N_3 ) { - info->flash_id += FLASH_S29GL128N; - info->sector_count = 128; - info->size = 0x01000000; - } - else - info->flash_id = FLASH_UNKNOWN; - break; /* => 2 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return 0; /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00020000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - - /* For AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if (i == 32) { - addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[4] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF0F0F0F0; - return info->size; -} - -static int wait_for_DQ7_2(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = - (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while (((CONFIG_SYS_FLASH_WORD_SIZE)addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080) != - (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -static int flash_erase_2(flash_info_t * info, int s_first, int s_last) -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080; - addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x50505050; /* block erase */ - for (i = 0; i < 50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080; - addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30303030; /* sector erase */ - } - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_2(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF0F0F0F0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -static int write_word_2(flash_info_t * info, ulong dest, ulong data) -{ - ulong *data_ptr = &data; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return 2; - } - - for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xA0A0A0A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080) != - (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080)) { - - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return 1; - } - } - } - - return 0; -} - -#endif /* FLASH_BASE1_PRELIM */ diff --git a/qemu/roms/u-boot/board/amcc/taihu/lcd.c b/qemu/roms/u-boot/board/amcc/taihu/lcd.c deleted file mode 100644 index c7c7fa443..000000000 --- a/qemu/roms/u-boot/board/amcc/taihu/lcd.c +++ /dev/null @@ -1,237 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <common.h> -#include <command.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> - -#define LCD_CMD_ADDR 0x50100002 -#define LCD_DATA_ADDR 0x50100003 -#define LCD_BLK_CTRL CPLD_REG1_ADDR - -static char *amcc_logo = "AMCC 405EP TAIHU EVALUATION KIT"; -static int addr_flag = 0x80; - -static void lcd_bl_ctrl(char val) -{ - out_8((u8 *) LCD_BLK_CTRL, in_8((u8 *) LCD_BLK_CTRL) | val); -} - -static void lcd_putc(int val) -{ - int i = 100; - char addr; - - while (i--) { - if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/ - udelay(50); - break; - } - udelay(50); - } - - if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) { - printf("LCD is busy\n"); - return; - } - - addr = in_8((u8 *) LCD_CMD_ADDR); - udelay(50); - if ((addr != 0) && (addr % 0x10 == 0)) { - addr_flag ^= 0x40; - out_8((u8 *) LCD_CMD_ADDR, addr_flag); - } - - udelay(50); - out_8((u8 *) LCD_DATA_ADDR, val); - udelay(50); -} - -static void lcd_puts(char *s) -{ - char *p = s; - int i = 100; - - while (i--) { - if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/ - udelay(50); - break; - } - udelay(50); - } - - if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) { - printf("LCD is busy\n"); - return; - } - - while (*p) - lcd_putc(*p++); -} - -static void lcd_put_logo(void) -{ - int i = 100; - char *p = amcc_logo; - - while (i--) { - if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/ - udelay(50); - break; - } - udelay(50); - } - - if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) { - printf("LCD is busy\n"); - return; - } - - out_8((u8 *) LCD_CMD_ADDR, 0x80); - while (*p) - lcd_putc(*p++); -} - -int lcd_init(void) -{ - puts("LCD: "); - out_8((u8 *) LCD_CMD_ADDR, 0x38); /* set function:8-bit,2-line,5x7 font type */ - udelay(50); - out_8((u8 *) LCD_CMD_ADDR, 0x0f); /* set display on,cursor on,blink on */ - udelay(50); - out_8((u8 *) LCD_CMD_ADDR, 0x01); /* display clear */ - udelay(2000); - out_8((u8 *) LCD_CMD_ADDR, 0x06); /* set entry */ - udelay(50); - lcd_bl_ctrl(0x02); /* set backlight on */ - lcd_put_logo(); - puts("ready\n"); - - return 0; -} - -static int do_lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - out_8((u8 *) LCD_CMD_ADDR, 0x01); - udelay(2000); - - return 0; -} - -static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc < 2) - return cmd_usage(cmdtp); - - lcd_puts(argv[1]); - - return 0; -} - -static int do_lcd_putc (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc < 2) - return cmd_usage(cmdtp); - - lcd_putc((char)argv[1][0]); - - return 0; -} - -static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - ulong count; - ulong dir; - char cur_addr; - - if (argc < 3) - return cmd_usage(cmdtp); - - count = simple_strtoul(argv[1], NULL, 16); - if (count > 31) { - printf("unable to shift > 0x20\n"); - count = 0; - } - - dir = simple_strtoul(argv[2], NULL, 16); - cur_addr = in_8((u8 *) LCD_CMD_ADDR); - udelay(50); - - if (dir == 0x0) { - if (addr_flag == 0x80) { - if (count >= (cur_addr & 0xf)) { - out_8((u8 *) LCD_CMD_ADDR, 0x80); - udelay(50); - count = 0; - } - } else { - if (count >= ((cur_addr & 0x0f) + 0x0f)) { - out_8((u8 *) LCD_CMD_ADDR, 0x80); - addr_flag = 0x80; - udelay(50); - count = 0x0; - } else if (count >= ( cur_addr & 0xf)) { - count -= cur_addr & 0xf ; - out_8((u8 *) LCD_CMD_ADDR, 0x80 | 0xf); - addr_flag = 0x80; - udelay(50); - } - } - } else { - if (addr_flag == 0x80) { - if (count >= (0x1f - (cur_addr & 0xf))) { - count = 0x0; - addr_flag = 0xc0; - out_8((u8 *) LCD_CMD_ADDR, 0xc0 | 0xf); - udelay(50); - } else if ((count + (cur_addr & 0xf ))>= 0x0f) { - count = count + (cur_addr & 0xf) - 0x0f; - addr_flag = 0xc0; - out_8((u8 *) LCD_CMD_ADDR, 0xc0); - udelay(50); - } - } else if ((count + (cur_addr & 0xf )) >= 0x0f) { - count = 0x0; - out_8((u8 *) LCD_CMD_ADDR, 0xC0 | 0x0F); - udelay(50); - } - } - while (count--) { - if (dir == 0) - out_8((u8 *) LCD_CMD_ADDR, 0x10); - else - out_8((u8 *) LCD_CMD_ADDR, 0x14); - udelay(50); - } - - return 0; -} - -U_BOOT_CMD( - lcd_cls, 1, 1, do_lcd_clear, - "lcd clear display", - "" -); - -U_BOOT_CMD( - lcd_puts, 2, 1, do_lcd_puts, - "display string on lcd", - "<string> - <string> to be displayed" -); - -U_BOOT_CMD( - lcd_putc, 2, 1, do_lcd_putc, - "display char on lcd", - "<char> - <char> to be displayed" -); - -U_BOOT_CMD( - lcd_cur, 3, 1, do_lcd_cur, - "shift cursor on lcd", - "<count> <dir> - shift cursor on lcd <count> times, direction is <dir> \n" - " <count> - 0..31\n" - " <dir> - 0=backward 1=forward" -); diff --git a/qemu/roms/u-boot/board/amcc/taihu/taihu.c b/qemu/roms/u-boot/board/amcc/taihu/taihu.c deleted file mode 100644 index fcb893633..000000000 --- a/qemu/roms/u-boot/board/amcc/taihu/taihu.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2005-2007 - * Beijing UD Technology Co., Ltd., taihusupport@amcc.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <spi.h> -#include <netdev.h> -#include <asm/ppc4xx-gpio.h> - -extern int lcd_init(void); - -/* - * board_early_init_f - */ -int board_early_init_f(void) -{ - lcd_init(); - - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); - mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */ - mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - - mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */ - mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR); - - /* - * Configure CPC0_PCI to enable PerWE as output - * and enable the internal PCI arbiter - */ - mtdcr(CPC0_PCI, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: Taihu - AMCC PPC405EP Evaluation Board"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char * const argv[]) -{ - char stat; - int i; - - stat = in_8((u8 *) CPLD_REG0_ADDR); - printf("SW2 status: "); - for (i=0; i<4; i++) /* 4-position */ - printf("%d:%s ", i, stat & (0x08 >> i)?"on":"off"); - printf("\n"); - return 0; -} - -U_BOOT_CMD ( - sw2_stat, 1, 1, do_sw_stat, - "show status of switch 2", - "" -); - -static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char * const argv[]) -{ - int led_no; - - if (argc != 3) - return cmd_usage(cmd_tp); - - led_no = simple_strtoul(argv[1], NULL, 16); - if (led_no != 1 && led_no != 2) - return cmd_usage(cmd_tp); - - if (strcmp(argv[2],"off") == 0x0) { - if (led_no == 1) - gpio_write_bit(30, 1); - else - gpio_write_bit(31, 1); - } else if (strcmp(argv[2],"on") == 0x0) { - if (led_no == 1) - gpio_write_bit(30, 0); - else - gpio_write_bit(31, 0); - } else { - return cmd_usage(cmd_tp); - } - - return 0; -} - -U_BOOT_CMD ( - led_ctl, 3, 1, do_led_ctl, - "make led 1 or 2 on or off", - "<led_no> <on/off> - make led <led_no> on/off,\n" - "\tled_no is 1 or 2" -); - -#define SPI_CS_GPIO0 0 -#define SPI_SCLK_GPIO14 14 -#define SPI_DIN_GPIO15 15 -#define SPI_DOUT_GPIO16 16 - -void spi_scl(int bit) -{ - gpio_write_bit(SPI_SCLK_GPIO14, bit); -} - -void spi_sda(int bit) -{ - gpio_write_bit(SPI_DOUT_GPIO16, bit); -} - -unsigned char spi_read(void) -{ - return (unsigned char)gpio_read_in_bit(SPI_DIN_GPIO15); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - gpio_write_bit(SPI_CS_GPIO0, 1); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - gpio_write_bit(SPI_CS_GPIO0, 0); -} - -#ifdef CONFIG_PCI -static unsigned char int_lines[32] = { - 29, 30, 27, 28, 29, 30, 25, 27, - 29, 30, 27, 28, 29, 30, 27, 28, - 29, 30, 27, 28, 29, 30, 27, 28, - 29, 30, 27, 28, 29, 30, 27, 28}; - -static void taihu_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char int_line = int_lines[PCI_DEV(dev) & 31]; - - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); -} - -int pci_pre_init(struct pci_controller *hose) -{ - hose->fixup_irq = taihu_pci_fixup_irq; - return 1; -} -#endif /* CONFIG_PCI */ - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); - return pci_eth_init(bis); -} diff --git a/qemu/roms/u-boot/board/amcc/taihu/update.c b/qemu/roms/u-boot/board/amcc/taihu/update.c deleted file mode 100644 index ace217d70..000000000 --- a/qemu/roms/u-boot/board/amcc/taihu/update.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <i2c.h> - -#define PCI_M66EN 0x10 - -static uchar buf_33[] = -{ - 0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/ - 0x80, /* 0x01~0x03:ptm1ms =0x80000001 */ - 0x00, - 0x00, - 0x00, /* 0x04~0x06:ptm1la = 0x00000000 */ - 0x00, - 0x00, - 0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */ - 0x00, - 0x00, - 0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */ - 0x00, - 0x00, - 0x10, /* 0x0d~0x0e:vendor id 0x1014*/ - 0x14, - 0x00, /* 0x0f~0x10:device id 0x0000*/ - 0x00, - 0x00, /* 0x11:revision 0x00 */ - 0x00, /* 0x12~0x14:class 0x000000 */ - 0x00, - 0x00, - 0x10, /* 0x15~0x16:subsystem vendor id */ - 0xe8, - 0x00, /* 0x17~0x18:subsystem device id */ - 0x00, - 0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */ - 0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */ - 0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */ - 0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */ - 0xbe, /* 0x1d: tun[24-31]=0xbe */ - 0x00, - 0x00 -}; - -static uchar buf_66[] = -{ - 0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/ - 0x80, /* 0x01~0x03:ptm1ms =0x80000001 */ - 0x00, - 0x00, - 0x00, /* 0x04~0x06:ptm1la = 0x00000000 */ - 0x00, - 0x00, - 0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */ - 0x00, - 0x00, - 0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */ - 0x00, - 0x00, - 0x10, /* 0x0d~0x0e:vendor id 0x1014*/ - 0x14, - 0x00, /* 0x0f~0x10:device id 0x0000*/ - 0x00, - 0x00, /* 0x11:revision 0x00 */ - 0x00, /* 0x12~0x14:class 0x000000 */ - 0x00, - 0x00, - 0x10, /* 0x15~0x16:subsystem vendor id */ - 0xe8, - 0x00, /* 0x17~0x18:subsystem device id */ - 0x00, - 0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */ - 0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */ - 0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */ - 0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */ - 0xbe, /* 0x1d: tun[24-31]=0xbe */ - 0x00, - 0x00 -}; - -static int update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char * const argv[]) -{ - ulong len = 0x20; - uchar chip = CONFIG_SYS_I2C_EEPROM_ADDR; - uchar *pbuf; - uchar base; - int i; - - if ((*(volatile char*)CPLD_REG0_ADDR & PCI_M66EN) != PCI_M66EN) { - pbuf = buf_33; - base = 0x00; - } else { - pbuf = buf_66; - base = 0x40; - } - - for (i = 0; i< len; i++, base++) { - if (i2c_write(chip, base, 1, &pbuf[i],1)!= 0) { - printf("i2c_write fail\n"); - return 1; - } - udelay(11000); - } - - return 0; -} - -U_BOOT_CMD ( - update_boot_eeprom, 1, 1, update_boot_eeprom, - "update boot eeprom content", - "" -); diff --git a/qemu/roms/u-boot/board/amcc/taishan/Makefile b/qemu/roms/u-boot/board/amcc/taishan/Makefile deleted file mode 100644 index 04e93cc0d..000000000 --- a/qemu/roms/u-boot/board/amcc/taishan/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = taishan.o lcd.o update.o showinfo.o -extra-y += init.o diff --git a/qemu/roms/u-boot/board/amcc/taishan/config.mk b/qemu/roms/u-boot/board/amcc/taishan/config.mk deleted file mode 100644 index 6de8b591b..000000000 --- a/qemu/roms/u-boot/board/amcc/taishan/config.mk +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# AMCC 440GX Reference Platform (Taishan) board -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/qemu/roms/u-boot/board/amcc/taishan/init.S b/qemu/roms/u-boot/board/amcc/taishan/init.S deleted file mode 100644 index ab1bb34fb..000000000 --- a/qemu/roms/u-boot/board/amcc/taishan/init.S +++ /dev/null @@ -1,35 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <ppc_asm.tmpl> -#include <asm/mmu.h> -#include <config.h> -#include <asm/ppc4xx.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) - tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX ) - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG ) - tlbtab_end diff --git a/qemu/roms/u-boot/board/amcc/taishan/lcd.c b/qemu/roms/u-boot/board/amcc/taishan/lcd.c deleted file mode 100644 index 124b81ee0..000000000 --- a/qemu/roms/u-boot/board/amcc/taishan/lcd.c +++ /dev/null @@ -1,358 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <common.h> -#include <command.h> -#include <i2c.h> -#include <miiphy.h> - -#ifdef CONFIG_TAISHAN - -#define LCD_DELAY_NORMAL_US 100 -#define LCD_DELAY_NORMAL_MS 2 -#define LCD_CMD_ADDR ((volatile char *)(CONFIG_SYS_EBC2_LCM_BASE)) -#define LCD_DATA_ADDR ((volatile char *)(CONFIG_SYS_EBC2_LCM_BASE+1)) -#define LCD_BLK_CTRL ((volatile char *)(CONFIG_SYS_EBC1_FPGA_BASE+0x2)) - -static int g_lcd_init_b = 0; -static char *amcc_logo = " AMCC TAISHAN 440GX EvalBoard"; -static char addr_flag = 0x80; - -static void lcd_bl_ctrl(char val) -{ - char cpld_val; - - cpld_val = *LCD_BLK_CTRL; - *LCD_BLK_CTRL = val | cpld_val; -} - -static void lcd_putc(char val) -{ - int i = 100; - char addr; - - while (i--) { - if ((*LCD_CMD_ADDR & 0x80) != 0x80) { /*BF = 1 ? */ - udelay(LCD_DELAY_NORMAL_US); - break; - } - udelay(LCD_DELAY_NORMAL_US); - } - - if (*LCD_CMD_ADDR & 0x80) { - printf("LCD is busy\n"); - return; - } - - addr = *LCD_CMD_ADDR; - udelay(LCD_DELAY_NORMAL_US); - if ((addr != 0) && (addr % 0x10 == 0)) { - addr_flag ^= 0x40; - *LCD_CMD_ADDR = addr_flag; - } - - udelay(LCD_DELAY_NORMAL_US); - *LCD_DATA_ADDR = val; - udelay(LCD_DELAY_NORMAL_US); -} - -static void lcd_puts(char *s) -{ - char *p = s; - int i = 100; - - while (i--) { - if ((*LCD_CMD_ADDR & 0x80) != 0x80) { /*BF = 1 ? */ - udelay(LCD_DELAY_NORMAL_US); - break; - } - udelay(LCD_DELAY_NORMAL_US); - } - - if (*LCD_CMD_ADDR & 0x80) { - printf("LCD is busy\n"); - return; - } - - while (*p) - lcd_putc(*p++); -} - -static void lcd_put_logo(void) -{ - int i = 100; - char *p = amcc_logo; - - while (i--) { - if ((*LCD_CMD_ADDR & 0x80) != 0x80) { /*BF = 1 ? */ - udelay(LCD_DELAY_NORMAL_US); - break; - } - udelay(LCD_DELAY_NORMAL_US); - } - - if (*LCD_CMD_ADDR & 0x80) { - printf("LCD is busy\n"); - return; - } - - *LCD_CMD_ADDR = 0x80; - while (*p) - lcd_putc(*p++); -} - -int lcd_init(void) -{ - if (g_lcd_init_b == 0) { - puts("LCD: "); - mdelay(100); /* Waiting for the LCD initialize */ - - *LCD_CMD_ADDR = 0x38; /*set function:8-bit,2-line,5x7 font type */ - udelay(LCD_DELAY_NORMAL_US); - - *LCD_CMD_ADDR = 0x0f; /*set display on,cursor on,blink on */ - udelay(LCD_DELAY_NORMAL_US); - - *LCD_CMD_ADDR = 0x01; /*display clear */ - mdelay(LCD_DELAY_NORMAL_MS); - - *LCD_CMD_ADDR = 0x06; /*set entry */ - udelay(LCD_DELAY_NORMAL_US); - - lcd_bl_ctrl(0x02); - lcd_put_logo(); - - puts(" ready\n"); - g_lcd_init_b = 1; - } - - return 0; -} - -static int do_lcd_test(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - lcd_init(); - return 0; -} - -static int do_lcd_clear(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - *LCD_CMD_ADDR = 0x01; - mdelay(LCD_DELAY_NORMAL_MS); - return 0; -} -static int do_lcd_puts(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc < 2) - return cmd_usage(cmdtp); - - lcd_puts(argv[1]); - return 0; -} -static int do_lcd_putc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc < 2) - return cmd_usage(cmdtp); - - lcd_putc((char)argv[1][0]); - return 0; -} -static int do_lcd_cur(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - ulong count; - ulong dir; - char cur_addr; - - if (argc < 3) - return cmd_usage(cmdtp); - - count = simple_strtoul(argv[1], NULL, 16); - if (count > 31) { - printf("unable to shift > 0x20\n"); - count = 0; - } - - dir = simple_strtoul(argv[2], NULL, 16); - cur_addr = *LCD_CMD_ADDR; - udelay(LCD_DELAY_NORMAL_US); - if (dir == 0x0) { - if (addr_flag == 0x80) { - if (count >= (cur_addr & 0xf)) { - *LCD_CMD_ADDR = 0x80; - udelay(LCD_DELAY_NORMAL_US); - count = 0; - } - } else { - if (count >= ((cur_addr & 0x0f) + 0x0f)) { - *LCD_CMD_ADDR = 0x80; - addr_flag = 0x80; - udelay(LCD_DELAY_NORMAL_US); - count = 0x0; - } else if (count >= (cur_addr & 0xf)) { - count -= cur_addr & 0xf; - *LCD_CMD_ADDR = 0x80 | 0xf; - addr_flag = 0x80; - udelay(LCD_DELAY_NORMAL_US); - } - } - } else { - if (addr_flag == 0x80) { - if (count >= (0x1f - (cur_addr & 0xf))) { - count = 0x0; - addr_flag = 0xc0; - *LCD_CMD_ADDR = 0xc0 | 0xf; - udelay(LCD_DELAY_NORMAL_US); - } else if ((count + (cur_addr & 0xf)) >= 0x0f) { - count = count + (cur_addr & 0xf) - 0x0f; - addr_flag = 0xc0; - *LCD_CMD_ADDR = 0xc0; - udelay(LCD_DELAY_NORMAL_US); - } - } else if ((count + (cur_addr & 0xf)) >= 0x0f) { - count = 0x0; - *LCD_CMD_ADDR = 0xc0 | 0xf; - udelay(LCD_DELAY_NORMAL_US); - } - } - - while (count--) { - if (dir == 0) { - *LCD_CMD_ADDR = 0x10; - } else { - *LCD_CMD_ADDR = 0x14; - } - udelay(LCD_DELAY_NORMAL_US); - } - - return 0; -} - -U_BOOT_CMD(lcd_test, 1, 1, do_lcd_test, "lcd test display", ""); -U_BOOT_CMD(lcd_cls, 1, 1, do_lcd_clear, "lcd clear display", ""); -U_BOOT_CMD(lcd_puts, 2, 1, do_lcd_puts, - "display string on lcd", - "<string> - <string> to be displayed"); -U_BOOT_CMD(lcd_putc, 2, 1, do_lcd_putc, - "display char on lcd", - "<char> - <char> to be displayed"); -U_BOOT_CMD(lcd_cur, 3, 1, do_lcd_cur, - "shift cursor on lcd", - "<count> <dir>- shift cursor on lcd <count> times, direction is <dir> \n" - " <count> - 0~31\n" " <dir> - 0,backward; 1, forward"); - -#if 0 /* test-only */ -void set_phy_loopback_mode(void) -{ - char devemac2[32]; - char devemac3[32]; - - sprintf(devemac2, "%s2", CONFIG_EMAC_DEV_NAME); - sprintf(devemac3, "%s3", CONFIG_EMAC_DEV_NAME); - -#if 0 - unsigned short reg_short; - - miiphy_read(devemac2, 0x1, 1, ®_short); - if (reg_short & 0x04) { - /* - * printf("EMAC2 link up,do nothing\n"); - */ - } else { - udelay(1000); - miiphy_write(devemac2, 0x1, 0, 0x6000); - udelay(1000); - miiphy_read(devemac2, 0x1, 0, ®_short); - if (reg_short != 0x6000) { - printf - ("\nEMAC2 error set LOOPBACK mode error,reg2[0]=%x\n", - reg_short); - } - } - - miiphy_read(devemac3, 0x3, 1, ®_short); - if (reg_short & 0x04) { - /* - * printf("EMAC3 link up,do nothing\n"); - */ - } else { - udelay(1000); - miiphy_write(devemac3, 0x3, 0, 0x6000); - udelay(1000); - miiphy_read(devemac3, 0x3, 0, ®_short); - if (reg_short != 0x6000) { - printf - ("\nEMAC3 error set LOOPBACK mode error,reg2[0]=%x\n", - reg_short); - } - } -#else - /* Set PHY as LOOPBACK MODE, for Linux emac initializing */ - miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0, 0x6000); - udelay(1000); - miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0, 0x6000); - udelay(1000); -#endif /* 0 */ -} - -void set_phy_normal_mode(void) -{ - char devemac2[32]; - char devemac3[32]; - unsigned short reg_short; - - sprintf(devemac2, "%s2", CONFIG_EMAC_DEV_NAME); - sprintf(devemac3, "%s3", CONFIG_EMAC_DEV_NAME); - - /* Set phy of EMAC2 */ - miiphy_read(devemac2, CONFIG_PHY2_ADDR, 0x16, ®_short); - reg_short &= ~(0x7); - reg_short |= 0x6; /* RGMII DLL Delay */ - miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x16, reg_short); - - miiphy_read(devemac2, CONFIG_PHY2_ADDR, 0x17, ®_short); - reg_short &= ~(0x40); - miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x17, reg_short); - - miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x1c, 0x74f0); - - /* Set phy of EMAC3 */ - miiphy_read(devemac3, CONFIG_PHY3_ADDR, 0x16, ®_short); - reg_short &= ~(0x7); - reg_short |= 0x6; /* RGMII DLL Delay */ - miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x16, reg_short); - - miiphy_read(devemac3, CONFIG_PHY3_ADDR, 0x17, ®_short); - reg_short &= ~(0x40); - miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x17, reg_short); - - miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x1c, 0x74f0); -} -#endif /* 0 - test only */ - -static int do_led_test_off(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - volatile unsigned int *GpioOr = - (volatile unsigned int *)(CONFIG_SYS_PERIPHERAL_BASE + 0x700); - *GpioOr |= 0x00300000; - return 0; -} - -static int do_led_test_on(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - volatile unsigned int *GpioOr = - (volatile unsigned int *)(CONFIG_SYS_PERIPHERAL_BASE + 0x700); - *GpioOr &= ~0x00300000; - return 0; -} - -U_BOOT_CMD(ledon, 1, 1, do_led_test_on, - "led test light on", ""); - -U_BOOT_CMD(ledoff, 1, 1, do_led_test_off, - "led test light off", ""); -#endif diff --git a/qemu/roms/u-boot/board/amcc/taishan/showinfo.c b/qemu/roms/u-boot/board/amcc/taishan/showinfo.c deleted file mode 100644 index 53bfdf790..000000000 --- a/qemu/roms/u-boot/board/amcc/taishan/showinfo.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <pci.h> - -void show_reset_reg(void) -{ - unsigned long reg; - - /* read clock regsiter */ - printf("===== Display reset and initialize register Start =========\n"); - mfcpr(CPR0_PLLC,reg); - printf("cpr_pllc = %#010lx\n",reg); - - mfcpr(CPR0_PLLD,reg); - printf("cpr_plld = %#010lx\n",reg); - - mfcpr(CPR0_PRIMAD0,reg); - printf("cpr_primad = %#010lx\n",reg); - - mfcpr(CPR0_PRIMBD0,reg); - printf("cpr_primbd = %#010lx\n",reg); - - mfcpr(CPR0_OPBD0,reg); - printf("cpr_opbd = %#010lx\n",reg); - - mfcpr(CPR0_PERD,reg); - printf("cpr_perd = %#010lx\n",reg); - - mfcpr(CPR0_MALD,reg); - printf("cpr_mald = %#010lx\n",reg); - - /* read sdr register */ - mfsdr(SDR0_EBC,reg); - printf("SDR0_EBC = %#010lx\n",reg); - - mfsdr(SDR0_CP440,reg); - printf("SDR0_CP440 = %#010lx\n",reg); - - mfsdr(SDR0_XCR,reg); - printf("SDR0_XCR = %#010lx\n",reg); - - mfsdr(SDR0_XPLLC,reg); - printf("SDR0_XPLLC = %#010lx\n",reg); - - mfsdr(SDR0_XPLLD,reg); - printf("SDR0_XPLLD = %#010lx\n",reg); - - mfsdr(SDR0_PFC0,reg); - printf("SDR0_PFC0 = %#010lx\n",reg); - - mfsdr(SDR0_PFC1,reg); - printf("SDR0_PFC1 = %#010lx\n",reg); - - mfsdr(SDR0_CUST0,reg); - printf("SDR0_CUST0 = %#010lx\n",reg); - - mfsdr(SDR0_CUST1,reg); - printf("SDR0_CUST1 = %#010lx\n",reg); - - mfsdr(SDR0_UART0,reg); - printf("SDR0_UART0 = %#010lx\n",reg); - - mfsdr(SDR0_UART1,reg); - printf("SDR0_UART1 = %#010lx\n",reg); - - printf("===== Display reset and initialize register End =========\n"); -} - -void show_xbridge_info(void) -{ - unsigned long reg; - - printf("PCI-X chip control registers\n"); - mfsdr(SDR0_XCR, reg); - printf("SDR0_XCR = %#010lx\n", reg); - - mfsdr(SDR0_XPLLC, reg); - printf("SDR0_XPLLC = %#010lx\n", reg); - - mfsdr(SDR0_XPLLD, reg); - printf("SDR0_XPLLD = %#010lx\n", reg); - - printf("PCI-X Bridge Configure registers\n"); - printf("PCIL0_VENDID = %#06x\n", in16r(PCIL0_VENDID)); - printf("PCIL0_DEVID = %#06x\n", in16r(PCIL0_DEVID)); - printf("PCIL0_CMD = %#06x\n", in16r(PCIL0_CMD)); - printf("PCIL0_STATUS = %#06x\n", in16r(PCIL0_STATUS)); - printf("PCIL0_REVID = %#04x\n", in8(PCIL0_REVID)); - printf("PCIL0_CACHELS = %#04x\n", in8(PCIL0_CACHELS)); - printf("PCIL0_LATTIM = %#04x\n", in8(PCIL0_LATTIM)); - printf("PCIL0_HDTYPE = %#04x\n", in8(PCIL0_HDTYPE)); - printf("PCIL0_BIST = %#04x\n", in8(PCIL0_BIST)); - - printf("PCIL0_BAR0 = %#010lx\n", in32r(PCIL0_BAR0)); - printf("PCIL0_BAR1 = %#010lx\n", in32r(PCIL0_BAR1)); - printf("PCIL0_BAR2 = %#010lx\n", in32r(PCIL0_BAR2)); - printf("PCIL0_BAR3 = %#010lx\n", in32r(PCIL0_BAR3)); - printf("PCIL0_BAR4 = %#010lx\n", in32r(PCIL0_BAR4)); - printf("PCIL0_BAR5 = %#010lx\n", in32r(PCIL0_BAR5)); - - printf("PCIL0_CISPTR = %#010lx\n", in32r(PCIL0_CISPTR)); - printf("PCIL0_SBSSYSVID = %#010x\n", in16r(PCIL0_SBSYSVID)); - printf("PCIL0_SBSSYSID = %#010x\n", in16r(PCIL0_SBSYSID)); - printf("PCIL0_EROMBA = %#010lx\n", in32r(PCIL0_EROMBA)); - printf("PCIL0_CAP = %#04x\n", in8(PCIL0_CAP)); - printf("PCIL0_INTLN = %#04x\n", in8(PCIL0_INTLN)); - printf("PCIL0_INTPN = %#04x\n", in8(PCIL0_INTPN)); - printf("PCIL0_MINGNT = %#04x\n", in8(PCIL0_MINGNT)); - printf("PCIL0_MAXLTNCY = %#04x\n", in8(PCIL0_MAXLTNCY)); - - printf("PCIL0_BRDGOPT1 = %#010lx\n", in32r(PCIL0_BRDGOPT1)); - printf("PCIL0_BRDGOPT2 = %#010lx\n", in32r(PCIL0_BRDGOPT2)); - - printf("PCIL0_POM0LAL = %#010lx\n", in32r(PCIL0_POM0LAL)); - printf("PCIL0_POM0LAH = %#010lx\n", in32r(PCIL0_POM0LAH)); - printf("PCIL0_POM0SA = %#010lx\n", in32r(PCIL0_POM0SA)); - printf("PCIL0_POM0PCILAL = %#010lx\n", in32r(PCIL0_POM0PCIAL)); - printf("PCIL0_POM0PCILAH = %#010lx\n", in32r(PCIL0_POM0PCIAH)); - printf("PCIL0_POM1LAL = %#010lx\n", in32r(PCIL0_POM1LAL)); - printf("PCIL0_POM1LAH = %#010lx\n", in32r(PCIL0_POM1LAH)); - printf("PCIL0_POM1SA = %#010lx\n", in32r(PCIL0_POM1SA)); - printf("PCIL0_POM1PCILAL = %#010lx\n", in32r(PCIL0_POM1PCIAL)); - printf("PCIL0_POM1PCILAH = %#010lx\n", in32r(PCIL0_POM1PCIAH)); - printf("PCIL0_POM2SA = %#010lx\n", in32r(PCIL0_POM2SA)); - - printf("PCIL0_PIM0SA = %#010lx\n", in32r(PCIL0_PIM0SA)); - printf("PCIL0_PIM0LAL = %#010lx\n", in32r(PCIL0_PIM0LAL)); - printf("PCIL0_PIM0LAH = %#010lx\n", in32r(PCIL0_PIM0LAH)); - printf("PCIL0_PIM1SA = %#010lx\n", in32r(PCIL0_PIM1SA)); - printf("PCIL0_PIM1LAL = %#010lx\n", in32r(PCIL0_PIM1LAL)); - printf("PCIL0_PIM1LAH = %#010lx\n", in32r(PCIL0_PIM1LAH)); - printf("PCIL0_PIM2SA = %#010lx\n", in32r(PCIL0_PIM1SA)); - printf("PCIL0_PIM2LAL = %#010lx\n", in32r(PCIL0_PIM1LAL)); - printf("PCIL0_PIM2LAH = %#010lx\n", in32r(PCIL0_PIM1LAH)); - - printf("PCIL0_XSTS = %#010lx\n", in32r(PCIL0_STS)); -} - -int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - show_xbridge_info(); - return 0; -} - -U_BOOT_CMD(xbriinfo, 1, 1, do_show_xbridge_info, - "Show PCIX bridge info", ""); - -#define TAISHAN_PCI_DEV_ID0 0x800 -#define TAISHAN_PCI_DEV_ID1 0x1000 - -void show_pcix_device_info(void) -{ - int ii; - int dev; - u8 capp; - u8 xcapid; - u16 status; - u16 xcommand; - u32 xstatus; - - for (ii = 0; ii < 2; ii++) { - if (ii == 0) - dev = TAISHAN_PCI_DEV_ID0; - else - dev = TAISHAN_PCI_DEV_ID1; - - pci_read_config_word(dev, PCI_STATUS, &status); - if (status & PCI_STATUS_CAP_LIST) { - pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &capp); - - pci_read_config_byte(dev, (int)(capp), &xcapid); - if (xcapid == 0x07) { - pci_read_config_word(dev, (int)(capp + 2), - &xcommand); - pci_read_config_dword(dev, (int)(capp + 4), - &xstatus); - printf("BUS0 dev%d Xcommand=%#06x,Xstatus=%#010x\n", - (ii + 1), xcommand, xstatus); - } else { - printf("BUS0 dev%d PCI-X CAP ID error," - "CAP=%#04x,XCAPID=%#04x\n", - (ii + 1), capp, xcapid); - } - } else { - printf("BUS0 dev%d not found PCI_STATUS_CAP_LIST supporting\n", - ii + 1); - } - } - -} - -int do_show_pcix_device_info(cmd_tbl_t * cmdtp, int flag, int argc, - char * const argv[]) -{ - show_pcix_device_info(); - return 0; -} - -U_BOOT_CMD(xdevinfo, 1, 1, do_show_pcix_device_info, - "Show PCIX Device info", ""); - -extern void show_reset_reg(void); - -int do_show_reset_reg_info(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - show_reset_reg(); - return 0; -} - -U_BOOT_CMD(resetinfo, 1, 1, do_show_reset_reg_info, - "Show Reset REG info", ""); diff --git a/qemu/roms/u-boot/board/amcc/taishan/taishan.c b/qemu/roms/u-boot/board/amcc/taishan/taishan.c deleted file mode 100644 index 5c8d9ec8f..000000000 --- a/qemu/roms/u-boot/board/amcc/taishan/taishan.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright (C) 2004 PaulReynolds@lhsolutions.com - * - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <spd_sdram.h> -#include <asm/ppc4xx-emac.h> -#include <netdev.h> - -#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG -void show_reset_reg(void); -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int lcd_init(void); - -int board_early_init_f (void) -{ - unsigned long reg; - volatile unsigned int *GpioOdr; - volatile unsigned int *GpioTcr; - volatile unsigned int *GpioOr; - - /*-------------------------------------------------------------------------+ - | Initialize EBC CONFIG - +-------------------------------------------------------------------------*/ - mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | - EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | - EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | - EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT | - EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); - - /*-------------------------------------------------------------------------+ - | 64MB FLASH. Initialize bank 0 with default values. - +-------------------------------------------------------------------------*/ - mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) | - EBC_BXAP_BCE_DISABLE | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) | - EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) | - EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED | - EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | - EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT); - - /*-------------------------------------------------------------------------+ - | FPGA. Initialize bank 1 with default values. - +-------------------------------------------------------------------------*/ - mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) | - EBC_BXAP_BCE_DISABLE | - EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) | - EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) | - EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED | - EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x41000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); - - /*-------------------------------------------------------------------------+ - | LCM. Initialize bank 2 with default values. - +-------------------------------------------------------------------------*/ - mtebc(PB2AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) | - EBC_BXAP_BCE_DISABLE | - EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) | - EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) | - EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED | - EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0x42000000) | - EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); - - /*-------------------------------------------------------------------------+ - | TMP. Initialize bank 3 with default values. - +-------------------------------------------------------------------------*/ - mtebc(PB3AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) | - EBC_BXAP_BCE_DISABLE | - EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) | - EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) | - EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED | - EBC_BXAP_BEM_WRITEONLY | - EBC_BXAP_PEN_DISABLED); - mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48000000) | - EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); - - /*-------------------------------------------------------------------------+ - | Connector 4~7. Initialize bank 3~ 7 with default values. - +-------------------------------------------------------------------------*/ - mtebc(PB4AP,0); - mtebc(PB4CR,0); - mtebc(PB5AP,0); - mtebc(PB5CR,0); - mtebc(PB6AP,0); - mtebc(PB6CR,0); - mtebc(PB7AP,0); - mtebc(PB7CR,0); - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - /* - * Because of the interrupt handling rework to handle 440GX interrupts - * with the common code, we needed to change names of the UIC registers. - * Here the new relationship: - * - * U-Boot name 440GX name - * ----------------------- - * UIC0 UICB0 - * UIC1 UIC0 - * UIC2 UIC1 - * UIC3 UIC2 - */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - mtdcr (UIC1ER, 0x00000000); /* disable all */ - mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */ - mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */ - mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC1SR, 0xffffffff); /* clear all */ - - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - mtdcr (UIC2ER, 0x00000000); /* disable all */ - mtdcr (UIC2CR, 0x00000000); /* all non-critical */ - mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */ - mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */ - mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC2SR, 0xffffffff); /* clear all */ - - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - mtdcr (UIC3ER, 0x00000000); /* disable all */ - mtdcr (UIC3CR, 0x00000000); /* all non-critical */ - mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */ - mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */ - mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (UIC3SR, 0xffffffff); /* clear all */ - - mtdcr (UIC0SR, 0xfc000000); /* clear all */ - mtdcr (UIC0ER, 0x00000000); /* disable all */ - mtdcr (UIC0CR, 0x00000000); /* all non-critical */ - mtdcr (UIC0PR, 0xfc000000); /* */ - mtdcr (UIC0TR, 0x00000000); /* */ - mtdcr (UIC0VR, 0x00000001); /* */ - - /* Enable two GPIO 10~11 and TraceA signal */ - mfsdr(SDR0_PFC0,reg); - reg |= 0x00300000; - mtsdr(SDR0_PFC0,reg); - - mfsdr(SDR0_PFC1,reg); - reg |= 0x00100000; - mtsdr(SDR0_PFC1,reg); - - /* Set GPIO 10 and 11 as output */ - GpioOdr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x718); - GpioTcr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x704); - GpioOr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x700); - - *GpioOdr &= ~(0x00300000); - *GpioTcr |= 0x00300000; - *GpioOr |= 0x00300000; - - return 0; -} - -int misc_init_r(void) -{ - lcd_init(); - - return 0; -} - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf ("Board: Taishan - AMCC PPC440GX Evaluation Board"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc ('\n'); - -#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG - show_reset_reg(); -#endif - - return (0); -} - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); - return pci_eth_init(bis); -} diff --git a/qemu/roms/u-boot/board/amcc/taishan/update.c b/qemu/roms/u-boot/board/amcc/taishan/update.c deleted file mode 100644 index 273898929..000000000 --- a/qemu/roms/u-boot/board/amcc/taishan/update.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <i2c.h> - -#if defined(CONFIG_TAISHAN) - -const uchar bootstrap_buf[16] = { - 0x86, - 0x78, - 0xc1, - 0xa6, - 0x09, - 0x67, - 0x04, - 0x63, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00 -}; - -static int update_boot_eeprom(void) -{ - ulong len = 0x10; - uchar chip = CONFIG_SYS_BOOTSTRAP_IIC_ADDR; - uchar *pbuf = (uchar *)bootstrap_buf; - int ii, jj; - - for (ii = 0; ii < len; ii++) { - if (i2c_write(chip, ii, 1, &pbuf[ii], 1) != 0) { - printf("i2c_write failed\n"); - return -1; - } - - /* wait 10ms */ - for (jj = 0; jj < 10; jj++) - udelay(1000); - } - return 0; -} - -int do_update_boot_eeprom(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - return update_boot_eeprom(); -} - -U_BOOT_CMD(update_boot_eeprom, 1, 1, do_update_boot_eeprom, - "update bootstrap eeprom content", ""); -#endif diff --git a/qemu/roms/u-boot/board/amcc/walnut/Makefile b/qemu/roms/u-boot/board/amcc/walnut/Makefile deleted file mode 100644 index 922817076..000000000 --- a/qemu/roms/u-boot/board/amcc/walnut/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = walnut.o flash.o diff --git a/qemu/roms/u-boot/board/amcc/walnut/flash.c b/qemu/roms/u-boot/board/amcc/walnut/flash.c deleted file mode 100644 index cc0f4254a..000000000 --- a/qemu/roms/u-boot/board/amcc/walnut/flash.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -/* - * include common flash code (for amcc boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static void flash_get_offsets(ulong base, flash_info_t * info); - -unsigned long flash_init(void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = - flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - /* Only one bank */ - if (CONFIG_SYS_MAX_FLASH_BANKS == 1) { - /* Setup offsets */ - flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]); - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[0]); -#ifdef CONFIG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - size_b1 = 0; - flash_info[0].size = size_b0; - } else { - /* 2 banks */ - size_b1 = - flash_get_size((vu_long *) FLASH_BASE1_PRELIM, - &flash_info[1]); - - /* Re-do sizing to get full correct info */ - - if (size_b1) { - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB0CR); - base_b1 = -size_b1; - pbcr = - (pbcr & 0x0001ffff) | base_b1 | - (((size_b1 / 1024 / 1024) - 1) << 17); - mtdcr(EBC0_CFGDATA, pbcr); - /* printf("PB1CR = %x\n", pbcr); */ - } - - if (size_b0) { - mtdcr(EBC0_CFGADDR, PB1CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB1CR); - base_b0 = base_b1 - size_b0; - pbcr = - (pbcr & 0x0001ffff) | base_b0 | - (((size_b0 / 1024 / 1024) - 1) << 17); - mtdcr(EBC0_CFGDATA, pbcr); - /* printf("PB0CR = %x\n", pbcr); */ - } - - size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]); - - flash_get_offsets(base_b0, &flash_info[0]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = - flash_get_size((vu_long *) base_b1, &flash_info[1]); - - flash_get_offsets(base_b1, &flash_info[1]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - base_b1 + size_b1 - - monitor_flash_len, - base_b1 + size_b1 - 1, - &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - (void)flash_protect(FLAG_PROTECT_CLEAR, - base_b0 + size_b0 - - monitor_flash_len, - base_b0 + size_b0 - 1, - &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - } /* else 2 banks */ - return (size_b0 + size_b1); -} - - -static void flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } -} diff --git a/qemu/roms/u-boot/board/amcc/walnut/walnut.c b/qemu/roms/u-boot/board/amcc/walnut/walnut.c deleted file mode 100644 index c9482094f..000000000 --- a/qemu/roms/u-boot/board/amcc/walnut/walnut.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <spd_sdram.h> - -int board_early_init_f(void) -{ - /*-------------------------------------------------------------------------+ - | Interrupt controller setup for the Walnut/Sycamore board. - | Note: IRQ 0-15 405GP internally generated; active high; level sensitive - | IRQ 16 405GP internally generated; active low; level sensitive - | IRQ 17-24 RESERVED - | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive - | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive - | IRQ 27 (EXT IRQ 2) Not Used - | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive - | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive - | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive - | Note for Walnut board: - | An interrupt taken for the FPGA (IRQ 25) indicates that either - | the Mouse, Keyboard, IRDA, or External Expansion caused the - | interrupt. The FPGA must be read to determine which device - | caused the interrupt. The default setting of the FPGA clears - | - +-------------------------------------------------------------------------*/ - - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */ - mtdcr(UIC0PR, 0xFFFFFFE0); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* set UART1 control to select CTS/RTS */ -#define FPGA_BRDC 0xF0300004 - *(volatile char *)(FPGA_BRDC) |= 0x1; - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - uint pvr = get_pvr(); - - if (pvr == PVR_405GPR_RB) { - puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board"); - } else { - puts("Board: Walnut - AMCC PPC405GP Evaluation Board"); - } - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} - -/* - * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of - * the necessary info for SDRAM controller configuration - */ -phys_size_t initdram(int board_type) -{ - return spd_sdram(); -} diff --git a/qemu/roms/u-boot/board/amcc/yosemite/Makefile b/qemu/roms/u-boot/board/amcc/yosemite/Makefile deleted file mode 100644 index daf020a5a..000000000 --- a/qemu/roms/u-boot/board/amcc/yosemite/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = yosemite.o -extra-y += init.o diff --git a/qemu/roms/u-boot/board/amcc/yosemite/config.mk b/qemu/roms/u-boot/board/amcc/yosemite/config.mk deleted file mode 100644 index f18b09710..000000000 --- a/qemu/roms/u-boot/board/amcc/yosemite/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/qemu/roms/u-boot/board/amcc/yosemite/init.S b/qemu/roms/u-boot/board/amcc/yosemite/init.S deleted file mode 100644 index 529cc65f7..000000000 --- a/qemu/roms/u-boot/board/amcc/yosemite/init.S +++ /dev/null @@ -1,49 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <asm/mmu.h> -#include <config.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/) - - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G ) - - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I ) - - /* PCI */ - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG ) - - /* USB 2.0 Device */ - tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG ) - - tlbtab_end diff --git a/qemu/roms/u-boot/board/amcc/yosemite/yosemite.c b/qemu/roms/u-boot/board/amcc/yosemite/yosemite.c deleted file mode 100644 index 56b5191d6..000000000 --- a/qemu/roms/u-boot/board/amcc/yosemite/yosemite.c +++ /dev/null @@ -1,357 +0,0 @@ -/* - * (C) Copyright 2006-2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <spd_sdram.h> -#include <libfdt.h> -#include <fdt_support.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -static inline u32 get_async_pci_freq(void) -{ - if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & - CONFIG_SYS_BCSR5_PCI66EN) - return 66666666; - else - return 33333333; -} - -int board_early_init_f(void) -{ - register uint reg; - - /*-------------------------------------------------------------------- - * Setup the external bus controller/chip selects - *-------------------------------------------------------------------*/ - mtdcr(EBC0_CFGADDR, EBC0_CFG); - reg = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */ - - /*-------------------------------------------------------------------- - * Setup the GPIO pins - *-------------------------------------------------------------------*/ - /*CPLD cs */ - /*setup Address lines for flash size 64Meg. */ - out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000); - out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000); - out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000); - - /*setup emac */ - out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080); - out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40); - out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55); - out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000); - out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000); - - /*UART1 */ - out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000); - out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000); - out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000); - - /* external interrupts IRQ0...3 */ - out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000); - out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00); - out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500); - -#ifdef CONFIG_440EP - /*setup USB 2.0 */ - out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000); - out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000); - out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf); - out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa); - out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500); -#endif - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ - mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - /*-------------------------------------------------------------------- - * Setup other serial configuration - *-------------------------------------------------------------------*/ - mfsdr(SDR0_PCI0, reg); - mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */ - mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */ - mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */ - - /* Check and reconfigure the PCI sync clock if necessary */ - ppc4xx_pci_sync_clock_config(get_async_pci_freq()); - - /*clear tmrclk divisor */ - *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00; - - /*enable ethernet */ - *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x08) = 0xf0; - -#ifdef CONFIG_440EP - /*enable usb 1.1 fs device and remove usb 2.0 reset */ - *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x09) = 0x00; -#endif - - /*get rid of flash write protect */ - *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x07) = 0x00; - - return 0; -} - -int misc_init_r (void) -{ - uint pbcr; - int size_val = 0; - - /* Re-do sizing to get full correct info */ - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - switch (gd->bd->bi_flashsize) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - case 32 << 20: - size_val = 5; - break; - case 64 << 20: - size_val = 6; - break; - case 128 << 20: - size_val = 7; - break; - } - pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(EBC0_CFGADDR, PB0CR); - mtdcr(EBC0_CFGDATA, pbcr); - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - u8 rev; - u32 clock = get_async_pci_freq(); - -#ifdef CONFIG_440EP - printf("Board: Yosemite - AMCC PPC440EP Evaluation Board"); -#else - printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board"); -#endif - - rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)); - printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - /* - * Reconfiguration of the PCI sync clock is already done, - * now check again if everything is in range: - */ - if (ppc4xx_pci_sync_clock_config(clock)) { - printf("ERROR: PCI clocking incorrect (async=%d " - "sync=%ld)!\n", clock, get_PCI_freq()); - } - - return (0); -} - -/************************************************************************* - * initdram -- doesn't use serial presence detect. - * - * Assumes: 256 MB, ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -#define NUM_TRIES 64 -#define NUM_READS 10 - -void sdram_tr1_set(int ram_address, int* tr1_value) -{ - int i; - int j, k; - volatile unsigned int* ram_pointer = (unsigned int*)ram_address; - int first_good = -1, last_bad = 0x1ff; - - unsigned long test[NUM_TRIES] = { - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 }; - - /* go through all possible SDRAM0_TR1[RDCT] values */ - for (i=0; i<=0x1ff; i++) { - /* set the current value for TR1 */ - mtsdram(SDRAM0_TR1, (0x80800800 | i)); - - /* write values */ - for (j=0; j<NUM_TRIES; j++) { - ram_pointer[j] = test[j]; - - /* clear any cache at ram location */ - __asm__("dcbf 0,%0": :"r" (&ram_pointer[j])); - } - - /* read values back */ - for (j=0; j<NUM_TRIES; j++) { - for (k=0; k<NUM_READS; k++) { - /* clear any cache at ram location */ - __asm__("dcbf 0,%0": :"r" (&ram_pointer[j])); - - if (ram_pointer[j] != test[j]) - break; - } - - /* read error */ - if (k != NUM_READS) { - break; - } - } - - /* we have a SDRAM0_TR1[RDCT] that is part of the window */ - if (j == NUM_TRIES) { - if (first_good == -1) - first_good = i; /* found beginning of window */ - } else { /* bad read */ - /* if we have not had a good read then don't care */ - if(first_good != -1) { - /* first failure after a good read */ - last_bad = i-1; - break; - } - } - } - - /* return the current value for TR1 */ - *tr1_value = (first_good + last_bad) / 2; -} - -phys_size_t initdram(int board) -{ - register uint reg; - int tr1_bank1, tr1_bank2; - - /*-------------------------------------------------------------------- - * Setup some default - *------------------------------------------------------------------*/ - mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ - mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram(SDRAM0_CLKTR, 0x40000000); /* ?? */ - mtsdram(SDRAM0_WDDCTR, 0x40000000); /* ?? */ - - /*clear this first, if the DDR is enabled by a debugger - then you can not make changes. */ - mtsdram(SDRAM0_CFG0, 0x00000000); /* Disable EEC */ - - /*-------------------------------------------------------------------- - * Setup for board-specific specific mem - *------------------------------------------------------------------*/ - /* - * Following for CAS Latency = 2.5 @ 133 MHz PLB - */ - mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram(SDRAM0_B1CR, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */ - - mtsdram(SDRAM0_TR0, 0x410a4012); /* ?? */ - mtsdram(SDRAM0_RTR, 0x04080000); /* ?? */ - mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ - mtsdram(SDRAM0_CFG0, 0x30000000); /* Disable EEC */ - udelay(400); /* Delay 200 usecs (min) */ - - /*-------------------------------------------------------------------- - * Enable the controller, then wait for DCEN to complete - *------------------------------------------------------------------*/ - mtsdram(SDRAM0_CFG0, 0x80000000); /* Enable */ - - for (;;) { - mfsdram(SDRAM0_MCSTS, reg); - if (reg & 0x80000000) - break; - } - - sdram_tr1_set(0x00000000, &tr1_bank1); - sdram_tr1_set(0x08000000, &tr1_bank2); - mtsdram(SDRAM0_TR1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800)); - - return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024); /* return bytes */ -} - -/************************************************************************* - * hw_watchdog_reset - * - * This routine is called to reset (keep alive) the watchdog timer - * - ************************************************************************/ -#if defined(CONFIG_HW_WATCHDOG) -void hw_watchdog_reset(void) -{ - -} -#endif - -void board_reset(void) -{ - /* give reset to BCSR */ - *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x06) = 0x09; -} diff --git a/qemu/roms/u-boot/board/amcc/yucca/Makefile b/qemu/roms/u-boot/board/amcc/yucca/Makefile deleted file mode 100644 index 5b1af3290..000000000 --- a/qemu/roms/u-boot/board/amcc/yucca/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = yucca.o flash.o cmd_yucca.o -extra-y += init.o diff --git a/qemu/roms/u-boot/board/amcc/yucca/cmd_yucca.c b/qemu/roms/u-boot/board/amcc/yucca/cmd_yucca.c deleted file mode 100644 index dc78b7373..000000000 --- a/qemu/roms/u-boot/board/amcc/yucca/cmd_yucca.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - * - * hacked for evb440spe - */ - -#include <common.h> -#include <command.h> -#include "yucca.h" -#include <i2c.h> -#include <asm/byteorder.h> - -extern void print_evb440spe_info(void); -static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, - int flag, int argc, char * const argv[]); - -/* ------------------------------------------------------------------------- */ -int do_evb440spe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - return setBootStrapClock (cmdtp, 1, flag, argc, argv); -} - -/* ------------------------------------------------------------------------- */ -/* Modify memory. - * - * Syntax: - * evb440spe wrclk prom0,prom1 - */ -static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, - int argc, char * const argv[]) -{ - uchar chip; - ulong data; - int nbytes; - - char sysClock[4]; - char cpuClock[4]; - char plbClock[4]; - char pcixClock[4]; - - if (argc < 3) - return cmd_usage(cmdtp); - - if (strcmp(argv[2], "prom0") == 0) - chip = IIC0_BOOTPROM_ADDR; - else - chip = IIC0_ALT_BOOTPROM_ADDR; - - do { - printf("enter sys clock frequency 33 or 66 MHz or quit to abort\n"); - nbytes = readline (" ? "); - - if (strcmp(console_buffer, "quit") == 0) - return 0; - - if ((strcmp(console_buffer, "33") != 0) & - (strcmp(console_buffer, "66") != 0)) - nbytes=0; - - strcpy(sysClock, console_buffer); - - } while (nbytes == 0); - - do { - if (strcmp(sysClock, "66") == 0) { - printf("enter cpu clock frequency 400, 533 MHz or quit to abort\n"); - } else { -#ifdef CONFIG_STRESS - printf("enter cpu clock frequency 400, 500, 533, 667 MHz or quit to abort\n"); -#else - printf("enter cpu clock frequency 400, 500, 533 MHz or quit to abort\n"); -#endif - } - nbytes = readline (" ? "); - - if (strcmp(console_buffer, "quit") == 0) - return 0; - - if (strcmp(sysClock, "66") == 0) { - if ((strcmp(console_buffer, "400") != 0) & - (strcmp(console_buffer, "533") != 0) -#ifdef CONFIG_STRESS - & (strcmp(console_buffer, "667") != 0) -#endif - ) { - nbytes = 0; - } - } else { - if ((strcmp(console_buffer, "400") != 0) & - (strcmp(console_buffer, "500") != 0) & - (strcmp(console_buffer, "533") != 0) -#ifdef CONFIG_STRESS - & (strcmp(console_buffer, "667") != 0) -#endif - ) { - nbytes = 0; - } - } - - strcpy(cpuClock, console_buffer); - - } while (nbytes == 0); - - if (strcmp(cpuClock, "500") == 0){ - strcpy(plbClock, "166"); - } else if (strcmp(cpuClock, "533") == 0){ - strcpy(plbClock, "133"); - } else { - do { - if (strcmp(cpuClock, "400") == 0) - printf("enter plb clock frequency 100, 133 MHz or quit to abort\n"); - -#ifdef CONFIG_STRESS - if (strcmp(cpuClock, "667") == 0) - printf("enter plb clock frequency 133, 166 MHz or quit to abort\n"); - -#endif - nbytes = readline (" ? "); - - if (strcmp(console_buffer, "quit") == 0) - return 0; - - if (strcmp(cpuClock, "400") == 0) { - if ((strcmp(console_buffer, "100") != 0) & - (strcmp(console_buffer, "133") != 0)) - nbytes = 0; - } -#ifdef CONFIG_STRESS - if (strcmp(cpuClock, "667") == 0) { - if ((strcmp(console_buffer, "133") != 0) & - (strcmp(console_buffer, "166") != 0)) - nbytes = 0; - } -#endif - strcpy(plbClock, console_buffer); - - } while (nbytes == 0); - } - - do { - printf("enter Pci-X clock frequency 33, 66, 100 or 133 MHz or quit to abort\n"); - nbytes = readline (" ? "); - - if (strcmp(console_buffer, "quit") == 0) - return 0; - - if ((strcmp(console_buffer, "33") != 0) & - (strcmp(console_buffer, "66") != 0) & - (strcmp(console_buffer, "100") != 0) & - (strcmp(console_buffer, "133") != 0)) { - nbytes = 0; - } - strcpy(pcixClock, console_buffer); - - } while (nbytes == 0); - - printf("\nsys clk = %s MHz\n", sysClock); - printf("cpu clk = %s MHz\n", cpuClock); - printf("plb clk = %s MHz\n", plbClock); - printf("Pci-X clk = %s MHz\n", pcixClock); - - do { - printf("\npress [y] to write I2C bootstrap \n"); - printf("or [n] to abort. \n"); - printf("Don't forget to set board switches \n"); - printf("according to your choice before re-starting \n"); - printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n"); - - nbytes = readline (" ? "); - if (strcmp(console_buffer, "n") == 0) - return 0; - - } while (nbytes == 0); - - if (strcmp(sysClock, "33") == 0) { - if ((strcmp(cpuClock, "400") == 0) & - (strcmp(plbClock, "100") == 0)) - data = 0x8678c206; - - if ((strcmp(cpuClock, "400") == 0) & - (strcmp(plbClock, "133") == 0)) - data = 0x8678c2c6; - - if ((strcmp(cpuClock, "500") == 0)) - data = 0x8778f2c6; - - if ((strcmp(cpuClock, "533") == 0)) - data = 0x87790252; - -#ifdef CONFIG_STRESS - if ((strcmp(cpuClock, "667") == 0) & - (strcmp(plbClock, "133") == 0)) - data = 0x87794256; - - if ((strcmp(cpuClock, "667") == 0) & - (strcmp(plbClock, "166") == 0)) - data = 0x87794206; - -#endif - } - if (strcmp(sysClock, "66") == 0) { - if ((strcmp(cpuClock, "400") == 0) & - (strcmp(plbClock, "100") == 0)) - data = 0x84706206; - - if ((strcmp(cpuClock, "400") == 0) & - (strcmp(plbClock, "133") == 0)) - data = 0x847062c6; - - if ((strcmp(cpuClock, "533") == 0)) - data = 0x85708206; - -#ifdef CONFIG_STRESS - if ((strcmp(cpuClock, "667") == 0) & - (strcmp(plbClock, "133") == 0)) - data = 0x8570a256; - - if ((strcmp(cpuClock, "667") == 0) & - (strcmp(plbClock, "166") == 0)) - data = 0x8570a206; - -#endif - } - -#ifdef DEBUG - printf(" pin strap0 to write in i2c = %x\n", data); -#endif /* DEBUG */ - - if (i2c_write(chip, 0, 1, (uchar *)&data, 4) != 0) - printf("Error writing strap0 in %s\n", argv[2]); - - if (strcmp(pcixClock, "33") == 0) - data = 0x00000701; - - if (strcmp(pcixClock, "66") == 0) - data = 0x00000601; - - if (strcmp(pcixClock, "100") == 0) - data = 0x00000501; - - if (strcmp(pcixClock, "133") == 0) - data = 0x00000401; - - if (strcmp(plbClock, "166") == 0) - data = data | 0x05950000; - else - data = data | 0x05A50000; - -#ifdef DEBUG - printf(" pin strap1 to write in i2c = %x\n", data); -#endif /* DEBUG */ - - udelay(1000); - if (i2c_write(chip, 4, 1, (uchar *)&data, 4) != 0) - printf("Error writing strap1 in %s\n", argv[2]); - - return 0; -} - -U_BOOT_CMD( - evb440spe, 3, 1, do_evb440spe, - "program the serial device strap", - "wrclk [prom0|prom1] - program the serial device strap" -); diff --git a/qemu/roms/u-boot/board/amcc/yucca/config.mk b/qemu/roms/u-boot/board/amcc/yucca/config.mk deleted file mode 100644 index 05a4162db..000000000 --- a/qemu/roms/u-boot/board/amcc/yucca/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# AMCC 440SPe Reference Platform (yucca) board -# - -ifeq ($(ramsym),1) -CONFIG_SYS_TEXT_BASE = 0x07FD0000 -else -CONFIG_SYS_TEXT_BASE = 0xfffb0000 -endif - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/qemu/roms/u-boot/board/amcc/yucca/flash.c b/qemu/roms/u-boot/board/amcc/yucca/flash.c deleted file mode 100644 index b1fd6576f..000000000 --- a/qemu/roms/u-boot/board/amcc/yucca/flash.c +++ /dev/null @@ -1,1033 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> - * Add support for Am29F016D and dynamic switch setting. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include <asm/ppc440.h> -#include "yucca.h" - -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0 - */ -static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = { - {0xfff00000, 0xfff80000, 0xe7c00001}, /* 0:boot from small flash */ - {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */ - {0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash */ - {0xe7F00000, 0xe7F80000, 0xFFC00001}, /* 3:boot from big flash 33*/ - {0xe7F00000, 0xe7F80000, 0xFFC00001}, /* 4:boot from big flash 66*/ - {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */ - {0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */ - {0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */ - {0xfff00000, 0xfff80000, 0xe7c00001}, /* 8:boot from small flash */ -}; - -/* - * include common flash code (for amcc boards) - */ -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word(flash_info_t * info, ulong dest, ulong data); -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -static int write_word_1(flash_info_t * info, ulong dest, ulong data); -static int write_word_2(flash_info_t * info, ulong dest, ulong data); -static int flash_erase_1(flash_info_t * info, int s_first, int s_last); -static int flash_erase_2(flash_info_t * info, int s_first, int s_last); -static ulong flash_get_size_1(vu_long * addr, flash_info_t * info); -static ulong flash_get_size_2(vu_long * addr, flash_info_t * info); -#endif - -void flash_print_info(flash_info_t * info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_STM: - printf("STM "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_SST: - printf("SST "); - break; - case FLASH_MAN_MX: - printf("MIXC "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AMD016: - printf("AM29F016D (16 Mbit, uniform sector size)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AM033C: - printf("AM29LV033C (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST800A: - printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: - printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - case FLASH_STMW320DT: - printf ("M29W320DT (32 M, top sector)\n"); - break; - case FLASH_MXLV320T: - printf ("MXLV320T (32 Mbit, top sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s%s", - info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); - } - printf("\n"); - return; -} - - -/* - * The following code cannot be run from FLASH! - */ -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - /* bit 0 used for big flash marking */ - if ((ulong)addr & 0x1) - return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info); - else - return flash_get_size_1(addr, info); -} - -static ulong flash_get_size_1(vu_long * addr, flash_info_t * info) -#else -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -#endif -{ - short i; - CONFIG_SYS_FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); - - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; - udelay(1000); - - value = addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D: - info->flash_id += FLASH_AMD016; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C: - info->flash_id += FLASH_AMDLV033C; - info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - - /* For AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if (i == 32) { - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; - - return (info->size); -} - -static int wait_for_DQ7_1(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = - (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) { - return flash_erase_2(info, s_first, s_last); - } else { - return flash_erase_1(info, s_first, s_last); - } -} - -static int flash_erase_1(flash_info_t * info, int s_first, int s_last) -#else -int flash_erase(flash_info_t * info, int s_first, int s_last) -#endif -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) - printf("- Warning: %d protected sectors will not be erased!", prot); - - printf("\n"); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_1(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - - for (; cnt == 0 && i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - if ((rc = write_word(info, wp, data)) != 0) - return (rc); - - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) - data = (data << 8) | *src++; - - if ((rc = write_word(info, wp, data)) != 0) - return (rc); - - wp += 4; - cnt -= 4; - } - - if (cnt == 0) - return (0); - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -static int write_word(flash_info_t * info, ulong dest, ulong data) -{ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) { - return write_word_2(info, dest, data); - } else { - return write_word_1(info, dest, data); - } -} - -static int write_word_1(flash_info_t * info, ulong dest, ulong data) -#else -static int write_word(flash_info_t * info, ulong dest, ulong data) -#endif -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data; - ulong start; - int i, flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) - return (2); - - for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return (1); - } - } - - return (0); -} - -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV - -#undef CONFIG_SYS_FLASH_WORD_SIZE -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) -{ - short i; - int n; - CONFIG_SYS_FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; - udelay(1000); - - value = addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) MX_MANUFACT: - info->flash_id = FLASH_MAN_MX; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 4 MB */ - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 4 MB */ - case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT: - info->flash_id += FLASH_STMW320DT; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - case (CONFIG_SYS_FLASH_WORD_SIZE)MX_ID_LV320T: - info->flash_id += FLASH_MXLV320T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 4 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) { - /* set sector offsets for top boot block type */ - base += info->size; - i = info->sector_count; - /* 1 x 16k boot sector */ - base -= 16 << 10; - --i; - info->start[i] = base; - /* 2 x 8k boot sectors */ - for (n = 0; n < 2; ++n) { - base -= 8 << 10; - --i; - info->start[i] = base; - } - /* 1 x 32k boot sector */ - base -= 32 << 10; - --i; - info->start[i] = base; - - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) { - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000a000; - info->start[i--] = base + info->size - 0x0000c000; - info->start[i--] = base + info->size - 0x0000e000; - info->start[i--] = base + info->size - 0x00010000; - - for (; i >= 0; i--) - info->start[i] = base + i * 0x00010000; - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - - for (i = 4; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - - for (; i >= 0; i--) - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - - /* For AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if (i == 32) { - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; - - return (info->size); -} - -static int wait_for_DQ7_2(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = - (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -static int flash_erase_2(flash_info_t * info, int s_first, int s_last) -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) - printf("- Warning: %d protected sectors will not be erased!", prot); - - printf("\n"); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_2(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -static int write_word_2(flash_info_t * info, ulong dest, ulong data) -{ - ulong *data_ptr = &data; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) - return (2); - - for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return (1); - } - } - - return (0); -} -#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_word(flash_info_t * info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - unsigned long total_b = 0; - unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; - unsigned short index = 0; - int i; - unsigned long val; - unsigned long ebc_boot_size; - unsigned long boot_selection; - - mfsdr(sdr_pstrp0, val); - index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 28; - - if ((index == 0xc) || (index == 8)) { - /* - * Boot Settings in IIC EEprom address 0xA8 or 0xA0 - * Read Serial Device Strap Register1 in PPC440SPe - */ - mfsdr(SDR0_SDSTP1, val); - boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK; - ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK; - - switch(boot_selection) { - case SDR0_SDSTP1_BOOT_SEL_EBC: - switch(ebc_boot_size) { - case SDR0_SDSTP1_EBC_ROM_BS_16BIT: - index = 3; - break; - case SDR0_SDSTP1_EBC_ROM_BS_8BIT: - index = 0; - break; - } - break; - - case SDR0_SDSTP1_BOOT_SEL_PCI: - index = 1; - break; - - } - } /*else if (index == 0) {*/ -/* if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE)*/ -/* index = 8;*/ /* sram below op code flash -> new index 8*/ -/* }*/ - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - - /* check whether the address is 0 */ - if (flash_addr_table[index][i] == 0) - continue; - - /* call flash_get_size() to initialize sector address */ - size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], - &flash_info[i]); - - flash_info[i].size = size_b[i]; - - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i] << 20); - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - } - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[i]); -#if defined(CONFIG_ENV_IS_IN_FLASH) - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[i]); -#if defined(CONFIG_ENV_ADDR_REDUND) - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[i]); -#endif -#endif - total_b += flash_info[i].size; - } - - return total_b; -} diff --git a/qemu/roms/u-boot/board/amcc/yucca/init.S b/qemu/roms/u-boot/board/amcc/yucca/init.S deleted file mode 100644 index 7da5c0d44..000000000 --- a/qemu/roms/u-boot/board/amcc/yucca/init.S +++ /dev/null @@ -1,106 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> -#include <asm/ppc4xx.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - -/************************************************************************** - * TLB table for revA - *************************************************************************/ - .globl tlbtabA -tlbtabA: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I) - tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I) - - tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG) - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG) - tlbtab_end - -/************************************************************************** - * TLB table for revB - * - * Notice: revB of the 440SPe chip is very strict about PLB real addresses - * and ranges to be mapped for config space: it seems to only work with - * d_nnnn_nnnn range (hangs the core upon config transaction attempts when - * set otherwise) while revA uses c_nnnn_nnnn. - *************************************************************************/ - .globl tlbtabB -tlbtabB: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I) - tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I) - - tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG) - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG) - tlbtab_end diff --git a/qemu/roms/u-boot/board/amcc/yucca/yucca.c b/qemu/roms/u-boot/board/amcc/yucca/yucca.c deleted file mode 100644 index c0445ef22..000000000 --- a/qemu/roms/u-boot/board/amcc/yucca/yucca.c +++ /dev/null @@ -1,714 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Port to AMCC-440SPE Evaluation Board SOP - April 2005 - * - * PCIe supporting routines derived from Linux 440SPe PCIe driver. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <i2c.h> -#include <netdev.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/4xx_pcie.h> -#include <asm/errno.h> - -#include "yucca.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fpga_init (void); - -#define DEBUG_ENV -#ifdef DEBUG_ENV -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif - -int board_early_init_f (void) -{ -/*----------------------------------------------------------------------------+ -| Define Boot devices -+----------------------------------------------------------------------------*/ -#define BOOT_FROM_SMALL_FLASH 0x00 -#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01 -#define BOOT_FROM_PCI 0x02 -#define BOOT_DEVICE_UNKNOWN 0x03 - -/*----------------------------------------------------------------------------+ -| EBC Devices Characteristics -| Peripheral Bank Access Parameters - EBC_BxAP -| Peripheral Bank Configuration Register - EBC_BxCR -+----------------------------------------------------------------------------*/ - -/* - * Small Flash and FRAM - * BU Value - * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 - * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000 - * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000 - */ -#define EBC_BXAP_SMALL_FLASH EBC_BXAP_BME_DISABLED | \ - EBC_BXAP_TWT_ENCODE(7) | \ - EBC_BXAP_BCE_DISABLE | \ - EBC_BXAP_BCT_2TRANS | \ - EBC_BXAP_CSN_ENCODE(0) | \ - EBC_BXAP_OEN_ENCODE(0) | \ - EBC_BXAP_WBN_ENCODE(0) | \ - EBC_BXAP_WBF_ENCODE(0) | \ - EBC_BXAP_TH_ENCODE(0) | \ - EBC_BXAP_RE_DISABLED | \ - EBC_BXAP_SOR_DELAYED | \ - EBC_BXAP_BEM_WRITEONLY | \ - EBC_BXAP_PEN_DISABLED - -#define EBC_BXCR_SMALL_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \ - EBC_BXCR_BS_16MB | \ - EBC_BXCR_BU_RW | \ - EBC_BXCR_BW_8BIT - -#define EBC_BXCR_SMALL_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xe7000000) | \ - EBC_BXCR_BS_16MB | \ - EBC_BXCR_BU_RW | \ - EBC_BXCR_BW_8BIT - -/* - * Large Flash and SRAM - * BU Value - * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 - * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000 - * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000 -*/ -#define EBC_BXAP_LARGE_FLASH EBC_BXAP_BME_DISABLED | \ - EBC_BXAP_TWT_ENCODE(7) | \ - EBC_BXAP_BCE_DISABLE | \ - EBC_BXAP_BCT_2TRANS | \ - EBC_BXAP_CSN_ENCODE(0) | \ - EBC_BXAP_OEN_ENCODE(0) | \ - EBC_BXAP_WBN_ENCODE(0) | \ - EBC_BXAP_WBF_ENCODE(0) | \ - EBC_BXAP_TH_ENCODE(0) | \ - EBC_BXAP_RE_DISABLED | \ - EBC_BXAP_SOR_DELAYED | \ - EBC_BXAP_BEM_WRITEONLY | \ - EBC_BXAP_PEN_DISABLED - -#define EBC_BXCR_LARGE_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \ - EBC_BXCR_BS_16MB | \ - EBC_BXCR_BU_RW | \ - EBC_BXCR_BW_16BIT - -#define EBC_BXCR_LARGE_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xE7000000) | \ - EBC_BXCR_BS_16MB | \ - EBC_BXCR_BU_RW | \ - EBC_BXCR_BW_16BIT - -/* - * FPGA - * BU value : - * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000 - * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000 - */ -#define EBC_BXAP_FPGA EBC_BXAP_BME_DISABLED | \ - EBC_BXAP_TWT_ENCODE(11) | \ - EBC_BXAP_BCE_DISABLE | \ - EBC_BXAP_BCT_2TRANS | \ - EBC_BXAP_CSN_ENCODE(10) | \ - EBC_BXAP_OEN_ENCODE(1) | \ - EBC_BXAP_WBN_ENCODE(1) | \ - EBC_BXAP_WBF_ENCODE(1) | \ - EBC_BXAP_TH_ENCODE(1) | \ - EBC_BXAP_RE_DISABLED | \ - EBC_BXAP_SOR_DELAYED | \ - EBC_BXAP_BEM_RW | \ - EBC_BXAP_PEN_DISABLED - -#define EBC_BXCR_FPGA_CS1 EBC_BXCR_BAS_ENCODE(0xe2000000) | \ - EBC_BXCR_BS_1MB | \ - EBC_BXCR_BU_RW | \ - EBC_BXCR_BW_16BIT - - unsigned long mfr; - /* - * Define Variables for EBC initialization depending on BOOTSTRAP option - */ - unsigned long sdr0_pinstp, sdr0_sdstp1 ; - unsigned long bootstrap_settings, ebc_data_width, boot_selection; - int computed_boot_device = BOOT_DEVICE_UNKNOWN; - - /*-------------------------------------------------------------------+ - | Initialize EBC CONFIG - - | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC - | default value : - | 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 - | - +-------------------------------------------------------------------*/ - mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | - EBC_CFG_PTD_ENABLE | - EBC_CFG_RTC_16PERCLK | - EBC_CFG_ATC_PREVIOUS | - EBC_CFG_DTC_PREVIOUS | - EBC_CFG_CTC_PREVIOUS | - EBC_CFG_OEO_PREVIOUS | - EBC_CFG_EMC_DEFAULT | - EBC_CFG_PME_DISABLE | - EBC_CFG_PR_16); - - /*-------------------------------------------------------------------+ - | - | PART 1 : Initialize EBC Bank 1 - | ============================== - | Bank1 is always associated to the EPLD. - | It has to be initialized prior to other banks settings computation - | since some board registers values may be needed to determine the - | boot type - | - +-------------------------------------------------------------------*/ - mtebc(PB1AP, EBC_BXAP_FPGA); - mtebc(PB1CR, EBC_BXCR_FPGA_CS1); - - /*-------------------------------------------------------------------+ - | - | PART 2 : Determine which boot device was selected - | ================================================= - | - | Read Pin Strap Register in PPC440SPe - | Result can either be : - | - Boot strap = boot from EBC 8bits => Small Flash - | - Boot strap = boot from PCI - | - Boot strap = IIC - | In case of boot from IIC, read Serial Device Strap Register1 - | - | Result can either be : - | - Boot from EBC - EBC Bus Width = 8bits => Small Flash - | - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM - | - Boot from PCI - | - +-------------------------------------------------------------------*/ - /* Read Pin Strap Register in PPC440SP */ - mfsdr(SDR0_PINSTP, sdr0_pinstp); - bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK; - - switch (bootstrap_settings) { - case SDR0_PINSTP_BOOTSTRAP_SETTINGS0: - /* - * Strapping Option A - * Boot from EBC - 8 bits , Small Flash - */ - computed_boot_device = BOOT_FROM_SMALL_FLASH; - break; - case SDR0_PINSTP_BOOTSTRAP_SETTINGS1: - /* - * Strappping Option B - * Boot from PCI - */ - computed_boot_device = BOOT_FROM_PCI; - break; - case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN: - case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN: - /* - * Strapping Option C or D - * Boot Settings in IIC EEprom address 0x50 or 0x54 - * Read Serial Device Strap Register1 in PPC440SPe - */ - mfsdr(SDR0_SDSTP1, sdr0_sdstp1); - boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK; - ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK; - - switch (boot_selection) { - case SDR0_SDSTP1_ERPN_EBC: - switch (ebc_data_width) { - case SDR0_SDSTP1_EBCW_16_BITS: - computed_boot_device = - BOOT_FROM_LARGE_FLASH_OR_SRAM; - break; - case SDR0_SDSTP1_EBCW_8_BITS : - computed_boot_device = BOOT_FROM_SMALL_FLASH; - break; - } - break; - - case SDR0_SDSTP1_ERPN_PCI: - computed_boot_device = BOOT_FROM_PCI; - break; - default: - /* should not occure */ - computed_boot_device = BOOT_DEVICE_UNKNOWN; - } - break; - default: - /* should not be */ - computed_boot_device = BOOT_DEVICE_UNKNOWN; - break; - } - - /*-------------------------------------------------------------------+ - | - | PART 3 : Compute EBC settings depending on selected boot device - | ====== ====================================================== - | - | Resulting EBC init will be among following configurations : - | - | - Boot from EBC 8bits => boot from Small Flash selected - | EBC-CS0 = Small Flash - | EBC-CS2 = Large Flash and SRAM - | - | - Boot from EBC 16bits => boot from Large Flash or SRAM - | EBC-CS0 = Large Flash or SRAM - | EBC-CS2 = Small Flash - | - | - Boot from PCI - | EBC-CS0 = not initialized to avoid address contention - | EBC-CS2 = same as boot from Small Flash selected - | - +-------------------------------------------------------------------*/ - unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0; - unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0; - - switch (computed_boot_device) { - /*-------------------------------------------------------------------*/ - case BOOT_FROM_PCI: - /*-------------------------------------------------------------------*/ - /* - * By Default CS2 is affected to LARGE Flash - * do not initialize SMALL FLASH to avoid address contention - * Large Flash - */ - ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; - ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2; - break; - - /*-------------------------------------------------------------------*/ - case BOOT_FROM_SMALL_FLASH: - /*-------------------------------------------------------------------*/ - ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH; - ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0; - - /* - * Large Flash or SRAM - */ - /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */ - ebc0_cs2_bxap_value = 0x048ff240; - ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2; - break; - - /*-------------------------------------------------------------------*/ - case BOOT_FROM_LARGE_FLASH_OR_SRAM: - /*-------------------------------------------------------------------*/ - ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH; - ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0; - - /* Small flash */ - ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH; - ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2; - break; - - /*-------------------------------------------------------------------*/ - default: - /*-------------------------------------------------------------------*/ - /* BOOT_DEVICE_UNKNOWN */ - break; - } - - mtebc(PB0AP, ebc0_cs0_bxap_value); - mtebc(PB0CR, ebc0_cs0_bxcr_value); - mtebc(PB2AP, ebc0_cs2_bxap_value); - mtebc(PB2CR, ebc0_cs2_bxcr_value); - - /*--------------------------------------------------------------------+ - | Interrupt controller setup for the AMCC 440SPe Evaluation board. - +--------------------------------------------------------------------+ - +---------------------------------------------------------------------+ - |Interrupt| Source | Pol. | Sensi.| Crit. | - +---------+-----------------------------------+-------+-------+-------+ - | IRQ 00 | UART0 | High | Level | Non | - | IRQ 01 | UART1 | High | Level | Non | - | IRQ 02 | IIC0 | High | Level | Non | - | IRQ 03 | IIC1 | High | Level | Non | - | IRQ 04 | PCI0X0 MSG IN | High | Level | Non | - | IRQ 05 | PCI0X0 CMD Write | High | Level | Non | - | IRQ 06 | PCI0X0 Power Mgt | High | Level | Non | - | IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non | - | IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non | - | IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non | - | IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non | - | IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit | - | IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non | - | IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non | - | IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non | - | IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non | - | IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non | - | IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit | - | IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non | - | IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non | - | IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non | - | IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non | - | IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non | - | IRQ 23 | I2O Inbound Doorbell | High | Level | Non | - | IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non | - | IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non | - | IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non | - | IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non | - | IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non | - | IRQ 29 | GPT Down Count Timer | Rising| Edge | Non | - | IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non | - | IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. | - |---------------------------------------------------------------------- - | IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non | - | IRQ 33 | MAL Serr | High | Level | Non | - | IRQ 34 | MAL Txde | High | Level | Non | - | IRQ 35 | MAL Rxde | High | Level | Non | - | IRQ 36 | DMC CE or DMC UE | High | Level | Non | - | IRQ 37 | EBC or UART2 | High |Lvl Edg| Non | - | IRQ 38 | MAL TX EOB | High | Level | Non | - | IRQ 39 | MAL RX EOB | High | Level | Non | - | IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non | - | IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non | - | IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non | - | IRQ 43 | L2 Cache | Risin | Edge | Non | - | IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non | - | IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non | - | IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non | - | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | - | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | - | IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non | - | IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non | - | IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non | - | IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | - | IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non | - | IRQ 54 | DMA Error | High | Level | Non | - | IRQ 55 | DMA I2O Error | High | Level | Non | - | IRQ 56 | Serial ROM | High | Level | Non | - | IRQ 57 | PCIX0 Error | High | Edge | Non | - | IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non | - | IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non | - | IRQ 60 | EMAC0 Interrupt | High | Level | Non | - | IRQ 61 | EMAC0 Wake-up | High | Level | Non | - | IRQ 62 | Reserved | High | Level | Non | - | IRQ 63 | XOR | High | Level | Non | - |---------------------------------------------------------------------- - | IRQ 64 | PE0 AL | High | Level | Non | - | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | - | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | - | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | - | IRQ 68 | PE0 TCR | High | Level | Non | - | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | - | IRQ 70 | PE0 DCR Error | High | Level | Non | - | IRQ 71 | Reserved | N/A | N/A | Non | - | IRQ 72 | PE1 AL | High | Level | Non | - | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | - | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | - | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | - | IRQ 76 | PE1 TCR | High | Level | Non | - | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | - | IRQ 78 | PE1 DCR Error | High | Level | Non | - | IRQ 79 | Reserved | N/A | N/A | Non | - | IRQ 80 | PE2 AL | High | Level | Non | - | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | - | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | - | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | - | IRQ 84 | PE2 TCR | High | Level | Non | - | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | - | IRQ 86 | PE2 DCR Error | High | Level | Non | - | IRQ 87 | Reserved | N/A | N/A | Non | - | IRQ 88 | External IRQ(5) | Progr | Progr | Non | - | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | - | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | - | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | - | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | - | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | - | IRQ 94 | Reserved | N/A | N/A | Non | - | IRQ 95 | Reserved | N/A | N/A | Non | - |--------------------------------------------------------------------- - | IRQ 96 | PE0 INTA | High | Level | Non | - | IRQ 97 | PE0 INTB | High | Level | Non | - | IRQ 98 | PE0 INTC | High | Level | Non | - | IRQ 99 | PE0 INTD | High | Level | Non | - | IRQ 100 | PE1 INTA | High | Level | Non | - | IRQ 101 | PE1 INTB | High | Level | Non | - | IRQ 102 | PE1 INTC | High | Level | Non | - | IRQ 103 | PE1 INTD | High | Level | Non | - | IRQ 104 | PE2 INTA | High | Level | Non | - | IRQ 105 | PE2 INTB | High | Level | Non | - | IRQ 106 | PE2 INTC | High | Level | Non | - | IRQ 107 | PE2 INTD | Risin | Edge | Non | - | IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non | - | IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non | - | IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non | - | IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non | - | IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non | - | IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non | - | IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non | - | IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non | - | IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non | - | IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non | - | IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non | - | IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non | - | IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non | - | IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non | - | IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non | - | IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non | - | IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non | - | IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non | - | IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non | - | IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non | - +---------+-----------------------------------+-------+-------+------*/ - /*--------------------------------------------------------------------+ - | Put UICs in PowerPC440SPemode. - | Initialise UIC registers. Clear all interrupts. Disable all - | interrupts. - | Set critical interrupt values. Set interrupt polarities. Set - | interrupt trigger levels. Make bit 0 High priority. Clear all - | interrupts again. - +-------------------------------------------------------------------*/ - mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */ - mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical - * interrupts */ - mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ - mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest - * priority */ - mtdcr (UIC3SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts */ - - mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */ - mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical - * interrupts */ - mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities */ - mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ - mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest - * priority */ - mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ - - mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */ - mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical - * interrupts */ - mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels */ - mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest - * priority */ - mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */ - - mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted - * cascade to be checked */ - mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical - * interrupts */ - mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */ - mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest - * priority */ - mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */ - - mfsdr(SDR0_MFR, mfr); - mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ - mtsdr(SDR0_MFR, mfr); - - fpga_init(); - - return 0; -} - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: Yucca - AMCC 440SPe Evaluation Board"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -/* - * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with - * board specific values. - */ -static int ppc440spe_rev_a(void) -{ - if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA)) - return 1; - else - return 0; -} - -u32 ddr_wrdtr(u32 default_val) { - /* - * Yucca boards with 440SPe rev. A need a slightly different setup - * for the MCIF0_WRDTR register. - */ - if (ppc440spe_rev_a()) - return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV); - - return default_val; -} - -u32 ddr_clktr(u32 default_val) { - /* - * Yucca boards with 440SPe rev. A need a slightly different setup - * for the MCIF0_CLKTR register. - */ - if (ppc440spe_rev_a()) - return (SDRAM_CLKTR_CLKP_180_DEG_ADV); - - return default_val; -} - -#if defined(CONFIG_PCI) -int board_pcie_card_present(int port) -{ - u16 reg; - - reg = in_be16((u16 *)FPGA_REG1C); - switch(port) { - case 0: - return !(reg & FPGA_REG1C_PE0_PRSNT); - case 1: - return !(reg & FPGA_REG1C_PE1_PRSNT); - case 2: - return !(reg & FPGA_REG1C_PE2_PRSNT); - default: - return 0; - } -} - -/* - * For the given slot, set endpoint mode, send power to the slot, - * turn on the green LED and turn off the yellow LED, enable the - * clock. In endpoint mode reset bit is read only. - */ -void board_pcie_setup_port(int port, int rootpoint) -{ - u16 power, clock, green_led, yellow_led, - reset_off, rp, ep; - - switch (port) { - case 0: - rp = FPGA_REG1C_PE0_ROOTPOINT; - ep = 0; - break; - case 1: - rp = 0; - ep = FPGA_REG1C_PE1_ENDPOINT; - break; - case 2: - rp = 0; - ep = FPGA_REG1C_PE2_ENDPOINT; - break; - - default: - return; - } - - power = FPGA_REG1A_PWRON_ENCODE(port); - green_led = FPGA_REG1A_GLED_ENCODE(port); - clock = FPGA_REG1A_REFCLK_ENCODE(port); - yellow_led = FPGA_REG1A_YLED_ENCODE(port); - reset_off = FPGA_REG1C_PERST_ENCODE(port); - - out_be16((u16 *)FPGA_REG1A, ~(power | clock | green_led) & - (yellow_led | in_be16((u16 *)FPGA_REG1A))); - - out_be16((u16 *)FPGA_REG1C, ~(ep | reset_off) & - (rp | in_be16((u16 *)FPGA_REG1C))); - - if (rootpoint) { - /* - * Leave device in reset for a while after powering on the - * slot to give it a chance to initialize. - */ - udelay(250 * 1000); - - out_be16((u16 *)FPGA_REG1C, - reset_off | in_be16((u16 *)FPGA_REG1C)); - } -} -#endif /* defined(CONFIG_PCI) */ - -int misc_init_f (void) -{ - uint reg; - - out16(FPGA_REG10, (in16(FPGA_REG10) & - ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) | - FPGA_REG10_10MHZ_ENABLE | - FPGA_REG10_100MHZ_ENABLE | - FPGA_REG10_GIGABIT_ENABLE | - FPGA_REG10_FULL_DUPLEX ); - - udelay(10000); /* wait 10ms */ - - out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH)); - - /* minimal init for PCIe */ - /* pci express 0 Endpoint Mode */ - mfsdr(SDRN_PESDR_DLPSET(0), reg); - reg &= (~0x00400000); - mtsdr(SDRN_PESDR_DLPSET(0), reg); - /* pci express 1 Rootpoint Mode */ - mfsdr(SDRN_PESDR_DLPSET(1), reg); - reg |= 0x00400000; - mtsdr(SDRN_PESDR_DLPSET(1), reg); - /* pci express 2 Rootpoint Mode */ - mfsdr(SDRN_PESDR_DLPSET(2), reg); - reg |= 0x00400000; - mtsdr(SDRN_PESDR_DLPSET(2), reg); - - out16(FPGA_REG1C,(in16 (FPGA_REG1C) & - ~FPGA_REG1C_PE0_ROOTPOINT & - ~FPGA_REG1C_PE1_ENDPOINT & - ~FPGA_REG1C_PE2_ENDPOINT)); - - return 0; -} - -void fpga_init(void) -{ - /* - * by default sdram access is disabled by fpga - */ - out16(FPGA_REG10, (in16 (FPGA_REG10) | - FPGA_REG10_SDRAM_ENABLE | - FPGA_REG10_ENABLE_DISPLAY )); - - return; -} - -/*---------------------------------------------------------------------------+ - | onboard_pci_arbiter_selected => from EPLD - +---------------------------------------------------------------------------*/ -int onboard_pci_arbiter_selected(int core_pci) -{ -#if 0 - unsigned long onboard_pci_arbiter_sel; - - onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK; - - if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL) - return (BOARD_OPTION_SELECTED); - else -#endif - return (BOARD_OPTION_NOT_SELECTED); -} - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); - return pci_eth_init(bis); -} diff --git a/qemu/roms/u-boot/board/amcc/yucca/yucca.h b/qemu/roms/u-boot/board/amcc/yucca/yucca.h deleted file mode 100644 index ac9e5ae5b..000000000 --- a/qemu/roms/u-boot/board/amcc/yucca/yucca.h +++ /dev/null @@ -1,350 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __YUCCA_H_ -#define __YUCCA_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/*----------------------------------------------------------------------------+ -| Defines -+----------------------------------------------------------------------------*/ - -#define TMR_FREQ_EXT 25000000 -#define BOARD_UART_CLOCK 11059200 - -#define BOARD_OPTION_SELECTED 1 -#define BOARD_OPTION_NOT_SELECTED 0 - -#define ENGINEERING_CLOCK_CHECKING "clk_chk" -#define ENGINEERING_EXTERNAL_CLOCK "ext_clk" - -#define ENGINEERING_CLOCK_CHECKING_DATA 1 -#define ENGINEERING_EXTERNAL_CLOCK_DATA 2 - -/* ethernet definition */ -#define MAX_ENETMODE_PARM 3 -#define ENETMODE_NEG 0 -#define ENETMODE_SPEED 1 -#define ENETMODE_DUPLEX 2 - -#define ENETMODE_AUTONEG 0 -#define ENETMODE_NO_AUTONEG 1 -#define ENETMODE_10 2 -#define ENETMODE_100 3 -#define ENETMODE_1000 4 -#define ENETMODE_HALF 5 -#define ENETMODE_FULL 6 - -#define NUM_TLB_ENTRIES 64 - -/* MICRON SPD JEDEC ID Code (first byte) - SPD data byte [64] */ -#define MICRON_SPD_JEDEC_ID 0x2c - -/*----------------------------------------------------------------------------+ -| TLB specific defines. -+----------------------------------------------------------------------------*/ -#define TLB_256MB_ALIGN_MASK 0xF0000000 -#define TLB_16MB_ALIGN_MASK 0xFF000000 -#define TLB_1MB_ALIGN_MASK 0xFFF00000 -#define TLB_256KB_ALIGN_MASK 0xFFFC0000 -#define TLB_64KB_ALIGN_MASK 0xFFFF0000 -#define TLB_16KB_ALIGN_MASK 0xFFFFC000 -#define TLB_4KB_ALIGN_MASK 0xFFFFF000 -#define TLB_1KB_ALIGN_MASK 0xFFFFFC00 -#define TLB_256MB_SIZE 0x10000000 -#define TLB_16MB_SIZE 0x01000000 -#define TLB_1MB_SIZE 0x00100000 -#define TLB_256KB_SIZE 0x00040000 -#define TLB_64KB_SIZE 0x00010000 -#define TLB_16KB_SIZE 0x00004000 -#define TLB_4KB_SIZE 0x00001000 -#define TLB_1KB_SIZE 0x00000400 - -#define TLB_WORD0_EPN_MASK 0xFFFFFC00 -#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00) -#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00) -#define TLB_WORD0_V_MASK 0x00000200 -#define TLB_WORD0_V_ENABLE 0x00000200 -#define TLB_WORD0_V_DISABLE 0x00000000 -#define TLB_WORD0_TS_MASK 0x00000100 -#define TLB_WORD0_TS_1 0x00000100 -#define TLB_WORD0_TS_0 0x00000000 -#define TLB_WORD0_SIZE_MASK 0x000000F0 -#define TLB_WORD0_SIZE_1KB 0x00000000 -#define TLB_WORD0_SIZE_4KB 0x00000010 -#define TLB_WORD0_SIZE_16KB 0x00000020 -#define TLB_WORD0_SIZE_64KB 0x00000030 -#define TLB_WORD0_SIZE_256KB 0x00000040 -#define TLB_WORD0_SIZE_1MB 0x00000050 -#define TLB_WORD0_SIZE_16MB 0x00000070 -#define TLB_WORD0_SIZE_256MB 0x00000090 -#define TLB_WORD0_TPAR_MASK 0x0000000F -#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0) -#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F) - -#define TLB_WORD1_RPN_MASK 0xFFFFFC00 -#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00) -#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00) -#define TLB_WORD1_PAR1_MASK 0x00000300 -#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8) -#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03) -#define TLB_WORD1_PAR1_0 0x00000000 -#define TLB_WORD1_PAR1_1 0x00000100 -#define TLB_WORD1_PAR1_2 0x00000200 -#define TLB_WORD1_PAR1_3 0x00000300 -#define TLB_WORD1_ERPN_MASK 0x0000000F -#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0) -#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F) - -#define TLB_WORD2_PAR2_MASK 0xC0000000 -#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30) -#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03) -#define TLB_WORD2_PAR2_0 0x00000000 -#define TLB_WORD2_PAR2_1 0x40000000 -#define TLB_WORD2_PAR2_2 0x80000000 -#define TLB_WORD2_PAR2_3 0xC0000000 -#define TLB_WORD2_U0_MASK 0x00008000 -#define TLB_WORD2_U0_ENABLE 0x00008000 -#define TLB_WORD2_U0_DISABLE 0x00000000 -#define TLB_WORD2_U1_MASK 0x00004000 -#define TLB_WORD2_U1_ENABLE 0x00004000 -#define TLB_WORD2_U1_DISABLE 0x00000000 -#define TLB_WORD2_U2_MASK 0x00002000 -#define TLB_WORD2_U2_ENABLE 0x00002000 -#define TLB_WORD2_U2_DISABLE 0x00000000 -#define TLB_WORD2_U3_MASK 0x00001000 -#define TLB_WORD2_U3_ENABLE 0x00001000 -#define TLB_WORD2_U3_DISABLE 0x00000000 -#define TLB_WORD2_W_MASK 0x00000800 -#define TLB_WORD2_W_ENABLE 0x00000800 -#define TLB_WORD2_W_DISABLE 0x00000000 -#define TLB_WORD2_I_MASK 0x00000400 -#define TLB_WORD2_I_ENABLE 0x00000400 -#define TLB_WORD2_I_DISABLE 0x00000000 -#define TLB_WORD2_M_MASK 0x00000200 -#define TLB_WORD2_M_ENABLE 0x00000200 -#define TLB_WORD2_M_DISABLE 0x00000000 -#define TLB_WORD2_G_MASK 0x00000100 -#define TLB_WORD2_G_ENABLE 0x00000100 -#define TLB_WORD2_G_DISABLE 0x00000000 -#define TLB_WORD2_E_MASK 0x00000080 -#define TLB_WORD2_E_ENABLE 0x00000080 -#define TLB_WORD2_E_DISABLE 0x00000000 -#define TLB_WORD2_UX_MASK 0x00000020 -#define TLB_WORD2_UX_ENABLE 0x00000020 -#define TLB_WORD2_UX_DISABLE 0x00000000 -#define TLB_WORD2_UW_MASK 0x00000010 -#define TLB_WORD2_UW_ENABLE 0x00000010 -#define TLB_WORD2_UW_DISABLE 0x00000000 -#define TLB_WORD2_UR_MASK 0x00000008 -#define TLB_WORD2_UR_ENABLE 0x00000008 -#define TLB_WORD2_UR_DISABLE 0x00000000 -#define TLB_WORD2_SX_MASK 0x00000004 -#define TLB_WORD2_SX_ENABLE 0x00000004 -#define TLB_WORD2_SX_DISABLE 0x00000000 -#define TLB_WORD2_SW_MASK 0x00000002 -#define TLB_WORD2_SW_ENABLE 0x00000002 -#define TLB_WORD2_SW_DISABLE 0x00000000 -#define TLB_WORD2_SR_MASK 0x00000001 -#define TLB_WORD2_SR_ENABLE 0x00000001 -#define TLB_WORD2_SR_DISABLE 0x00000000 - -/*----------------------------------------------------------------------------+ -| Board specific defines. -+----------------------------------------------------------------------------*/ -#define NONCACHE_MEMORY_SIZE (64*1024) -#define NONCACHE_AREA0_ENDOFFSET (64*1024) -#define NONCACHE_AREA1_ENDOFFSET (32*1024) - -#define FLASH_SECTORSIZE 0x00010000 - -/* SDRAM MICRON */ -#define SDRAM_MICRON 0x2C - -#define SDRAM_TRUE 1 -#define SDRAM_FALSE 0 -#define SDRAM_DDR1 1 -#define SDRAM_DDR2 2 -#define SDRAM_NONE 0 -#define MAXDIMMS 2 /* Changes le 12/01/05 pour 1.6 */ -#define MAXRANKS 4 /* Changes le 12/01/05 pour 1.6 */ -#define MAXBANKSPERDIMM 2 -#define MAXRANKSPERDIMM 2 -#define MAXBXCF 4 /* Changes le 12/01/05 pour 1.6 */ -#define MAXSDRAMMEMORY 0xFFFFFFFF /* 4GB */ -#define ERROR_STR_LENGTH 256 -#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */ - -/*----------------------------------------------------------------------------+ -| SDR Configuration registers -+----------------------------------------------------------------------------*/ -/* Serial Device Strap Reg 0 */ -#define sdr_pstrp0 0x0040 - -#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00000080 /* EBC Boot bus width Mask */ -#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00000080 /* EBC 16 Bits */ -#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */ - -#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00080000 /* Boot device Selection Mask */ -#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */ -#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00080000 /* PCI */ - -#define SDR0_SDSTP1_EBC_SIZE_MASK 0x00000060 /* Boot rom size Mask */ -#define SDR0_SDSTP1_BOOT_SIZE_16MB 0x00000060 /* 16 MB */ -#define SDR0_SDSTP1_BOOT_SIZE_8MB 0x00000040 /* 8 MB */ -#define SDR0_SDSTP1_BOOT_SIZE_4MB 0x00000020 /* 4 MB */ -#define SDR0_SDSTP1_BOOT_SIZE_2MB 0x00000000 /* 2 MB */ - -/* Serial Device Enabled - Addr = 0xA8 */ -#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 -/* Serial Device Enabled - Addr = 0xA4 */ -#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 - -/* Pin Straps Reg */ -#define SDR0_PSTRP0 0x0040 -#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */ - -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */ - -/* fpgareg - defines are in include/config/YUCCA.h */ - -#define SDR0_CUST0_ENET3_MASK 0x00000080 -#define SDR0_CUST0_ENET3_COPPER 0x00000000 -#define SDR0_CUST0_ENET3_FIBER 0x00000080 -#define SDR0_CUST0_RGMII3_MASK 0x00000070 -#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4) -#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07) -#define SDR0_CUST0_RGMII3_DISAB 0x00000000 -#define SDR0_CUST0_RGMII3_RTBI 0x00000040 -#define SDR0_CUST0_RGMII3_RGMII 0x00000050 -#define SDR0_CUST0_RGMII3_TBI 0x00000060 -#define SDR0_CUST0_RGMII3_GMII 0x00000070 -#define SDR0_CUST0_ENET2_MASK 0x00000008 -#define SDR0_CUST0_ENET2_COPPER 0x00000000 -#define SDR0_CUST0_ENET2_FIBER 0x00000008 -#define SDR0_CUST0_RGMII2_MASK 0x00000007 -#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) -#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07) -#define SDR0_CUST0_RGMII2_DISAB 0x00000000 -#define SDR0_CUST0_RGMII2_RTBI 0x00000004 -#define SDR0_CUST0_RGMII2_RGMII 0x00000005 -#define SDR0_CUST0_RGMII2_TBI 0x00000006 -#define SDR0_CUST0_RGMII2_GMII 0x00000007 - -#define ONE_MILLION 1000000 -#define ONE_BILLION 1000000000 - -/*----------------------------------------------------------------------------+ -| X -| XX -| XX XXX XXXXX XX XXX XXXXX -| XX XX X XXX XX XX -| XX XX XXXXXX XX XX -| XX XX X XX XX XX XX -| XXX XX XXXXX X XXXX XXX -+----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------+ -| Declare Configuration values -+----------------------------------------------------------------------------*/ - -typedef enum config_selection { - CONFIG_NOT_SELECTED, - CONFIG_SELECTED -} config_selection_t; - -typedef enum config_list { - UART2_IN_SERVICE_MODE, - CPU_TRACE_MODE, - UART1_CTS_RTS, - CONFIG_NB -} config_list_t; - -#define MAX_CONFIG_SELECT_NB 3 - -#define BOARD_INFO_UART2_IN_SERVICE_MODE 1 -#define BOARD_INFO_CPU_TRACE_MODE 2 -#define BOARD_INFO_UART1_CTS_RTS_MODE 4 - -void force_bup_config_selection(config_selection_t *confgi_select_P); -void update_config_selection_table(config_selection_t *config_select_P); -void display_config_selection(config_selection_t *config_select_P); - -/*----------------------------------------------------------------------------+ -| XX -| -| XXXX XX XXX XXX XXXX -| XX XX XX XX XX XX -| XX XXX XX XX XX XX XX -| XX XX XXXXX XX XX XX -| XXXX XX XXXX XXXX -| XXXX -| -| -| -| +------------------------------------------------------------------+ -| | GPIO/Secondary func | Primary Function | I/O | Alternate1 | I/O | -| +----------------------+------------------+-----+------------+-----+ -| | | | | | | -| | GPIO0_0 | PCIX0REQ2_N | I/O | TRCCLK | | -| | GPIO0_1 | PCIX0REQ3_N | I/O | TRCBS0 | | -| | GPIO0_2 | PCIX0GNT2_N | I/O | TRCBS1 | | -| | GPIO0_3 | PCIX0GNT3_N | I/O | TRCBS2 | | -| | GPIO0_4 | PCIX1REQ2_N | I/O | TRCES0 | | -| | GPIO0_5 | PCIX1REQ3_N | I/O | TRCES1 | | -| | GPIO0_6 | PCIX1GNT2_N | I/O | TRCES2 | NA | -| | GPIO0_7 | PCIX1GNT3_N | I/O | TRCES3 | NA | -| | GPIO0_8 | PERREADY | I | TRCES4 | NA | -| | GPIO0_9 | PERCS1_N | O | TRCTS0 | NA | -| | GPIO0_10 | PERCS2_N | O | TRCTS1 | NA | -| | GPIO0_11 | IRQ0 | I | TRCTS2 | NA | -| | GPIO0_12 | IRQ1 | I | TRCTS3 | NA | -| | GPIO0_13 | IRQ2 | I | TRCTS4 | NA | -| | GPIO0_14 | IRQ3 | I | TRCTS5 | NA | -| | GPIO0_15 | IRQ4 | I | TRCTS6 | NA | -| | GPIO0_16 | IRQ5 | I | UART2RX | I | -| | GPIO0_17 | PERBE0_N | O | UART2TX | O | -| | GPIO0_18 | PCI0GNT0_N | I/O | NA | NA | -| | GPIO0_19 | PCI0GNT1_N | I/O | NA | NA | -| | GPIO0_20 | PCI0REQ0_N | I/O | NA | NA | -| | GPIO0_21 | PCI0REQ1_N | I/O | NA | NA | -| | GPIO0_22 | PCI1GNT0_N | I/O | NA | NA | -| | GPIO0_23 | PCI1GNT1_N | I/O | NA | NA | -| | GPIO0_24 | PCI1REQ0_N | I/O | NA | NA | -| | GPIO0_25 | PCI1REQ1_N | I/O | NA | NA | -| | GPIO0_26 | PCI2GNT0_N | I/O | NA | NA | -| | GPIO0_27 | PCI2GNT1_N | I/O | NA | NA | -| | GPIO0_28 | PCI2REQ0_N | I/O | NA | NA | -| | GPIO0_29 | PCI2REQ1_N | I/O | NA | NA | -| | GPIO0_30 | UART1RX | I | NA | NA | -| | GPIO0_31 | UART1TX | O | NA | NA | -| | | | | | | -| +----------------------+------------------+-----+------------+-----+ -| -+----------------------------------------------------------------------------*/ - -unsigned long auto_calc_speed(void); -/*----------------------------------------------------------------------------+ -| Prototypes -+----------------------------------------------------------------------------*/ -void print_evb440spe_info(void); - -int onboard_pci_arbiter_selected(int core_pci); - -#ifdef __cplusplus -} -#endif -#endif /* __YUCCA_H_ */ |