diff options
Diffstat (limited to 'qemu/roms/u-boot/board/LaCie')
20 files changed, 0 insertions, 1601 deletions
diff --git a/qemu/roms/u-boot/board/LaCie/common/common.c b/qemu/roms/u-boot/board/LaCie/common/common.c deleted file mode 100644 index d6ffefec8..000000000 --- a/qemu/roms/u-boot/board/LaCie/common/common.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <i2c.h> -#include <miiphy.h> - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) - -#define MII_MARVELL_PHY_PAGE 22 - -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) - -void mv_phy_88e1116_init(const char *name, u16 phyaddr) -{ - u16 reg; - - if (miiphy_set_current_dev(name)) - return; - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2); - miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®); - reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0); - - if (miiphy_reset(name, phyaddr) == 0) - printf("88E1116 Initialized on %s\n", name); -} - -void mv_phy_88e1318_init(const char *name, u16 phyaddr) -{ - u16 reg; - - if (miiphy_set_current_dev(name)) - return; - - /* - * Set control mode 4 for LED[0]. - */ - miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3); - miiphy_read(name, phyaddr, 16, ®); - reg |= 0xf; - miiphy_write(name, phyaddr, 16, reg); - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2); - miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®); - reg |= (MV88E1116_RGMII_TXTM_CTRL | MV88E1116_RGMII_RXTM_CTRL); - miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0); - - if (miiphy_reset(name, phyaddr) == 0) - printf("88E1318 Initialized on %s\n", name); -} -#endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */ - -#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) -int lacie_read_mac_address(uchar *mac_addr) -{ - int ret; - ushort version; - - /* I2C-0 for on-board EEPROM */ - i2c_set_bus_num(0); - - /* Check layout version for EEPROM data */ - ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - (uchar *) &version, 2); - if (ret != 0) { - printf("Error: failed to read I2C EEPROM @%02x\n", - CONFIG_SYS_I2C_EEPROM_ADDR); - return ret; - } - version = be16_to_cpu(version); - if (version < 1 || version > 3) { - printf("Error: unknown version %d for EEPROM data\n", - version); - return -1; - } - - /* Read Ethernet MAC address from EEPROM */ - ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 2, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, mac_addr, 6); - if (ret != 0) - printf("Error: failed to read I2C EEPROM @%02x\n", - CONFIG_SYS_I2C_EEPROM_ADDR); - return ret; -} -#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_EEPROM_ADDR */ diff --git a/qemu/roms/u-boot/board/LaCie/common/common.h b/qemu/roms/u-boot/board/LaCie/common/common.h deleted file mode 100644 index c24e5885d..000000000 --- a/qemu/roms/u-boot/board/LaCie/common/common.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _LACIE_COMMON_H -#define _LACIE_COMMON_H - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) -void mv_phy_88e1116_init(const char *name, u16 phyaddr); -void mv_phy_88e1318_init(const char *name, u16 phyaddr); -#endif -#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) -int lacie_read_mac_address(uchar *mac); -#endif - -#endif /* _LACIE_COMMON_H */ diff --git a/qemu/roms/u-boot/board/LaCie/common/cpld-gpio-bus.c b/qemu/roms/u-boot/board/LaCie/common/cpld-gpio-bus.c deleted file mode 100644 index 9b24dc535..000000000 --- a/qemu/roms/u-boot/board/LaCie/common/cpld-gpio-bus.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * cpld-gpio-bus.c: provides support for the CPLD GPIO bus found on some LaCie - * boards (as the 2Big/5Big Network v2 and the 2Big NAS). This parallel GPIO - * bus exposes two registers (address and data). Each of this register is made - * up of several dedicated GPIOs. An extra GPIO is used to notify the CPLD that - * the registers have been updated. - * - * Mostly this bus is used to configure the LEDs on LaCie boards. - * - * Copyright (C) 2013 Simon Guinot <simon.guinot@sequanux.org> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm/arch/gpio.h> -#include "cpld-gpio-bus.h" - -static void cpld_gpio_bus_set_addr(struct cpld_gpio_bus *bus, unsigned addr) -{ - int pin; - - for (pin = 0; pin < bus->num_addr; pin++) - kw_gpio_set_value(bus->addr[pin], (addr >> pin) & 1); -} - -static void cpld_gpio_bus_set_data(struct cpld_gpio_bus *bus, unsigned data) -{ - int pin; - - for (pin = 0; pin < bus->num_data; pin++) - kw_gpio_set_value(bus->data[pin], (data >> pin) & 1); -} - -static void cpld_gpio_bus_enable_select(struct cpld_gpio_bus *bus) -{ - /* The transfer is enabled on the raising edge. */ - kw_gpio_set_value(bus->enable, 0); - kw_gpio_set_value(bus->enable, 1); -} - -void cpld_gpio_bus_write(struct cpld_gpio_bus *bus, - unsigned addr, unsigned value) -{ - cpld_gpio_bus_set_addr(bus, addr); - cpld_gpio_bus_set_data(bus, value); - cpld_gpio_bus_enable_select(bus); -} diff --git a/qemu/roms/u-boot/board/LaCie/common/cpld-gpio-bus.h b/qemu/roms/u-boot/board/LaCie/common/cpld-gpio-bus.h deleted file mode 100644 index 3dfac0b5a..000000000 --- a/qemu/roms/u-boot/board/LaCie/common/cpld-gpio-bus.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2013 Simon Guinot <simon.guinot@sequanux.org> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _LACIE_CPLD_GPI0_BUS_H -#define _LACIE_CPLD_GPI0_BUS_H - -struct cpld_gpio_bus { - unsigned *addr; - unsigned num_addr; - unsigned *data; - unsigned num_data; - unsigned enable; -}; - -void cpld_gpio_bus_write(struct cpld_gpio_bus *cpld_gpio_bus, - unsigned addr, unsigned value); - -#endif /* _LACIE_CPLD_GPI0_BUS_H */ diff --git a/qemu/roms/u-boot/board/LaCie/edminiv2/Makefile b/qemu/roms/u-boot/board/LaCie/edminiv2/Makefile deleted file mode 100644 index 035f6865d..000000000 --- a/qemu/roms/u-boot/board/LaCie/edminiv2/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> -# -# Based on original Kirkwood support which is -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := edminiv2.o ../common/common.o diff --git a/qemu/roms/u-boot/board/LaCie/edminiv2/config.mk b/qemu/roms/u-boot/board/LaCie/edminiv2/config.mk deleted file mode 100644 index dfa84f032..000000000 --- a/qemu/roms/u-boot/board/LaCie/edminiv2/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# TEXT_BASE must equal the intended FLASH location of u-boot. -CONFIG_SYS_TEXT_BASE = 0xfff90000 diff --git a/qemu/roms/u-boot/board/LaCie/edminiv2/edminiv2.c b/qemu/roms/u-boot/board/LaCie/edminiv2/edminiv2.c deleted file mode 100644 index 80ec7faa0..000000000 --- a/qemu/roms/u-boot/board/LaCie/edminiv2/edminiv2.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> - * - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <miiphy.h> -#include <asm/arch/orion5x.h> -#include "../common/common.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH - * which CFI does not properly detect, hence the LEGACY config. - */ -#if defined(CONFIG_FLASH_CFI_LEGACY) -#include <flash.h> -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{ - int sectsz[] = CONFIG_SYS_FLASH_SECTSZ; - int sect; - - if (base != CONFIG_SYS_FLASH_BASE) - return 0; - - info->size = 0; - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - /* set each sector's start address and size based */ - for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) { - info->start[sect] = base+info->size; - info->size += sectsz[sect]; - } - /* This flash must be accessed in 8-bits mode, no buffer. */ - info->flash_id = 0x01000000; - info->portwidth = FLASH_CFI_8BIT; - info->chipwidth = FLASH_CFI_BY8; - info->buffer_size = 0; - /* timings are derived from the Macronix datasheet. */ - info->erase_blk_tout = 1000; - info->write_tout = 10; - info->buffer_write_tout = 300; - /* Commands and addresses are for AMD mode 8-bit access. */ - info->vendor = CFI_CMDSET_AMD_LEGACY; - info->cmd_reset = 0xF0; - info->interface = FLASH_CFI_X8; - info->legacy_unlock = 0; - info->ext_addr = 0; - info->addr_unlock1 = 0x00000aaa; - info->addr_unlock2 = 0x00000555; - /* Manufacturer Macronix, device MX29LV400CB, CFI 1.3. */ - info->manufacturer_id = 0x22; - info->device_id = 0xBA; - info->device_id2 = 0; - info->cfi_version = 0x3133; - info->cfi_offset = 0x0000; - info->name = "MX29LV400CB"; - - return 1; -} -#endif /* CONFIG_SYS_FLASH_CFI */ - -int board_init(void) -{ - /* arch number of board */ - gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2; - - /* boot parameter start at 256th byte of RAM base */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; - - return 0; -} - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) -/* Configure and enable MV88E1116 PHY */ -void reset_phy(void) -{ - mv_phy_88e1116_init("egiga0", 8); -} -#endif /* CONFIG_RESET_PHY_R */ diff --git a/qemu/roms/u-boot/board/LaCie/net2big_v2/Makefile b/qemu/roms/u-boot/board/LaCie/net2big_v2/Makefile deleted file mode 100644 index f3074af25..000000000 --- a/qemu/roms/u-boot/board/LaCie/net2big_v2/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> -# -# Based on Kirkwood support: -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := net2big_v2.o ../common/common.o -ifneq ($(and $(CONFIG_KIRKWOOD_GPIO),$(CONFIG_NET2BIG_V2)),) -obj-y += ../common/cpld-gpio-bus.o -endif diff --git a/qemu/roms/u-boot/board/LaCie/net2big_v2/kwbimage.cfg b/qemu/roms/u-boot/board/LaCie/net2big_v2/kwbimage.cfg deleted file mode 100644 index 453fcb2a2..000000000 --- a/qemu/roms/u-boot/board/LaCie/net2big_v2/kwbimage.cfg +++ /dev/null @@ -1,151 +0,0 @@ -# -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> -# -# Based on Kirkwood support: -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM spi # Boot from SPI flash - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Configure RGMII-0 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1B1B1B9B - -#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000C30 # DDR Configuration register -# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01 - -DATA 0xFFD01404 0x38743000 # DDR Controller Control Low -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay - -DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP - -DATA 0xFFD0140C 0x00000A32 # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required - -DATA 0xFFD01410 0x0000CCCC # DDR Address Control -# bit1-0: 01, Cs0width=x16 -# bit3-2: 11, Cs0size=1Gb -# bit5-4: 00, Cs2width=nonexistent -# bit7-6: 00, Cs1size =nonexistent -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required - -DATA 0xFFD0141C 0x00000662 # DDR Mode -# bit2-0: 2, BurstLen=2 required -# bit3: 0, BurstType=0 required -# bit6-4: 4, CL=5 -# bit7: 0, TestMode=0 normal -# bit8: 0, DLL reset=0 normal -# bit11-9: 6, auto-precharge write recovery ???????????? -# bit12: 0, PD must be zero -# bit31-13: 0 required - -DATA 0xFFD01420 0x00000044 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 1, DDR drive strenght reduced -# bit2: 1, DDR ODT control lsd enabled -# bit5-3: 000, required -# bit6: 1, DDR ODT control msb, enabled -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required - -DATA 0xFFD01424 0x0000F17F # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 1 , D2P Latency enabled -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required - -DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values) -DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values) - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x07, Size (i.e. 128MB) - -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) -# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 -# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 - -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above -# bit3-2: 01, ODT1 active NEVER! -# bit31-4: zero, required - -DATA 0xFFD0149C 0x0000E40F # CPU ODT Control -# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 -# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0 -# bit11-10:1, DQ_ODTSel. ODT select turned on - -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -#bit0=1, enable DDR init upon this register write - -# End of Header extension -DATA 0x0 0x0 diff --git a/qemu/roms/u-boot/board/LaCie/net2big_v2/net2big_v2.c b/qemu/roms/u-boot/board/LaCie/net2big_v2/net2big_v2.c deleted file mode 100644 index 4c3a9ba78..000000000 --- a/qemu/roms/u-boot/board/LaCie/net2big_v2/net2big_v2.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> - * - * Based on Kirkwood support: - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <i2c.h> -#include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> -#include <asm/arch/mpp.h> -#include <asm/arch/gpio.h> - -#include "net2big_v2.h" -#include "../common/common.h" -#include "../common/cpld-gpio-bus.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* GPIO configuration */ - kw_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH, - NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH); - - /* Multi-Purpose Pins Functionality configuration */ - static const u32 kwmpp_config[] = { - MPP0_SPI_SCn, - MPP1_SPI_MOSI, - MPP2_SPI_SCK, - MPP3_SPI_MISO, - MPP6_SYSRST_OUTn, - MPP7_GPO, /* Request power-off */ - MPP8_TW_SDA, - MPP9_TW_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP13_GPIO, /* Rear power switch (on|auto) */ - MPP14_GPIO, /* USB fuse alarm */ - MPP15_GPIO, /* Rear power switch (auto|off) */ - MPP16_GPIO, /* SATA HDD1 power */ - MPP17_GPIO, /* SATA HDD2 power */ - MPP20_SATA1_ACTn, - MPP21_SATA0_ACTn, - MPP24_GPIO, /* USB mode select */ - MPP26_GPIO, /* USB device vbus */ - MPP28_GPIO, /* USB enable host vbus */ - MPP29_GPIO, /* CPLD GPIO bus ALE */ - MPP34_GPIO, /* Rear Push button 0=on 1=off */ - MPP35_GPIO, /* Inhibit switch power-off */ - MPP36_GPIO, /* SATA HDD1 presence */ - MPP37_GPIO, /* SATA HDD2 presence */ - MPP40_GPIO, /* eSATA presence */ - MPP44_GPIO, /* CPLD GPIO bus (data 0) */ - MPP45_GPIO, /* CPLD GPIO bus (data 1) */ - MPP46_GPIO, /* CPLD GPIO bus (data 2) */ - MPP47_GPIO, /* CPLD GPIO bus (addr 0) */ - MPP48_GPIO, /* CPLD GPIO bus (addr 1) */ - MPP49_GPIO, /* CPLD GPIO bus (addr 2) */ - 0 - }; - - kirkwood_mpp_conf(kwmpp_config, NULL); - - return 0; -} - -int board_init(void) -{ - /* Machine number */ - gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2; - - /* Boot parameters address */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; - - return 0; -} - -#if defined(CONFIG_MISC_INIT_R) - -#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_G762_ADDR) -/* - * Start I2C fan (GMT G762 controller) - */ -static void init_fan(void) -{ - u8 data; - - i2c_set_bus_num(0); - - /* Enable open-loop and PWM modes */ - data = 0x20; - if (i2c_write(CONFIG_SYS_I2C_G762_ADDR, - G762_REG_FAN_CMD1, 1, &data, 1) != 0) - goto err; - data = 0; - if (i2c_write(CONFIG_SYS_I2C_G762_ADDR, - G762_REG_SET_CNT, 1, &data, 1) != 0) - goto err; - /* - * RPM to PWM (set_out register) fan speed conversion array: - * 0 0x00 - * 1500 0x04 - * 2800 0x08 - * 3400 0x0C - * 3700 0x10 - * 4400 0x20 - * 4700 0x30 - * 4800 0x50 - * 5200 0x80 - * 5400 0xC0 - * 5500 0xFF - * - * Start fan at low speed (2800 RPM): - */ - data = 0x08; - if (i2c_write(CONFIG_SYS_I2C_G762_ADDR, - G762_REG_SET_OUT, 1, &data, 1) != 0) - goto err; - - return; -err: - printf("Error: failed to start I2C fan @%02x\n", - CONFIG_SYS_I2C_G762_ADDR); -} -#else -static void init_fan(void) {} -#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_G762_ADDR */ - -#if defined(CONFIG_NET2BIG_V2) && defined(CONFIG_KIRKWOOD_GPIO) -/* - * CPLD GPIO bus: - * - * - address register : bit [0-2] -> GPIO [47-49] - * - data register : bit [0-2] -> GPIO [44-46] - * - enable register : GPIO 29 - */ -static unsigned cpld_gpio_bus_addr[] = { 47, 48, 49 }; -static unsigned cpld_gpio_bus_data[] = { 44, 45, 46 }; - -static struct cpld_gpio_bus cpld_gpio_bus = { - .addr = cpld_gpio_bus_addr, - .num_addr = ARRAY_SIZE(cpld_gpio_bus_addr), - .data = cpld_gpio_bus_data, - .num_data = ARRAY_SIZE(cpld_gpio_bus_data), - .enable = 29, -}; - -/* - * LEDs configuration: - * - * The LEDs are controlled by a CPLD and can be configured through - * the CPLD GPIO bus. - * - * Address register selection: - * - * addr | register - * ---------------------------- - * 0 | front LED - * 1 | front LED brightness - * 2 | SATA LED brightness - * 3 | SATA0 LED - * 4 | SATA1 LED - * 5 | SATA2 LED - * 6 | SATA3 LED - * 7 | SATA4 LED - * - * Data register configuration: - * - * data | LED brightness - * ------------------------------------------------- - * 0 | min (off) - * - | - - * 7 | max - * - * data | front LED mode - * ------------------------------------------------- - * 0 | fix off - * 1 | fix blue on - * 2 | fix red on - * 3 | blink blue on=1 sec and blue off=1 sec - * 4 | blink red on=1 sec and red off=1 sec - * 5 | blink blue on=2.5 sec and red on=0.5 sec - * 6 | blink blue on=1 sec and red on=1 sec - * 7 | blink blue on=0.5 sec and blue off=2.5 sec - * - * data | SATA LED mode - * ------------------------------------------------- - * 0 | fix off - * 1 | SATA activity blink - * 2 | fix red on - * 3 | blink blue on=1 sec and blue off=1 sec - * 4 | blink red on=1 sec and red off=1 sec - * 5 | blink blue on=2.5 sec and red on=0.5 sec - * 6 | blink blue on=1 sec and red on=1 sec - * 7 | fix blue on - */ -static void init_leds(void) -{ - /* Enable the front blue LED */ - cpld_gpio_bus_write(&cpld_gpio_bus, 0, 1); - cpld_gpio_bus_write(&cpld_gpio_bus, 1, 3); - - /* Configure SATA LEDs to blink in relation with the SATA activity */ - cpld_gpio_bus_write(&cpld_gpio_bus, 3, 1); - cpld_gpio_bus_write(&cpld_gpio_bus, 4, 1); - cpld_gpio_bus_write(&cpld_gpio_bus, 2, 3); -} -#else -static void init_leds(void) {} -#endif /* CONFIG_NET2BIG_V2 && CONFIG_KIRKWOOD_GPIO */ - -int misc_init_r(void) -{ - init_fan(); -#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) - if (!getenv("ethaddr")) { - uchar mac[6]; - if (lacie_read_mac_address(mac) == 0) - eth_setenv_enetaddr("ethaddr", mac); - } -#endif - init_leds(); - - return 0; -} -#endif /* CONFIG_MISC_INIT_R */ - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) -/* Configure and initialize PHY */ -void reset_phy(void) -{ - mv_phy_88e1116_init("egiga0", 8); -} -#endif - -#if defined(CONFIG_KIRKWOOD_GPIO) -/* Return GPIO push button status */ -static int -do_read_push_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - return !kw_gpio_get_value(NET2BIG_V2_GPIO_PUSH_BUTTON); -} - -U_BOOT_CMD(button, 1, 1, do_read_push_button, - "Return GPIO push button status 0=off 1=on", ""); -#endif diff --git a/qemu/roms/u-boot/board/LaCie/net2big_v2/net2big_v2.h b/qemu/roms/u-boot/board/LaCie/net2big_v2/net2big_v2.h deleted file mode 100644 index 8dead8914..000000000 --- a/qemu/roms/u-boot/board/LaCie/net2big_v2/net2big_v2.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> - * - * Based on Kirkwood support: - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef NET2BIG_V2_H -#define NET2BIG_V2_H - -/* GPIO configuration */ -#define NET2BIG_V2_OE_LOW 0x0600E000 -#define NET2BIG_V2_OE_HIGH 0x00000134 -#define NET2BIG_V2_OE_VAL_LOW 0x10030000 -#define NET2BIG_V2_OE_VAL_HIGH 0x00000000 - -/* Buttons */ -#define NET2BIG_V2_GPIO_PUSH_BUTTON 34 - -/* GMT G762 registers (I2C fan controller) */ -#define G762_REG_SET_CNT 0x00 -#define G762_REG_SET_OUT 0x03 -#define G762_REG_FAN_CMD1 0x04 - -#endif /* NET2BIG_V2_H */ diff --git a/qemu/roms/u-boot/board/LaCie/netspace_v2/Makefile b/qemu/roms/u-boot/board/LaCie/netspace_v2/Makefile deleted file mode 100644 index 47778d847..000000000 --- a/qemu/roms/u-boot/board/LaCie/netspace_v2/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> -# -# Based on Kirkwood support: -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := netspace_v2.o ../common/common.o diff --git a/qemu/roms/u-boot/board/LaCie/netspace_v2/kwbimage-is2.cfg b/qemu/roms/u-boot/board/LaCie/netspace_v2/kwbimage-is2.cfg deleted file mode 100644 index 98713ea0e..000000000 --- a/qemu/roms/u-boot/board/LaCie/netspace_v2/kwbimage-is2.cfg +++ /dev/null @@ -1,151 +0,0 @@ -# -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> -# -# Based on Kirkwood support: -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM spi # Boot from SPI flash - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Configure RGMII-0 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1B1B1B9B - -#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000618 # DDR Configuration register -# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01 - -DATA 0xFFD01404 0x35143000 # DDR Controller Control Low -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay - -DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP - -DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required - -DATA 0xFFD01410 0x00000008 # DDR Address Control -# bit1-0: 00, Cs0width=x8 -# bit3-2: 10, Cs0size=512Mb -# bit5-4: 00, Cs2width=nonexistent -# bit7-6: 00, Cs1size =nonexistent -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required - -DATA 0xFFD0141C 0x00000632 # DDR Mode -# bit2-0: 2, BurstLen=2 required -# bit3: 0, BurstType=0 required -# bit6-4: 4, CL=5 -# bit7: 0, TestMode=0 normal -# bit8: 0, DLL reset=0 normal -# bit11-9: 6, auto-precharge write recovery ???????????? -# bit12: 0, PD must be zero -# bit31-13: 0 required - -DATA 0xFFD01420 0x00000004 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 1, DDR drive strenght reduced -# bit2: 1, DDR ODT control lsd enabled -# bit5-3: 000, required -# bit6: 1, DDR ODT control msb, enabled -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required - -DATA 0xFFD01424 0x0000F07F # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 1 , D2P Latency enabled -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required - -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x07, Size (i.e. 128MB) - -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) -# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 -# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 - -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above -# bit3-2: 01, ODT1 active NEVER! -# bit31-4: zero, required - -DATA 0xFFD0149C 0x0000E40F # CPU ODT Control -# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 -# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0 -# bit11-10:1, DQ_ODTSel. ODT select turned on - -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -#bit0=1, enable DDR init upon this register write - -# End of Header extension -DATA 0x0 0x0 diff --git a/qemu/roms/u-boot/board/LaCie/netspace_v2/kwbimage-ns2l.cfg b/qemu/roms/u-boot/board/LaCie/netspace_v2/kwbimage-ns2l.cfg deleted file mode 100644 index 6b321937d..000000000 --- a/qemu/roms/u-boot/board/LaCie/netspace_v2/kwbimage-ns2l.cfg +++ /dev/null @@ -1,151 +0,0 @@ -# -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> -# -# Based on Kirkwood support: -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM spi # Boot from SPI flash - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Configure RGMII-0 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1B1B1B9B - -#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000618 # DDR Configuration register -# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01 - -DATA 0xFFD01404 0x34143000 # DDR Controller Control Low -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay - -DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP - -DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required - -DATA 0xFFD01410 0x0000DDDD # DDR Address Control -# bit1-0: 00, Cs0width=x8 -# bit3-2: 10, Cs0size=512Mb -# bit5-4: 00, Cs2width=nonexistent -# bit7-6: 00, Cs1size =nonexistent -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required - -DATA 0xFFD0141C 0x00000632 # DDR Mode -# bit2-0: 2, BurstLen=2 required -# bit3: 0, BurstType=0 required -# bit6-4: 4, CL=5 -# bit7: 0, TestMode=0 normal -# bit8: 0, DLL reset=0 normal -# bit11-9: 6, auto-precharge write recovery ???????????? -# bit12: 0, PD must be zero -# bit31-13: 0 required - -DATA 0xFFD01420 0x00000004 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 1, DDR drive strenght reduced -# bit2: 1, DDR ODT control lsd enabled -# bit5-3: 000, required -# bit6: 1, DDR ODT control msb, enabled -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required - -DATA 0xFFD01424 0x0000F07F # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 1 , D2P Latency enabled -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required - -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x07, Size (i.e. 128MB) - -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) -# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 -# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 - -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above -# bit3-2: 01, ODT1 active NEVER! -# bit31-4: zero, required - -DATA 0xFFD0149C 0x0000E40F # CPU ODT Control -# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 -# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0 -# bit11-10:1, DQ_ODTSel. ODT select turned on - -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -#bit0=1, enable DDR init upon this register write - -# End of Header extension -DATA 0x0 0x0 diff --git a/qemu/roms/u-boot/board/LaCie/netspace_v2/kwbimage.cfg b/qemu/roms/u-boot/board/LaCie/netspace_v2/kwbimage.cfg deleted file mode 100644 index 1515f8151..000000000 --- a/qemu/roms/u-boot/board/LaCie/netspace_v2/kwbimage.cfg +++ /dev/null @@ -1,151 +0,0 @@ -# -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> -# -# Based on Kirkwood support: -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM spi # Boot from SPI flash - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Configure RGMII-0 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1B1B1B9B - -#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000618 # DDR Configuration register -# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01 - -DATA 0xFFD01404 0x35143000 # DDR Controller Control Low -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay - -DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP - -DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required - -DATA 0xFFD01410 0x0000000C # DDR Address Control -# bit1-0: 00, Cs0width=x8 -# bit3-2: 11, Cs0size=1Gb -# bit5-4: 00, Cs2width=nonexistent -# bit7-6: 00, Cs1size =nonexistent -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required - -DATA 0xFFD0141C 0x00000632 # DDR Mode -# bit2-0: 2, BurstLen=2 required -# bit3: 0, BurstType=0 required -# bit6-4: 4, CL=5 -# bit7: 0, TestMode=0 normal -# bit8: 0, DLL reset=0 normal -# bit11-9: 6, auto-precharge write recovery ???????????? -# bit12: 0, PD must be zero -# bit31-13: 0 required - -DATA 0xFFD01420 0x00000004 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 1, DDR drive strenght reduced -# bit2: 1, DDR ODT control lsd enabled -# bit5-3: 000, required -# bit6: 1, DDR ODT control msb, enabled -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required - -DATA 0xFFD01424 0x0000F07F # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 1 , D2P Latency enabled -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required - -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x07, Size (i.e. 128MB) - -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) -# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 -# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 - -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above -# bit3-2: 01, ODT1 active NEVER! -# bit31-4: zero, required - -DATA 0xFFD0149C 0x0000E40F # CPU ODT Control -# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 -# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0 -# bit11-10:1, DQ_ODTSel. ODT select turned on - -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -#bit0=1, enable DDR init upon this register write - -# End of Header extension -DATA 0x0 0x0 diff --git a/qemu/roms/u-boot/board/LaCie/netspace_v2/netspace_v2.c b/qemu/roms/u-boot/board/LaCie/netspace_v2/netspace_v2.c deleted file mode 100644 index 3773587cc..000000000 --- a/qemu/roms/u-boot/board/LaCie/netspace_v2/netspace_v2.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> - * - * Based on Kirkwood support: - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> -#include <asm/arch/mpp.h> -#include <asm/arch/gpio.h> - -#include "netspace_v2.h" -#include "../common/common.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /* Gpio configuration */ - kw_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH, - NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH); - - /* Multi-Purpose Pins Functionality configuration */ - static const u32 kwmpp_config[] = { - MPP0_SPI_SCn, - MPP1_SPI_MOSI, - MPP2_SPI_SCK, - MPP3_SPI_MISO, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP6_SYSRST_OUTn, - MPP7_GPO, /* Fan speed (bit 1) */ - MPP8_TW_SDA, - MPP9_TW_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_GPO, /* Red led */ - MPP14_GPIO, /* USB fuse */ - MPP16_GPIO, /* SATA 0 power */ - MPP17_GPIO, /* SATA 1 power */ - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP20_SATA1_ACTn, - MPP21_SATA0_ACTn, - MPP22_GPIO, /* Fan speed (bit 0) */ - MPP23_GPIO, /* Fan power */ - MPP24_GPIO, /* USB mode select */ - MPP25_GPIO, /* Fan rotation fail */ - MPP26_GPIO, /* USB vbus-in detection */ - MPP28_GPIO, /* USB enable vbus-out */ - MPP29_GPIO, /* Blue led (slow register) */ - MPP30_GPIO, /* Blue led (command register) */ - MPP31_GPIO, /* Board power off */ - MPP32_GPIO, /* Button (0 = Released, 1 = Pushed) */ - MPP33_GPIO, /* Fan speed (bit 2) */ - 0 - }; - kirkwood_mpp_conf(kwmpp_config, NULL); - - return 0; -} - -int board_init(void) -{ - /* Machine number */ - gd->bd->bi_arch_number = CONFIG_MACH_TYPE; - - /* Boot parameters address */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; - - return 0; -} - -#if defined(CONFIG_MISC_INIT_R) -int misc_init_r(void) -{ -#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) - if (!getenv("ethaddr")) { - uchar mac[6]; - if (lacie_read_mac_address(mac) == 0) - eth_setenv_enetaddr("ethaddr", mac); - } -#endif - return 0; -} -#endif - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) -/* Configure and initialize PHY */ -void reset_phy(void) -{ -#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2) - mv_phy_88e1318_init("egiga0", 0); -#else - mv_phy_88e1116_init("egiga0", 8); -#endif -} -#endif - -#if defined(CONFIG_KIRKWOOD_GPIO) -/* Return GPIO button status */ -static int -do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - return kw_gpio_get_value(NETSPACE_V2_GPIO_BUTTON); -} - -U_BOOT_CMD(button, 1, 1, do_read_button, - "Return GPIO button status 0=off 1=on", ""); -#endif diff --git a/qemu/roms/u-boot/board/LaCie/netspace_v2/netspace_v2.h b/qemu/roms/u-boot/board/LaCie/netspace_v2/netspace_v2.h deleted file mode 100644 index cdf5238f7..000000000 --- a/qemu/roms/u-boot/board/LaCie/netspace_v2/netspace_v2.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> - * - * Based on Kirkwood support: - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef NETSPACE_V2_H -#define NETSPACE_V2_H - -/* GPIO configuration */ -#define NETSPACE_V2_OE_LOW 0x06004000 -#define NETSPACE_V2_OE_HIGH 0x00000031 -#define NETSPACE_V2_OE_VAL_LOW 0x10030000 -#define NETSPACE_V2_OE_VAL_HIGH 0x00000000 - -#define NETSPACE_V2_GPIO_BUTTON 32 - -#endif /* NETSPACE_V2_H */ diff --git a/qemu/roms/u-boot/board/LaCie/wireless_space/Makefile b/qemu/roms/u-boot/board/LaCie/wireless_space/Makefile deleted file mode 100644 index 90a84f489..000000000 --- a/qemu/roms/u-boot/board/LaCie/wireless_space/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> -# -# Based on Kirkwood support: -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := wireless_space.o ../common/common.o diff --git a/qemu/roms/u-boot/board/LaCie/wireless_space/kwbimage.cfg b/qemu/roms/u-boot/board/LaCie/wireless_space/kwbimage.cfg deleted file mode 100644 index 037248b3c..000000000 --- a/qemu/roms/u-boot/board/LaCie/wireless_space/kwbimage.cfg +++ /dev/null @@ -1,71 +0,0 @@ -# -# Copyright (C) 2012 Albert ARIBAUD <albert.u.boot@aribaud.net> -# -# Based on netspace_v2 kwbimage.cfg: -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> -# -# Based on Kirkwood support: -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM nand # Boot from NAND flash -NAND_PAGE_SIZE 800 - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Values taken from image original LaCie U-Boot header dump! - -# Configure RGMII-0 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1B1B1B9B - -#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000c30 # DDR Configuration register - -DATA 0xFFD01404 0x37743000 # DDR Controller Control Low - -DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) - -DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) - -DATA 0xFFD01410 0x0000CCCC # DDR Address Control - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control - -DATA 0xFFD01418 0x00000000 # DDR Operation - -DATA 0xFFD0141C 0x00000662 # DDR Mode - -DATA 0xFFD01420 0x00000004 # DDR Extended Mode - -DATA 0xFFD01424 0x0000F07F # DDR Controller Control High - -DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values) - -DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values) - -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size -DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0 -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled -DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -DATA 0xFFD0149C 0x0000E40F # CPU ODT Control -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -DATA 0xFFD20134 0x66666666 -DATA 0xFFD20138 0x66666666 -DATA 0xFFD10000 0x01112222 -DATA 0xFFD1000C 0x00000000 -DATA 0xFFD10104 0x00000000 -DATA 0xFFD10100 0x40000000 -# End of Header extension -DATA 0x0 0x0 diff --git a/qemu/roms/u-boot/board/LaCie/wireless_space/wireless_space.c b/qemu/roms/u-boot/board/LaCie/wireless_space/wireless_space.c deleted file mode 100644 index 2dc501856..000000000 --- a/qemu/roms/u-boot/board/LaCie/wireless_space/wireless_space.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> - * - * Based on Kirkwood support: - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/arch/cpu.h> -#include <asm/arch/kirkwood.h> -#include <asm/arch/mpp.h> -#include <asm/arch/gpio.h> - -#include "../common/common.h" -#include "netdev.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* GPIO configuration: start FAN at low speed, USB and HDD */ - -#define WIRELESS_SPACE_OE_LOW 0xFF006808 -#define WIRELESS_SPACE_OE_HIGH 0x0000F989 -#define WIRELESS_SPACE_OE_VAL_LOW 0x00010080 -#define WIRELESS_SPACE_OE_VAL_HIGH 0x00000240 - -#define WIRELESS_SPACE_REAR_BUTTON 13 -#define WIRELESS_SPACE_FRONT_BUTTON 43 - -const u32 kwmpp_config[] = { - MPP0_NF_IO2, - MPP1_NF_IO3, - MPP2_NF_IO4, - MPP3_NF_IO5, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP6_SYSRST_OUTn, - MPP7_GPO, /* Fan speed (bit 1) */ - MPP8_TW_SDA, - MPP9_TW_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP13_GPIO, /* Red led */ - MPP14_GPIO, /* USB fuse */ - MPP15_SATA0_ACTn, - MPP16_GPIO, /* SATA 0 power */ - MPP17_GPIO, /* SATA 1 power */ - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP20_GE1_0, /* Gigabit Ethernet 1 */ - MPP21_GE1_1, - MPP22_GE1_2, - MPP23_GE1_3, - MPP24_GE1_4, - MPP25_GE1_5, - MPP26_GE1_6, - MPP27_GE1_7, - MPP28_GE1_8, - MPP29_GE1_9, - MPP30_GE1_10, - MPP31_GE1_11, - MPP32_GE1_12, - MPP33_GE1_13, - MPP34_GE1_14, - MPP35_GE1_15, - MPP36_GPIO, /* Fan speed (bit 2) */ - MPP37_GPIO, /* Fan speed (bit 0) */ - MPP38_GPIO, /* Fan power */ - MPP39_GPIO, /* Fan rotation fail */ - MPP40_GPIO, /* Ethernet switch link */ - MPP41_GPIO, /* USB enable host vbus */ - MPP42_GPIO, /* LED clock control */ - MPP43_GPIO, /* WPS button (0=Pushed, 1=Released) */ - MPP44_GPIO, /* Red LED on/off */ - MPP45_GPIO, /* Red LED timer blink (on=off=100ms) */ - MPP46_GPIO, /* Green LED on/off */ - MPP47_GPIO, /* LED (blue, green) SATA activity blink */ - MPP48_GPIO, /* Blue LED on/off */ - 0 -}; - -struct mv88e61xx_config swcfg = { - .name = "egiga0", - .vlancfg = MV88E61XX_VLANCFG_ROUTER, - .rgmii_delay = MV88E61XX_RGMII_DELAY_EN, - .led_init = MV88E61XX_LED_INIT_EN, - .mdip = MV88E61XX_MDIP_NOCHANGE, - .portstate = MV88E61XX_PORTSTT_FORWARDING, - .cpuport = 0x20, - .ports_enabled = 0x3F, -}; - -int board_early_init_f(void) -{ - /* Gpio configuration */ - kw_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH, - WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH); - - /* Multi-Purpose Pins Functionality configuration */ - kirkwood_mpp_conf(kwmpp_config, NULL); - - return 0; -} - -int board_init(void) -{ - /* Machine number */ - gd->bd->bi_arch_number = CONFIG_MACH_TYPE; - - /* Boot parameters address */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; - - return 0; -} - -#if defined(CONFIG_MISC_INIT_R) -int misc_init_r(void) -{ -#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) - if (!getenv("ethaddr")) { - uchar mac[6]; - if (lacie_read_mac_address(mac) == 0) - eth_setenv_enetaddr("ethaddr", mac); - } -#endif - return 0; -} -#endif - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) -/* Configure and initialize PHY */ -void reset_phy(void) -{ - /* configure switch on egiga0 */ - mv88e61xx_switch_initialize(&swcfg); -} -#endif - -#if defined(CONFIG_KIRKWOOD_GPIO) && defined(CONFIG_WIRELESS_SPACE_CMD) -/* Return GPIO button status */ -static int -do_ws(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (strcmp(argv[1], "button") == 0) { - if (strcmp(argv[2], "rear") == 0) - /* invert GPIO result for intuitive while/until use */ - return !kw_gpio_get_value(WIRELESS_SPACE_REAR_BUTTON); - else if (strcmp(argv[2], "front") == 0) - return kw_gpio_get_value(WIRELESS_SPACE_FRONT_BUTTON); - else - return -1; - } else { - return -1; - } -} - -U_BOOT_CMD(ws, 3, 0, do_ws, - "Return GPIO button status 0=off 1=on", - "- ws button rear|front: test buttons' states\n" -); -#endif |