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diff --git a/qemu/roms/u-boot/board/AndesTech/adp-ag101/Makefile b/qemu/roms/u-boot/board/AndesTech/adp-ag101/Makefile
new file mode 100644
index 000000000..4cc590ff2
--- /dev/null
+++ b/qemu/roms/u-boot/board/AndesTech/adp-ag101/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= adp-ag101.o
diff --git a/qemu/roms/u-boot/board/AndesTech/adp-ag101/README b/qemu/roms/u-boot/board/AndesTech/adp-ag101/README
new file mode 100644
index 000000000..46fc63774
--- /dev/null
+++ b/qemu/roms/u-boot/board/AndesTech/adp-ag101/README
@@ -0,0 +1,74 @@
+Andes Technology SoC AG101
+==========================
+
+AG101 is the first SoC produced by Andes Technology using N1213 CPU core.
+AG101 has integrated both AHB and APB bus and many periphals for application
+and product development.
+
+ADP-AG101
+=========
+
+ADP-AG101 is the SoC with AG101 hardcore CPU.
+
+Please check http://www.andestech.com/p2-4.htm for detail of this SoC.
+
+Configurations
+==============
+
+CONFIG_MEM_REMAP:
+	Doing memory remap is essential for preparing some non-OS or RTOS
+	applications.
+
+	This is also a must on ADP-AG101 board.
+	(While other boards may not have this problem).
+
+	The reason is because the ROM/FLASH circuit on PCB board.
+	AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
+	ROM/FLASH is used to boot.
+
+	When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
+	and the FLASH is connected to BANK1.
+	When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
+	and the FLASH is connected to BANK0.
+	It will occur problem when doing flash probing if the flash is at
+	BANK0 (0x00000000) while memory remapping was skipped.
+
+	Other board like ADP-AG101P may not enable this since there is only
+	a FLASH connected to bank0.
+
+CONFIG_SKIP_LOWLEVEL_INIT:
+	If you want to boot this system from FLASH and bypass e-bios (the
+	other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
+	in "include/configs/adp-ag101.h".
+
+Build and boot steps
+====================
+
+build:
+1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
+2. Use `make adp-ag101` in u-boot root to build the image.
+
+burn u-boot to flash:
+1. Make sure the MA17 (J16) is Lo.
+2. Make sure the dip switch SW5 is set to "0101".
+3. Power On. Press button "S1", then press button "SW1", then you will found the
+   debug LED show 67 means the system successfully booted into e-bios.
+   Now you can control the e-bios boot loader from your console.
+4. Under "Command>>" prompt, enter "97" (CopyImageFromCard)
+5. Under "Type Dir Name of [CF/SD] =>" promtp, enter "c".
+6. Under "Enter Filename =>" prompt, enter the file name of u-boot image you
+   just build. It is usually "u-boot.bin".
+7. Under "Enter Dest. Address =>" prompt, enter the memory address where you
+   want to put the binary from SD card to RAM.
+   Address "0x500000" is our suggestion.
+8. Under "Command>>" prompt again, enter "55" (CLI) to use interactive command
+   environment.
+9. Under "CLI>" prompt, enter "burn 0x500000 0x80400000 0x30000" to burn the
+   binary from RAM to FLASH.
+10. Under "CLI>" prompt, enter "exit" to finish the burn process.
+
+boot u-boot from flash:
+1. Make sure the MA17 (J16) is Hi).
+2. Make sure the dip switch SW5 is set to "1010".
+3. Power On. Press button "S1", then you will see the debug LED count to 20.
+4. Now you can use u-boot on ADP-AG101 board.
diff --git a/qemu/roms/u-boot/board/AndesTech/adp-ag101/adp-ag101.c b/qemu/roms/u-boot/board/AndesTech/adp-ag101/adp-ag101.c
new file mode 100644
index 000000000..9884a5b52
--- /dev/null
+++ b/qemu/roms/u-boot/board/AndesTech/adp-ag101/adp-ag101.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftsdc010.h>
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+	/*
+	 * refer to BOOT_PARAMETER_PA_BASE within
+	 * "linux/arch/nds32/include/asm/misc_spec.h"
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_ADPAG101;
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+	ftsmc020_init();	/* initialize Flash */
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned long sdram_base = PHYS_SDRAM_0;
+	unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
+	unsigned long actual_size;
+
+	actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+	gd->ram_size = actual_size;
+
+	if (expected_size != actual_size) {
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+	}
+
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
+	gd->bd->bi_dram[0].size =  PHYS_SDRAM_0_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[1].size =  PHYS_SDRAM_1_SIZE;
+}
+
+int board_eth_init(bd_t *bd)
+{
+	return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	ftsdc010_mmc_init(0);
+	return 0;
+}