14 files changed, 1454 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/arch/sh/lib/Makefile b/qemu/roms/u-boot/arch/sh/lib/Makefile
new file mode 100644
index 000000000..8a84b24af
--- /dev/null
+++ b/qemu/roms/u-boot/arch/sh/lib/Makefile
@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+
+obj-y	+= board.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
+ifeq ($(CONFIG_SH2),y)
+obj-y	+= time_sh2.o
+else
+obj-y	+= time.o
+endif
+obj-$(CONFIG_CMD_SH_ZIMAGEBOOT) += zimageboot.o
+
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashiftrt.o ashiftlt.o lshiftrt.o \
+				    ashldi3.o ashrsi3.o lshrdi3.o movmem.o
diff --git a/qemu/roms/u-boot/arch/sh/lib/ashiftlt.S b/qemu/roms/u-boot/arch/sh/lib/ashiftlt.S
new file mode 100644
index 000000000..f971568e3
--- /dev/null
+++ b/qemu/roms/u-boot/arch/sh/lib/ashiftlt.S
@@ -0,0 +1,171 @@
+/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+   2004, 2005, 2006
+   Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+!! libgcc routines for the Renesas / SuperH SH CPUs.
+!! Contributed by Steve Chamberlain.
+!! sac@cygnus.com
+
+!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
+!! recoded in assembly by Toshiyasu Morita
+!! tm@netcom.com
+
+/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
+   ELF local label prefixes by J"orn Rennecke
+   amylaar@cygnus.com  */
+
+!
+! GLOBAL(ashlsi3)
+!
+! Entry:
+!
+! r4: Value to shift
+! r5: Shifts
+!
+! Exit:
+!
+! r0: Result
+!
+! Destroys:
+!
+! (none)
+!
+	.global	__ashlsi3
+	.align	2
+__ashlsi3:
+	mov	#31,r0
+	and	r0,r5
+	mova	__ashlsi3_table,r0
+	mov.b	@(r0,r5),r5
+#ifdef __sh1__
+	add	r5,r0
+	jmp	@r0
+#else
+	braf	r5
+#endif
+	mov	r4,r0
+
+	.align	2
+__ashlsi3_table:
+	.byte		__ashlsi3_0-__ashlsi3_table
+	.byte		__ashlsi3_1-__ashlsi3_table
+	.byte		__ashlsi3_2-__ashlsi3_table
+	.byte		__ashlsi3_3-__ashlsi3_table
+	.byte		__ashlsi3_4-__ashlsi3_table
+	.byte		__ashlsi3_5-__ashlsi3_table
+	.byte		__ashlsi3_6-__ashlsi3_table
+	.byte		__ashlsi3_7-__ashlsi3_table
+	.byte		__ashlsi3_8-__ashlsi3_table
+	.byte		__ashlsi3_9-__ashlsi3_table
+	.byte		__ashlsi3_10-__ashlsi3_table
+	.byte		__ashlsi3_11-__ashlsi3_table
+	.byte		__ashlsi3_12-__ashlsi3_table
+	.byte		__ashlsi3_13-__ashlsi3_table
+	.byte		__ashlsi3_14-__ashlsi3_table
+	.byte		__ashlsi3_15-__ashlsi3_table
+	.byte		__ashlsi3_16-__ashlsi3_table
+	.byte		__ashlsi3_17-__ashlsi3_table
+	.byte		__ashlsi3_18-__ashlsi3_table
+	.byte		__ashlsi3_19-__ashlsi3_table
+	.byte		__ashlsi3_20-__ashlsi3_table
+	.byte		__ashlsi3_21-__ashlsi3_table
+	.byte		__ashlsi3_22-__ashlsi3_table
+	.byte		__ashlsi3_23-__ashlsi3_table
+	.byte		__ashlsi3_24-__ashlsi3_table
+	.byte		__ashlsi3_25-__ashlsi3_table
+	.byte		__ashlsi3_26-__ashlsi3_table
+	.byte		__ashlsi3_27-__ashlsi3_table
+	.byte		__ashlsi3_28-__ashlsi3_table
+	.byte		__ashlsi3_29-__ashlsi3_table
+	.byte		__ashlsi3_30-__ashlsi3_table
+	.byte		__ashlsi3_31-__ashlsi3_table
+
+__ashlsi3_6:
+	shll2	r0
+__ashlsi3_4:
+	shll2	r0
+__ashlsi3_2:
+	rts
+	shll2	r0
+
+__ashlsi3_7:
+	shll2	r0
+__ashlsi3_5:
+	shll2	r0
+__ashlsi3_3:
+	shll2	r0
+__ashlsi3_1:
+	rts
+	shll	r0
+
+__ashlsi3_14:
+	shll2	r0
+__ashlsi3_12:
+	shll2	r0
+__ashlsi3_10:
+	shll2	r0
+__ashlsi3_8:
+	rts
+	shll8	r0
+
+__ashlsi3_15:
+	shll2	r0
+__ashlsi3_13:
+	shll2	r0
+__ashlsi3_11:
+	shll2	r0
+__ashlsi3_9:
+	shll8	r0
+	rts
+	shll	r0
+
+__ashlsi3_22:
+	shll2	r0
+__ashlsi3_20:
+	shll2	r0
+__ashlsi3_18:
+	shll2	r0
+__ashlsi3_16:
+	rts
+	shll16	r0
+
+__ashlsi3_23:
+	shll2	r0
+__ashlsi3_21:
+	shll2	r0
+__ashlsi3_19:
+	shll2	r0
+__ashlsi3_17:
+	shll16	r0
+	rts
+	shll	r0
+
+__ashlsi3_30:
+	shll2	r0
+__ashlsi3_28:
+	shll2	r0
+__ashlsi3_26:
+	shll2	r0
+__ashlsi3_24:
+	shll16	r0
+	rts
+	shll8	r0
+
+__ashlsi3_31:
+	shll2	r0
+__ashlsi3_29:
+	shll2	r0
+__ashlsi3_27:
+	shll2	r0
+__ashlsi3_25:
+	shll16	r0
+	shll8	r0
+	rts
+	shll	r0
+
+__ashlsi3_0:
+	rts
+	nop
diff --git a/qemu/roms/u-boot/arch/sh/lib/ashiftrt.S b/qemu/roms/u-boot/arch/sh/lib/ashiftrt.S
new file mode 100644
index 000000000..7143afc52
--- /dev/null
+++ b/qemu/roms/u-boot/arch/sh/lib/ashiftrt.S
@@ -0,0 +1,128 @@
+/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+   2004, 2005, 2006
+   Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+!! libgcc routines for the Renesas / SuperH SH CPUs.
+!! Contributed by Steve Chamberlain.
+!! sac@cygnus.com
+
+!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
+!! recoded in assembly by Toshiyasu Morita
+!! tm@netcom.com
+
+/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
+   ELF local label prefixes by J"orn Rennecke
+   amylaar@cygnus.com  */
+
+	.global	__ashiftrt_r4_0
+	.global	__ashiftrt_r4_1
+	.global	__ashiftrt_r4_2
+	.global	__ashiftrt_r4_3
+	.global	__ashiftrt_r4_4
+	.global	__ashiftrt_r4_5
+	.global	__ashiftrt_r4_6
+	.global	__ashiftrt_r4_7
+	.global	__ashiftrt_r4_8
+	.global	__ashiftrt_r4_9
+	.global	__ashiftrt_r4_10
+	.global	__ashiftrt_r4_11
+	.global	__ashiftrt_r4_12
+	.global	__ashiftrt_r4_13
+	.global	__ashiftrt_r4_14
+	.global	__ashiftrt_r4_15
+	.global	__ashiftrt_r4_16
+	.global	__ashiftrt_r4_17
+	.global	__ashiftrt_r4_18
+	.global	__ashiftrt_r4_19
+	.global	__ashiftrt_r4_20
+	.global	__ashiftrt_r4_21
+	.global	__ashiftrt_r4_22
+	.global	__ashiftrt_r4_23
+	.global	__ashiftrt_r4_24
+	.global	__ashiftrt_r4_25
+	.global	__ashiftrt_r4_26
+	.global	__ashiftrt_r4_27
+	.global	__ashiftrt_r4_28
+	.global	__ashiftrt_r4_29
+	.global	__ashiftrt_r4_30
+	.global	__ashiftrt_r4_31
+	.global	__ashiftrt_r4_32
+
+	.align	1
+__ashiftrt_r4_32:
+__ashiftrt_r4_31:
+	rotcl	r4
+	rts
+	subc	r4,r4
+__ashiftrt_r4_30:
+	shar	r4
+__ashiftrt_r4_29:
+	shar	r4
+__ashiftrt_r4_28:
+	shar	r4
+__ashiftrt_r4_27:
+	shar	r4
+__ashiftrt_r4_26:
+	shar	r4
+__ashiftrt_r4_25:
+	shar	r4
+__ashiftrt_r4_24:
+	shlr16	r4
+	shlr8	r4
+	rts
+	exts.b	r4,r4
+__ashiftrt_r4_23:
+	shar	r4
+__ashiftrt_r4_22:
+	shar	r4
+__ashiftrt_r4_21:
+	shar	r4
+__ashiftrt_r4_20:
+	shar	r4
+__ashiftrt_r4_19:
+	shar	r4
+__ashiftrt_r4_18:
+	shar	r4
+__ashiftrt_r4_17:
+	shar	r4
+__ashiftrt_r4_16:
+	shlr16	r4
+	rts
+	exts.w	r4,r4
+__ashiftrt_r4_15:
+	shar	r4
+__ashiftrt_r4_14:
+	shar	r4
+__ashiftrt_r4_13:
+	shar	r4
+__ashiftrt_r4_12:
+	shar	r4
+__ashiftrt_r4_11:
+	shar	r4
+__ashiftrt_r4_10:
+	shar	r4
+__ashiftrt_r4_9:
+	shar	r4
+__ashiftrt_r4_8:
+	shar	r4
+__ashiftrt_r4_7:
+	shar	r4
+__ashiftrt_r4_6:
+	shar	r4
+__ashiftrt_r4_5:
+	shar	r4
+__ashiftrt_r4_4:
+	shar	r4
+__ashiftrt_r4_3:
+	shar	r4
+__ashiftrt_r4_2:
+	shar	r4
+__ashiftrt_r4_1:
+	rts
+	shar	r4
+__ashiftrt_r4_0:
+	rts
+	nop
diff --git a/qemu/roms/u-boot/arch/sh/lib/ashldi3.c b/qemu/roms/u-boot/arch/sh/lib/ashldi3.c
new file mode 100644
index 000000000..9b50d866a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/sh/lib/ashldi3.c
@@ -0,0 +1,25 @@
+#include "libgcc.h"
+
+long long __ashldi3(long long u, word_type b)
+{
+	DWunion uu, w;
+	word_type bm;
+
+	if (b == 0)
+		return u;
+
+	uu.ll = u;
+	bm = 32 - b;
+
+	if (bm <= 0) {
+		w.s.low = 0;
+		w.s.high = (unsigned int) uu.s.low << -bm;
+	} else {
+		const unsigned int carries = (unsigned int) uu.s.low >> bm;
+
+		w.s.low = (unsigned int) uu.s.low << b;
+		w.s.high = ((unsigned int) uu.s.high << b) | carries;
+	}
+
+	return w.ll;
+}
diff --git a/qemu/roms/u-boot/arch/sh/lib/ashrsi3.S b/qemu/roms/u-boot/arch/sh/lib/ashrsi3.S
new file mode 100644
index 000000000..01f15def9
--- /dev/null
+++ b/qemu/roms/u-boot/arch/sh/lib/ashrsi3.S
@@ -0,0 +1,164 @@
+/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+   2004, 2005, 2006
+   Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+!! libgcc routines for the Renesas / SuperH SH CPUs.
+!! Contributed by Steve Chamberlain.
+!! sac@cygnus.com
+
+!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
+!! recoded in assembly by Toshiyasu Morita
+!! tm@netcom.com
+
+/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
+   ELF local label prefixes by J"orn Rennecke
+   amylaar@cygnus.com  */
+
+!
+! __ashrsi3
+!
+! Entry:
+!
+! r4: Value to shift
+! r5: Shifts
+!
+! Exit:
+!
+! r0: Result
+!
+! Destroys:
+!
+! (none)
+!
+
+	.global	__ashrsi3
+
+	.align	2
+__ashrsi3:
+	mov	#31,r0
+	and	r0,r5
+	mova	ashrsi3_table,r0
+	mov.b	@(r0,r5),r5
+#ifdef __sh1__
+	add	r5,r0
+	jmp	@r0
+#else
+	braf	r5
+#endif
+	mov	r4,r0
+
+	.align	2
+ashrsi3_table:
+	.byte		ashrsi3_0-ashrsi3_table
+	.byte		ashrsi3_1-ashrsi3_table
+	.byte		ashrsi3_2-ashrsi3_table
+	.byte		ashrsi3_3-ashrsi3_table
+	.byte		ashrsi3_4-ashrsi3_table
+	.byte		ashrsi3_5-ashrsi3_table
+	.byte		ashrsi3_6-ashrsi3_table
+	.byte		ashrsi3_7-ashrsi3_table
+	.byte		ashrsi3_8-ashrsi3_table
+	.byte		ashrsi3_9-ashrsi3_table
+	.byte		ashrsi3_10-ashrsi3_table
+	.byte		ashrsi3_11-ashrsi3_table
+	.byte		ashrsi3_12-ashrsi3_table
+	.byte		ashrsi3_13-ashrsi3_table
+	.byte		ashrsi3_14-ashrsi3_table
+	.byte		ashrsi3_15-ashrsi3_table
+	.byte		ashrsi3_16-ashrsi3_table
+	.byte		ashrsi3_17-ashrsi3_table
+	.byte		ashrsi3_18-ashrsi3_table
+	.byte		ashrsi3_19-ashrsi3_table
+	.byte		ashrsi3_20-ashrsi3_table
+	.byte		ashrsi3_21-ashrsi3_table
+	.byte		ashrsi3_22-ashrsi3_table
+	.byte		ashrsi3_23-ashrsi3_table
+	.byte		ashrsi3_24-ashrsi3_table
+	.byte		ashrsi3_25-ashrsi3_table
+	.byte		ashrsi3_26-ashrsi3_table
+	.byte		ashrsi3_27-ashrsi3_table
+	.byte		ashrsi3_28-ashrsi3_table
+	.byte		ashrsi3_29-ashrsi3_table
+	.byte		ashrsi3_30-ashrsi3_table
+	.byte		ashrsi3_31-ashrsi3_table
+
+ashrsi3_31:
+	rotcl	r0
+	rts
+	subc	r0,r0
+
+ashrsi3_30:
+	shar	r0
+ashrsi3_29:
+	shar	r0
+ashrsi3_28:
+	shar	r0
+ashrsi3_27:
+	shar	r0
+ashrsi3_26:
+	shar	r0
+ashrsi3_25:
+	shar	r0
+ashrsi3_24:
+	shlr16	r0
+	shlr8	r0
+	rts
+	exts.b	r0,r0
+
+ashrsi3_23:
+	shar	r0
+ashrsi3_22:
+	shar	r0
+ashrsi3_21:
+	shar	r0
+ashrsi3_20:
+	shar	r0
+ashrsi3_19:
+	shar	r0
+ashrsi3_18:
+	shar	r0
+ashrsi3_17:
+	shar	r0
+ashrsi3_16:
+	shlr16	r0
+	rts
+	exts.w	r0,r0
+
+ashrsi3_15:
+	shar	r0
+ashrsi3_14:
+	shar	r0
+ashrsi3_13:
+	shar	r0
+ashrsi3_12:
+	shar	r0
+ashrsi3_11:
+	shar	r0
+ashrsi3_10:
+	shar	r0
+ashrsi3_9:
+	shar	r0
+ashrsi3_8:
+	shar	r0
+ashrsi3_7:
+	shar	r0
+ashrsi3_6:
+	shar	r0
+ashrsi3_5:
+	shar	r0
+ashrsi3_4:
+	shar	r0
+ashrsi3_3:
+	shar	r0
+ashrsi3_2:
+	shar	r0
+ashrsi3_1:
+	rts
+	shar	r0
+
+ashrsi3_0:
+	rts
+	nop
diff --git a/qemu/roms/u-boot/arch/sh/lib/board.c b/qemu/roms/u-boot/arch/sh/lib/board.c
new file mode 100644
index 000000000..1eb7afb89
--- /dev/null
+++ b/qemu/roms/u-boot/arch/sh/lib/board.c
@@ -0,0 +1,188 @@
+/*
+ * Copyright (C) 2007, 2008, 2010
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+#include <version.h>
+#include <watchdog.h>
+#include <net.h>
+#include <mmc.h>
+#include <environment.h>
+
+#ifdef CONFIG_BITBANGMII
+#include <miiphy.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern int cpu_init(void);
+extern int board_init(void);
+extern int dram_init(void);
+extern int timer_init(void);
+
+unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
+
+#ifndef CONFIG_SYS_NO_FLASH
+static int sh_flash_init(void)
+{
+	gd->bd->bi_flashsize = flash_init();
+
+	if (gd->bd->bi_flashsize >= (1024 * 1024))
+		printf("Flash: %ldMB\n", gd->bd->bi_flashsize / (1024*1024));
+	else
+		printf("Flash: %ldKB\n", gd->bd->bi_flashsize / 1024);
+
+	return 0;
+}
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_NAND)
+# include <nand.h>
+# define INIT_FUNC_NAND_INIT nand_init,
+#else
+# define INIT_FUNC_NAND_INIT
+#endif /* CONFIG_CMD_NAND */
+
+#if defined(CONFIG_WATCHDOG)
+extern int watchdog_init(void);
+extern int watchdog_disable(void);
+# undef INIT_FUNC_WATCHDOG_INIT
+# define INIT_FUNC_WATCHDOG_INIT	watchdog_init,
+# define WATCHDOG_DISABLE       	watchdog_disable
+#else
+# define INIT_FUNC_WATCHDOG_INIT
+# define WATCHDOG_DISABLE
+#endif /* CONFIG_WATCHDOG */
+
+#if defined(CONFIG_CMD_IDE)
+# include <ide.h>
+# define INIT_FUNC_IDE_INIT	ide_init,
+#else
+# define INIT_FUNC_IDE_INIT
+#endif /* CONFIG_CMD_IDE */
+
+#if defined(CONFIG_PCI)
+#include <pci.h>
+static int sh_pci_init(void)
+{
+	pci_init();
+	return 0;
+}
+# define INIT_FUNC_PCI_INIT sh_pci_init,
+#else
+# define INIT_FUNC_PCI_INIT
+#endif /* CONFIG_PCI */
+
+static int sh_mem_env_init(void)
+{
+	mem_malloc_init(CONFIG_SYS_TEXT_BASE - GENERATED_GBL_DATA_SIZE -
+			CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN - 16);
+	env_relocate();
+	jumptable_init();
+	return 0;
+}
+
+#if defined(CONFIG_CMD_MMC)
+static int sh_mmc_init(void)
+{
+	puts("MMC:   ");
+	mmc_initialize(gd->bd);
+	return 0;
+}
+#endif
+
+typedef int (init_fnc_t) (void);
+
+init_fnc_t *init_sequence[] =
+{
+	cpu_init,		/* basic cpu dependent setup */
+	board_init,		/* basic board dependent setup */
+	interrupt_init,	/* set up exceptions */
+	env_init,		/* event init */
+	serial_init,	/* SCIF init */
+	INIT_FUNC_WATCHDOG_INIT	/* watchdog init */
+	console_init_f,
+	display_options,
+	checkcpu,
+	checkboard,		/* Check support board */
+	dram_init,		/* SDRAM init */
+	timer_init,		/* SuperH Timer (TCNT0 only) init */
+	sh_mem_env_init,
+#ifndef CONFIG_SYS_NO_FLASH
+	sh_flash_init,	/* Flash memory init*/
+#endif
+	INIT_FUNC_NAND_INIT/* Flash memory (NAND) init */
+	INIT_FUNC_PCI_INIT	/* PCI init */
+	stdio_init,
+	console_init_r,
+	interrupt_init,
+#ifdef CONFIG_BOARD_LATE_INIT
+	board_late_init,
+#endif
+#if defined(CONFIG_CMD_MMC)
+	sh_mmc_init,
+#endif
+	NULL			/* Terminate this list */
+};
+
+void sh_generic_init(void)
+{
+	bd_t *bd;
+	init_fnc_t **init_fnc_ptr;
+
+	memset(gd, 0, GENERATED_GBL_DATA_SIZE);
+
+	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
+
+	gd->bd = (bd_t *)(gd + 1);	/* At end of global data */
+	gd->baudrate = CONFIG_BAUDRATE;
+
+	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
+
+	bd = gd->bd;
+	bd->bi_memstart	= CONFIG_SYS_SDRAM_BASE;
+	bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+#ifndef CONFIG_SYS_NO_FLASH
+	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+#endif
+#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
+	bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
+	bd->bi_sramsize	= CONFIG_SYS_SRAM_SIZE;
+#endif
+
+	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+		WATCHDOG_RESET();
+		if ((*init_fnc_ptr) () != 0)
+			hang();
+	}
+
+#ifdef CONFIG_WATCHDOG
+	/* disable watchdog if environment is set */
+	{
+		char *s = getenv("watchdog");
+		if (s != NULL)
+			if (strncmp(s, "off", 3) == 0)
+				WATCHDOG_DISABLE();
+	}
+#endif /* CONFIG_WATCHDOG*/
+
+
+#ifdef CONFIG_BITBANGMII
+	bb_miiphy_init();
+#endif
+#if defined(CONFIG_CMD_NET)
+	puts("Net:   ");
+	eth_initialize(gd->bd);
+#endif /* CONFIG_CMD_NET */
+
+	while (1) {
+		WATCHDOG_RESET();
+		main_loop();
+	}
+}
diff --git a/qemu/roms/u-boot/arch/sh/lib/bootm.c b/qemu/roms/u-boot/arch/sh/lib/bootm.c
new file mode 100644
index 000000000..8a0010be2
--- /dev/null
+++ b/qemu/roms/u-boot/arch/sh/lib/bootm.c
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (c) Copyright 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ * (c) Copyright 2008 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/byteorder.h>
+#include <asm/zimage.h>
+
+#ifdef CONFIG_SYS_DEBUG
+static void hexdump(unsigned char *buf, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++) {
+		if ((i % 16) == 0)
+			printf("%s%08x: ", i ? "\n" : "",
+							(unsigned int)&buf[i]);
+		printf("%02x ", buf[i]);
+	}
+	printf("\n");
+}
+#endif
+
+#ifdef CONFIG_SH_SDRAM_OFFSET
+#define GET_INITRD_START(initrd, linux) (initrd - linux + CONFIG_SH_SDRAM_OFFSET)
+#else
+#define GET_INITRD_START(initrd, linux) (initrd - linux)
+#endif
+
+static void set_sh_linux_param(unsigned long param_addr, unsigned long data)
+{
+	*(unsigned long *)(param_addr) = data;
+}
+
+static unsigned long sh_check_cmd_arg(char *cmdline, char *key, int base)
+{
+	unsigned long val = 0;
+	char *p = strstr(cmdline, key);
+	if (p) {
+		p += strlen(key);
+		val = simple_strtol(p, NULL, base);
+	}
+	return val;
+}
+
+int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
+{
+	/* Linux kernel load address */
+	void (*kernel) (void) = (void (*)(void))images->ep;
+	/* empty_zero_page */
+	unsigned char *param
+		= (unsigned char *)image_get_load(images->legacy_hdr_os);
+	/* Linux kernel command line */
+	char *cmdline = (char *)param + COMMAND_LINE;
+	/* PAGE_SIZE */
+	unsigned long size = images->ep - (unsigned long)param;
+	char *bootargs = getenv("bootargs");
+
+	/*
+	 * allow the PREP bootm subcommand, it is required for bootm to work
+	 */
+	if (flag & BOOTM_STATE_OS_PREP)
+		return 0;
+
+	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
+		return 1;
+
+	/* Clear zero page */
+	memset(param, 0, size);
+
+	/* Set commandline */
+	strcpy(cmdline, bootargs);
+
+	/* Initrd */
+	if (images->rd_start || images->rd_end) {
+		unsigned long ramdisk_flags = 0;
+		int val = sh_check_cmd_arg(bootargs, CMD_ARG_RD_PROMPT, 10);
+		if (val == 1)
+				ramdisk_flags |= RD_PROMPT;
+		else
+				ramdisk_flags &= ~RD_PROMPT;
+
+		val = sh_check_cmd_arg(bootargs, CMD_ARG_RD_DOLOAD, 10);
+		if (val == 1)
+				ramdisk_flags |= RD_DOLOAD;
+		else
+				ramdisk_flags &= ~RD_DOLOAD;
+
+		set_sh_linux_param((unsigned long)param + MOUNT_ROOT_RDONLY, 0x0001);
+		set_sh_linux_param((unsigned long)param + RAMDISK_FLAGS, ramdisk_flags);
+		set_sh_linux_param((unsigned long)param + ORIG_ROOT_DEV, 0x0200);
+		set_sh_linux_param((unsigned long)param + LOADER_TYPE, 0x0001);
+		set_sh_linux_param((unsigned long)param + INITRD_START,
+			GET_INITRD_START(images->rd_start, CONFIG_SYS_SDRAM_BASE));
+		set_sh_linux_param((unsigned long)param + INITRD_SIZE,
+			images->rd_end - images->rd_start);
+	}
+
+	/* Boot kernel */
+	kernel();
+
+	/* does not return */
+	return 1;
+}
diff --git a/qemu/roms/u-boot/arch/sh/lib/libgcc.h b/qemu/roms/u-boot/arch/sh/lib/libgcc.h
new file mode 100644
index 000000000..05909d58e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/sh/lib/libgcc.h
@@ -0,0 +1,25 @@
+#ifndef __ASM_LIBGCC_H
+#define __ASM_LIBGCC_H
+
+#include <asm/byteorder.h>
+
+typedef int word_type __attribute__ ((mode (__word__)));
+
+#ifdef __BIG_ENDIAN
+struct DWstruct {
+	int high, low;
+};
+#elif defined(__LITTLE_ENDIAN)
+struct DWstruct {
+	int low, high;
+};
+#else
+#error I feel sick.
+#endif
+
+typedef union {
+	struct DWstruct s;
+	long long ll;
+} DWunion;
+
+#endif /* __ASM_LIBGCC_H */
diff --git a/qemu/roms/u-boot/arch/sh/lib/lshiftrt.S b/qemu/roms/u-boot/arch/sh/lib/lshiftrt.S
new file mode 100644
index 000000000..787044d2e
--- /dev/null
+++ b/qemu/roms/u-boot/arch/sh/lib/lshiftrt.S
@@ -0,0 +1,171 @@
+/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+   2004, 2005, 2006
+   Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+!! libgcc routines for the Renesas / SuperH SH CPUs.
+!! Contributed by Steve Chamberlain.
+!! sac@cygnus.com
+
+!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
+!! recoded in assembly by Toshiyasu Morita
+!! tm@netcom.com
+
+/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
+   ELF local label prefixes by J"orn Rennecke
+   amylaar@cygnus.com  */
+
+!
+! __lshrsi3)
+!
+! Entry:
+!
+! r4: Value to shift
+! r5: Shifts
+!
+! Exit:
+!
+! r0: Result
+!
+! Destroys:
+!
+! (none)
+!
+	.global	__lshrsi3
+	.align	2
+__lshrsi3:
+	mov	#31,r0
+	and	r0,r5
+	mova	__lshrsi3_table,r0
+	mov.b	@(r0,r5),r5
+#ifdef __sh1__
+	add	r5,r0
+	jmp	@r0
+#else
+	braf	r5
+#endif
+	mov	r4,r0
+
+	.align	2
+__lshrsi3_table:
+	.byte		__lshrsi3_0-__lshrsi3_table
+	.byte		__lshrsi3_1-__lshrsi3_table
+	.byte		__lshrsi3_2-__lshrsi3_table
+	.byte		__lshrsi3_3-__lshrsi3_table
+	.byte		__lshrsi3_4-__lshrsi3_table
+	.byte		__lshrsi3_5-__lshrsi3_table
+	.byte		__lshrsi3_6-__lshrsi3_table
+	.byte		__lshrsi3_7-__lshrsi3_table
+	.byte		__lshrsi3_8-__lshrsi3_table
+	.byte		__lshrsi3_9-__lshrsi3_table
+	.byte		__lshrsi3_10-__lshrsi3_table
+	.byte		__lshrsi3_11-__lshrsi3_table
+	.byte		__lshrsi3_12-__lshrsi3_table
+	.byte		__lshrsi3_13-__lshrsi3_table
+	.byte		__lshrsi3_14-__lshrsi3_table
+	.byte		__lshrsi3_15-__lshrsi3_table
+	.byte		__lshrsi3_16-__lshrsi3_table
+	.byte		__lshrsi3_17-__lshrsi3_table
+	.byte		__lshrsi3_18-__lshrsi3_table
+	.byte		__lshrsi3_19-__lshrsi3_table
+	.byte		__lshrsi3_20-__lshrsi3_table
+	.byte		__lshrsi3_21-__lshrsi3_table
+	.byte		__lshrsi3_22-__lshrsi3_table
+	.byte		__lshrsi3_23-__lshrsi3_table
+	.byte		__lshrsi3_24-__lshrsi3_table
+	.byte		__lshrsi3_25-__lshrsi3_table
+	.byte		__lshrsi3_26-__lshrsi3_table
+	.byte		__lshrsi3_27-__lshrsi3_table
+	.byte		__lshrsi3_28-__lshrsi3_table
+	.byte		__lshrsi3_29-__lshrsi3_table
+	.byte		__lshrsi3_30-__lshrsi3_table
+	.byte		__lshrsi3_31-__lshrsi3_table
+
+__lshrsi3_6:
+	shlr2	r0
+__lshrsi3_4:
+	shlr2	r0
+__lshrsi3_2:
+	rts
+	shlr2	r0
+
+__lshrsi3_7:
+	shlr2	r0
+__lshrsi3_5:
+	shlr2	r0
+__lshrsi3_3:
+	shlr2	r0
+__lshrsi3_1:
+	rts
+	shlr	r0
+
+__lshrsi3_14:
+	shlr2	r0
+__lshrsi3_12:
+	shlr2	r0
+__lshrsi3_10:
+	shlr2	r0
+__lshrsi3_8:
+	rts
+	shlr8	r0
+
+__lshrsi3_15:
+	shlr2	r0
+__lshrsi3_13:
+	shlr2	r0
+__lshrsi3_11:
+	shlr2	r0
+__lshrsi3_9:
+	shlr8	r0
+	rts
+	shlr	r0
+
+__lshrsi3_22:
+	shlr2	r0
+__lshrsi3_20:
+	shlr2	r0
+__lshrsi3_18:
+	shlr2	r0
+__lshrsi3_16:
+	rts
+	shlr16	r0
+
+__lshrsi3_23:
+	shlr2	r0
+__lshrsi3_21:
+	shlr2	r0
+__lshrsi3_19:
+	shlr2	r0
+__lshrsi3_17:
+	shlr16	r0
+	rts
+	shlr	r0
+
+__lshrsi3_30:
+	shlr2	r0
+__lshrsi3_28:
+	shlr2	r0
+__lshrsi3_26:
+	shlr2	r0
+__lshrsi3_24:
+	shlr16	r0
+	rts
+	shlr8	r0
+
+__lshrsi3_31:
+	shlr2	r0
+__lshrsi3_29:
+	shlr2	r0
+__lshrsi3_27:
+	shlr2	r0
+__lshrsi3_25:
+	shlr16	r0
+	shlr8	r0
+	rts
+	shlr	r0
+
+__lshrsi3_0:
+	rts
+	nop
diff --git a/qemu/roms/u-boot/arch/sh/lib/lshrdi3.c b/qemu/roms/u-boot/arch/sh/lib/lshrdi3.c
new file mode 100644
index 000000000..bb340accb
--- /dev/null
+++ b/qemu/roms/u-boot/arch/sh/lib/lshrdi3.c
@@ -0,0 +1,25 @@
+#include "libgcc.h"
+
+long long __lshrdi3(long long u, word_type b)
+{
+	DWunion uu, w;
+	word_type bm;
+
+	if (b == 0)
+		return u;
+
+	uu.ll = u;
+	bm = 32 - b;
+
+	if (bm <= 0) {
+		w.s.high = 0;
+		w.s.low = (unsigned int) uu.s.high >> -bm;
+	} else {
+		const unsigned int carries = (unsigned int) uu.s.high << bm;
+
+		w.s.high = (unsigned int) uu.s.high >> b;
+		w.s.low = ((unsigned int) uu.s.low >> b) | carries;
+	}
+
+	return w.ll;
+}
diff --git a/qemu/roms/u-boot/arch/sh/lib/movmem.S b/qemu/roms/u-boot/arch/sh/lib/movmem.S
new file mode 100644
index 000000000..99e52da07
--- /dev/null
+++ b/qemu/roms/u-boot/arch/sh/lib/movmem.S
@@ -0,0 +1,217 @@
+/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+   2004, 2005, 2006
+   Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+!! libgcc routines for the Renesas / SuperH SH CPUs.
+!! Contributed by Steve Chamberlain.
+!! sac@cygnus.com
+
+!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
+!! recoded in assembly by Toshiyasu Morita
+!! tm@netcom.com
+
+/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
+   ELF local label prefixes by J"orn Rennecke
+   amylaar@cygnus.com  */
+
+	.text
+	.balign	4
+	.global	__movmem
+	.global __movstr
+	.set __movstr, __movmem
+	/* This would be a lot simpler if r6 contained the byte count
+	   minus 64, and we wouldn't be called here for a byte count of 64.  */
+__movmem:
+	sts.l	pr,@-r15
+	shll2	r6
+	bsr	__movmemSI52+2
+	mov.l	@(48,r5),r0
+	.balign	4
+movmem_loop: /* Reached with rts */
+	mov.l	@(60,r5),r0
+	add	#-64,r6
+	mov.l	r0,@(60,r4)
+	tst	r6,r6
+	mov.l	@(56,r5),r0
+	bt	movmem_done
+	mov.l	r0,@(56,r4)
+	cmp/pl	r6
+	mov.l	@(52,r5),r0
+	add	#64,r5
+	mov.l	r0,@(52,r4)
+	add	#64,r4
+	bt	__movmemSI52
+! done all the large groups, do the remainder
+! jump to movmem+
+	mova	__movmemSI4+4,r0
+	add	r6,r0
+	jmp	@r0
+movmem_done: ! share slot insn, works out aligned.
+	lds.l	@r15+,pr
+	mov.l	r0,@(56,r4)
+	mov.l	@(52,r5),r0
+	rts
+	mov.l	r0,@(52,r4)
+	.balign	4
+
+	.global	__movmemSI64
+	.global __movstrSI64
+	.set	__movstrSI64, __movmemSI64
+__movmemSI64:
+	mov.l	@(60,r5),r0
+	mov.l	r0,@(60,r4)
+	.global	__movmemSI60
+	.global __movstrSI60
+	.set	__movstrSI60, __movmemSI60
+__movmemSI60:
+	mov.l	@(56,r5),r0
+	mov.l	r0,@(56,r4)
+	.global	__movmemSI56
+	.global __movstrSI56
+	.set	__movstrSI56, __movmemSI56
+__movmemSI56:
+	mov.l	@(52,r5),r0
+	mov.l	r0,@(52,r4)
+	.global	__movmemSI52
+	.global __movstrSI52
+	.set	__movstrSI52, __movmemSI52
+__movmemSI52:
+	mov.l	@(48,r5),r0
+	mov.l	r0,@(48,r4)
+	.global	__movmemSI48
+	.global	__movstrSI48
+	.set	__movstrSI48, __movmemSI48
+__movmemSI48:
+	mov.l	@(44,r5),r0
+	mov.l	r0,@(44,r4)
+	.global	__movmemSI44
+	.global	__movstrSI44
+	.set	__movstrSI44, __movmemSI44
+__movmemSI44:
+	mov.l	@(40,r5),r0
+	mov.l	r0,@(40,r4)
+	.global	__movmemSI40
+	.global __movstrSI40
+	.set	__movstrSI40, __movmemSI40
+__movmemSI40:
+	mov.l	@(36,r5),r0
+	mov.l	r0,@(36,r4)
+	.global	__movmemSI36
+	.global	__movstrSI36
+	.set	__movstrSI36, __movmemSI36
+__movmemSI36:
+	mov.l	@(32,r5),r0
+	mov.l	r0,@(32,r4)
+	.global	__movmemSI32
+	.global	__movstrSI32
+	.set	__movstrSI32, __movmemSI32
+__movmemSI32:
+	mov.l	@(28,r5),r0
+	mov.l	r0,@(28,r4)
+	.global	__movmemSI28
+	.global	__movstrSI28
+	.set	__movstrSI28, __movmemSI28
+__movmemSI28:
+	mov.l	@(24,r5),r0
+	mov.l	r0,@(24,r4)
+	.global	__movmemSI24
+	.global	__movstrSI24
+	.set	__movstrSI24, __movmemSI24
+__movmemSI24:
+	mov.l	@(20,r5),r0
+	mov.l	r0,@(20,r4)
+	.global	__movmemSI20
+	.global	__movstrSI20
+	.set	__movstrSI20, __movmemSI20
+__movmemSI20:
+	mov.l	@(16,r5),r0
+	mov.l	r0,@(16,r4)
+	.global	__movmemSI16
+	.global	__movstrSI16
+	.set	__movstrSI16, __movmemSI16
+__movmemSI16:
+	mov.l	@(12,r5),r0
+	mov.l	r0,@(12,r4)
+	.global	__movmemSI12
+	.global	__movstrSI12
+	.set	__movstrSI12, __movmemSI12
+__movmemSI12:
+	mov.l	@(8,r5),r0
+	mov.l	r0,@(8,r4)
+	.global	__movmemSI8
+	.global	__movstrSI8
+	.set	__movstrSI8, __movmemSI8
+__movmemSI8:
+	mov.l	@(4,r5),r0
+	mov.l	r0,@(4,r4)
+	.global	__movmemSI4
+	.global	__movstrSI4
+	.set	__movstrSI4, __movmemSI4
+__movmemSI4:
+	mov.l	@(0,r5),r0
+	rts
+	mov.l	r0,@(0,r4)
+
+	.global	__movmem_i4_even
+	.global	__movstr_i4_even
+	.set	__movstr_i4_even, __movmem_i4_even
+
+	.global	__movmem_i4_odd
+	.global	__movstr_i4_odd
+	.set	__movstr_i4_odd, __movmem_i4_odd
+
+	.global	__movmemSI12_i4
+	.global	__movstrSI12_i4
+	.set	__movstrSI12_i4, __movmemSI12_i4
+
+	.p2align	5
+L_movmem_2mod4_end:
+	mov.l	r0,@(16,r4)
+	rts
+	mov.l	r1,@(20,r4)
+
+	.p2align	2
+
+__movmem_i4_even:
+	mov.l	@r5+,r0
+	bra	L_movmem_start_even
+	mov.l	@r5+,r1
+
+__movmem_i4_odd:
+	mov.l	@r5+,r1
+	add	#-4,r4
+	mov.l	@r5+,r2
+	mov.l	@r5+,r3
+	mov.l	r1,@(4,r4)
+	mov.l	r2,@(8,r4)
+
+L_movmem_loop:
+	mov.l	r3,@(12,r4)
+	dt	r6
+	mov.l	@r5+,r0
+	bt/s	L_movmem_2mod4_end
+	mov.l	@r5+,r1
+	add	#16,r4
+L_movmem_start_even:
+	mov.l	@r5+,r2
+	mov.l	@r5+,r3
+	mov.l	r0,@r4
+	dt	r6
+	mov.l	r1,@(4,r4)
+	bf/s	L_movmem_loop
+	mov.l	r2,@(8,r4)
+	rts
+	mov.l	r3,@(12,r4)
+
+	.p2align	4
+__movmemSI12_i4:
+	mov.l	@r5,r0
+	mov.l	@(4,r5),r1
+	mov.l	@(8,r5),r2
+	mov.l	r0,@r4
+	mov.l	r1,@(4,r4)
+	rts
+	mov.l	r2,@(8,r4)
diff --git a/qemu/roms/u-boot/arch/sh/lib/time.c b/qemu/roms/u-boot/arch/sh/lib/time.c
new file mode 100644
index 000000000..d970a1e4f
--- /dev/null
+++ b/qemu/roms/u-boot/arch/sh/lib/time.c
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2009
+ * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * (C) Copyright 2007-2012
+ * Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <sh_tmu.h>
+
+#define TCR_TPSC 0x07
+
+static struct tmu_regs *tmu = (struct tmu_regs *)TMU_BASE;
+
+unsigned long get_tbclk(void)
+{
+	u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
+	return get_tmu0_clk_rate() >> ((tmu_bit + 1) * 2);
+}
+
+unsigned long timer_read_counter(void)
+{
+	return ~readl(&tmu->tcnt0);
+}
+
+static void tmu_timer_start(unsigned int timer)
+{
+	if (timer > 2)
+		return;
+	writeb(readb(&tmu->tstr) | (1 << timer), &tmu->tstr);
+}
+
+static void tmu_timer_stop(unsigned int timer)
+{
+	if (timer > 2)
+		return;
+	writeb(readb(&tmu->tstr) & ~(1 << timer), &tmu->tstr);
+}
+
+int timer_init(void)
+{
+	u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
+	writew((readw(&tmu->tcr0) & ~TCR_TPSC) | tmu_bit, &tmu->tcr0);
+
+	tmu_timer_stop(0);
+	tmu_timer_start(0);
+
+	return 0;
+}
+
diff --git a/qemu/roms/u-boot/arch/sh/lib/time_sh2.c b/qemu/roms/u-boot/arch/sh/lib/time_sh2.c
new file mode 100644
index 000000000..4b1f47b6a
--- /dev/null
+++ b/qemu/roms/u-boot/arch/sh/lib/time_sh2.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2007,2008 Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+#define CMT_CMCSR_INIT	0x0001	/* PCLK/32 */
+#define CMT_CMCSR_CALIB 0x0000
+#define CMT_MAX_COUNTER (0xFFFFFFFF)
+#define CMT_TIMER_RESET (0xFFFF)
+
+static vu_long cmt0_timer;
+
+static void cmt_timer_start(unsigned int timer)
+{
+	writew(readw(CMSTR) | 0x01, CMSTR);
+}
+
+static void cmt_timer_stop(unsigned int timer)
+{
+	writew(readw(CMSTR) & ~0x01, CMSTR);
+}
+
+int timer_init(void)
+{
+	cmt0_timer = 0;
+	/* Divide clock by 32 */
+	readw(CMCSR_0);
+	writew(CMT_CMCSR_INIT, CMCSR_0);
+
+	/* User Device 0 only */
+	cmt_timer_stop(0);
+	writew(CMT_TIMER_RESET, CMCOR_0);
+	cmt_timer_start(0);
+
+	return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+	return cmt0_timer;
+}
+
+static vu_long cmcnt = 0;
+static unsigned long get_usec (void)
+{
+	ulong data = readw(CMCNT_0);
+
+	if (data >= cmcnt)
+		cmcnt = data - cmcnt;
+	else
+		cmcnt = (CMT_TIMER_RESET - cmcnt) + data;
+
+	if ((cmt0_timer + cmcnt) > CMT_MAX_COUNTER)
+		cmt0_timer = ((cmt0_timer + cmcnt) - CMT_MAX_COUNTER);
+	else
+		cmt0_timer += cmcnt;
+
+	cmcnt = data;
+	return cmt0_timer;
+}
+
+/* return msec */
+ulong get_timer(ulong base)
+{
+	return (get_usec() / 1000) - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long end = get_usec() + usec;
+
+	while (get_usec() < end)
+		continue;
+}
+
+unsigned long get_tbclk(void)
+{
+	return CONFIG_SH_CMT_CLK_FREQ;
+}
diff --git a/qemu/roms/u-boot/arch/sh/lib/zimageboot.c b/qemu/roms/u-boot/arch/sh/lib/zimageboot.c
new file mode 100644
index 000000000..86d39983c
--- /dev/null
+++ b/qemu/roms/u-boot/arch/sh/lib/zimageboot.c
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2010
+ *   Renesas Solutions Corp.
+ *   Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Linux SuperH zImage loading and boot
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/zimage.h>
+
+int do_sh_zimageboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong (*zboot_entry)(int, char * const []) = NULL;
+	char *s0, *s1;
+	unsigned char *param = NULL;
+	char *cmdline;
+	char *bootargs;
+
+	disable_interrupts();
+
+	if (argc >= 3) {
+		/* argv[1] holds the address of the zImage */
+		s0 = argv[1];
+		/* argv[2] holds the address of zero page */
+		s1 = argv[2];
+	} else {
+		goto exit;
+	}
+
+	if (s0)
+		zboot_entry = (ulong (*)(int, char * const []))simple_strtoul(s0, NULL, 16);
+
+	/* empty_zero_page */
+	if (s1)
+		param = (unsigned char*)simple_strtoul(s1, NULL, 16);
+
+	/* Linux kernel command line */
+	cmdline = (char *)param + COMMAND_LINE;
+	bootargs = getenv("bootargs");
+
+	/* Clear zero page */
+	memset(param, 0, 0x1000);
+
+	/* Set commandline */
+	strcpy(cmdline, bootargs);
+
+	/* Boot */
+	zboot_entry(0, NULL);
+
+exit:
+	return -1;
+}
+
+U_BOOT_CMD(
+	zimageboot, 3, 0,	do_sh_zimageboot,
+	"Boot zImage for Renesas SH",
+	""
+);