diff options
Diffstat (limited to 'qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx')
64 files changed, 14415 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/Makefile b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/Makefile new file mode 100644 index 000000000..ad26b432f --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/Makefile @@ -0,0 +1,116 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2002,2003 Motorola Inc. +# Xianghua Xiao,X.Xiao@motorola.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +MINIMAL= + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +extra-y = start.o resetvec.o + +ifdef MINIMAL + +obj-y += cpu_init_early.o tlb.o spl_minimal.o + +else + +obj-$(CONFIG_MP) += release.o + +obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o +obj-$(CONFIG_CPM2) += commproc.o + +obj-$(CONFIG_CPM2) += ether_fcc.o +obj-$(CONFIG_OF_LIBFDT) += fdt.o +obj-$(CONFIG_FSL_CORENET) += liodn.o +obj-$(CONFIG_MP) += mp.o +obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_SYS_DPAA_QBMAN) += portals.o + +# various SoC specific assignments +obj-$(CONFIG_PPC_P2041) += p2041_ids.o +obj-$(CONFIG_PPC_P3041) += p3041_ids.o +obj-$(CONFIG_PPC_P4080) += p4080_ids.o +obj-$(CONFIG_PPC_P5020) += p5020_ids.o +obj-$(CONFIG_PPC_P5040) += p5040_ids.o +obj-$(CONFIG_PPC_T4240) += t4240_ids.o +obj-$(CONFIG_PPC_T4160) += t4240_ids.o +obj-$(CONFIG_PPC_T4080) += t4240_ids.o +obj-$(CONFIG_PPC_B4420) += b4860_ids.o +obj-$(CONFIG_PPC_B4860) += b4860_ids.o +obj-$(CONFIG_PPC_T1040) += t1040_ids.o +obj-$(CONFIG_PPC_T1042) += t1040_ids.o +obj-$(CONFIG_PPC_T1020) += t1040_ids.o +obj-$(CONFIG_PPC_T1022) += t1040_ids.o +obj-$(CONFIG_PPC_T2080) += t2080_ids.o +obj-$(CONFIG_PPC_T2081) += t2080_ids.o + + +obj-$(CONFIG_QE) += qe_io.o +obj-$(CONFIG_CPM2) += serial_scc.o +obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o +obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o + +# SoC specific SERDES support +obj-$(CONFIG_PPC_C29X) += c29x_serdes.o +obj-$(CONFIG_MPC8536) += mpc8536_serdes.o +obj-$(CONFIG_MPC8544) += mpc8544_serdes.o +obj-$(CONFIG_MPC8548) += mpc8548_serdes.o +obj-$(CONFIG_MPC8568) += mpc8568_serdes.o +obj-$(CONFIG_MPC8569) += mpc8569_serdes.o +obj-$(CONFIG_MPC8572) += mpc8572_serdes.o +obj-$(CONFIG_P1010) += p1010_serdes.o +obj-$(CONFIG_P1011) += p1021_serdes.o +obj-$(CONFIG_P1012) += p1021_serdes.o +obj-$(CONFIG_P1013) += p1022_serdes.o +obj-$(CONFIG_P1014) += p1010_serdes.o +obj-$(CONFIG_P1017) += p1023_serdes.o +obj-$(CONFIG_P1020) += p1021_serdes.o +obj-$(CONFIG_P1021) += p1021_serdes.o +obj-$(CONFIG_P1022) += p1022_serdes.o +obj-$(CONFIG_P1023) += p1023_serdes.o +obj-$(CONFIG_P1024) += p1021_serdes.o +obj-$(CONFIG_P1025) += p1021_serdes.o +obj-$(CONFIG_P2010) += p2020_serdes.o +obj-$(CONFIG_P2020) += p2020_serdes.o +obj-$(CONFIG_PPC_P2041) += p2041_serdes.o +obj-$(CONFIG_PPC_P3041) += p3041_serdes.o +obj-$(CONFIG_PPC_P4080) += p4080_serdes.o +obj-$(CONFIG_PPC_P5020) += p5020_serdes.o +obj-$(CONFIG_PPC_P5040) += p5040_serdes.o +obj-$(CONFIG_PPC_T4240) += t4240_serdes.o +obj-$(CONFIG_PPC_T4160) += t4240_serdes.o +obj-$(CONFIG_PPC_T4080) += t4240_serdes.o +obj-$(CONFIG_PPC_B4420) += b4860_serdes.o +obj-$(CONFIG_PPC_B4860) += b4860_serdes.o +obj-$(CONFIG_BSC9132) += bsc9132_serdes.o +obj-$(CONFIG_PPC_T1040) += t1040_serdes.o +obj-$(CONFIG_PPC_T1042) += t1040_serdes.o +obj-$(CONFIG_PPC_T1020) += t1040_serdes.o +obj-$(CONFIG_PPC_T1022) += t1040_serdes.o +obj-$(CONFIG_PPC_T2080) += t2080_serdes.o +obj-$(CONFIG_PPC_T2081) += t2080_serdes.o + +obj-y += cpu.o +obj-y += cpu_init.o +obj-y += cpu_init_early.o +obj-y += interrupts.o +ifneq ($(CONFIG_QEMU_E500),y) +obj-y += speed.o +endif +obj-y += tlb.o +obj-y += traps.o + +# Stub implementations of cache management functions for USB +obj-y += cache.o + +endif # not minimal diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/b4860_ids.c new file mode 100644 index 000000000..39b8e3ecc --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/b4860_ids.c @@ -0,0 +1,131 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO(1, 27, 1, 0), + SET_QP_INFO(2, 28, 1, 0), + SET_QP_INFO(3, 29, 1, 1), + SET_QP_INFO(4, 30, 1, 1), + SET_QP_INFO(5, 31, 1, 2), + SET_QP_INFO(6, 32, 1, 2), + SET_QP_INFO(7, 33, 1, 3), + SET_QP_INFO(8, 34, 1, 3), + SET_QP_INFO(9, 35, 1, 0), + SET_QP_INFO(10, 36, 1, 0), + SET_QP_INFO(11, 37, 1, 1), + SET_QP_INFO(12, 38, 1, 1), + SET_QP_INFO(13, 39, 1, 2), + SET_QP_INFO(14, 40, 1, 2), + SET_QP_INFO(15, 41, 1, 3), + SET_QP_INFO(16, 42, 1, 3), + SET_QP_INFO(17, 43, 1, 0), + SET_QP_INFO(18, 44, 1, 0), + SET_QP_INFO(19, 45, 1, 1), + SET_QP_INFO(20, 46, 1, 1), + SET_QP_INFO(21, 47, 1, 2), + SET_QP_INFO(22, 48, 1, 2), + SET_QP_INFO(23, 49, 1, 3), + SET_QP_INFO(24, 50, 1, 3), + SET_QP_INFO(25, 51, 1, 0), +}; +#endif + +#ifdef CONFIG_SYS_SRIO +struct srio_liodn_id_table srio_liodn_tbl[] = { + SET_SRIO_LIODN_BASE(1, 307), + SET_SRIO_LIODN_BASE(2, 387), +}; +int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); +#endif + +struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(62), + SET_BMAN_LIODN(63), +#endif + + SET_SDHC_LIODN(1, 552), + + SET_USB_LIODN(1, "fsl-usb2-mph", 553), + + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), + + SET_DMA_LIODN(1, 147), + SET_DMA_LIODN(2, 227), + +#ifndef CONFIG_PPC_B4420 + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), + SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), +#endif + + /* SET_NEXUS_LIODN(557), -- not yet implemented */ +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 88), + SET_FMAN_RX_1G_LIODN(1, 1, 89), + SET_FMAN_RX_1G_LIODN(1, 2, 90), + SET_FMAN_RX_1G_LIODN(1, 3, 91), + SET_FMAN_RX_1G_LIODN(1, 4, 92), + SET_FMAN_RX_1G_LIODN(1, 5, 93), +#ifndef CONFIG_PPC_B4420 + SET_FMAN_RX_10G_LIODN(1, 0, 94), + SET_FMAN_RX_10G_LIODN(1, 1, 95), +#endif +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 454, 458), + SET_SEC_JR_LIODN_ENTRY(1, 455, 459), + SET_SEC_JR_LIODN_ENTRY(2, 456, 460), + SET_SEC_JR_LIODN_ENTRY(3, 457, 461), + SET_SEC_RTIC_LIODN_ENTRY(a, 453), + SET_SEC_RTIC_LIODN_ENTRY(b, 549), + SET_SEC_RTIC_LIODN_ENTRY(c, 550), + SET_SEC_RTIC_LIODN_ENTRY(d, 551), + SET_SEC_DECO_LIODN_ENTRY(0, 541, 610), + SET_SEC_DECO_LIODN_ENTRY(1, 542, 611), + SET_SEC_DECO_LIODN_ENTRY(2, 543, 612), + SET_SEC_DECO_LIODN_ENTRY(3, 544, 613), + SET_SEC_DECO_LIODN_ENTRY(4, 545, 614), + SET_SEC_DECO_LIODN_ENTRY(5, 546, 615), + SET_SEC_DECO_LIODN_ENTRY(6, 547, 616), + SET_SEC_DECO_LIODN_ENTRY(7, 548, 617), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_RMAN +struct liodn_id_table rman_liodn_tbl[] = { + /* Set RMan block 0-3 liodn offset */ + SET_RMAN_LIODN(0, 6), + SET_RMAN_LIODN(1, 7), + SET_RMAN_LIODN(2, 8), + SET_RMAN_LIODN(3, 9), +}; +int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); +#endif + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), +#endif +#ifdef CONFIG_SYS_DPAA_RMAN + [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922), +#endif +}; diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/b4860_serdes.c new file mode 100644 index 000000000..cf18be552 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/b4860_serdes.c @@ -0,0 +1,267 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_serdes.h> +#include <asm/processor.h> +#include <asm/io.h> +#include "fsl_corenet2_serdes.h" + +struct serdes_config { + u8 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +#ifdef CONFIG_PPC_B4860 +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x02, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x04, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x05, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x06, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x08, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x09, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x0A, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x0B, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x0C, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x0E, {CPRI8, CPRI7, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x12, {CPRI8, CPRI7, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x29, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x2D, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x2F, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x30, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x32, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x33, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x34, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x39, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x3A, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x3C, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x3D, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x3E, {CPRI8, CPRI7, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x5C, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x5D, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1} }, + {} +}; +static struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {0x17, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + AURORA, AURORA, SRIO1, SRIO1} }, + {0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + AURORA, AURORA, SRIO1, SRIO1}}, + {0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + AURORA, AURORA, SRIO1, SRIO1}}, + {0x2A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, + AURORA, AURORA, SRIO1, SRIO1} }, + {0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, + AURORA, AURORA, SRIO1, SRIO1}}, + {0x30, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, + AURORA, AURORA, + SRIO1, SRIO1}}, + {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + SRIO1, SRIO1, SRIO1, SRIO1} }, + {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {0x4C, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {0x79, {SRIO2, SRIO2, SRIO2, SRIO2, + SRIO1, SRIO1, SRIO1, SRIO1} }, + {0x7A, {SRIO2, SRIO2, SRIO2, SRIO2, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {0x83, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, AURORA, AURORA, + XFI_FM1_MAC9, XFI_FM1_MAC10} }, + {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, AURORA, AURORA, + XFI_FM1_MAC9, XFI_FM1_MAC10}}, + {0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, AURORA, AURORA, + XFI_FM1_MAC9, XFI_FM1_MAC10}}, + {0x86, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XFI_FM1_MAC9, XFI_FM1_MAC10} }, + {0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XFI_FM1_MAC9, XFI_FM1_MAC10}}, + {0x8C, {SRIO2, SRIO2, SRIO2, SRIO2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XFI_FM1_MAC9, XFI_FM1_MAC10} }, + {0x8D, {SRIO2, SRIO2, SRIO2, SRIO2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XFI_FM1_MAC9, XFI_FM1_MAC10}}, + {0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XAUI_FM1_MAC10, XAUI_FM1_MAC10, + XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, + {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1, + XAUI_FM1_MAC10, XAUI_FM1_MAC10, + XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, + {0x9A, {PCIE1, PCIE1, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XAUI_FM1_MAC10, XAUI_FM1_MAC10, + XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, + {0xB1, {PCIE1, PCIE1, PCIE1, PCIE1, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XFI_FM1_MAC9, XFI_FM1_MAC10} }, + {0xB2, {PCIE1, PCIE1, PCIE1, PCIE1, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XFI_FM1_MAC9, XFI_FM1_MAC10}}, + {0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, + XAUI_FM1_MAC9, XAUI_FM1_MAC9, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {0x98, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, + XAUI_FM1_MAC9, XAUI_FM1_MAC9, + XAUI_FM1_MAC10, XAUI_FM1_MAC10, + XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, + {} +}; +#endif + +#ifdef CONFIG_PPC_B4420 +static struct serdes_config serdes1_cfg_tbl[] = { + {0x0D, {NONE, NONE, CPRI6, CPRI5, + CPRI4, CPRI3, NONE, NONE} }, + {0x0E, {NONE, NONE, CPRI8, CPRI5, + CPRI4, CPRI3, NONE, NONE} }, + {0x0F, {NONE, NONE, CPRI6, CPRI5, + CPRI4, CPRI3, NONE, NONE} }, + {0x18, {NONE, NONE, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + NONE, NONE, NONE, NONE} }, + {0x1B, {NONE, NONE, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + NONE, NONE, NONE, NONE} }, + {0x1E, {NONE, NONE, AURORA, AURORA, + NONE, NONE, NONE, NONE} }, + {0x21, {NONE, NONE, AURORA, AURORA, + NONE, NONE, NONE, NONE} }, + {0x3E, {NONE, NONE, CPRI6, CPRI5, + CPRI4, CPRI3, NONE, NONE} }, + {} +}; +static struct serdes_config serdes2_cfg_tbl[] = { + {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + NONE, NONE, NONE, NONE} }, + {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + NONE, NONE, NONE, NONE} }, + {0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + AURORA, AURORA, NONE, NONE, NONE, NONE} }, + {0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + AURORA, AURORA, NONE, NONE, NONE, NONE} }, + {0x9A, {PCIE1, PCIE1, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + NONE, NONE, NONE, NONE} }, + {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1, + NONE, NONE, NONE, NONE} }, + {} +}; +#endif + +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, + serdes2_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c new file mode 100644 index 000000000..399b20889 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c @@ -0,0 +1,93 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * Author: Prabhakar Kushwaha <prabhakar@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 + +static u32 serdes1_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0] = {NONE, NONE, NONE, NONE}, + [1] = {PCIE1, PCIE2, CPRI2, CPRI1}, + [2] = {PCIE1, PCIE2, CPRI2, CPRI1}, + [3] = {PCIE1, PCIE2, CPRI2, CPRI1}, + [4] = {PCIE1, PCIE2, CPRI2, CPRI1}, + [5] = {PCIE1, PCIE2, CPRI2, CPRI1}, + [6] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1}, + [7] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1}, + [8] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1}, + [9] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1}, + [10] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1}, + [11] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2}, + [12] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1}, + [13] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1}, + [14] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1}, + [15] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1}, + [16] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1}, + [17] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1}, + [18] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1}, + [19] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1}, + [20] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1}, + [21] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1}, + [22] = {PCIE1, PCIE2, CPRI2, CPRI1}, + [23] = {PCIE1, PCIE2, CPRI2, CPRI1}, + [24] = {PCIE1, PCIE2, CPRI2, CPRI1}, + [25] = {PCIE1, PCIE2, CPRI2, CPRI1}, + [26] = {PCIE1, PCIE2, CPRI2, CPRI1}, + [27] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1}, + [28] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1}, + [29] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1}, + [30] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1}, + [31] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1}, + [32] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2}, + [33] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1}, + [34] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1}, + [35] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1}, + [36] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1}, + [37] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1}, + [38] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1}, + [39] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1}, + [40] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1}, + [41] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1}, + [42] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1}, + [43] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1}, + [44] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1}, + [45] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1}, + [46] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1}, + [47] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1}, +}; + +int is_serdes_configured(enum srds_prtcl prtcl) +{ + return (1 << prtcl) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/c29x_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/c29x_serdes.c new file mode 100644 index 000000000..51972cb7c --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/c29x_serdes.c @@ -0,0 +1,62 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 + +static u32 serdes1_prtcl_map; + +struct serdes_config { + u32 protocol; + u8 lanes[SRDS1_MAX_LANES]; +}; + +static const struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {1, {PCIE1, PCIE1, PCIE1, PCIE1} }, + {2, {PCIE1, PCIE1, PCIE1, PCIE1} }, + {3, {PCIE1, PCIE1, NONE, NONE} }, + {4, {PCIE1, PCIE1, NONE, NONE} }, + {5, {PCIE1, NONE, NONE, NONE} }, + {6, {PCIE1, NONE, NONE, NONE} }, + {} +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + return (1 << device) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + const struct serdes_config *ptr; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + ptr = &serdes1_cfg_tbl[srds_cfg]; + if (!ptr->protocol) + return; + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = ptr->lanes[lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/cache.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/cache.c new file mode 100644 index 000000000..66384f988 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/cache.c @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2012 Marek Vasut <marex@denx.de> + * + * This file contains stub implementation of + * invalidate_dcache_range() + * flush_dcache_range() + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/cmd_errata.c new file mode 100644 index 000000000..9d8acd0aa --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -0,0 +1,310 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <linux/compiler.h> +#include <asm/fsl_errata.h> +#include <asm/processor.h> +#include "fsl_corenet_serdes.h" + +#ifdef CONFIG_SYS_FSL_ERRATUM_A004849 +/* + * This work-around is implemented in PBI, so just check to see if the + * work-around was actually applied. To do this, we check for specific data + * at specific addresses in DCSR. + * + * Array offsets[] contains a list of offsets within DCSR. According to the + * erratum document, the value at each offset should be 2. + */ +static void check_erratum_a4849(uint32_t svr) +{ + void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000; + unsigned int i; + +#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041) + static const uint8_t offsets[] = { + 0x50, 0x54, 0x58, 0x90, 0x94, 0x98 + }; +#endif +#ifdef CONFIG_PPC_P4080 + static const uint8_t offsets[] = { + 0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac + }; +#endif + uint32_t x108; /* The value that should be at offset 0x108 */ + + for (i = 0; i < ARRAY_SIZE(offsets); i++) { + if (in_be32(dcsr + offsets[i]) != 2) { + printf("Work-around for Erratum A004849 is not enabled\n"); + return; + } + } + +#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041) + x108 = 0x12; +#endif + +#ifdef CONFIG_PPC_P4080 + /* + * For P4080, the erratum document says that the value at offset 0x108 + * should be 0x12 on rev2, or 0x1c on rev3. + */ + if (SVR_MAJ(svr) == 2) + x108 = 0x12; + if (SVR_MAJ(svr) == 3) + x108 = 0x1c; +#endif + + if (in_be32(dcsr + 0x108) != x108) { + printf("Work-around for Erratum A004849 is not enabled\n"); + return; + } + + /* Everything matches, so the erratum work-around was applied */ + + printf("Work-around for Erratum A004849 enabled\n"); +} +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A004580 +/* + * This work-around is implemented in PBI, so just check to see if the + * work-around was actually applied. To do this, we check for specific data + * at specific addresses in the SerDes register block. + * + * The work-around says that for each SerDes lane, write BnTTLCRy0 = + * 0x1B00_0001, Register 2 = 0x0088_0000, and Register 3 = 0x4000_0000. + + */ +static void check_erratum_a4580(uint32_t svr) +{ + const serdes_corenet_t __iomem *srds_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + unsigned int lane; + + for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + if (serdes_lane_enabled(lane)) { + const struct serdes_lane __iomem *srds_lane = + &srds_regs->lane[serdes_get_lane_idx(lane)]; + + /* + * Verify that the values we were supposed to write in + * the PBI are actually there. Also, the lower 15 + * bits of res4[3] should be the same as the upper 15 + * bits of res4[1]. + */ + if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) || + (in_be32(&srds_lane->res4[1]) != 0x880000) || + (in_be32(&srds_lane->res4[3]) != 0x40000044)) { + printf("Work-around for Erratum A004580 is " + "not enabled\n"); + return; + } + } + } + + /* Everything matches, so the erratum work-around was applied */ + + printf("Work-around for Erratum A004580 enabled\n"); +} +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 +/* + * This workaround can be implemented in PBI, or by u-boot. + */ +static void check_erratum_a007212(void) +{ + u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); + + if (in_be32(plldgdcr) & 0x1fe) { + /* check if PLL ratio is set by workaround */ + puts("Work-around for Erratum A007212 enabled\n"); + } +} +#endif + +static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 + extern int enable_cpu_a011_workaround; +#endif + __maybe_unused u32 svr = get_svr(); + +#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) + if (IS_SVR_REV(svr, 1, 0)) { + switch (SVR_SOC_VER(svr)) { + case SVR_P1013: + case SVR_P1022: + puts("Work-around for Erratum SATA A001 enabled\n"); + } + } +#endif + +#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) + puts("Work-around for Erratum SERDES8 enabled\n"); +#endif +#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) + puts("Work-around for Erratum SERDES9 enabled\n"); +#endif +#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005) + puts("Work-around for Erratum SERDES-A005 enabled\n"); +#endif +#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) + if (SVR_MAJ(svr) < 3) + puts("Work-around for Erratum CPU22 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 + /* + * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 + * The SVR has been checked by cpu_init_r(). + */ + if (enable_cpu_a011_workaround) + puts("Work-around for Erratum CPU-A011 enabled\n"); +#endif +#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999) + puts("Work-around for Erratum CPU-A003999 enabled\n"); +#endif +#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474) + puts("Work-around for Erratum DDR-A003474 enabled\n"); +#endif +#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) + puts("Work-around for DDR MSYNC_IN Erratum enabled\n"); +#endif +#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111) + puts("Work-around for Erratum ESDHC111 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004468 + puts("Work-around for Erratum A004468 enabled\n"); +#endif +#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135) + puts("Work-around for Erratum ESDHC135 enabled\n"); +#endif +#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13) + if (SVR_MAJ(svr) < 3) + puts("Work-around for Erratum ESDHC13 enabled\n"); +#endif +#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001) + puts("Work-around for Erratum ESDHC-A001 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 + puts("Work-around for Erratum CPC-A002 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 + puts("Work-around for Erratum CPC-A003 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001 + puts("Work-around for Erratum ELBC-A001 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 + puts("Work-around for Erratum DDR-A003 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115 + puts("Work-around for Erratum DDR115 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 + puts("Work-around for Erratum DDR111 enabled\n"); + puts("Work-around for Erratum DDR134 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 + puts("Work-around for Erratum IFC-A002769 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 + puts("Work-around for Erratum P1010-A003549 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 + puts("Work-around for Erratum IFC A-003399 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 + if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) + puts("Work-around for Erratum NMG DDR120 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 + puts("Work-around for Erratum NMG_LBC103 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 + if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) + puts("Work-around for Erratum NMG ETSEC129 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 + puts("Work-around for Erratum A004510 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 + puts("Work-around for Erratum SRIO-A004034 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934 + puts("Work-around for Erratum A004934 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005871 + if (IS_SVR_REV(svr, 1, 0)) + puts("Work-around for Erratum A005871 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006475 + if (SVR_MAJ(get_svr()) == 1) + puts("Work-around for Erratum A006475 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006384 + if (SVR_MAJ(get_svr()) == 1) + puts("Work-around for Erratum A006384 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004849 + /* This work-around is implemented in PBI, so just check for it */ + check_erratum_a4849(svr); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004580 + /* This work-around is implemented in PBI, so just check for it */ + check_erratum_a4580(svr); +#endif +#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 + puts("Work-around for Erratum PCIe-A003 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_USB14 + puts("Work-around for Erratum USB14 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006593 + puts("Work-around for Erratum A006593 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 + if (has_erratum_a006379()) + puts("Work-around for Erratum A006379 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 + if (IS_SVR_REV(svr, 1, 0)) + puts("Work-around for Erratum A003571 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005812 + puts("Work-around for Erratum A-005812 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005125 + puts("Work-around for Erratum A005125 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007075 + if (has_erratum_a007075()) + puts("Work-around for Erratum A007075 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 + if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) || + (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) + puts("Work-around for Erratum I2C-A004447 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 + if (has_erratum_a006261()) + puts("Work-around for Erratum A006261 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 + check_erratum_a007212(); +#endif + + return 0; +} + +U_BOOT_CMD( + errata, 1, 0, do_errata, + "Report errata workarounds", + "" +); diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/commproc.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/commproc.c new file mode 100644 index 000000000..37e706238 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/commproc.c @@ -0,0 +1,186 @@ +/* + * Adapted for Motorola MPC8560 chips + * Xianghua Xiao <x.xiao@motorola.com> + * + * This file is based on "arch/powerpc/8260_io/commproc.c" - here is it's + * copyright notice: + * + * General Purpose functions for the global management of the + * 8220 Communication Processor Module. + * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) + * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) + * 2.3.99 Updates + * Copyright (c) 2003 Motorola,Inc. + * + * In addition to the individual control of the communication + * channels, there are a few functions that globally affect the + * communication processor. + * + * Buffer descriptors must be allocated from the dual ported memory + * space. The allocator for that is here. When the communication + * process is reset, we reclaim the memory available. There is + * currently no deallocator for this memory. + */ +#include <common.h> +#include <asm/cpm_85xx.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * because we have stack and init data in dual port ram + * we must reduce the size + */ +#undef CPM_DATAONLY_SIZE +#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) + +void +m8560_cpm_reset(void) +{ + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; + volatile ulong count; + + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + + /* Reclaim the DP memory for our use. + */ + gd->arch.dp_alloc_base = CPM_DATAONLY_BASE; + gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE; + + /* + * Reset CPM + */ + cpm->im_cpm_cp.cpcr = CPM_CR_RST; + count = 0; + do { /* Spin until command processed */ + __asm__ __volatile__ ("eieio"); + } while ((cpm->im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000); +} + +/* Allocate some memory from the dual ported ram. + * To help protocols with object alignment restrictions, we do that + * if they ask. + */ +uint +m8560_cpm_dpalloc(uint size, uint align) +{ + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; + uint retloc; + uint align_mask, off; + uint savebase; + + align_mask = align - 1; + savebase = gd->arch.dp_alloc_base; + + off = gd->arch.dp_alloc_base & align_mask; + if (off != 0) + gd->arch.dp_alloc_base += (align - off); + + if ((off = size & align_mask) != 0) + size += align - off; + + if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) { + gd->arch.dp_alloc_base = savebase; + panic("m8560_cpm_dpalloc: ran out of dual port ram!"); + } + + retloc = gd->arch.dp_alloc_base; + gd->arch.dp_alloc_base += size; + + memset((void *)&(cpm->im_dprambase[retloc]), 0, size); + + return(retloc); +} + +/* We also own one page of host buffer space for the allocation of + * UART "fifos" and the like. + */ +uint +m8560_cpm_hostalloc(uint size, uint align) +{ + /* the host might not even have RAM yet - just use dual port RAM */ + return (m8560_cpm_dpalloc(size, align)); +} + +/* Set a baud rate generator. This needs lots of work. There are + * eight BRGs, which can be connected to the CPM channels or output + * as clocks. The BRGs are in two different block of internal + * memory mapped space. + * The baud rate clock is the system clock divided by something. + * It was set up long ago during the initial boot phase and is + * is given to us. + * Baud rate clocks are zero-based in the driver code (as that maps + * to port numbers). Documentation uses 1-based numbering. + */ +#define BRG_INT_CLK gd->arch.brg_clk +#define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16) + +/* This function is used by UARTS, or anything else that uses a 16x + * oversampled clock. + */ +void +m8560_cpm_setbrg(uint brg, uint rate) +{ + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; + volatile uint *bp; + + /* This is good enough to get SMCs running..... + */ + if (brg < 4) { + bp = (uint *)&(cpm->im_cpm_brg1.brgc1); + } + else { + bp = (uint *)&(cpm->im_cpm_brg2.brgc5); + brg -= 4; + } + bp += brg; + *bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; +} + +/* This function is used to set high speed synchronous baud rate + * clocks. + */ +void +m8560_cpm_fastbrg(uint brg, uint rate, int div16) +{ + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; + volatile uint *bp; + + /* This is good enough to get SMCs running..... + */ + if (brg < 4) { + bp = (uint *)&(cpm->im_cpm_brg1.brgc1); + } + else { + bp = (uint *)&(cpm->im_cpm_brg2.brgc5); + brg -= 4; + } + bp += brg; + *bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; + if (div16) + *bp |= CPM_BRG_DIV16; +} + +/* This function is used to set baud rate generators using an external + * clock source and 16x oversampling. + */ + +void +m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel) +{ + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; + volatile uint *bp; + + if (brg < 4) { + bp = (uint *)&(cpm->im_cpm_brg1.brgc1); + } + else { + bp = (uint *)&(cpm->im_cpm_brg2.brgc5); + brg -= 4; + } + bp += brg; + *bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; + if (pinsel == 0) + *bp |= CPM_BRG_EXTC_CLK3_9; + else + *bp |= CPM_BRG_EXTC_CLK5_15; +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/config.mk b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/config.mk new file mode 100644 index 000000000..1470f95ff --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/config.mk @@ -0,0 +1,14 @@ +# +# (C) Copyright 2002,2003 Motorola Inc. +# Xianghua Xiao, X.Xiao@motorola.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -Wa,-me500 -msoft-float -mno-string + +# -mspe=yes is needed to have -mno-spe accepted by a buggy GCC; +# see "[PATCH,rs6000] make -mno-spe work as expected" on +# http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html +PLATFORM_CPPFLAGS += $(call cc-option,-mspe=yes) \ + $(call cc-option,-mno-spe) diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/cpu.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/cpu.c new file mode 100644 index 000000000..684d4007e --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/cpu.c @@ -0,0 +1,648 @@ +/* + * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. + * (C) Copyright 2002, 2003 Motorola Inc. + * Xianghua Xiao (X.Xiao@motorola.com) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <watchdog.h> +#include <command.h> +#include <fsl_esdhc.h> +#include <asm/cache.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <fsl_ifc.h> +#include <asm/fsl_law.h> +#include <asm/fsl_lbc.h> +#include <post.h> +#include <asm/processor.h> +#include <fsl_ddr_sdram.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Default board reset function + */ +static void +__board_reset(void) +{ + /* Do nothing */ +} +void board_reset(void) __attribute__((weak, alias("__board_reset"))); + +int checkcpu (void) +{ + sys_info_t sysinfo; + uint pvr, svr; + uint ver; + uint major, minor; + struct cpu_type *cpu; + char buf1[32], buf2[32]; +#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) + ccsr_gur_t __iomem *gur = + (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif + + /* + * Cornet platforms use ddr sync bit in RCW to indicate sync vs async + * mode. Previous platform use ddr ratio to do the same. This + * information is only for display here. + */ +#ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 + u32 ddr_sync = 0; /* only async mode is supported */ +#else + u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) + >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; +#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ +#else /* CONFIG_FSL_CORENET */ +#ifdef CONFIG_DDR_CLK_FREQ + u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) + >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; +#else + u32 ddr_ratio = 0; +#endif /* CONFIG_DDR_CLK_FREQ */ +#endif /* CONFIG_FSL_CORENET */ + + unsigned int i, core, nr_cores = cpu_numcores(); + u32 mask = cpu_mask(); + + svr = get_svr(); + major = SVR_MAJ(svr); + minor = SVR_MIN(svr); + +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) + if (SVR_SOC_VER(svr) == SVR_T4080) { + ccsr_rcpm_t *rcpm = + (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); + + setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 || + FSL_CORENET_DEVDISR2_DTSEC1_9); + setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3); + setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3); + + /* It needs SW to disable core4~7 as HW design sake on T4080 */ + for (i = 4; i < 8; i++) + cpu_disable(i); + + /* request core4~7 into PH20 state, prior to entering PCL10 + * state, all cores in cluster should be placed in PH20 state. + */ + setbits_be32(&rcpm->pcph20setr, 0xf0); + + /* put the 2nd cluster into PCL10 state */ + setbits_be32(&rcpm->clpcl10setr, 1 << 1); + } +#endif + + if (cpu_numcores() > 1) { +#ifndef CONFIG_MP + puts("Unicore software on multiprocessor system!!\n" + "To enable mutlticore build define CONFIG_MP\n"); +#endif + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); + printf("CPU%d: ", pic->whoami); + } else { + puts("CPU: "); + } + + cpu = gd->arch.cpu; + + puts(cpu->name); + if (IS_E_PROCESSOR(svr)) + puts("E"); + + printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); + + pvr = get_pvr(); + ver = PVR_VER(pvr); + major = PVR_MAJ(pvr); + minor = PVR_MIN(pvr); + + printf("Core: "); + switch(ver) { + case PVR_VER_E500_V1: + case PVR_VER_E500_V2: + puts("e500"); + break; + case PVR_VER_E500MC: + puts("e500mc"); + break; + case PVR_VER_E5500: + puts("e5500"); + break; + case PVR_VER_E6500: + puts("e6500"); + break; + default: + puts("Unknown"); + break; + } + + printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); + + if (nr_cores > CONFIG_MAX_CPUS) { + panic("\nUnexpected number of cores: %d, max is %d\n", + nr_cores, CONFIG_MAX_CPUS); + } + + get_sys_info(&sysinfo); + +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + if (sysinfo.diff_sysclk == 1) + puts("Single Source Clock Configuration\n"); +#endif + + puts("Clock Configuration:"); + for_each_cpu(i, core, nr_cores, mask) { + if (!(i & 3)) + printf ("\n "); + printf("CPU%d:%-4s MHz, ", core, + strmhz(buf1, sysinfo.freq_processor[core])); + } + printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus)); + printf("\n"); + +#ifdef CONFIG_FSL_CORENET + if (ddr_sync == 1) { + printf(" DDR:%-4s MHz (%s MT/s data rate) " + "(Synchronous), ", + strmhz(buf1, sysinfo.freq_ddrbus/2), + strmhz(buf2, sysinfo.freq_ddrbus)); + } else { + printf(" DDR:%-4s MHz (%s MT/s data rate) " + "(Asynchronous), ", + strmhz(buf1, sysinfo.freq_ddrbus/2), + strmhz(buf2, sysinfo.freq_ddrbus)); + } +#else + switch (ddr_ratio) { + case 0x0: + printf(" DDR:%-4s MHz (%s MT/s data rate), ", + strmhz(buf1, sysinfo.freq_ddrbus/2), + strmhz(buf2, sysinfo.freq_ddrbus)); + break; + case 0x7: + printf(" DDR:%-4s MHz (%s MT/s data rate) " + "(Synchronous), ", + strmhz(buf1, sysinfo.freq_ddrbus/2), + strmhz(buf2, sysinfo.freq_ddrbus)); + break; + default: + printf(" DDR:%-4s MHz (%s MT/s data rate) " + "(Asynchronous), ", + strmhz(buf1, sysinfo.freq_ddrbus/2), + strmhz(buf2, sysinfo.freq_ddrbus)); + break; + } +#endif + +#if defined(CONFIG_FSL_LBC) + if (sysinfo.freq_localbus > LCRR_CLKDIV) { + printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); + } else { + printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", + sysinfo.freq_localbus); + } +#endif + +#if defined(CONFIG_FSL_IFC) + printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); +#endif + +#ifdef CONFIG_CPM2 + printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus)); +#endif + +#ifdef CONFIG_QE + printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe)); +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN + for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { + printf(" FMAN%d: %s MHz\n", i + 1, + strmhz(buf1, sysinfo.freq_fman[i])); + } +#endif + +#ifdef CONFIG_SYS_DPAA_QBMAN + printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman)); +#endif + +#ifdef CONFIG_SYS_DPAA_PME + printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme)); +#endif + + puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n"); + +#ifdef CONFIG_FSL_CORENET + /* Display the RCW, so that no one gets confused as to what RCW + * we're actually using for this boot. + */ + puts("Reset Configuration Word (RCW):"); + for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { + u32 rcw = in_be32(&gur->rcwsr[i]); + + if ((i % 4) == 0) + printf("\n %08x:", i * 4); + printf(" %08x", rcw); + } + puts("\n"); +#endif + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ +/* Everything after the first generation of PQ3 parts has RSTCR */ +#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560) + unsigned long val, msr; + + /* + * Initiate hard reset in debug control register DBCR0 + * Make sure MSR[DE] = 1. This only resets the core. + */ + msr = mfmsr (); + msr |= MSR_DE; + mtmsr (msr); + + val = mfspr(DBCR0); + val |= 0x70000000; + mtspr(DBCR0,val); +#else + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* Attempt board-specific reset */ + board_reset(); + + /* Next try asserting HRESET_REQ */ + out_be32(&gur->rstcr, 0x2); + udelay(100); +#endif + + return 1; +} + + +/* + * Get timebase clock frequency + */ +#ifndef CONFIG_SYS_FSL_TBCLK_DIV +#define CONFIG_SYS_FSL_TBCLK_DIV 8 +#endif +__weak unsigned long get_tbclk (void) +{ + unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; + + return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; +} + + +#if defined(CONFIG_WATCHDOG) +void +reset_85xx_watchdog(void) +{ + /* + * Clear TSR(WIS) bit by writing 1 + */ + mtspr(SPRN_TSR, TSR_WIS); +} + +void +watchdog_reset(void) +{ + int re_enable = disable_interrupts(); + + reset_85xx_watchdog(); + if (re_enable) + enable_interrupts(); +} +#endif /* CONFIG_WATCHDOG */ + +/* + * Initializes on-chip MMC controllers. + * to override, implement board_mmc_init() + */ +int cpu_mmc_init(bd_t *bis) +{ +#ifdef CONFIG_FSL_ESDHC + return fsl_esdhc_mmc_init(bis); +#else + return 0; +#endif +} + +/* + * Print out the state of various machine registers. + * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing + * parameters for IFC and TLBs + */ +void mpc85xx_reginfo(void) +{ + print_tlbcam(); + print_laws(); +#if defined(CONFIG_FSL_LBC) + print_lbc_regs(); +#endif +#ifdef CONFIG_FSL_IFC + print_ifc_regs(); +#endif + +} + +/* Common ddr init for non-corenet fsl 85xx platforms */ +#ifndef CONFIG_FSL_CORENET +#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \ + !defined(CONFIG_SYS_INIT_L2_ADDR) +phys_size_t initdram(int board_type) +{ +#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \ + defined(CONFIG_QEMU_E500) + return fsl_ddr_sdram_size(); +#else + return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; +#endif +} +#else /* CONFIG_SYS_RAMBOOT */ +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = 0; + +#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) + { + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + unsigned int x = 10; + unsigned int i; + + /* + * Work around to stabilize DDR DLL + */ + out_be32(&gur->ddrdllcr, 0x81000000); + asm("sync;isync;msync"); + udelay(200); + while (in_be32(&gur->ddrdllcr) != 0x81000100) { + setbits_be32(&gur->devdisr, 0x00010000); + for (i = 0; i < x; i++) + ; + clrbits_be32(&gur->devdisr, 0x00010000); + x++; + } + } +#endif + +#if defined(CONFIG_SPD_EEPROM) || \ + defined(CONFIG_DDR_SPD) || \ + defined(CONFIG_SYS_DDR_RAW_TIMING) + dram_size = fsl_ddr_sdram(); +#else + dram_size = fixed_sdram(); +#endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + +#if defined(CONFIG_FSL_LBC) + /* Some boards also have sdram on the lbc */ + lbc_sdram_init(); +#endif + + debug("DDR: "); + return dram_size; +} +#endif /* CONFIG_SYS_RAMBOOT */ +#endif + +#if CONFIG_POST & CONFIG_SYS_POST_MEMORY + +/* Board-specific functions defined in each board's ddr.c */ +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num); +void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, + phys_addr_t *rpn); +unsigned int + setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); + +void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); + +static void dump_spd_ddr_reg(void) +{ + int i, j, k, m; + u8 *p_8; + u32 *p_32; + struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS]; + generic_spd_eeprom_t + spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; + + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + fsl_ddr_get_spd(spd[i], i); + + puts("SPD data of all dimms (zero vaule is omitted)...\n"); + puts("Byte (hex) "); + k = 1; + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) + printf("Dimm%d ", k++); + } + puts("\n"); + for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) { + m = 0; + printf("%3d (0x%02x) ", k, k); + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + p_8 = (u8 *) &spd[i][j]; + if (p_8[k]) { + printf("0x%02x ", p_8[k]); + m++; + } else + puts(" "); + } + } + if (m) + puts("\n"); + else + puts("\r"); + } + + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + switch (i) { + case 0: + ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR; + break; +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) + case 1: + ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR; + break; +#endif +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) + case 2: + ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR; + break; +#endif +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) + case 3: + ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR; + break; +#endif + default: + printf("%s unexpected controller number = %u\n", + __func__, i); + return; + } + } + printf("DDR registers dump for all controllers " + "(zero vaule is omitted)...\n"); + puts("Offset (hex) "); + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); + puts("\n"); + for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) { + m = 0; + printf("%6d (0x%04x)", k * 4, k * 4); + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + p_32 = (u32 *) ddr[i]; + if (p_32[k]) { + printf(" 0x%08x", p_32[k]); + m++; + } else + puts(" "); + } + if (m) + puts("\n"); + else + puts("\r"); + } + puts("\n"); +} + +/* invalid the TLBs for DDR and setup new ones to cover p_addr */ +static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) +{ + u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; + unsigned long epn; + u32 tsize, valid, ptr; + int ddr_esel; + + clear_ddr_tlbs_phys(p_addr, size>>20); + + /* Setup new tlb to cover the physical address */ + setup_ddr_tlbs_phys(p_addr, size>>20); + + ptr = vstart; + ddr_esel = find_tlb_idx((void *)ptr, 1); + if (ddr_esel != -1) { + read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset); + } else { + printf("TLB error in function %s\n", __func__); + return -1; + } + + return 0; +} + +/* + * slide the testing window up to test another area + * for 32_bit system, the maximum testable memory is limited to + * CONFIG_MAX_MEM_MAPPED + */ +int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) +{ + phys_addr_t test_cap, p_addr; + phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); + +#if !defined(CONFIG_PHYS_64BIT) || \ + !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ + (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) + test_cap = p_size; +#else + test_cap = gd->ram_size; +#endif + p_addr = (*vstart) + (*size) + (*phys_offset); + if (p_addr < test_cap - 1) { + p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); + if (reset_tlb(p_addr, p_size, phys_offset) == -1) + return -1; + *vstart = CONFIG_SYS_DDR_SDRAM_BASE; + *size = (u32) p_size; + printf("Testing 0x%08llx - 0x%08llx\n", + (u64)(*vstart) + (*phys_offset), + (u64)(*vstart) + (*phys_offset) + (*size) - 1); + } else + return 1; + + return 0; +} + +/* initialization for testing area */ +int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) +{ + phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); + + *vstart = CONFIG_SYS_DDR_SDRAM_BASE; + *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ + *phys_offset = 0; + +#if !defined(CONFIG_PHYS_64BIT) || \ + !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ + (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) + if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { + puts("Cannot test more than "); + print_size(CONFIG_MAX_MEM_MAPPED, + " without proper 36BIT support.\n"); + } +#endif + printf("Testing 0x%08llx - 0x%08llx\n", + (u64)(*vstart) + (*phys_offset), + (u64)(*vstart) + (*phys_offset) + (*size) - 1); + + return 0; +} + +/* invalid TLBs for DDR and remap as normal after testing */ +int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset) +{ + unsigned long epn; + u32 tsize, valid, ptr; + phys_addr_t rpn = 0; + int ddr_esel; + + /* disable the TLBs for this testing */ + ptr = *vstart; + + while (ptr < (*vstart) + (*size)) { + ddr_esel = find_tlb_idx((void *)ptr, 1); + if (ddr_esel != -1) { + read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); + disable_tlb(ddr_esel); + } + ptr += TSIZE_TO_BYTES(tsize); + } + + puts("Remap DDR "); + setup_ddr_tlbs(gd->ram_size>>20); + puts("\n"); + + return 0; +} + +void arch_memory_failure_handle(void) +{ + dump_spd_ddr_reg(); +} +#endif diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/cpu_init.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/cpu_init.c new file mode 100644 index 000000000..d6cf88555 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -0,0 +1,940 @@ +/* + * Copyright 2007-2011 Freescale Semiconductor, Inc. + * + * (C) Copyright 2003 Motorola Inc. + * Modified by Xianghua Xiao, X.Xiao@motorola.com + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/processor.h> +#include <ioports.h> +#include <sata.h> +#include <fm_eth.h> +#include <asm/io.h> +#include <asm/cache.h> +#include <asm/mmu.h> +#include <asm/fsl_errata.h> +#include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_srio.h> +#include <fsl_usb.h> +#include <hwconfig.h> +#include <linux/compiler.h> +#include "mp.h" +#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND +#include <nand.h> +#include <errno.h> +#endif + +#include "../../../../drivers/block/fsl_sata.h" +#ifdef CONFIG_U_QE +#include "../../../../drivers/qe/qe.h" +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK +/* + * For deriving usb clock from 100MHz sysclk, reference divisor is set + * to a value of 5, which gives an intermediate value 20(100/5). The + * multiplication factor integer is set to 24, which when multiplied to + * above intermediate value provides clock for usb ip. + */ +void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy) +{ + sys_info_t sysinfo; + + get_sys_info(&sysinfo); + if (sysinfo.diff_sysclk == 1) { + clrbits_be32(&usb_phy->pllprg[1], + CONFIG_SYS_FSL_USB_PLLPRG2_MFI); + setbits_be32(&usb_phy->pllprg[1], + CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK | + CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK | + CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN); + } +} +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 +void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) +{ +#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE + u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg); + + /* Increase Disconnect Threshold by 50mV */ + xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | + INC_DCNT_THRESHOLD_50MV; + /* Enable programming of USB High speed Disconnect threshold */ + xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; + out_be32(&usb_phy->port1.xcvrprg, xcvrprg); + + xcvrprg = in_be32(&usb_phy->port2.xcvrprg); + /* Increase Disconnect Threshold by 50mV */ + xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK | + INC_DCNT_THRESHOLD_50MV; + /* Enable programming of USB High speed Disconnect threshold */ + xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN; + out_be32(&usb_phy->port2.xcvrprg, xcvrprg); +#else + + u32 temp = 0; + u32 status = in_be32(&usb_phy->status1); + + u32 squelch_prog_rd_0_2 = + (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0) + & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; + + u32 squelch_prog_rd_3_5 = + (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3) + & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK; + + setbits_be32(&usb_phy->config1, + CONFIG_SYS_FSL_USB_HS_DISCNCT_INC); + setbits_be32(&usb_phy->config2, + CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL); + + temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0; + out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); + + temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3; + out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); +#endif +} +#endif + + +#if defined(CONFIG_QE) && !defined(CONFIG_U_QE) +extern qe_iop_conf_t qe_iop_conf_tab[]; +extern void qe_config_iopin(u8 port, u8 pin, int dir, + int open_drain, int assign); +extern void qe_init(uint qe_base); +extern void qe_reset(void); + +static void config_qe_ioports(void) +{ + u8 port, pin; + int dir, open_drain, assign; + int i; + + for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { + port = qe_iop_conf_tab[i].port; + pin = qe_iop_conf_tab[i].pin; + dir = qe_iop_conf_tab[i].dir; + open_drain = qe_iop_conf_tab[i].open_drain; + assign = qe_iop_conf_tab[i].assign; + qe_config_iopin(port, pin, dir, open_drain, assign); + } +} +#endif + +#ifdef CONFIG_CPM2 +void config_8560_ioports (volatile ccsr_cpm_t * cpm) +{ + int portnum; + + for (portnum = 0; portnum < 4; portnum++) { + uint pmsk = 0, + ppar = 0, + psor = 0, + pdir = 0, + podr = 0, + pdat = 0; + iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; + iop_conf_t *eiopc = iopc + 32; + uint msk = 1; + + /* + * NOTE: + * index 0 refers to pin 31, + * index 31 refers to pin 0 + */ + while (iopc < eiopc) { + if (iopc->conf) { + pmsk |= msk; + if (iopc->ppar) + ppar |= msk; + if (iopc->psor) + psor |= msk; + if (iopc->pdir) + pdir |= msk; + if (iopc->podr) + podr |= msk; + if (iopc->pdat) + pdat |= msk; + } + + msk <<= 1; + iopc++; + } + + if (pmsk != 0) { + volatile ioport_t *iop = ioport_addr (cpm, portnum); + uint tpmsk = ~pmsk; + + /* + * the (somewhat confused) paragraph at the + * bottom of page 35-5 warns that there might + * be "unknown behaviour" when programming + * PSORx and PDIRx, if PPARx = 1, so I + * decided this meant I had to disable the + * dedicated function first, and enable it + * last. + */ + iop->ppar &= tpmsk; + iop->psor = (iop->psor & tpmsk) | psor; + iop->podr = (iop->podr & tpmsk) | podr; + iop->pdat = (iop->pdat & tpmsk) | pdat; + iop->pdir = (iop->pdir & tpmsk) | pdir; + iop->ppar |= ppar; + } + } +} +#endif + +#ifdef CONFIG_SYS_FSL_CPC +#if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F) +static void disable_cpc_sram(void) +{ + int i; + + cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; + + for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { + /* find and disable LAW of SRAM */ + struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); + + if (law.index == -1) { + printf("\nFatal error happened\n"); + return; + } + disable_law(law.index); + + clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); + out_be32(&cpc->cpccsr0, 0); + out_be32(&cpc->cpcsrcr0, 0); + } + } +} +#endif + +static void enable_cpc(void) +{ + int i; + u32 size = 0; + + cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; + + for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + u32 cpccfg0 = in_be32(&cpc->cpccfg0); + size += CPC_CFG0_SZ_K(cpccfg0); + +#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 + setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 + setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006593 + setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 + if (has_erratum_a006379()) { + setbits_be32(&cpc->cpchdbcr0, + CPC_HDBCR0_SPLRU_LEVEL_EN); + } +#endif + + out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); + /* Read back to sync write */ + in_be32(&cpc->cpccsr0); + + } + + puts("Corenet Platform Cache: "); + print_size(size * 1024, " enabled\n"); +} + +static void invalidate_cpc(void) +{ + int i; + cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; + + for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + /* skip CPC when it used as all SRAM */ + if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) + continue; + /* Flash invalidate the CPC and clear all the locks */ + out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); + while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) + ; + } +} +#else +#define enable_cpc() +#define invalidate_cpc() +#endif /* CONFIG_SYS_FSL_CPC */ + +/* + * Breathe some life into the CPU... + * + * Set up the memory map + * initialize a bunch of registers + */ + +#ifdef CONFIG_FSL_CORENET +static void corenet_tb_init(void) +{ + volatile ccsr_rcpm_t *rcpm = + (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); + volatile ccsr_pic_t *pic = + (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); + u32 whoami = in_be32(&pic->whoami); + + /* Enable the timebase register for this core */ + out_be32(&rcpm->ctbenrl, (1 << whoami)); +} +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 +void fsl_erratum_a007212_workaround(void) +{ + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 ddr_pll_ratio; + u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); + u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); + u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) + u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40); + u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) + u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60); + u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); +#endif +#endif + /* + * Even this workaround applies to selected version of SoCs, it is + * safe to apply to all versions, with the limitation of odd ratios. + * If RCW has disabled DDR PLL, we have to apply this workaround, + * otherwise DDR will not work. + */ + ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> + FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & + FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; + /* check if RCW sets ratio to 0, required by this workaround */ + if (ddr_pll_ratio != 0) + return; + ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> + FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & + FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; + /* check if reserved bits have the desired ratio */ + if (ddr_pll_ratio == 0) { + printf("Error: Unknown DDR PLL ratio!\n"); + return; + } + ddr_pll_ratio >>= 1; + + setbits_be32(plldadcr1, 0x02000001); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) + setbits_be32(plldadcr2, 0x02000001); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) + setbits_be32(plldadcr3, 0x02000001); +#endif +#endif + setbits_be32(dpdovrcr4, 0xe0000000); + out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1)); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) + out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1)); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) + out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1)); +#endif +#endif + udelay(100); + clrbits_be32(plldadcr1, 0x02000001); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) + clrbits_be32(plldadcr2, 0x02000001); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) + clrbits_be32(plldadcr3, 0x02000001); +#endif +#endif + clrbits_be32(dpdovrcr4, 0xe0000000); +} +#endif + +ulong cpu_init_f(void) +{ + ulong flag = 0; + extern void m8560_cpm_reset (void); +#ifdef CONFIG_SYS_DCSRBAR_PHYS + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif +#if defined(CONFIG_SECURE_BOOT) + struct law_entry law; +#endif +#ifdef CONFIG_MPC8548 + ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + uint svr = get_svr(); + + /* + * CPU2 errata workaround: A core hang possible while executing + * a msync instruction and a snoopable transaction from an I/O + * master tagged to make quick forward progress is present. + * Fixed in silicon rev 2.1. + */ + if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) + out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); +#endif + + disable_tlb(14); + disable_tlb(15); + +#if defined(CONFIG_SECURE_BOOT) + /* Disable the LAW created for NOR flash by the PBI commands */ + law = find_law(CONFIG_SYS_PBI_FLASH_BASE); + if (law.index != -1) + disable_law(law.index); + +#if defined(CONFIG_SYS_CPC_REINIT_F) + disable_cpc_sram(); +#endif +#endif + +#ifdef CONFIG_CPM2 + config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); +#endif + + init_early_memctl_regs(); + +#if defined(CONFIG_CPM2) + m8560_cpm_reset(); +#endif + +#if defined(CONFIG_QE) && !defined(CONFIG_U_QE) + /* Config QE ioports */ + config_qe_ioports(); +#endif + +#if defined(CONFIG_FSL_DMA) + dma_init(); +#endif +#ifdef CONFIG_FSL_CORENET + corenet_tb_init(); +#endif + init_used_tlb_cams(); + + /* Invalidate the CPC before DDR gets enabled */ + invalidate_cpc(); + + #ifdef CONFIG_SYS_DCSRBAR_PHYS + /* set DCSRCR so that DCSR space is 1G */ + setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); + in_be32(&gur->dcsrcr); +#endif + +#ifdef CONFIG_SYS_DCSRBAR_PHYS +#ifdef CONFIG_DEEP_SLEEP + /* disable the console if boot from deep sleep */ + if (in_be32(&gur->scrtsr[0]) & (1 << 3)) + flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; +#endif +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 + fsl_erratum_a007212_workaround(); +#endif + + return flag; +} + +/* Implement a dummy function for those platforms w/o SERDES */ +static void __fsl_serdes__init(void) +{ + return ; +} +__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); + +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) +int enable_cluster_l2(void) +{ + int i = 0; + u32 cluster, svr = get_svr(); + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + struct ccsr_cluster_l2 __iomem *l2cache; + + /* only the L2 of first cluster should be enabled as expected on T4080, + * but there is no EOC in the first cluster as HW sake, so return here + * to skip enabling L2 cache of the 2nd cluster. + */ + if (SVR_SOC_VER(svr) == SVR_T4080) + return 0; + + cluster = in_be32(&gur->tp_cluster[i].lower); + if (cluster & TP_CLUSTER_EOC) + return 0; + + /* The first cache has already been set up, so skip it */ + i++; + + /* Look through the remaining clusters, and set up their caches */ + do { + int j, cluster_valid = 0; + + l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); + + cluster = in_be32(&gur->tp_cluster[i].lower); + + /* check that at least one core/accel is enabled in cluster */ + for (j = 0; j < 4; j++) { + u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; + u32 type = in_be32(&gur->tp_ityp[idx]); + + if (type & TP_ITYP_AV) + cluster_valid = 1; + } + + if (cluster_valid) { + /* set stash ID to (cluster) * 2 + 32 + 1 */ + clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); + + printf("enable l2 for cluster %d %p\n", i, l2cache); + + out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); + while ((in_be32(&l2cache->l2csr0) + & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) + ; + out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); + } + i++; + } while (!(cluster & TP_CLUSTER_EOC)); + + return 0; +} +#endif + +/* + * Initialize L2 as cache. + * + * The newer 8548, etc, parts have twice as much cache, but + * use the same bit-encoding as the older 8555, etc, parts. + * + */ +int cpu_init_r(void) +{ + __maybe_unused u32 svr = get_svr(); +#ifdef CONFIG_SYS_LBC_LCRR + fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; +#endif +#ifdef CONFIG_L2_CACHE + ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; +#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) + struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; +#endif +#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) + extern int spin_table_compat; + const char *spin; +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 + ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; +#endif +#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ + defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) + /* + * CPU22 and NMG_CPU_A011 share the same workaround. + * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both + * fixed in 2.0. NMG_CPU_A011 is activated by default and can + * be disabled by hwconfig with syntax: + * + * fsl_cpu_a011:disable + */ + extern int enable_cpu_a011_workaround; +#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 + enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); +#else + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; + int n, res; + + n = getenv_f("hwconfig", buffer, sizeof(buffer)); + if (n > 0) + buf = buffer; + + res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); + if (res > 0) + enable_cpu_a011_workaround = 0; + else { + if (n >= HWCONFIG_BUFFER_SIZE) { + printf("fsl_cpu_a011 was not found. hwconfig variable " + "may be too long\n"); + } + enable_cpu_a011_workaround = + (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || + (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); + } +#endif + if (enable_cpu_a011_workaround) { + flush_dcache(); + mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); + sync(); + } +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005812 + /* + * A-005812 workaround sets bit 32 of SPR 976 for SoCs running + * in write shadow mode. Checking DCWS before setting SPR 976. + */ + if (mfspr(L1CSR2) & L1CSR2_DCWS) + mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); +#endif + +#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) + spin = getenv("spin_table_compat"); + if (spin && (*spin == 'n')) + spin_table_compat = 0; + else + spin_table_compat = 1; +#endif + + puts ("L2: "); + +#if defined(CONFIG_L2_CACHE) + volatile uint cache_ctl; + uint ver; + u32 l2siz_field; + + ver = SVR_SOC_VER(svr); + + asm("msync;isync"); + cache_ctl = l2cache->l2ctl; + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + if (cache_ctl & MPC85xx_L2CTL_L2E) { + /* Clear L2 SRAM memory-mapped base address */ + out_be32(&l2cache->l2srbar0, 0x0); + out_be32(&l2cache->l2srbar1, 0x0); + + /* set MBECCDIS=0, SBECCDIS=0 */ + clrbits_be32(&l2cache->l2errdis, + (MPC85xx_L2ERRDIS_MBECC | + MPC85xx_L2ERRDIS_SBECC)); + + /* set L2E=0, L2SRAM=0 */ + clrbits_be32(&l2cache->l2ctl, + (MPC85xx_L2CTL_L2E | + MPC85xx_L2CTL_L2SRAM_ENTIRE)); + } +#endif + + l2siz_field = (cache_ctl >> 28) & 0x3; + + switch (l2siz_field) { + case 0x0: + printf(" unknown size (0x%08x)\n", cache_ctl); + return -1; + break; + case 0x1: + if (ver == SVR_8540 || ver == SVR_8560 || + ver == SVR_8541 || ver == SVR_8555) { + puts("128 KiB "); + /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */ + cache_ctl = 0xc4000000; + } else { + puts("256 KiB "); + cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ + } + break; + case 0x2: + if (ver == SVR_8540 || ver == SVR_8560 || + ver == SVR_8541 || ver == SVR_8555) { + puts("256 KiB "); + /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */ + cache_ctl = 0xc8000000; + } else { + puts("512 KiB "); + /* set L2E=1, L2I=1, & L2SRAM=0 */ + cache_ctl = 0xc0000000; + } + break; + case 0x3: + puts("1024 KiB "); + /* set L2E=1, L2I=1, & L2SRAM=0 */ + cache_ctl = 0xc0000000; + break; + } + + if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { + puts("already enabled"); +#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) + u32 l2srbar = l2cache->l2srbar0; + if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE + && l2srbar >= CONFIG_SYS_FLASH_BASE) { + l2srbar = CONFIG_SYS_INIT_L2_ADDR; + l2cache->l2srbar0 = l2srbar; + printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); + } +#endif /* CONFIG_SYS_INIT_L2_ADDR */ + puts("\n"); + } else { + asm("msync;isync"); + l2cache->l2ctl = cache_ctl; /* invalidate & enable */ + asm("msync;isync"); + puts("enabled\n"); + } +#elif defined(CONFIG_BACKSIDE_L2_CACHE) + if (SVR_SOC_VER(svr) == SVR_P2040) { + puts("N/A\n"); + goto skip_l2; + } + + u32 l2cfg0 = mfspr(SPRN_L2CFG0); + + /* invalidate the L2 cache */ + mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); + while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) + ; + +#ifdef CONFIG_SYS_CACHE_STASHING + /* set stash id to (coreID) * 2 + 32 + L2 (1) */ + mtspr(SPRN_L2CSR1, (32 + 1)); +#endif + + /* enable the cache */ + mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); + + if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { + while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) + ; + print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); + } + +skip_l2: +#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) + if (l2cache->l2csr0 & L2CSR0_L2E) + print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, + " enabled\n"); + + enable_cluster_l2(); +#else + puts("disabled\n"); +#endif + +#if defined(CONFIG_RAMBOOT_PBL) + disable_cpc_sram(); +#endif + enable_cpc(); + +#ifndef CONFIG_SYS_FSL_NO_SERDES + /* needs to be in ram since code uses global static vars */ + fsl_serdes_init(); +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 +#define MCFGR_AXIPIPE 0x000000f0 + if (IS_SVR_REV(svr, 1, 0)) + clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE); +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A005871 + if (IS_SVR_REV(svr, 1, 0)) { + int i; + __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; + + for (i = 0; i < 12; i++) { + p += i + (i > 5 ? 11 : 0); + out_be32(p, 0x2); + } + p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; + out_be32(p, 0x34); + } +#endif + +#ifdef CONFIG_SYS_SRIO + srio_init(); +#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER + char *s = getenv("bootmaster"); + if (s) { + if (!strcmp(s, "SRIO1")) { + srio_boot_master(1); + srio_boot_master_release_slave(1); + } + if (!strcmp(s, "SRIO2")) { + srio_boot_master(2); + srio_boot_master_release_slave(2); + } + } +#endif +#endif + +#if defined(CONFIG_MP) + setup_mp(); +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 + { + if (SVR_MAJ(svr) < 3) { + void *p; + p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; + setbits_be32(p, 1 << (31 - 14)); + } + } +#endif + +#ifdef CONFIG_SYS_LBC_LCRR + /* + * Modify the CLKDIV field of LCRR register to improve the writing + * speed for NOR flash. + */ + clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); + __raw_readl(&lbc->lcrr); + isync(); +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 + udelay(100); +#endif +#endif + +#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE + { + struct ccsr_usb_phy __iomem *usb_phy1 = + (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 + if (has_erratum_a006261()) + fsl_erratum_a006261_workaround(usb_phy1); +#endif + out_be32(&usb_phy1->usb_enable_override, + CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); + } +#endif +#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE + { + struct ccsr_usb_phy __iomem *usb_phy2 = + (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 + if (has_erratum_a006261()) + fsl_erratum_a006261_workaround(usb_phy2); +#endif + out_be32(&usb_phy2->usb_enable_override, + CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); + } +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_USB14 + /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal + * multi-bit ECC errors which has impact on performance, so software + * should disable all ECC reporting from USB1 and USB2. + */ + if (IS_SVR_REV(get_svr(), 1, 0)) { + struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) + (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); + setbits_be32(&dcfg->ecccr1, + (DCSR_DCFG_ECC_DISABLE_USB1 | + DCSR_DCFG_ECC_DISABLE_USB2)); + } +#endif + +#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) + struct ccsr_usb_phy __iomem *usb_phy = + (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; + setbits_be32(&usb_phy->pllprg[1], + CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | + CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | + CONFIG_SYS_FSL_USB_PLLPRG2_MFI | + CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + usb_single_source_clk_configure(usb_phy); +#endif + setbits_be32(&usb_phy->port1.ctrl, + CONFIG_SYS_FSL_USB_CTRL_PHY_EN); + setbits_be32(&usb_phy->port1.drvvbuscfg, + CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); + setbits_be32(&usb_phy->port1.pwrfltcfg, + CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); + setbits_be32(&usb_phy->port2.ctrl, + CONFIG_SYS_FSL_USB_CTRL_PHY_EN); + setbits_be32(&usb_phy->port2.drvvbuscfg, + CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); + setbits_be32(&usb_phy->port2.pwrfltcfg, + CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); + +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261 + if (has_erratum_a006261()) + fsl_erratum_a006261_workaround(usb_phy); +#endif + +#endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */ + +#ifdef CONFIG_FMAN_ENET + fman_enet_init(); +#endif + +#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) + /* + * For P1022/1013 Rev1.0 silicon, after power on SATA host + * controller is configured in legacy mode instead of the + * expected enterprise mode. Software needs to clear bit[28] + * of HControl register to change to enterprise mode from + * legacy mode. We assume that the controller is offline. + */ + if (IS_SVR_REV(svr, 1, 0) && + ((SVR_SOC_VER(svr) == SVR_P1022) || + (SVR_SOC_VER(svr) == SVR_P1013))) { + fsl_sata_reg_t *reg; + + /* first SATA controller */ + reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; + clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); + + /* second SATA controller */ + reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; + clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); + } +#endif + + init_used_tlb_cams(); + + return 0; +} + +void arch_preboot_os(void) +{ + u32 msr; + + /* + * We are changing interrupt offsets and are about to boot the OS so + * we need to make sure we disable all async interrupts. EE is already + * disabled by the time we get called. + */ + msr = mfmsr(); + msr &= ~(MSR_ME|MSR_CE); + mtmsr(msr); +} + +#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) +int sata_initialize(void) +{ + if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) + return __sata_initialize(); + + return 1; +} +#endif + +void cpu_secondary_init_r(void) +{ +#ifdef CONFIG_U_QE + uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */ +#elif defined CONFIG_QE + uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ +#endif + +#ifdef CONFIG_QE + qe_init(qe_base); + qe_reset(); +#endif +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/cpu_init_early.c new file mode 100644 index 000000000..47b712d56 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -0,0 +1,185 @@ +/* + * Copyright 2009-2012 Freescale Semiconductor, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/fsl_law.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_A003399_NOR_WORKAROUND +void setup_ifc(void) +{ + struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; + u32 _mas0, _mas1, _mas2, _mas3, _mas7; + phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS; + + /* + * Adjust the TLB we were running out of to match the phys addr of the + * chip select we are adjusting and will return to. + */ + flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024; + + _mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15); + _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT | + MAS1_TSIZE(BOOKE_PAGESZ_4M); + _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G); + _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX); + _mas7 = FSL_BOOKE_MAS7(flash_phys); + + mtspr(MAS0, _mas0); + mtspr(MAS1, _mas1); + mtspr(MAS2, _mas2); + mtspr(MAS3, _mas3); + mtspr(MAS7, _mas7); + + asm volatile("isync;msync;tlbwe;isync"); + +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) +/* + * TLB entry for debuggging in AS1 + * Create temporary TLB entry in AS0 to handle debug exception + * As on debug exception MSR is cleared i.e. Address space is changed + * to 0. A TLB entry (in AS0) is required to handle debug exception generated + * in AS1. + * + * TLB entry is created for IVPR + IVOR15 to map on valid OP code address + * bacause flash's physical address is going to change as + * CONFIG_SYS_FLASH_BASE_PHYS. + */ + _mas0 = MAS0_TLBSEL(1) | + MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB); + _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT | + MAS1_TSIZE(BOOKE_PAGESZ_4M); + _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G); + _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX); + _mas7 = FSL_BOOKE_MAS7(flash_phys); + + mtspr(MAS0, _mas0); + mtspr(MAS1, _mas1); + mtspr(MAS2, _mas2); + mtspr(MAS3, _mas3); + mtspr(MAS7, _mas7); + + asm volatile("isync;msync;tlbwe;isync"); +#endif + + /* Change flash's physical address */ + out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0); + out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0); + out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0); + + return ; +} +#endif + +/* We run cpu_init_early_f in AS = 1 */ +void cpu_init_early_f(void *fdt) +{ + u32 mas0, mas1, mas2, mas3, mas7; + int i; +#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif +#ifdef CONFIG_A003399_NOR_WORKAROUND + ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; + u32 *dst, *src; + void (*setup_ifc_sram)(void); +#endif + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + + /* + * Clear initial global data + * we don't use memset so we can share this code with NAND_SPL + */ + for (i = 0; i < sizeof(gd_t); i++) + ((char *)gd)[i] = 0; + +#ifdef CONFIG_QEMU_E500 + /* + * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems, + * so we need to populate it before it accesses it. + */ + gd->fdt_blob = fdt; +#endif + + mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13); + mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); + mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); + mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS); + + write_tlb(mas0, mas1, mas2, mas3, mas7); + +/* + * Work Around for IFC Erratum A-003549. This issue is P1010 + * specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC + * Hence specifically selecting CS3. + */ +#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3); +#endif + + init_laws(); + +/* + * Work Around for IFC Erratum A003399, issue will hit only when execution + * from NOR Flash + */ +#ifdef CONFIG_A003399_NOR_WORKAROUND +#define SRAM_BASE_ADDR (0x00000000) + /* TLB for SRAM */ + mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9); + mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | + MAS1_TSIZE(BOOKE_PAGESZ_1M); + mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I); + mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(0); + + write_tlb(mas0, mas1, mas2, mas3, mas7); + + out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR); + + out_be32(&l2cache->l2errdis, + (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); + + out_be32(&l2cache->l2ctl, + (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); + + /* + * Copy the code in setup_ifc to L2SRAM. Do a word copy + * because NOR Flash on P1010 does not support byte + * access (Erratum IFC-A002769) + */ + setup_ifc_sram = (void *)SRAM_BASE_ADDR; + dst = (u32 *) SRAM_BASE_ADDR; + src = (u32 *) setup_ifc; + for (i = 0; i < 1024; i++) + *dst++ = *src++; + + setup_ifc_sram(); + + /* CLEANUP */ + clrbits_be32(&l2cache->l2ctl, + (MPC85xx_L2CTL_L2E | + MPC85xx_L2CTL_L2SRAM_ENTIRE)); + out_be32(&l2cache->l2srbar0, 0x0); +#endif + + invalidate_tlb(1); + +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && \ + !(defined(CONFIG_SPL_INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \ + !defined(CONFIG_NAND_SPL) + disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB); +#endif + + init_tlbs(); +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/ether_fcc.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/ether_fcc.c new file mode 100644 index 000000000..166dc9ed1 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/ether_fcc.c @@ -0,0 +1,452 @@ +/* + * MPC8560 FCC Fast Ethernet + * Copyright (c) 2003 Motorola,Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net) + * + * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * MPC8560 FCC Fast Ethernet + * Basic ET HW initialization and packet RX/TX routines + * + * This code will not perform the IO port configuration. This should be + * done in the iop_conf_t structure specific for the board. + * + * TODO: + * add a PHY driver to do the negotiation + * reflect negotiation results in FPSMR + * look for ways to configure the board specific stuff elsewhere, eg. + * config_xxx.h or the board directory + */ + +#include <common.h> +#include <malloc.h> +#include <asm/cpm_85xx.h> +#include <command.h> +#include <config.h> +#include <net.h> + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#include <miiphy.h> +#endif + +#if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET) + +static struct ether_fcc_info_s +{ + int ether_index; + int proff_enet; + ulong cpm_cr_enet_sblock; + ulong cpm_cr_enet_page; + ulong cmxfcr_mask; + ulong cmxfcr_value; +} + ether_fcc_info[] = +{ +#ifdef CONFIG_ETHER_ON_FCC1 +{ + 0, + PROFF_FCC1, + CPM_CR_FCC1_SBLOCK, + CPM_CR_FCC1_PAGE, + CONFIG_SYS_CMXFCR_MASK1, + CONFIG_SYS_CMXFCR_VALUE1 +}, +#endif + +#ifdef CONFIG_ETHER_ON_FCC2 +{ + 1, + PROFF_FCC2, + CPM_CR_FCC2_SBLOCK, + CPM_CR_FCC2_PAGE, + CONFIG_SYS_CMXFCR_MASK2, + CONFIG_SYS_CMXFCR_VALUE2 +}, +#endif + +#ifdef CONFIG_ETHER_ON_FCC3 +{ + 2, + PROFF_FCC3, + CPM_CR_FCC3_SBLOCK, + CPM_CR_FCC3_PAGE, + CONFIG_SYS_CMXFCR_MASK3, + CONFIG_SYS_CMXFCR_VALUE3 +}, +#endif +}; + +/*---------------------------------------------------------------------*/ + +/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */ +#define PKT_MAXDMA_SIZE 1520 + +/* The FCC stores dest/src/type, data, and checksum for receive packets. */ +#define PKT_MAXBUF_SIZE 1518 +#define PKT_MINBUF_SIZE 64 + +/* Maximum input buffer size. Must be a multiple of 32. */ +#define PKT_MAXBLR_SIZE 1536 + +#define TOUT_LOOP 1000000 + +#define TX_BUF_CNT 2 + +static uint rxIdx; /* index of the current RX buffer */ +static uint txIdx; /* index of the current TX buffer */ + +/* + * FCC Ethernet Tx and Rx buffer descriptors. + * Provide for Double Buffering + * Note: PKTBUFSRX is defined in net.h + */ + +typedef volatile struct rtxbd { + cbd_t rxbd[PKTBUFSRX]; + cbd_t txbd[TX_BUF_CNT]; +} RTXBD; + +/* Good news: the FCC supports external BDs! */ +#ifdef __GNUC__ +static RTXBD rtx __attribute__ ((aligned(8))); +#else +#error "rtx must be 64-bit aligned" +#endif + +#undef ET_DEBUG + +static int fec_send(struct eth_device *dev, void *packet, int length) +{ + int i = 0; + int result = 0; + + if (length <= 0) { + printf("fec: bad packet size: %d\n", length); + goto out; + } + + for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { + if (i >= TOUT_LOOP) { + printf("fec: tx buffer not ready\n"); + goto out; + } + } + + rtx.txbd[txIdx].cbd_bufaddr = (uint)packet; + rtx.txbd[txIdx].cbd_datlen = length; + rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \ + BD_ENET_TX_TC | BD_ENET_TX_PAD); + + for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { + if (i >= TOUT_LOOP) { + printf("fec: tx error\n"); + goto out; + } + } + +#ifdef ET_DEBUG + printf("cycles: 0x%x txIdx=0x%04x status: 0x%04x\n", i, txIdx,rtx.txbd[txIdx].cbd_sc); + printf("packets at 0x%08x, length_in_bytes=0x%x\n",(uint)packet,length); + for(i=0;i<(length/16 + 1);i++) { + printf("%08x %08x %08x %08x\n",*((uint *)rtx.txbd[txIdx].cbd_bufaddr+i*4),\ + *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 1),*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 2), \ + *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 3)); + } +#endif + + /* return only status bits */ + result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS; + txIdx = (txIdx + 1) % TX_BUF_CNT; + +out: + return result; +} + +static int fec_recv(struct eth_device* dev) +{ + int length; + + for (;;) + { + if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { + length = -1; + break; /* nothing received - leave for() loop */ + } + length = rtx.rxbd[rxIdx].cbd_datlen; + + if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) { + printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc); + } + else { + /* Pass the packet up to the protocol layers. */ + NetReceive(NetRxPackets[rxIdx], length - 4); + } + + + /* Give the buffer back to the FCC. */ + rtx.rxbd[rxIdx].cbd_datlen = 0; + + /* wrap around buffer index when necessary */ + if ((rxIdx + 1) >= PKTBUFSRX) { + rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); + rxIdx = 0; + } + else { + rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; + rxIdx++; + } + } + return length; +} + + +static int fec_init(struct eth_device* dev, bd_t *bis) +{ + struct ether_fcc_info_s * info = dev->priv; + int i; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp); + fcc_enet_t *pram_ptr; + unsigned long mem_addr; + +#if 0 + mii_discover_phy(); +#endif + + /* 28.9 - (1-2): ioports have been set up already */ + + /* 28.9 - (3): connect FCC's tx and rx clocks */ + cpm->im_cpm_mux.cmxuar = 0; /* ATM */ + cpm->im_cpm_mux.cmxfcr = (cpm->im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) | + info->cmxfcr_value; + + /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */ + if(info->ether_index == 0) { + cpm->im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; + } else if (info->ether_index == 1) { + cpm->im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; + } else if (info->ether_index == 2) { + cpm->im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; + } + + /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */ + if(info->ether_index == 0) { + cpm->im_cpm_fcc1.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; + } else if (info->ether_index == 1){ + cpm->im_cpm_fcc2.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; + } else if (info->ether_index == 2){ + cpm->im_cpm_fcc3.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; + } + + /* 28.9 - (6): FDSR: Ethernet Syn */ + if(info->ether_index == 0) { + cpm->im_cpm_fcc1.fdsr = 0xD555; + } else if (info->ether_index == 1) { + cpm->im_cpm_fcc2.fdsr = 0xD555; + } else if (info->ether_index == 2) { + cpm->im_cpm_fcc3.fdsr = 0xD555; + } + + /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */ + rxIdx = 0; + txIdx = 0; + + /* Setup Receiver Buffer Descriptors */ + for (i = 0; i < PKTBUFSRX; i++) + { + rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; + rtx.rxbd[i].cbd_datlen = 0; + rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i]; + } + rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; + + /* Setup Ethernet Transmitter Buffer Descriptors */ + for (i = 0; i < TX_BUF_CNT; i++) + { + rtx.txbd[i].cbd_sc = 0; + rtx.txbd[i].cbd_datlen = 0; + rtx.txbd[i].cbd_bufaddr = 0; + } + rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; + + /* 28.9 - (7): initialize parameter ram */ + pram_ptr = (fcc_enet_t *)&(cpm->im_dprambase[info->proff_enet]); + + /* clear whole structure to make sure all reserved fields are zero */ + memset((void*)pram_ptr, 0, sizeof(fcc_enet_t)); + + /* + * common Parameter RAM area + * + * Allocate space in the reserved FCC area of DPRAM for the + * internal buffers. No one uses this space (yet), so we + * can do this. Later, we will add resource management for + * this area. + * CPM_FCC_SPECIAL_BASE: 0xB000 for MPC8540, MPC8560 + * 0x9000 for MPC8541, MPC8555 + */ + mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64); + pram_ptr->fen_genfcc.fcc_riptr = mem_addr; + pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32; + /* + * Set maximum bytes per receive buffer. + * It must be a multiple of 32. + */ + pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */ + /* localbus SDRAM should be preferred */ + pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB | + CONFIG_SYS_CPMFCR_RAMTYPE) << 24; + pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]); + pram_ptr->fen_genfcc.fcc_rbdstat = 0; + pram_ptr->fen_genfcc.fcc_rbdlen = 0; + pram_ptr->fen_genfcc.fcc_rdptr = 0; + /* localbus SDRAM should be preferred */ + pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB | + CONFIG_SYS_CPMFCR_RAMTYPE) << 24; + pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]); + pram_ptr->fen_genfcc.fcc_tbdstat = 0; + pram_ptr->fen_genfcc.fcc_tbdlen = 0; + pram_ptr->fen_genfcc.fcc_tdptr = 0; + + /* protocol-specific area */ + pram_ptr->fen_statbuf = 0x0; + pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */ + pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */ + pram_ptr->fen_crcec = 0; + pram_ptr->fen_alec = 0; + pram_ptr->fen_disfc = 0; + pram_ptr->fen_retlim = 15; /* Retry limit threshold */ + pram_ptr->fen_retcnt = 0; + pram_ptr->fen_pper = 0; + pram_ptr->fen_boffcnt = 0; + pram_ptr->fen_gaddrh = 0; + pram_ptr->fen_gaddrl = 0; + pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */ + /* + * Set Ethernet station address. + * + * This is supplied in the board information structure, so we + * copy that into the controller. + * So far we have only been given one Ethernet address. We make + * it unique by setting a few bits in the upper byte of the + * non-static part of the address. + */ +#define ea eth_get_dev()->enetaddr + pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4]; + pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2]; + pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0]; +#undef ea + pram_ptr->fen_ibdcount = 0; + pram_ptr->fen_ibdstart = 0; + pram_ptr->fen_ibdend = 0; + pram_ptr->fen_txlen = 0; + pram_ptr->fen_iaddrh = 0; /* disable hash */ + pram_ptr->fen_iaddrl = 0; + pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register: 64 */ + /* pad pointer. use tiptr since we don't need a specific padding char */ + pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr; + pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length:1520 */ + pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length:1520 */ + +#if defined(ET_DEBUG) + printf("parm_ptr(0xff788500) = %p\n",pram_ptr); + printf("pram_ptr->fen_genfcc.fcc_rbase %08x\n", + pram_ptr->fen_genfcc.fcc_rbase); + printf("pram_ptr->fen_genfcc.fcc_tbase %08x\n", + pram_ptr->fen_genfcc.fcc_tbase); +#endif + + /* 28.9 - (8)(9): clear out events in FCCE */ + /* 28.9 - (9): FCCM: mask all events */ + if(info->ether_index == 0) { + cpm->im_cpm_fcc1.fcce = ~0x0; + cpm->im_cpm_fcc1.fccm = 0; + } else if (info->ether_index == 1) { + cpm->im_cpm_fcc2.fcce = ~0x0; + cpm->im_cpm_fcc2.fccm = 0; + } else if (info->ether_index == 2) { + cpm->im_cpm_fcc3.fcce = ~0x0; + cpm->im_cpm_fcc3.fccm = 0; + } + + /* 28.9 - (10-12): we don't use ethernet interrupts */ + + /* 28.9 - (13) + * + * Let's re-initialize the channel now. We have to do it later + * than the manual describes because we have just now finished + * the BD initialization. + */ + cp->cpcr = mk_cr_cmd(info->cpm_cr_enet_page, + info->cpm_cr_enet_sblock, + 0x0c, + CPM_CR_INIT_TRX) | CPM_CR_FLG; + do { + __asm__ __volatile__ ("eieio"); + } while (cp->cpcr & CPM_CR_FLG); + + /* 28.9 - (14): enable tx/rx in gfmr */ + if(info->ether_index == 0) { + cpm->im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; + } else if (info->ether_index == 1) { + cpm->im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; + } else if (info->ether_index == 2) { + cpm->im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; + } + + return 1; +} + +static void fec_halt(struct eth_device* dev) +{ + struct ether_fcc_info_s * info = dev->priv; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; + + /* write GFMR: disable tx/rx */ + if(info->ether_index == 0) { + cpm->im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); + } else if(info->ether_index == 1) { + cpm->im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); + } else if(info->ether_index == 2) { + cpm->im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); + } +} + +int fec_initialize(bd_t *bis) +{ + struct eth_device* dev; + int i; + + for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) + { + dev = (struct eth_device*) malloc(sizeof *dev); + memset(dev, 0, sizeof *dev); + + sprintf(dev->name, "FCC%d", + ether_fcc_info[i].ether_index + 1); + dev->priv = ðer_fcc_info[i]; + dev->init = fec_init; + dev->halt = fec_halt; + dev->send = fec_send; + dev->recv = fec_recv; + + eth_register(dev); + +#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \ + && defined(CONFIG_BITBANGMII) + miiphy_register(dev->name, + bb_miiphy_read, bb_miiphy_write); +#endif + } + + return 1; +} + +#endif diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/fdt.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/fdt.c new file mode 100644 index 000000000..ed80a8418 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/fdt.c @@ -0,0 +1,857 @@ +/* + * Copyright 2007-2011 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <asm/processor.h> +#include <linux/ctype.h> +#include <asm/io.h> +#include <asm/fsl_portals.h> +#ifdef CONFIG_FSL_ESDHC +#include <fsl_esdhc.h> +#endif +#include "../../../../drivers/qe/qe.h" /* For struct qe_firmware */ + +DECLARE_GLOBAL_DATA_PTR; + +extern void ft_qe_setup(void *blob); +extern void ft_fixup_num_cores(void *blob); +extern void ft_srio_setup(void *blob); + +#ifdef CONFIG_MP +#include "mp.h" + +void ft_fixup_cpu(void *blob, u64 memory_limit) +{ + int off; + phys_addr_t spin_tbl_addr = get_spin_phys_addr(); + u32 bootpg = determine_mp_bootpg(NULL); + u32 id = get_my_id(); + const char *enable_method; + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + while (off != -FDT_ERR_NOTFOUND) { + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); + + if (reg) { + u32 phys_cpu_id = thread_to_core(*reg); + u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr; + val = cpu_to_fdt64(val); + if (*reg == id) { + fdt_setprop_string(blob, off, "status", + "okay"); + } else { + fdt_setprop_string(blob, off, "status", + "disabled"); + } + + if (hold_cores_in_reset(0)) { +#ifdef CONFIG_FSL_CORENET + /* Cores held in reset, use BRR to release */ + enable_method = "fsl,brr-holdoff"; +#else + /* Cores held in reset, use EEBPCR to release */ + enable_method = "fsl,eebpcr-holdoff"; +#endif + } else { + /* Cores out of reset and in a spin-loop */ + enable_method = "spin-table"; + + fdt_setprop(blob, off, "cpu-release-addr", + &val, sizeof(val)); + } + + fdt_setprop_string(blob, off, "enable-method", + enable_method); + } else { + printf ("cpu NULL\n"); + } + off = fdt_node_offset_by_prop_value(blob, off, + "device_type", "cpu", 4); + } + + /* Reserve the boot page so OSes dont use it */ + if ((u64)bootpg < memory_limit) { + off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); + if (off < 0) + printf("Failed to reserve memory for bootpg: %s\n", + fdt_strerror(off)); + } + +#ifndef CONFIG_MPC8xxx_DISABLE_BPTR + /* + * Reserve the default boot page so OSes dont use it. + * The default boot page is always mapped to bootpg above using + * boot page translation. + */ + if (0xfffff000ull < memory_limit) { + off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096); + if (off < 0) { + printf("Failed to reserve memory for 0xfffff000: %s\n", + fdt_strerror(off)); + } + } +#endif + + /* Reserve spin table page */ + if (spin_tbl_addr < memory_limit) { + off = fdt_add_mem_rsv(blob, + (spin_tbl_addr & ~0xffful), 4096); + if (off < 0) + printf("Failed to reserve memory for spin table: %s\n", + fdt_strerror(off)); + } +} +#endif + +#ifdef CONFIG_SYS_FSL_CPC +static inline void ft_fixup_l3cache(void *blob, int off) +{ + u32 line_size, num_ways, size, num_sets; + cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR; + u32 cfg0 = in_be32(&cpc->cpccfg0); + + size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; + num_ways = CPC_CFG0_NUM_WAYS(cfg0); + line_size = CPC_CFG0_LINE_SZ(cfg0); + num_sets = size / (line_size * num_ways); + + fdt_setprop(blob, off, "cache-unified", NULL, 0); + fdt_setprop_cell(blob, off, "cache-block-size", line_size); + fdt_setprop_cell(blob, off, "cache-size", size); + fdt_setprop_cell(blob, off, "cache-sets", num_sets); + fdt_setprop_cell(blob, off, "cache-level", 3); +#ifdef CONFIG_SYS_CACHE_STASHING + fdt_setprop_cell(blob, off, "cache-stash-id", 1); +#endif +} +#else +#define ft_fixup_l3cache(x, y) +#endif + +#if defined(CONFIG_L2_CACHE) +/* return size in kilobytes */ +static inline u32 l2cache_size(void) +{ + volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; + volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; + u32 ver = SVR_SOC_VER(get_svr()); + + switch (l2siz_field) { + case 0x0: + break; + case 0x1: + if (ver == SVR_8540 || ver == SVR_8560 || + ver == SVR_8541 || ver == SVR_8555) + return 128; + else + return 256; + break; + case 0x2: + if (ver == SVR_8540 || ver == SVR_8560 || + ver == SVR_8541 || ver == SVR_8555) + return 256; + else + return 512; + break; + case 0x3: + return 1024; + break; + } + + return 0; +} + +static inline void ft_fixup_l2cache(void *blob) +{ + int len, off; + u32 *ph; + struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); + + const u32 line_size = 32; + const u32 num_ways = 8; + const u32 size = l2cache_size() * 1024; + const u32 num_sets = size / (line_size * num_ways); + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + if (off < 0) { + debug("no cpu node fount\n"); + return; + } + + ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); + + if (ph == NULL) { + debug("no next-level-cache property\n"); + return ; + } + + off = fdt_node_offset_by_phandle(blob, *ph); + if (off < 0) { + printf("%s: %s\n", __func__, fdt_strerror(off)); + return ; + } + + if (cpu) { + char buf[40]; + + if (isdigit(cpu->name[0])) { + /* MPCxxxx, where xxxx == 4-digit number */ + len = sprintf(buf, "fsl,mpc%s-l2-cache-controller", + cpu->name) + 1; + } else { + /* Pxxxx or Txxxx, where xxxx == 4-digit number */ + len = sprintf(buf, "fsl,%c%s-l2-cache-controller", + tolower(cpu->name[0]), cpu->name + 1) + 1; + } + + /* + * append "cache" after the NULL character that the previous + * sprintf wrote. This is how a device tree stores multiple + * strings in a property. + */ + len += sprintf(buf + len, "cache") + 1; + + fdt_setprop(blob, off, "compatible", buf, len); + } + fdt_setprop(blob, off, "cache-unified", NULL, 0); + fdt_setprop_cell(blob, off, "cache-block-size", line_size); + fdt_setprop_cell(blob, off, "cache-size", size); + fdt_setprop_cell(blob, off, "cache-sets", num_sets); + fdt_setprop_cell(blob, off, "cache-level", 2); + + /* we dont bother w/L3 since no platform of this type has one */ +} +#elif defined(CONFIG_BACKSIDE_L2_CACHE) || \ + defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) +static inline void ft_fixup_l2cache(void *blob) +{ + int off, l2_off, l3_off = -1; + u32 *ph; +#ifdef CONFIG_BACKSIDE_L2_CACHE + u32 l2cfg0 = mfspr(SPRN_L2CFG0); +#else + struct ccsr_cluster_l2 *l2cache = + (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2); + u32 l2cfg0 = in_be32(&l2cache->l2cfg0); +#endif + u32 size, line_size, num_ways, num_sets; + int has_l2 = 1; + + /* P2040/P2040E has no L2, so dont set any L2 props */ + if (SVR_SOC_VER(get_svr()) == SVR_P2040) + has_l2 = 0; + + size = (l2cfg0 & 0x3fff) * 64 * 1024; + num_ways = ((l2cfg0 >> 14) & 0x1f) + 1; + line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32; + num_sets = size / (line_size * num_ways); + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + + while (off != -FDT_ERR_NOTFOUND) { + ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); + + if (ph == NULL) { + debug("no next-level-cache property\n"); + goto next; + } + + l2_off = fdt_node_offset_by_phandle(blob, *ph); + if (l2_off < 0) { + printf("%s: %s\n", __func__, fdt_strerror(off)); + goto next; + } + + if (has_l2) { +#ifdef CONFIG_SYS_CACHE_STASHING + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) + /* Only initialize every eighth thread */ + if (reg && !((*reg) % 8)) { + fdt_setprop_cell(blob, l2_off, "cache-stash-id", + (*reg / 4) + 32 + 1); + } +#else + if (reg) { + fdt_setprop_cell(blob, l2_off, "cache-stash-id", + (*reg * 2) + 32 + 1); + } +#endif +#endif + + fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); + fdt_setprop_cell(blob, l2_off, "cache-block-size", + line_size); + fdt_setprop_cell(blob, l2_off, "cache-size", size); + fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); + fdt_setprop_cell(blob, l2_off, "cache-level", 2); + fdt_setprop(blob, l2_off, "compatible", "cache", 6); + } + + if (l3_off < 0) { + ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0); + + if (ph == NULL) { + debug("no next-level-cache property\n"); + goto next; + } + l3_off = *ph; + } +next: + off = fdt_node_offset_by_prop_value(blob, off, + "device_type", "cpu", 4); + } + if (l3_off > 0) { + l3_off = fdt_node_offset_by_phandle(blob, l3_off); + if (l3_off < 0) { + printf("%s: %s\n", __func__, fdt_strerror(off)); + return ; + } + ft_fixup_l3cache(blob, l3_off); + } +} +#else +#define ft_fixup_l2cache(x) +#endif + +static inline void ft_fixup_cache(void *blob) +{ + int off; + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + + while (off != -FDT_ERR_NOTFOUND) { + u32 l1cfg0 = mfspr(SPRN_L1CFG0); + u32 l1cfg1 = mfspr(SPRN_L1CFG1); + u32 isize, iline_size, inum_sets, inum_ways; + u32 dsize, dline_size, dnum_sets, dnum_ways; + + /* d-side config */ + dsize = (l1cfg0 & 0x7ff) * 1024; + dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1; + dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32; + dnum_sets = dsize / (dline_size * dnum_ways); + + fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size); + fdt_setprop_cell(blob, off, "d-cache-size", dsize); + fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); + +#ifdef CONFIG_SYS_CACHE_STASHING + { + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); + if (reg) + fdt_setprop_cell(blob, off, "cache-stash-id", + (*reg * 2) + 32 + 0); + } +#endif + + /* i-side config */ + isize = (l1cfg1 & 0x7ff) * 1024; + inum_ways = ((l1cfg1 >> 11) & 0xff) + 1; + iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32; + inum_sets = isize / (iline_size * inum_ways); + + fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size); + fdt_setprop_cell(blob, off, "i-cache-size", isize); + fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets); + + off = fdt_node_offset_by_prop_value(blob, off, + "device_type", "cpu", 4); + } + + ft_fixup_l2cache(blob); +} + + +void fdt_add_enet_stashing(void *fdt) +{ + do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1); + + do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1); + + do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1); + do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1); + do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1); + do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1); +} + +#if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME) +#ifdef CONFIG_SYS_DPAA_FMAN +static void ft_fixup_clks(void *blob, const char *compat, u32 offset, + unsigned long freq) +{ + phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS; + int off = fdt_node_offset_by_compat_reg(blob, compat, phys); + + if (off >= 0) { + off = fdt_setprop_cell(blob, off, "clock-frequency", freq); + if (off > 0) + printf("WARNING enable to set clock-frequency " + "for %s: %s\n", compat, fdt_strerror(off)); + } +} +#endif + +static void ft_fixup_dpaa_clks(void *blob) +{ + sys_info_t sysinfo; + + get_sys_info(&sysinfo); +#ifdef CONFIG_SYS_DPAA_FMAN + ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET, + sysinfo.freq_fman[0]); + +#if (CONFIG_SYS_NUM_FMAN == 2) + ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET, + sysinfo.freq_fman[1]); +#endif +#endif + +#ifdef CONFIG_SYS_DPAA_QBMAN + do_fixup_by_compat_u32(blob, "fsl,qman", + "clock-frequency", sysinfo.freq_qman, 1); +#endif + +#ifdef CONFIG_SYS_DPAA_PME + do_fixup_by_compat_u32(blob, "fsl,pme", + "clock-frequency", sysinfo.freq_pme, 1); +#endif +} +#else +#define ft_fixup_dpaa_clks(x) +#endif + +#ifdef CONFIG_QE +static void ft_fixup_qe_snum(void *blob) +{ + unsigned int svr; + + svr = mfspr(SPRN_SVR); + if (SVR_SOC_VER(svr) == SVR_8569) { + if(IS_SVR_REV(svr, 1, 0)) + do_fixup_by_compat_u32(blob, "fsl,qe", + "fsl,qe-num-snums", 46, 1); + else + do_fixup_by_compat_u32(blob, "fsl,qe", + "fsl,qe-num-snums", 76, 1); + } +} +#endif + +/** + * fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree + * + * The binding for an Fman firmware node is documented in + * Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt. This node contains + * the actual Fman firmware binary data. The operating system is expected to + * be able to parse the binary data to determine any attributes it needs. + */ +#ifdef CONFIG_SYS_DPAA_FMAN +void fdt_fixup_fman_firmware(void *blob) +{ + int rc, fmnode, fwnode = -1; + uint32_t phandle; + struct qe_firmware *fmanfw; + const struct qe_header *hdr; + unsigned int length; + uint32_t crc; + const char *p; + + /* The first Fman we find will contain the actual firmware. */ + fmnode = fdt_node_offset_by_compatible(blob, -1, "fsl,fman"); + if (fmnode < 0) + /* Exit silently if there are no Fman devices */ + return; + + /* If we already have a firmware node, then also exit silently. */ + if (fdt_node_offset_by_compatible(blob, -1, "fsl,fman-firmware") > 0) + return; + + /* If the environment variable is not set, then exit silently */ + p = getenv("fman_ucode"); + if (!p) + return; + + fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 16); + if (!fmanfw) + return; + + hdr = &fmanfw->header; + length = be32_to_cpu(hdr->length); + + /* Verify the firmware. */ + if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || + (hdr->magic[2] != 'F')) { + printf("Data at %p is not an Fman firmware\n", fmanfw); + return; + } + + if (length > CONFIG_SYS_QE_FMAN_FW_LENGTH) { + printf("Fman firmware at %p is too large (size=%u)\n", + fmanfw, length); + return; + } + + length -= sizeof(u32); /* Subtract the size of the CRC */ + crc = be32_to_cpu(*(u32 *)((void *)fmanfw + length)); + if (crc != crc32_no_comp(0, (void *)fmanfw, length)) { + printf("Fman firmware at %p has invalid CRC\n", fmanfw); + return; + } + + /* Increase the size of the fdt to make room for the node. */ + rc = fdt_increase_size(blob, fmanfw->header.length); + if (rc < 0) { + printf("Unable to make room for Fman firmware: %s\n", + fdt_strerror(rc)); + return; + } + + /* Create the firmware node. */ + fwnode = fdt_add_subnode(blob, fmnode, "fman-firmware"); + if (fwnode < 0) { + char s[64]; + fdt_get_path(blob, fmnode, s, sizeof(s)); + printf("Could not add firmware node to %s: %s\n", s, + fdt_strerror(fwnode)); + return; + } + rc = fdt_setprop_string(blob, fwnode, "compatible", "fsl,fman-firmware"); + if (rc < 0) { + char s[64]; + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add compatible property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } + phandle = fdt_create_phandle(blob, fwnode); + if (!phandle) { + char s[64]; + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add phandle property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } + rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, fmanfw->header.length); + if (rc < 0) { + char s[64]; + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add firmware property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } + + /* Find all other Fman nodes and point them to the firmware node. */ + while ((fmnode = fdt_node_offset_by_compatible(blob, fmnode, "fsl,fman")) > 0) { + rc = fdt_setprop_cell(blob, fmnode, "fsl,firmware-phandle", phandle); + if (rc < 0) { + char s[64]; + fdt_get_path(blob, fmnode, s, sizeof(s)); + printf("Could not add pointer property to node %s: %s\n", + s, fdt_strerror(rc)); + return; + } + } +} +#else +#define fdt_fixup_fman_firmware(x) +#endif + +#if defined(CONFIG_PPC_P4080) +static void fdt_fixup_usb(void *fdt) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr11 = in_be32(&gur->rcwsr[11]); + int off; + + off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph"); + if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) != + FSL_CORENET_RCWSR11_EC1_FM1_USB1) + fdt_status_disabled(fdt, off); + + off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr"); + if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) != + FSL_CORENET_RCWSR11_EC2_USB2) + fdt_status_disabled(fdt, off); +} +#else +#define fdt_fixup_usb(x) +#endif + +#if defined(CONFIG_PPC_T1040) +static void fdt_fixup_l2_switch(void *blob) +{ + uchar l2swaddr[6]; + int node; + + /* The l2switch node from device-tree has + * compatible string "vitesse-9953" */ + node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953"); + if (node == -FDT_ERR_NOTFOUND) + /* no l2switch node has been found */ + return; + + /* Get MAC address for the l2switch from "l2switchaddr"*/ + if (!eth_getenv_enetaddr("l2switchaddr", l2swaddr)) { + printf("Warning: MAC address for l2switch not found\n"); + memset(l2swaddr, 0, sizeof(l2swaddr)); + } + + /* Add MAC address to l2switch node */ + fdt_setprop(blob, node, "local-mac-address", l2swaddr, + sizeof(l2swaddr)); +} +#else +#define fdt_fixup_l2_switch(x) +#endif + +void ft_cpu_setup(void *blob, bd_t *bd) +{ + int off; + int val; + int len; + sys_info_t sysinfo; + + /* delete crypto node if not on an E-processor */ + if (!IS_E_PROCESSOR(get_svr())) + fdt_fixup_crypto_node(blob, 0); +#if CONFIG_SYS_FSL_SEC_COMPAT >= 4 + else { + ccsr_sec_t __iomem *sec; + + sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + fdt_fixup_crypto_node(blob, in_be32(&sec->secvid_ms)); + } +#endif + + fdt_fixup_ethernet(blob); + + fdt_add_enet_stashing(blob); + +#ifndef CONFIG_FSL_TBCLK_EXTRA_DIV +#define CONFIG_FSL_TBCLK_EXTRA_DIV 1 +#endif + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV, + 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "bus-frequency", bd->bi_busfreq, 1); + get_sys_info(&sysinfo); + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + while (off != -FDT_ERR_NOTFOUND) { + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len); + val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]); + fdt_setprop(blob, off, "clock-frequency", &val, 4); + off = fdt_node_offset_by_prop_value(blob, off, "device_type", + "cpu", 4); + } + do_fixup_by_prop_u32(blob, "device_type", "soc", 4, + "bus-frequency", bd->bi_busfreq, 1); + + do_fixup_by_compat_u32(blob, "fsl,pq3-localbus", + "bus-frequency", gd->arch.lbc_clk, 1); + do_fixup_by_compat_u32(blob, "fsl,elbc", + "bus-frequency", gd->arch.lbc_clk, 1); +#ifdef CONFIG_QE + ft_qe_setup(blob); + ft_fixup_qe_snum(blob); +#endif + + fdt_fixup_fman_firmware(blob); + +#ifdef CONFIG_SYS_NS16550 + do_fixup_by_compat_u32(blob, "ns16550", + "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); +#endif + +#ifdef CONFIG_CPM2 + do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart", + "current-speed", gd->baudrate, 1); + + do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", + "clock-frequency", bd->bi_brgfreq, 1); +#endif + +#ifdef CONFIG_FSL_CORENET + do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0", + "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); + do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0", + "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); + do_fixup_by_compat_u32(blob, "fsl,mpic", + "clock-frequency", get_bus_freq(0)/2, 1); +#else + do_fixup_by_compat_u32(blob, "fsl,mpic", + "clock-frequency", get_bus_freq(0), 1); +#endif + + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); + +#ifdef CONFIG_MP + ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); + ft_fixup_num_cores(blob); +#endif + + ft_fixup_cache(blob); + +#if defined(CONFIG_FSL_ESDHC) + fdt_fixup_esdhc(blob, bd); +#endif + + ft_fixup_dpaa_clks(blob); + +#if defined(CONFIG_SYS_BMAN_MEM_PHYS) + fdt_portal(blob, "fsl,bman-portal", "bman-portals", + (u64)CONFIG_SYS_BMAN_MEM_PHYS, + CONFIG_SYS_BMAN_MEM_SIZE); + fdt_fixup_bportals(blob); +#endif + +#if defined(CONFIG_SYS_QMAN_MEM_PHYS) + fdt_portal(blob, "fsl,qman-portal", "qman-portals", + (u64)CONFIG_SYS_QMAN_MEM_PHYS, + CONFIG_SYS_QMAN_MEM_SIZE); + + fdt_fixup_qportals(blob); +#endif + +#ifdef CONFIG_SYS_SRIO + ft_srio_setup(blob); +#endif + + /* + * system-clock = CCB clock/2 + * Here gd->bus_clk = CCB clock + * We are using the system clock as 1588 Timer reference + * clock source select + */ + do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer", + "timer-frequency", gd->bus_clk/2, 1); + + /* + * clock-freq should change to clock-frequency and + * flexcan-v1.0 should change to p1010-flexcan respectively + * in the future. + */ + do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", + "clock_freq", gd->bus_clk/2, 1); + + do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", + "clock-frequency", gd->bus_clk/2, 1); + + do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan", + "clock-frequency", gd->bus_clk/2, 1); + + fdt_fixup_usb(blob); + + fdt_fixup_l2_switch(blob); +} + +/* + * For some CCSR devices, we only have the virtual address, not the physical + * address. This is because we map CCSR as a whole, so we typically don't need + * a macro for the physical address of any device within CCSR. In this case, + * we calculate the physical address of that device using it's the difference + * between the virtual address of the device and the virtual address of the + * beginning of CCSR. + */ +#define CCSR_VIRT_TO_PHYS(x) \ + (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR)) + +static void msg(const char *name, uint64_t uaddr, uint64_t daddr) +{ + printf("Warning: U-Boot configured %s at address %llx,\n" + "but the device tree has it at %llx\n", name, uaddr, daddr); +} + +/* + * Verify the device tree + * + * This function compares several CONFIG_xxx macros that contain physical + * addresses with the corresponding nodes in the device tree, to see if + * the physical addresses are all correct. For example, if + * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address + * of the first UART. We convert this to a physical address and compare + * that with the physical address of the first ns16550-compatible node + * in the device tree. If they don't match, then we display a warning. + * + * Returns 1 on success, 0 on failure + */ +int ft_verify_fdt(void *fdt) +{ + uint64_t addr = 0; + int aliases; + int off; + + /* First check the CCSR base address */ + off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4); + if (off > 0) + addr = fdt_get_base_address(fdt, off); + + if (!addr) { + printf("Warning: could not determine base CCSR address in " + "device tree\n"); + /* No point in checking anything else */ + return 0; + } + + if (addr != CONFIG_SYS_CCSRBAR_PHYS) { + msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr); + /* No point in checking anything else */ + return 0; + } + + /* + * Check some nodes via aliases. We assume that U-Boot and the device + * tree enumerate the devices equally. E.g. the first serial port in + * U-Boot is the same as "serial0" in the device tree. + */ + aliases = fdt_path_offset(fdt, "/aliases"); + if (aliases > 0) { +#ifdef CONFIG_SYS_NS16550_COM1 + if (!fdt_verify_alias_address(fdt, aliases, "serial0", + CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1))) + return 0; +#endif + +#ifdef CONFIG_SYS_NS16550_COM2 + if (!fdt_verify_alias_address(fdt, aliases, "serial1", + CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2))) + return 0; +#endif + } + + /* + * The localbus node is typically a root node, even though the lbc + * controller is part of CCSR. If we were to put the lbc node under + * the SOC node, then the 'ranges' property in the lbc node would + * translate through the 'ranges' property of the parent SOC node, and + * we don't want that. Since it's a separate node, it's possible for + * the 'reg' property to be wrong, so check it here. For now, we + * only check for "fsl,elbc" nodes. + */ +#ifdef CONFIG_SYS_LBC_ADDR + off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc"); + if (off > 0) { + const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL); + if (reg) { + uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR); + + addr = fdt_translate_address(fdt, off, reg); + if (uaddr != addr) { + msg("the localbus", uaddr, addr); + return 0; + } + } + } +#endif + + return 1; +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c new file mode 100644 index 000000000..70e09eaed --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -0,0 +1,226 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_serdes.h> +#include <asm/immap_85xx.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <asm/fsl_law.h> +#include <asm/errno.h> +#include "fsl_corenet2_serdes.h" + +#ifdef CONFIG_SYS_FSL_SRDS_1 +static u64 serdes1_prtcl_map; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 +static u64 serdes2_prtcl_map; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_3 +static u64 serdes3_prtcl_map; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_4 +static u64 serdes4_prtcl_map; +#endif + +#ifdef DEBUG +static const char *serdes_prtcl_str[] = { + [NONE] = "NA", + [PCIE1] = "PCIE1", + [PCIE2] = "PCIE2", + [PCIE3] = "PCIE3", + [PCIE4] = "PCIE4", + [SATA1] = "SATA1", + [SATA2] = "SATA2", + [SRIO1] = "SRIO1", + [SRIO2] = "SRIO2", + [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1", + [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2", + [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3", + [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4", + [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5", + [SGMII_FM1_DTSEC6] = "SGMII_FM1_DTSEC6", + [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1", + [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2", + [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3", + [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4", + [XAUI_FM1] = "XAUI_FM1", + [XAUI_FM2] = "XAUI_FM2", + [AURORA] = "DEBUG", + [CPRI1] = "CPRI1", + [CPRI2] = "CPRI2", + [CPRI3] = "CPRI3", + [CPRI4] = "CPRI4", + [CPRI5] = "CPRI5", + [CPRI6] = "CPRI6", + [CPRI7] = "CPRI7", + [CPRI8] = "CPRI8", + [XAUI_FM1_MAC9] = "XAUI_FM1_MAC9", + [XAUI_FM1_MAC10] = "XAUI_FM1_MAC10", + [XAUI_FM2_MAC9] = "XAUI_FM2_MAC9", + [XAUI_FM2_MAC10] = "XAUI_FM2_MAC10", + [HIGIG_FM1_MAC9] = "HiGig_FM1_MAC9", + [HIGIG_FM1_MAC10] = "HiGig_FM1_MAC10", + [HIGIG_FM2_MAC9] = "HiGig_FM2_MAC9", + [HIGIG_FM2_MAC10] = "HiGig_FM2_MAC10", + [QSGMII_FM1_A] = "QSGMII_FM1_A", + [QSGMII_FM1_B] = "QSGMII_FM1_B", + [QSGMII_FM2_A] = "QSGMII_FM2_A", + [QSGMII_FM2_B] = "QSGMII_FM2_B", + [XFI_FM1_MAC9] = "XFI_FM1_MAC9", + [XFI_FM1_MAC10] = "XFI_FM1_MAC10", + [XFI_FM2_MAC9] = "XFI_FM2_MAC9", + [XFI_FM2_MAC10] = "XFI_FM2_MAC10", + [INTERLAKEN] = "INTERLAKEN", + [QSGMII_SW1_A] = "QSGMII_SW1_A", + [QSGMII_SW1_B] = "QSGMII_SW1_B", +}; +#endif + +int is_serdes_configured(enum srds_prtcl device) +{ + u64 ret = 0; + +#ifdef CONFIG_SYS_FSL_SRDS_1 + ret |= (1ULL << device) & serdes1_prtcl_map; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + ret |= (1ULL << device) & serdes2_prtcl_map; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_3 + ret |= (1ULL << device) & serdes3_prtcl_map; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_4 + ret |= (1ULL << device) & serdes4_prtcl_map; +#endif + + return !!ret; +} + +int serdes_get_first_lane(u32 sd, enum srds_prtcl device) +{ + const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 cfg = in_be32(&gur->rcwsr[4]); + int i; + + switch (sd) { +#ifdef CONFIG_SYS_FSL_SRDS_1 + case FSL_SRDS_1: + cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + break; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + case FSL_SRDS_2: + cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + break; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_3 + case FSL_SRDS_3: + cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL; + cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT; + break; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_4 + case FSL_SRDS_4: + cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL; + cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; + break; +#endif + default: + printf("invalid SerDes%d\n", sd); + break; + } + /* Is serdes enabled at all? */ + if (unlikely(cfg == 0)) + return -ENODEV; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_get_prtcl(sd, cfg, i) == device) + return i; + } + + return -ENODEV; +} + +u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u64 serdes_prtcl_map = 0; + u32 cfg; + int lane; + + cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask; + /* Is serdes enabled at all? */ + if (!cfg) { + printf("SERDES%d is not enabled\n", sd + 1); + return 0; + } + + cfg >>= sd_prctl_shift; + printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); + if (!is_serdes_prtcl_valid(sd, cfg)) + printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); + + for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); + serdes_prtcl_map |= (1ULL << lane_prtcl); + } + + return serdes_prtcl_map; +} + +void fsl_serdes_init(void) +{ + +#ifdef CONFIG_SYS_FSL_SRDS_1 + serdes1_prtcl_map = serdes_init(FSL_SRDS_1, + CONFIG_SYS_FSL_CORENET_SERDES_ADDR, + FSL_CORENET2_RCWSR4_SRDS1_PRTCL, + FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT); +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + serdes2_prtcl_map = serdes_init(FSL_SRDS_2, + CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000, + FSL_CORENET2_RCWSR4_SRDS2_PRTCL, + FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT); +#endif +#ifdef CONFIG_SYS_FSL_SRDS_3 + serdes3_prtcl_map = serdes_init(FSL_SRDS_3, + CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000, + FSL_CORENET2_RCWSR4_SRDS3_PRTCL, + FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT); +#endif +#ifdef CONFIG_SYS_FSL_SRDS_4 + serdes4_prtcl_map = serdes_init(FSL_SRDS_4, + CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000, + FSL_CORENET2_RCWSR4_SRDS4_PRTCL, + FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT); +#endif + +} + +const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + case SRDS_PLLCR0_RFCK_SEL_161_13: + return "161.1328123"; + default: +#if defined(CONFIG_T4240QDS) + return "???"; +#else + return "122.88"; +#endif + } +} + diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h new file mode 100644 index 000000000..d515b234a --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h @@ -0,0 +1,12 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_CORENET2_SERDES_H +#define __FSL_CORENET2_SERDES_H + +int is_serdes_prtcl_valid(int serdes, u32 prtcl); +int serdes_lane_enabled(int lane); +#endif /* __FSL_CORENET2_SERDES_H */ diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c new file mode 100644 index 000000000..ba22f90a6 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -0,0 +1,877 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 +#include <hwconfig.h> +#endif +#include <asm/fsl_serdes.h> +#include <asm/immap_85xx.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <asm/fsl_law.h> +#include <asm/errno.h> +#include "fsl_corenet_serdes.h" + +/* + * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together. + * The code is already very complicated as it is, and separating the two + * completely would just make things worse. We try to keep them as separate + * as possible, but for now we require SERDES8 if SERDES_A001 is defined. + */ +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 +#ifndef CONFIG_SYS_P4080_ERRATUM_SERDES8 +#error "CONFIG_SYS_P4080_ERRATUM_SERDES_A001 requires CONFIG_SYS_P4080_ERRATUM_SERDES8" +#endif +#endif + +static u32 serdes_prtcl_map; + +#ifdef DEBUG +static const char *serdes_prtcl_str[] = { + [NONE] = "NA", + [PCIE1] = "PCIE1", + [PCIE2] = "PCIE2", + [PCIE3] = "PCIE3", + [PCIE4] = "PCIE4", + [SATA1] = "SATA1", + [SATA2] = "SATA2", + [SRIO1] = "SRIO1", + [SRIO2] = "SRIO2", + [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1", + [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2", + [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3", + [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4", + [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5", + [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1", + [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2", + [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3", + [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4", + [SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5", + [XAUI_FM1] = "XAUI_FM1", + [XAUI_FM2] = "XAUI_FM2", + [AURORA] = "DEBUG", +}; +#endif + +static const struct { + int idx; + unsigned int lpd; /* RCW lane powerdown bit */ + int bank; +} lanes[SRDS_MAX_LANES] = { + { 0, 152, FSL_SRDS_BANK_1 }, + { 1, 153, FSL_SRDS_BANK_1 }, + { 2, 154, FSL_SRDS_BANK_1 }, + { 3, 155, FSL_SRDS_BANK_1 }, + { 4, 156, FSL_SRDS_BANK_1 }, + { 5, 157, FSL_SRDS_BANK_1 }, + { 6, 158, FSL_SRDS_BANK_1 }, + { 7, 159, FSL_SRDS_BANK_1 }, + { 8, 160, FSL_SRDS_BANK_1 }, + { 9, 161, FSL_SRDS_BANK_1 }, + { 16, 162, FSL_SRDS_BANK_2 }, + { 17, 163, FSL_SRDS_BANK_2 }, + { 18, 164, FSL_SRDS_BANK_2 }, + { 19, 165, FSL_SRDS_BANK_2 }, +#ifdef CONFIG_PPC_P4080 + { 20, 170, FSL_SRDS_BANK_3 }, + { 21, 171, FSL_SRDS_BANK_3 }, + { 22, 172, FSL_SRDS_BANK_3 }, + { 23, 173, FSL_SRDS_BANK_3 }, +#else + { 20, 166, FSL_SRDS_BANK_3 }, + { 21, 167, FSL_SRDS_BANK_3 }, + { 22, 168, FSL_SRDS_BANK_3 }, + { 23, 169, FSL_SRDS_BANK_3 }, +#endif +#if SRDS_MAX_BANK > 3 + { 24, 175, FSL_SRDS_BANK_4 }, + { 25, 176, FSL_SRDS_BANK_4 }, +#endif +}; + +int serdes_get_lane_idx(int lane) +{ + return lanes[lane].idx; +} + +int serdes_get_bank_by_lane(int lane) +{ + return lanes[lane].bank; +} + +int serdes_lane_enabled(int lane) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + + int bank = lanes[lane].bank; + int word = lanes[lane].lpd / 32; + int bit = lanes[lane].lpd % 32; + + if (in_be32(®s->bank[bank].rstctl) & SRDS_RSTCTL_SDPD) + return 0; + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 + /* + * For banks two and three, use the srds_lpd_b[] array instead of the + * RCW, because this array contains the real values of SRDS_LPD_B2 and + * SRDS_LPD_B3. + */ + if (bank > 0) + return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank)))); +#endif + + return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit)); +} + +int is_serdes_configured(enum srds_prtcl device) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* Is serdes enabled at all? */ + if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) + return 0; + + return (1 << device) & serdes_prtcl_map; +} + +static int __serdes_get_first_lane(uint32_t prtcl, enum srds_prtcl device) +{ + int i; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_get_prtcl(prtcl, i) == device) + return i; + } + + return -ENODEV; +} + +/* + * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given + * device. This depends on the current SERDES protocol, as defined in the RCW. + * + * Returns a negative error code if SERDES is disabled or the given device is + * not supported in the current SERDES protocol. + */ +int serdes_get_first_lane(enum srds_prtcl device) +{ + u32 prtcl; + const ccsr_gur_t *gur; + + gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Is serdes enabled at all? */ + if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) + return -ENODEV; + + prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + return __serdes_get_first_lane(prtcl, device); +} + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 +/* + * Returns the SERDES bank (1, 2, or 3) that a given device is on for a given + * SERDES protocol. + * + * Returns a negative error code if the given device is not supported for the + * given SERDES protocol. + */ +static int serdes_get_bank_by_device(uint32_t prtcl, enum srds_prtcl device) +{ + int lane; + + lane = __serdes_get_first_lane(prtcl, device); + if (unlikely(lane < 0)) + return lane; + + return serdes_get_bank_by_lane(lane); +} + +static uint32_t __serdes_get_lane_count(uint32_t prtcl, enum srds_prtcl device, + int first) +{ + int lane; + + for (lane = first; lane < SRDS_MAX_LANES; lane++) { + if (serdes_get_prtcl(prtcl, lane) != device) + break; + } + + return lane - first; +} + +static void __serdes_reset_rx(serdes_corenet_t *regs, + uint32_t prtcl, + enum srds_prtcl device) +{ + int lane, idx, first, last; + + lane = __serdes_get_first_lane(prtcl, device); + if (unlikely(lane < 0)) + return; + first = serdes_get_lane_idx(lane); + last = first + __serdes_get_lane_count(prtcl, device, lane); + + /* + * Set BnGCRy0[RRST] = 0 for each lane in the each bank that is + * selected as XAUI to place the lane into reset. + */ + for (idx = first; idx < last; idx++) + clrbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST); + + /* Wait at least 250 ns */ + udelay(1); + + /* + * Set BnGCRy0[RRST] = 1 for each lane in the each bank that is + * selected as XAUI to bring the lane out of reset. + */ + for (idx = first; idx < last; idx++) + setbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST); +} + +void serdes_reset_rx(enum srds_prtcl device) +{ + u32 prtcl; + const ccsr_gur_t *gur; + serdes_corenet_t *regs; + + if (unlikely(device == NONE)) + return; + + gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Is serdes enabled at all? */ + if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) + return; + + regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + __serdes_reset_rx(regs, prtcl, device); +} +#endif + +#ifndef CONFIG_SYS_DCSRBAR_PHYS +#define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */ +#define CONFIG_SYS_DCSRBAR 0x80000000 +#define __DCSR_NOT_DEFINED_BY_CONFIG +#endif + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 +/* + * Enable a SERDES bank that was disabled via the RCW + * + * We only call this function for SERDES8 and SERDES-A001 in cases we really + * want to enable the bank, whether we actually want to use the lanes or not, + * so make sure at least one lane is enabled. We're only enabling this one + * lane to satisfy errata requirements that the bank be enabled. + * + * We use a local variable instead of srds_lpd_b[] because we want drivers to + * think that the lanes actually are disabled. + */ +static void enable_bank(ccsr_gur_t *gur, int bank) +{ + u32 rcw5; + u32 temp_lpd_b = srds_lpd_b[bank]; + + /* + * If we're asked to disable all lanes, just pretend we're doing + * that. + */ + if (temp_lpd_b == 0xF) + temp_lpd_b = 0xE; + + /* + * Enable the lanes SRDS_LPD_Bn. The RCW bits are read-only in + * CCSR, and read/write in DSCR. + */ + rcw5 = in_be32(gur->rcwsr + 5); + if (bank == FSL_SRDS_BANK_2) { + rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2; + rcw5 |= temp_lpd_b << 26; + } else if (bank == FSL_SRDS_BANK_3) { + rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3; + rcw5 |= temp_lpd_b << 18; + } else { + printf("SERDES: enable_bank: bad bank %d\n", bank + 1); + return; + } + + /* See similar code in cpu/mpc85xx/cpu_init.c for an explanation + * of the DCSR mapping. + */ + { +#ifdef __DCSR_NOT_DEFINED_BY_CONFIG + struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS); + int law_index; + if (law.index == -1) + law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS, + LAW_SIZE_1M, LAW_TRGT_IF_DCSR); + else + set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M, + LAW_TRGT_IF_DCSR); +#endif + u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114; + out_be32(p, rcw5); +#ifdef __DCSR_NOT_DEFINED_BY_CONFIG + if (law.index == -1) + disable_law(law_index); + else + set_law(law.index, law.addr, law.size, law.trgt_id); +#endif + } +} + +/* + * To avoid problems with clock jitter, rev 2 p4080 uses the pll from + * bank 3 to clock banks 2 and 3, as well as a limited selection of + * protocol configurations. This requires that banks 2 and 3's lanes be + * disabled in the RCW, and enabled with some fixup here to re-enable + * them, and to configure bank 2's clock parameters in bank 3's pll in + * cases where they differ. + */ +static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur, + u32 devdisr, u32 devdisr2, int cfg) +{ + int srds_ratio_b2; + int rfck_sel; + + /* + * The disabled lanes of bank 2 will cause the associated + * logic blocks to be disabled in DEVDISR. We reverse that here. + * + * Note that normally it is not permitted to clear DEVDISR bits + * once the device has been disabled, but the hardware people + * say that this special case is OK. + */ + clrbits_be32(&gur->devdisr, devdisr); + clrbits_be32(&gur->devdisr2, devdisr2); + + /* + * Some protocols require special handling. There are a few + * additional protocol configurations that can be used, which are + * not listed here. See app note 4065 for supported protocol + * configurations. + */ + switch (cfg) { + case 0x19: + /* + * Bank 2 has PCIe which wants BWSEL -- tell bank 3's PLL. + * SGMII on bank 3 should still be usable. + */ + setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + break; + + case 0x0f: + case 0x10: + /* + * Banks 2 (XAUI) and 3 (SGMII) have different clocking + * requirements in these configurations. Bank 3 cannot + * be used and should have its lanes (but not the bank + * itself) disabled in the RCW. We set up bank 3's pll + * for bank 2's needs here. + */ + srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7; + + /* Determine refclock from XAUI ratio */ + switch (srds_ratio_b2) { + case 1: /* 20:1 */ + rfck_sel = SRDS_PLLCR0_RFCK_SEL_156_25; + break; + case 2: /* 25:1 */ + rfck_sel = SRDS_PLLCR0_RFCK_SEL_125; + break; + default: + printf("SERDES: bad SRDS_RATIO_B2 %d\n", + srds_ratio_b2); + return; + } + + clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0, + SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel); + + clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0, + SRDS_PLLCR0_FRATE_SEL_MASK, + SRDS_PLLCR0_FRATE_SEL_6_25); + break; + } + + enable_bank(gur, FSL_SRDS_BANK_3); +} +#endif + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005 +/* + * If PCIe is not selected as a protocol for any lanes driven by a given PLL, + * that PLL should have SRDSBnPLLCR1[PLLBW_SEL] = 0. + */ +static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg) +{ + enum srds_prtcl device; + + switch (cfg) { + case 0x13: + case 0x16: + /* + * If SRDS_PRTCL = 0x13 or 0x16, set SRDSB1PLLCR1[PLLBW_SEL] + * to 0. + */ + clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + break; + case 0x19: + /* + * If SRDS_PRTCL = 0x19, set SRDSB1PLLCR1[PLLBW_SEL] to 0 and + * SRDSB3PLLCR1[PLLBW_SEL] to 1. + */ + clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + break; + } + + /* + * Set SRDSBnPLLCR1[PLLBW_SEL] to 0 for each bank that selects XAUI + * before XAUI is initialized. + */ + for (device = XAUI_FM1; device <= XAUI_FM2; device++) { + if (is_serdes_configured(device)) { + int bank = serdes_get_bank_by_device(cfg, device); + + clrbits_be32(®s->bank[bank].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + } + } +} +#endif + +/* + * Wait for the RSTDONE bit to get set, or a one-second timeout. + */ +static void wait_for_rstdone(unsigned int bank) +{ + serdes_corenet_t *srds_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + unsigned long long end_tick; + u32 rstctl; + + /* wait for reset complete or 1-second timeout */ + end_tick = usec2ticks(1000000) + get_ticks(); + do { + rstctl = in_be32(&srds_regs->bank[bank].rstctl); + if (rstctl & SRDS_RSTCTL_RSTDONE) + break; + } while (end_tick > get_ticks()); + + if (!(rstctl & SRDS_RSTCTL_RSTDONE)) + printf("SERDES: timeout resetting bank %u\n", bank + 1); +} + + +static void __soc_serdes_init(void) +{ + /* Allow for SoC-specific initialization in <SOC>_serdes.c */ +}; +void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init"))); + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int cfg; + serdes_corenet_t *srds_regs; +#ifdef CONFIG_PPC_P5040 + serdes_corenet_t *srds2_regs; +#endif + int lane, bank, idx; + int have_bank[SRDS_MAX_BANK] = {}; +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 + u32 serdes8_devdisr = 0; + u32 serdes8_devdisr2 = 0; + char srds_lpd_opt[16]; + const char *srds_lpd_arg; + size_t arglen; +#endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 + int need_serdes_a001; /* true == need work-around for SERDES A001 */ +#endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; + + /* + * Extract hwconfig from environment since we have not properly setup + * the environment but need it for ddr config params + */ + if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) + buf = buffer; +#endif + + /* Is serdes enabled at all? */ + if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) + return; + + srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR); + cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + debug("Using SERDES configuration 0x%x, lane settings:\n", cfg); + + if (!is_serdes_prtcl_valid(cfg)) { + printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg); + return; + } + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 + /* + * Display a warning if banks two and three are not disabled in the RCW, + * since our work-around for SERDES8 depends on these banks being + * disabled at power-on. + */ +#define B2_B3 (FSL_CORENET_RCWSRn_SRDS_LPD_B2 | FSL_CORENET_RCWSRn_SRDS_LPD_B3) + if ((in_be32(&gur->rcwsr[5]) & B2_B3) != B2_B3) { + printf("Warning: SERDES8 requires banks two and " + "three to be disabled in the RCW\n"); + } + + /* + * Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3 + * hwconfig options into the srds_lpd_b[] array. See README.p4080ds + * for a description of these options. + */ + for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) { + sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1); + srds_lpd_arg = + hwconfig_subarg_f("serdes", srds_lpd_opt, &arglen, buf); + if (srds_lpd_arg) + srds_lpd_b[bank] = + simple_strtoul(srds_lpd_arg, NULL, 0) & 0xf; + } + + if ((cfg == 0xf) || (cfg == 0x10)) { + /* + * For SERDES protocols 0xF and 0x10, force bank 3 to be + * disabled, because it is not supported. + */ + srds_lpd_b[FSL_SRDS_BANK_3] = 0xF; + } +#endif + + /* Look for banks with all lanes disabled, and power down the bank. */ + for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane); + if (serdes_lane_enabled(lane)) { + have_bank[serdes_get_bank_by_lane(lane)] = 1; + serdes_prtcl_map |= (1 << lane_prtcl); + } + } + +#ifdef CONFIG_PPC_P5040 + /* + * Lanes on bank 4 on P5040 are commented-out, but for some SERDES + * protocols, these lanes are routed to SATA. We use serdes_prtcl_map + * to decide whether a protocol is supported on a given lane, so SATA + * will be identified as not supported, and therefore not initialized. + * So for protocols which use SATA on bank4, we add SATA support in + * serdes_prtcl_map. + */ + switch (cfg) { + case 0x0: + case 0x1: + case 0x2: + case 0x3: + case 0x4: + case 0x5: + case 0x6: + case 0x7: + serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2; + break; + default: + srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR; + + /* We don't need bank 4, so power it down */ + setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD); + } +#endif + + soc_serdes_init(); + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 + /* + * Bank two uses the clock from bank three, so if bank two is enabled, + * then bank three must also be enabled. + */ + if (have_bank[FSL_SRDS_BANK_2]) + have_bank[FSL_SRDS_BANK_3] = 1; +#endif + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 + /* + * The work-aroud for erratum SERDES-A001 is needed only if bank two + * is disabled and bank three is enabled. The converse is also true, + * but SERDES8 ensures that bank 3 is always enabled if bank 2 is + * enabled, so there's no point in complicating the code to handle + * that situation. + */ + need_serdes_a001 = + !have_bank[FSL_SRDS_BANK_2] && have_bank[FSL_SRDS_BANK_3]; +#endif + + /* Power down the banks we're not interested in */ + for (bank = 0; bank < SRDS_MAX_BANK; bank++) { + if (!have_bank[bank]) { + printf("SERDES: bank %d disabled\n", bank + 1); +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 + /* + * Erratum SERDES-A001 says bank two needs to be powered + * down after bank three is powered up, so don't power + * down bank two here. + */ + if (!need_serdes_a001 || (bank != FSL_SRDS_BANK_2)) + setbits_be32(&srds_regs->bank[bank].rstctl, + SRDS_RSTCTL_SDPD); +#else + setbits_be32(&srds_regs->bank[bank].rstctl, + SRDS_RSTCTL_SDPD); +#endif + } + } + +#ifdef CONFIG_SYS_FSL_ERRATUM_A004699 + /* + * To avoid the situation that resulted in the P4080 erratum + * SERDES-8, a given SerDes bank will use the PLLs from the previous + * bank if one of the PLL frequencies is a multiple of the other. For + * instance, if bank 3 is running at 2.5GHz and bank 2 is at 1.25GHz, + * then bank 3 will use bank 2's PLL. P5040 Erratum A-004699 says + * that, in this situation, lane synchronization is not initiated. So + * when we detect a bank with a "borrowed" PLL, we have to manually + * initiate lane synchronization. + */ + for (bank = FSL_SRDS_BANK_2; bank <= FSL_SRDS_BANK_3; bank++) { + /* Determine the first lane for this bank */ + unsigned int lane; + + for (lane = 0; lane < SRDS_MAX_LANES; lane++) + if (lanes[lane].bank == bank) + break; + idx = lanes[lane].idx; + + /* + * Check if the PLL for the bank is borrowed. The UOTHL + * bit of the first lane will tell us that. + */ + if (in_be32(&srds_regs->lane[idx].gcr0) & SRDS_GCR0_UOTHL) { + /* Manually start lane synchronization */ + setbits_be32(&srds_regs->bank[bank].pllcr0, + SRDS_PLLCR0_PVCOCNT_EN); + } + } +#endif + +#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9) + for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl; + + idx = serdes_get_lane_idx(lane); + lane_prtcl = serdes_get_prtcl(cfg, lane); + +#ifdef DEBUG + switch (lane) { + case 0: + puts("Bank1: "); + break; + case 10: + puts("\nBank2: "); + break; + case 14: + puts("\nBank3: "); + break; + default: + break; + } + + printf("%s ", serdes_prtcl_str[lane_prtcl]); +#endif + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 + /* + * Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1 + * for each of the SerDes lanes selected as SGMII, XAUI, SRIO, + * or AURORA before the device is initialized. + * + * Note that this part of the SERDES-9 work-around is + * redundant if the work-around for A-4580 has already been + * applied via PBI. + */ + switch (lane_prtcl) { + case SGMII_FM1_DTSEC1: + case SGMII_FM1_DTSEC2: + case SGMII_FM1_DTSEC3: + case SGMII_FM1_DTSEC4: + case SGMII_FM2_DTSEC1: + case SGMII_FM2_DTSEC2: + case SGMII_FM2_DTSEC3: + case SGMII_FM2_DTSEC4: + case SGMII_FM2_DTSEC5: + case XAUI_FM1: + case XAUI_FM2: + case SRIO1: + case SRIO2: + case AURORA: + out_be32(&srds_regs->lane[idx].ttlcr0, + SRDS_TTLCR0_FLT_SEL_KFR_26 | + SRDS_TTLCR0_FLT_SEL_KPH_28 | + SRDS_TTLCR0_FLT_SEL_750PPM | + SRDS_TTLCR0_FREQOVD_EN); + break; + default: + break; + } +#endif + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 + switch (lane_prtcl) { + case PCIE1: + case PCIE2: + case PCIE3: + serdes8_devdisr |= FSL_CORENET_DEVDISR_PCIE1 >> + (lane_prtcl - PCIE1); + break; + case SRIO1: + case SRIO2: + serdes8_devdisr |= FSL_CORENET_DEVDISR_SRIO1 >> + (lane_prtcl - SRIO1); + break; + case SGMII_FM1_DTSEC1: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | + FSL_CORENET_DEVDISR2_DTSEC1_1; + break; + case SGMII_FM1_DTSEC2: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | + FSL_CORENET_DEVDISR2_DTSEC1_2; + break; + case SGMII_FM1_DTSEC3: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | + FSL_CORENET_DEVDISR2_DTSEC1_3; + break; + case SGMII_FM1_DTSEC4: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | + FSL_CORENET_DEVDISR2_DTSEC1_4; + break; + case SGMII_FM2_DTSEC1: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | + FSL_CORENET_DEVDISR2_DTSEC2_1; + break; + case SGMII_FM2_DTSEC2: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | + FSL_CORENET_DEVDISR2_DTSEC2_2; + break; + case SGMII_FM2_DTSEC3: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | + FSL_CORENET_DEVDISR2_DTSEC2_3; + break; + case SGMII_FM2_DTSEC4: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | + FSL_CORENET_DEVDISR2_DTSEC2_4; + break; + case SGMII_FM2_DTSEC5: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | + FSL_CORENET_DEVDISR2_DTSEC2_5; + break; + case XAUI_FM1: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | + FSL_CORENET_DEVDISR2_10GEC1; + break; + case XAUI_FM2: + serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | + FSL_CORENET_DEVDISR2_10GEC2; + break; + case AURORA: + break; + default: + break; + } + +#endif + } +#endif + +#ifdef DEBUG + puts("\n"); +#endif + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005 + p4080_erratum_serdes_a005(srds_regs, cfg); +#endif + + for (idx = 0; idx < SRDS_MAX_BANK; idx++) { + bank = idx; + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 + /* + * Change bank init order to 0, 2, 1, so that the third bank's + * PLL is established before we start the second bank. The + * second bank uses the third bank's PLL. + */ + + if (idx == 1) + bank = FSL_SRDS_BANK_3; + else if (idx == 2) + bank = FSL_SRDS_BANK_2; +#endif + + /* Skip disabled banks */ + if (!have_bank[bank]) + continue; + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 + if (idx == 1) { + /* + * Re-enable devices on banks two and three that were + * disabled by the RCW, and then enable bank three. The + * devices need to be enabled before either bank is + * powered up. + */ + p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr, + serdes8_devdisr2, cfg); + } else if (idx == 2) { + /* Enable bank two now that bank three is enabled. */ + enable_bank(gur, FSL_SRDS_BANK_2); + } +#endif + + wait_for_rstdone(bank); + } + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 + if (need_serdes_a001) { + /* Bank 3 has been enabled, so now we can disable bank 2 */ + setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl, + SRDS_RSTCTL_SDPD); + } +#endif +} + +const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + case SRDS_PLLCR0_RFCK_SEL_161_13: + return "161.1328123"; + default: + return "150"; + } +} + diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h new file mode 100644 index 000000000..c02dd20af --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h @@ -0,0 +1,28 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * Author: Roy Zang <tie-fei.zang@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_CORENET_SERDES_H +#define __FSL_CORENET_SERDES_H + +enum srds_bank { + FSL_SRDS_BANK_1 = 0, + FSL_SRDS_BANK_2 = 1, + FSL_SRDS_BANK_3 = 2, +}; + +int is_serdes_prtcl_valid(u32 prtcl); +int serdes_get_lane_idx(int lane); +int serdes_get_bank_by_lane(int lane); +int serdes_lane_enabled(int lane); +enum srds_prtcl serdes_get_prtcl(int cfg, int lane); + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 +extern uint16_t srds_lpd_b[SRDS_MAX_BANK]; +#endif + +#endif /* __FSL_CORENET_SERDES_H */ diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/interrupts.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/interrupts.c new file mode 100644 index 000000000..a36a4af9d --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/interrupts.c @@ -0,0 +1,110 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 (440 port) + * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com + * + * (C) Copyright 2003 Motorola Inc. (MPC85xx port) + * Xianghua Xiao (X.Xiao@motorola.com) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <watchdog.h> +#include <command.h> +#include <asm/processor.h> +#include <asm/io.h> +#ifdef CONFIG_POST +#include <post.h> +#endif + +int interrupt_init_cpu(unsigned int *decrementer_count) +{ + ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; + +#ifdef CONFIG_POST + /* + * The POST word is stored in the PIC's TFRR register which gets + * cleared when the PIC is reset. Save it off so we can restore it + * later. + */ + ulong post_word = post_word_load(); +#endif + + out_be32(&pic->gcr, MPC85xx_PICGCR_RST); + while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST) + ; + out_be32(&pic->gcr, MPC85xx_PICGCR_M); + in_be32(&pic->gcr); + + *decrementer_count = get_tbclk() / CONFIG_SYS_HZ; + + /* PIE is same as DIE, dec interrupt enable */ + mtspr(SPRN_TCR, TCR_PIE); + +#ifdef CONFIG_INTERRUPTS + pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */ + debug("iivpr1@%x = %x\n", (uint)&pic->iivpr1, pic->iivpr1); + + pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ + debug("iivpr2@%x = %x\n", (uint)&pic->iivpr2, pic->iivpr2); + + pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */ + debug("iivpr3@%x = %x\n", (uint)&pic->iivpr3, pic->iivpr3); + +#ifdef CONFIG_PCI1 + pic->iivpr8 = 0x810008; /* enable pci1 interrupts */ + debug("iivpr8@%x = %x\n", (uint)&pic->iivpr8, pic->iivpr8); +#endif +#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2) + pic->iivpr9 = 0x810009; /* enable pci1 interrupts */ + debug("iivpr9@%x = %x\n", (uint)&pic->iivpr9, pic->iivpr9); +#endif +#ifdef CONFIG_PCIE1 + pic->iivpr10 = 0x81000a; /* enable pcie1 interrupts */ + debug("iivpr10@%x = %x\n", (uint)&pic->iivpr10, pic->iivpr10); +#endif +#ifdef CONFIG_PCIE3 + pic->iivpr11 = 0x81000b; /* enable pcie3 interrupts */ + debug("iivpr11@%x = %x\n", (uint)&pic->iivpr11, pic->iivpr11); +#endif + + pic->ctpr=0; /* 40080 clear current task priority register */ +#endif + +#ifdef CONFIG_POST + post_word_store(post_word); +#endif + + return (0); +} + +/* Install and free a interrupt handler. Not implemented yet. */ + +void +irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) +{ + return; +} + +void +irq_free_handler(int vec) +{ + return; +} + +void timer_interrupt_cpu(struct pt_regs *regs) +{ + /* PIS is same as DIS, dec interrupt status */ + mtspr(SPRN_TSR, TSR_PIS); +} + +#if defined(CONFIG_CMD_IRQ) +/* irqinfo - print information about PCI devices,not implemented. */ +int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + return 0; +} +#endif diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/liodn.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/liodn.c new file mode 100644 index 000000000..19e130e87 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/liodn.c @@ -0,0 +1,359 @@ +/* + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <libfdt.h> +#include <fdt_support.h> + +#include <asm/immap_85xx.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev, u32 *liodns, int liodn_offset) +{ + liodns[0] = liodn_bases[dpaa_dev].id[0] + liodn_offset; + + if (liodn_bases[dpaa_dev].num_ids == 2) + liodns[1] = liodn_bases[dpaa_dev].id[1] + liodn_offset; + + return liodn_bases[dpaa_dev].num_ids; +} + +#ifdef CONFIG_SYS_SRIO +static void set_srio_liodn(struct srio_liodn_id_table *tbl, int size) +{ + int i; + + for (i = 0; i < size; i++) { + unsigned long reg_off = tbl[i].reg_offset[0]; + out_be32((u32 *)reg_off, tbl[i].id[0]); + + if (tbl[i].num_ids == 2) { + reg_off = tbl[i].reg_offset[1]; + out_be32((u32 *)reg_off, tbl[i].id[1]); + } + } +} +#endif + +static void set_liodn(struct liodn_id_table *tbl, int size) +{ + int i; + + for (i = 0; i < size; i++) { + u32 liodn; + if (tbl[i].num_ids == 2) { + liodn = (tbl[i].id[0] << 16) | tbl[i].id[1]; + } else { + liodn = tbl[i].id[0]; + } + + out_be32((volatile u32 *)(tbl[i].reg_offset), liodn); + } +} + +static void setup_sec_liodn_base(void) +{ + ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + u32 base; + + if (!IS_E_PROCESSOR(get_svr())) + return; + + /* QILCR[QSLOM] */ + out_be32(&sec->qilcr_ms, 0x3ff<<16); + + base = (liodn_bases[FSL_HW_PORTAL_SEC].id[0] << 16) | + liodn_bases[FSL_HW_PORTAL_SEC].id[1]; + + out_be32(&sec->qilcr_ls, base); +} + +#ifdef CONFIG_SYS_DPAA_FMAN +static void setup_fman_liodn_base(enum fsl_dpaa_dev dev, + struct liodn_id_table *tbl, int size) +{ + int i; + ccsr_fman_t *fm; + u32 base; + + switch(dev) { + case FSL_HW_PORTAL_FMAN1: + fm = (void *)CONFIG_SYS_FSL_FM1_ADDR; + break; + +#if (CONFIG_SYS_NUM_FMAN == 2) + case FSL_HW_PORTAL_FMAN2: + fm = (void *)CONFIG_SYS_FSL_FM2_ADDR; + break; +#endif + default: + printf("Error: Invalid device type to %s\n", __FUNCTION__); + return ; + } + + base = (liodn_bases[dev].id[0] << 16) | liodn_bases[dev].id[0]; + + /* setup all bases the same */ + for (i = 0; i < 32; i++) { + out_be32(&fm->fm_dma.fmdmplr[i], base); + } + + /* update tbl to ... */ + for (i = 0; i < size; i++) + tbl[i].id[0] += liodn_bases[dev].id[0]; +} +#endif + +static void setup_pme_liodn_base(void) +{ +#ifdef CONFIG_SYS_DPAA_PME + ccsr_pme_t *pme = (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR; + u32 base = (liodn_bases[FSL_HW_PORTAL_PME].id[0] << 16) | + liodn_bases[FSL_HW_PORTAL_PME].id[1]; + + out_be32(&pme->liodnbr, base); +#endif +} + +#ifdef CONFIG_SYS_FSL_RAID_ENGINE +static void setup_raide_liodn_base(void) +{ + struct ccsr_raide *raide = (void *)CONFIG_SYS_FSL_RAID_ENGINE_ADDR; + + /* setup raid engine liodn base for data/desc ; both set to 47 */ + u32 base = (liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0] << 16) | + liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0]; + + out_be32(&raide->liodnbr, base); +} +#endif + +#ifdef CONFIG_SYS_DPAA_RMAN +static void set_rman_liodn(struct liodn_id_table *tbl, int size) +{ + int i; + struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR; + + for (i = 0; i < size; i++) { + /* write the RMan block number */ + out_be32(&rman->mmitar, i); + /* write the liodn offset corresponding to the block */ + out_be32((u32 *)(tbl[i].reg_offset), tbl[i].id[0]); + } +} + +static void setup_rman_liodn_base(struct liodn_id_table *tbl, int size) +{ + int i; + struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR; + u32 base = liodn_bases[FSL_HW_PORTAL_RMAN].id[0]; + + out_be32(&rman->mmliodnbr, base); + + /* update liodn offset */ + for (i = 0; i < size; i++) + tbl[i].id[0] += base; +} +#endif + +void set_liodns(void) +{ + /* setup general liodn offsets */ + set_liodn(liodn_tbl, liodn_tbl_sz); + +#ifdef CONFIG_SYS_SRIO + /* setup SRIO port liodns */ + set_srio_liodn(srio_liodn_tbl, srio_liodn_tbl_sz); +#endif + + /* setup SEC block liodn bases & offsets if we have one */ + if (IS_E_PROCESSOR(get_svr())) { + set_liodn(sec_liodn_tbl, sec_liodn_tbl_sz); + setup_sec_liodn_base(); + } + + /* setup FMAN block(s) liodn bases & offsets if we have one */ +#ifdef CONFIG_SYS_DPAA_FMAN + set_liodn(fman1_liodn_tbl, fman1_liodn_tbl_sz); + setup_fman_liodn_base(FSL_HW_PORTAL_FMAN1, fman1_liodn_tbl, + fman1_liodn_tbl_sz); + +#if (CONFIG_SYS_NUM_FMAN == 2) + set_liodn(fman2_liodn_tbl, fman2_liodn_tbl_sz); + setup_fman_liodn_base(FSL_HW_PORTAL_FMAN2, fman2_liodn_tbl, + fman2_liodn_tbl_sz); +#endif +#endif + /* setup PME liodn base */ + setup_pme_liodn_base(); + +#ifdef CONFIG_SYS_FSL_RAID_ENGINE + /* raid engine ccr addr code for liodn */ + set_liodn(raide_liodn_tbl, raide_liodn_tbl_sz); + setup_raide_liodn_base(); +#endif + +#ifdef CONFIG_SYS_DPAA_RMAN + /* setup RMan liodn offsets */ + set_rman_liodn(rman_liodn_tbl, rman_liodn_tbl_sz); + /* setup RMan liodn base */ + setup_rman_liodn_base(rman_liodn_tbl, rman_liodn_tbl_sz); +#endif +} + +#ifdef CONFIG_SYS_SRIO +static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl) +{ + int i, srio_off; + + /* search for srio node, if doesn't exist just return - nothing todo */ + srio_off = fdt_node_offset_by_compatible(blob, -1, "fsl,srio"); + if (srio_off < 0) + return ; + + for (i = 0; i < srio_liodn_tbl_sz; i++) { + int off, portid = tbl[i].portid; + + off = fdt_node_offset_by_prop_value(blob, srio_off, + "cell-index", &portid, 4); + if (off >= 0) { + off = fdt_setprop(blob, off, "fsl,liodn", + &tbl[i].id[0], + sizeof(u32) * tbl[i].num_ids); + if (off > 0) + printf("WARNING unable to set fsl,liodn for " + "fsl,srio port %d: %s\n", + portid, fdt_strerror(off)); + } else { + debug("WARNING: couldn't set fsl,liodn for srio: %s.\n", + fdt_strerror(off)); + } + } +} +#endif + +#define CONFIG_SYS_MAX_PCI_EPS 8 + +static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat, + int ep_liodn_start) +{ + int off, pci_idx = 0, pci_cnt = 0, i, rc; + const uint32_t *base_liodn; + uint32_t liodn_offs[CONFIG_SYS_MAX_PCI_EPS + 1] = { 0 }; + + /* + * Count the number of pci nodes. + * It's needed later when the interleaved liodn offsets are generated. + */ + off = fdt_node_offset_by_compatible(fdt, -1, compat); + while (off != -FDT_ERR_NOTFOUND) { + pci_cnt++; + off = fdt_node_offset_by_compatible(fdt, off, compat); + } + + for (off = fdt_node_offset_by_compatible(fdt, -1, compat); + off != -FDT_ERR_NOTFOUND; + off = fdt_node_offset_by_compatible(fdt, off, compat)) { + base_liodn = fdt_getprop(fdt, off, "fsl,liodn", &rc); + if (!base_liodn) { + char path[64]; + + if (fdt_get_path(fdt, off, path, sizeof(path)) < 0) + strcpy(path, "(unknown)"); + printf("WARNING Could not get liodn of node %s: %s\n", + path, fdt_strerror(rc)); + continue; + } + for (i = 0; i < CONFIG_SYS_MAX_PCI_EPS; i++) + liodn_offs[i + 1] = ep_liodn_start + + i * pci_cnt + pci_idx - *base_liodn; + rc = fdt_setprop(fdt, off, "fsl,liodn-offset-list", + liodn_offs, sizeof(liodn_offs)); + if (rc) { + char path[64]; + + if (fdt_get_path(fdt, off, path, sizeof(path)) < 0) + strcpy(path, "(unknown)"); + printf("WARNING Unable to set fsl,liodn-offset-list for " + "node %s: %s\n", path, fdt_strerror(rc)); + continue; + } + pci_idx++; + } +} + +static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz) +{ + int i; + + for (i = 0; i < sz; i++) { + int off; + + if (tbl[i].compat == NULL) + continue; + + off = fdt_node_offset_by_compat_reg(blob, + tbl[i].compat, tbl[i].compat_offset); + if (off >= 0) { + off = fdt_setprop(blob, off, "fsl,liodn", + &tbl[i].id[0], + sizeof(u32) * tbl[i].num_ids); + if (off > 0) + printf("WARNING unable to set fsl,liodn for " + "%s: %s\n", + tbl[i].compat, fdt_strerror(off)); + } else { + debug("WARNING: could not set fsl,liodn for %s: %s.\n", + tbl[i].compat, fdt_strerror(off)); + } + } +} + +void fdt_fixup_liodn(void *blob) +{ +#ifdef CONFIG_SYS_SRIO + fdt_fixup_srio_liodn(blob, srio_liodn_tbl); +#endif + + fdt_fixup_liodn_tbl(blob, liodn_tbl, liodn_tbl_sz); +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_liodn_tbl(blob, fman1_liodn_tbl, fman1_liodn_tbl_sz); +#if (CONFIG_SYS_NUM_FMAN == 2) + fdt_fixup_liodn_tbl(blob, fman2_liodn_tbl, fman2_liodn_tbl_sz); +#endif +#endif + fdt_fixup_liodn_tbl(blob, sec_liodn_tbl, sec_liodn_tbl_sz); + +#ifdef CONFIG_SYS_FSL_RAID_ENGINE + fdt_fixup_liodn_tbl(blob, raide_liodn_tbl, raide_liodn_tbl_sz); +#endif + +#ifdef CONFIG_SYS_DPAA_RMAN + fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz); +#endif + + ccsr_pcix_t *pcix = (ccsr_pcix_t *)CONFIG_SYS_PCIE1_ADDR; + int pci_ver = pcix->ipver1 & 0xffff, liodn_base = 0; + + if (pci_ver >= 0x0204) { + if (pci_ver >= 0x0300) + liodn_base = 1024; + else + liodn_base = 256; + } + + if (liodn_base) { + char compat[32]; + + sprintf(compat, "fsl,qoriq-pcie-v%d.%d", + (pci_ver & 0xff00) >> 8, pci_ver & 0xff); + fdt_fixup_pci_liodn_offsets(blob, compat, liodn_base); + fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie", liodn_base); + } +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mp.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mp.c new file mode 100644 index 000000000..88c8e6593 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mp.c @@ -0,0 +1,472 @@ +/* + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/processor.h> +#include <ioports.h> +#include <lmb.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <asm/fsl_law.h> +#include <fsl_ddr_sdram.h> +#include "mp.h" + +DECLARE_GLOBAL_DATA_PTR; +u32 fsl_ddr_get_intl3r(void); + +extern u32 __spin_table[]; + +u32 get_my_id() +{ + return mfspr(SPRN_PIR); +} + +/* + * Determine if U-Boot should keep secondary cores in reset, or let them out + * of reset and hold them in a spinloop + */ +int hold_cores_in_reset(int verbose) +{ + /* Default to no, overriden by 'y', 'yes', 'Y', 'Yes', or '1' */ + if (getenv_yesno("mp_holdoff") == 1) { + if (verbose) { + puts("Secondary cores are being held in reset.\n"); + puts("See 'mp_holdoff' environment variable\n"); + } + + return 1; + } + + return 0; +} + +int cpu_reset(int nr) +{ + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); + out_be32(&pic->pir, 1 << nr); + /* the dummy read works around an errata on early 85xx MP PICs */ + (void)in_be32(&pic->pir); + out_be32(&pic->pir, 0x0); + + return 0; +} + +int cpu_status(int nr) +{ + u32 *table, id = get_my_id(); + + if (hold_cores_in_reset(1)) + return 0; + + if (nr == id) { + table = (u32 *)&__spin_table; + printf("table base @ 0x%p\n", table); + } else if (is_core_disabled(nr)) { + puts("Disabled\n"); + } else { + table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY; + printf("Running on cpu %d\n", id); + printf("\n"); + printf("table @ 0x%p\n", table); + printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]); + printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]); + printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]); + } + + return 0; +} + +#ifdef CONFIG_FSL_CORENET +int cpu_disable(int nr) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->coredisrl, 1 << nr); + + return 0; +} + +int is_core_disabled(int nr) { + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 coredisrl = in_be32(&gur->coredisrl); + + return (coredisrl & (1 << nr)); +} +#else +int cpu_disable(int nr) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + switch (nr) { + case 0: + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0); + break; + case 1: + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1); + break; + default: + printf("Invalid cpu number for disable %d\n", nr); + return 1; + } + + return 0; +} + +int is_core_disabled(int nr) { + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr = in_be32(&gur->devdisr); + + switch (nr) { + case 0: + return (devdisr & MPC85xx_DEVDISR_CPU0); + case 1: + return (devdisr & MPC85xx_DEVDISR_CPU1); + default: + printf("Invalid cpu number for disable %d\n", nr); + } + + return 0; +} +#endif + +static u8 boot_entry_map[4] = { + 0, + BOOT_ENTRY_PIR, + BOOT_ENTRY_R3_LOWER, +}; + +int cpu_release(int nr, int argc, char * const argv[]) +{ + u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY; + u64 boot_addr; + + if (hold_cores_in_reset(1)) + return 0; + + if (nr == get_my_id()) { + printf("Invalid to release the boot core.\n\n"); + return 1; + } + + if (argc != 4) { + printf("Invalid number of arguments to release.\n\n"); + return 1; + } + + boot_addr = simple_strtoull(argv[0], NULL, 16); + + /* handle pir, r3 */ + for (i = 1; i < 3; i++) { + if (argv[i][0] != '-') { + u8 entry = boot_entry_map[i]; + val = simple_strtoul(argv[i], NULL, 16); + table[entry] = val; + } + } + + table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32); + + /* ensure all table updates complete before final address write */ + eieio(); + + table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff); + + return 0; +} + +u32 determine_mp_bootpg(unsigned int *pagesize) +{ + u32 bootpg; +#ifdef CONFIG_SYS_FSL_ERRATUM_A004468 + u32 svr = get_svr(); + u32 granule_size, check; + struct law_entry e; +#endif + + + /* use last 4K of mapped memory */ + bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? + CONFIG_MAX_MEM_MAPPED : gd->ram_size) + + CONFIG_SYS_SDRAM_BASE - 4096; + if (pagesize) + *pagesize = 4096; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A004468 +/* + * Erratum A004468 has two parts. The 3-way interleaving applies to T4240, + * to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But + * the way boot page chosen in u-boot avoids hitting this erratum. So only + * thw workaround for 3-way interleaving is needed. + * + * To make sure boot page translation works with 3-Way DDR interleaving + * enforce a check for the following constrains + * 8K granule size requires BRSIZE=8K and + * bootpg >> log2(BRSIZE) %3 == 1 + * 4K and 1K granule size requires BRSIZE=4K and + * bootpg >> log2(BRSIZE) %3 == 0 + */ + if (SVR_SOC_VER(svr) == SVR_T4240 && SVR_MAJ(svr) < 2) { + e = find_law(bootpg); + switch (e.trgt_id) { + case LAW_TRGT_IF_DDR_INTLV_123: + granule_size = fsl_ddr_get_intl3r() & 0x1f; + if (granule_size == FSL_DDR_3WAY_8KB_INTERLEAVING) { + if (pagesize) + *pagesize = 8192; + bootpg &= 0xffffe000; /* align to 8KB */ + check = bootpg >> 13; + while ((check % 3) != 1) + check--; + bootpg = check << 13; + debug("Boot page (8K) at 0x%08x\n", bootpg); + break; + } else { + bootpg &= 0xfffff000; /* align to 4KB */ + check = bootpg >> 12; + while ((check % 3) != 0) + check--; + bootpg = check << 12; + debug("Boot page (4K) at 0x%08x\n", bootpg); + } + break; + default: + break; + } + } +#endif /* CONFIG_SYS_FSL_ERRATUM_A004468 */ + + return bootpg; +} + +phys_addr_t get_spin_phys_addr(void) +{ + return virt_to_phys(&__spin_table); +} + +#ifdef CONFIG_FSL_CORENET +static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) +{ + u32 cpu_up_mask, whoami, brsize = LAW_SIZE_4K; + u32 *table = (u32 *)&__spin_table; + volatile ccsr_gur_t *gur; + volatile ccsr_local_t *ccm; + volatile ccsr_rcpm_t *rcpm; + volatile ccsr_pic_t *pic; + int timeout = 10; + u32 mask = cpu_mask(); + struct law_entry e; + + gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); + rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); + pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); + + whoami = in_be32(&pic->whoami); + cpu_up_mask = 1 << whoami; + out_be32(&ccm->bstrl, bootpg); + + e = find_law(bootpg); + /* pagesize is only 4K or 8K */ + if (pagesize == 8192) + brsize = LAW_SIZE_8K; + out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize); + debug("BRSIZE is 0x%x\n", brsize); + + /* readback to sync write */ + in_be32(&ccm->bstrar); + + /* disable time base at the platform */ + out_be32(&rcpm->ctbenrl, cpu_up_mask); + + out_be32(&gur->brrl, mask); + + /* wait for everyone */ + while (timeout) { + unsigned int i, cpu, nr_cpus = cpu_numcores(); + + for_each_cpu(i, cpu, nr_cpus, mask) { + if (table[cpu * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) + cpu_up_mask |= (1 << cpu); + } + + if ((cpu_up_mask & mask) == mask) + break; + + udelay(100); + timeout--; + } + + if (timeout == 0) + printf("CPU up timeout. CPU up mask is %x should be %x\n", + cpu_up_mask, mask); + + /* enable time base at the platform */ + out_be32(&rcpm->ctbenrl, 0); + + /* readback to sync write */ + in_be32(&rcpm->ctbenrl); + + mtspr(SPRN_TBWU, 0); + mtspr(SPRN_TBWL, 0); + + out_be32(&rcpm->ctbenrl, mask); + +#ifdef CONFIG_MPC8xxx_DISABLE_BPTR + /* + * Disabling Boot Page Translation allows the memory region 0xfffff000 + * to 0xffffffff to be used normally. Leaving Boot Page Translation + * enabled remaps 0xfffff000 to SDRAM which makes that memory region + * unusable for normal operation but it does allow OSes to easily + * reset a processor core to put it back into U-Boot's spinloop. + */ + clrbits_be32(&ccm->bstrar, LAW_EN); +#endif +} +#else +static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) +{ + u32 up, cpu_up_mask, whoami; + u32 *table = (u32 *)&__spin_table; + volatile u32 bpcr; + volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); + u32 devdisr; + int timeout = 10; + + whoami = in_be32(&pic->whoami); + out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12)); + + /* disable time base at the platform */ + devdisr = in_be32(&gur->devdisr); + if (whoami) + devdisr |= MPC85xx_DEVDISR_TB0; + else + devdisr |= MPC85xx_DEVDISR_TB1; + out_be32(&gur->devdisr, devdisr); + + /* release the hounds */ + up = ((1 << cpu_numcores()) - 1); + bpcr = in_be32(&ecm->eebpcr); + bpcr |= (up << 24); + out_be32(&ecm->eebpcr, bpcr); + asm("sync; isync; msync"); + + cpu_up_mask = 1 << whoami; + /* wait for everyone */ + while (timeout) { + int i; + for (i = 0; i < cpu_numcores(); i++) { + if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) + cpu_up_mask |= (1 << i); + }; + + if ((cpu_up_mask & up) == up) + break; + + udelay(100); + timeout--; + } + + if (timeout == 0) + printf("CPU up timeout. CPU up mask is %x should be %x\n", + cpu_up_mask, up); + + /* enable time base at the platform */ + if (whoami) + devdisr |= MPC85xx_DEVDISR_TB1; + else + devdisr |= MPC85xx_DEVDISR_TB0; + out_be32(&gur->devdisr, devdisr); + + /* readback to sync write */ + in_be32(&gur->devdisr); + + mtspr(SPRN_TBWU, 0); + mtspr(SPRN_TBWL, 0); + + devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1); + out_be32(&gur->devdisr, devdisr); + +#ifdef CONFIG_MPC8xxx_DISABLE_BPTR + /* + * Disabling Boot Page Translation allows the memory region 0xfffff000 + * to 0xffffffff to be used normally. Leaving Boot Page Translation + * enabled remaps 0xfffff000 to SDRAM which makes that memory region + * unusable for normal operation but it does allow OSes to easily + * reset a processor core to put it back into U-Boot's spinloop. + */ + clrbits_be32(&ecm->bptr, 0x80000000); +#endif +} +#endif + +void cpu_mp_lmb_reserve(struct lmb *lmb) +{ + u32 bootpg = determine_mp_bootpg(NULL); + + lmb_reserve(lmb, bootpg, 4096); +} + +void setup_mp(void) +{ + extern u32 __secondary_start_page; + extern u32 __bootpg_addr, __spin_table_addr, __second_half_boot_page; + + int i; + ulong fixup = (u32)&__secondary_start_page; + u32 bootpg, bootpg_map, pagesize; + + bootpg = determine_mp_bootpg(&pagesize); + + /* + * pagesize is only 4K or 8K + * we only use the last 4K of boot page + * bootpg_map saves the address for the boot page + * 8K is used for the workaround of 3-way DDR interleaving + */ + + bootpg_map = bootpg; + + if (pagesize == 8192) + bootpg += 4096; /* use 2nd half */ + + /* Some OSes expect secondary cores to be held in reset */ + if (hold_cores_in_reset(0)) + return; + + /* + * Store the bootpg's cache-able half address for use by secondary + * CPU cores to continue to boot + */ + __bootpg_addr = (u32)virt_to_phys(&__second_half_boot_page); + + /* Store spin table's physical address for use by secondary cores */ + __spin_table_addr = (u32)get_spin_phys_addr(); + + /* flush bootpg it before copying invalidate any staled cacheline */ + flush_cache(bootpg, 4096); + + /* look for the tlb covering the reset page, there better be one */ + i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1); + + /* we found a match */ + if (i != -1) { + /* map reset page to bootpg so we can copy code there */ + disable_tlb(i); + + set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */ + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ + 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ + + memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096); + + plat_mp_up(bootpg_map, pagesize); + } else { + puts("WARNING: No reset page TLB. " + "Skipping secondary core setup\n"); + } +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mp.h b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mp.h new file mode 100644 index 000000000..ad9950bcf --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mp.h @@ -0,0 +1,21 @@ +#ifndef __MPC85XX_MP_H_ +#define __MPC85XX_MP_H_ + +#include <asm/mp.h> + +phys_addr_t get_spin_phys_addr(void); +u32 get_my_id(void); +int hold_cores_in_reset(int verbose); + +#define BOOT_ENTRY_ADDR_UPPER 0 +#define BOOT_ENTRY_ADDR_LOWER 1 +#define BOOT_ENTRY_R3_UPPER 2 +#define BOOT_ENTRY_R3_LOWER 3 +#define BOOT_ENTRY_RESV 4 +#define BOOT_ENTRY_PIR 5 +#define BOOT_ENTRY_R6_UPPER 6 +#define BOOT_ENTRY_R6_LOWER 7 +#define NUM_BOOT_ENTRY 16 /* pad to 64 bytes */ +#define SIZE_BOOT_ENTRY (NUM_BOOT_ENTRY * sizeof(u32)) + +#endif diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c new file mode 100644 index 000000000..baf52d549 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c @@ -0,0 +1,233 @@ +/* + * Copyright 2008,2010 Freescale Semiconductor, Inc. + * Dave Liu <daveliu@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +/* PORDEVSR register */ +#define GUTS_PORDEVSR_OFFS 0xc +#define GUTS_PORDEVSR_SERDES2_IO_SEL 0x38000000 +#define GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT 27 + +/* SerDes CR0 register */ +#define FSL_SRDSCR0_OFFS 0x0 +#define FSL_SRDSCR0_TXEQA_MASK 0x00007000 +#define FSL_SRDSCR0_TXEQA_SGMII 0x00004000 +#define FSL_SRDSCR0_TXEQA_SATA 0x00001000 +#define FSL_SRDSCR0_TXEQE_MASK 0x00000700 +#define FSL_SRDSCR0_TXEQE_SGMII 0x00000400 +#define FSL_SRDSCR0_TXEQE_SATA 0x00000100 + +/* SerDes CR1 register */ +#define FSL_SRDSCR1_OFFS 0x4 +#define FSL_SRDSCR1_LANEA_MASK 0x80200000 +#define FSL_SRDSCR1_LANEA_OFF 0x80200000 +#define FSL_SRDSCR1_LANEE_MASK 0x08020000 +#define FSL_SRDSCR1_LANEE_OFF 0x08020000 + +/* SerDes CR2 register */ +#define FSL_SRDSCR2_OFFS 0x8 +#define FSL_SRDSCR2_EICA_MASK 0x00001f00 +#define FSL_SRDSCR2_EICA_SGMII 0x00000400 +#define FSL_SRDSCR2_EICA_SATA 0x00001400 +#define FSL_SRDSCR2_EICE_MASK 0x0000001f +#define FSL_SRDSCR2_EICE_SGMII 0x00000004 +#define FSL_SRDSCR2_EICE_SATA 0x00000014 + +/* SerDes CR3 register */ +#define FSL_SRDSCR3_OFFS 0xc +#define FSL_SRDSCR3_LANEA_MASK 0x3f000700 +#define FSL_SRDSCR3_LANEA_SGMII 0x00000000 +#define FSL_SRDSCR3_LANEA_SATA 0x15000500 +#define FSL_SRDSCR3_LANEE_MASK 0x003f0007 +#define FSL_SRDSCR3_LANEE_SGMII 0x00000000 +#define FSL_SRDSCR3_LANEE_SATA 0x00150005 + +#define SRDS1_MAX_LANES 8 +#define SRDS2_MAX_LANES 2 + +static u32 serdes1_prtcl_map, serdes2_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE}, + [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}, + [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}, + [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3}, +}; + +static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x1] = {SATA1, SATA2}, + [0x3] = {SATA1, NONE}, + [0x4] = {SGMII_TSEC1, SGMII_TSEC3}, + [0x6] = {SGMII_TSEC1, NONE}, +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = (1 << device) & serdes1_prtcl_map; + + if (ret) + return ret; + + return (1 << device) & serdes2_prtcl_map; +} + +void fsl_serdes_init(void) +{ + void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + void *sd = (void *)CONFIG_SYS_MPC85xx_SERDES2_ADDR; + u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS); + u32 srds1_io_sel, srds2_io_sel; + u32 tmp; + int lane; + + srds1_io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + + /* parse the SRDS2_IO_SEL of PORDEVSR */ + srds2_io_sel = (pordevsr & GUTS_PORDEVSR_SERDES2_IO_SEL) + >> GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT; + + debug("PORDEVSR[SRDS1_IO_SEL] = %x\n", srds1_io_sel); + debug("PORDEVSR[SRDS2_IO_SEL] = %x\n", srds2_io_sel); + + switch (srds2_io_sel) { + case 1: /* Lane A - SATA1, Lane E - SATA2 */ + /* CR 0 */ + tmp = in_be32(sd + FSL_SRDSCR0_OFFS); + tmp &= ~FSL_SRDSCR0_TXEQA_MASK; + tmp |= FSL_SRDSCR0_TXEQA_SATA; + tmp &= ~FSL_SRDSCR0_TXEQE_MASK; + tmp |= FSL_SRDSCR0_TXEQE_SATA; + out_be32(sd + FSL_SRDSCR0_OFFS, tmp); + /* CR 1 */ + tmp = in_be32(sd + FSL_SRDSCR1_OFFS); + tmp &= ~FSL_SRDSCR1_LANEA_MASK; + tmp &= ~FSL_SRDSCR1_LANEE_MASK; + out_be32(sd + FSL_SRDSCR1_OFFS, tmp); + /* CR 2 */ + tmp = in_be32(sd + FSL_SRDSCR2_OFFS); + tmp &= ~FSL_SRDSCR2_EICA_MASK; + tmp |= FSL_SRDSCR2_EICA_SATA; + tmp &= ~FSL_SRDSCR2_EICE_MASK; + tmp |= FSL_SRDSCR2_EICE_SATA; + out_be32(sd + FSL_SRDSCR2_OFFS, tmp); + /* CR 3 */ + tmp = in_be32(sd + FSL_SRDSCR3_OFFS); + tmp &= ~FSL_SRDSCR3_LANEA_MASK; + tmp |= FSL_SRDSCR3_LANEA_SATA; + tmp &= ~FSL_SRDSCR3_LANEE_MASK; + tmp |= FSL_SRDSCR3_LANEE_SATA; + out_be32(sd + FSL_SRDSCR3_OFFS, tmp); + break; + case 3: /* Lane A - SATA1, Lane E - disabled */ + /* CR 0 */ + tmp = in_be32(sd + FSL_SRDSCR0_OFFS); + tmp &= ~FSL_SRDSCR0_TXEQA_MASK; + tmp |= FSL_SRDSCR0_TXEQA_SATA; + out_be32(sd + FSL_SRDSCR0_OFFS, tmp); + /* CR 1 */ + tmp = in_be32(sd + FSL_SRDSCR1_OFFS); + tmp &= ~FSL_SRDSCR1_LANEE_MASK; + tmp |= FSL_SRDSCR1_LANEE_OFF; + out_be32(sd + FSL_SRDSCR1_OFFS, tmp); + /* CR 2 */ + tmp = in_be32(sd + FSL_SRDSCR2_OFFS); + tmp &= ~FSL_SRDSCR2_EICA_MASK; + tmp |= FSL_SRDSCR2_EICA_SATA; + out_be32(sd + FSL_SRDSCR2_OFFS, tmp); + /* CR 3 */ + tmp = in_be32(sd + FSL_SRDSCR3_OFFS); + tmp &= ~FSL_SRDSCR3_LANEA_MASK; + tmp |= FSL_SRDSCR3_LANEA_SATA; + out_be32(sd + FSL_SRDSCR3_OFFS, tmp); + break; + case 4: /* Lane A - eTSEC1 SGMII, Lane E - eTSEC3 SGMII */ + /* CR 0 */ + tmp = in_be32(sd + FSL_SRDSCR0_OFFS); + tmp &= ~FSL_SRDSCR0_TXEQA_MASK; + tmp |= FSL_SRDSCR0_TXEQA_SGMII; + tmp &= ~FSL_SRDSCR0_TXEQE_MASK; + tmp |= FSL_SRDSCR0_TXEQE_SGMII; + out_be32(sd + FSL_SRDSCR0_OFFS, tmp); + /* CR 1 */ + tmp = in_be32(sd + FSL_SRDSCR1_OFFS); + tmp &= ~FSL_SRDSCR1_LANEA_MASK; + tmp &= ~FSL_SRDSCR1_LANEE_MASK; + out_be32(sd + FSL_SRDSCR1_OFFS, tmp); + /* CR 2 */ + tmp = in_be32(sd + FSL_SRDSCR2_OFFS); + tmp &= ~FSL_SRDSCR2_EICA_MASK; + tmp |= FSL_SRDSCR2_EICA_SGMII; + tmp &= ~FSL_SRDSCR2_EICE_MASK; + tmp |= FSL_SRDSCR2_EICE_SGMII; + out_be32(sd + FSL_SRDSCR2_OFFS, tmp); + /* CR 3 */ + tmp = in_be32(sd + FSL_SRDSCR3_OFFS); + tmp &= ~FSL_SRDSCR3_LANEA_MASK; + tmp |= FSL_SRDSCR3_LANEA_SGMII; + tmp &= ~FSL_SRDSCR3_LANEE_MASK; + tmp |= FSL_SRDSCR3_LANEE_SGMII; + out_be32(sd + FSL_SRDSCR3_OFFS, tmp); + break; + case 6: /* Lane A - eTSEC1 SGMII, Lane E - disabled */ + /* CR 0 */ + tmp = in_be32(sd + FSL_SRDSCR0_OFFS); + tmp &= ~FSL_SRDSCR0_TXEQA_MASK; + tmp |= FSL_SRDSCR0_TXEQA_SGMII; + out_be32(sd + FSL_SRDSCR0_OFFS, tmp); + /* CR 1 */ + tmp = in_be32(sd + FSL_SRDSCR1_OFFS); + tmp &= ~FSL_SRDSCR1_LANEE_MASK; + tmp |= FSL_SRDSCR1_LANEE_OFF; + out_be32(sd + FSL_SRDSCR1_OFFS, tmp); + /* CR 2 */ + tmp = in_be32(sd + FSL_SRDSCR2_OFFS); + tmp &= ~FSL_SRDSCR2_EICA_MASK; + tmp |= FSL_SRDSCR2_EICA_SGMII; + out_be32(sd + FSL_SRDSCR2_OFFS, tmp); + /* CR 3 */ + tmp = in_be32(sd + FSL_SRDSCR3_OFFS); + tmp &= ~FSL_SRDSCR3_LANEA_MASK; + tmp |= FSL_SRDSCR3_LANEA_SGMII; + out_be32(sd + FSL_SRDSCR3_OFFS, tmp); + break; + case 7: /* Lane A - disabled, Lane E - disabled */ + /* CR 1 */ + tmp = in_be32(sd + FSL_SRDSCR1_OFFS); + tmp &= ~FSL_SRDSCR1_LANEA_MASK; + tmp |= FSL_SRDSCR1_LANEA_OFF; + tmp &= ~FSL_SRDSCR1_LANEE_MASK; + tmp |= FSL_SRDSCR1_LANEE_OFF; + out_be32(sd + FSL_SRDSCR1_OFFS, tmp); + break; + default: + break; + } + + if (srds1_io_sel >= ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[SRDS1_IO_SEL] = %d\n", srds1_io_sel); + return; + } + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_io_sel][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + + if (srds2_io_sel >= ARRAY_SIZE(serdes2_cfg_tbl)) { + printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_io_sel); + return; + } + + for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds2_io_sel][lane]; + serdes2_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c new file mode 100644 index 000000000..ed78a66f5 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c @@ -0,0 +1,79 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 8 +#define SRDS2_MAX_LANES 4 + +static u32 serdes1_prtcl_map, serdes2_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE}, + [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE}, + [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}, + [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}, + [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}, + [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}, +}; + +static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x1] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3}, + [0x3] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3}, + [0x5] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3}, + [0x6] = {PCIE3, NONE, NONE, NONE}, + [0x7] = {PCIE3, NONE, SGMII_TSEC1, SGMII_TSEC3}, +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = (1 << device) & serdes1_prtcl_map; + + if (ret) + return ret; + + return (1 << device) & serdes2_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + + if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; + serdes2_prtcl_map |= (1 << lane_prtcl); + } + + if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS) + serdes2_prtcl_map &= ~(1 << SGMII_TSEC1); + + if (pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS) + serdes2_prtcl_map &= ~(1 << SGMII_TSEC3); +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c new file mode 100644 index 000000000..d14695506 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c @@ -0,0 +1,49 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 8 + +static u32 serdes1_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x5] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}, +}; + +int is_serdes_configured(enum srds_prtcl prtcl) +{ + return (1 << prtcl) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg); + + if (srds1_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg); + return ; + } + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c new file mode 100644 index 000000000..9199f01b9 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c @@ -0,0 +1,49 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 8 + +static u32 serdes1_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x5] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}, +}; + +int is_serdes_configured(enum srds_prtcl prtcl) +{ + return (1 << prtcl) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c new file mode 100644 index 000000000..6c80b5e4b --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c @@ -0,0 +1,58 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 + +static u32 serdes1_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x0] = {PCIE1, NONE, NONE, NONE}, + [0x1] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2}, + [0x2] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2}, + [0x3] = {SRIO1, SRIO2, NONE, NONE}, + [0x4] = {PCIE1, NONE, SGMII_TSEC1, SGMII_TSEC2}, + [0x5] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, + [0x6] = {PCIE1, NONE, SRIO1, SRIO2}, + [0x7] = {PCIE1, PCIE1, SRIO1, SRIO2}, + [0x8] = {PCIE1, PCIE1, SRIO1, SRIO2}, + [0x9] = {SRIO1, SRIO1, SRIO1, SRIO1}, + [0xa] = {SRIO1, SRIO1, SRIO1, SRIO1}, + [0xb] = {SRIO1, SRIO1, SRIO1, SRIO1}, + [0xc] = {PCIE1, SRIO1, SGMII_TSEC1, SGMII_TSEC2}, + [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1}, +}; + +int is_serdes_configured(enum srds_prtcl prtcl) +{ + return (1 << prtcl) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c new file mode 100644 index 000000000..3632eb557 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c @@ -0,0 +1,65 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 8 + +static u32 serdes1_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE}, + [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}, + [0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3}, + [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}, + [0xc] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}, + [0xd] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, + [0xe] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, + [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}, +}; + +int is_serdes_configured(enum srds_prtcl prtcl) +{ + return (1 << prtcl) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) + serdes1_prtcl_map |= (1 << SGMII_TSEC1); + + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + serdes1_prtcl_map |= (1 << SGMII_TSEC2); + + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + serdes1_prtcl_map |= (1 << SGMII_TSEC3); + + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) + serdes1_prtcl_map |= (1 << SGMII_TSEC4); +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p1010_serdes.c new file mode 100644 index 000000000..4b965f7a0 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p1010_serdes.c @@ -0,0 +1,72 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Author: Prabhakar Kushwaha <prabhakar@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 +#define SRDS2_MAX_LANES 2 + +static u32 serdes1_prtcl_map, serdes2_prtcl_map; + +static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x00] = {NONE, NONE, NONE, NONE}, + [0x01] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3}, + [0x02] = {PCIE1, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3}, + [0x03] = {NONE, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3}, +}; + +static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x00] = {NONE, NONE}, + [0x01] = {SATA1, SATA2}, + [0x02] = {SATA1, SATA2}, + [0x03] = {PCIE1, PCIE2}, +}; + + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = (1 << device) & serdes1_prtcl_map; + + if (ret) + return ret; + + return (1 << device) & serdes2_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + + if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; + serdes2_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p1021_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p1021_serdes.c new file mode 100644 index 000000000..99a77bd2b --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p1021_serdes.c @@ -0,0 +1,95 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +typedef struct serdes_85xx { + u32 srdscr0; /* 0x00 - SRDS Control Register 0 */ + u32 srdscr1; /* 0x04 - SRDS Control Register 1 */ + u32 srdscr2; /* 0x08 - SRDS Control Register 2 */ + u32 srdscr3; /* 0x0C - SRDS Control Register 3 */ + u32 srdscr4; /* 0x10 - SRDS Control Register 4 */ +} serdes_85xx_t; +#define FSL_SRDSCR3_EIC0(x) (((x) & 0x1f) << 8) +#define FSL_SRDSCR3_EIC0_MASK FSL_SRDSCR3_EIC0(0x1f) +#define FSL_SRDSCR3_EIC1(x) (((x) & 0x1f) << 0) +#define FSL_SRDSCR3_EIC1_MASK FSL_SRDSCR3_EIC1(0x1f) +#define FSL_SRDSCR4_EIC2(x) (((x) & 0x1f) << 8) +#define FSL_SRDSCR4_EIC2_MASK FSL_SRDSCR4_EIC2(0x1f) +#define FSL_SRDSCR4_EIC3(x) (((x) & 0x1f) << 0) +#define FSL_SRDSCR4_EIC3_MASK FSL_SRDSCR4_EIC3(0x1f) +#define EIC_PCIE 0x13 +#define EIC_SGMII 0x04 + +#define SRDS1_MAX_LANES 4 + +static u32 serdes1_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x0] = {PCIE1, NONE, NONE, NONE}, + [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0xe] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3}, + [0xf] = {PCIE1, PCIE1, SGMII_TSEC2, SGMII_TSEC3}, +}; + +int is_serdes_configured(enum srds_prtcl prtcl) +{ + return (1 << prtcl) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + serdes_85xx_t *serdes = (void *)CONFIG_SYS_MPC85xx_SERDES1_ADDR; + + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + u32 mask, val; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + + /* Init SERDES Receiver electrical idle detection control for PCIe */ + + /* Lane 0 is always PCIe 1 */ + mask = FSL_SRDSCR3_EIC0_MASK; + val = FSL_SRDSCR3_EIC0(EIC_PCIE); + + /* Lane 1 */ + if ((serdes1_cfg_tbl[srds_cfg][1] == PCIE1) || + (serdes1_cfg_tbl[srds_cfg][1] == PCIE2)) { + mask |= FSL_SRDSCR3_EIC1_MASK; + val |= FSL_SRDSCR3_EIC1(EIC_PCIE); + } + + /* Handle lanes 0 & 1 */ + clrsetbits_be32(&serdes->srdscr3, mask, val); + + /* Handle lanes 2 & 3 */ + if (srds_cfg == 0x6) { + mask = FSL_SRDSCR4_EIC2_MASK | FSL_SRDSCR4_EIC3_MASK; + val = FSL_SRDSCR4_EIC2(EIC_PCIE) | FSL_SRDSCR4_EIC3(EIC_PCIE); + clrsetbits_be32(&serdes->srdscr4, mask, val); + } + + /* 100 ms delay */ + udelay(100000); +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p1022_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p1022_serdes.c new file mode 100644 index 000000000..14d17eb51 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p1022_serdes.c @@ -0,0 +1,111 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Author: Timur Tabi <timur@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 +#define SRDS2_MAX_LANES 2 + +static u32 serdes1_prtcl_map, serdes2_prtcl_map; + +static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x00] = {NONE, NONE, NONE, NONE}, + [0x01] = {NONE, NONE, NONE, NONE}, + [0x02] = {NONE, NONE, NONE, NONE}, + [0x03] = {NONE, NONE, NONE, NONE}, + [0x04] = {NONE, NONE, NONE, NONE}, + [0x06] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2}, + [0x07] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2}, + [0x09] = {PCIE1, NONE, NONE, NONE}, + [0x0a] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2}, + [0x0b] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2}, + [0x0d] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, + [0x0e] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, + [0x0f] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, + [0x15] = {PCIE1, PCIE3, PCIE2, PCIE2}, + [0x16] = {PCIE1, PCIE3, PCIE2, PCIE2}, + [0x17] = {PCIE1, PCIE3, PCIE2, PCIE2}, + [0x18] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x19] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1a] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1b] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1c] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x1d] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1e] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1f] = {PCIE1, PCIE1, PCIE2, PCIE2}, +}; + +static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x00] = {PCIE3, PCIE3}, + [0x01] = {PCIE2, PCIE3}, + [0x02] = {SATA1, SATA2}, + [0x03] = {SGMII_TSEC1, SGMII_TSEC2}, + [0x04] = {NONE, NONE}, + [0x06] = {SATA1, SATA2}, + [0x07] = {NONE, NONE}, + [0x09] = {PCIE3, PCIE2}, + [0x0a] = {SATA1, SATA2}, + [0x0b] = {NONE, NONE}, + [0x0d] = {PCIE3, PCIE2}, + [0x0e] = {SATA1, SATA2}, + [0x0f] = {NONE, NONE}, + [0x15] = {SGMII_TSEC1, SGMII_TSEC2}, + [0x16] = {SATA1, SATA2}, + [0x17] = {NONE, NONE}, + [0x18] = {PCIE3, PCIE3}, + [0x19] = {SGMII_TSEC1, SGMII_TSEC2}, + [0x1a] = {SATA1, SATA2}, + [0x1b] = {NONE, NONE}, + [0x1c] = {PCIE3, PCIE3}, + [0x1d] = {SGMII_TSEC1, SGMII_TSEC2}, + [0x1e] = {SATA1, SATA2}, + [0x1f] = {NONE, NONE}, +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = (1 << device) & serdes1_prtcl_map; + + if (ret) + return ret; + + return (1 << device) & serdes2_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + + if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; + serdes2_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p1023_serdes.c new file mode 100644 index 000000000..e83b0a335 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p1023_serdes.c @@ -0,0 +1,50 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Author: Roy Zang <tie-fei.zang@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 + +static u32 serdes1_prtcl_map; + +static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x00] = {PCIE1, PCIE2, NONE, NONE}, + [0x01] = {PCIE1, PCIE2, PCIE3, NONE}, + [0x02] = {PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC2}, + [0x03] = {PCIE1, PCIE2, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2}, +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = (1 << device) & serdes1_prtcl_map; + return ret; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p2020_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p2020_serdes.c new file mode 100644 index 000000000..59d402c96 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p2020_serdes.c @@ -0,0 +1,57 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 + +static u32 serdes1_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x0] = {PCIE1, NONE, NONE, NONE}, + [0x2] = {PCIE1, PCIE2, PCIE3, PCIE3}, + [0x4] = {PCIE1, PCIE1, PCIE3, PCIE3}, + [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x7] = {SRIO2, SRIO1, NONE, NONE}, + [0x8] = {SRIO2, SRIO2, SRIO2, SRIO2}, + [0x9] = {SRIO2, SRIO2, SRIO2, SRIO2}, + [0xa] = {SRIO2, SRIO2, SRIO2, SRIO2}, + [0xb] = {SRIO2, SRIO1, SGMII_TSEC2, SGMII_TSEC3}, + [0xc] = {SRIO2, SRIO1, SGMII_TSEC2, SGMII_TSEC3}, + [0xd] = {PCIE1, SRIO1, SGMII_TSEC2, SGMII_TSEC3}, + [0xe] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3}, + [0xf] = {PCIE1, PCIE1, SGMII_TSEC2, SGMII_TSEC3}, +}; + +int is_serdes_configured(enum srds_prtcl prtcl) +{ + return (1 << prtcl) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p2041_ids.c new file mode 100644 index 000000000..488e07846 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -0,0 +1,113 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO(1, 2, 1, 0), + SET_QP_INFO(3, 4, 2, 1), + SET_QP_INFO(5, 6, 3, 2), + SET_QP_INFO(7, 8, 4, 3), + SET_QP_INFO(9, 10, 5, 0), + SET_QP_INFO(11, 12, 6, 1), + SET_QP_INFO(13, 14, 7, 2), + SET_QP_INFO(15, 16, 8, 3), + SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */ + SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */ +}; +#endif + +struct srio_liodn_id_table srio_liodn_tbl[] = { + SET_SRIO_LIODN_2(1, 199, 200), + SET_SRIO_LIODN_2(2, 201, 202), +}; +int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); + +struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(31), + SET_BMAN_LIODN(32), +#endif + + SET_SDHC_LIODN(1, 64), + + SET_PME_LIODN(117), + + SET_USB_LIODN(1, "fsl-usb2-mph", 125), + SET_USB_LIODN(2, "fsl-usb2-dr", 126), + + SET_SATA_LIODN(1, 127), + SET_SATA_LIODN(2, 128), + + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), + + SET_DMA_LIODN(1, 197), + SET_DMA_LIODN(2, 198), + + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), + SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 10), + SET_FMAN_RX_1G_LIODN(1, 1, 11), + SET_FMAN_RX_1G_LIODN(1, 2, 12), + SET_FMAN_RX_1G_LIODN(1, 3, 13), + SET_FMAN_RX_1G_LIODN(1, 4, 14), +#if (CONFIG_SYS_NUM_FM1_10GEC == 1) + SET_FMAN_RX_10G_LIODN(1, 0, 15), +#endif +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 129, 130), + SET_SEC_JR_LIODN_ENTRY(1, 131, 132), + SET_SEC_JR_LIODN_ENTRY(2, 133, 134), + SET_SEC_JR_LIODN_ENTRY(3, 135, 136), + SET_SEC_RTIC_LIODN_ENTRY(a, 154), + SET_SEC_RTIC_LIODN_ENTRY(b, 155), + SET_SEC_RTIC_LIODN_ENTRY(c, 156), + SET_SEC_RTIC_LIODN_ENTRY(d, 157), + SET_SEC_DECO_LIODN_ENTRY(0, 97, 98), + SET_SEC_DECO_LIODN_ENTRY(1, 99, 100), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_RMAN +struct liodn_id_table rman_liodn_tbl[] = { + /* Set RMan block 0-3 liodn offset */ + SET_RMAN_LIODN(0, 6), + SET_RMAN_LIODN(1, 7), + SET_RMAN_LIODN(2, 8), + SET_RMAN_LIODN(3, 9), +}; +int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); +#endif + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), +#endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172), +#endif +#ifdef CONFIG_SYS_DPAA_RMAN + [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(80), +#endif +}; diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p2041_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p2041_serdes.c new file mode 100644 index 000000000..f278549cb --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p2041_serdes.c @@ -0,0 +1,90 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_serdes.h> +#include <asm/processor.h> +#include <asm/io.h> +#include "fsl_corenet_serdes.h" + +static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { + [0x2] = {NONE, NONE, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, }, + [0x5] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, }, + [0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, + PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1, + SATA2, NONE, NONE, NONE, NONE, }, + [0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, + PCIE2, PCIE2, PCIE2, NONE, NONE, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, NONE, NONE, NONE, NONE, }, + [0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, + PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3, + PCIE3, NONE, NONE, NONE, NONE, }, + [0xf] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, + SRIO2, SRIO1, SRIO1, NONE, NONE, PCIE3, SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, }, + [0x14] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, + PCIE2, SRIO1, SRIO1, NONE, NONE, AURORA, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, + NONE, NONE, NONE, }, + [0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, + NONE, NONE, NONE, }, + [0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, NONE, NONE, XAUI_FM1, XAUI_FM1, XAUI_FM1, + XAUI_FM1, NONE, NONE, NONE, NONE, }, + [0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, + PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, + NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, + [0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2, + SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, + NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, + [0x1c] = {NONE, NONE, PCIE1, SGMII_FM1_DTSEC2, PCIE2, PCIE2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, AURORA, + SGMII_FM1_DTSEC5, NONE, NONE, NONE, NONE, NONE, NONE, }, +}; + +enum srds_prtcl serdes_get_prtcl(int cfg, int lane) +{ + enum srds_prtcl prtcl; + u32 svr = get_svr(); + u32 ver = SVR_SOC_VER(svr); + + if (!serdes_lane_enabled(lane)) + return NONE; + + prtcl = serdes_cfg_tbl[cfg][lane]; + + /* P2040[e] does not support XAUI */ + if (ver == SVR_P2040 && prtcl == XAUI_FM1) + prtcl = NONE; + + return prtcl; +} + +int is_serdes_prtcl_valid(u32 prtcl) +{ + int i; + u32 svr = get_svr(); + u32 ver = SVR_SOC_VER(svr); + + if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + /* P2040[e] does not support XAUI */ + if (ver == SVR_P2040 && prtcl == XAUI_FM1) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_cfg_tbl[prtcl][i] != NONE) + return 1; + } + + return 0; +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p3041_ids.c new file mode 100644 index 000000000..7d98870e3 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -0,0 +1,112 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO(1, 2, 1, 0), + SET_QP_INFO(3, 4, 2, 1), + SET_QP_INFO(5, 6, 3, 2), + SET_QP_INFO(7, 8, 4, 3), + SET_QP_INFO(9, 10, 5, 0), + SET_QP_INFO(1, 12, 6, 1), + SET_QP_INFO(13, 14, 7, 2), + SET_QP_INFO(15, 16, 8, 3), + SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */ + SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */ +}; +#endif + +struct srio_liodn_id_table srio_liodn_tbl[] = { + SET_SRIO_LIODN_2(1, 199, 200), + SET_SRIO_LIODN_2(2, 201, 202), +}; +int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); + +struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(31), + SET_BMAN_LIODN(32), +#endif + + SET_SDHC_LIODN(1, 64), + + SET_PME_LIODN(117), + + SET_USB_LIODN(1, "fsl-usb2-mph", 125), + SET_USB_LIODN(2, "fsl-usb2-dr", 126), + + SET_SATA_LIODN(1, 127), + SET_SATA_LIODN(2, 128), + + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196), + + SET_DMA_LIODN(1, 197), + SET_DMA_LIODN(2, 198), + + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), + SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 10), + SET_FMAN_RX_1G_LIODN(1, 1, 11), + SET_FMAN_RX_1G_LIODN(1, 2, 12), + SET_FMAN_RX_1G_LIODN(1, 3, 13), + SET_FMAN_RX_1G_LIODN(1, 4, 14), + SET_FMAN_RX_10G_LIODN(1, 0, 15), +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 129, 130), + SET_SEC_JR_LIODN_ENTRY(1, 131, 132), + SET_SEC_JR_LIODN_ENTRY(2, 133, 134), + SET_SEC_JR_LIODN_ENTRY(3, 135, 136), + SET_SEC_RTIC_LIODN_ENTRY(a, 154), + SET_SEC_RTIC_LIODN_ENTRY(b, 155), + SET_SEC_RTIC_LIODN_ENTRY(c, 156), + SET_SEC_RTIC_LIODN_ENTRY(d, 157), + SET_SEC_DECO_LIODN_ENTRY(0, 97, 98), + SET_SEC_DECO_LIODN_ENTRY(1, 99, 100), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_RMAN +struct liodn_id_table rman_liodn_tbl[] = { + /* Set RMan block 0-3 liodn offset */ + SET_RMAN_LIODN(0, 6), + SET_RMAN_LIODN(1, 7), + SET_RMAN_LIODN(2, 8), + SET_RMAN_LIODN(3, 9), +}; +int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); +#endif + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), +#endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172), +#endif +#ifdef CONFIG_SYS_DPAA_RMAN + [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(80), +#endif +}; diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p3041_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p3041_serdes.c new file mode 100644 index 000000000..c88c78c4e --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p3041_serdes.c @@ -0,0 +1,135 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_serdes.h> +#include <asm/processor.h> +#include <asm/io.h> +#include "fsl_corenet_serdes.h" + +static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { + [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + PCIE4, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x4] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, }, + [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, + PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x10] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x13] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, }, + [0x14] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, }, + [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x16] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SRIO1, SRIO1, SRIO1, + SRIO1, }, + [0x17] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x18] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x1b] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x1d] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, + SATA1, SATA2, }, + [0x20] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, }, + [0x21] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, }, + [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x23] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x24] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x28] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x29] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, }, + [0x2b] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x2f] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO2, SRIO2, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x31] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x33] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, + AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, + NONE, SATA1, SATA2, }, + [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, + XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, }, + [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, + AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, + NONE, SATA1, SATA2, }, + [0x37] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, + XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, }, +}; + +enum srds_prtcl serdes_get_prtcl(int cfg, int lane) +{ + if (!serdes_lane_enabled(lane)) + return NONE; + + return serdes_cfg_tbl[cfg][lane]; +} + +int is_serdes_prtcl_valid(u32 prtcl) { + int i; + + if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_cfg_tbl[prtcl][i] != NONE) + return 1; + } + + return 0; +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p4080_ids.c new file mode 100644 index 000000000..b2a23c0c9 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -0,0 +1,112 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO( 1, 2, 1, 0), + SET_QP_INFO( 3, 4, 2, 1), + SET_QP_INFO( 5, 6, 3, 2), + SET_QP_INFO( 7, 8, 4, 3), + SET_QP_INFO( 9, 10, 5, 4), + SET_QP_INFO(11, 12, 6, 5), + SET_QP_INFO(13, 14, 7, 6), + SET_QP_INFO(15, 16, 8, 7), + SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */ + SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */ +}; +#endif + +struct srio_liodn_id_table srio_liodn_tbl[] = { + SET_SRIO_LIODN_1(1, 198), + SET_SRIO_LIODN_1(2, 199), +}; +int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); + +struct liodn_id_table liodn_tbl[] = { + SET_USB_LIODN(1, "fsl-usb2-mph", 127), + SET_USB_LIODN(2, "fsl-usb2-dr", 157), + + SET_SDHC_LIODN(1, 156), + + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), + + SET_DMA_LIODN(1, 196), + SET_DMA_LIODN(2, 197), + + SET_GUTS_LIODN("fsl,srio-rmu", 200, rmuliodnr, 0xd3000), + +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(31), + SET_BMAN_LIODN(32), +#endif + SET_PME_LIODN(128), +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 11), + SET_FMAN_RX_1G_LIODN(1, 1, 12), + SET_FMAN_RX_1G_LIODN(1, 2, 13), + SET_FMAN_RX_1G_LIODN(1, 3, 14), + SET_FMAN_RX_10G_LIODN(1, 0, 15), +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); + +#if (CONFIG_SYS_NUM_FMAN == 2) +struct liodn_id_table fman2_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(2, 0, 16), + SET_FMAN_RX_1G_LIODN(2, 1, 17), + SET_FMAN_RX_1G_LIODN(2, 2, 18), + SET_FMAN_RX_1G_LIODN(2, 3, 19), + SET_FMAN_RX_10G_LIODN(2, 0, 20), +}; +int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl); +#endif +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + /* + * We assume currently that all JR are in the same partition + * and as such they need to represent the same LIODN due to + * a 4080 rev.2 h/w requirement that DECOs sharing from themselves + * or from another DECO have the two Non-SEQ LIODN values equal + */ + SET_SEC_JR_LIODN_ENTRY(0, 146, 154), /* (0, 146, 154), */ + SET_SEC_JR_LIODN_ENTRY(1, 146, 154), /* (1, 147, 155), */ + SET_SEC_JR_LIODN_ENTRY(2, 146, 154), /* (2, 178, 186), */ + SET_SEC_JR_LIODN_ENTRY(3, 146, 154), /* (3, 179, 187), */ + SET_SEC_RTIC_LIODN_ENTRY(a, 144), + SET_SEC_RTIC_LIODN_ENTRY(b, 145), + SET_SEC_RTIC_LIODN_ENTRY(c, 176), + SET_SEC_RTIC_LIODN_ENTRY(d, 177), + SET_SEC_DECO_LIODN_ENTRY(0, 129, 161), + SET_SEC_DECO_LIODN_ENTRY(1, 130, 162), + SET_SEC_DECO_LIODN_ENTRY(2, 131, 163), + SET_SEC_DECO_LIODN_ENTRY(3, 132, 164), + SET_SEC_DECO_LIODN_ENTRY(4, 133, 165), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(96, 106), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), +#if (CONFIG_SYS_NUM_FMAN == 2) + [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(64), +#endif +#endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(116, 133), +#endif +}; diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p4080_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p4080_serdes.c new file mode 100644 index 000000000..e719d322e --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p4080_serdes.c @@ -0,0 +1,82 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/fsl_serdes.h> +#include <asm/processor.h> +#include <asm/io.h> +#include "fsl_corenet_serdes.h" + +static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { + [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, + AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, + [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, + [0x8] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, + [0xd] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC3, + SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, + [0xe] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, SGMII_FM2_DTSEC3, + SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, + [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, + XAUI_FM2, XAUI_FM2, XAUI_FM2, NONE, NONE, NONE, NONE}, + [0x10] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM2_DTSEC1, + SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, + AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, + NONE, NONE, NONE, NONE}, + [0x13] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, + [0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}, + [0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}, + [0x1d] = {PCIE1, PCIE1, PCIE3, PCIE3, NONE, SRIO2, NONE, SRIO1, + AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, + [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, + [0x25] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1}, +}; + +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 +uint16_t srds_lpd_b[SRDS_MAX_BANK]; +#endif + +enum srds_prtcl serdes_get_prtcl(int cfg, int lane) +{ + if (!serdes_lane_enabled(lane)) + return NONE; + + return serdes_cfg_tbl[cfg][lane]; +} + +int is_serdes_prtcl_valid(u32 prtcl) { + int i; + + if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_cfg_tbl[prtcl][i] != NONE) + return 1; + } + + return 0; +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p5020_ids.c new file mode 100644 index 000000000..b5d787c8e --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -0,0 +1,125 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO(1, 2, 1, 0), + SET_QP_INFO(3, 4, 2, 1), + SET_QP_INFO(5, 6, 3, 0), + SET_QP_INFO(7, 8, 4, 1), + SET_QP_INFO(9, 10, 5, 0), + SET_QP_INFO(11, 12, 6, 1), + SET_QP_INFO(13, 14, 7, 0), + SET_QP_INFO(15, 16, 8, 1), + SET_QP_INFO(17, 18, 9, 0), + SET_QP_INFO(19, 20, 10, 1), +}; +#endif + +struct srio_liodn_id_table srio_liodn_tbl[] = { + SET_SRIO_LIODN_2(1, 199, 200), + SET_SRIO_LIODN_2(2, 201, 202), +}; +int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); + +struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(31), + SET_BMAN_LIODN(32), +#endif + + SET_SDHC_LIODN(1, 64), + + SET_PME_LIODN(117), + + SET_USB_LIODN(1, "fsl-usb2-mph", 125), + SET_USB_LIODN(2, "fsl-usb2-dr", 126), + + SET_SATA_LIODN(1, 127), + SET_SATA_LIODN(2, 128), + + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196), + + SET_DMA_LIODN(1, 197), + SET_DMA_LIODN(2, 198), + + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), + SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 10), + SET_FMAN_RX_1G_LIODN(1, 1, 11), + SET_FMAN_RX_1G_LIODN(1, 2, 12), + SET_FMAN_RX_1G_LIODN(1, 3, 13), + SET_FMAN_RX_1G_LIODN(1, 4, 14), + SET_FMAN_RX_10G_LIODN(1, 0, 15), +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 129, 130), + SET_SEC_JR_LIODN_ENTRY(1, 131, 132), + SET_SEC_JR_LIODN_ENTRY(2, 133, 134), + SET_SEC_JR_LIODN_ENTRY(3, 135, 136), + SET_SEC_RTIC_LIODN_ENTRY(a, 154), + SET_SEC_RTIC_LIODN_ENTRY(b, 155), + SET_SEC_RTIC_LIODN_ENTRY(c, 156), + SET_SEC_RTIC_LIODN_ENTRY(d, 157), + SET_SEC_DECO_LIODN_ENTRY(0, 97, 98), + SET_SEC_DECO_LIODN_ENTRY(1, 99, 100), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +#ifdef CONFIG_SYS_FSL_RAID_ENGINE +struct liodn_id_table raide_liodn_tbl[] = { + SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 0, 60), + SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 1, 61), + SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 0, 62), + SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 1, 63), +}; +int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl); +#endif + +#ifdef CONFIG_SYS_DPAA_RMAN +struct liodn_id_table rman_liodn_tbl[] = { + /* Set RMan block 0-3 liodn offset */ + SET_RMAN_LIODN(0, 6), + SET_RMAN_LIODN(1, 7), + SET_RMAN_LIODN(2, 8), + SET_RMAN_LIODN(3, 9), +}; +int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); +#endif + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), +#endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172), +#endif +#ifdef CONFIG_SYS_FSL_RAID_ENGINE + [FSL_HW_PORTAL_RAID_ENGINE] = SET_LIODN_BASE_1(47), +#endif +#ifdef CONFIG_SYS_DPAA_RMAN + [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(80), +#endif +}; diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p5020_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p5020_serdes.c new file mode 100644 index 000000000..c88c78c4e --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p5020_serdes.c @@ -0,0 +1,135 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_serdes.h> +#include <asm/processor.h> +#include <asm/io.h> +#include "fsl_corenet_serdes.h" + +static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { + [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + PCIE4, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x4] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, }, + [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, + PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x10] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x13] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, }, + [0x14] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, }, + [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x16] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SRIO1, SRIO1, SRIO1, + SRIO1, }, + [0x17] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x18] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x1b] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x1d] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, + SATA1, SATA2, }, + [0x20] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, }, + [0x21] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, }, + [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x23] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x24] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x28] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, }, + [0x29] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, }, + [0x2b] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x2f] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO2, SRIO2, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x31] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE, + NONE, NONE, }, + [0x33] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, }, + [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, + AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, + NONE, SATA1, SATA2, }, + [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, + XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, }, + [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, + AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, + NONE, SATA1, SATA2, }, + [0x37] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, + XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, }, +}; + +enum srds_prtcl serdes_get_prtcl(int cfg, int lane) +{ + if (!serdes_lane_enabled(lane)) + return NONE; + + return serdes_cfg_tbl[cfg][lane]; +} + +int is_serdes_prtcl_valid(u32 prtcl) { + int i; + + if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_cfg_tbl[prtcl][i] != NONE) + return 1; + } + + return 0; +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p5040_ids.c new file mode 100644 index 000000000..990f17949 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p5040_ids.c @@ -0,0 +1,111 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO(1, 2, 1, 0), + SET_QP_INFO(3, 4, 2, 1), + SET_QP_INFO(5, 6, 3, 2), + SET_QP_INFO(7, 8, 4, 3), + SET_QP_INFO(9, 10, 5, 0), + SET_QP_INFO(11, 12, 6, 1), + SET_QP_INFO(13, 14, 7, 2), + SET_QP_INFO(15, 16, 8, 3), + SET_QP_INFO(17, 18, 9, 0), /* for now, set sdest to 0 */ + SET_QP_INFO(19, 20, 10, 0), /* for now, set sdest to 0 */ +}; +#endif + +struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(31), + SET_BMAN_LIODN(32), +#endif + + SET_SDHC_LIODN(1, 64), + + SET_USB_LIODN(1, "fsl-usb2-mph", 93), + SET_USB_LIODN(2, "fsl-usb2-dr", 94), + + SET_SATA_LIODN(1, 95), + SET_SATA_LIODN(2, 96), + + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 195), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 196), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 197), + + SET_DMA_LIODN(1, 193), + SET_DMA_LIODN(2, 194), +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 6), + SET_FMAN_RX_1G_LIODN(1, 1, 7), + SET_FMAN_RX_1G_LIODN(1, 2, 8), + SET_FMAN_RX_1G_LIODN(1, 3, 9), + SET_FMAN_RX_1G_LIODN(1, 4, 10), + SET_FMAN_RX_10G_LIODN(1, 0, 11), +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); + +#if (CONFIG_SYS_NUM_FMAN == 2) +struct liodn_id_table fman2_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(2, 0, 12), + SET_FMAN_RX_1G_LIODN(2, 1, 13), + SET_FMAN_RX_1G_LIODN(2, 2, 14), + SET_FMAN_RX_1G_LIODN(2, 3, 15), + SET_FMAN_RX_1G_LIODN(2, 4, 16), + SET_FMAN_RX_10G_LIODN(2, 0, 17), +}; +int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl); +#endif +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 129, 130), + SET_SEC_JR_LIODN_ENTRY(1, 131, 132), + SET_SEC_JR_LIODN_ENTRY(2, 133, 134), + SET_SEC_JR_LIODN_ENTRY(3, 135, 136), + SET_SEC_RTIC_LIODN_ENTRY(a, 89), + SET_SEC_RTIC_LIODN_ENTRY(b, 90), + SET_SEC_RTIC_LIODN_ENTRY(c, 91), + SET_SEC_RTIC_LIODN_ENTRY(d, 92), + SET_SEC_DECO_LIODN_ENTRY(0, 139, 140), + SET_SEC_DECO_LIODN_ENTRY(1, 141, 142), + SET_SEC_DECO_LIODN_ENTRY(2, 143, 144), + SET_SEC_DECO_LIODN_ENTRY(3, 145, 146), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +#ifdef CONFIG_SYS_FSL_RAID_ENGINE +struct liodn_id_table raide_liodn_tbl[] = { + SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 0, 60), + SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 1, 61), + SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 0, 62), + SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 1, 63), +}; +int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl); +#endif + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 101), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), +#endif +#if (CONFIG_SYS_NUM_FMAN == 2) + [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(160), +#endif +#ifdef CONFIG_SYS_FSL_RAID_ENGINE + [FSL_HW_PORTAL_RAID_ENGINE] = SET_LIODN_BASE_1(49), +#endif +}; diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p5040_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p5040_serdes.c new file mode 100644 index 000000000..2655974a4 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/p5040_serdes.c @@ -0,0 +1,101 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_serdes.h> +#include <asm/processor.h> +#include <asm/io.h> +#include "fsl_corenet_serdes.h" + +/* + * Note: For P5040, the fourth SerDes bank (with two lanes) is on SerDes2, but + * U-boot only supports one SerDes controller. Therefore, we ignore bank 4 in + * this table. This works because most of the SerDes code is for errata + * work-arounds, and there are no P5040 errata that effect bank 4. + */ + +static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { + [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2, */ }, + [0x01] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM2, /* SATA1, SATA2 */ }, + [0x02] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, + XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, + XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ }, + [0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC1, + SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, + /* SATA1, SATA2 */ }, + [0x04] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM2_DTSEC1, + SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, + /* SATA1, SATA2 */ }, + [0x05] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, + XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, + XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ }, + [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ }, + [0x07] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, + SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2, + XAUI_FM2, /* SATA1, SATA2 */ }, + [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, + /* NONE, NONE */ }, + [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, + NONE, NONE, SATA1, SATA2, /* NONE, NONE */ }, + [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2, + AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, + XAUI_FM2, XAUI_FM2, /* NONE, NONE */ }, + [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, + AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, + NONE, SATA1, SATA2, /* NONE, NONE */ }, + [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1, + XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, + /* NONE, NONE */ }, + [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, + AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, + NONE, SATA1, SATA2, /* NONE, NONE */ }, +}; + +enum srds_prtcl serdes_get_prtcl(int cfg, int lane) +{ + if (!serdes_lane_enabled(lane)) + return NONE; + + return serdes_cfg_tbl[cfg][lane]; +} + +int is_serdes_prtcl_valid(u32 prtcl) +{ + int i; + + if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_cfg_tbl[prtcl][i] != NONE) + return 1; + } + + return 0; +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/pci.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/pci.c new file mode 100644 index 000000000..c6d2fda5d --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/pci.c @@ -0,0 +1,214 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright (C) 2003 Motorola Inc. + * Xianghua Xiao (x.xiao@motorola.com) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * PCI Configuration space access support for MPC85xx PCI Bridge + */ +#include <common.h> +#include <asm/cpm_85xx.h> +#include <pci.h> + +#if !defined(CONFIG_FSL_PCI_INIT) + +#ifndef CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE +#endif + +#ifndef CONFIG_SYS_PCI1_IO_BUS +#define CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_BASE +#endif + +#ifndef CONFIG_SYS_PCI2_MEM_BUS +#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI2_MEM_BASE +#endif + +#ifndef CONFIG_SYS_PCI2_IO_BUS +#define CONFIG_SYS_PCI2_IO_BUS CONFIG_SYS_PCI2_IO_BASE +#endif + +static struct pci_controller *pci_hose; + +void +pci_mpc85xx_init(struct pci_controller *board_hose) +{ + u16 reg16; + u32 dev; + + volatile ccsr_pcix_t *pcix = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR); +#ifdef CONFIG_MPC85XX_PCI2 + volatile ccsr_pcix_t *pcix2 = (void *)(CONFIG_SYS_MPC85xx_PCIX2_ADDR); +#endif + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + struct pci_controller * hose; + + pci_hose = board_hose; + + hose = &pci_hose[0]; + + hose->first_busno = 0; + hose->last_busno = 0xff; + + pci_setup_indirect(hose, + (CONFIG_SYS_IMMR+0x8000), + (CONFIG_SYS_IMMR+0x8004)); + + /* + * Hose scan. + */ + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + + if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { + /* PCI-X init */ + if (CONFIG_SYS_CLK_FREQ < 66000000) + printf("PCI-X will only work at 66 MHz\n"); + + reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ + | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; + pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16); + } + + pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BUS >> 12) & 0x000fffff; + pcix->potear1 = 0x00000000; + pcix->powbar1 = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff; + pcix->powbear1 = 0x00000000; + pcix->powar1 = (POWAR_EN | POWAR_MEM_READ | + POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1)); + + pcix->potar2 = (CONFIG_SYS_PCI1_IO_BUS >> 12) & 0x000fffff; + pcix->potear2 = 0x00000000; + pcix->powbar2 = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff; + pcix->powbear2 = 0x00000000; + pcix->powar2 = (POWAR_EN | POWAR_IO_READ | + POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI1_IO_SIZE) - 1)); + + pcix->pitar1 = 0x00000000; + pcix->piwbar1 = 0x00000000; + pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL | + PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G); + + pcix->powar3 = 0; + pcix->powar4 = 0; + pcix->piwar2 = 0; + pcix->piwar3 = 0; + + pci_set_region(hose->regions + 0, + CONFIG_SYS_PCI1_MEM_BUS, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + pci_set_region(hose->regions + 1, + CONFIG_SYS_PCI1_IO_BUS, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 2; + + pci_register_hose(hose); + +#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS) + /* + * This is a SW workaround for an apparent HW problem + * in the PCI controller on the MPC85555/41 CDS boards. + * The first config cycle must be to a valid, known + * device on the PCI bus in order to trick the PCI + * controller state machine into a known valid state. + * Without this, the first config cycle has the chance + * of hanging the controller permanently, just leaving + * it in a semi-working state, or leaving it working. + * + * Pick on the Tundra, Device 17, to get it right. + */ + { + u8 header_type; + + pci_hose_read_config_byte(hose, + PCI_BDF(0,BRIDGE_ID,0), + PCI_HEADER_TYPE, + &header_type); + } +#endif + + hose->last_busno = pci_hose_scan(hose); + +#ifdef CONFIG_MPC85XX_PCI2 + hose = &pci_hose[1]; + + hose->first_busno = pci_hose[0].last_busno + 1; + hose->last_busno = 0xff; + + pci_setup_indirect(hose, + (CONFIG_SYS_IMMR+0x9000), + (CONFIG_SYS_IMMR+0x9004)); + + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + + pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BUS >> 12) & 0x000fffff; + pcix2->potear1 = 0x00000000; + pcix2->powbar1 = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff; + pcix2->powbear1 = 0x00000000; + pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ | + POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1)); + + pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BUS >> 12) & 0x000fffff; + pcix2->potear2 = 0x00000000; + pcix2->powbar2 = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff; + pcix2->powbear2 = 0x00000000; + pcix2->powar2 = (POWAR_EN | POWAR_IO_READ | + POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI2_IO_SIZE) - 1)); + + pcix2->pitar1 = 0x00000000; + pcix2->piwbar1 = 0x00000000; + pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL | + PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G); + + pcix2->powar3 = 0; + pcix2->powar4 = 0; + pcix2->piwar2 = 0; + pcix2->piwar3 = 0; + + pci_set_region(hose->regions + 0, + CONFIG_SYS_PCI2_MEM_BUS, + CONFIG_SYS_PCI2_MEM_PHYS, + CONFIG_SYS_PCI2_MEM_SIZE, + PCI_REGION_MEM); + + pci_set_region(hose->regions + 1, + CONFIG_SYS_PCI2_IO_BUS, + CONFIG_SYS_PCI2_IO_PHYS, + CONFIG_SYS_PCI2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 2; + + /* + * Hose scan. + */ + pci_register_hose(hose); + + hose->last_busno = pci_hose_scan(hose); +#endif +} +#endif /* !CONFIG_FSL_PCI_INIT */ diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/portals.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/portals.c new file mode 100644 index 000000000..98815f8e1 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/portals.c @@ -0,0 +1,308 @@ +/* + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <libfdt.h> +#include <fdt_support.h> + +#include <asm/processor.h> +#include <asm/io.h> + +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +void setup_portals(void) +{ + ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR; +#ifdef CONFIG_FSL_CORENET + int i; + + for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) { + u8 sdest = qp_info[i].sdest; + u16 fliodn = qp_info[i].fliodn; + u16 dliodn = qp_info[i].dliodn; + u16 liodn_off = qp_info[i].liodn_offset; + + out_be32(&qman->qcsp[i].qcsp_lio_cfg, (liodn_off << 16) | + dliodn); + /* set frame liodn */ + out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn); + } +#endif + + /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */ +#ifdef CONFIG_PHYS_64BIT + out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32)); +#endif + out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS); +} + +/* Update portal containter to match LAW setup of portal in phy map */ +void fdt_portal(void *blob, const char *compat, const char *container, + u64 addr, u32 size) +{ + int off; + + off = fdt_node_offset_by_compatible(blob, -1, compat); + if (off < 0) + return ; + + off = fdt_parent_offset(blob, off); + /* if non-zero assume we have a container */ + if (off > 0) { + char buf[60]; + const char *p, *name; + u32 *range; + int len; + + /* fixup ranges */ + range = fdt_getprop_w(blob, off, "ranges", &len); + if (range == NULL) { + printf("ERROR: container for %s has no ranges", compat); + return ; + } + + range[0] = 0; + if (len == 16) { + range[1] = addr >> 32; + range[2] = addr & 0xffffffff; + range[3] = size; + } else { + range[1] = addr & 0xffffffff; + range[2] = size; + } + fdt_setprop_inplace(blob, off, "ranges", range, len); + + /* fixup the name */ + name = fdt_get_name(blob, off, &len); + p = memchr(name, '@', len); + + if (p) + len = p - name; + + /* if we are given a container name check it + * against what we found, if it doesnt match exit out */ + if (container && (memcmp(container, name, len))) { + printf("WARNING: container names didn't match %s %s\n", + container, name); + return ; + } + + memcpy(&buf, name, len); + len += sprintf(&buf[len], "@%llx", addr); + fdt_set_name(blob, off, buf); + return ; + } + + printf("ERROR: %s isn't in a container. Not supported\n", compat); +} + +static int fdt_qportal(void *blob, int off, int id, char *name, + enum fsl_dpaa_dev dev, int create) +{ + int childoff, dev_off, ret = 0; + uint32_t dev_handle; +#ifdef CONFIG_FSL_CORENET + int num; + u32 liodns[2]; +#endif + + childoff = fdt_subnode_offset(blob, off, name); + if (create) { + char handle[64], *p; + + strncpy(handle, name, sizeof(handle)); + p = strchr(handle, '@'); + if (!strncmp(name, "fman", 4)) { + *p = *(p + 1); + p++; + } + *p = '\0'; + + dev_off = fdt_path_offset(blob, handle); + /* skip this node if alias is not found */ + if (dev_off == -FDT_ERR_BADPATH) + return 0; + if (dev_off < 0) + return dev_off; + + if (childoff <= 0) + childoff = fdt_add_subnode(blob, off, name); + + /* need to update the dev_off after adding a subnode */ + dev_off = fdt_path_offset(blob, handle); + if (dev_off < 0) + return dev_off; + + if (childoff > 0) { + dev_handle = fdt_get_phandle(blob, dev_off); + if (dev_handle <= 0) { + dev_handle = fdt_alloc_phandle(blob); + ret = fdt_set_phandle(blob, dev_off, + dev_handle); + if (ret < 0) + return ret; + } + + ret = fdt_setprop(blob, childoff, "dev-handle", + &dev_handle, sizeof(dev_handle)); + if (ret < 0) + return ret; + +#ifdef CONFIG_FSL_CORENET + num = get_dpaa_liodn(dev, &liodns[0], id); + ret = fdt_setprop(blob, childoff, "fsl,liodn", + &liodns[0], sizeof(u32) * num); + if (!strncmp(name, "pme", 3)) { + u32 pme_rev1, pme_rev2; + ccsr_pme_t *pme_regs = + (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR; + + pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1); + pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2); + ret = fdt_setprop(blob, childoff, + "fsl,pme-rev1", &pme_rev1, sizeof(u32)); + if (ret < 0) + return ret; + ret = fdt_setprop(blob, childoff, + "fsl,pme-rev2", &pme_rev2, sizeof(u32)); + } +#endif + } else { + return childoff; + } + } else { + if (childoff > 0) + ret = fdt_del_node(blob, childoff); + } + + return ret; +} + +void fdt_fixup_qportals(void *blob) +{ + int off, err; + unsigned int maj, min; + unsigned int ip_cfg; + ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR; + u32 rev_1 = in_be32(&qman->ip_rev_1); + u32 rev_2 = in_be32(&qman->ip_rev_2); + char compat[64]; + int compat_len; + + maj = (rev_1 >> 8) & 0xff; + min = rev_1 & 0xff; + ip_cfg = rev_2 & 0xff; + + compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u", + maj, min, ip_cfg) + 1; + compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1; + + off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal"); + while (off != -FDT_ERR_NOTFOUND) { +#ifdef CONFIG_FSL_CORENET + u32 liodns[2]; +#endif + const int *ci = fdt_getprop(blob, off, "cell-index", NULL); + int i = *ci; +#ifdef CONFIG_SYS_DPAA_FMAN + int j; +#endif + + err = fdt_setprop(blob, off, "compatible", compat, compat_len); + if (err < 0) + goto err; + +#ifdef CONFIG_FSL_CORENET + liodns[0] = qp_info[i].dliodn; + liodns[1] = qp_info[i].fliodn; + + err = fdt_setprop(blob, off, "fsl,liodn", + &liodns, sizeof(u32) * 2); + if (err < 0) + goto err; +#endif + + i++; + + err = fdt_qportal(blob, off, i, "crypto@0", FSL_HW_PORTAL_SEC, + IS_E_PROCESSOR(get_svr())); + if (err < 0) + goto err; + +#ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SYS_DPAA_PME + err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1); + if (err < 0) + goto err; +#else + fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0); +#endif +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN + for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) { + char name[] = "fman@0"; + + name[sizeof(name) - 2] = '0' + j; + err = fdt_qportal(blob, off, i, name, + FSL_HW_PORTAL_FMAN1 + j, 1); + if (err < 0) + goto err; + } +#endif +#ifdef CONFIG_SYS_DPAA_RMAN + err = fdt_qportal(blob, off, i, "rman@0", + FSL_HW_PORTAL_RMAN, 1); + if (err < 0) + goto err; +#endif + +err: + if (err < 0) { + printf("ERROR: unable to create props for %s: %s\n", + fdt_get_name(blob, off, NULL), fdt_strerror(err)); + return; + } + + off = fdt_node_offset_by_compatible(blob, off, "fsl,qman-portal"); + } +} + +void fdt_fixup_bportals(void *blob) +{ + int off, err; + unsigned int maj, min; + unsigned int ip_cfg; + ccsr_bman_t *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR; + u32 rev_1 = in_be32(&bman->ip_rev_1); + u32 rev_2 = in_be32(&bman->ip_rev_2); + char compat[64]; + int compat_len; + + maj = (rev_1 >> 8) & 0xff; + min = rev_1 & 0xff; + + ip_cfg = rev_2 & 0xff; + + compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u", + maj, min, ip_cfg) + 1; + compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1; + + off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal"); + while (off != -FDT_ERR_NOTFOUND) { + err = fdt_setprop(blob, off, "compatible", compat, compat_len); + if (err < 0) { + printf("ERROR: unable to create props for %s: %s\n", + fdt_get_name(blob, off, NULL), + fdt_strerror(err)); + return; + } + + off = fdt_node_offset_by_compatible(blob, off, "fsl,bman-portal"); + } + +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/qe_io.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/qe_io.c new file mode 100644 index 000000000..d2825ec36 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/qe_io.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * Dave Liu <daveliu@freescale.com> + * based on source code of Shlomi Gridish + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "common.h" +#include "asm/errno.h" +#include "asm/io.h" +#include "asm/immap_85xx.h" + +#if defined(CONFIG_QE) && !defined(CONFIG_U_QE) +#define NUM_OF_PINS 32 +void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) +{ + u32 pin_2bit_mask; + u32 pin_2bit_dir; + u32 pin_2bit_assign; + u32 pin_1bit_mask; + u32 tmp_val; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile par_io_t *par_io = (volatile par_io_t *) + &(gur->qe_par_io); + + /* Caculate pin location and 2bit mask and dir */ + pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); + pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); + + /* Setup the direction */ + tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \ + in_be32(&par_io[port].cpdir2) : + in_be32(&par_io[port].cpdir1); + + if (pin > (NUM_OF_PINS/2) -1) { + out_be32(&par_io[port].cpdir2, ~pin_2bit_mask & tmp_val); + out_be32(&par_io[port].cpdir2, pin_2bit_dir | tmp_val); + } else { + out_be32(&par_io[port].cpdir1, ~pin_2bit_mask & tmp_val); + out_be32(&par_io[port].cpdir1, pin_2bit_dir | tmp_val); + } + + /* Calculate pin location for 1bit mask */ + pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); + + /* Setup the open drain */ + tmp_val = in_be32(&par_io[port].cpodr); + if (open_drain) + out_be32(&par_io[port].cpodr, pin_1bit_mask | tmp_val); + else + out_be32(&par_io[port].cpodr, ~pin_1bit_mask & tmp_val); + + /* Setup the assignment */ + tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? + in_be32(&par_io[port].cppar2): + in_be32(&par_io[port].cppar1); + pin_2bit_assign = (u32)(assign + << (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2)); + + /* Clear and set 2 bits mask */ + if (pin > (NUM_OF_PINS/2) - 1) { + out_be32(&par_io[port].cppar2, ~pin_2bit_mask & tmp_val); + out_be32(&par_io[port].cppar2, pin_2bit_assign | tmp_val); + } else { + out_be32(&par_io[port].cppar1, ~pin_2bit_mask & tmp_val); + out_be32(&par_io[port].cppar1, pin_2bit_assign | tmp_val); + } +} + +#endif /* CONFIG_QE */ diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/release.S b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/release.S new file mode 100644 index 000000000..a2c0ad424 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/release.S @@ -0,0 +1,487 @@ +/* + * Copyright 2008-2012 Freescale Semiconductor, Inc. + * Kumar Gala <kumar.gala@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm-offsets.h> +#include <config.h> +#include <mpc85xx.h> +#include <version.h> + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> + +#include <asm/cache.h> +#include <asm/mmu.h> + +/* To boot secondary cpus, we need a place for them to start up. + * Normally, they start at 0xfffffffc, but that's usually the + * firmware, and we don't want to have to run the firmware again. + * Instead, the primary cpu will set the BPTR to point here to + * this page. We then set up the core, and head to + * start_secondary. Note that this means that the code below + * must never exceed 1023 instructions (the branch at the end + * would then be the 1024th). + */ + .globl __secondary_start_page + .align 12 +__secondary_start_page: +/* First do some preliminary setup */ + lis r3, HID0_EMCP@h /* enable machine check */ +#ifndef CONFIG_E500MC + ori r3,r3,HID0_TBEN@l /* enable Timebase */ +#endif +#ifdef CONFIG_PHYS_64BIT + ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */ +#endif + mtspr SPRN_HID0,r3 + +#ifndef CONFIG_E500MC + li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ + mfspr r0,PVR + andi. r0,r0,0xff + cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */ + blt 1f + /* Set MBDD bit also */ + ori r3, r3, HID1_MBDD@l +1: + mtspr SPRN_HID1,r3 +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 + mfspr r3,SPRN_HDBCR1 + oris r3,r3,0x0100 + mtspr SPRN_HDBCR1,r3 +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 + mfspr r3,SPRN_SVR + rlwinm r3,r3,0,0xff + li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV + cmpw r3,r4 + beq 1f + +#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 + li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 + cmpw r3,r4 + beq 1f +#endif + + /* Not a supported revision affected by erratum */ + b 2f + +1: /* Erratum says set bits 55:60 to 001001 */ + msync + isync + mfspr r3,SPRN_HDBCR0 + li r4,0x48 + rlwimi r3,r4,0,0x1f8 + mtspr SPRN_HDBCR0,r3 + isync +2: +#endif + + /* Enable branch prediction */ + lis r3,BUCSR_ENABLE@h + ori r3,r3,BUCSR_ENABLE@l + mtspr SPRN_BUCSR,r3 + + /* Ensure TB is 0 */ + li r3,0 + mttbl r3 + mttbu r3 + + /* Enable/invalidate the I-Cache */ + lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h + ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l + mtspr SPRN_L1CSR1,r2 +1: + mfspr r3,SPRN_L1CSR1 + and. r1,r3,r2 + bne 1b + + lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h + ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l + mtspr SPRN_L1CSR1,r3 + isync +2: + mfspr r3,SPRN_L1CSR1 + andi. r1,r3,L1CSR1_ICE@l + beq 2b + + /* Enable/invalidate the D-Cache */ + lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h + ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l + mtspr SPRN_L1CSR0,r2 +1: + mfspr r3,SPRN_L1CSR0 + and. r1,r3,r2 + bne 1b + + lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h + ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l + mtspr SPRN_L1CSR0,r3 + isync +2: + mfspr r3,SPRN_L1CSR0 + andi. r1,r3,L1CSR0_DCE@l + beq 2b + +#define toreset(x) (x - __secondary_start_page + 0xfffff000) + + /* get our PIR to figure out our table entry */ + lis r3,toreset(__spin_table_addr)@h + ori r3,r3,toreset(__spin_table_addr)@l + lwz r3,0(r3) + + mfspr r0,SPRN_PIR +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +/* + * PIR definition for Chassis 2 + * 0-17 Reserved (logic 0s) + * 18-19 CHIP_ID, 2'b00 - SoC 1 + * all others - reserved + * 20-24 CLUSTER_ID 5'b00000 - CCM 1 + * all others - reserved + * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1 + * 2'b01 - cluster 2 + * 2'b10 - cluster 3 + * 2'b11 - cluster 4 + * 27-28 CORE_ID 2'b00 - core 0 + * 2'b01 - core 1 + * 2'b10 - core 2 + * 2'b11 - core 3 + * 29-31 THREAD_ID 3'b000 - thread 0 + * 3'b001 - thread 1 + * + * Power-on PIR increments threads by 0x01, cores within a cluster by 0x08 + * and clusters by 0x20. + * + * We renumber PIR so that all threads in the system are consecutive. + */ + + rlwinm r8,r0,29,0x03 /* r8 = core within cluster */ + srwi r10,r0,5 /* r10 = cluster */ + + mulli r5,r10,CONFIG_SYS_FSL_CORES_PER_CLUSTER + add r5,r5,r8 /* for spin table index */ + mulli r4,r5,CONFIG_SYS_FSL_THREADS_PER_CORE /* for PIR */ +#elif defined(CONFIG_E500MC) + rlwinm r4,r0,27,27,31 + mr r5,r4 +#else + mr r4,r0 + mr r5,r4 +#endif + + /* + * r10 has the base address for the entry. + * we cannot access it yet before setting up a new TLB + */ + slwi r8,r5,6 /* spin table is padded to 64 byte */ + add r10,r3,r8 + + mtspr SPRN_PIR,r4 /* write to PIR register */ + +#ifdef CONFIG_SYS_CACHE_STASHING + /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ + slwi r8,r4,1 + addi r8,r8,32 + mtspr L1CSR2,r8 +#endif + +#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ + defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) + /* + * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 + */ + mfspr r3,SPRN_SVR + rlwinm r6,r3,24,~0x800 /* clear E bit */ + + lis r5,SVR_P4080@h + ori r5,r5,SVR_P4080@l + cmpw r6,r5 + bne 1f + + rlwinm r3,r3,0,0xf0 + li r5,0x30 + cmpw r3,r5 + bge 2f +1: +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 + lis r3,toreset(enable_cpu_a011_workaround)@ha + lwz r3,toreset(enable_cpu_a011_workaround)@l(r3) + cmpwi r3,0 + beq 2f +#endif + mfspr r3,L1CSR2 + oris r3,r3,(L1CSR2_DCWS)@h + mtspr L1CSR2,r3 +2: +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A005812 + /* + * A-005812 workaround sets bit 32 of SPR 976 for SoCs running in + * write shadow mode. This code should run after other code setting + * DCWS. + */ + mfspr r3,L1CSR2 + andis. r3,r3,(L1CSR2_DCWS)@h + beq 1f + mfspr r3, SPRN_HDBCR0 + oris r3, r3, 0x8000 + mtspr SPRN_HDBCR0, r3 +1: +#endif + +#ifdef CONFIG_BACKSIDE_L2_CACHE + /* skip L2 setup on P2040/P2040E as they have no L2 */ + mfspr r3,SPRN_SVR + rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */ + + lis r3,SVR_P2040@h + ori r3,r3,SVR_P2040@l + cmpw r6,r3 + beq 3f + + /* Enable/invalidate the L2 cache */ + msync + lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h + ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l + mtspr SPRN_L2CSR0,r2 +1: + mfspr r3,SPRN_L2CSR0 + and. r1,r3,r2 + bne 1b + +#ifdef CONFIG_SYS_CACHE_STASHING + /* set stash id to (coreID) * 2 + 32 + L2 (1) */ + addi r3,r8,1 + mtspr SPRN_L2CSR1,r3 +#endif + + lis r3,CONFIG_SYS_INIT_L2CSR0@h + ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l + mtspr SPRN_L2CSR0,r3 + isync +2: + mfspr r3,SPRN_L2CSR0 + andis. r1,r3,L2CSR0_L2E@h + beq 2b +#endif +3: + /* setup mapping for the spin table, WIMGE=0b00100 */ + lis r13,toreset(__spin_table_addr)@h + ori r13,r13,toreset(__spin_table_addr)@l + lwz r13,0(r13) + /* mask by 4K */ + rlwinm r13,r13,0,0,19 + + lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h + mtspr SPRN_MAS0,r11 + lis r11,(MAS1_VALID|MAS1_IPROT)@h + ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l + mtspr SPRN_MAS1,r11 + oris r11,r13,(MAS2_M|MAS2_G)@h + ori r11,r13,(MAS2_M|MAS2_G)@l + mtspr SPRN_MAS2,r11 + oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h + ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l + mtspr SPRN_MAS3,r11 + li r11,0 + mtspr SPRN_MAS7,r11 + tlbwe + + /* + * __bootpg_addr has the address of __second_half_boot_page + * jump there in AS=1 space with cache enabled + */ + lis r13,toreset(__bootpg_addr)@h + ori r13,r13,toreset(__bootpg_addr)@l + lwz r11,0(r13) + mtspr SPRN_SRR0,r11 + mfmsr r13 + ori r12,r13,MSR_IS|MSR_DS@l + mtspr SPRN_SRR1,r12 + rfi + + /* + * Allocate some space for the SDRAM address of the bootpg. + * This variable has to be in the boot page so that it can + * be accessed by secondary cores when they come out of reset. + */ + .align L1_CACHE_SHIFT + .globl __bootpg_addr +__bootpg_addr: + .long 0 + + .global __spin_table_addr +__spin_table_addr: + .long 0 + + /* + * This variable is set by cpu_init_r() after parsing hwconfig + * to enable workaround for erratum NMG_CPU_A011. + */ + .align L1_CACHE_SHIFT + .global enable_cpu_a011_workaround +enable_cpu_a011_workaround: + .long 1 + + /* Fill in the empty space. The actual reset vector is + * the last word of the page */ +__secondary_start_code_end: + .space 4092 - (__secondary_start_code_end - __secondary_start_page) +__secondary_reset_vector: + b __secondary_start_page + + +/* this is a separated page for the spin table and cacheable boot code */ + .align L1_CACHE_SHIFT + .global __second_half_boot_page +__second_half_boot_page: +#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE + lis r3,(spin_table_compat - __second_half_boot_page)@h + ori r3,r3,(spin_table_compat - __second_half_boot_page)@l + add r3,r3,r11 /* r11 has the address of __second_half_boot_page */ + lwz r14,0(r3) +#endif + +#define ENTRY_ADDR_UPPER 0 +#define ENTRY_ADDR_LOWER 4 +#define ENTRY_R3_UPPER 8 +#define ENTRY_R3_LOWER 12 +#define ENTRY_RESV 16 +#define ENTRY_PIR 20 +#define ENTRY_SIZE 64 + /* + * setup the entry + * r10 has the base address of the spin table. + * spin table is defined as + * struct { + * uint64_t entry_addr; + * uint64_t r3; + * uint32_t rsvd1; + * uint32_t pir; + * }; + * we pad this struct to 64 bytes so each entry is in its own cacheline + */ + li r3,0 + li r8,1 + mfspr r4,SPRN_PIR + stw r3,ENTRY_ADDR_UPPER(r10) + stw r3,ENTRY_R3_UPPER(r10) + stw r4,ENTRY_R3_LOWER(r10) + stw r3,ENTRY_RESV(r10) + stw r4,ENTRY_PIR(r10) + msync + stw r8,ENTRY_ADDR_LOWER(r10) + + /* spin waiting for addr */ +3: +/* + * To comply with ePAPR 1.1, the spin table has been moved to cache-enabled + * memory. Old OS may not work with this change. A patch is waiting to be + * accepted for Linux kernel. Other OS needs similar fix to spin table. + * For OSes with old spin table code, we can enable this temporary fix by + * setting environmental variable "spin_table_compat". For new OSes, set + * "spin_table_compat=no". After Linux is fixed, we can remove this macro + * and related code. For now, it is enabled by default. + */ +#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE + cmpwi r14,0 + beq 4f + dcbf 0, r10 + sync +4: +#endif + lwz r4,ENTRY_ADDR_LOWER(r10) + andi. r11,r4,1 + bne 3b + isync + + /* get the upper bits of the addr */ + lwz r11,ENTRY_ADDR_UPPER(r10) + + /* setup branch addr */ + mtspr SPRN_SRR0,r4 + + /* mark the entry as released */ + li r8,3 + stw r8,ENTRY_ADDR_LOWER(r10) + + /* mask by ~64M to setup our tlb we will jump to */ + rlwinm r12,r4,0,0,5 + + /* + * setup r3, r4, r5, r6, r7, r8, r9 + * r3 contains the value to put in the r3 register at secondary cpu + * entry. The high 32-bits are ignored on 32-bit chip implementations. + * 64-bit chip implementations however shall load all 64-bits + */ +#ifdef CONFIG_SYS_PPC64 + ld r3,ENTRY_R3_UPPER(r10) +#else + lwz r3,ENTRY_R3_LOWER(r10) +#endif + li r4,0 + li r5,0 + li r6,0 + lis r7,(64*1024*1024)@h + li r8,0 + li r9,0 + + /* load up the pir */ + lwz r0,ENTRY_PIR(r10) + mtspr SPRN_PIR,r0 + mfspr r0,SPRN_PIR + stw r0,ENTRY_PIR(r10) + + mtspr IVPR,r12 +/* + * Coming here, we know the cpu has one TLB mapping in TLB1[0] + * which maps 0xfffff000-0xffffffff one-to-one. We set up a + * second mapping that maps addr 1:1 for 64M, and then we jump to + * addr + */ + lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h + mtspr SPRN_MAS0,r10 + lis r10,(MAS1_VALID|MAS1_IPROT)@h + ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l + mtspr SPRN_MAS1,r10 + /* WIMGE = 0b00000 for now */ + mtspr SPRN_MAS2,r12 + ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR) + mtspr SPRN_MAS3,r12 +#ifdef CONFIG_ENABLE_36BIT_PHYS + mtspr SPRN_MAS7,r11 +#endif + tlbwe + +/* Now we have another mapping for this page, so we jump to that + * mapping + */ + mtspr SPRN_SRR1,r13 + rfi + + + .align 6 + .globl __spin_table +__spin_table: + .space CONFIG_MAX_CPUS*ENTRY_SIZE + +#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE + .align L1_CACHE_SHIFT + .global spin_table_compat +spin_table_compat: + .long 1 + +#endif + +__spin_table_end: + .space 4096 - (__spin_table_end - __spin_table) diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/resetvec.S b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/resetvec.S new file mode 100644 index 000000000..29555d4a0 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/resetvec.S @@ -0,0 +1,2 @@ + .section .resetvec,"ax" + b _start_e500 diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/serial_scc.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/serial_scc.c new file mode 100644 index 000000000..faba6421f --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/serial_scc.c @@ -0,0 +1,262 @@ +/* + * (C) Copyright 2003 Motorola Inc. + * Xianghua Xiao (X.Xiao@motorola.com) + * Modified based on 8260 for 8560. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00. + */ + +/* + * Minimal serial functions needed to use one of the SCC ports + * as serial console interface. + */ + +#include <common.h> +#include <asm/cpm_85xx.h> +#include <serial.h> +#include <linux/compiler.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CONS_ON_SCC) + +#if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */ + +#define SCC_INDEX 0 +#define PROFF_SCC PROFF_SCC1 +#define CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\ + CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK) +#define CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1) +#define CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE +#define CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK + +#elif CONFIG_CONS_INDEX == 2 /* Console on SCC2 */ + +#define SCC_INDEX 1 +#define PROFF_SCC PROFF_SCC2 +#define CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\ + CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK) +#define CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2) +#define CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE +#define CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK + +#elif CONFIG_CONS_INDEX == 3 /* Console on SCC3 */ + +#define SCC_INDEX 2 +#define PROFF_SCC PROFF_SCC3 +#define CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\ + CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK) +#define CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3) +#define CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE +#define CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK + +#elif CONFIG_CONS_INDEX == 4 /* Console on SCC4 */ + +#define SCC_INDEX 3 +#define PROFF_SCC PROFF_SCC4 +#define CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\ + CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK) +#define CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4) +#define CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE +#define CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK + +#else + +#error "console not correctly defined" + +#endif + +static int mpc85xx_serial_init(void) +{ + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; + volatile ccsr_cpm_scc_t *sp; + volatile scc_uart_t *up; + volatile cbd_t *tbdf, *rbdf; + volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp); + uint dpaddr; + + /* initialize pointers to SCC */ + + sp = (ccsr_cpm_scc_t *) &(cpm->im_cpm_scc[SCC_INDEX]); + up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); + + /* Disable transmitter/receiver. + */ + sp->gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); + + /* put the SCC channel into NMSI (non multiplexd serial interface) + * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15). + */ + cpm->im_cpm_mux.cmxscr = \ + (cpm->im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE; + + /* Set up the baud rate generator. + */ + serial_setbrg (); + + /* Allocate space for two buffer descriptors in the DP ram. + * damm: allocating space after the two buffers for rx/tx data + */ + + dpaddr = m8560_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); + + /* Set the physical address of the host memory buffers in + * the buffer descriptors. + */ + rbdf = (cbd_t *)&(cpm->im_dprambase[dpaddr]); + rbdf->cbd_bufaddr = (uint) (rbdf+2); + rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; + tbdf = rbdf + 1; + tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; + tbdf->cbd_sc = BD_SC_WRAP; + + /* Set up the uart parameters in the parameter ram. + */ + up->scc_genscc.scc_rbase = dpaddr; + up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); + up->scc_genscc.scc_rfcr = CPMFCR_EB; + up->scc_genscc.scc_tfcr = CPMFCR_EB; + up->scc_genscc.scc_mrblr = 1; + up->scc_maxidl = 0; + up->scc_brkcr = 1; + up->scc_parec = 0; + up->scc_frmec = 0; + up->scc_nosec = 0; + up->scc_brkec = 0; + up->scc_uaddr1 = 0; + up->scc_uaddr2 = 0; + up->scc_toseq = 0; + up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000; + up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000; + up->scc_rccm = 0xc0ff; + + /* Mask all interrupts and remove anything pending. + */ + sp->sccm = 0; + sp->scce = 0xffff; + + /* Set 8 bit FIFO, 16 bit oversampling and UART mode. + */ + sp->gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */ + sp->gsmrl = \ + SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART; + + /* Set CTS no flow control, 1 stop bit, 8 bit character length, + * normal async UART mode, no parity + */ + sp->psmr = SCU_PSMR_CL; + + /* execute the "Init Rx and Tx params" CP command. + */ + + while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + cp->cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK, + 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; + + while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */ + ; + + /* Enable transmitter/receiver. + */ + sp->gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT; + + return (0); +} + +static void mpc85xx_serial_setbrg(void) +{ +#if defined(CONFIG_CONS_USE_EXTC) + m8560_cpm_extcbrg(SCC_INDEX, gd->baudrate, + CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL); +#else + m8560_cpm_setbrg(SCC_INDEX, gd->baudrate); +#endif +} + +static void mpc85xx_serial_putc(const char c) +{ + volatile scc_uart_t *up; + volatile cbd_t *tbdf; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; + + if (c == '\n') + serial_putc ('\r'); + + up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); + tbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_tbase]); + + /* Wait for last character to go. + */ + while (tbdf->cbd_sc & BD_SC_READY) + ; + + /* Load the character into the transmit buffer. + */ + *(volatile char *)tbdf->cbd_bufaddr = c; + tbdf->cbd_datlen = 1; + tbdf->cbd_sc |= BD_SC_READY; +} + +static int mpc85xx_serial_getc(void) +{ + volatile cbd_t *rbdf; + volatile scc_uart_t *up; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; + unsigned char c; + + up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); + rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]); + + /* Wait for character to show up. + */ + while (rbdf->cbd_sc & BD_SC_EMPTY) + ; + + /* Grab the char and clear the buffer again. + */ + c = *(volatile unsigned char *)rbdf->cbd_bufaddr; + rbdf->cbd_sc |= BD_SC_EMPTY; + + return (c); +} + +static int mpc85xx_serial_tstc(void) +{ + volatile cbd_t *rbdf; + volatile scc_uart_t *up; + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; + + up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); + rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]); + + return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0); +} + +static struct serial_device mpc85xx_serial_drv = { + .name = "mpc85xx_serial", + .start = mpc85xx_serial_init, + .stop = NULL, + .setbrg = mpc85xx_serial_setbrg, + .putc = mpc85xx_serial_putc, + .puts = default_serial_puts, + .getc = mpc85xx_serial_getc, + .tstc = mpc85xx_serial_tstc, +}; + +void mpc85xx_serial_initialize(void) +{ + serial_register(&mpc85xx_serial_drv); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &mpc85xx_serial_drv; +} +#endif /* CONFIG_CONS_ON_SCC */ diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/speed.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/speed.c new file mode 100644 index 000000000..3236f6a5d --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/speed.c @@ -0,0 +1,532 @@ +/* + * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. + * + * (C) Copyright 2003 Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <ppc_asm.tmpl> +#include <linux/compiler.h> +#include <asm/processor.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + + +#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS +#define CONFIG_SYS_FSL_NUM_CC_PLLS 6 +#endif +/* --------------------------------------------------------------- */ + +void get_sys_info(sys_info_t *sys_info) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_FSL_IFC + struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR; + u32 ccr; +#endif +#ifdef CONFIG_FSL_CORENET + volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); + unsigned int cpu; +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 + int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; +#endif + + const u8 core_cplx_PLL[16] = { + [ 0] = 0, /* CC1 PPL / 1 */ + [ 1] = 0, /* CC1 PPL / 2 */ + [ 2] = 0, /* CC1 PPL / 4 */ + [ 4] = 1, /* CC2 PPL / 1 */ + [ 5] = 1, /* CC2 PPL / 2 */ + [ 6] = 1, /* CC2 PPL / 4 */ + [ 8] = 2, /* CC3 PPL / 1 */ + [ 9] = 2, /* CC3 PPL / 2 */ + [10] = 2, /* CC3 PPL / 4 */ + [12] = 3, /* CC4 PPL / 1 */ + [13] = 3, /* CC4 PPL / 2 */ + [14] = 3, /* CC4 PPL / 4 */ + }; + + const u8 core_cplx_pll_div[16] = { + [ 0] = 1, /* CC1 PPL / 1 */ + [ 1] = 2, /* CC1 PPL / 2 */ + [ 2] = 4, /* CC1 PPL / 4 */ + [ 4] = 1, /* CC2 PPL / 1 */ + [ 5] = 2, /* CC2 PPL / 2 */ + [ 6] = 4, /* CC2 PPL / 4 */ + [ 8] = 1, /* CC3 PPL / 1 */ + [ 9] = 2, /* CC3 PPL / 2 */ + [10] = 4, /* CC3 PPL / 4 */ + [12] = 1, /* CC4 PPL / 1 */ + [13] = 2, /* CC4 PPL / 2 */ + [14] = 4, /* CC4 PPL / 4 */ + }; + uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; +#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) + uint rcw_tmp; +#endif + uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; + unsigned long sysclk = CONFIG_SYS_CLK_FREQ; + uint mem_pll_rat; + + sys_info->freq_systembus = sysclk; +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + uint ddr_refclk_sel; + unsigned int porsr1_sys_clk; + porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT + & FSL_DCFG_PORSR1_SYSCLK_MASK; + if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF) + sys_info->diff_sysclk = 1; + else + sys_info->diff_sysclk = 0; + + /* + * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS + * are driven by separate DDR Refclock or single source + * differential clock. + */ + ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >> + FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) & + FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK; + /* + * For single source clocking, both ddrclock and sysclock + * are driven by differential sysclock. + */ + if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) + sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ; + else +#endif +#ifdef CONFIG_DDR_CLK_FREQ + sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; +#else + sys_info->freq_ddrbus = sysclk; +#endif + + sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> + FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) + & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 + if (mem_pll_rat == 0) { + mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> + FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & + FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; + } +#endif + /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of + * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 + * it uses 6. + */ +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) + if (SVR_MAJ(get_svr()) >= 2) + mem_pll_rat *= 2; +#endif + if (mem_pll_rat > 2) + sys_info->freq_ddrbus *= mem_pll_rat; + else + sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat; + + for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { + ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; + if (ratio[i] > 4) + freq_c_pll[i] = sysclk * ratio[i]; + else + freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; + } +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 + /* + * As per CHASSIS2 architeture total 12 clusters are posible and + * Each cluster has up to 4 cores, sharing the same PLL selection. + * The cluster clock assignment is SoC defined. + * + * Total 4 clock groups are possible with 3 PLLs each. + * as per array indices, clock group A has 0, 1, 2 numbered PLLs & + * clock group B has 3, 4, 6 and so on. + * + * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster + * depends upon the SoC architeture. Same applies to other + * clock groups and clusters. + * + */ + for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { + int cluster = fsl_qoriq_core_to_cluster(cpu); + u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) + & 0xf; + u32 cplx_pll = core_cplx_PLL[c_pll_sel]; + cplx_pll += cc_group[cluster] - 1; + sys_info->freq_processor[cpu] = + freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; + } +#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \ + defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#define FM1_CLK_SEL 0xe0000000 +#define FM1_CLK_SHIFT 29 +#else +#define PME_CLK_SEL 0xe0000000 +#define PME_CLK_SHIFT 29 +#define FM1_CLK_SEL 0x1c000000 +#define FM1_CLK_SHIFT 26 +#endif +#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) + rcw_tmp = in_be32(&gur->rcwsr[7]); +#endif + +#ifdef CONFIG_SYS_DPAA_PME +#ifndef CONFIG_PME_PLAT_CLK_DIV + switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { + case 1: + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK]; + break; + case 2: + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2; + break; + case 3: + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3; + break; + case 4: + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4; + break; + case 6: + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2; + break; + case 7: + sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3; + break; + default: + printf("Error: Unknown PME clock select!\n"); + case 0: + sys_info->freq_pme = sys_info->freq_systembus / 2; + break; + + } +#else + sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK; + +#endif +#endif + +#ifdef CONFIG_SYS_DPAA_QBMAN + sys_info->freq_qman = sys_info->freq_systembus / 2; +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN +#ifndef CONFIG_FM_PLAT_CLK_DIV + switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { + case 1: + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK]; + break; + case 2: + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2; + break; + case 3: + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3; + break; + case 4: + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4; + break; + case 5: + sys_info->freq_fman[0] = sys_info->freq_systembus; + break; + case 6: + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2; + break; + case 7: + sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3; + break; + default: + printf("Error: Unknown FMan1 clock select!\n"); + case 0: + sys_info->freq_fman[0] = sys_info->freq_systembus / 2; + break; + } +#if (CONFIG_SYS_NUM_FMAN) == 2 +#ifdef CONFIG_SYS_FM2_CLK +#define FM2_CLK_SEL 0x00000038 +#define FM2_CLK_SHIFT 3 + rcw_tmp = in_be32(&gur->rcwsr[15]); + switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) { + case 1: + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1]; + break; + case 2: + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2; + break; + case 3: + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3; + break; + case 4: + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4; + break; + case 5: + sys_info->freq_fman[1] = sys_info->freq_systembus; + break; + case 6: + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2; + break; + case 7: + sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3; + break; + default: + printf("Error: Unknown FMan2 clock select!\n"); + case 0: + sys_info->freq_fman[1] = sys_info->freq_systembus / 2; + break; + } +#endif +#endif /* CONFIG_SYS_NUM_FMAN == 2 */ +#else + sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; +#endif +#endif + +#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ + + for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { + u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) + & 0xf; + u32 cplx_pll = core_cplx_PLL[c_pll_sel]; + + sys_info->freq_processor[cpu] = + freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; + } +#define PME_CLK_SEL 0x80000000 +#define FM1_CLK_SEL 0x40000000 +#define FM2_CLK_SEL 0x20000000 +#define HWA_ASYNC_DIV 0x04000000 +#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2) +#define HWA_CC_PLL 1 +#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3) +#define HWA_CC_PLL 2 +#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4) +#define HWA_CC_PLL 2 +#else +#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case +#endif + rcw_tmp = in_be32(&gur->rcwsr[7]); + +#ifdef CONFIG_SYS_DPAA_PME + if (rcw_tmp & PME_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4; + else + sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2; + } else { + sys_info->freq_pme = sys_info->freq_systembus / 2; + } +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN + if (rcw_tmp & FM1_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4; + else + sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2; + } else { + sys_info->freq_fman[0] = sys_info->freq_systembus / 2; + } +#if (CONFIG_SYS_NUM_FMAN) == 2 + if (rcw_tmp & FM2_CLK_SEL) { + if (rcw_tmp & HWA_ASYNC_DIV) + sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4; + else + sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2; + } else { + sys_info->freq_fman[1] = sys_info->freq_systembus / 2; + } +#endif +#endif + +#ifdef CONFIG_SYS_DPAA_QBMAN + sys_info->freq_qman = sys_info->freq_systembus / 2; +#endif + +#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ + +#ifdef CONFIG_U_QE + sys_info->freq_qe = sys_info->freq_systembus / 2; +#endif + +#else /* CONFIG_FSL_CORENET */ + uint plat_ratio, e500_ratio, half_freq_systembus; + int i; +#ifdef CONFIG_QE + __maybe_unused u32 qe_ratio; +#endif + + plat_ratio = (gur->porpllsr) & 0x0000003e; + plat_ratio >>= 1; + sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ; + + /* Divide before multiply to avoid integer + * overflow for processor speeds above 2GHz */ + half_freq_systembus = sys_info->freq_systembus/2; + for (i = 0; i < cpu_numcores(); i++) { + e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; + sys_info->freq_processor[i] = e500_ratio * half_freq_systembus; + } + + /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */ + sys_info->freq_ddrbus = sys_info->freq_systembus; + +#ifdef CONFIG_DDR_CLK_FREQ + { + u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) + >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; + if (ddr_ratio != 0x7) + sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ; + } +#endif + +#ifdef CONFIG_QE +#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) + sys_info->freq_qe = sys_info->freq_systembus; +#else + qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) + >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; + sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ; +#endif +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN + sys_info->freq_fman[0] = sys_info->freq_systembus; +#endif + +#endif /* CONFIG_FSL_CORENET */ + +#if defined(CONFIG_FSL_LBC) + uint lcrr_div; +#if defined(CONFIG_SYS_LBC_LCRR) + /* We will program LCRR to this value later */ + lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; +#else + lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; +#endif + if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { +#if defined(CONFIG_FSL_CORENET) + /* If this is corenet based SoC, bit-representation + * for four times the clock divider values. + */ + lcrr_div *= 4; +#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ + !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) + /* + * Yes, the entire PQ38 family use the same + * bit-representation for twice the clock divider values. + */ + lcrr_div *= 2; +#endif + sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div; + } else { + /* In case anyone cares what the unknown value is */ + sys_info->freq_localbus = lcrr_div; + } +#endif + +#if defined(CONFIG_FSL_IFC) + ccr = in_be32(&ifc_regs->ifc_ccr); + ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; + + sys_info->freq_localbus = sys_info->freq_systembus / ccr; +#endif +} + + +int get_clocks (void) +{ + sys_info_t sys_info; +#ifdef CONFIG_MPC8544 + volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; +#endif +#if defined(CONFIG_CPM2) + volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; + uint sccr, dfbrg; + + /* set VCO = 4 * BRG */ + cpm->im_cpm_intctl.sccr &= 0xfffffffc; + sccr = cpm->im_cpm_intctl.sccr; + dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; +#endif + get_sys_info (&sys_info); + gd->cpu_clk = sys_info.freq_processor[0]; + gd->bus_clk = sys_info.freq_systembus; + gd->mem_clk = sys_info.freq_ddrbus; + gd->arch.lbc_clk = sys_info.freq_localbus; + +#ifdef CONFIG_QE + gd->arch.qe_clk = sys_info.freq_qe; + gd->arch.brg_clk = gd->arch.qe_clk / 2; +#endif + /* + * The base clock for I2C depends on the actual SOC. Unfortunately, + * there is no pattern that can be used to determine the frequency, so + * the only choice is to look up the actual SOC number and use the value + * for that SOC. This information is taken from application note + * AN2919. + */ +#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \ + defined(CONFIG_P1022) + gd->arch.i2c1_clk = sys_info.freq_systembus; +#elif defined(CONFIG_MPC8544) + /* + * On the 8544, the I2C clock is the same as the SEC clock. This can be + * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See + * 4.4.3.3 of the 8544 RM. Note that this might actually work for all + * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the + * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. + */ + if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) + gd->arch.i2c1_clk = sys_info.freq_systembus / 3; + else + gd->arch.i2c1_clk = sys_info.freq_systembus / 2; +#else + /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ + gd->arch.i2c1_clk = sys_info.freq_systembus / 2; +#endif + gd->arch.i2c2_clk = gd->arch.i2c1_clk; + +#if defined(CONFIG_FSL_ESDHC) +#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ + defined(CONFIG_P1014) + gd->arch.sdhc_clk = gd->bus_clk; +#else + gd->arch.sdhc_clk = gd->bus_clk / 2; +#endif +#endif /* defined(CONFIG_FSL_ESDHC) */ + +#if defined(CONFIG_CPM2) + gd->arch.vco_out = 2*sys_info.freq_systembus; + gd->arch.cpm_clk = gd->arch.vco_out / 2; + gd->arch.scc_clk = gd->arch.vco_out / 4; + gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1))); +#endif + + if(gd->cpu_clk != 0) return (0); + else return (1); +} + + +/******************************************** + * get_bus_freq + * return system bus freq in Hz + *********************************************/ +ulong get_bus_freq (ulong dummy) +{ + return gd->bus_clk; +} + +/******************************************** + * get_ddr_freq + * return ddr bus freq in Hz + *********************************************/ +ulong get_ddr_freq (ulong dummy) +{ + return gd->mem_clk; +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/spl_minimal.c new file mode 100644 index 000000000..cc45f715e --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/spl_minimal.c @@ -0,0 +1,45 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/global_data.h> +#include <fsl_ifc.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +ulong cpu_init_f(void) +{ +#ifdef CONFIG_SYS_INIT_L2_ADDR + ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; + + out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); + + /* set MBECCDIS=1, SBECCDIS=1 */ + out_be32(&l2cache->l2errdis, + (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); + + /* set L2E=1 & L2SRAM=001 */ + out_be32(&l2cache->l2ctl, + (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); +#endif + + return 0; +} + +#ifndef CONFIG_SYS_FSL_TBCLK_DIV +#define CONFIG_SYS_FSL_TBCLK_DIV 8 +#endif + +void udelay(unsigned long usec) +{ + u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000); + u32 ticks = ticks_per_usec * usec; + u32 s = mfspr(SPRN_TBRL); + + while ((mfspr(SPRN_TBRL) - s) < ticks); +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/start.S b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/start.S new file mode 100644 index 000000000..d8c9fb6b2 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/start.S @@ -0,0 +1,1978 @@ +/* + * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc. + * Copyright (C) 2003 Motorola,Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards + * + * The processor starts at 0xfffffffc and the code is first executed in the + * last 4K page(0xfffff000-0xffffffff) in flash/rom. + * + */ + +#include <asm-offsets.h> +#include <config.h> +#include <mpc85xx.h> +#include <version.h> + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> + +#include <asm/cache.h> +#include <asm/mmu.h> + +#undef MSR_KERNEL +#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ + +#define LAW_EN 0x80000000 + +#if defined(CONFIG_NAND_SPL) || \ + (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) +#define MINIMAL_SPL +#endif + +#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \ + !defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +#define NOR_BOOT +#endif + +/* + * Set up GOT: Global Offset Table + * + * Use r12 to access the GOT + */ + START_GOT + GOT_ENTRY(_GOT2_TABLE_) + GOT_ENTRY(_FIXUP_TABLE_) + +#ifndef MINIMAL_SPL + GOT_ENTRY(_start) + GOT_ENTRY(_start_of_vectors) + GOT_ENTRY(_end_of_vectors) + GOT_ENTRY(transfer_to_handler) +#endif + + GOT_ENTRY(__init_end) + GOT_ENTRY(__bss_end) + GOT_ENTRY(__bss_start) + END_GOT + +/* + * e500 Startup -- after reset only the last 4KB of the effective + * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg + * section is located at THIS LAST page and basically does three + * things: clear some registers, set up exception tables and + * add more TLB entries for 'larger spaces'(e.g. the boot rom) to + * continue the boot procedure. + + * Once the boot rom is mapped by TLB entries we can proceed + * with normal startup. + * + */ + + .section .bootpg,"ax" + .globl _start_e500 + +_start_e500: +/* Enable debug exception */ + li r1,MSR_DE + mtmsr r1 + + /* + * If we got an ePAPR device tree pointer passed in as r3, we need that + * later in cpu_init_early_f(). Save it to a safe register before we + * clobber it so that we can fetch it from there later. + */ + mr r24, r3 + +#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 + mfspr r3,SPRN_SVR + rlwinm r3,r3,0,0xff + li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV + cmpw r3,r4 + beq 1f + +#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 + li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 + cmpw r3,r4 + beq 1f +#endif + + /* Not a supported revision affected by erratum */ + li r27,0 + b 2f + +1: li r27,1 /* Remember for later that we have the erratum */ + /* Erratum says set bits 55:60 to 001001 */ + msync + isync + mfspr r3,SPRN_HDBCR0 + li r4,0x48 + rlwimi r3,r4,0,0x1f8 + mtspr SPRN_HDBCR0,r3 + isync +2: +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005125 + msync + isync + mfspr r3, SPRN_HDBCR0 + oris r3, r3, 0x0080 + mtspr SPRN_HDBCR0, r3 +#endif + + +#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \ + !defined(CONFIG_E6500) + /* ISBC uses L2 as stack. + * Disable L2 cache here so that u-boot can enable it later + * as part of it's normal flow + */ + + /* Check if L2 is enabled */ + mfspr r3, SPRN_L2CSR0 + lis r2, L2CSR0_L2E@h + ori r2, r2, L2CSR0_L2E@l + and. r4, r3, r2 + beq l2_disabled + + mfspr r3, SPRN_L2CSR0 + /* Flush L2 cache */ + lis r2,(L2CSR0_L2FL)@h + ori r2, r2, (L2CSR0_L2FL)@l + or r3, r2, r3 + sync + isync + mtspr SPRN_L2CSR0,r3 + isync +1: + mfspr r3, SPRN_L2CSR0 + and. r1, r3, r2 + bne 1b + + mfspr r3, SPRN_L2CSR0 + lis r2, L2CSR0_L2E@h + ori r2, r2, L2CSR0_L2E@l + andc r4, r3, r2 + sync + isync + mtspr SPRN_L2CSR0,r4 + isync + +l2_disabled: +#endif + +/* clear registers/arrays not reset by hardware */ + + /* L1 */ + li r0,2 + mtspr L1CSR0,r0 /* invalidate d-cache */ + mtspr L1CSR1,r0 /* invalidate i-cache */ + + mfspr r1,DBSR + mtspr DBSR,r1 /* Clear all valid bits */ + + + .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch + lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h + ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l + mtspr MAS0, \scratch + lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h + ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l + mtspr MAS1, \scratch + lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h + ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l + mtspr MAS2, \scratch + lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h + ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l + mtspr MAS3, \scratch + lis \scratch, \phy_high@h + ori \scratch, \scratch, \phy_high@l + mtspr MAS7, \scratch + isync + msync + tlbwe + isync + .endm + + .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch + lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h + ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l + mtspr MAS0, \scratch + lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h + ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l + mtspr MAS1, \scratch + lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h + ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l + mtspr MAS2, \scratch + lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h + ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l + mtspr MAS3, \scratch + lis \scratch, \phy_high@h + ori \scratch, \scratch, \phy_high@l + mtspr MAS7, \scratch + isync + msync + tlbwe + isync + .endm + + .macro delete_tlb1_entry esel scratch + lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h + ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l + mtspr MAS0, \scratch + li \scratch, 0 + mtspr MAS1, \scratch + isync + msync + tlbwe + isync + .endm + + .macro delete_tlb0_entry esel epn wimg scratch + lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h + ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l + mtspr MAS0, \scratch + li \scratch, 0 + mtspr MAS1, \scratch + lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h + ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l + mtspr MAS2, \scratch + isync + msync + tlbwe + isync + .endm + +/* Interrupt vectors do not fit in minimal SPL. */ +#if !defined(MINIMAL_SPL) + /* Setup interrupt vectors */ + lis r1,CONFIG_SYS_MONITOR_BASE@h + mtspr IVPR,r1 + + lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h + ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l + + addi r4,r3,CriticalInput - _start + _START_OFFSET + mtspr IVOR0,r4 /* 0: Critical input */ + addi r4,r3,MachineCheck - _start + _START_OFFSET + mtspr IVOR1,r4 /* 1: Machine check */ + addi r4,r3,DataStorage - _start + _START_OFFSET + mtspr IVOR2,r4 /* 2: Data storage */ + addi r4,r3,InstStorage - _start + _START_OFFSET + mtspr IVOR3,r4 /* 3: Instruction storage */ + addi r4,r3,ExtInterrupt - _start + _START_OFFSET + mtspr IVOR4,r4 /* 4: External interrupt */ + addi r4,r3,Alignment - _start + _START_OFFSET + mtspr IVOR5,r4 /* 5: Alignment */ + addi r4,r3,ProgramCheck - _start + _START_OFFSET + mtspr IVOR6,r4 /* 6: Program check */ + addi r4,r3,FPUnavailable - _start + _START_OFFSET + mtspr IVOR7,r4 /* 7: floating point unavailable */ + addi r4,r3,SystemCall - _start + _START_OFFSET + mtspr IVOR8,r4 /* 8: System call */ + /* 9: Auxiliary processor unavailable(unsupported) */ + addi r4,r3,Decrementer - _start + _START_OFFSET + mtspr IVOR10,r4 /* 10: Decrementer */ + addi r4,r3,IntervalTimer - _start + _START_OFFSET + mtspr IVOR11,r4 /* 11: Interval timer */ + addi r4,r3,WatchdogTimer - _start + _START_OFFSET + mtspr IVOR12,r4 /* 12: Watchdog timer */ + addi r4,r3,DataTLBError - _start + _START_OFFSET + mtspr IVOR13,r4 /* 13: Data TLB error */ + addi r4,r3,InstructionTLBError - _start + _START_OFFSET + mtspr IVOR14,r4 /* 14: Instruction TLB error */ + addi r4,r3,DebugBreakpoint - _start + _START_OFFSET + mtspr IVOR15,r4 /* 15: Debug */ +#endif + + /* Clear and set up some registers. */ + li r0,0x0000 + lis r1,0xffff + mtspr DEC,r0 /* prevent dec exceptions */ + mttbl r0 /* prevent fit & wdt exceptions */ + mttbu r0 + mtspr TSR,r1 /* clear all timer exception status */ + mtspr TCR,r0 /* disable all */ + mtspr ESR,r0 /* clear exception syndrome register */ + mtspr MCSR,r0 /* machine check syndrome register */ + mtxer r0 /* clear integer exception register */ + +#ifdef CONFIG_SYS_BOOK3E_HV + mtspr MAS8,r0 /* make sure MAS8 is clear */ +#endif + + /* Enable Time Base and Select Time Base Clock */ + lis r0,HID0_EMCP@h /* Enable machine check */ +#if defined(CONFIG_ENABLE_36BIT_PHYS) + ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */ +#endif +#ifndef CONFIG_E500MC + ori r0,r0,HID0_TBEN@l /* Enable Timebase */ +#endif + mtspr HID0,r0 + +#if !defined(CONFIG_E500MC) && !defined(CONFIG_QEMU_E500) + li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ + mfspr r3,PVR + andi. r3,r3, 0xff + cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */ + blt 1f + /* Set MBDD bit also */ + ori r0, r0, HID1_MBDD@l +1: + mtspr HID1,r0 +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999 + mfspr r3,SPRN_HDBCR1 + oris r3,r3,0x0100 + mtspr SPRN_HDBCR1,r3 +#endif + + /* Enable Branch Prediction */ +#if defined(CONFIG_BTB) + lis r0,BUCSR_ENABLE@h + ori r0,r0,BUCSR_ENABLE@l + mtspr SPRN_BUCSR,r0 +#endif + +#if defined(CONFIG_SYS_INIT_DBCR) + lis r1,0xffff + ori r1,r1,0xffff + mtspr DBSR,r1 /* Clear all status bits */ + lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ + ori r0,r0,CONFIG_SYS_INIT_DBCR@l + mtspr DBCR0,r0 +#endif + +#ifdef CONFIG_MPC8569 +#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000) +#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0) + + /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to + * use address space which is more than 12bits, and it must be done in + * the 4K boot page. So we set this bit here. + */ + + /* create a temp mapping TLB0[0] for LBCR */ + create_tlb0_entry 0, \ + 0, BOOKE_PAGESZ_4K, \ + CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \ + CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \ + 0, r6 + + /* Set LBCR register */ + lis r4,CONFIG_SYS_LBCR_ADDR@h + ori r4,r4,CONFIG_SYS_LBCR_ADDR@l + + lis r5,CONFIG_SYS_LBC_LBCR@h + ori r5,r5,CONFIG_SYS_LBC_LBCR@l + stw r5,0(r4) + isync + + /* invalidate this temp TLB */ + lis r4,CONFIG_SYS_LBC_ADDR@h + ori r4,r4,CONFIG_SYS_LBC_ADDR@l + tlbivax 0,r4 + isync + +#endif /* CONFIG_MPC8569 */ + +/* + * Search for the TLB that covers the code we're executing, and shrink it + * so that it covers only this 4K page. That will ensure that any other + * TLB we create won't interfere with it. We assume that the TLB exists, + * which is why we don't check the Valid bit of MAS1. We also assume + * it is in TLB1. + * + * This is necessary, for example, when booting from the on-chip ROM, + * which (oddly) creates a single 4GB TLB that covers CCSR and DDR. + */ + bl nexti /* Find our address */ +nexti: mflr r1 /* R1 = our PC */ + li r2, 0 + mtspr MAS6, r2 /* Assume the current PID and AS are 0 */ + isync + msync + tlbsx 0, r1 /* This must succeed */ + + mfspr r14, MAS0 /* Save ESEL for later */ + rlwinm r14, r14, 16, 0xfff + + /* Set the size of the TLB to 4KB */ + mfspr r3, MAS1 + li r2, 0xF80 + andc r3, r3, r2 /* Clear the TSIZE bits */ + ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l + oris r3, r3, MAS1_IPROT@h + mtspr MAS1, r3 + + /* + * Set the base address of the TLB to our PC. We assume that + * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN. + */ + lis r3, MAS2_EPN@h + ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */ + + and r1, r1, r3 /* Our PC, rounded down to the nearest page */ + + mfspr r2, MAS2 + andc r2, r2, r3 + or r2, r2, r1 +#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 + cmpwi r27,0 + beq 1f + andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */ + rlwinm r2, r2, 0, ~MAS2_I + ori r2, r2, MAS2_G +1: +#endif + mtspr MAS2, r2 /* Set the EPN to our PC base address */ + + mfspr r2, MAS3 + andc r2, r2, r3 + or r2, r2, r1 + mtspr MAS3, r2 /* Set the RPN to our PC base address */ + + isync + msync + tlbwe + +/* + * Clear out any other TLB entries that may exist, to avoid conflicts. + * Our TLB entry is in r14. + */ + li r0, TLBIVAX_ALL | TLBIVAX_TLB0 + tlbivax 0, r0 + tlbsync + + mfspr r4, SPRN_TLB1CFG + rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK + + li r3, 0 + mtspr MAS1, r3 +1: cmpw r3, r14 + rlwinm r5, r3, 16, MAS0_ESEL_MSK + addi r3, r3, 1 + beq 2f /* skip the entry we're executing from */ + + oris r5, r5, MAS0_TLBSEL(1)@h + mtspr MAS0, r5 + + isync + tlbwe + isync + msync + +2: cmpw r3, r4 + blt 1b + +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \ + !defined(CONFIG_SECURE_BOOT) +/* + * TLB entry for debuggging in AS1 + * Create temporary TLB entry in AS0 to handle debug exception + * As on debug exception MSR is cleared i.e. Address space is changed + * to 0. A TLB entry (in AS0) is required to handle debug exception generated + * in AS1. + */ + +#ifdef NOR_BOOT +/* + * TLB entry is created for IVPR + IVOR15 to map on valid OP code address + * bacause flash's virtual address maps to 0xff800000 - 0xffffffff. + * and this window is outside of 4K boot window. + */ + create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ + 0, BOOKE_PAGESZ_4M, \ + CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \ + 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 + +#else +/* + * TLB entry is created for IVPR + IVOR15 to map on valid OP code address + * because "nexti" will resize TLB to 4K + */ + create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ + 0, BOOKE_PAGESZ_256K, \ + CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \ + CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 +#endif +#endif + +/* + * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default + * location is not where we want it. This typically happens on a 36-bit + * system, where we want to move CCSR to near the top of 36-bit address space. + * + * To move CCSR, we create two temporary TLBs, one for the old location, and + * another for the new location. On CoreNet systems, we also need to create + * a special, temporary LAW. + * + * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for + * long-term TLBs, so we use TLB0 here. + */ +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) + +#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW) +#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined." +#endif + +create_ccsr_new_tlb: + /* + * Create a TLB for the new location of CCSR. Register R8 is reserved + * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR). + */ + lis r8, CONFIG_SYS_CCSRBAR@h + ori r8, r8, CONFIG_SYS_CCSRBAR@l + lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h + ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l + create_tlb0_entry 0, \ + 0, BOOKE_PAGESZ_4K, \ + CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \ + CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \ + CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3 + /* + * Create a TLB for the current location of CCSR. Register R9 is reserved + * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). + */ +create_ccsr_old_tlb: + create_tlb0_entry 1, \ + 0, BOOKE_PAGESZ_4K, \ + CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \ + CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \ + 0, r3 /* The default CCSR address is always a 32-bit number */ + + + /* + * We have a TLB for what we think is the current (old) CCSR. Let's + * verify that, otherwise we won't be able to move it. + * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only + * need to compare the lower 32 bits of CCSRBAR on CoreNet systems. + */ +verify_old_ccsr: + lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h + ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l +#ifdef CONFIG_FSL_CORENET + lwz r1, 4(r9) /* CCSRBARL */ +#else + lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */ + slwi r1, r1, 12 +#endif + + cmpl 0, r0, r1 + + /* + * If the value we read from CCSRBARL is not what we expect, then + * enter an infinite loop. This will at least allow a debugger to + * halt execution and examine TLBs, etc. There's no point in going + * on. + */ +infinite_debug_loop: + bne infinite_debug_loop + +#ifdef CONFIG_FSL_CORENET + +#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) +#define LAW_SIZE_4K 0xb +#define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K) +#define CCSRAR_C 0x80000000 /* Commit */ + +create_temp_law: + /* + * On CoreNet systems, we create the temporary LAW using a special LAW + * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR. + */ + lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h + ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l + lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h + ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l + lis r2, CCSRBAR_LAWAR@h + ori r2, r2, CCSRBAR_LAWAR@l + + stw r0, 0xc00(r9) /* LAWBARH0 */ + stw r1, 0xc04(r9) /* LAWBARL0 */ + sync + stw r2, 0xc08(r9) /* LAWAR0 */ + + /* + * Read back from LAWAR to ensure the update is complete. e500mc + * cores also require an isync. + */ + lwz r0, 0xc08(r9) /* LAWAR0 */ + isync + + /* + * Read the current CCSRBARH and CCSRBARL using load word instructions. + * Follow this with an isync instruction. This forces any outstanding + * accesses to configuration space to completion. + */ +read_old_ccsrbar: + lwz r0, 0(r9) /* CCSRBARH */ + lwz r0, 4(r9) /* CCSRBARL */ + isync + + /* + * Write the new values for CCSRBARH and CCSRBARL to their old + * locations. The CCSRBARH has a shadow register. When the CCSRBARH + * has a new value written it loads a CCSRBARH shadow register. When + * the CCSRBARL is written, the CCSRBARH shadow register contents + * along with the CCSRBARL value are loaded into the CCSRBARH and + * CCSRBARL registers, respectively. Follow this with a sync + * instruction. + */ +write_new_ccsrbar: + lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h + ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l + lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h + ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l + lis r2, CCSRAR_C@h + ori r2, r2, CCSRAR_C@l + + stw r0, 0(r9) /* Write to CCSRBARH */ + sync /* Make sure we write to CCSRBARH first */ + stw r1, 4(r9) /* Write to CCSRBARL */ + sync + + /* + * Write a 1 to the commit bit (C) of CCSRAR at the old location. + * Follow this with a sync instruction. + */ + stw r2, 8(r9) + sync + + /* Delete the temporary LAW */ +delete_temp_law: + li r1, 0 + stw r1, 0xc08(r8) + sync + stw r1, 0xc00(r8) + stw r1, 0xc04(r8) + sync + +#else /* #ifdef CONFIG_FSL_CORENET */ + +write_new_ccsrbar: + /* + * Read the current value of CCSRBAR using a load word instruction + * followed by an isync. This forces all accesses to configuration + * space to complete. + */ + sync + lwz r0, 0(r9) + isync + +/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */ +#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \ + (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12)) + + /* Write the new value to CCSRBAR. */ + lis r0, CCSRBAR_PHYS_RS12@h + ori r0, r0, CCSRBAR_PHYS_RS12@l + stw r0, 0(r9) + sync + + /* + * The manual says to perform a load of an address that does not + * access configuration space or the on-chip SRAM using an existing TLB, + * but that doesn't appear to be necessary. We will do the isync, + * though. + */ + isync + + /* + * Read the contents of CCSRBAR from its new location, followed by + * another isync. + */ + lwz r0, 0(r8) + isync + +#endif /* #ifdef CONFIG_FSL_CORENET */ + + /* Delete the temporary TLBs */ +delete_temp_tlbs: + delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3 + delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3 + +#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ + +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) +create_ccsr_l2_tlb: + /* + * Create a TLB for the MMR location of CCSR + * to access L2CSR0 register + */ + create_tlb0_entry 0, \ + 0, BOOKE_PAGESZ_4K, \ + CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \ + CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \ + CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3 + +enable_l2_cluster_l2: + /* enable L2 cache */ + lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h + ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l + li r4, 33 /* stash id */ + stw r4, 4(r3) + lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h + ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l + sync + stw r4, 0(r3) /* invalidate L2 */ +1: sync + lwz r0, 0(r3) + twi 0, r0, 0 + isync + and. r1, r0, r4 + bne 1b + lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h + ori r4, r4, (L2CSR0_L2REP_MODE)@l + sync + stw r4, 0(r3) /* enable L2 */ +delete_ccsr_l2_tlb: + delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3 +#endif + + /* + * Enable the L1. On e6500, this has to be done + * after the L2 is up. + */ + +#ifdef CONFIG_SYS_CACHE_STASHING + /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ + li r2,(32 + 0) + mtspr L1CSR2,r2 +#endif + + /* Enable/invalidate the I-Cache */ + lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h + ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l + mtspr SPRN_L1CSR1,r2 +1: + mfspr r3,SPRN_L1CSR1 + and. r1,r3,r2 + bne 1b + + lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h + ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l + mtspr SPRN_L1CSR1,r3 + isync +2: + mfspr r3,SPRN_L1CSR1 + andi. r1,r3,L1CSR1_ICE@l + beq 2b + + /* Enable/invalidate the D-Cache */ + lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h + ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l + mtspr SPRN_L1CSR0,r2 +1: + mfspr r3,SPRN_L1CSR0 + and. r1,r3,r2 + bne 1b + + lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h + ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l + mtspr SPRN_L1CSR0,r3 + isync +2: + mfspr r3,SPRN_L1CSR0 + andi. r1,r3,L1CSR0_DCE@l + beq 2b +#ifdef CONFIG_SYS_FSL_ERRATUM_A004510 +#define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) +#define LAW_SIZE_1M 0x13 +#define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M) + + cmpwi r27,0 + beq 9f + + /* + * Create a TLB entry for CCSR + * + * We're executing out of TLB1 entry in r14, and that's the only + * TLB entry that exists. To allocate some TLB entries for our + * own use, flip a bit high enough that we won't flip it again + * via incrementing. + */ + + xori r8, r14, 32 + lis r0, MAS0_TLBSEL(1)@h + rlwimi r0, r8, 16, MAS0_ESEL_MSK + lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h + ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l + lis r7, CONFIG_SYS_CCSRBAR@h + ori r7, r7, CONFIG_SYS_CCSRBAR@l + ori r2, r7, MAS2_I|MAS2_G + lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h + ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l + lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h + ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l + mtspr MAS0, r0 + mtspr MAS1, r1 + mtspr MAS2, r2 + mtspr MAS3, r3 + mtspr MAS7, r4 + isync + tlbwe + isync + msync + + /* Map DCSR temporarily to physical address zero */ + li r0, 0 + lis r3, DCSRBAR_LAWAR@h + ori r3, r3, DCSRBAR_LAWAR@l + + stw r0, 0xc00(r7) /* LAWBARH0 */ + stw r0, 0xc04(r7) /* LAWBARL0 */ + sync + stw r3, 0xc08(r7) /* LAWAR0 */ + + /* Read back from LAWAR to ensure the update is complete. */ + lwz r3, 0xc08(r7) /* LAWAR0 */ + isync + + /* Create a TLB entry for DCSR at zero */ + + addi r9, r8, 1 + lis r0, MAS0_TLBSEL(1)@h + rlwimi r0, r9, 16, MAS0_ESEL_MSK + lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h + ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l + li r6, 0 /* DCSR effective address */ + ori r2, r6, MAS2_I|MAS2_G + li r3, MAS3_SW|MAS3_SR + li r4, 0 + mtspr MAS0, r0 + mtspr MAS1, r1 + mtspr MAS2, r2 + mtspr MAS3, r3 + mtspr MAS7, r4 + isync + tlbwe + isync + msync + + /* enable the timebase */ +#define CTBENR 0xe2084 + li r3, 1 + addis r4, r7, CTBENR@ha + stw r3, CTBENR@l(r4) + lwz r3, CTBENR@l(r4) + twi 0,r3,0 + isync + + .macro erratum_set_ccsr offset value + addis r3, r7, \offset@ha + lis r4, \value@h + addi r3, r3, \offset@l + ori r4, r4, \value@l + bl erratum_set_value + .endm + + .macro erratum_set_dcsr offset value + addis r3, r6, \offset@ha + lis r4, \value@h + addi r3, r3, \offset@l + ori r4, r4, \value@l + bl erratum_set_value + .endm + + erratum_set_dcsr 0xb0e08 0xe0201800 + erratum_set_dcsr 0xb0e18 0xe0201800 + erratum_set_dcsr 0xb0e38 0xe0400000 + erratum_set_dcsr 0xb0008 0x00900000 + erratum_set_dcsr 0xb0e40 0xe00a0000 + erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY +#ifdef CONFIG_RAMBOOT_PBL + erratum_set_ccsr 0x10f00 0x495e5000 +#else + erratum_set_ccsr 0x10f00 0x415e5000 +#endif + erratum_set_ccsr 0x11f00 0x415e5000 + + /* Make temp mapping uncacheable again, if it was initially */ + bl 2f +2: mflr r3 + tlbsx 0, r3 + mfspr r4, MAS2 + rlwimi r4, r15, 0, MAS2_I + rlwimi r4, r15, 0, MAS2_G + mtspr MAS2, r4 + isync + tlbwe + isync + msync + + /* Clear the cache */ + lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h + ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l + sync + isync + mtspr SPRN_L1CSR1,r3 + isync +2: sync + mfspr r4,SPRN_L1CSR1 + and. r4,r4,r3 + bne 2b + + lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h + ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l + sync + isync + mtspr SPRN_L1CSR1,r3 + isync +2: sync + mfspr r4,SPRN_L1CSR1 + and. r4,r4,r3 + beq 2b + + /* Remove temporary mappings */ + lis r0, MAS0_TLBSEL(1)@h + rlwimi r0, r9, 16, MAS0_ESEL_MSK + li r3, 0 + mtspr MAS0, r0 + mtspr MAS1, r3 + isync + tlbwe + isync + msync + + li r3, 0 + stw r3, 0xc08(r7) /* LAWAR0 */ + lwz r3, 0xc08(r7) + isync + + lis r0, MAS0_TLBSEL(1)@h + rlwimi r0, r8, 16, MAS0_ESEL_MSK + li r3, 0 + mtspr MAS0, r0 + mtspr MAS1, r3 + isync + tlbwe + isync + msync + + b 9f + + /* r3 = addr, r4 = value, clobbers r5, r11, r12 */ +erratum_set_value: + /* Lock two cache lines into I-Cache */ + sync + mfspr r11, SPRN_L1CSR1 + rlwinm r11, r11, 0, ~L1CSR1_ICUL + sync + isync + mtspr SPRN_L1CSR1, r11 + isync + + mflr r12 + bl 5f +5: mflr r5 + addi r5, r5, 2f - 5b + icbtls 0, 0, r5 + addi r5, r5, 64 + + sync + mfspr r11, SPRN_L1CSR1 +3: andi. r11, r11, L1CSR1_ICUL + bne 3b + + icbtls 0, 0, r5 + addi r5, r5, 64 + + sync + mfspr r11, SPRN_L1CSR1 +3: andi. r11, r11, L1CSR1_ICUL + bne 3b + + b 2f + .align 6 + /* Inside a locked cacheline, wait a while, write, then wait a while */ +2: sync + + mfspr r5, SPRN_TBRL + addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */ +4: mfspr r5, SPRN_TBRL + subf. r5, r5, r11 + bgt 4b + + stw r4, 0(r3) + + mfspr r5, SPRN_TBRL + addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */ +4: mfspr r5, SPRN_TBRL + subf. r5, r5, r11 + bgt 4b + + sync + + /* + * Fill out the rest of this cache line and the next with nops, + * to ensure that nothing outside the locked area will be + * fetched due to a branch. + */ + .rept 19 + nop + .endr + + sync + mfspr r11, SPRN_L1CSR1 + rlwinm r11, r11, 0, ~L1CSR1_ICUL + sync + isync + mtspr SPRN_L1CSR1, r11 + isync + + mtlr r12 + blr + +9: +#endif + +create_init_ram_area: + lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h + ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l + +#ifdef NOR_BOOT + /* create a temp mapping in AS=1 to the 4M boot window */ + create_tlb1_entry 15, \ + 1, BOOKE_PAGESZ_4M, \ + CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \ + 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 + +#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) + /* create a temp mapping in AS = 1 for Flash mapping + * created by PBL for ISBC code + */ + create_tlb1_entry 15, \ + 1, BOOKE_PAGESZ_1M, \ + CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ + CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 +#else + /* + * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main + * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage. + */ + create_tlb1_entry 15, \ + 1, BOOKE_PAGESZ_1M, \ + CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ + CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 +#endif + + /* create a temp mapping in AS=1 to the stack */ +#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ + defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH) + create_tlb1_entry 14, \ + 1, BOOKE_PAGESZ_16K, \ + CONFIG_SYS_INIT_RAM_ADDR, 0, \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6 + +#else + create_tlb1_entry 14, \ + 1, BOOKE_PAGESZ_16K, \ + CONFIG_SYS_INIT_RAM_ADDR, 0, \ + CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \ + 0, r6 +#endif + + lis r6,MSR_IS|MSR_DS|MSR_DE@h + ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l + lis r7,switch_as@h + ori r7,r7,switch_as@l + + mtspr SPRN_SRR0,r7 + mtspr SPRN_SRR1,r6 + rfi + +switch_as: +/* L1 DCache is used for initial RAM */ + + /* Allocate Initial RAM in data cache. + */ + lis r3,CONFIG_SYS_INIT_RAM_ADDR@h + ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l + mfspr r2, L1CFG0 + andi. r2, r2, 0x1ff + /* cache size * 1024 / (2 * L1 line size) */ + slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT) + mtctr r2 + li r0,0 +1: + dcbz r0,r3 + dcbtls 0,r0,r3 + addi r3,r3,CONFIG_SYS_CACHELINE_SIZE + bdnz 1b + + /* Jump out the last 4K page and continue to 'normal' start */ +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) + /* We assume that we're already running at the address we're linked at */ + b _start_cont +#else + /* Calculate absolute address in FLASH and jump there */ + /*--------------------------------------------------------------*/ + lis r3,CONFIG_SYS_MONITOR_BASE@h + ori r3,r3,CONFIG_SYS_MONITOR_BASE@l + addi r3,r3,_start_cont - _start + _START_OFFSET + mtlr r3 + blr +#endif + + .text + .globl _start +_start: + .long 0x27051956 /* U-BOOT Magic Number */ + .globl version_string +version_string: + .ascii U_BOOT_VERSION_STRING, "\0" + + .align 4 + .globl _start_cont +_start_cont: + /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ + lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h + ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */ + li r0,0 + stw r0,0(r3) /* Terminate Back Chain */ + stw r0,+4(r3) /* NULL return address. */ + mr r1,r3 /* Transfer to SP(r1) */ + + GET_GOT + + /* Pass our potential ePAPR device tree pointer to cpu_init_early_f */ + mr r3, r24 + + bl cpu_init_early_f + + /* switch back to AS = 0 */ + lis r3,(MSR_CE|MSR_ME|MSR_DE)@h + ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l + mtmsr r3 + isync + + bl cpu_init_f /* return boot_flag for calling board_init_f */ + bl board_init_f + isync + + /* NOTREACHED - board_init_f() does not return */ + +#ifndef MINIMAL_SPL + . = EXC_OFF_SYS_RESET + .globl _start_of_vectors +_start_of_vectors: + +/* Critical input. */ + CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException) + +/* Machine check */ + MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) + +/* Data Storage exception. */ + STD_EXCEPTION(0x0300, DataStorage, UnknownException) + +/* Instruction Storage exception. */ + STD_EXCEPTION(0x0400, InstStorage, UnknownException) + +/* External Interrupt exception. */ + STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException) + +/* Alignment exception. */ + . = 0x0600 +Alignment: + EXCEPTION_PROLOG(SRR0, SRR1) + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) + +/* Program check exception */ + . = 0x0700 +ProgramCheck: + EXCEPTION_PROLOG(SRR0, SRR1) + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, + MSR_KERNEL, COPY_EE) + + /* No FPU on MPC85xx. This exception is not supposed to happen. + */ + STD_EXCEPTION(0x0800, FPUnavailable, UnknownException) + + . = 0x0900 +/* + * r0 - SYSCALL number + * r3-... arguments + */ +SystemCall: + addis r11,r0,0 /* get functions table addr */ + ori r11,r11,0 /* Note: this code is patched in trap_init */ + addis r12,r0,0 /* get number of functions */ + ori r12,r12,0 + + cmplw 0,r0,r12 + bge 1f + + rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ + add r11,r11,r0 + lwz r11,0(r11) + + li r20,0xd00-4 /* Get stack pointer */ + lwz r12,0(r20) + subi r12,r12,12 /* Adjust stack pointer */ + li r0,0xc00+_end_back-SystemCall + cmplw 0,r0,r12 /* Check stack overflow */ + bgt 1f + stw r12,0(r20) + + mflr r0 + stw r0,0(r12) + mfspr r0,SRR0 + stw r0,4(r12) + mfspr r0,SRR1 + stw r0,8(r12) + + li r12,0xc00+_back-SystemCall + mtlr r12 + mtspr SRR0,r11 + +1: SYNC + rfi +_back: + + mfmsr r11 /* Disable interrupts */ + li r12,0 + ori r12,r12,MSR_EE + andc r11,r11,r12 + SYNC /* Some chip revs need this... */ + mtmsr r11 + SYNC + + li r12,0xd00-4 /* restore regs */ + lwz r12,0(r12) + + lwz r11,0(r12) + mtlr r11 + lwz r11,4(r12) + mtspr SRR0,r11 + lwz r11,8(r12) + mtspr SRR1,r11 + + addi r12,r12,12 /* Adjust stack pointer */ + li r20,0xd00-4 + stw r12,0(r20) + + SYNC + rfi +_end_back: + + STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt) + STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException) + STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException) + + STD_EXCEPTION(0x0d00, DataTLBError, UnknownException) + STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException) + + CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException ) + + .globl _end_of_vectors +_end_of_vectors: + + + . = . + (0x100 - ( . & 0xff )) /* align for debug */ + +/* + * This code finishes saving the registers to the exception frame + * and jumps to the appropriate handler for the exception. + * Register r21 is pointer into trap frame, r1 has new stack pointer. + */ + .globl transfer_to_handler +transfer_to_handler: + stw r22,_NIP(r21) + lis r22,MSR_POW@h + andc r23,r23,r22 + stw r23,_MSR(r21) + SAVE_GPR(7, r21) + SAVE_4GPRS(8, r21) + SAVE_8GPRS(12, r21) + SAVE_8GPRS(24, r21) + + mflr r23 + andi. r24,r23,0x3f00 /* get vector offset */ + stw r24,TRAP(r21) + li r22,0 + stw r22,RESULT(r21) + mtspr SPRG2,r22 /* r1 is now kernel sp */ + + lwz r24,0(r23) /* virtual address of handler */ + lwz r23,4(r23) /* where to go when done */ + mtspr SRR0,r24 + mtspr SRR1,r20 + mtlr r23 + SYNC + rfi /* jump to handler, enable MMU */ + +int_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SRR0,r2 + mtspr SRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfi + +crit_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SPRN_CSRR0,r2 + mtspr SPRN_CSRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfci + +mck_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SPRN_MCSRR0,r2 + mtspr SPRN_MCSRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfmci + +/* Cache functions. +*/ +.globl flush_icache +flush_icache: +.globl invalidate_icache +invalidate_icache: + mfspr r0,L1CSR1 + ori r0,r0,L1CSR1_ICFI + msync + isync + mtspr L1CSR1,r0 + isync + blr /* entire I cache */ + +.globl invalidate_dcache +invalidate_dcache: + mfspr r0,L1CSR0 + ori r0,r0,L1CSR0_DCFI + msync + isync + mtspr L1CSR0,r0 + isync + blr + + .globl icache_enable +icache_enable: + mflr r8 + bl invalidate_icache + mtlr r8 + isync + mfspr r4,L1CSR1 + ori r4,r4,0x0001 + oris r4,r4,0x0001 + mtspr L1CSR1,r4 + isync + blr + + .globl icache_disable +icache_disable: + mfspr r0,L1CSR1 + lis r3,0 + ori r3,r3,L1CSR1_ICE + andc r0,r0,r3 + mtspr L1CSR1,r0 + isync + blr + + .globl icache_status +icache_status: + mfspr r3,L1CSR1 + andi. r3,r3,L1CSR1_ICE + blr + + .globl dcache_enable +dcache_enable: + mflr r8 + bl invalidate_dcache + mtlr r8 + isync + mfspr r0,L1CSR0 + ori r0,r0,0x0001 + oris r0,r0,0x0001 + msync + isync + mtspr L1CSR0,r0 + isync + blr + + .globl dcache_disable +dcache_disable: + mfspr r3,L1CSR0 + lis r4,0 + ori r4,r4,L1CSR0_DCE + andc r3,r3,r4 + mtspr L1CSR0,r3 + isync + blr + + .globl dcache_status +dcache_status: + mfspr r3,L1CSR0 + andi. r3,r3,L1CSR0_DCE + blr + + .globl get_pir +get_pir: + mfspr r3,PIR + blr + + .globl get_pvr +get_pvr: + mfspr r3,PVR + blr + + .globl get_svr +get_svr: + mfspr r3,SVR + blr + + .globl wr_tcr +wr_tcr: + mtspr TCR,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in8 */ +/* Description: Input 8 bits */ +/*------------------------------------------------------------------------------- */ + .globl in8 +in8: + lbz r3,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out8 */ +/* Description: Output 8 bits */ +/*------------------------------------------------------------------------------- */ + .globl out8 +out8: + stb r4,0x0000(r3) + sync + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out16 */ +/* Description: Output 16 bits */ +/*------------------------------------------------------------------------------- */ + .globl out16 +out16: + sth r4,0x0000(r3) + sync + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out16r */ +/* Description: Byte reverse and output 16 bits */ +/*------------------------------------------------------------------------------- */ + .globl out16r +out16r: + sthbrx r4,r0,r3 + sync + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out32 */ +/* Description: Output 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl out32 +out32: + stw r4,0x0000(r3) + sync + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out32r */ +/* Description: Byte reverse and output 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl out32r +out32r: + stwbrx r4,r0,r3 + sync + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in16 */ +/* Description: Input 16 bits */ +/*------------------------------------------------------------------------------- */ + .globl in16 +in16: + lhz r3,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in16r */ +/* Description: Input 16 bits and byte reverse */ +/*------------------------------------------------------------------------------- */ + .globl in16r +in16r: + lhbrx r3,r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in32 */ +/* Description: Input 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl in32 +in32: + lwz 3,0x0000(3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in32r */ +/* Description: Input 32 bits and byte reverse */ +/*------------------------------------------------------------------------------- */ + .globl in32r +in32r: + lwbrx r3,r0,r3 + blr +#endif /* !MINIMAL_SPL */ + +/*------------------------------------------------------------------------------*/ + +/* + * void write_tlb(mas0, mas1, mas2, mas3, mas7) + */ + .globl write_tlb +write_tlb: + mtspr MAS0,r3 + mtspr MAS1,r4 + mtspr MAS2,r5 + mtspr MAS3,r6 +#ifdef CONFIG_ENABLE_36BIT_PHYS + mtspr MAS7,r7 +#endif + li r3,0 +#ifdef CONFIG_SYS_BOOK3E_HV + mtspr MAS8,r3 +#endif + isync + tlbwe + msync + isync + blr + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + mr r1,r3 /* Set new stack pointer */ + mr r9,r4 /* Save copy of Init Data pointer */ + mr r10,r5 /* Save copy of Destination Address */ + + GET_GOT +#ifndef CONFIG_SPL_SKIP_RELOCATE + mr r3,r5 /* Destination Address */ + lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4,r4,CONFIG_SYS_MONITOR_BASE@l + lwz r5,GOT(__init_end) + sub r5,r5,r4 + li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address + * + * Offset: + */ + sub r15,r10,r4 + + /* First our own GOT */ + add r12,r12,r15 + /* the the one used by the C code */ + add r30,r30,r15 + + /* + * Now relocate code + */ + + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* In place copy is not necessary */ + beq 7f /* Protect against 0 count */ + mtctr r0 + bge cr1,2f + + la r8,-4(r4) + la r7,-4(r3) +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + b 4f + +2: slwi r0,r0,2 + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b + +/* + * Now flush the cache: note that we must start from a cache aligned + * address. Otherwise we might miss one cache line. + */ +4: cmpwi r6,0 + add r5,r3,r5 + beq 7f /* Always flush prefetch queue in any case */ + subi r0,r6,1 + andc r3,r3,r0 + mr r4,r3 +5: dcbst 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 5b + sync /* Wait for all dcbst to complete on bus */ + mr r4,r3 +6: icbi 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 6b +7: sync /* Wait for all icbi to complete on bus */ + isync + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + + addi r0,r10,in_ram - _start + _START_OFFSET + + /* + * As IVPR is going to point RAM address, + * Make sure IVOR15 has valid opcode to support debugger + */ + mtspr IVOR15,r0 + + /* + * Re-point the IVPR at RAM + */ + mtspr IVPR,r10 + + mtlr r0 + blr /* NEVER RETURNS! */ +#endif + .globl in_ram +in_ram: + + /* + * Relocation Function, r12 point to got2+0x8000 + * + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. + */ + li r0,__got2_entries@sectoff@l + la r3,GOT(_GOT2_TABLE_) + lwz r11,GOT(_GOT2_TABLE_) + mtctr r0 + sub r11,r3,r11 + addi r3,r3,-4 +1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f + add r0,r0,r11 + stw r0,0(r3) +2: bdnz 1b + + /* + * Now adjust the fixups and the pointers to the fixups + * in case we need to move ourselves again. + */ + li r0,__fixup_entries@sectoff@l + lwz r3,GOT(_FIXUP_TABLE_) + cmpwi r0,0 + mtctr r0 + addi r3,r3,-4 + beq 4f +3: lwzu r4,4(r3) + lwzux r0,r4,r11 + cmpwi r0,0 + add r0,r0,r11 + stw r4,0(r3) + beq- 5f + stw r0,0(r4) +5: bdnz 3b +4: +clear_bss: + /* + * Now clear BSS segment + */ + lwz r3,GOT(__bss_start) + lwz r4,GOT(__bss_end) + + cmplw 0,r3,r4 + beq 6f + + li r0,0 +5: + stw r0,0(r3) + addi r3,r3,4 + cmplw 0,r3,r4 + blt 5b +6: + + mr r3,r9 /* Init Data pointer */ + mr r4,r10 /* Destination Address */ + bl board_init_r + +#ifndef MINIMAL_SPL + /* + * Copy exception vector code to low memory + * + * r3: dest_addr + * r7: source address, r8: end address, r9: target address + */ + .globl trap_init +trap_init: + mflr r4 /* save link register */ + GET_GOT + lwz r7,GOT(_start_of_vectors) + lwz r8,GOT(_end_of_vectors) + + li r9,0x100 /* reset vector always at 0x100 */ + + cmplw 0,r7,r8 + bgelr /* return if r7>=r8 - just in case */ +1: + lwz r0,0(r7) + stw r0,0(r9) + addi r7,r7,4 + addi r9,r9,4 + cmplw 0,r7,r8 + bne 1b + + /* + * relocate `hdlr' and `int_return' entries + */ + li r7,.L_CriticalInput - _start + _START_OFFSET + bl trap_reloc + li r7,.L_MachineCheck - _start + _START_OFFSET + bl trap_reloc + li r7,.L_DataStorage - _start + _START_OFFSET + bl trap_reloc + li r7,.L_InstStorage - _start + _START_OFFSET + bl trap_reloc + li r7,.L_ExtInterrupt - _start + _START_OFFSET + bl trap_reloc + li r7,.L_Alignment - _start + _START_OFFSET + bl trap_reloc + li r7,.L_ProgramCheck - _start + _START_OFFSET + bl trap_reloc + li r7,.L_FPUnavailable - _start + _START_OFFSET + bl trap_reloc + li r7,.L_Decrementer - _start + _START_OFFSET + bl trap_reloc + li r7,.L_IntervalTimer - _start + _START_OFFSET + li r8,_end_of_vectors - _start + _START_OFFSET +2: + bl trap_reloc + addi r7,r7,0x100 /* next exception vector */ + cmplw 0,r7,r8 + blt 2b + + /* Update IVORs as per relocated vector table address */ + li r7,0x0100 + mtspr IVOR0,r7 /* 0: Critical input */ + li r7,0x0200 + mtspr IVOR1,r7 /* 1: Machine check */ + li r7,0x0300 + mtspr IVOR2,r7 /* 2: Data storage */ + li r7,0x0400 + mtspr IVOR3,r7 /* 3: Instruction storage */ + li r7,0x0500 + mtspr IVOR4,r7 /* 4: External interrupt */ + li r7,0x0600 + mtspr IVOR5,r7 /* 5: Alignment */ + li r7,0x0700 + mtspr IVOR6,r7 /* 6: Program check */ + li r7,0x0800 + mtspr IVOR7,r7 /* 7: floating point unavailable */ + li r7,0x0900 + mtspr IVOR8,r7 /* 8: System call */ + /* 9: Auxiliary processor unavailable(unsupported) */ + li r7,0x0a00 + mtspr IVOR10,r7 /* 10: Decrementer */ + li r7,0x0b00 + mtspr IVOR11,r7 /* 11: Interval timer */ + li r7,0x0c00 + mtspr IVOR12,r7 /* 12: Watchdog timer */ + li r7,0x0d00 + mtspr IVOR13,r7 /* 13: Data TLB error */ + li r7,0x0e00 + mtspr IVOR14,r7 /* 14: Instruction TLB error */ + li r7,0x0f00 + mtspr IVOR15,r7 /* 15: Debug */ + + lis r7,0x0 + mtspr IVPR,r7 + + mtlr r4 /* restore link register */ + blr + +.globl unlock_ram_in_cache +unlock_ram_in_cache: + /* invalidate the INIT_RAM section */ + lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h + ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l + mfspr r4,L1CFG0 + andi. r4,r4,0x1ff + slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) + mtctr r4 +1: dcbi r0,r3 + dcblc r0,r3 + addi r3,r3,CONFIG_SYS_CACHELINE_SIZE + bdnz 1b + sync + + /* Invalidate the TLB entries for the cache */ + lis r3,CONFIG_SYS_INIT_RAM_ADDR@h + ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l + tlbivax 0,r3 + addi r3,r3,0x1000 + tlbivax 0,r3 + addi r3,r3,0x1000 + tlbivax 0,r3 + addi r3,r3,0x1000 + tlbivax 0,r3 + isync + blr + +.globl flush_dcache +flush_dcache: + mfspr r3,SPRN_L1CFG0 + + rlwinm r5,r3,9,3 /* Extract cache block size */ + twlgti r5,1 /* Only 32 and 64 byte cache blocks + * are currently defined. + */ + li r4,32 + subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - + * log2(number of ways) + */ + slw r5,r4,r5 /* r5 = cache block size */ + + rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ + mulli r7,r7,13 /* An 8-way cache will require 13 + * loads per set. + */ + slw r7,r7,r6 + + /* save off HID0 and set DCFA */ + mfspr r8,SPRN_HID0 + ori r9,r8,HID0_DCFA@l + mtspr SPRN_HID0,r9 + isync + + lis r4,0 + mtctr r7 + +1: lwz r3,0(r4) /* Load... */ + add r4,r4,r5 + bdnz 1b + + msync + lis r4,0 + mtctr r7 + +1: dcbf 0,r4 /* ...and flush. */ + add r4,r4,r5 + bdnz 1b + + /* restore HID0 */ + mtspr SPRN_HID0,r8 + isync + + blr +#endif /* !MINIMAL_SPL */ diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/t1040_ids.c new file mode 100644 index 000000000..1034cd485 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/t1040_ids.c @@ -0,0 +1,84 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO(1, 27, 1, 0), + SET_QP_INFO(2, 28, 1, 0), + SET_QP_INFO(3, 29, 1, 1), + SET_QP_INFO(4, 30, 1, 1), + SET_QP_INFO(5, 31, 1, 2), + SET_QP_INFO(6, 32, 1, 2), + SET_QP_INFO(7, 33, 1, 3), + SET_QP_INFO(8, 34, 1, 3), + SET_QP_INFO(9, 35, 1, 0), + SET_QP_INFO(10, 36, 1, 0), +}; +#endif + +struct srio_liodn_id_table srio_liodn_tbl[] = { + SET_SRIO_LIODN_1(1, 307), + SET_SRIO_LIODN_1(2, 387), +}; +int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); + +struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(62), + SET_BMAN_LIODN(63), +#endif + + SET_SDHC_LIODN(1, 552), + + SET_USB_LIODN(1, "fsl-usb2-mph", 553), + + SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 148), + + SET_DMA_LIODN(1, 147), + SET_DMA_LIODN(2, 227), + + /* SET_NEXUS_LIODN(557), -- not yet implemented */ + SET_QE_LIODN(559), +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 88), + SET_FMAN_RX_1G_LIODN(1, 1, 89), + SET_FMAN_RX_1G_LIODN(1, 2, 90), + SET_FMAN_RX_1G_LIODN(1, 3, 91), + SET_FMAN_RX_1G_LIODN(1, 4, 92), + SET_FMAN_RX_1G_LIODN(1, 5, 93), +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 454, 458), + SET_SEC_JR_LIODN_ENTRY(1, 455, 459), + SET_SEC_JR_LIODN_ENTRY(2, 456, 460), + SET_SEC_JR_LIODN_ENTRY(3, 457, 461), + SET_SEC_RTIC_LIODN_ENTRY(a, 453), + SET_SEC_RTIC_LIODN_ENTRY(b, 549), + SET_SEC_RTIC_LIODN_ENTRY(c, 550), + SET_SEC_RTIC_LIODN_ENTRY(d, 551), + SET_SEC_DECO_LIODN_ENTRY(0, 541, 610), + SET_SEC_DECO_LIODN_ENTRY(1, 542, 611), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), +#endif +}; diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/t1040_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/t1040_serdes.c new file mode 100644 index 000000000..d86bb2737 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/t1040_serdes.c @@ -0,0 +1,68 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_serdes.h> +#include <asm/processor.h> +#include <asm/io.h> + + +static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { + [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, + PCIE2, PCIE2, PCIE2, PCIE2}, + [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, + PCIE2, PCIE3, PCIE4, SATA1}, + [0x08] = {PCIE1, PCIE1, PCIE1, PCIE1, + PCIE2, PCIE3, SATA2, SATA1}, + [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE2, PCIE2, PCIE2, PCIE2}, + [0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, + PCIE2, PCIE2, PCIE2, PCIE2}, + [0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, + PCIE2, PCIE3, PCIE4, SATA1}, + [0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, + PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, + [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, + PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1}, + [0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE2, PCIE3, PCIE4, SATA1}, + [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, + [0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, + [0x89] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A, + PCIE2, PCIE3, QSGMII_SW1_B, SATA1}, + [0x8D] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A, + PCIE2, QSGMII_SW1_B, QSGMII_SW1_B, QSGMII_SW1_B}, + [0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, + [0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, + [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5}, + [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + return serdes_cfg_tbl[cfg][lane]; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + + if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_cfg_tbl[prtcl][i] != NONE) + return 1; + } + + return 0; +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/t2080_ids.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/t2080_ids.c new file mode 100644 index 000000000..0bfd44738 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/t2080_ids.c @@ -0,0 +1,144 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO(1, 27, 1, 0), + SET_QP_INFO(2, 28, 1, 0), + SET_QP_INFO(3, 29, 1, 1), + SET_QP_INFO(4, 30, 1, 1), + SET_QP_INFO(5, 31, 1, 2), + SET_QP_INFO(6, 32, 1, 2), + SET_QP_INFO(7, 33, 1, 3), + SET_QP_INFO(8, 34, 1, 3), + SET_QP_INFO(9, 35, 1, 0), + SET_QP_INFO(10, 36, 1, 0), + SET_QP_INFO(11, 37, 1, 1), + SET_QP_INFO(12, 38, 1, 1), + SET_QP_INFO(13, 39, 1, 2), + SET_QP_INFO(14, 40, 1, 2), + SET_QP_INFO(15, 41, 1, 3), + SET_QP_INFO(16, 42, 1, 3), + SET_QP_INFO(17, 43, 1, 0), + SET_QP_INFO(18, 44, 1, 0), +}; +#endif + +#ifdef CONFIG_SYS_SRIO +struct srio_liodn_id_table srio_liodn_tbl[] = { + SET_SRIO_LIODN_BASE(1, 307), + SET_SRIO_LIODN_BASE(2, 387), +}; +int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); +#endif + +struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(62), + SET_BMAN_LIODN(63), +#endif + + SET_SDHC_LIODN(1, 552), + + SET_PME_LIODN(117), + + SET_USB_LIODN(1, "fsl-usb2-mph", 553), + SET_USB_LIODN(2, "fsl-usb2-dr", 554), + +#ifdef CONFIG_FSL_SATA_V2 + SET_SATA_LIODN(1, 555), + SET_SATA_LIODN(2, 556), +#endif + + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), + + SET_DMA_LIODN(1, 147), + SET_DMA_LIODN(2, 227), + SET_DMA_LIODN(3, 226), + + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), + SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), + +#ifdef CONFIG_SYS_PMAN + SET_PMAN_LIODN(1, 513), + SET_PMAN_LIODN(2, 514), + SET_PMAN_LIODN(3, 515), +#endif + + /* SET_NEXUS_LIODN(557), -- not yet implemented */ +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 88), + SET_FMAN_RX_1G_LIODN(1, 1, 89), + SET_FMAN_RX_1G_LIODN(1, 2, 90), + SET_FMAN_RX_1G_LIODN(1, 3, 91), + SET_FMAN_RX_1G_LIODN(1, 4, 92), + SET_FMAN_RX_1G_LIODN(1, 5, 93), + SET_FMAN_RX_10G_LIODN(1, 0, 94), + SET_FMAN_RX_10G_LIODN(1, 1, 95), +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 454, 458), + SET_SEC_JR_LIODN_ENTRY(1, 455, 459), + SET_SEC_JR_LIODN_ENTRY(2, 456, 460), + SET_SEC_JR_LIODN_ENTRY(3, 457, 461), + SET_SEC_RTIC_LIODN_ENTRY(a, 453), + SET_SEC_RTIC_LIODN_ENTRY(b, 549), + SET_SEC_RTIC_LIODN_ENTRY(c, 550), + SET_SEC_RTIC_LIODN_ENTRY(d, 551), + SET_SEC_DECO_LIODN_ENTRY(0, 541, 610), + SET_SEC_DECO_LIODN_ENTRY(1, 542, 611), + SET_SEC_DECO_LIODN_ENTRY(2, 543, 612), + SET_SEC_DECO_LIODN_ENTRY(3, 544, 613), + SET_SEC_DECO_LIODN_ENTRY(4, 545, 614), + SET_SEC_DECO_LIODN_ENTRY(5, 546, 615), + SET_SEC_DECO_LIODN_ENTRY(6, 547, 616), + SET_SEC_DECO_LIODN_ENTRY(7, 548, 617), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_RMAN +struct liodn_id_table rman_liodn_tbl[] = { + /* Set RMan block 0-3 liodn offset */ + SET_RMAN_LIODN(0, 6), + SET_RMAN_LIODN(1, 7), + SET_RMAN_LIODN(2, 8), + SET_RMAN_LIODN(3, 9), +}; +int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); +#endif + +struct liodn_id_table liodn_bases[] = { +#ifdef CONFIG_SYS_DPAA_DCE + [FSL_HW_PORTAL_DCE] = SET_LIODN_BASE_2(618, 694), +#endif + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), +#endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(770, 846), +#endif +#ifdef CONFIG_SYS_DPAA_RMAN + [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922), +#endif +}; diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/t2080_serdes.c new file mode 100644 index 000000000..07e27deb1 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/t2080_serdes.c @@ -0,0 +1,207 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Shengzhou Liu <Shengzhou.Liu@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_serdes.h> +#include <asm/processor.h> +#include "fsl_corenet2_serdes.h" + +struct serdes_config { + u32 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static const struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x6E, {XFI_FM1_MAC9, XFI_FM1_MAC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xBC, {PCIE3, PCIE3, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE4, PCIE4, PCIE4} }, + {0xC8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xD6, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xDE, {PCIE3, PCIE3, PCIE3, PCIE3, + PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, + {0xE0, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, + PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xF2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, + {0xF8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, + {0xFA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE1, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x95, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xA2, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x94, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, + XAUI_FM1_MAC9, XAUI_FM1_MAC9, + PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM1_MAC1, XFI_FM1_MAC2, + PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x6D, {XFI_FM1_MAC9, XFI_FM1_MAC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0x71, {XFI_FM1_MAC9, XFI_FM1_MAC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, + SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xA6, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, + PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x8E, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, + PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x8F, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, + PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x82, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x83, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xA4, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0x96, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0x8A, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0x67, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM1_MAC1, XFI_FM1_MAC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0xAB, {PCIE3, PCIE3, PCIE3, PCIE3, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0xDA, {PCIE3, PCIE3, PCIE3, PCIE3, + PCIE3, PCIE3, PCIE3, PCIE3} }, + {0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xCB, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xD8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM1_MAC1, XFI_FM1_MAC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + +#if defined(CONFIG_PPC_T2081) + {0xAA, {PCIE3, PCIE3, PCIE3, PCIE3, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, +#endif + {} +}; + +#ifndef CONFIG_PPC_T2081 +static const struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, + {0x16, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} }, + {0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, + {0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, + {0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, + {0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} }, + {0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} }, + {0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, + {0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} }, + {} +}; +#endif + +static const struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, +#ifndef CONFIG_PPC_T2081 + serdes2_cfg_tbl, +#endif +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + const struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + const struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/t4240_ids.c new file mode 100644 index 000000000..1a3cb3398 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -0,0 +1,189 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO(1, 27, 1, 0), + SET_QP_INFO(2, 28, 1, 0), + SET_QP_INFO(3, 29, 1, 1), + SET_QP_INFO(4, 30, 1, 1), + SET_QP_INFO(5, 31, 1, 2), + SET_QP_INFO(6, 32, 1, 2), + SET_QP_INFO(7, 33, 1, 3), + SET_QP_INFO(8, 34, 1, 3), + SET_QP_INFO(9, 35, 1, 4), + SET_QP_INFO(10, 36, 1, 4), + SET_QP_INFO(11, 37, 1, 5), + SET_QP_INFO(12, 38, 1, 5), + SET_QP_INFO(13, 39, 1, 6), + SET_QP_INFO(14, 40, 1, 6), + SET_QP_INFO(15, 41, 1, 7), + SET_QP_INFO(16, 42, 1, 7), + SET_QP_INFO(17, 43, 1, 8), + SET_QP_INFO(18, 44, 1, 8), + SET_QP_INFO(19, 45, 1, 9), + SET_QP_INFO(20, 46, 1, 9), + SET_QP_INFO(21, 47, 1, 10), + SET_QP_INFO(22, 48, 1, 10), + SET_QP_INFO(23, 49, 1, 11), + SET_QP_INFO(24, 50, 1, 11), + SET_QP_INFO(65, 89, 1, 0), + SET_QP_INFO(66, 90, 1, 0), + SET_QP_INFO(67, 91, 1, 1), + SET_QP_INFO(68, 92, 1, 1), + SET_QP_INFO(69, 93, 1, 2), + SET_QP_INFO(70, 94, 1, 2), + SET_QP_INFO(71, 95, 1, 3), + SET_QP_INFO(72, 96, 1, 3), + SET_QP_INFO(73, 97, 1, 4), + SET_QP_INFO(74, 98, 1, 4), + SET_QP_INFO(75, 99, 1, 5), + SET_QP_INFO(76, 100, 1, 5), + SET_QP_INFO(77, 101, 1, 6), + SET_QP_INFO(78, 102, 1, 6), + SET_QP_INFO(79, 103, 1, 7), + SET_QP_INFO(80, 104, 1, 7), + SET_QP_INFO(81, 105, 1, 8), + SET_QP_INFO(82, 106, 1, 8), + SET_QP_INFO(83, 107, 1, 9), + SET_QP_INFO(84, 108, 1, 9), + SET_QP_INFO(85, 109, 1, 10), + SET_QP_INFO(86, 110, 1, 10), + SET_QP_INFO(87, 111, 1, 11), + SET_QP_INFO(88, 112, 1, 11), + SET_QP_INFO(25, 51, 1, 0), + SET_QP_INFO(26, 52, 1, 0), +}; +#endif + +#ifdef CONFIG_SYS_SRIO +struct srio_liodn_id_table srio_liodn_tbl[] = { + SET_SRIO_LIODN_BASE(1, 307), + SET_SRIO_LIODN_BASE(2, 387), +}; +int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); +#endif + +struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(62), + SET_BMAN_LIODN(63), +#endif + + SET_SDHC_LIODN(1, 552), + + SET_PME_LIODN(117), + + SET_USB_LIODN(1, "fsl-usb2-mph", 553), + SET_USB_LIODN(2, "fsl-usb2-dr", 554), + + SET_SATA_LIODN(1, 555), + SET_SATA_LIODN(2, 556), + + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), + + SET_DMA_LIODN(1, 147), + SET_DMA_LIODN(2, 227), + + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), + SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), + +#ifdef CONFIG_SYS_PMAN + SET_PMAN_LIODN(1, 513), + SET_PMAN_LIODN(2, 514), + SET_PMAN_LIODN(3, 515), +#endif + + /* SET_NEXUS_LIODN(557), -- not yet implemented */ +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 88), + SET_FMAN_RX_1G_LIODN(1, 1, 89), + SET_FMAN_RX_1G_LIODN(1, 2, 90), + SET_FMAN_RX_1G_LIODN(1, 3, 91), + SET_FMAN_RX_1G_LIODN(1, 4, 92), + SET_FMAN_RX_1G_LIODN(1, 5, 93), + SET_FMAN_RX_10G_LIODN(1, 0, 94), + SET_FMAN_RX_10G_LIODN(1, 1, 95), +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +#if (CONFIG_SYS_NUM_FMAN == 2) +struct liodn_id_table fman2_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(2, 0, 88), + SET_FMAN_RX_1G_LIODN(2, 1, 89), + SET_FMAN_RX_1G_LIODN(2, 2, 90), + SET_FMAN_RX_1G_LIODN(2, 3, 91), + SET_FMAN_RX_1G_LIODN(2, 4, 92), + SET_FMAN_RX_1G_LIODN(2, 5, 93), + SET_FMAN_RX_10G_LIODN(2, 0, 94), + SET_FMAN_RX_10G_LIODN(2, 1, 95), +}; +int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl); +#endif +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 454, 458), + SET_SEC_JR_LIODN_ENTRY(1, 455, 459), + SET_SEC_JR_LIODN_ENTRY(2, 456, 460), + SET_SEC_JR_LIODN_ENTRY(3, 457, 461), + SET_SEC_RTIC_LIODN_ENTRY(a, 453), + SET_SEC_RTIC_LIODN_ENTRY(b, 549), + SET_SEC_RTIC_LIODN_ENTRY(c, 550), + SET_SEC_RTIC_LIODN_ENTRY(d, 551), + SET_SEC_DECO_LIODN_ENTRY(0, 541, 610), + SET_SEC_DECO_LIODN_ENTRY(1, 542, 611), + SET_SEC_DECO_LIODN_ENTRY(2, 543, 612), + SET_SEC_DECO_LIODN_ENTRY(3, 544, 613), + SET_SEC_DECO_LIODN_ENTRY(4, 545, 614), + SET_SEC_DECO_LIODN_ENTRY(5, 546, 615), + SET_SEC_DECO_LIODN_ENTRY(6, 547, 616), + SET_SEC_DECO_LIODN_ENTRY(7, 548, 617), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_RMAN +struct liodn_id_table rman_liodn_tbl[] = { + /* Set RMan block 0-3 liodn offset */ + SET_RMAN_LIODN(0, 6), + SET_RMAN_LIODN(1, 7), + SET_RMAN_LIODN(2, 8), + SET_RMAN_LIODN(3, 9), +}; +int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); +#endif + +struct liodn_id_table liodn_bases[] = { +#ifdef CONFIG_SYS_DPAA_DCE + [FSL_HW_PORTAL_DCE] = SET_LIODN_BASE_2(618, 694), +#endif + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), +#if (CONFIG_SYS_NUM_FMAN == 2) + [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(1069), +#endif +#endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(770, 846), +#endif +#ifdef CONFIG_SYS_DPAA_RMAN + [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922), +#endif +}; diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/t4240_serdes.c new file mode 100644 index 000000000..1f99a0a89 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -0,0 +1,353 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_serdes.h> +#include <asm/processor.h> +#include <asm/io.h> +#include "fsl_corenet2_serdes.h" + +struct serdes_config { + u32 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +#ifdef CONFIG_PPC_T4240 +static const struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, + XAUI_FM1_MAC9, XAUI_FM1_MAC9, + XAUI_FM1_MAC10, XAUI_FM1_MAC10, + XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, + {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, + HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}}, + {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, + HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}}, + {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}}, + {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}}, + {38, {NONE, NONE, QSGMII_FM1_B, NONE, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {} +}; +static const struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC10, XAUI_FM2_MAC10, + XAUI_FM2_MAC10, XAUI_FM2_MAC10}}, + {2, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC10, HIGIG_FM2_MAC10, + HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}}, + {4, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC10, HIGIG_FM2_MAC10, + HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}}, + {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {14, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {23, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {38, {NONE, NONE, QSGMII_FM2_B, NONE, + NONE, NONE, QSGMII_FM2_A, NONE} }, + {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, + {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, + {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, + {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, + {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, + {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, QSGMII_FM2_A, NONE} }, + {56, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM2_MAC10, XFI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {57, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM2_MAC10, XFI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {} +}; +static const struct serdes_config serdes3_cfg_tbl[] = { + /* SerDes 3 */ + {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}}, + {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}}, + {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}}, + {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}}, + {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}}, + {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}}, + {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2}}, + {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2}}, + {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {} +}; +static const struct serdes_config serdes4_cfg_tbl[] = { + /* SerDes 4 */ + {2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}}, + {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}}, + {6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}}, + {8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}}, + {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} }, + {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} }, + {14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}}, + {16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}}, + {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}}, + {} +}; +#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080) +static const struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, + XAUI_FM1_MAC9, XAUI_FM1_MAC9, + XAUI_FM1_MAC10, XAUI_FM1_MAC10, + XAUI_FM1_MAC10, XAUI_FM1_MAC10} }, + {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, + HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} }, + {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, + HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} }, + {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, + {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, + {38, {NONE, NONE, QSGMII_FM1_B, NONE, + NONE, NONE, QSGMII_FM1_A, NONE} }, + {} +}; +static const struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + NONE, NONE} }, + {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {38, {NONE, NONE, QSGMII_FM2_B, NONE, + NONE, QSGMII_FM1_A, NONE, NONE} }, + {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, QSGMII_FM1_A, NONE, NONE} }, + {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, QSGMII_FM1_A, NONE, NONE} }, + {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, QSGMII_FM1_A, NONE, NONE} }, + {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + NONE, NONE, NONE, NONE} }, + {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, NONE, NONE} }, + {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, NONE, NONE} }, + {56, {NONE, XFI_FM1_MAC10, + XFI_FM2_MAC10, NONE, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, + {57, {NONE, XFI_FM1_MAC10, + XFI_FM2_MAC10, NONE, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + NONE, NONE} }, + {} +}; +static const struct serdes_config serdes3_cfg_tbl[] = { + /* SerDes 3 */ + {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, + {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, + {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, + {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} }, + {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} }, + {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} }, + {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2} }, + {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2} }, + {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1} }, + {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1} }, + {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1} }, + {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + NONE, NONE, NONE, NONE} }, + {} +}; +static const struct serdes_config serdes4_cfg_tbl[] = { + /* SerDes 4 */ + {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} }, + {6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, + {8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} }, + {10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} }, + {12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} }, + {14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, + {16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} }, + {18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} }, + {} +} +; +#else +#error "Need to define SerDes protocol" +#endif +static const struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, + serdes2_cfg_tbl, + serdes3_cfg_tbl, + serdes4_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + const struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + const struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/tlb.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/tlb.c new file mode 100644 index 000000000..129ec662f --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/tlb.c @@ -0,0 +1,346 @@ +/* + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#ifdef CONFIG_ADDR_MAP +#include <addr_map.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +void invalidate_tlb(u8 tlb) +{ + if (tlb == 0) + mtspr(MMUCSR0, 0x4); + if (tlb == 1) + mtspr(MMUCSR0, 0x2); +} + +__weak void init_tlbs(void) +{ + int i; + + for (i = 0; i < num_tlb_entries; i++) { + write_tlb(tlb_table[i].mas0, + tlb_table[i].mas1, + tlb_table[i].mas2, + tlb_table[i].mas3, + tlb_table[i].mas7); + } + + return ; +} + +#if !defined(CONFIG_NAND_SPL) && \ + (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL)) +void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, + phys_addr_t *rpn) +{ + u32 _mas1; + + mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0)); + asm volatile("tlbre;isync"); + _mas1 = mfspr(MAS1); + + *valid = (_mas1 & MAS1_VALID); + *tsize = (_mas1 >> 7) & 0x1f; + *epn = mfspr(MAS2) & MAS2_EPN; + *rpn = mfspr(MAS3) & MAS3_RPN; +#ifdef CONFIG_ENABLE_36BIT_PHYS + *rpn |= ((u64)mfspr(MAS7)) << 32; +#endif +} + +void print_tlbcam(void) +{ + int i; + unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; + + /* walk all the entries */ + printf("TLBCAM entries\n"); + for (i = 0; i < num_cam; i++) { + unsigned long epn; + u32 tsize, valid; + phys_addr_t rpn; + + read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn); + printf("entry %02d: V: %d EPN 0x%08x RPN 0x%08llx size:", + i, (valid == 0) ? 0 : 1, (unsigned int)epn, + (unsigned long long)rpn); + print_size(TSIZE_TO_BYTES(tsize), "\n"); + } +} + +static inline void use_tlb_cam(u8 idx) +{ + int i = idx / 32; + int bit = idx % 32; + + gd->arch.used_tlb_cams[i] |= (1 << bit); +} + +static inline void free_tlb_cam(u8 idx) +{ + int i = idx / 32; + int bit = idx % 32; + + gd->arch.used_tlb_cams[i] &= ~(1 << bit); +} + +void init_used_tlb_cams(void) +{ + int i; + unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; + + for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) + gd->arch.used_tlb_cams[i] = 0; + + /* walk all the entries */ + for (i = 0; i < num_cam; i++) { + mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0)); + asm volatile("tlbre;isync"); + if (mfspr(MAS1) & MAS1_VALID) + use_tlb_cam(i); + } +} + +int find_free_tlbcam(void) +{ + int i; + u32 idx; + + for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) { + idx = ffz(gd->arch.used_tlb_cams[i]); + + if (idx != 32) + break; + } + + idx += i * 32; + + if (idx >= CONFIG_SYS_NUM_TLBCAMS) + return -1; + + return idx; +} + +void set_tlb(u8 tlb, u32 epn, u64 rpn, + u8 perms, u8 wimge, + u8 ts, u8 esel, u8 tsize, u8 iprot) +{ + u32 _mas0, _mas1, _mas2, _mas3, _mas7; + + if (tlb == 1) + use_tlb_cam(esel); + + if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1 && + tsize & 1) { + printf("%s: bad tsize %d on entry %d at 0x%08x\n", + __func__, tsize, tlb, epn); + return; + } + + _mas0 = FSL_BOOKE_MAS0(tlb, esel, 0); + _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize); + _mas2 = FSL_BOOKE_MAS2(epn, wimge); + _mas3 = FSL_BOOKE_MAS3(rpn, 0, perms); + _mas7 = FSL_BOOKE_MAS7(rpn); + + write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7); + +#ifdef CONFIG_ADDR_MAP + if ((tlb == 1) && (gd->flags & GD_FLG_RELOC)) + addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), esel); +#endif +} + +void disable_tlb(u8 esel) +{ + u32 _mas0, _mas1, _mas2, _mas3; + + free_tlb_cam(esel); + + _mas0 = FSL_BOOKE_MAS0(1, esel, 0); + _mas1 = 0; + _mas2 = 0; + _mas3 = 0; + + mtspr(MAS0, _mas0); + mtspr(MAS1, _mas1); + mtspr(MAS2, _mas2); + mtspr(MAS3, _mas3); +#ifdef CONFIG_ENABLE_36BIT_PHYS + mtspr(MAS7, 0); +#endif + asm volatile("isync;msync;tlbwe;isync"); + +#ifdef CONFIG_ADDR_MAP + if (gd->flags & GD_FLG_RELOC) + addrmap_set_entry(0, 0, 0, esel); +#endif +} + +static void tlbsx (const volatile unsigned *addr) +{ + __asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr)); +} + +/* return -1 if we didn't find anything */ +int find_tlb_idx(void *addr, u8 tlbsel) +{ + u32 _mas0, _mas1; + + /* zero out Search PID, AS */ + mtspr(MAS6, 0); + + tlbsx(addr); + + _mas0 = mfspr(MAS0); + _mas1 = mfspr(MAS1); + + /* we found something, and its in the TLB we expect */ + if ((MAS1_VALID & _mas1) && + (MAS0_TLBSEL(tlbsel) == (_mas0 & MAS0_TLBSEL_MSK))) { + return ((_mas0 & MAS0_ESEL_MSK) >> 16); + } + + return -1; +} + +#ifdef CONFIG_ADDR_MAP +void init_addr_map(void) +{ + int i; + unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; + + /* walk all the entries */ + for (i = 0; i < num_cam; i++) { + unsigned long epn; + u32 tsize, valid; + phys_addr_t rpn; + + read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn); + if (valid & MAS1_VALID) + addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i); + } + + return ; +} +#endif + +uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size, + enum tlb_map_type map_type) +{ + int i; + unsigned int tlb_size; + unsigned int wimge; + unsigned int perm; + unsigned int max_cam, tsize_mask; + + if (map_type == TLB_MAP_RAM) { + perm = MAS3_SX|MAS3_SW|MAS3_SR; + wimge = MAS2_M; +#ifdef CONFIG_SYS_PPC_DDR_WIMGE + wimge = CONFIG_SYS_PPC_DDR_WIMGE; +#endif + } else { + perm = MAS3_SW|MAS3_SR; + wimge = MAS2_I|MAS2_G; + } + + if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) { + /* Convert (4^max) kB to (2^max) bytes */ + max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10; + tsize_mask = ~1U; + } else { + /* Convert (2^max) kB to (2^max) bytes */ + max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10; + tsize_mask = ~0U; + } + + for (i = 0; size && i < 8; i++) { + int tlb_index = find_free_tlbcam(); + u32 camsize = __ilog2_u64(size) & tsize_mask; + u32 align = __ilog2(v_addr) & tsize_mask; + + if (tlb_index == -1) + break; + + if (align == -2) align = max_cam; + if (camsize > align) + camsize = align; + + if (camsize > max_cam) + camsize = max_cam; + + tlb_size = camsize - 10; + + set_tlb(1, v_addr, p_addr, perm, wimge, + 0, tlb_index, tlb_size, 1); + + size -= 1ULL << camsize; + v_addr += 1UL << camsize; + p_addr += 1UL << camsize; + } + + return size; +} + +unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, + unsigned int memsize_in_meg) +{ + unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; + u64 memsize = (u64)memsize_in_meg << 20; + + memsize = min(memsize, CONFIG_MAX_MEM_MAPPED); + memsize = tlb_map_range(ram_tlb_address, p_addr, memsize, TLB_MAP_RAM); + + if (memsize) + print_size(memsize, " left unmapped\n"); + + return memsize_in_meg; +} + +unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) +{ + return + setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); +} + +/* Invalidate the DDR TLBs for the requested size */ +void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) +{ + u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; + unsigned long epn; + u32 tsize, valid, ptr; + phys_addr_t rpn = 0; + int ddr_esel; + u64 memsize = (u64)memsize_in_meg << 20; + + ptr = vstart; + + while (ptr < (vstart + memsize)) { + ddr_esel = find_tlb_idx((void *)ptr, 1); + if (ddr_esel != -1) { + read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn); + disable_tlb(ddr_esel); + } + ptr += TSIZE_TO_BYTES(tsize); + } +} + +void clear_ddr_tlbs(unsigned int memsize_in_meg) +{ + clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); +} + + +#endif /* not SPL */ diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/traps.c b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/traps.c new file mode 100644 index 000000000..24adbc307 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/traps.c @@ -0,0 +1,296 @@ +/* + * linux/arch/powerpc/kernel/traps.c + * + * Copyright 2007 Freescale Semiconductor. + * Copyright (C) 2003 Motorola + * Modified by Xianghua Xiao(x.xiao@motorola.com) + * + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modified by Cort Dougan (cort@cs.nmt.edu) + * and Paul Mackerras (paulus@cs.anu.edu.au) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This file handles the architecture-dependent parts of hardware exceptions + */ + +#include <common.h> +#include <command.h> +#include <kgdb.h> +#include <asm/processor.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Returns 0 if exception not found and fixup otherwise. */ +extern unsigned long search_exception_table(unsigned long); + +/* + * End of addressable memory. This may be less than the actual + * amount of memory on the system if we're unable to keep all + * the memory mapped in. + */ +#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) + +static __inline__ void set_tsr(unsigned long val) +{ + asm volatile("mtspr 0x150, %0" : : "r" (val)); +} + +static __inline__ unsigned long get_esr(void) +{ + unsigned long val; + asm volatile("mfspr %0, 0x03e" : "=r" (val) :); + return val; +} + +#define ESR_MCI 0x80000000 +#define ESR_PIL 0x08000000 +#define ESR_PPR 0x04000000 +#define ESR_PTR 0x02000000 +#define ESR_DST 0x00800000 +#define ESR_DIZ 0x00400000 +#define ESR_U0F 0x00008000 + +#if defined(CONFIG_CMD_BEDBUG) +extern void do_bedbug_breakpoint(struct pt_regs *); +#endif + +/* + * Trap & Exception support + */ + +static void print_backtrace(unsigned long *sp) +{ + int cnt = 0; + unsigned long i; + + printf("Call backtrace: "); + while (sp) { + if ((uint)sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + printf("\n"); + printf("%08lX ", i); + if (cnt > 32) break; + sp = (unsigned long *)*sp; + } + printf("\n"); +} + +void show_regs(struct pt_regs *regs) +{ + int i; + + printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", + regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); + printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", + regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, + regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, + regs->msr&MSR_IR ? 1 : 0, + regs->msr&MSR_DR ? 1 : 0); + + printf("\n"); + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) + { + printf("GPR%02d: ", i); + } + + printf("%08lX ", regs->gpr[i]); + if ((i % 8) == 7) + { + printf("\n"); + } + } +} + + +static void _exception(int signr, struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Exception in kernel pc %lx signal %d",regs->nip,signr); +} + +void CritcalInputException(struct pt_regs *regs) +{ + panic("Critical Input Exception"); +} + +int machinecheck_count = 0; +int machinecheck_error = 0; +void MachineCheckException(struct pt_regs *regs) +{ + unsigned long fixup; + unsigned int mcsr, mcsrr0, mcsrr1, mcar; + + /* Probing PCI using config cycles cause this exception + * when a device is not present. Catch it and return to + * the PCI exception handler. + */ + if ((fixup = search_exception_table(regs->nip)) != 0) { + regs->nip = fixup; + return; + } + + mcsrr0 = mfspr(SPRN_MCSRR0); + mcsrr1 = mfspr(SPRN_MCSRR1); + mcsr = mfspr(SPRN_MCSR); + mcar = mfspr(SPRN_MCAR); + + machinecheck_count++; + machinecheck_error=1; + +#if defined(CONFIG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + printf("Machine check in kernel mode.\n"); + printf("Caused by (from mcsr): "); + printf("mcsr = 0x%08x\n", mcsr); + if (mcsr & 0x80000000) + printf("Machine check input pin\n"); + if (mcsr & 0x40000000) + printf("Instruction cache parity error\n"); + if (mcsr & 0x20000000) + printf("Data cache push parity error\n"); + if (mcsr & 0x10000000) + printf("Data cache parity error\n"); + if (mcsr & 0x00000080) + printf("Bus instruction address error\n"); + if (mcsr & 0x00000040) + printf("Bus Read address error\n"); + if (mcsr & 0x00000020) + printf("Bus Write address error\n"); + if (mcsr & 0x00000010) + printf("Bus Instruction data bus error\n"); + if (mcsr & 0x00000008) + printf("Bus Read data bus error\n"); + if (mcsr & 0x00000004) + printf("Bus Write bus error\n"); + if (mcsr & 0x00000002) + printf("Bus Instruction parity error\n"); + if (mcsr & 0x00000001) + printf("Bus Read parity error\n"); + + show_regs(regs); + printf("MCSR=0x%08x \tMCSRR0=0x%08x \nMCSRR1=0x%08x \tMCAR=0x%08x\n", + mcsr, mcsrr0, mcsrr1, mcar); + print_backtrace((unsigned long *)regs->gpr[1]); + if (machinecheck_count > 10) { + panic("machine check count too high\n"); + } + + if (machinecheck_count > 1) { + regs->nip += 4; /* skip offending instruction */ + printf("Skipping current instr, Returning to 0x%08lx\n", + regs->nip); + } else { + printf("Returning back to 0x%08lx\n",regs->nip); + } +} + +void AlignmentException(struct pt_regs *regs) +{ +#if defined(CONFIG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Alignment Exception"); +} + +void ProgramCheckException(struct pt_regs *regs) +{ + long esr_val; + +#if defined(CONFIG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + show_regs(regs); + + esr_val = get_esr(); + if( esr_val & ESR_PIL ) + printf( "** Illegal Instruction **\n" ); + else if( esr_val & ESR_PPR ) + printf( "** Privileged Instruction **\n" ); + else if( esr_val & ESR_PTR ) + printf( "** Trap Instruction **\n" ); + + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Program Check Exception"); +} + +void PITException(struct pt_regs *regs) +{ + /* + * Reset PIT interrupt + */ + set_tsr(0x0c000000); + + /* + * Call timer_interrupt routine in interrupts.c + */ + timer_interrupt(NULL); +} + +void UnknownException(struct pt_regs *regs) +{ +#if defined(CONFIG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + regs->nip, regs->msr, regs->trap); + _exception(0, regs); +} + +void ExtIntException(struct pt_regs *regs) +{ + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); + + uint vect; + +#if defined(CONFIG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + printf("External Interrupt Exception at PC: %lx, SR: %lx, vector=%lx", + regs->nip, regs->msr, regs->trap); + vect = pic->iack0; + printf(" irq IACK0@%05x=%d\n",(int)&pic->iack0,vect); + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); +} + +void DebugException(struct pt_regs *regs) +{ + printf("Debugger trap at @ %lx\n", regs->nip ); + show_regs(regs); +#if defined(CONFIG_CMD_BEDBUG) + do_bedbug_breakpoint( regs ); +#endif +} + +/* Probe an address by reading. If not present, return -1, otherwise + * return 0. + */ +int addr_probe(uint *addr) +{ + return 0; +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds new file mode 100644 index 000000000..f933b2194 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds @@ -0,0 +1,98 @@ +/* + * Copyright 2009-2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "config.h" + +#ifndef CONFIG_SYS_MONITOR_LEN +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .text : + { + *(.text*) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } :text + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + _GOT2_TABLE_ = .; + KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); + _FIXUP_TABLE_ = .; + KEEP(*(.fixup)) + } + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data*) + *(.sdata*) + } + _edata = .; + PROVIDE (edata = .); + + . = .; + + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg ADDR(.text) - 0x1000 : + { + KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) + } :text = 0xffff + + . = ADDR(.text) + CONFIG_SYS_MONITOR_LEN; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss*) + *(.bss*) + *(COMMON) + } :bss + + . = ALIGN(4); + __bss_end = . ; + PROVIDE (end = .); +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds new file mode 100644 index 000000000..b83c55388 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds @@ -0,0 +1,69 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de + * + * Copyright 2009 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "config.h" + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + . = 0xfff00000; + .text : { + *(.text*) + } + _etext = .; + + .reloc : { + _GOT2_TABLE_ = .; + KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); + _FIXUP_TABLE_ = .; + KEEP(*(.fixup)) + } + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + . = ALIGN(8); + .data : { + *(.rodata*) + *(.data*) + *(.sdata*) + } + _edata = .; + + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(8); + __init_begin = .; + __init_end = .; +#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ + .bootpg ADDR(.text) + 0x1000 : + { + start.o (.bootpg) + } +#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */ +#elif defined(CONFIG_FSL_ELBC) +#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */ +#else +#error unknown NAND controller +#endif + .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : { + KEEP(*(.resetvec)) + } = 0xffff + + __bss_start = .; + .bss : { + *(.sbss*) + *(.bss*) + } + __bss_end = .; +} +ASSERT(__init_end <= (0xfff00000 + RESET_VECTOR_OFFSET), "NAND bootstrap too big"); diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds new file mode 100644 index 000000000..5ae7b3eed --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de + * + * Copyright 2009 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "config.h" + +OUTPUT_ARCH(powerpc) +#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} +#endif +SECTIONS +{ + . = CONFIG_SPL_TEXT_BASE; + .text : { + *(.text*) + } + _etext = .; + + .reloc : { + _GOT2_TABLE_ = .; + KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); + _FIXUP_TABLE_ = .; + KEEP(*(.fixup)) + } + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + . = ALIGN(8); + .data : { + *(.rodata*) + *(.data*) + *(.sdata*) + } + _edata = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(8); + __init_begin = .; + __init_end = .; +#ifdef CONFIG_SPL_SKIP_RELOCATE + . = ALIGN(4); + __bss_start = .; + .bss : { + *(.sbss*) + *(.bss*) + } + . = ALIGN(4); + __bss_end = .; +#endif + +/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */ +#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC + .bootpg ADDR(.text) - 0x1000 : + { + KEEP(*(.bootpg)) + } :text = 0xffff +#else +#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ +#ifndef BOOT_PAGE_OFFSET +#define BOOT_PAGE_OFFSET 0x1000 +#endif + .bootpg ADDR(.text) + BOOT_PAGE_OFFSET : + { + arch/powerpc/cpu/mpc85xx/start.o (.bootpg) + } +#ifndef RESET_VECTOR_OFFSET +#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */ +#endif +#elif defined(CONFIG_FSL_ELBC) +#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */ +#else +#error unknown NAND controller +#endif + .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : { + KEEP(*(.resetvec)) + } = 0xffff +#endif + +#ifndef CONFIG_SPL_SKIP_RELOCATE + /* + * Make sure that the bss segment isn't linked at 0x0, otherwise its + * address won't be updated during relocation fixups. + */ + . |= 0x10; + + . = ALIGN(4); + __bss_start = .; + .bss : { + *(.sbss*) + *(.bss*) + } + . = ALIGN(4); + __bss_end = .; +#endif +} diff --git a/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/u-boot.lds b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/u-boot.lds new file mode 100644 index 000000000..2cf0b2595 --- /dev/null +++ b/qemu/roms/u-boot/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -0,0 +1,129 @@ +/* + * Copyright 2007-2009, 2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "config.h" + +#ifdef CONFIG_RESET_VECTOR_ADDRESS +#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS +#else +#define RESET_VECTOR_ADDRESS 0xfffffffc +#endif + +#ifndef CONFIG_SYS_MONITOR_LEN +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif + +OUTPUT_ARCH(powerpc) +ENTRY(_start_e500) + +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .text : + { + *(.text*) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } :text + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + _GOT2_TABLE_ = .; + KEEP(*(.got2)) + KEEP(*(.got)) + PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); + _FIXUP_TABLE_ = .; + KEEP(*(.fixup)) + } + __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data*) + *(.sdata*) + } + _edata = .; + PROVIDE (edata = .); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + +#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC + .bootpg ADDR(.text) - 0x1000 : + { + KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) + } :text = 0xffff + . = ADDR(.text) + CONFIG_SYS_MONITOR_LEN; +#else + .bootpg RESET_VECTOR_ADDRESS - 0xffc : + { + arch/powerpc/cpu/mpc85xx/start.o (.bootpg) + } :text = 0xffff + + .resetvec RESET_VECTOR_ADDRESS : + { + KEEP(*(.resetvec)) + } :text = 0xffff + + . = RESET_VECTOR_ADDRESS + 0x4; + + /* + * Make sure that the bss segment isn't linked at 0x0, otherwise its + * address won't be updated during relocation fixups. Note that + * this is a temporary fix. Code to dynamically the fixup the bss + * location will be added in the future. When the bss relocation + * fixup code is present this workaround should be removed. + */ +#if (RESET_VECTOR_ADDRESS == 0xfffffffc) + . |= 0x10; +#endif +#endif + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss*) + *(.bss*) + *(COMMON) + } :bss + + . = ALIGN(4); + __bss_end = . ; + PROVIDE (end = .); +} |