diff options
Diffstat (limited to 'qemu/roms/u-boot/arch/nios2/include/asm')
23 files changed, 1048 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/bitops.h b/qemu/roms/u-boot/arch/nios2/include/asm/bitops.h new file mode 100644 index 000000000..3e17964f2 --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/bitops.h @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_NIOS2_BITOPS_H_ +#define __ASM_NIOS2_BITOPS_H_ + +/* copied from linux-2.6/include/asm-generic/bitops */ +#include <asm/bitops/atomic.h> +#include <asm/bitops/non-atomic.h> +#include <asm/bitops/ffs.h> + +#endif /* __ASM_NIOS2_BITOPS_H */ diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/bitops/atomic.h b/qemu/roms/u-boot/arch/nios2/include/asm/bitops/atomic.h new file mode 100644 index 000000000..c8946465e --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/bitops/atomic.h @@ -0,0 +1,189 @@ +#ifndef _ASM_GENERIC_BITOPS_ATOMIC_H_ +#define _ASM_GENERIC_BITOPS_ATOMIC_H_ + +#include <asm/types.h> +#include <asm/system.h> + +#ifdef CONFIG_SMP +#include <asm/spinlock.h> +#include <asm/cache.h> /* we use L1_CACHE_BYTES */ + +/* Use an array of spinlocks for our atomic_ts. + * Hash function to index into a different SPINLOCK. + * Since "a" is usually an address, use one spinlock per cacheline. + */ +# define ATOMIC_HASH_SIZE 4 +# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ])) + +extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned; + +/* Can't use raw_spin_lock_irq because of #include problems, so + * this is the substitute */ +#define _atomic_spin_lock_irqsave(l,f) do { \ + raw_spinlock_t *s = ATOMIC_HASH(l); \ + local_irq_save(f); \ + __raw_spin_lock(s); \ +} while(0) + +#define _atomic_spin_unlock_irqrestore(l,f) do { \ + raw_spinlock_t *s = ATOMIC_HASH(l); \ + __raw_spin_unlock(s); \ + local_irq_restore(f); \ +} while(0) + + +#else +# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0) +# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0) +#endif + +/* + * NMI events can occur at any time, including when interrupts have been + * disabled by *_irqsave(). So you can get NMI events occurring while a + * *_bit function is holding a spin lock. If the NMI handler also wants + * to do bit manipulation (and they do) then you can get a deadlock + * between the original caller of *_bit() and the NMI handler. + * + * by Keith Owens + */ + +/** + * set_bit - Atomically set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * This function is atomic and may not be reordered. See __set_bit() + * if you do not require the atomic guarantees. + * + * Note: there are no guarantees that this function will not be reordered + * on non x86 architectures, so if you are writing portable code, + * make sure not to rely on its reordering guarantees. + * + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + *p |= mask; + _atomic_spin_unlock_irqrestore(p, flags); +} + +/** + * clear_bit - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * clear_bit() is atomic and may not be reordered. However, it does + * not contain a memory barrier, so if it is used for locking purposes, + * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() + * in order to ensure changes are visible on other processors. + */ +static inline void clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + *p &= ~mask; + _atomic_spin_unlock_irqrestore(p, flags); +} + +/** + * change_bit - Toggle a bit in memory + * @nr: Bit to change + * @addr: Address to start counting from + * + * change_bit() is atomic and may not be reordered. It may be + * reordered on other architectures than x86. + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void change_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + *p ^= mask; + _atomic_spin_unlock_irqrestore(p, flags); +} + +/** + * test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It may be reordered on other architectures than x86. + * It also implies a memory barrier. + */ +static inline int test_and_set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + old = *p; + *p = old | mask; + _atomic_spin_unlock_irqrestore(p, flags); + + return (old & mask) != 0; +} + +/** + * test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It can be reorderdered on other architectures other than x86. + * It also implies a memory barrier. + */ +static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + old = *p; + *p = old & ~mask; + _atomic_spin_unlock_irqrestore(p, flags); + + return (old & mask) != 0; +} + +/** + * test_and_change_bit - Change a bit and return its old value + * @nr: Bit to change + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +static inline int test_and_change_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + old = *p; + *p = old ^ mask; + _atomic_spin_unlock_irqrestore(p, flags); + + return (old & mask) != 0; +} + +#endif /* _ASM_GENERIC_BITOPS_ATOMIC_H */ diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/bitops/ffs.h b/qemu/roms/u-boot/arch/nios2/include/asm/bitops/ffs.h new file mode 100644 index 000000000..fbbb43af7 --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/bitops/ffs.h @@ -0,0 +1,41 @@ +#ifndef _ASM_GENERIC_BITOPS_FFS_H_ +#define _ASM_GENERIC_BITOPS_FFS_H_ + +/** + * ffs - find first bit set + * @x: the word to search + * + * This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ +static inline int ffs(int x) +{ + int r = 1; + + if (!x) + return 0; + if (!(x & 0xffff)) { + x >>= 16; + r += 16; + } + if (!(x & 0xff)) { + x >>= 8; + r += 8; + } + if (!(x & 0xf)) { + x >>= 4; + r += 4; + } + if (!(x & 3)) { + x >>= 2; + r += 2; + } + if (!(x & 1)) { + x >>= 1; + r += 1; + } + return r; +} + +#endif /* _ASM_GENERIC_BITOPS_FFS_H_ */ diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/bitops/non-atomic.h b/qemu/roms/u-boot/arch/nios2/include/asm/bitops/non-atomic.h new file mode 100644 index 000000000..697cc2b7e --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/bitops/non-atomic.h @@ -0,0 +1,108 @@ +#ifndef _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ +#define _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ + +#include <asm/types.h> + +/** + * __set_bit - Set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Unlike set_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +static inline void __set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p |= mask; +} + +static inline void __clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p &= ~mask; +} + +/** + * __change_bit - Toggle a bit in memory + * @nr: the bit to change + * @addr: the address to start counting from + * + * Unlike change_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +static inline void __change_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p ^= mask; +} + +/** + * __test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static inline int __test_and_set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old | mask; + return (old & mask) != 0; +} + +/** + * __test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old & ~mask; + return (old & mask) != 0; +} + +/* WARNING: non atomic and it can be reordered! */ +static inline int __test_and_change_bit(int nr, + volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old ^ mask; + return (old & mask) != 0; +} + +/** + * test_bit - Determine whether a bit is set + * @nr: bit number to test + * @addr: Address to start counting from + */ +static inline int test_bit(int nr, const volatile unsigned long *addr) +{ + return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); +} + +#endif /* _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ */ diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/byteorder.h b/qemu/roms/u-boot/arch/nios2/include/asm/byteorder.h new file mode 100644 index 000000000..d52acf814 --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/byteorder.h @@ -0,0 +1,20 @@ +/* +* (C) Copyright 2004, Psyent Corporation <www.psyent.com> +* Scott McNutt <smcnutt@psyent.com> +* + * SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __ASM_NIOS2_BYTEORDER_H_ +#define __ASM_NIOS2_BYTEORDER_H_ + +#include <asm/types.h> + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#include <linux/byteorder/little_endian.h> + +#endif /* __ASM_NIOS2_BYTEORDER_H_ */ diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/cache.h b/qemu/roms/u-boot/arch/nios2/include/asm/cache.h new file mode 100644 index 000000000..9b87c9f75 --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/cache.h @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_NIOS2_CACHE_H_ +#define __ASM_NIOS2_CACHE_H_ + +extern void flush_dcache (unsigned long start, unsigned long size); +extern void flush_icache (unsigned long start, unsigned long size); + +/* + * Valid L1 data cache line sizes for the NIOS2 architecture are 4, 16, and 32 + * bytes. If the board configuration has not specified one we default to the + * largest of these values for alignment of DMA buffers. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 32 +#endif + +#endif /* __ASM_NIOS2_CACHE_H_ */ diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/config.h b/qemu/roms/u-boot/arch/nios2/include/asm/config.h new file mode 100644 index 000000000..cd2973478 --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/config.h @@ -0,0 +1,10 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/dma-mapping.h b/qemu/roms/u-boot/arch/nios2/include/asm/dma-mapping.h new file mode 100644 index 000000000..1350e3b96 --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/dma-mapping.h @@ -0,0 +1,23 @@ +#ifndef __ASM_NIOS2_DMA_MAPPING_H +#define __ASM_NIOS2_DMA_MAPPING_H + +/* dma_alloc_coherent() return cache-line aligned allocation which is mapped + * to uncached io region. + * + * IO_REGION_BASE should be defined in board config header file + * 0x80000000 for nommu, 0xe0000000 for mmu + */ + +static inline void *dma_alloc_coherent(size_t len, unsigned long *handle) +{ + void *addr = malloc(len + CONFIG_SYS_DCACHELINE_SIZE); + if (!addr) + return 0; + flush_dcache((unsigned long)addr, len + CONFIG_SYS_DCACHELINE_SIZE); + *handle = ((unsigned long)addr + + (CONFIG_SYS_DCACHELINE_SIZE - 1)) & + ~(CONFIG_SYS_DCACHELINE_SIZE - 1) & ~(IO_REGION_BASE); + return (void *)(*handle | IO_REGION_BASE); +} + +#endif /* __ASM_NIOS2_DMA_MAPPING_H */ diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/errno.h b/qemu/roms/u-boot/arch/nios2/include/asm/errno.h new file mode 100644 index 000000000..4c82b503d --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/errno.h @@ -0,0 +1 @@ +#include <asm-generic/errno.h> diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/global_data.h b/qemu/roms/u-boot/arch/nios2/include/asm/global_data.h new file mode 100644 index 000000000..580b0199b --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/global_data.h @@ -0,0 +1,18 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_NIOS2_GLOBALDATA_H_ +#define __ASM_NIOS2_GLOBALDATA_H_ + +/* Architecture-specific global data */ +struct arch_global_data { +}; + +#include <asm-generic/global_data.h> + +#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("gp") + +#endif /* __ASM_NIOS2_GLOBALDATA_H_ */ diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/gpio.h b/qemu/roms/u-boot/arch/nios2/include/asm/gpio.h new file mode 100644 index 000000000..908381f5f --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/gpio.h @@ -0,0 +1,79 @@ +/* + * nios2 gpio driver + * + * This gpio core is described in http://nioswiki.com/GPIO + * bit[0] data + * bit[1] output enable + * + * When CONFIG_SYS_GPIO_BASE is not defined, the board may either + * provide its own driver or the altera_pio driver may be used. + * + * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _ASM_NIOS2_GPIO_H_ +#define _ASM_NIOS2_GPIO_H_ + +#ifdef CONFIG_SYS_GPIO_BASE +#include <asm/io.h> + +static inline int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + +static inline int gpio_free(unsigned gpio) +{ + return 0; +} + +static inline int gpio_direction_input(unsigned gpio) +{ + writel(1, CONFIG_SYS_GPIO_BASE + (gpio << 2)); + return 0; +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ + writel(value ? 3 : 2, CONFIG_SYS_GPIO_BASE + (gpio << 2)); + return 0; +} + +static inline int gpio_get_value(unsigned gpio) +{ + return readl(CONFIG_SYS_GPIO_BASE + (gpio << 2)); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + writel(value ? 3 : 2, CONFIG_SYS_GPIO_BASE + (gpio << 2)); +} + +static inline int gpio_is_valid(int number) +{ + return ((unsigned)number) < CONFIG_SYS_GPIO_WIDTH; +} +#else +#ifdef CONFIG_ALTERA_PIO +extern int altera_pio_init(u32 base, u8 width, char iot, + u32 rstval, u32 negmask, + const char *label); + +extern void altera_pio_info(void); +#define gpio_status() altera_pio_info() +#endif + +extern int gpio_request(unsigned gpio, const char *label); +extern int gpio_free(unsigned gpio); +extern int gpio_direction_input(unsigned gpio); +extern int gpio_direction_output(unsigned gpio, int value); +extern int gpio_get_value(unsigned gpio); +extern void gpio_set_value(unsigned gpio, int value); +extern int gpio_is_valid(int number); +#endif /* CONFIG_SYS_GPIO_BASE */ + +#endif /* _ASM_NIOS2_GPIO_H_ */ diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/io.h b/qemu/roms/u-boot/arch/nios2/include/asm/io.h new file mode 100644 index 000000000..69ab23e5f --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/io.h @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_NIOS2_IO_H_ +#define __ASM_NIOS2_IO_H_ + +static inline void sync(void) +{ + __asm__ __volatile__ ("sync" : : : "memory"); +} + +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + +static inline phys_addr_t virt_to_phys(void * vaddr) +{ + return (phys_addr_t)(vaddr); +} + +extern unsigned char inb (unsigned char *port); +extern unsigned short inw (unsigned short *port); +extern unsigned inl (unsigned port); + +#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) + +#define __raw_readb(a) (*(volatile unsigned char *)(a)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_readl(a) (*(volatile unsigned int *)(a)) + +#define readb(addr)\ + ({unsigned char val;\ + asm volatile( "ldbio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) +#define readw(addr)\ + ({unsigned short val;\ + asm volatile( "ldhio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) +#define readl(addr)\ + ({unsigned long val;\ + asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) + +#define writeb(val,addr)\ + asm volatile ("stbio %0, 0(%1)" : : "r" (val), "r" (addr)) +#define writew(val,addr)\ + asm volatile ("sthio %0, 0(%1)" : : "r" (val), "r" (addr)) +#define writel(val,addr)\ + asm volatile ("stwio %0, 0(%1)" : : "r" (val), "r" (addr)) + +#define inb(addr) readb(addr) +#define inw(addr) readw(addr) +#define inl(addr) readl(addr) +#define outb(val, addr) writeb(val,addr) +#define outw(val, addr) writew(val,addr) +#define outl(val, addr) writel(val,addr) + +static inline void insb (unsigned long port, void *dst, unsigned long count) +{ + unsigned char *p = dst; + while (count--) *p++ = inb (port); +} +static inline void insw (unsigned long port, void *dst, unsigned long count) +{ + unsigned short *p = dst; + while (count--) *p++ = inw (port); +} +static inline void insl (unsigned long port, void *dst, unsigned long count) +{ + unsigned long *p = dst; + while (count--) *p++ = inl (port); +} + +static inline void outsb (unsigned long port, const void *src, unsigned long count) +{ + const unsigned char *p = src; + while (count--) outb (*p++, port); +} + +static inline void outsw (unsigned long port, const void *src, unsigned long count) +{ + const unsigned short *p = src; + while (count--) outw (*p++, port); +} +static inline void outsl (unsigned long port, const void *src, unsigned long count) +{ + const unsigned long *p = src; + while (count--) outl (*p++, port); +} + +#endif /* __ASM_NIOS2_IO_H_ */ diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/opcodes.h b/qemu/roms/u-boot/arch/nios2/include/asm/opcodes.h new file mode 100644 index 000000000..69d79b785 --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/opcodes.h @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_NIOS2_OPCODES_H_ +#define __ASM_NIOS2_OPCODES_H_ + +#define OPCODE_OP(inst) ((inst) & 0x3f) +#define OPCODE_OPX(inst) (((inst)>>11) & 0x3f) +#define OPCODE_RA(inst) (((inst)>>27) & 01f) +#define OPCODE_RB(inst) (((inst)>>22) & 01f) +#define OPCODE_RC(inst) (((inst)>>17) & 01f) + +/* I-TYPE (immediate) and J-TYPE (jump) opcodes + */ +#define OPCODE_CALL 0x00 +#define OPCODE_LDBU 0x03 +#define OPCODE_ADDI 0x04 +#define OPCODE_STB 0x05 +#define OPCODE_BR 0x06 +#define OPCODE_LDB 0x07 +#define OPCODE_CMPGEI 0x08 +#define OPCODE_LDHU 0x0B +#define OPCODE_ANDI 0x0C +#define OPCODE_STH 0x0D +#define OPCODE_BGE 0x0E +#define OPCODE_LDH 0x0F +#define OPCODE_CMPLTI 0x10 +#define OPCODE_XORI 0x1C +#define OPCODE_ORI 0x14 +#define OPCODE_STW 0x15 +#define OPCODE_BLT 0x16 +#define OPCODE_LDW 0x17 +#define OPCODE_CMPNEI 0x18 +#define OPCODE_BNE 0x1E +#define OPCODE_CMPEQI 0x20 +#define OPCODE_LDBUIO 0x23 +#define OPCODE_MULI 0x24 +#define OPCODE_STBIO 0x25 +#define OPCODE_BEQ 0x26 +#define OPCODE_LDBIO 0x27 +#define OPCODE_CMPGEUI 0x28 +#define OPCODE_ANDHI 0x2C +#define OPCODE_STHIO 0x2D +#define OPCODE_BGEU 0x2E +#define OPCODE_LDHIO 0x2F +#define OPCODE_CMPLTUI 0x30 +#define OPCODE_CUSTOM 0x32 +#define OPCODE_INITD 0x33 +#define OPCODE_ORHI 0x34 +#define OPCODE_STWIO 0x35 +#define OPCODE_BLTU 0x36 +#define OPCODE_LDWIO 0x37 +#define OPCODE_RTYPE 0x3A +#define OPCODE_LDHUIO 0x2B +#define OPCODE_FLUSHD 0x3B +#define OPCODE_XORHI 0x3C + +/* R-Type (register) OPX field encodings + */ +#define OPCODE_ERET 0x01 +#define OPCODE_ROLI 0x02 +#define OPCODE_ROL 0x03 +#define OPCODE_FLUSHP 0x04 +#define OPCODE_RET 0x05 +#define OPCODE_NOR 0x06 +#define OPCODE_MULXUU 0x07 +#define OPCODE_CMPGE 0x08 +#define OPCODE_BRET 0x09 +#define OPCODE_ROR 0x0B +#define OPCODE_FLUSHI 0x0C +#define OPCODE_JMP 0x0D +#define OPCODE_AND 0x0E + +#define OPCODE_CMPLT 0x10 +#define OPCODE_SLLI 0x12 +#define OPCODE_SLL 0x13 +#define OPCODE_OR 0x16 +#define OPCODE_MULXSU 0x17 +#define OPCODE_CMPNE 0x18 +#define OPCODE_SRLI 0x1A +#define OPCODE_SRL 0x1B +#define OPCODE_NEXTPC 0x1C +#define OPCODE_CALLR 0x1D +#define OPCODE_XOR 0x1E +#define OPCODE_MULXSS 0x1F + +#define OPCODE_CMPEQ 0x20 +#define OPCODE_CMPLTU 0x30 +#define OPCODE_ADD 0x31 +#define OPCODE_DIVU 0x24 +#define OPCODE_DIV 0x25 +#define OPCODE_RDCTL 0x26 +#define OPCODE_MUL 0x27 +#define OPCODE_CMPGEU 0x28 +#define OPCODE_TRAP 0x2D +#define OPCODE_WRCTL 0x2E + +#define OPCODE_BREAK 0x34 +#define OPCODE_SYNC 0x36 +#define OPCODE_INITI 0x29 +#define OPCODE_SUB 0x39 +#define OPCODE_SRAI 0x3A +#define OPCODE_SRA 0x3B + +/*Full instruction encodings for R-Type, without the R's ;-) + * + * TODO: BREAK, BRET, ERET, RET, SYNC (as needed) + */ +#define OPC_TRAP 0x003b683a + +#endif /* __ASM_NIOS2_OPCODES_H_ */ diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/posix_types.h b/qemu/roms/u-boot/arch/nios2/include/asm/posix_types.h new file mode 100644 index 000000000..673364099 --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/posix_types.h @@ -0,0 +1,63 @@ +#ifndef __ASM_NIOS2_POSIX_TYPES_H_ +#define __ASM_NIOS2_POSIX_TYPES_H_ + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef unsigned long __kernel_size_t; +typedef long __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) + +#undef __FD_CLR +#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d)) + +#undef __FD_ISSET +#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) + +#undef __FD_ZERO +#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) + +#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ + +#endif /* __ASM_NIOS2_POSIX_TYPES_H_ */ diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/processor.h b/qemu/roms/u-boot/arch/nios2/include/asm/processor.h new file mode 100644 index 000000000..28a25c53d --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/processor.h @@ -0,0 +1,10 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_NIOS2_PROCESSOR_H_ +#define __ASM_NIOS2_PROCESSOR_H_ +#endif /* __ASM_NIOS2_PROCESSOR_H_ */ diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/psr.h b/qemu/roms/u-boot/arch/nios2/include/asm/psr.h new file mode 100644 index 000000000..3ebb2a011 --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/psr.h @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_NIOS2_PSR_H_ +#define __ASM_NIOS2_PSR_H_ + + +#endif /* __ASM_NIOS2_PSR_H_ */ diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/ptrace.h b/qemu/roms/u-boot/arch/nios2/include/asm/ptrace.h new file mode 100644 index 000000000..732e9d7e7 --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/ptrace.h @@ -0,0 +1,17 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_NIOS2_PTRACE_H_ +#define __ASM_NIOS2_PTRACE_H_ + +struct pt_regs { + unsigned reg[32]; + unsigned status; +}; + + +#endif /* __ASM_NIOS2_PTRACE_H_ */ diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/sections.h b/qemu/roms/u-boot/arch/nios2/include/asm/sections.h new file mode 100644 index 000000000..f0da75dcf --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/sections.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_NIOS2_SECTIONS_H +#define __ASM_NIOS2_SECTIONS_H + +#include <asm-generic/sections.h> + +#endif diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/string.h b/qemu/roms/u-boot/arch/nios2/include/asm/string.h new file mode 100644 index 000000000..aff3a7985 --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/string.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_NIOS2_STRING_H_ +#define __ASM_NIOS2_STRING_H_ + +#undef __HAVE_ARCH_STRRCHR +extern char * strrchr(const char * s, int c); + +#undef __HAVE_ARCH_STRCHR +extern char * strchr(const char * s, int c); + +#undef __HAVE_ARCH_MEMCPY +extern void * memcpy(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMMOVE +extern void * memmove(void *, const void *, __kernel_size_t); + +#undef __HAVE_ARCH_MEMCHR +extern void * memchr(const void *, int, __kernel_size_t); + +#undef __HAVE_ARCH_MEMSET +extern void * memset(void *, int, __kernel_size_t); + +#undef __HAVE_ARCH_MEMZERO +extern void memzero(void *ptr, __kernel_size_t n); + +#endif /* __ASM_NIOS2_STRING_H_ */ diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/system.h b/qemu/roms/u-boot/arch/nios2/include/asm/system.h new file mode 100644 index 000000000..6213a16ed --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/system.h @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_NIOS2_SYSTEM_H_ +#define __ASM_NIOS2_SYSTEM_H_ + +#define local_irq_enable() __asm__ __volatile__ ( \ + "rdctl r8, status\n" \ + "ori r8, r8, 1\n" \ + "wrctl status, r8\n" \ + : : : "r8") + +#define local_irq_disable() __asm__ __volatile__ ( \ + "rdctl r8, status\n" \ + "andi r8, r8, 0xfffe\n" \ + "wrctl status, r8\n" \ + : : : "r8") + +#define local_save_flags(x) __asm__ __volatile__ ( \ + "rdctl r8, status\n" \ + "mov %0, r8\n" \ + : "=r" (x) : : "r8", "memory") + +#define local_irq_restore(x) __asm__ __volatile__ ( \ + "mov r8, %0\n" \ + "wrctl status, r8\n" \ + : : "r" (x) : "r8", "memory") + +/* For spinlocks etc */ +#define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } \ + while (0) + +#define irqs_disabled() \ +({ \ + unsigned long flags; \ + local_save_flags(flags); \ + ((flags & NIOS2_STATUS_PIE_MSK) == 0x0); \ +}) + +/* indirect call to go beyond 256MB limitation of toolchain */ +#define nios2_callr(addr) __asm__ __volatile__ ( \ + "callr %0" \ + : : "r" (addr)) + +#endif /* __ASM_NIOS2_SYSTEM_H */ diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/types.h b/qemu/roms/u-boot/arch/nios2/include/asm/types.h new file mode 100644 index 000000000..ea859c077 --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/types.h @@ -0,0 +1,60 @@ +#ifndef __ASM_NIOS2_TYPES_H_ +#define __ASM_NIOS2_TYPES_H_ + +/* + * This file is never included by application software unless + * explicitly requested (e.g., via linux/types.h) in which case the + * application is Linux specific so (user-) name space pollution is + * not a major issue. However, for interoperability, libraries still + * need to be careful to avoid a name clashes. + */ + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) +__extension__ typedef __signed__ long long __s64; +__extension__ typedef unsigned long long __u64; +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; + +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; +#endif /* __KERNEL__ */ + +#endif /* __ASM_NIOS2_TYPES_H */ diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/u-boot.h b/qemu/roms/u-boot/arch/nios2/include/asm/u-boot.h new file mode 100644 index 000000000..51f6c30ef --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/u-boot.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef __ASM_NIOS2_U_BOOT_H_ +#define __ASM_NIOS2_U_BOOT_H_ + +typedef struct bd_info { + unsigned long bi_memstart; /* start of DRAM memory */ + phys_size_t bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + unsigned long bi_sramstart; /* start of SRAM memory */ + unsigned long bi_sramsize; /* size of SRAM memory */ +} bd_t; + +/* For image.h:image_check_target_arch() */ +#define IH_ARCH_DEFAULT IH_ARCH_NIOS2 + +#endif /* __ASM_NIOS2_U_BOOT_H_ */ diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/unaligned.h b/qemu/roms/u-boot/arch/nios2/include/asm/unaligned.h new file mode 100644 index 000000000..779117c4b --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/unaligned.h @@ -0,0 +1,6 @@ +#ifndef _ASM_NIOS2_UNALIGNED_H +#define _ASM_NIOS2_UNALIGNED_H + +#include <asm-generic/unaligned.h> + +#endif /* _ASM_NIOS2_UNALIGNED_H */ |