diff options
Diffstat (limited to 'qemu/roms/u-boot/arch/nios2/include/asm/cache.h')
| -rw-r--r-- | qemu/roms/u-boot/arch/nios2/include/asm/cache.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/arch/nios2/include/asm/cache.h b/qemu/roms/u-boot/arch/nios2/include/asm/cache.h new file mode 100644 index 000000000..9b87c9f75 --- /dev/null +++ b/qemu/roms/u-boot/arch/nios2/include/asm/cache.h @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_NIOS2_CACHE_H_ +#define __ASM_NIOS2_CACHE_H_ + +extern void flush_dcache (unsigned long start, unsigned long size); +extern void flush_icache (unsigned long start, unsigned long size); + +/* + * Valid L1 data cache line sizes for the NIOS2 architecture are 4, 16, and 32 + * bytes. If the board configuration has not specified one we default to the + * largest of these values for alignment of DMA buffers. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 32 +#endif + +#endif /* __ASM_NIOS2_CACHE_H_ */ |