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-rw-r--r--qemu/roms/seabios/src/fw/biostables.c66
-rw-r--r--qemu/roms/seabios/src/fw/coreboot.c17
-rw-r--r--qemu/roms/seabios/src/fw/csm.c23
-rw-r--r--qemu/roms/seabios/src/fw/dev-q35.h3
-rw-r--r--qemu/roms/seabios/src/fw/multiboot.c111
-rw-r--r--qemu/roms/seabios/src/fw/paravirt.c93
-rw-r--r--qemu/roms/seabios/src/fw/paravirt.h26
-rw-r--r--qemu/roms/seabios/src/fw/pciinit.c24
-rw-r--r--qemu/roms/seabios/src/fw/shadow.c12
-rw-r--r--qemu/roms/seabios/src/fw/smbios.c2
-rw-r--r--qemu/roms/seabios/src/fw/smm.c8
-rw-r--r--qemu/roms/seabios/src/fw/smp.c3
-rw-r--r--qemu/roms/seabios/src/fw/xen.c9
13 files changed, 318 insertions, 79 deletions
diff --git a/qemu/roms/seabios/src/fw/biostables.c b/qemu/roms/seabios/src/fw/biostables.c
index 50a891be8..9fb9ff9df 100644
--- a/qemu/roms/seabios/src/fw/biostables.c
+++ b/qemu/roms/seabios/src/fw/biostables.c
@@ -6,14 +6,15 @@
#include "byteorder.h" // le32_to_cpu
#include "config.h" // CONFIG_*
+#include "hw/pci.h" // pci_config_writeb
#include "malloc.h" // malloc_fseg
+#include "memmap.h" // SYMBOL
#include "output.h" // dprintf
-#include "hw/pci.h" // pci_config_writeb
+#include "romfile.h" // romfile_find
#include "std/acpi.h" // struct rsdp_descriptor
#include "std/mptable.h" // MPTABLE_SIGNATURE
#include "std/pirtable.h" // struct pir_header
#include "std/smbios.h" // struct smbios_entry_point
-#include "romfile.h"
#include "string.h" // memcpy
#include "util.h" // copy_table
#include "x86.h" // outb
@@ -54,6 +55,11 @@ copy_mptable(void *pos)
return;
u32 length = p->length * 16;
u16 mpclength = ((struct mptable_config_s *)p->physaddr)->length;
+ if (length + mpclength > BUILD_MAX_MPTABLE_FSEG) {
+ dprintf(1, "Skipping MPTABLE copy due to large size (%d bytes)\n"
+ , length + mpclength);
+ return;
+ }
// Allocate final memory location. (In theory the config
// structure can go in high memory, but Linux kernels before
// v2.6.30 crash with that.)
@@ -117,9 +123,8 @@ copy_acpi_rsdp(void *pos)
void *find_acpi_rsdp(void)
{
- extern u8 zonefseg_start[], zonefseg_end[];
- unsigned long start = (unsigned long)zonefseg_start;
- unsigned long end = (unsigned long)zonefseg_end;
+ unsigned long start = SYMBOL(zonefseg_start);
+ unsigned long end = SYMBOL(zonefseg_end);
unsigned long pos;
for (pos = ALIGN(start, 0x10); pos <= ALIGN_DOWN(end, 0x10); pos += 0x10)
@@ -271,7 +276,7 @@ copy_smbios(void *pos)
if (SMBiosAddr)
return;
struct smbios_entry_point *p = pos;
- if (memcmp(p->anchor_string, "_SM_", 4))
+ if (p->signature != SMBIOS_SIGNATURE)
return;
if (checksum(pos, 0x10) != 0)
return;
@@ -301,17 +306,42 @@ display_uuid(void)
if (memcmp(uuid, empty_uuid, sizeof(empty_uuid)) == 0)
return;
- printf("Machine UUID"
- " %02x%02x%02x%02x"
- "-%02x%02x"
- "-%02x%02x"
- "-%02x%02x"
- "-%02x%02x%02x%02x%02x%02x\n"
- , uuid[ 0], uuid[ 1], uuid[ 2], uuid[ 3]
- , uuid[ 4], uuid[ 5]
- , uuid[ 6], uuid[ 7]
- , uuid[ 8], uuid[ 9]
- , uuid[10], uuid[11], uuid[12], uuid[13], uuid[14], uuid[15]);
+ /*
+ * According to SMBIOS v2.6 the first three fields are encoded in
+ * little-endian format. Versions prior to v2.6 did not specify
+ * the encoding, but we follow dmidecode and assume big-endian
+ * encoding.
+ */
+ if (SMBiosAddr->smbios_major_version > 2 ||
+ (SMBiosAddr->smbios_major_version == 2 &&
+ SMBiosAddr->smbios_minor_version >= 6)) {
+ printf("Machine UUID"
+ " %02x%02x%02x%02x"
+ "-%02x%02x"
+ "-%02x%02x"
+ "-%02x%02x"
+ "-%02x%02x%02x%02x%02x%02x\n"
+ , uuid[ 3], uuid[ 2], uuid[ 1], uuid[ 0]
+ , uuid[ 5], uuid[ 4]
+ , uuid[ 7], uuid[ 6]
+ , uuid[ 8], uuid[ 9]
+ , uuid[10], uuid[11], uuid[12]
+ , uuid[13], uuid[14], uuid[15]);
+ } else {
+ printf("Machine UUID"
+ " %02x%02x%02x%02x"
+ "-%02x%02x"
+ "-%02x%02x"
+ "-%02x%02x"
+ "-%02x%02x%02x%02x%02x%02x\n"
+ , uuid[ 0], uuid[ 1], uuid[ 2], uuid[ 3]
+ , uuid[ 4], uuid[ 5]
+ , uuid[ 6], uuid[ 7]
+ , uuid[ 8], uuid[ 9]
+ , uuid[10], uuid[11], uuid[12]
+ , uuid[13], uuid[14], uuid[15]);
+ }
+
return;
}
}
@@ -447,7 +477,7 @@ void
smbios_setup(void)
{
if (smbios_romfile_setup())
- return;
+ return;
smbios_legacy_setup();
}
diff --git a/qemu/roms/seabios/src/fw/coreboot.c b/qemu/roms/seabios/src/fw/coreboot.c
index 8fd84493b..4fe12928c 100644
--- a/qemu/roms/seabios/src/fw/coreboot.c
+++ b/qemu/roms/seabios/src/fw/coreboot.c
@@ -7,10 +7,10 @@
#include "block.h" // MAXDESCSIZE
#include "byteorder.h" // be32_to_cpu
#include "config.h" // CONFIG_*
+#include "e820map.h" // e820_add
#include "hw/pci.h" // pci_probe_devices
#include "lzmadecode.h" // LzmaDecode
#include "malloc.h" // free
-#include "memmap.h" // add_e820
#include "output.h" // dprintf
#include "paravirt.h" // PlatformRunningOn
#include "romfile.h" // romfile_findprefix
@@ -184,12 +184,12 @@ coreboot_preinit(void)
u32 type = m->type;
if (type == CB_MEM_TABLE)
type = E820_RESERVED;
- add_e820(m->start, m->size, type);
+ e820_add(m->start, m->size, type);
}
// Ughh - coreboot likes to set a map at 0x0000-0x1000, but this
// confuses grub. So, override it.
- add_e820(0, 16*1024, E820_RAM);
+ e820_add(0, 16*1024, E820_RAM);
struct cb_cbmem_ref *cbref = find_cb_subtable(cbh, CB_TAG_CBMEM_CONSOLE);
if (cbref) {
@@ -210,7 +210,7 @@ coreboot_preinit(void)
fail:
// No table found.. Use 16Megs as a dummy value.
dprintf(1, "Unable to find coreboot table!\n");
- add_e820(0, 16*1024*1024, E820_RAM);
+ e820_add(0, 16*1024*1024, E820_RAM);
return;
}
@@ -421,6 +421,13 @@ coreboot_cbfs_init(void)
return;
struct cbfs_header *hdr = *(void **)(CONFIG_CBFS_LOCATION - 4);
+ if ((u32)hdr & 0x03) {
+ dprintf(1, "Invalid CBFS pointer %p\n", hdr);
+ return;
+ }
+ if (CONFIG_CBFS_LOCATION && (u32)hdr > CONFIG_CBFS_LOCATION)
+ // Looks like the pointer is relative to CONFIG_CBFS_LOCATION
+ hdr = (void*)hdr + CONFIG_CBFS_LOCATION;
if (hdr->magic != cpu_to_be32(CBFS_HEADER_MAGIC)) {
dprintf(1, "Unable to find CBFS (ptr=%p; got %x not %x)\n"
, hdr, hdr->magic, cpu_to_be32(CBFS_HEADER_MAGIC));
@@ -503,7 +510,7 @@ cbfs_run_payload(struct cbfs_file *fhdr)
break;
case PAYLOAD_SEGMENT_ENTRY: {
dprintf(1, "Calling addr %p\n", dest);
- void (*func)() = dest;
+ void (*func)(void) = dest;
func();
return;
}
diff --git a/qemu/roms/seabios/src/fw/csm.c b/qemu/roms/seabios/src/fw/csm.c
index 7cdb398f2..7cadd12e5 100644
--- a/qemu/roms/seabios/src/fw/csm.c
+++ b/qemu/roms/seabios/src/fw/csm.c
@@ -4,20 +4,21 @@
//
// This file may be distributed under the terms of the GNU LGPLv3 license.
-#include "bregs.h"
+#include "bregs.h" // struct bregs
#include "config.h" // CONFIG_*
+#include "e820map.h" // e820_add
#include "farptr.h" // MAKE_FLATPTR
-#include "hw/pci.h"
-#include "hw/pic.h"
-#include "malloc.h" // csm_malloc_preinit
-#include "memmap.h"
+#include "hw/pci.h" // pci_probe_devices
+#include "hw/pic.h" // pic_irqmask_read
+#include "malloc.h" // malloc_csm_preinit
+#include "memmap.h" // SYMBOL
#include "output.h" // dprintf
+#include "paravirt.h" // qemu_preinit
#include "stacks.h" // wait_threads
#include "std/acpi.h" // RSDP_SIGNATURE
#include "std/bda.h" // struct bios_data_area_s
#include "std/optionrom.h" // struct rom_header
#include "util.h" // copy_smbios
-#include "paravirt.h" // qemu_preinit
#define UINT8 u8
#define UINT16 u16
@@ -47,12 +48,11 @@ static void
csm_return(struct bregs *regs)
{
u32 rommax = rom_get_max();
- extern u8 final_readonly_start[];
dprintf(3, "handle_csm returning AX=%04x\n", regs->ax);
csm_compat_table.UmaAddress = rommax;
- csm_compat_table.UmaSize = (u32)final_readonly_start - rommax;
+ csm_compat_table.UmaSize = SYMBOL(final_readonly_start) - rommax;
PICMask = pic_irqmask_read();
__csm_return(regs);
@@ -95,7 +95,7 @@ handle_csm_0000(struct bregs *regs)
dprintf(3, "LoPmmMemory %08x\n", csm_init_table->LowPmmMemory);
dprintf(3, "LoPmmMemorySize %08x\n", csm_init_table->LowPmmMemorySizeInBytes);
- csm_malloc_preinit(csm_init_table->LowPmmMemory,
+ malloc_csm_preinit(csm_init_table->LowPmmMemory,
csm_init_table->LowPmmMemorySizeInBytes,
csm_init_table->HiPmmMemory,
csm_init_table->HiPmmMemorySizeInBytes);
@@ -147,11 +147,11 @@ handle_csm_0002(struct bregs *regs)
struct e820entry *p = (void *)csm_compat_table.E820Pointer;
int i;
for (i=0; i < csm_compat_table.E820Length / sizeof(struct e820entry); i++)
- add_e820(p[i].start, p[i].size, p[i].type);
+ e820_add(p[i].start, p[i].size, p[i].type);
if (csm_init_table->HiPmmMemorySizeInBytes > BUILD_MAX_HIGHTABLE) {
u32 hi_pmm_end = csm_init_table->HiPmmMemory + csm_init_table->HiPmmMemorySizeInBytes;
- add_e820(hi_pmm_end - BUILD_MAX_HIGHTABLE, BUILD_MAX_HIGHTABLE, E820_RESERVED);
+ e820_add(hi_pmm_end - BUILD_MAX_HIGHTABLE, BUILD_MAX_HIGHTABLE, E820_RESERVED);
}
// For PCIBIOS 1ab10e
@@ -183,6 +183,7 @@ handle_csm_0002(struct bregs *regs)
struct bios_data_area_s *bda = MAKE_FLATPTR(SEG_BDA, 0);
bda->hdcount = 0;
+ thread_setup();
mathcp_setup();
timer_setup();
clock_setup();
diff --git a/qemu/roms/seabios/src/fw/dev-q35.h b/qemu/roms/seabios/src/fw/dev-q35.h
index c6f8bd9e7..201825deb 100644
--- a/qemu/roms/seabios/src/fw/dev-q35.h
+++ b/qemu/roms/seabios/src/fw/dev-q35.h
@@ -27,6 +27,9 @@
#define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4)
#define ICH9_LPC_PORT_ELCR1 0x4d0
#define ICH9_LPC_PORT_ELCR2 0x4d1
+#define ICH9_LPC_RCBA 0xf0
+#define ICH9_LPC_RCBA_ADDR 0xfed1c000
+#define ICH9_LPC_RCBA_EN 0x1
#define PCI_DEVICE_ID_INTEL_ICH9_SMBUS 0x2930
#define ICH9_SMB_SMB_BASE 0x20
#define ICH9_SMB_HOSTC 0x40
diff --git a/qemu/roms/seabios/src/fw/multiboot.c b/qemu/roms/seabios/src/fw/multiboot.c
new file mode 100644
index 000000000..d9df06764
--- /dev/null
+++ b/qemu/roms/seabios/src/fw/multiboot.c
@@ -0,0 +1,111 @@
+// Multiboot interface support.
+//
+// Copyright (C) 2015 Vladimir Serbinenko <phcoder@gmail.com>
+//
+// This file may be distributed under the terms of the GNU LGPLv3 license.
+
+#include "config.h" // CONFIG_*
+#include "malloc.h" // free
+#include "output.h" // dprintf
+#include "romfile.h" // romfile_add
+#include "std/multiboot.h" // MULTIBOOT_*
+#include "string.h" // memset
+#include "util.h" // multiboot_init
+
+struct mbfs_romfile_s {
+ struct romfile_s file;
+ void *data;
+};
+
+static int
+extract_filename(char *dest, char *src, size_t lim)
+{
+ char *ptr;
+ for (ptr = src; *ptr; ptr++) {
+ if (!(ptr == src || ptr[-1] == ' ' || ptr[-1] == '\t'))
+ continue;
+ /* memcmp stops early if it encounters \0 as it doesn't match name=. */
+ if (memcmp(ptr, "name=", 5) == 0) {
+ int i;
+ char *optr = dest;
+ for (i = 0, ptr += 5; *ptr && *ptr != ' ' && i < lim; i++) {
+ *optr++ = *ptr++;
+ }
+ *optr++ = '\0';
+ return 1;
+ }
+ }
+ return 0;
+}
+
+// Copy a file to memory
+static int
+mbfs_copyfile(struct romfile_s *file, void *dst, u32 maxlen)
+{
+ struct mbfs_romfile_s *cfile;
+ cfile = container_of(file, struct mbfs_romfile_s, file);
+ u32 size = cfile->file.size;
+ void *src = cfile->data;
+
+ // Not compressed.
+ dprintf(3, "Copying data %d@%p to %d@%p\n", size, src, maxlen, dst);
+ if (size > maxlen) {
+ warn_noalloc();
+ return -1;
+ }
+ iomemcpy(dst, src, size);
+ return size;
+}
+
+u32 __VISIBLE entry_elf_eax, entry_elf_ebx;
+
+void
+multiboot_init(void)
+{
+ struct multiboot_info *mbi;
+ if (!CONFIG_MULTIBOOT)
+ return;
+ dprintf(1, "multiboot: eax=%x, ebx=%x\n", entry_elf_eax, entry_elf_ebx);
+ if (entry_elf_eax != MULTIBOOT_BOOTLOADER_MAGIC)
+ return;
+ mbi = (void *)entry_elf_ebx;
+ dprintf(1, "mbptr=%p\n", mbi);
+ dprintf(1, "flags=0x%x, mods=0x%x, mods_c=%d\n", mbi->flags, mbi->mods_addr,
+ mbi->mods_count);
+ if (!(mbi->flags & MULTIBOOT_INFO_MODS))
+ return;
+ int i;
+ struct multiboot_mod_list *mod = (void *)mbi->mods_addr;
+ for (i = 0; i < mbi->mods_count; i++) {
+ struct mbfs_romfile_s *cfile;
+ u8 *copy;
+ u32 len;
+ if (!mod[i].cmdline)
+ continue;
+ len = mod[i].mod_end - mod[i].mod_start;
+ cfile = malloc_tmp(sizeof(*cfile));
+ if (!cfile) {
+ warn_noalloc();
+ return;
+ }
+ memset(cfile, 0, sizeof(*cfile));
+ dprintf(1, "module %s, size 0x%x\n", (char *)mod[i].cmdline, len);
+ if (!extract_filename(cfile->file.name, (char *)mod[i].cmdline,
+ sizeof(cfile->file.name))) {
+ free(cfile);
+ continue;
+ }
+ dprintf(1, "assigned file name <%s>\n", cfile->file.name);
+ cfile->file.size = len;
+ copy = malloc_tmp(len);
+ if (!copy) {
+ warn_noalloc();
+ free(cfile);
+ return;
+ }
+ memcpy(copy, (void *)mod[i].mod_start, len);
+ cfile->file.copy = mbfs_copyfile;
+ cfile->data = copy;
+ romfile_add(&cfile->file);
+ }
+}
diff --git a/qemu/roms/seabios/src/fw/paravirt.c b/qemu/roms/seabios/src/fw/paravirt.c
index db22ae8fc..3fae13a83 100644
--- a/qemu/roms/seabios/src/fw/paravirt.c
+++ b/qemu/roms/seabios/src/fw/paravirt.c
@@ -10,11 +10,11 @@
#include "byteorder.h" // be32_to_cpu
#include "config.h" // CONFIG_QEMU
+#include "e820map.h" // e820_add
#include "hw/pci.h" // create_pirtable
#include "hw/pci_regs.h" // PCI_DEVICE_ID
#include "hw/rtc.h" // CMOS_*
#include "malloc.h" // malloc_tmp
-#include "memmap.h" // add_e820
#include "output.h" // dprintf
#include "paravirt.h" // qemu_cfg_preinit
#include "romfile.h" // romfile_loadint
@@ -23,6 +23,7 @@
#include "util.h" // pci_setup
#include "x86.h" // cpuid
#include "xen.h" // xen_biostable_setup
+#include "stacks.h" // yield
// Amount of continuous ram under 4Gig
u32 RamSize;
@@ -30,6 +31,13 @@ u32 RamSize;
u64 RamSizeOver4G;
// Type of emulator platform.
int PlatformRunningOn VARFSEG;
+// cfg_dma enabled
+int cfg_dma_enabled = 0;
+
+inline int qemu_cfg_dma_enabled(void)
+{
+ return cfg_dma_enabled;
+}
/* This CPUID returns the signature 'KVMKVMKVM' in ebx, ecx, and edx. It
* should be used to determine that a VM is running under KVM.
@@ -114,10 +122,10 @@ qemu_preinit(void)
| (rtc_read(CMOS_MEM_EXTMEM_HIGH) << 18))
+ 1 * 1024 * 1024);
RamSize = rs;
- add_e820(0, rs, E820_RAM);
+ e820_add(0, rs, E820_RAM);
/* reserve 256KB BIOS area at the end of 4 GB */
- add_e820(0xfffc0000, 256*1024, E820_RESERVED);
+ e820_add(0xfffc0000, 256*1024, E820_RESERVED);
dprintf(1, "RamSize: 0x%08x [cmos]\n", RamSize);
}
@@ -199,23 +207,63 @@ qemu_cfg_select(u16 f)
}
static void
+qemu_cfg_dma_transfer(void *address, u32 length, u32 control)
+{
+ QemuCfgDmaAccess access;
+
+ access.address = cpu_to_be64((u64)(u32)address);
+ access.length = cpu_to_be32(length);
+ access.control = cpu_to_be32(control);
+
+ barrier();
+
+ outl(cpu_to_be32((u32)&access), PORT_QEMU_CFG_DMA_ADDR_LOW);
+
+ while(be32_to_cpu(access.control) & ~QEMU_CFG_DMA_CTL_ERROR) {
+ yield();
+ }
+}
+
+static void
qemu_cfg_read(void *buf, int len)
{
- insb(PORT_QEMU_CFG_DATA, buf, len);
+ if (len == 0) {
+ return;
+ }
+
+ if (qemu_cfg_dma_enabled()) {
+ qemu_cfg_dma_transfer(buf, len, QEMU_CFG_DMA_CTL_READ);
+ } else {
+ insb(PORT_QEMU_CFG_DATA, buf, len);
+ }
}
static void
qemu_cfg_skip(int len)
{
- while (len--)
- inb(PORT_QEMU_CFG_DATA);
+ if (len == 0) {
+ return;
+ }
+
+ if (qemu_cfg_dma_enabled()) {
+ qemu_cfg_dma_transfer(0, len, QEMU_CFG_DMA_CTL_SKIP);
+ } else {
+ while (len--)
+ inb(PORT_QEMU_CFG_DATA);
+ }
}
static void
qemu_cfg_read_entry(void *buf, int e, int len)
{
- qemu_cfg_select(e);
- qemu_cfg_read(buf, len);
+ if (qemu_cfg_dma_enabled()) {
+ u32 control = (e << 16) | QEMU_CFG_DMA_CTL_SELECT
+ | QEMU_CFG_DMA_CTL_READ;
+ qemu_cfg_dma_transfer(buf, len, control);
+ } else {
+ qemu_cfg_select(e);
+ qemu_cfg_read(buf, len);
+ }
}
struct qemu_romfile_s {
@@ -230,9 +278,14 @@ qemu_cfg_read_file(struct romfile_s *file, void *dst, u32 maxlen)
return -1;
struct qemu_romfile_s *qfile;
qfile = container_of(file, struct qemu_romfile_s, file);
- qemu_cfg_select(qfile->select);
- qemu_cfg_skip(qfile->skip);
- qemu_cfg_read(dst, file->size);
+ if (qfile->skip == 0) {
+ /* Do it in one transfer */
+ qemu_cfg_read_entry(dst, qfile->select, file->size);
+ } else {
+ qemu_cfg_select(qfile->select);
+ qemu_cfg_skip(qfile->skip);
+ qemu_cfg_read(dst, file->size);
+ }
return file->size;
}
@@ -302,7 +355,7 @@ qemu_cfg_e820(void)
}
/* fall through */
case E820_RESERVED:
- add_e820(table[i].address, table[i].length, table[i].type);
+ e820_add(table[i].address, table[i].length, table[i].type);
break;
default:
/*
@@ -324,13 +377,13 @@ qemu_cfg_e820(void)
int i;
for (i = 0; i < count32; i++) {
qemu_cfg_read(&entry, sizeof(entry));
- add_e820(entry.address, entry.length, entry.type);
+ e820_add(entry.address, entry.length, entry.type);
}
} else if (runningOnKVM()) {
// Backwards compatibility - provide hard coded range.
// 4 pages before the bios, 3 pages for vmx tss pages, the
// other page for EPT real mode pagetable
- add_e820(0xfffbc000, 4*4096, E820_RESERVED);
+ e820_add(0xfffbc000, 4*4096, E820_RESERVED);
}
// Check for memory over 4Gig in cmos
@@ -338,7 +391,7 @@ qemu_cfg_e820(void)
| ((u32)rtc_read(CMOS_MEM_HIGHMEM_MID) << 24)
| ((u64)rtc_read(CMOS_MEM_HIGHMEM_HIGH) << 32));
RamSizeOver4G = high;
- add_e820(0x100000000ull, high, E820_RAM);
+ e820_add(0x100000000ull, high, E820_RAM);
dprintf(1, "RamSizeOver4G: 0x%016llx [cmos]\n", RamSizeOver4G);
}
@@ -422,8 +475,18 @@ void qemu_cfg_init(void)
for (i = 0; i < 4; i++)
if (inb(PORT_QEMU_CFG_DATA) != sig[i])
return;
+
dprintf(1, "Found QEMU fw_cfg\n");
+ // Detect DMA interface.
+ u32 id;
+ qemu_cfg_read_entry(&id, QEMU_CFG_ID, sizeof(id));
+
+ if (id & QEMU_CFG_VERSION_DMA) {
+ dprintf(1, "QEMU fw_cfg DMA interface supported\n");
+ cfg_dma_enabled = 1;
+ }
+
// Populate romfiles for legacy fw_cfg entries
qemu_cfg_legacy();
diff --git a/qemu/roms/seabios/src/fw/paravirt.h b/qemu/roms/seabios/src/fw/paravirt.h
index 95ffb92ad..ed8e5f1f8 100644
--- a/qemu/roms/seabios/src/fw/paravirt.h
+++ b/qemu/roms/seabios/src/fw/paravirt.h
@@ -9,6 +9,12 @@
#define PF_XEN (1<<1)
#define PF_KVM (1<<2)
+typedef struct QemuCfgDmaAccess {
+ u32 control;
+ u32 length;
+ u64 address;
+} PACKED QemuCfgDmaAccess;
+
extern u32 RamSize;
extern u64 RamSizeOver4G;
extern int PlatformRunningOn;
@@ -25,11 +31,23 @@ static inline int runningOnKVM(void) {
}
// Common paravirt ports.
-#define PORT_SMI_CMD 0x00b2
-#define PORT_SMI_STATUS 0x00b3
-#define PORT_QEMU_CFG_CTL 0x0510
-#define PORT_QEMU_CFG_DATA 0x0511
+#define PORT_SMI_CMD 0x00b2
+#define PORT_SMI_STATUS 0x00b3
+#define PORT_QEMU_CFG_CTL 0x0510
+#define PORT_QEMU_CFG_DATA 0x0511
+#define PORT_QEMU_CFG_DMA_ADDR_HIGH 0x0514
+#define PORT_QEMU_CFG_DMA_ADDR_LOW 0x0518
+
+// QEMU_CFG_DMA_CONTROL bits
+#define QEMU_CFG_DMA_CTL_ERROR 0x01
+#define QEMU_CFG_DMA_CTL_READ 0x02
+#define QEMU_CFG_DMA_CTL_SKIP 0x04
+#define QEMU_CFG_DMA_CTL_SELECT 0x08
+
+// QEMU_CFG_DMA ID bit
+#define QEMU_CFG_VERSION_DMA 2
+int qemu_cfg_dma_enabled(void);
void qemu_preinit(void);
void qemu_platform_setup(void);
void qemu_cfg_init(void);
diff --git a/qemu/roms/seabios/src/fw/pciinit.c b/qemu/roms/seabios/src/fw/pciinit.c
index 46ae7090e..c31c2fa0c 100644
--- a/qemu/roms/seabios/src/fw/pciinit.c
+++ b/qemu/roms/seabios/src/fw/pciinit.c
@@ -9,13 +9,13 @@
#include "config.h" // CONFIG_*
#include "dev-q35.h" // Q35_HOST_BRIDGE_PCIEXBAR_ADDR
#include "dev-piix.h" // PIIX_*
+#include "e820map.h" // e820_add
#include "hw/ata.h" // PORT_ATA1_CMD_BASE
#include "hw/pci.h" // pci_config_readl
#include "hw/pci_ids.h" // PCI_VENDOR_ID_INTEL
#include "hw/pci_regs.h" // PCI_COMMAND
#include "list.h" // struct hlist_node
#include "malloc.h" // free
-#include "memmap.h" // add_e820
#include "output.h" // dprintf
#include "paravirt.h" // RamSize
#include "romfile.h" // romfile_loadint
@@ -183,6 +183,11 @@ static void mch_isa_bridge_setup(struct pci_device *dev, void *arg)
/* acpi enable, SCI: IRQ9 000b = irq9*/
pci_config_writeb(bdf, ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_ACPI_EN);
+ /* set root complex register block BAR */
+ pci_config_writel(bdf, ICH9_LPC_RCBA,
+ ICH9_LPC_RCBA_ADDR | ICH9_LPC_RCBA_EN);
+ e820_add(ICH9_LPC_RCBA_ADDR, 16*1024, E820_RESERVED);
+
acpi_pm1a_cnt = acpi_pm_base + 0x04;
pmtimer_setup(acpi_pm_base + 0x08);
}
@@ -316,6 +321,10 @@ static void pci_bios_init_device(struct pci_device *pci)
/* enable memory mappings */
pci_config_maskw(bdf, PCI_COMMAND, 0,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SERR);
+ /* enable SERR# for forwarding */
+ if (pci->header_type & PCI_HEADER_TYPE_BRIDGE)
+ pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0,
+ PCI_BRIDGE_CTL_SERR);
}
static void pci_bios_init_devices(void)
@@ -391,7 +400,7 @@ static void mch_mem_addr_setup(struct pci_device *dev, void *arg)
pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, 0);
pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR + 4, upper);
pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, lower);
- add_e820(addr, size, E820_RESERVED);
+ e820_add(addr, size, E820_RESERVED);
/* setup pci i/o window (above mmconfig) */
pcimem_start = addr + size;
@@ -636,9 +645,8 @@ pci_region_create_entry(struct pci_bus *bus, struct pci_device *dev,
return entry;
}
-static int pci_bus_hotplug_support(struct pci_bus *bus)
+static int pci_bus_hotplug_support(struct pci_bus *bus, u8 pcie_cap)
{
- u8 pcie_cap = pci_find_capability(bus->bus_dev, PCI_CAP_ID_EXP);
u8 shpc_cap;
if (pcie_cap) {
@@ -662,7 +670,7 @@ static int pci_bus_hotplug_support(struct pci_bus *bus)
return downstream_port && slot_implemented;
}
- shpc_cap = pci_find_capability(bus->bus_dev, PCI_CAP_ID_SHPC);
+ shpc_cap = pci_find_capability(bus->bus_dev, PCI_CAP_ID_SHPC, 0);
return !!shpc_cap;
}
@@ -718,7 +726,8 @@ static int pci_bios_check_devices(struct pci_bus *busses)
*/
parent = &busses[0];
int type;
- int hotplug_support = pci_bus_hotplug_support(s);
+ u8 pcie_cap = pci_find_capability(s->bus_dev, PCI_CAP_ID_EXP, 0);
+ int hotplug_support = pci_bus_hotplug_support(s, pcie_cap);
for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
u64 align = (type == PCI_REGION_TYPE_IO) ?
PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN;
@@ -727,7 +736,8 @@ static int pci_bios_check_devices(struct pci_bus *busses)
if (pci_region_align(&s->r[type]) > align)
align = pci_region_align(&s->r[type]);
u64 sum = pci_region_sum(&s->r[type]);
- if (!sum && hotplug_support)
+ int resource_optional = pcie_cap && (type == PCI_REGION_TYPE_IO);
+ if (!sum && hotplug_support && !resource_optional)
sum = align; /* reserve min size for hot-plug */
u64 size = ALIGN(sum, align);
int is64 = pci_bios_bridge_region_is64(&s->r[type],
diff --git a/qemu/roms/seabios/src/fw/shadow.c b/qemu/roms/seabios/src/fw/shadow.c
index 4f00006bf..ee87d36e0 100644
--- a/qemu/roms/seabios/src/fw/shadow.c
+++ b/qemu/roms/seabios/src/fw/shadow.c
@@ -53,9 +53,8 @@ __make_bios_writable_intel(u16 bdf, u32 pam0)
return;
// Copy bios.
- extern u8 code32flat_start[], code32flat_end[];
- memcpy(code32flat_start, code32flat_start + BIOS_SRC_OFFSET
- , code32flat_end - code32flat_start);
+ memcpy(VSYMBOL(code32flat_start), VSYMBOL(code32flat_start) + BIOS_SRC_OFFSET
+ , SYMBOL(code32flat_end) - SYMBOL(code32flat_start));
}
static void
@@ -65,7 +64,7 @@ make_bios_writable_intel(u16 bdf, u32 pam0)
if (!(reg & 0x10)) {
// QEMU doesn't fully implement the piix shadow capabilities -
// if ram isn't backing the bios segment when shadowing is
- // disabled, the code itself wont be in memory. So, run the
+ // disabled, the code itself won't be in memory. So, run the
// code from the high-memory flash location.
u32 pos = (u32)__make_bios_writable_intel + BIOS_SRC_OFFSET;
void (*func)(u16 bdf, u32 pam0) = (void*)pos;
@@ -165,7 +164,6 @@ qemu_prep_reset(void)
// QEMU doesn't map 0xc0000-0xfffff back to the original rom on a
// reset, so do that manually before invoking a hard reset.
make_bios_writable();
- extern u8 code32flat_start[], code32flat_end[];
- memcpy(code32flat_start, code32flat_start + BIOS_SRC_OFFSET
- , code32flat_end - code32flat_start);
+ memcpy(VSYMBOL(code32flat_start), VSYMBOL(code32flat_start) + BIOS_SRC_OFFSET
+ , SYMBOL(code32flat_end) - SYMBOL(code32flat_start));
}
diff --git a/qemu/roms/seabios/src/fw/smbios.c b/qemu/roms/seabios/src/fw/smbios.c
index dba054133..f3b5ad9dd 100644
--- a/qemu/roms/seabios/src/fw/smbios.c
+++ b/qemu/roms/seabios/src/fw/smbios.c
@@ -37,7 +37,7 @@ smbios_entry_point_setup(u16 max_structure_size,
struct smbios_entry_point ep;
memset(&ep, 0, sizeof(ep));
- memcpy(ep.anchor_string, "_SM_", 4);
+ ep.signature = SMBIOS_SIGNATURE;
ep.length = 0x1f;
ep.smbios_major_version = 2;
ep.smbios_minor_version = 4;
diff --git a/qemu/roms/seabios/src/fw/smm.c b/qemu/roms/seabios/src/fw/smm.c
index 6cb484e7e..8f042ee4d 100644
--- a/qemu/roms/seabios/src/fw/smm.c
+++ b/qemu/roms/seabios/src/fw/smm.c
@@ -64,11 +64,11 @@ handle_smi(u16 cs)
return;
u8 cmd = inb(PORT_SMI_CMD);
struct smm_layout *smm = MAKE_FLATPTR(cs, 0);
+ u32 rev = smm->cpu.i32.smm_rev & SMM_REV_MASK;
dprintf(DEBUG_HDL_smi, "handle_smi cmd=%x smbase=%p\n", cmd, smm);
if (smm == (void*)BUILD_SMM_INIT_ADDR) {
// relocate SMBASE to 0xa0000
- u32 rev = smm->cpu.i32.smm_rev & SMM_REV_MASK;
if (rev == SMM_REV_I32) {
smm->cpu.i32.smm_base = BUILD_SMM_ADDR;
} else if (rev == SMM_REV_I64) {
@@ -92,7 +92,7 @@ handle_smi(u16 cs)
}
if (CONFIG_CALL32_SMM && cmd == CALL32SMM_CMDID) {
- if (smm->cpu.i32.smm_rev == SMM_REV_I32) {
+ if (rev == SMM_REV_I32) {
u32 regs[8];
memcpy(regs, &smm->cpu.i32.eax, sizeof(regs));
if (smm->cpu.i32.ecx == CALL32SMM_ENTERID) {
@@ -107,7 +107,7 @@ handle_smi(u16 cs)
memcpy(&smm->cpu.i32.eax, regs, sizeof(regs));
smm->cpu.i32.eip = regs[3];
}
- } else if (smm->cpu.i64.smm_rev == SMM_REV_I64) {
+ } else if (rev == SMM_REV_I64) {
u64 regs[8];
memcpy(regs, &smm->cpu.i64.rdi, sizeof(regs));
if ((u32)smm->cpu.i64.rcx == CALL32SMM_ENTERID) {
@@ -184,7 +184,7 @@ static void piix4_apmc_smm_setup(int isabdf, int i440_bdf)
/* enable SMI generation */
value = inl(acpi_pm_base + PIIX_PMIO_GLBCTL);
- outl(acpi_pm_base + PIIX_PMIO_GLBCTL, value | PIIX_PMIO_GLBCTL_SMI_EN);
+ outl(value | PIIX_PMIO_GLBCTL_SMI_EN, acpi_pm_base + PIIX_PMIO_GLBCTL);
smm_relocate_and_restore();
diff --git a/qemu/roms/seabios/src/fw/smp.c b/qemu/roms/seabios/src/fw/smp.c
index a466ea6e9..579acdbd0 100644
--- a/qemu/roms/seabios/src/fw/smp.c
+++ b/qemu/roms/seabios/src/fw/smp.c
@@ -52,9 +52,6 @@ handle_smp(void)
if (!CONFIG_QEMU)
return;
- // Enable CPU caching
- setcr0(getcr0() & ~(CR0_CD|CR0_NW));
-
// Detect apic_id
u32 eax, ebx, ecx, cpuid_features;
cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
diff --git a/qemu/roms/seabios/src/fw/xen.c b/qemu/roms/seabios/src/fw/xen.c
index dd8e8afd4..3f19ef2dc 100644
--- a/qemu/roms/seabios/src/fw/xen.c
+++ b/qemu/roms/seabios/src/fw/xen.c
@@ -4,16 +4,17 @@
//
// This file may be distributed under the terms of the GNU LGPLv3 license.
-#include "config.h"
+#include "config.h" // CONFIG_XEN
+#include "e820map.h" // e820_add
#include "hw/serialio.h" // DebugOutputPort
#include "malloc.h" // memalign_high
-#include "memmap.h" // add_e820
+#include "memmap.h" // PAGE_SIZE
#include "output.h" // dprintf
#include "paravirt.h" // PlatformRunningOn
#include "string.h" // memcpy
#include "util.h" // copy_acpi_rsdp
#include "x86.h" // cpuid
-#include "xen.h"
+#include "xen.h" // xen_extraversion_t
#define INFO_PHYSICAL_ADDRESS 0x00001000
@@ -142,6 +143,6 @@ void xen_ramsize_preinit(void)
for (i = 0; i < info->e820_nr; i++) {
struct e820entry *e = &e820[i];
- add_e820(e->start, e->size, e->type);
+ e820_add(e->start, e->size, e->type);
}
}