1 files changed, 74 insertions, 0 deletions
diff --git a/qemu/roms/openbios/arch/ppc/misc.S b/qemu/roms/openbios/arch/ppc/misc.S
new file mode 100644
index 000000000..435ce0eca
--- /dev/null
+++ b/qemu/roms/openbios/arch/ppc/misc.S
@@ -0,0 +1,74 @@
+/*
+ *   Creation Date: <2002/10/20 15:54:50 samuel>
+ *   Time-stamp: <2002/10/20 15:57:21 samuel>
+ *
+ *	<misc.S>
+ *
+ *	Low-level stuff
+ *
+ *   Copyright (C) 2002, 2003 Samuel Rydh (samuel@ibrium.se)
+ *
+ *   Based upon misc.S from the the linux kernel with the following
+ *   copyrights:
+ *
+ *   Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org),
+ *   Cort Dougan (cort@cs.nmt.edu), Paul Mackerras
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation
+ *
+ */
+
+#include "asm/asmdefs.h"
+#include "asm/processor.h"
+
+
+/*
+ * Extended precision shifts.
+ *
+ * Updated to be valid for shift counts from 0 to 63 inclusive.
+ * -- Gabriel
+ *
+ * R3/R4 has 64 bit value
+ * R5    has shift count
+ * result in R3/R4
+ *
+ *  ashrdi3: arithmetic right shift (sign propagation)
+ *  lshrdi3: logical right shift
+ *  ashldi3: left shift
+ */
+GLOBL(__ashrdi3):
+	subfic	r6,r5,32
+	srw	r4,r4,r5	# LSW = count > 31 ? 0 : LSW >> count
+	addi	r7,r5,32	# could be xori, or addi with -32
+	slw	r6,r3,r6	# t1 = count > 31 ? 0 : MSW << (32-count)
+	rlwinm	r8,r7,0,32	# t3 = (count < 32) ? 32 : 0
+	sraw	r7,r3,r7	# t2 = MSW >> (count-32)
+	or	r4,r4,r6	# LSW |= t1
+	slw	r7,r7,r8	# t2 = (count < 32) ? 0 : t2
+	sraw	r3,r3,r5	# MSW = MSW >> count
+	or	r4,r4,r7	# LSW |= t2
+	blr
+
+GLOBL(__ashldi3):
+	subfic	r6,r5,32
+	slw	r3,r3,r5	# MSW = count > 31 ? 0 : MSW << count
+	addi	r7,r5,32	# could be xori, or addi with -32
+	srw	r6,r4,r6	# t1 = count > 31 ? 0 : LSW >> (32-count)
+	slw	r7,r4,r7	# t2 = count < 32 ? 0 : LSW << (count-32)
+	or	r3,r3,r6	# MSW |= t1
+	slw	r4,r4,r5	# LSW = LSW << count
+	or	r3,r3,r7	# MSW |= t2
+	blr
+
+GLOBL(__lshrdi3):
+	subfic	r6,r5,32
+	srw	r4,r4,r5	# LSW = count > 31 ? 0 : LSW >> count
+	addi	r7,r5,32	# could be xori, or addi with -32
+	slw	r6,r3,r6	# t1 = count > 31 ? 0 : MSW << (32-count)
+	srw	r7,r3,r7	# t2 = count < 32 ? 0 : MSW >> (count-32)
+	or	r4,r4,r6	# LSW |= t1
+	srw	r3,r3,r5	# MSW = MSW >> count
+	or	r4,r4,r7	# LSW |= t2
+	blr