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-rw-r--r--qemu/include/hw/acpi/acpi-defs.h9
-rw-r--r--qemu/include/hw/acpi/acpi.h11
-rw-r--r--qemu/include/hw/acpi/aml-build.h111
-rw-r--r--qemu/include/hw/acpi/bios-linker-loader.h4
-rw-r--r--qemu/include/hw/acpi/cpu_hotplug.h10
-rw-r--r--qemu/include/hw/acpi/ich9.h1
-rw-r--r--qemu/include/hw/acpi/memory_hotplug.h9
-rw-r--r--qemu/include/hw/acpi/pc-hotplug.h44
-rw-r--r--qemu/include/hw/acpi/pcihp.h2
-rw-r--r--qemu/include/hw/acpi/piix4.h2
-rw-r--r--qemu/include/hw/acpi/tco.h1
-rw-r--r--qemu/include/hw/arm/allwinner-a10.h4
-rw-r--r--qemu/include/hw/arm/arm.h32
-rw-r--r--qemu/include/hw/arm/ast2400.h35
-rw-r--r--qemu/include/hw/arm/bcm2835_peripherals.h48
-rw-r--r--qemu/include/hw/arm/bcm2836.h35
-rw-r--r--qemu/include/hw/arm/fsl-imx25.h249
-rw-r--r--qemu/include/hw/arm/fsl-imx31.h122
-rw-r--r--qemu/include/hw/arm/imx.h34
-rw-r--r--qemu/include/hw/arm/linux-boot-if.h43
-rw-r--r--qemu/include/hw/arm/raspi_platform.h128
-rw-r--r--qemu/include/hw/arm/virt-acpi-build.h3
-rw-r--r--qemu/include/hw/arm/virt.h8
-rw-r--r--qemu/include/hw/arm/xlnx-zynqmp.h29
-rw-r--r--qemu/include/hw/block/block.h1
-rw-r--r--qemu/include/hw/block/fdc.h11
-rw-r--r--qemu/include/hw/boards.h101
-rw-r--r--qemu/include/hw/bt.h21
-rw-r--r--qemu/include/hw/char/bcm2835_aux.h33
-rw-r--r--qemu/include/hw/char/digic-uart.h1
-rw-r--r--qemu/include/hw/char/imx_serial.h102
-rw-r--r--qemu/include/hw/compat.h153
-rw-r--r--qemu/include/hw/cpu/icc_bus.h82
-rw-r--r--qemu/include/hw/display/bcm2835_fb.h47
-rw-r--r--qemu/include/hw/dma/bcm2835_dma.h47
-rw-r--r--qemu/include/hw/elf_ops.h45
-rw-r--r--qemu/include/hw/gpio/imx_gpio.h63
-rw-r--r--qemu/include/hw/hotplug.h1
-rw-r--r--qemu/include/hw/hw.h6
-rw-r--r--qemu/include/hw/i2c/imx_i2c.h87
-rw-r--r--qemu/include/hw/i386/apic_internal.h104
-rw-r--r--qemu/include/hw/i386/ich9.h6
-rw-r--r--qemu/include/hw/i386/intel_iommu.h17
-rw-r--r--qemu/include/hw/i386/ioapic_internal.h7
-rw-r--r--qemu/include/hw/i386/pc.h924
-rw-r--r--qemu/include/hw/i386/topology.h35
-rw-r--r--qemu/include/hw/input/adb.h2
-rw-r--r--qemu/include/hw/intc/arm_gic_common.h16
-rw-r--r--qemu/include/hw/intc/arm_gicv3_common.h68
-rw-r--r--qemu/include/hw/intc/aspeed_vic.h48
-rw-r--r--qemu/include/hw/intc/bcm2835_ic.h33
-rw-r--r--qemu/include/hw/intc/bcm2836_control.h51
-rw-r--r--qemu/include/hw/intc/imx_avic.h55
-rw-r--r--qemu/include/hw/ipmi/ipmi.h258
-rw-r--r--qemu/include/hw/isa/apm.h1
-rw-r--r--qemu/include/hw/isa/i8257.h42
-rw-r--r--qemu/include/hw/isa/isa.h56
-rw-r--r--qemu/include/hw/loader.h61
-rw-r--r--qemu/include/hw/mem/nvdimm.h62
-rw-r--r--qemu/include/hw/mem/pc-dimm.h2
-rw-r--r--qemu/include/hw/mips/cps.h46
-rw-r--r--qemu/include/hw/misc/bcm2835_mbox.h38
-rw-r--r--qemu/include/hw/misc/bcm2835_mbox_defs.h27
-rw-r--r--qemu/include/hw/misc/bcm2835_property.h35
-rw-r--r--qemu/include/hw/misc/imx25_ccm.h79
-rw-r--r--qemu/include/hw/misc/imx31_ccm.h88
-rw-r--r--qemu/include/hw/misc/imx6_ccm.h197
-rw-r--r--qemu/include/hw/misc/imx_ccm.h64
-rw-r--r--qemu/include/hw/misc/ivshmem.h25
-rw-r--r--qemu/include/hw/misc/mips_cmgcr.h59
-rw-r--r--qemu/include/hw/misc/mips_cpc.h47
-rw-r--r--qemu/include/hw/misc/mips_itu.h72
-rw-r--r--qemu/include/hw/misc/zynq-xadc.h46
-rw-r--r--qemu/include/hw/net/imx_fec.h113
-rw-r--r--qemu/include/hw/nvram/fw_cfg.h201
-rw-r--r--qemu/include/hw/nvram/fw_cfg_keys.h46
-rw-r--r--qemu/include/hw/pci-host/q35.h1
-rw-r--r--qemu/include/hw/pci-host/spapr.h67
-rw-r--r--qemu/include/hw/pci/msi.h2
-rw-r--r--qemu/include/hw/pci/msix.h16
-rw-r--r--qemu/include/hw/pci/pci-assign.h27
-rw-r--r--qemu/include/hw/pci/pci.h19
-rw-r--r--qemu/include/hw/pci/pci_bridge.h2
-rw-r--r--qemu/include/hw/pci/pci_ids.h1
-rw-r--r--qemu/include/hw/pci/pcie_aer.h3
-rw-r--r--qemu/include/hw/pci/shpc.h1
-rw-r--r--qemu/include/hw/ppc/mac_dbdma.h1
-rw-r--r--qemu/include/hw/ppc/spapr.h102
-rw-r--r--qemu/include/hw/ppc/spapr_drc.h31
-rw-r--r--qemu/include/hw/ppc/spapr_vio.h2
-rw-r--r--qemu/include/hw/ppc/xics.h5
-rw-r--r--qemu/include/hw/qdev-core.h20
-rw-r--r--qemu/include/hw/qdev-properties.h6
-rw-r--r--qemu/include/hw/s390x/event-facility.h12
-rw-r--r--qemu/include/hw/s390x/s390-virtio-ccw.h40
-rw-r--r--qemu/include/hw/s390x/sclp.h33
-rw-r--r--qemu/include/hw/s390x/storage-keys.h60
-rw-r--r--qemu/include/hw/scsi/scsi.h5
-rw-r--r--qemu/include/hw/sd/sd.h (renamed from qemu/include/hw/sd.h)65
-rw-r--r--qemu/include/hw/sd/sdhci.h95
-rw-r--r--qemu/include/hw/smbios/smbios.h (renamed from qemu/include/hw/i386/smbios.h)64
-rw-r--r--qemu/include/hw/ssi/ssi.h (renamed from qemu/include/hw/ssi.h)10
-rw-r--r--qemu/include/hw/ssi/xilinx_spips.h72
-rw-r--r--qemu/include/hw/timer/aspeed_timer.h59
-rw-r--r--qemu/include/hw/timer/digic-timer.h1
-rw-r--r--qemu/include/hw/timer/hpet.h5
-rw-r--r--qemu/include/hw/timer/imx_epit.h80
-rw-r--r--qemu/include/hw/timer/imx_gpt.h108
-rw-r--r--qemu/include/hw/usb.h1
-rw-r--r--qemu/include/hw/vfio/vfio-amd-xgbe.h51
-rw-r--r--qemu/include/hw/vfio/vfio-common.h61
-rw-r--r--qemu/include/hw/vfio/vfio-platform.h4
-rw-r--r--qemu/include/hw/vfio/vfio.h6
-rw-r--r--qemu/include/hw/virtio/dataplane/vring-accessors.h75
-rw-r--r--qemu/include/hw/virtio/dataplane/vring.h49
-rw-r--r--qemu/include/hw/virtio/vhost-backend.h76
-rw-r--r--qemu/include/hw/virtio/vhost-scsi.h25
-rw-r--r--qemu/include/hw/virtio/vhost.h16
-rw-r--r--qemu/include/hw/virtio/virtio-9p.h24
-rw-r--r--qemu/include/hw/virtio/virtio-access.h30
-rw-r--r--qemu/include/hw/virtio/virtio-balloon.h2
-rw-r--r--qemu/include/hw/virtio/virtio-blk.h13
-rw-r--r--qemu/include/hw/virtio/virtio-bus.h8
-rw-r--r--qemu/include/hw/virtio/virtio-gpu.h26
-rw-r--r--qemu/include/hw/virtio/virtio-input.h17
-rw-r--r--qemu/include/hw/virtio/virtio-net.h4
-rw-r--r--qemu/include/hw/virtio/virtio-scsi.h53
-rw-r--r--qemu/include/hw/virtio/virtio-serial.h2
-rw-r--r--qemu/include/hw/virtio/virtio.h35
-rw-r--r--qemu/include/hw/xen/xen.h11
-rw-r--r--qemu/include/hw/xen/xen_backend.h7
-rw-r--r--qemu/include/hw/xen/xen_common.h274
132 files changed, 5328 insertions, 1363 deletions
diff --git a/qemu/include/hw/acpi/acpi-defs.h b/qemu/include/hw/acpi/acpi-defs.h
index 2b431e624..c7a03d43b 100644
--- a/qemu/include/hw/acpi/acpi-defs.h
+++ b/qemu/include/hw/acpi/acpi-defs.h
@@ -384,6 +384,15 @@ struct AcpiMadtGenericMsiFrame {
typedef struct AcpiMadtGenericMsiFrame AcpiMadtGenericMsiFrame;
+struct AcpiMadtGenericRedistributor {
+ ACPI_SUB_HEADER_DEF
+ uint16_t reserved;
+ uint64_t base_address;
+ uint32_t range_length;
+} QEMU_PACKED;
+
+typedef struct AcpiMadtGenericRedistributor AcpiMadtGenericRedistributor;
+
/*
* Generic Timer Description Table (GTDT)
*/
diff --git a/qemu/include/hw/acpi/acpi.h b/qemu/include/hw/acpi/acpi.h
index b20bd55a6..e0978c8b9 100644
--- a/qemu/include/hw/acpi/acpi.h
+++ b/qemu/include/hw/acpi/acpi.h
@@ -19,8 +19,6 @@
* <http://www.gnu.org/licenses/>.
*/
-#include "qapi/error.h"
-#include "qemu/typedefs.h"
#include "qemu/notify.h"
#include "qemu/option.h"
#include "exec/memory.h"
@@ -156,7 +154,7 @@ void acpi_pm_tmr_reset(ACPIREGS *ar);
static inline int64_t acpi_pm_tmr_get_clock(void)
{
return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), PM_TIMER_FREQUENCY,
- get_ticks_per_sec());
+ NANOSECONDS_PER_SECOND);
}
/* PM1a_EVT: piix and ich9 don't implement PM1b. */
@@ -196,4 +194,11 @@ unsigned acpi_table_len(void *current);
void acpi_table_add(const QemuOpts *opts, Error **errp);
void acpi_table_add_builtin(const QemuOpts *opts, Error **errp);
+typedef struct AcpiSlicOem AcpiSlicOem;
+struct AcpiSlicOem {
+ char *id;
+ char *table_id;
+};
+int acpi_get_slic_oem(AcpiSlicOem *oem);
+
#endif /* !QEMU_HW_ACPI_H */
diff --git a/qemu/include/hw/acpi/aml-build.h b/qemu/include/hw/acpi/aml-build.h
index e3afa1367..2c994b351 100644
--- a/qemu/include/hw/acpi/aml-build.h
+++ b/qemu/include/hw/acpi/aml-build.h
@@ -1,15 +1,12 @@
#ifndef HW_ACPI_GEN_UTILS_H
#define HW_ACPI_GEN_UTILS_H
-#include <stdint.h>
#include <glib.h>
-#include "qemu/compiler.h"
#include "hw/acpi/acpi-defs.h"
/* Reserve RAM space for tables: add another order of magnitude. */
#define ACPI_BUILD_TABLE_MAX_SIZE 0x200000
-#define ACPI_BUILD_APPNAME "Bochs"
#define ACPI_BUILD_APPNAME6 "BOCHS "
#define ACPI_BUILD_APPNAME4 "BXPC"
@@ -17,6 +14,8 @@
#define ACPI_BUILD_RSDP_FILE "etc/acpi/rsdp"
#define ACPI_BUILD_TPMLOG_FILE "etc/tpm/log"
+#define AML_NOTIFY_METHOD "NTFY"
+
typedef enum {
AML_NO_OPCODE = 0,/* has only data */
AML_OPCODE, /* has opcode optionally followed by data */
@@ -36,6 +35,24 @@ struct Aml {
typedef struct Aml Aml;
typedef enum {
+ AML_COMPATIBILITY = 0,
+ AML_TYPEA = 1,
+ AML_TYPEB = 2,
+ AML_TYPEF = 3,
+} AmlDmaType;
+
+typedef enum {
+ AML_NOTBUSMASTER = 0,
+ AML_BUSMASTER = 1,
+} AmlDmaBusMaster;
+
+typedef enum {
+ AML_TRANSFER8 = 0,
+ AML_TRANSFER8_16 = 1,
+ AML_TRANSFER16 = 2,
+} AmlTransferSize;
+
+typedef enum {
AML_DECODE10 = 0,
AML_DECODE16 = 1,
} AmlIODecode;
@@ -50,6 +67,11 @@ typedef enum {
} AmlAccessType;
typedef enum {
+ AML_NOLOCK = 0,
+ AML_LOCK = 1,
+} AmlLockRule;
+
+typedef enum {
AML_PRESERVE = 0,
AML_WRITE_AS_ONES = 1,
AML_WRITE_AS_ZEROS = 2,
@@ -58,6 +80,7 @@ typedef enum {
typedef enum {
AML_SYSTEM_MEMORY = 0X00,
AML_SYSTEM_IO = 0X01,
+ AML_PCI_CONFIG = 0X02,
} AmlRegionSpace;
typedef enum {
@@ -149,6 +172,32 @@ typedef enum {
AML_SHARED_AND_WAKE = 3,
} AmlShared;
+/* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: MethodFlags */
+typedef enum {
+ AML_NOTSERIALIZED = 0,
+ AML_SERIALIZED = 1,
+} AmlSerializeFlag;
+
+/*
+ * ACPI 5.0: Table 6-189 GPIO Connection Descriptor Definition
+ * GPIO Connection Type
+ */
+typedef enum {
+ AML_INTERRUPT_CONNECTION = 0,
+ AML_IO_CONNECTION = 1,
+} AmlGpioConnectionType;
+
+/*
+ * ACPI 5.0: Table 6-189 GPIO Connection Descriptor Definition
+ * _PPI field definition
+ */
+typedef enum {
+ AML_PULL_DEFAULT = 0,
+ AML_PULL_UP = 1,
+ AML_PULL_DOWN = 2,
+ AML_PULL_NONE = 3,
+} AmlPinConfig;
+
typedef
struct AcpiBuildTables {
GArray *table_data;
@@ -199,30 +248,44 @@ Aml *aml_name_decl(const char *name, Aml *val);
Aml *aml_return(Aml *val);
Aml *aml_int(const uint64_t val);
Aml *aml_arg(int pos);
+Aml *aml_to_integer(Aml *arg);
+Aml *aml_to_hexstring(Aml *src, Aml *dst);
+Aml *aml_to_buffer(Aml *src, Aml *dst);
Aml *aml_store(Aml *val, Aml *target);
-Aml *aml_and(Aml *arg1, Aml *arg2);
-Aml *aml_or(Aml *arg1, Aml *arg2);
+Aml *aml_and(Aml *arg1, Aml *arg2, Aml *dst);
+Aml *aml_or(Aml *arg1, Aml *arg2, Aml *dst);
+Aml *aml_lor(Aml *arg1, Aml *arg2);
Aml *aml_shiftleft(Aml *arg1, Aml *count);
-Aml *aml_shiftright(Aml *arg1, Aml *count);
+Aml *aml_shiftright(Aml *arg1, Aml *count, Aml *dst);
Aml *aml_lless(Aml *arg1, Aml *arg2);
-Aml *aml_add(Aml *arg1, Aml *arg2);
+Aml *aml_add(Aml *arg1, Aml *arg2, Aml *dst);
+Aml *aml_subtract(Aml *arg1, Aml *arg2, Aml *dst);
Aml *aml_increment(Aml *arg);
+Aml *aml_decrement(Aml *arg);
Aml *aml_index(Aml *arg1, Aml *idx);
Aml *aml_notify(Aml *arg1, Aml *arg2);
+Aml *aml_call0(const char *method);
Aml *aml_call1(const char *method, Aml *arg1);
Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3);
Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4);
+Aml *aml_gpio_int(AmlConsumerAndProducer con_and_pro,
+ AmlLevelAndEdge edge_level,
+ AmlActiveHighAndLow active_level, AmlShared shared,
+ AmlPinConfig pin_config, uint16_t debounce_timeout,
+ const uint32_t pin_list[], uint32_t pin_count,
+ const char *resource_source_name,
+ const uint8_t *vendor_data, uint16_t vendor_data_len);
Aml *aml_memory32_fixed(uint32_t addr, uint32_t size,
AmlReadAndWrite read_and_write);
Aml *aml_interrupt(AmlConsumerAndProducer con_and_pro,
AmlLevelAndEdge level_and_edge,
AmlActiveHighAndLow high_and_low, AmlShared shared,
- uint32_t irq);
+ uint32_t *irq_list, uint8_t irq_count);
Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
uint8_t aln, uint8_t len);
Aml *aml_operation_region(const char *name, AmlRegionSpace rs,
- uint32_t offset, uint32_t len);
+ Aml *offset, uint32_t len);
Aml *aml_irq_no_flags(uint8_t irq);
Aml *aml_named_field(const char *name, unsigned length);
Aml *aml_reserved_field(unsigned length);
@@ -230,6 +293,8 @@ Aml *aml_local(int num);
Aml *aml_string(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
Aml *aml_lnot(Aml *arg);
Aml *aml_equal(Aml *arg1, Aml *arg2);
+Aml *aml_lgreater(Aml *arg1, Aml *arg2);
+Aml *aml_lgreater_equal(Aml *arg1, Aml *arg2);
Aml *aml_processor(uint8_t proc_id, uint32_t pblk_addr, uint8_t pblk_len,
const char *name_format, ...) GCC_FMT_ATTR(4, 5);
Aml *aml_eisaid(const char *str);
@@ -259,32 +324,52 @@ Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed,
uint64_t addr_gran, uint64_t addr_min,
uint64_t addr_max, uint64_t addr_trans,
uint64_t len);
+Aml *aml_dma(AmlDmaType typ, AmlDmaBusMaster bm, AmlTransferSize sz,
+ uint8_t channel);
+Aml *aml_sleep(uint64_t msec);
/* Block AML object primitives */
Aml *aml_scope(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
Aml *aml_device(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
-Aml *aml_method(const char *name, int arg_count);
+Aml *aml_method(const char *name, int arg_count, AmlSerializeFlag sflag);
Aml *aml_if(Aml *predicate);
Aml *aml_else(void);
Aml *aml_while(Aml *predicate);
Aml *aml_package(uint8_t num_elements);
Aml *aml_buffer(int buffer_size, uint8_t *byte_list);
Aml *aml_resource_template(void);
-Aml *aml_field(const char *name, AmlAccessType type, AmlUpdateRule rule);
+Aml *aml_field(const char *name, AmlAccessType type, AmlLockRule lock,
+ AmlUpdateRule rule);
+Aml *aml_mutex(const char *name, uint8_t sync_level);
+Aml *aml_acquire(Aml *mutex, uint16_t timeout);
+Aml *aml_release(Aml *mutex);
+Aml *aml_alias(const char *source_object, const char *alias_object);
+Aml *aml_create_field(Aml *srcbuf, Aml *bit_index, Aml *num_bits,
+ const char *name);
Aml *aml_create_dword_field(Aml *srcbuf, Aml *index, const char *name);
+Aml *aml_create_qword_field(Aml *srcbuf, Aml *index, const char *name);
Aml *aml_varpackage(uint32_t num_elements);
Aml *aml_touuid(const char *uuid);
Aml *aml_unicode(const char *str);
+Aml *aml_derefof(Aml *arg);
+Aml *aml_sizeof(Aml *arg);
+Aml *aml_concatenate(Aml *source1, Aml *source2, Aml *target);
void
build_header(GArray *linker, GArray *table_data,
- AcpiTableHeader *h, const char *sig, int len, uint8_t rev);
+ AcpiTableHeader *h, const char *sig, int len, uint8_t rev,
+ const char *oem_id, const char *oem_table_id);
void *acpi_data_push(GArray *table_data, unsigned size);
unsigned acpi_data_len(GArray *table);
void acpi_add_table(GArray *table_offsets, GArray *table_data);
void acpi_build_tables_init(AcpiBuildTables *tables);
void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre);
void
-build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets);
+build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets,
+ const char *oem_id, const char *oem_table_id);
+
+int
+build_append_named_dword(GArray *array, const char *name_format, ...)
+GCC_FMT_ATTR(2, 3);
#endif
diff --git a/qemu/include/hw/acpi/bios-linker-loader.h b/qemu/include/hw/acpi/bios-linker-loader.h
index 498c0af77..82f1af643 100644
--- a/qemu/include/hw/acpi/bios-linker-loader.h
+++ b/qemu/include/hw/acpi/bios-linker-loader.h
@@ -2,8 +2,6 @@
#define BIOS_LINKER_LOADER_H
#include <glib.h>
-#include <stdbool.h>
-#include <inttypes.h>
GArray *bios_linker_loader_init(void);
@@ -13,7 +11,7 @@ void bios_linker_loader_alloc(GArray *linker,
bool alloc_fseg);
void bios_linker_loader_add_checksum(GArray *linker, const char *file,
- void *table,
+ GArray *table,
void *start, unsigned size,
uint8_t *checksum);
diff --git a/qemu/include/hw/acpi/cpu_hotplug.h b/qemu/include/hw/acpi/cpu_hotplug.h
index f6d358def..f22640e38 100644
--- a/qemu/include/hw/acpi/cpu_hotplug.h
+++ b/qemu/include/hw/acpi/cpu_hotplug.h
@@ -14,6 +14,7 @@
#include "hw/acpi/acpi.h"
#include "hw/acpi/pc-hotplug.h"
+#include "hw/acpi/aml-build.h"
typedef struct AcpiCpuHotplug {
MemoryRegion io;
@@ -25,4 +26,13 @@ void acpi_cpu_plug_cb(ACPIREGS *ar, qemu_irq irq,
void acpi_cpu_hotplug_init(MemoryRegion *parent, Object *owner,
AcpiCpuHotplug *gpe_cpu, uint16_t base);
+
+#define CPU_EJECT_METHOD "CPEJ"
+#define CPU_MAT_METHOD "CPMA"
+#define CPU_ON_BITMAP "CPON"
+#define CPU_STATUS_METHOD "CPST"
+#define CPU_STATUS_MAP "PRS"
+#define CPU_SCAN_METHOD "PRSC"
+
+void build_cpu_hotplug_aml(Aml *ctx);
#endif
diff --git a/qemu/include/hw/acpi/ich9.h b/qemu/include/hw/acpi/ich9.h
index 345fd8d92..63fa19814 100644
--- a/qemu/include/hw/acpi/ich9.h
+++ b/qemu/include/hw/acpi/ich9.h
@@ -62,7 +62,6 @@ typedef struct ICH9LPCPMRegs {
void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
bool smm_enabled,
- bool enable_tco,
qemu_irq sci_irq);
void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
diff --git a/qemu/include/hw/acpi/memory_hotplug.h b/qemu/include/hw/acpi/memory_hotplug.h
index 1342adb08..3a646b12e 100644
--- a/qemu/include/hw/acpi/memory_hotplug.h
+++ b/qemu/include/hw/acpi/memory_hotplug.h
@@ -4,6 +4,7 @@
#include "hw/qdev-core.h"
#include "hw/acpi/acpi.h"
#include "migration/vmstate.h"
+#include "hw/acpi/aml-build.h"
/**
* MemStatus:
@@ -45,4 +46,12 @@ extern const VMStateDescription vmstate_memory_hotplug;
vmstate_memory_hotplug, MemHotplugState)
void acpi_memory_ospm_status(MemHotplugState *mem_st, ACPIOSTInfoList ***list);
+
+#define MEMORY_HOTPLUG_DEVICE "MHPD"
+#define MEMORY_SLOT_SCAN_METHOD "MSCN"
+#define MEMORY_HOTPLUG_HANDLER_PATH "\\_SB.PCI0." \
+ MEMORY_HOTPLUG_DEVICE "." MEMORY_SLOT_SCAN_METHOD
+
+void build_memory_hotplug_aml(Aml *ctx, uint32_t nr_mem,
+ uint16_t io_base, uint16_t io_len);
#endif
diff --git a/qemu/include/hw/acpi/pc-hotplug.h b/qemu/include/hw/acpi/pc-hotplug.h
index 77b156900..6a8d268f8 100644
--- a/qemu/include/hw/acpi/pc-hotplug.h
+++ b/qemu/include/hw/acpi/pc-hotplug.h
@@ -32,28 +32,26 @@
#define ACPI_MEMORY_HOTPLUG_IO_LEN 24
#define ACPI_MEMORY_HOTPLUG_BASE 0x0a00
-#define MEMORY_HOTPLUG_DEVICE MHPD
-#define MEMORY_SLOTS_NUMBER MDNR
-#define MEMORY_HOTPLUG_IO_REGION HPMR
-#define MEMORY_SLOT_ADDR_LOW MRBL
-#define MEMORY_SLOT_ADDR_HIGH MRBH
-#define MEMORY_SLOT_SIZE_LOW MRLL
-#define MEMORY_SLOT_SIZE_HIGH MRLH
-#define MEMORY_SLOT_PROXIMITY MPX
-#define MEMORY_SLOT_ENABLED MES
-#define MEMORY_SLOT_INSERT_EVENT MINS
-#define MEMORY_SLOT_REMOVE_EVENT MRMV
-#define MEMORY_SLOT_EJECT MEJ
-#define MEMORY_SLOT_SLECTOR MSEL
-#define MEMORY_SLOT_OST_EVENT MOEV
-#define MEMORY_SLOT_OST_STATUS MOSC
-#define MEMORY_SLOT_LOCK MLCK
-#define MEMORY_SLOT_STATUS_METHOD MRST
-#define MEMORY_SLOT_CRS_METHOD MCRS
-#define MEMORY_SLOT_OST_METHOD MOST
-#define MEMORY_SLOT_PROXIMITY_METHOD MPXM
-#define MEMORY_SLOT_EJECT_METHOD MEJ0
-#define MEMORY_SLOT_NOTIFY_METHOD MTFY
-#define MEMORY_SLOT_SCAN_METHOD MSCN
+#define MEMORY_SLOTS_NUMBER "MDNR"
+#define MEMORY_HOTPLUG_IO_REGION "HPMR"
+#define MEMORY_SLOT_ADDR_LOW "MRBL"
+#define MEMORY_SLOT_ADDR_HIGH "MRBH"
+#define MEMORY_SLOT_SIZE_LOW "MRLL"
+#define MEMORY_SLOT_SIZE_HIGH "MRLH"
+#define MEMORY_SLOT_PROXIMITY "MPX"
+#define MEMORY_SLOT_ENABLED "MES"
+#define MEMORY_SLOT_INSERT_EVENT "MINS"
+#define MEMORY_SLOT_REMOVE_EVENT "MRMV"
+#define MEMORY_SLOT_EJECT "MEJ"
+#define MEMORY_SLOT_SLECTOR "MSEL"
+#define MEMORY_SLOT_OST_EVENT "MOEV"
+#define MEMORY_SLOT_OST_STATUS "MOSC"
+#define MEMORY_SLOT_LOCK "MLCK"
+#define MEMORY_SLOT_STATUS_METHOD "MRST"
+#define MEMORY_SLOT_CRS_METHOD "MCRS"
+#define MEMORY_SLOT_OST_METHOD "MOST"
+#define MEMORY_SLOT_PROXIMITY_METHOD "MPXM"
+#define MEMORY_SLOT_EJECT_METHOD "MEJ0"
+#define MEMORY_SLOT_NOTIFY_METHOD "MTFY"
#endif
diff --git a/qemu/include/hw/acpi/pcihp.h b/qemu/include/hw/acpi/pcihp.h
index f3526d4aa..79a43923e 100644
--- a/qemu/include/hw/acpi/pcihp.h
+++ b/qemu/include/hw/acpi/pcihp.h
@@ -27,8 +27,6 @@
#ifndef HW_ACPI_PCIHP_H
#define HW_ACPI_PCIHP_H
-#include <inttypes.h>
-#include <qemu/typedefs.h>
#include "hw/acpi/acpi.h"
#include "migration/vmstate.h"
diff --git a/qemu/include/hw/acpi/piix4.h b/qemu/include/hw/acpi/piix4.h
index 65e6fd7aa..26c2370e3 100644
--- a/qemu/include/hw/acpi/piix4.h
+++ b/qemu/include/hw/acpi/piix4.h
@@ -1,8 +1,6 @@
#ifndef HW_ACPI_PIIX4_H
#define HW_ACPI_PIIX4_H
-#include "qemu/typedefs.h"
-
Object *piix4_pm_find(void);
#endif
diff --git a/qemu/include/hw/acpi/tco.h b/qemu/include/hw/acpi/tco.h
index c63afc8ca..52ad767dd 100644
--- a/qemu/include/hw/acpi/tco.h
+++ b/qemu/include/hw/acpi/tco.h
@@ -9,7 +9,6 @@
#ifndef HW_ACPI_TCO_H
#define HW_ACPI_TCO_H
-#include "qemu/typedefs.h"
#include "qemu-common.h"
/* As per ICH9 spec, the internal timer has an error of ~0.6s on every tick */
diff --git a/qemu/include/hw/arm/allwinner-a10.h b/qemu/include/hw/arm/allwinner-a10.h
index 01a189bcd..6b32a99e2 100644
--- a/qemu/include/hw/arm/allwinner-a10.h
+++ b/qemu/include/hw/arm/allwinner-a10.h
@@ -7,6 +7,8 @@
#include "hw/timer/allwinner-a10-pit.h"
#include "hw/intc/allwinner-a10-pic.h"
#include "hw/net/allwinner_emac.h"
+#include "hw/ide/pci.h"
+#include "hw/ide/ahci.h"
#include "sysemu/sysemu.h"
#include "exec/address-spaces.h"
@@ -16,6 +18,7 @@
#define AW_A10_PIT_REG_BASE 0x01c20c00
#define AW_A10_UART0_REG_BASE 0x01c28000
#define AW_A10_EMAC_BASE 0x01c0b000
+#define AW_A10_SATA_BASE 0x01c18000
#define AW_A10_SDRAM_BASE 0x40000000
@@ -32,6 +35,7 @@ typedef struct AwA10State {
AwA10PITState timer;
AwA10PICState intc;
AwEmacState emac;
+ AllwinnerAHCIState sata;
} AwA10State;
#define ALLWINNER_H_
diff --git a/qemu/include/hw/arm/arm.h b/qemu/include/hw/arm/arm.h
index 4dcd4f9b6..b2517f9a4 100644
--- a/qemu/include/hw/arm/arm.h
+++ b/qemu/include/hw/arm/arm.h
@@ -16,8 +16,15 @@
#include "qemu/notify.h"
#include "cpu.h"
+typedef enum {
+ ARM_ENDIANNESS_UNKNOWN = 0,
+ ARM_ENDIANNESS_LE,
+ ARM_ENDIANNESS_BE8,
+ ARM_ENDIANNESS_BE32,
+} arm_endianness;
+
/* armv7m.c */
-qemu_irq *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
+DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
const char *kernel_filename, const char *cpu_model);
/*
@@ -87,6 +94,24 @@ struct arm_boot_info {
* -pflash. It also implies that fw_cfg_find() will succeed.
*/
bool firmware_loaded;
+
+ /* Address at which board specific loader/setup code exists. If enabled,
+ * this code-blob will run before anything else. It must return to the
+ * caller via the link register. There is no stack set up. Enabled by
+ * defining write_board_setup, which is responsible for loading the blob
+ * to the specified address.
+ */
+ hwaddr board_setup_addr;
+ void (*write_board_setup)(ARMCPU *cpu,
+ const struct arm_boot_info *info);
+
+ /* If set, the board specific loader/setup blob will be run from secure
+ * mode, regardless of secure_boot. The blob becomes responsible for
+ * changing to non-secure state if implementing a non-secure boot
+ */
+ bool secure_board_setup;
+
+ arm_endianness endianness;
};
/**
@@ -106,6 +131,11 @@ struct arm_boot_info {
*/
void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info);
+/* Write a secure board setup routine with a dummy handler for SMCs */
+void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
+ const struct arm_boot_info *info,
+ hwaddr mvbar_addr);
+
/* Multiplication factor to convert from system clock ticks to qemu timer
ticks. */
extern int system_clock_scale;
diff --git a/qemu/include/hw/arm/ast2400.h b/qemu/include/hw/arm/ast2400.h
new file mode 100644
index 000000000..f16a1ed25
--- /dev/null
+++ b/qemu/include/hw/arm/ast2400.h
@@ -0,0 +1,35 @@
+/*
+ * ASPEED AST2400 SoC
+ *
+ * Andrew Jeffery <andrew@aj.id.au>
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#ifndef AST2400_H
+#define AST2400_H
+
+#include "hw/arm/arm.h"
+#include "hw/intc/aspeed_vic.h"
+#include "hw/timer/aspeed_timer.h"
+
+typedef struct AST2400State {
+ /*< private >*/
+ DeviceState parent;
+
+ /*< public >*/
+ ARMCPU *cpu;
+ MemoryRegion iomem;
+ AspeedVICState vic;
+ AspeedTimerCtrlState timerctrl;
+} AST2400State;
+
+#define TYPE_AST2400 "ast2400"
+#define AST2400(obj) OBJECT_CHECK(AST2400State, (obj), TYPE_AST2400)
+
+#define AST2400_SDRAM_BASE 0x40000000
+
+#endif /* AST2400_H */
diff --git a/qemu/include/hw/arm/bcm2835_peripherals.h b/qemu/include/hw/arm/bcm2835_peripherals.h
new file mode 100644
index 000000000..e12ae3721
--- /dev/null
+++ b/qemu/include/hw/arm/bcm2835_peripherals.h
@@ -0,0 +1,48 @@
+/*
+ * Raspberry Pi emulation (c) 2012 Gregory Estrade
+ * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
+ *
+ * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
+ * Written by Andrew Baumann
+ *
+ * This code is licensed under the GNU GPLv2 and later.
+ */
+
+#ifndef BCM2835_PERIPHERALS_H
+#define BCM2835_PERIPHERALS_H
+
+#include "qemu-common.h"
+#include "exec/address-spaces.h"
+#include "hw/sysbus.h"
+#include "hw/char/bcm2835_aux.h"
+#include "hw/display/bcm2835_fb.h"
+#include "hw/dma/bcm2835_dma.h"
+#include "hw/intc/bcm2835_ic.h"
+#include "hw/misc/bcm2835_property.h"
+#include "hw/misc/bcm2835_mbox.h"
+#include "hw/sd/sdhci.h"
+
+#define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals"
+#define BCM2835_PERIPHERALS(obj) \
+ OBJECT_CHECK(BCM2835PeripheralState, (obj), TYPE_BCM2835_PERIPHERALS)
+
+typedef struct BCM2835PeripheralState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ MemoryRegion peri_mr, peri_mr_alias, gpu_bus_mr, mbox_mr;
+ MemoryRegion ram_alias[4];
+ qemu_irq irq, fiq;
+
+ SysBusDevice *uart0;
+ BCM2835AuxState aux;
+ BCM2835FBState fb;
+ BCM2835DMAState dma;
+ BCM2835ICState ic;
+ BCM2835PropertyState property;
+ BCM2835MboxState mboxes;
+ SDHCIState sdhci;
+} BCM2835PeripheralState;
+
+#endif /* BCM2835_PERIPHERALS_H */
diff --git a/qemu/include/hw/arm/bcm2836.h b/qemu/include/hw/arm/bcm2836.h
new file mode 100644
index 000000000..76de1996a
--- /dev/null
+++ b/qemu/include/hw/arm/bcm2836.h
@@ -0,0 +1,35 @@
+/*
+ * Raspberry Pi emulation (c) 2012 Gregory Estrade
+ * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
+ *
+ * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
+ * Written by Andrew Baumann
+ *
+ * This code is licensed under the GNU GPLv2 and later.
+ */
+
+#ifndef BCM2836_H
+#define BCM2836_H
+
+#include "hw/arm/arm.h"
+#include "hw/arm/bcm2835_peripherals.h"
+#include "hw/intc/bcm2836_control.h"
+
+#define TYPE_BCM2836 "bcm2836"
+#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836)
+
+#define BCM2836_NCPUS 4
+
+typedef struct BCM2836State {
+ /*< private >*/
+ DeviceState parent_obj;
+ /*< public >*/
+
+ uint32_t enabled_cpus;
+
+ ARMCPU cpus[BCM2836_NCPUS];
+ BCM2836ControlState control;
+ BCM2835PeripheralState peripherals;
+} BCM2836State;
+
+#endif /* BCM2836_H */
diff --git a/qemu/include/hw/arm/fsl-imx25.h b/qemu/include/hw/arm/fsl-imx25.h
new file mode 100644
index 000000000..d0e8e9d95
--- /dev/null
+++ b/qemu/include/hw/arm/fsl-imx25.h
@@ -0,0 +1,249 @@
+/*
+ * Freescale i.MX25 SoC emulation
+ *
+ * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#ifndef FSL_IMX25_H
+#define FSL_IMX25_H
+
+#include "hw/arm/arm.h"
+#include "hw/intc/imx_avic.h"
+#include "hw/misc/imx25_ccm.h"
+#include "hw/char/imx_serial.h"
+#include "hw/timer/imx_gpt.h"
+#include "hw/timer/imx_epit.h"
+#include "hw/net/imx_fec.h"
+#include "hw/i2c/imx_i2c.h"
+#include "hw/gpio/imx_gpio.h"
+#include "exec/memory.h"
+
+#define TYPE_FSL_IMX25 "fsl,imx25"
+#define FSL_IMX25(obj) OBJECT_CHECK(FslIMX25State, (obj), TYPE_FSL_IMX25)
+
+#define FSL_IMX25_NUM_UARTS 5
+#define FSL_IMX25_NUM_GPTS 4
+#define FSL_IMX25_NUM_EPITS 2
+#define FSL_IMX25_NUM_I2CS 3
+#define FSL_IMX25_NUM_GPIOS 4
+
+typedef struct FslIMX25State {
+ /*< private >*/
+ DeviceState parent_obj;
+
+ /*< public >*/
+ ARMCPU cpu;
+ IMXAVICState avic;
+ IMX25CCMState ccm;
+ IMXSerialState uart[FSL_IMX25_NUM_UARTS];
+ IMXGPTState gpt[FSL_IMX25_NUM_GPTS];
+ IMXEPITState epit[FSL_IMX25_NUM_EPITS];
+ IMXFECState fec;
+ IMXI2CState i2c[FSL_IMX25_NUM_I2CS];
+ IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
+ MemoryRegion rom[2];
+ MemoryRegion iram;
+ MemoryRegion iram_alias;
+} FslIMX25State;
+
+/**
+ * i.MX25 memory map
+ ****************************************************************
+ * 0x0000_0000 0x0000_3FFF 16 Kbytes ROM (36 Kbytes)
+ * 0x0000_4000 0x0040_3FFF 4 Mbytes Reserved
+ * 0x0040_4000 0x0040_8FFF 20 Kbytes ROM (36 Kbytes)
+ * 0x0040_9000 0x0FFF_FFFF 252 Mbytes (minus 36 Kbytes) Reserved
+ * 0x1000_0000 0x1FFF_FFFF 256 Mbytes Reserved
+ * 0x2000_0000 0x2FFF_FFFF 256 Mbytes Reserved
+ * 0x3000_0000 0x3FFF_FFFF 256 Mbytes Reserved
+ * 0x4000_0000 0x43EF_FFFF 63 Mbytes Reserved
+ * 0x43F0_0000 0x43F0_3FFF 16 Kbytes AIPS A control registers
+ * 0x43F0_4000 0x43F0_7FFF 16 Kbytes ARM926 platform MAX
+ * 0x43F0_8000 0x43F0_BFFF 16 Kbytes ARM926 platform CLKCTL
+ * 0x43F0_C000 0x43F0_FFFF 16 Kbytes ARM926 platform ETB registers
+ * 0x43F1_0000 0x43F1_3FFF 16 Kbytes ARM926 platform ETB memory
+ * 0x43F1_4000 0x43F1_7FFF 16 Kbytes ARM926 platform AAPE registers
+ * 0x43F1_8000 0x43F7_FFFF 416 Kbytes Reserved
+ * 0x43F8_0000 0x43F8_3FFF 16 Kbytes I2C-1
+ * 0x43F8_4000 0x43F8_7FFF 16 Kbytes I2C-3
+ * 0x43F8_8000 0x43F8_BFFF 16 Kbytes CAN-1
+ * 0x43F8_C000 0x43F8_FFFF 16 Kbytes CAN-2
+ * 0x43F9_0000 0x43F9_3FFF 16 Kbytes UART-1
+ * 0x43F9_4000 0x43F9_7FFF 16 Kbytes UART-2
+ * 0x43F9_8000 0x43F9_BFFF 16 Kbytes I2C-2
+ * 0x43F9_C000 0x43F9_FFFF 16 Kbytes 1-Wire
+ * 0x43FA_0000 0x43FA_3FFF 16 Kbytes ATA (CPU side)
+ * 0x43FA_4000 0x43FA_7FFF 16 Kbytes CSPI-1
+ * 0x43FA_8000 0x43FA_BFFF 16 Kbytes KPP
+ * 0x43FA_C000 0x43FA_FFFF 16 Kbytes IOMUXC
+ * 0x43FB_0000 0x43FB_3FFF 16 Kbytes AUDMUX
+ * 0x43FB_4000 0x43FB_7FFF 16 Kbytes Reserved
+ * 0x43FB_8000 0x43FB_BFFF 16 Kbytes ECT (IP BUS A)
+ * 0x43FB_C000 0x43FB_FFFF 16 Kbytes ECT (IP BUS B)
+ * 0x43FC_0000 0x43FF_FFFF 256 Kbytes Reserved AIPS A off-platform slots
+ * 0x4400_0000 0x4FFF_FFFF 192 Mbytes Reserved
+ * 0x5000_0000 0x5000_3FFF 16 Kbytes SPBA base address
+ * 0x5000_4000 0x5000_7FFF 16 Kbytes CSPI-3
+ * 0x5000_8000 0x5000_BFFF 16 Kbytes UART-4
+ * 0x5000_C000 0x5000_FFFF 16 Kbytes UART-3
+ * 0x5001_0000 0x5001_3FFF 16 Kbytes CSPI-2
+ * 0x5001_4000 0x5001_7FFF 16 Kbytes SSI-2
+ * 0x5001_C000 0x5001_FFFF 16 Kbytes Reserved
+ * 0x5002_0000 0x5002_3FFF 16 Kbytes ATA
+ * 0x5002_4000 0x5002_7FFF 16 Kbytes SIM-1
+ * 0x5002_8000 0x5002_BFFF 16 Kbytes SIM-2
+ * 0x5002_C000 0x5002_FFFF 16 Kbytes UART-5
+ * 0x5003_0000 0x5003_3FFF 16 Kbytes TSC
+ * 0x5003_4000 0x5003_7FFF 16 Kbytes SSI-1
+ * 0x5003_8000 0x5003_BFFF 16 Kbytes FEC
+ * 0x5003_C000 0x5003_FFFF 16 Kbytes SPBA registers
+ * 0x5004_0000 0x51FF_FFFF 32 Mbytes (minus 256 Kbytes)
+ * 0x5200_0000 0x53EF_FFFF 31 Mbytes Reserved
+ * 0x53F0_0000 0x53F0_3FFF 16 Kbytes AIPS B control registers
+ * 0x53F0_4000 0x53F7_FFFF 496 Kbytes Reserved
+ * 0x53F8_0000 0x53F8_3FFF 16 Kbytes CCM
+ * 0x53F8_4000 0x53F8_7FFF 16 Kbytes GPT-4
+ * 0x53F8_8000 0x53F8_BFFF 16 Kbytes GPT-3
+ * 0x53F8_C000 0x53F8_FFFF 16 Kbytes GPT-2
+ * 0x53F9_0000 0x53F9_3FFF 16 Kbytes GPT-1
+ * 0x53F9_4000 0x53F9_7FFF 16 Kbytes EPIT-1
+ * 0x53F9_8000 0x53F9_BFFF 16 Kbytes EPIT-2
+ * 0x53F9_C000 0x53F9_FFFF 16 Kbytes GPIO-4
+ * 0x53FA_0000 0x53FA_3FFF 16 Kbytes PWM-2
+ * 0x53FA_4000 0x53FA_7FFF 16 Kbytes GPIO-3
+ * 0x53FA_8000 0x53FA_BFFF 16 Kbytes PWM-3
+ * 0x53FA_C000 0x53FA_FFFF 16 Kbytes SCC
+ * 0x53FB_0000 0x53FB_3FFF 16 Kbytes RNGB
+ * 0x53FB_4000 0x53FB_7FFF 16 Kbytes eSDHC-1
+ * 0x53FB_8000 0x53FB_BFFF 16 Kbytes eSDHC-2
+ * 0x53FB_C000 0x53FB_FFFF 16 Kbytes LCDC
+ * 0x53FC_0000 0x53FC_3FFF 16 Kbytes SLCDC
+ * 0x53FC_4000 0x53FC_7FFF 16 Kbytes Reserved
+ * 0x53FC_8000 0x53FC_BFFF 16 Kbytes PWM-4
+ * 0x53FC_C000 0x53FC_FFFF 16 Kbytes GPIO-1
+ * 0x53FD_0000 0x53FD_3FFF 16 Kbytes GPIO-2
+ * 0x53FD_4000 0x53FD_7FFF 16 Kbytes SDMA
+ * 0x53FD_8000 0x53FD_BFFF 16 Kbytes Reserved
+ * 0x53FD_C000 0x53FD_FFFF 16 Kbytes WDOG
+ * 0x53FE_0000 0x53FE_3FFF 16 Kbytes PWM-1
+ * 0x53FE_4000 0x53FE_7FFF 16 Kbytes Reserved
+ * 0x53FE_8000 0x53FE_BFFF 16 Kbytes Reserved
+ * 0x53FE_C000 0x53FE_FFFF 16 Kbytes RTICv3
+ * 0x53FF_0000 0x53FF_3FFF 16 Kbytes IIM
+ * 0x53FF_4000 0x53FF_7FFF 16 Kbytes USB
+ * 0x53FF_8000 0x53FF_BFFF 16 Kbytes CSI
+ * 0x53FF_C000 0x53FF_FFFF 16 Kbytes DryIce
+ * 0x5400_0000 0x5FFF_FFFF 192 Mbytes Reserved (aliased AIPS B slots)
+ * 0x6000_0000 0x67FF_FFFF 128 Mbytes ARM926 platform ROMPATCH
+ * 0x6800_0000 0x6FFF_FFFF 128 Mbytes ARM926 platform ASIC
+ * 0x7000_0000 0x77FF_FFFF 128 Mbytes Reserved
+ * 0x7800_0000 0x7801_FFFF 128 Kbytes RAM
+ * 0x7802_0000 0x7FFF_FFFF 128 Mbytes (minus 128 Kbytes)
+ * 0x8000_0000 0x8FFF_FFFF 256 Mbytes SDRAM bank 0
+ * 0x9000_0000 0x9FFF_FFFF 256 Mbytes SDRAM bank 1
+ * 0xA000_0000 0xA7FF_FFFF 128 Mbytes WEIM CS0 (flash 128) 1
+ * 0xA800_0000 0xAFFF_FFFF 128 Mbytes WEIM CS1 (flash 64) 1
+ * 0xB000_0000 0xB1FF_FFFF 32 Mbytes WEIM CS2 (SRAM)
+ * 0xB200_0000 0xB3FF_FFFF 32 Mbytes WEIM CS3 (SRAM)
+ * 0xB400_0000 0xB5FF_FFFF 32 Mbytes WEIM CS4
+ * 0xB600_0000 0xB7FF_FFFF 32 Mbytes Reserved
+ * 0xB800_0000 0xB800_0FFF 4 Kbytes Reserved
+ * 0xB800_1000 0xB800_1FFF 4 Kbytes SDRAM control registers
+ * 0xB800_2000 0xB800_2FFF 4 Kbytes WEIM control registers
+ * 0xB800_3000 0xB800_3FFF 4 Kbytes M3IF control registers
+ * 0xB800_4000 0xB800_4FFF 4 Kbytes EMI control registers
+ * 0xB800_5000 0xBAFF_FFFF 32 Mbytes (minus 20 Kbytes)
+ * 0xBB00_0000 0xBB00_0FFF 4 Kbytes NAND flash main area buffer
+ * 0xBB00_1000 0xBB00_11FF 512 B NAND flash spare area buffer
+ * 0xBB00_1200 0xBB00_1DFF 3 Kbytes Reserved
+ * 0xBB00_1E00 0xBB00_1FFF 512 B NAND flash control regisers
+ * 0xBB01_2000 0xBFFF_FFFF 96 Mbytes (minus 8 Kbytes) Reserved
+ * 0xC000_0000 0xFFFF_FFFF 1024 Mbytes Reserved
+ */
+
+#define FSL_IMX25_ROM0_ADDR 0x00000000
+#define FSL_IMX25_ROM0_SIZE 0x4000
+#define FSL_IMX25_ROM1_ADDR 0x00404000
+#define FSL_IMX25_ROM1_SIZE 0x4000
+#define FSL_IMX25_I2C1_ADDR 0x43F80000
+#define FSL_IMX25_I2C1_SIZE 0x4000
+#define FSL_IMX25_I2C3_ADDR 0x43F84000
+#define FSL_IMX25_I2C3_SIZE 0x4000
+#define FSL_IMX25_UART1_ADDR 0x43F90000
+#define FSL_IMX25_UART1_SIZE 0x4000
+#define FSL_IMX25_UART2_ADDR 0x43F94000
+#define FSL_IMX25_UART2_SIZE 0x4000
+#define FSL_IMX25_I2C2_ADDR 0x43F98000
+#define FSL_IMX25_I2C2_SIZE 0x4000
+#define FSL_IMX25_UART4_ADDR 0x50008000
+#define FSL_IMX25_UART4_SIZE 0x4000
+#define FSL_IMX25_UART3_ADDR 0x5000C000
+#define FSL_IMX25_UART3_SIZE 0x4000
+#define FSL_IMX25_UART5_ADDR 0x5002C000
+#define FSL_IMX25_UART5_SIZE 0x4000
+#define FSL_IMX25_FEC_ADDR 0x50038000
+#define FSL_IMX25_FEC_SIZE 0x4000
+#define FSL_IMX25_CCM_ADDR 0x53F80000
+#define FSL_IMX25_CCM_SIZE 0x4000
+#define FSL_IMX25_GPT4_ADDR 0x53F84000
+#define FSL_IMX25_GPT4_SIZE 0x4000
+#define FSL_IMX25_GPT3_ADDR 0x53F88000
+#define FSL_IMX25_GPT3_SIZE 0x4000
+#define FSL_IMX25_GPT2_ADDR 0x53F8C000
+#define FSL_IMX25_GPT2_SIZE 0x4000
+#define FSL_IMX25_GPT1_ADDR 0x53F90000
+#define FSL_IMX25_GPT1_SIZE 0x4000
+#define FSL_IMX25_EPIT1_ADDR 0x53F94000
+#define FSL_IMX25_EPIT1_SIZE 0x4000
+#define FSL_IMX25_EPIT2_ADDR 0x53F98000
+#define FSL_IMX25_EPIT2_SIZE 0x4000
+#define FSL_IMX25_GPIO4_ADDR 0x53F9C000
+#define FSL_IMX25_GPIO4_SIZE 0x4000
+#define FSL_IMX25_GPIO3_ADDR 0x53FA4000
+#define FSL_IMX25_GPIO3_SIZE 0x4000
+#define FSL_IMX25_GPIO1_ADDR 0x53FCC000
+#define FSL_IMX25_GPIO1_SIZE 0x4000
+#define FSL_IMX25_GPIO2_ADDR 0x53FD0000
+#define FSL_IMX25_GPIO2_SIZE 0x4000
+#define FSL_IMX25_AVIC_ADDR 0x68000000
+#define FSL_IMX25_AVIC_SIZE 0x4000
+#define FSL_IMX25_IRAM_ADDR 0x78000000
+#define FSL_IMX25_IRAM_SIZE 0x20000
+#define FSL_IMX25_IRAM_ALIAS_ADDR 0x78020000
+#define FSL_IMX25_IRAM_ALIAS_SIZE 0x7FE0000
+#define FSL_IMX25_SDRAM0_ADDR 0x80000000
+#define FSL_IMX25_SDRAM0_SIZE 0x10000000
+#define FSL_IMX25_SDRAM1_ADDR 0x90000000
+#define FSL_IMX25_SDRAM1_SIZE 0x10000000
+
+#define FSL_IMX25_UART1_IRQ 45
+#define FSL_IMX25_UART2_IRQ 32
+#define FSL_IMX25_UART3_IRQ 18
+#define FSL_IMX25_UART4_IRQ 5
+#define FSL_IMX25_UART5_IRQ 40
+#define FSL_IMX25_GPT1_IRQ 54
+#define FSL_IMX25_GPT2_IRQ 53
+#define FSL_IMX25_GPT3_IRQ 29
+#define FSL_IMX25_GPT4_IRQ 1
+#define FSL_IMX25_EPIT1_IRQ 28
+#define FSL_IMX25_EPIT2_IRQ 27
+#define FSL_IMX25_FEC_IRQ 57
+#define FSL_IMX25_I2C1_IRQ 3
+#define FSL_IMX25_I2C2_IRQ 4
+#define FSL_IMX25_I2C3_IRQ 10
+#define FSL_IMX25_GPIO1_IRQ 52
+#define FSL_IMX25_GPIO2_IRQ 51
+#define FSL_IMX25_GPIO3_IRQ 16
+#define FSL_IMX25_GPIO4_IRQ 23
+
+#endif /* FSL_IMX25_H */
diff --git a/qemu/include/hw/arm/fsl-imx31.h b/qemu/include/hw/arm/fsl-imx31.h
new file mode 100644
index 000000000..d408abbba
--- /dev/null
+++ b/qemu/include/hw/arm/fsl-imx31.h
@@ -0,0 +1,122 @@
+/*
+ * Freescale i.MX31 SoC emulation
+ *
+ * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#ifndef FSL_IMX31_H
+#define FSL_IMX31_H
+
+#include "hw/arm/arm.h"
+#include "hw/intc/imx_avic.h"
+#include "hw/misc/imx31_ccm.h"
+#include "hw/char/imx_serial.h"
+#include "hw/timer/imx_gpt.h"
+#include "hw/timer/imx_epit.h"
+#include "hw/i2c/imx_i2c.h"
+#include "hw/gpio/imx_gpio.h"
+#include "exec/memory.h"
+
+#define TYPE_FSL_IMX31 "fsl,imx31"
+#define FSL_IMX31(obj) OBJECT_CHECK(FslIMX31State, (obj), TYPE_FSL_IMX31)
+
+#define FSL_IMX31_NUM_UARTS 2
+#define FSL_IMX31_NUM_EPITS 2
+#define FSL_IMX31_NUM_I2CS 3
+#define FSL_IMX31_NUM_GPIOS 3
+
+typedef struct FslIMX31State {
+ /*< private >*/
+ DeviceState parent_obj;
+
+ /*< public >*/
+ ARMCPU cpu;
+ IMXAVICState avic;
+ IMX31CCMState ccm;
+ IMXSerialState uart[FSL_IMX31_NUM_UARTS];
+ IMXGPTState gpt;
+ IMXEPITState epit[FSL_IMX31_NUM_EPITS];
+ IMXI2CState i2c[FSL_IMX31_NUM_I2CS];
+ IMXGPIOState gpio[FSL_IMX31_NUM_GPIOS];
+ MemoryRegion secure_rom;
+ MemoryRegion rom;
+ MemoryRegion iram;
+ MemoryRegion iram_alias;
+} FslIMX31State;
+
+#define FSL_IMX31_SECURE_ROM_ADDR 0x00000000
+#define FSL_IMX31_SECURE_ROM_SIZE 0x4000
+#define FSL_IMX31_ROM_ADDR 0x00404000
+#define FSL_IMX31_ROM_SIZE 0x4000
+#define FSL_IMX31_IRAM_ALIAS_ADDR 0x10000000
+#define FSL_IMX31_IRAM_ALIAS_SIZE 0xFFC0000
+#define FSL_IMX31_IRAM_ADDR 0x1FFFC000
+#define FSL_IMX31_IRAM_SIZE 0x4000
+#define FSL_IMX31_I2C1_ADDR 0x43F80000
+#define FSL_IMX31_I2C1_SIZE 0x4000
+#define FSL_IMX31_I2C3_ADDR 0x43F84000
+#define FSL_IMX31_I2C3_SIZE 0x4000
+#define FSL_IMX31_UART1_ADDR 0x43F90000
+#define FSL_IMX31_UART1_SIZE 0x4000
+#define FSL_IMX31_UART2_ADDR 0x43F94000
+#define FSL_IMX31_UART2_SIZE 0x4000
+#define FSL_IMX31_I2C2_ADDR 0x43F98000
+#define FSL_IMX31_I2C2_SIZE 0x4000
+#define FSL_IMX31_CCM_ADDR 0x53F80000
+#define FSL_IMX31_CCM_SIZE 0x4000
+#define FSL_IMX31_GPT_ADDR 0x53F90000
+#define FSL_IMX31_GPT_SIZE 0x4000
+#define FSL_IMX31_EPIT1_ADDR 0x53F94000
+#define FSL_IMX31_EPIT1_SIZE 0x4000
+#define FSL_IMX31_EPIT2_ADDR 0x53F98000
+#define FSL_IMX31_EPIT2_SIZE 0x4000
+#define FSL_IMX31_GPIO3_ADDR 0x53FA4000
+#define FSL_IMX31_GPIO3_SIZE 0x4000
+#define FSL_IMX31_GPIO1_ADDR 0x53FCC000
+#define FSL_IMX31_GPIO1_SIZE 0x4000
+#define FSL_IMX31_GPIO2_ADDR 0x53FD0000
+#define FSL_IMX31_GPIO2_SIZE 0x4000
+#define FSL_IMX31_AVIC_ADDR 0x68000000
+#define FSL_IMX31_AVIC_SIZE 0x100
+#define FSL_IMX31_SDRAM0_ADDR 0x80000000
+#define FSL_IMX31_SDRAM0_SIZE 0x10000000
+#define FSL_IMX31_SDRAM1_ADDR 0x90000000
+#define FSL_IMX31_SDRAM1_SIZE 0x10000000
+#define FSL_IMX31_FLASH0_ADDR 0xA0000000
+#define FSL_IMX31_FLASH0_SIZE 0x8000000
+#define FSL_IMX31_FLASH1_ADDR 0xA8000000
+#define FSL_IMX31_FLASH1_SIZE 0x8000000
+#define FSL_IMX31_CS2_ADDR 0xB0000000
+#define FSL_IMX31_CS2_SIZE 0x2000000
+#define FSL_IMX31_CS3_ADDR 0xB2000000
+#define FSL_IMX31_CS3_SIZE 0x2000000
+#define FSL_IMX31_CS4_ADDR 0xB4000000
+#define FSL_IMX31_CS4_SIZE 0x2000000
+#define FSL_IMX31_CS5_ADDR 0xB6000000
+#define FSL_IMX31_CS5_SIZE 0x2000000
+#define FSL_IMX31_NAND_ADDR 0xB8000000
+#define FSL_IMX31_NAND_SIZE 0x1000
+
+#define FSL_IMX31_EPIT2_IRQ 27
+#define FSL_IMX31_EPIT1_IRQ 28
+#define FSL_IMX31_GPT_IRQ 29
+#define FSL_IMX31_UART2_IRQ 32
+#define FSL_IMX31_UART1_IRQ 45
+#define FSL_IMX31_I2C1_IRQ 10
+#define FSL_IMX31_I2C2_IRQ 4
+#define FSL_IMX31_I2C3_IRQ 3
+#define FSL_IMX31_GPIO1_IRQ 52
+#define FSL_IMX31_GPIO2_IRQ 51
+#define FSL_IMX31_GPIO3_IRQ 56
+
+#endif /* FSL_IMX31_H */
diff --git a/qemu/include/hw/arm/imx.h b/qemu/include/hw/arm/imx.h
deleted file mode 100644
index ea9e09327..000000000
--- a/qemu/include/hw/arm/imx.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * i.MX31 emulation
- *
- * Copyright (C) 2012 Peter Chubb
- * NICTA
- *
- * This code is released under the GPL, version 2.0 or later
- * See the file `../COPYING' for details.
- */
-
-#ifndef IMX_H
-#define IMX_H
-
-void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq);
-
-typedef enum {
- NOCLK,
- MCU,
- HSP,
- IPG,
- CLK_32k
-} IMXClk;
-
-uint32_t imx_clock_frequency(DeviceState *s, IMXClk clock);
-
-void imx_timerp_create(const hwaddr addr,
- qemu_irq irq,
- DeviceState *ccm);
-void imx_timerg_create(const hwaddr addr,
- qemu_irq irq,
- DeviceState *ccm);
-
-
-#endif /* IMX_H */
diff --git a/qemu/include/hw/arm/linux-boot-if.h b/qemu/include/hw/arm/linux-boot-if.h
new file mode 100644
index 000000000..aba4479a1
--- /dev/null
+++ b/qemu/include/hw/arm/linux-boot-if.h
@@ -0,0 +1,43 @@
+/*
+ * hw/arm/linux-boot-if.h : interface for devices which need to behave
+ * specially for direct boot of an ARM Linux kernel
+ */
+
+#ifndef HW_ARM_LINUX_BOOT_IF_H
+#define HW_ARM_LINUX_BOOT_IF_H
+
+#include "qom/object.h"
+
+#define TYPE_ARM_LINUX_BOOT_IF "arm-linux-boot-if"
+#define ARM_LINUX_BOOT_IF_CLASS(klass) \
+ OBJECT_CLASS_CHECK(ARMLinuxBootIfClass, (klass), TYPE_ARM_LINUX_BOOT_IF)
+#define ARM_LINUX_BOOT_IF_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(ARMLinuxBootIfClass, (obj), TYPE_ARM_LINUX_BOOT_IF)
+#define ARM_LINUX_BOOT_IF(obj) \
+ INTERFACE_CHECK(ARMLinuxBootIf, (obj), TYPE_ARM_LINUX_BOOT_IF)
+
+typedef struct ARMLinuxBootIf {
+ /*< private >*/
+ Object parent_obj;
+} ARMLinuxBootIf;
+
+typedef struct ARMLinuxBootIfClass {
+ /*< private >*/
+ InterfaceClass parent_class;
+
+ /*< public >*/
+ /** arm_linux_init: configure the device for a direct boot
+ * of an ARM Linux kernel (so that device reset puts it into
+ * the state the kernel expects after firmware initialization,
+ * rather than the true hardware reset state). This callback is
+ * called once after machine construction is complete (before the
+ * first system reset).
+ *
+ * @obj: the object implementing this interface
+ * @secure_boot: true if we are booting Secure, false for NonSecure
+ * (or for a CPU which doesn't support TrustZone)
+ */
+ void (*arm_linux_init)(ARMLinuxBootIf *obj, bool secure_boot);
+} ARMLinuxBootIfClass;
+
+#endif
diff --git a/qemu/include/hw/arm/raspi_platform.h b/qemu/include/hw/arm/raspi_platform.h
new file mode 100644
index 000000000..6467e88ae
--- /dev/null
+++ b/qemu/include/hw/arm/raspi_platform.h
@@ -0,0 +1,128 @@
+/*
+ * bcm2708 aka bcm2835/2836 aka Raspberry Pi/Pi2 SoC platform defines
+ *
+ * These definitions are derived from those in Raspbian Linux at
+ * arch/arm/mach-{bcm2708,bcm2709}/include/mach/platform.h
+ * where they carry the following notice:
+ *
+ * Copyright (C) 2010 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#define MCORE_OFFSET 0x0000 /* Fake frame buffer device
+ * (the multicore sync block) */
+#define IC0_OFFSET 0x2000
+#define ST_OFFSET 0x3000 /* System Timer */
+#define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */
+#define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */
+#define ARM_OFFSET 0xB000 /* BCM2708 ARM control block */
+#define ARMCTRL_OFFSET (ARM_OFFSET + 0x000)
+#define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */
+#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */
+#define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores
+ * Doorbells & Mailboxes */
+#define PM_OFFSET 0x100000 /* Power Management, Reset controller
+ * and Watchdog registers */
+#define PCM_CLOCK_OFFSET 0x101098
+#define RNG_OFFSET 0x104000
+#define GPIO_OFFSET 0x200000
+#define UART0_OFFSET 0x201000
+#define MMCI0_OFFSET 0x202000
+#define I2S_OFFSET 0x203000
+#define SPI0_OFFSET 0x204000
+#define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */
+#define UART1_OFFSET 0x215000
+#define EMMC_OFFSET 0x300000
+#define SMI_OFFSET 0x600000
+#define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */
+#define USB_OFFSET 0x980000 /* DTC_OTG USB controller */
+#define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */
+
+/* GPU interrupts */
+#define INTERRUPT_TIMER0 0
+#define INTERRUPT_TIMER1 1
+#define INTERRUPT_TIMER2 2
+#define INTERRUPT_TIMER3 3
+#define INTERRUPT_CODEC0 4
+#define INTERRUPT_CODEC1 5
+#define INTERRUPT_CODEC2 6
+#define INTERRUPT_JPEG 7
+#define INTERRUPT_ISP 8
+#define INTERRUPT_USB 9
+#define INTERRUPT_3D 10
+#define INTERRUPT_TRANSPOSER 11
+#define INTERRUPT_MULTICORESYNC0 12
+#define INTERRUPT_MULTICORESYNC1 13
+#define INTERRUPT_MULTICORESYNC2 14
+#define INTERRUPT_MULTICORESYNC3 15
+#define INTERRUPT_DMA0 16
+#define INTERRUPT_DMA1 17
+#define INTERRUPT_DMA2 18
+#define INTERRUPT_DMA3 19
+#define INTERRUPT_DMA4 20
+#define INTERRUPT_DMA5 21
+#define INTERRUPT_DMA6 22
+#define INTERRUPT_DMA7 23
+#define INTERRUPT_DMA8 24
+#define INTERRUPT_DMA9 25
+#define INTERRUPT_DMA10 26
+#define INTERRUPT_DMA11 27
+#define INTERRUPT_DMA12 28
+#define INTERRUPT_AUX 29
+#define INTERRUPT_ARM 30
+#define INTERRUPT_VPUDMA 31
+#define INTERRUPT_HOSTPORT 32
+#define INTERRUPT_VIDEOSCALER 33
+#define INTERRUPT_CCP2TX 34
+#define INTERRUPT_SDC 35
+#define INTERRUPT_DSI0 36
+#define INTERRUPT_AVE 37
+#define INTERRUPT_CAM0 38
+#define INTERRUPT_CAM1 39
+#define INTERRUPT_HDMI0 40
+#define INTERRUPT_HDMI1 41
+#define INTERRUPT_PIXELVALVE1 42
+#define INTERRUPT_I2CSPISLV 43
+#define INTERRUPT_DSI1 44
+#define INTERRUPT_PWA0 45
+#define INTERRUPT_PWA1 46
+#define INTERRUPT_CPR 47
+#define INTERRUPT_SMI 48
+#define INTERRUPT_GPIO0 49
+#define INTERRUPT_GPIO1 50
+#define INTERRUPT_GPIO2 51
+#define INTERRUPT_GPIO3 52
+#define INTERRUPT_I2C 53
+#define INTERRUPT_SPI 54
+#define INTERRUPT_I2SPCM 55
+#define INTERRUPT_SDIO 56
+#define INTERRUPT_UART 57
+#define INTERRUPT_SLIMBUS 58
+#define INTERRUPT_VEC 59
+#define INTERRUPT_CPG 60
+#define INTERRUPT_RNG 61
+#define INTERRUPT_ARASANSDIO 62
+#define INTERRUPT_AVSPMON 63
+
+/* ARM CPU IRQs use a private number space */
+#define INTERRUPT_ARM_TIMER 0
+#define INTERRUPT_ARM_MAILBOX 1
+#define INTERRUPT_ARM_DOORBELL_0 2
+#define INTERRUPT_ARM_DOORBELL_1 3
+#define INTERRUPT_VPU0_HALTED 4
+#define INTERRUPT_VPU1_HALTED 5
+#define INTERRUPT_ILLEGAL_TYPE0 6
+#define INTERRUPT_ILLEGAL_TYPE1 7
diff --git a/qemu/include/hw/arm/virt-acpi-build.h b/qemu/include/hw/arm/virt-acpi-build.h
index 04f174d52..7d3700ebf 100644
--- a/qemu/include/hw/arm/virt-acpi-build.h
+++ b/qemu/include/hw/arm/virt-acpi-build.h
@@ -23,7 +23,6 @@
#include "qemu-common.h"
#include "hw/arm/virt.h"
-#define VIRT_ACPI_CPU_ID_LIMIT 8
#define ACPI_GICC_ENABLED 1
typedef struct VirtGuestInfo {
@@ -31,6 +30,8 @@ typedef struct VirtGuestInfo {
FWCfgState *fw_cfg;
const MemMapEntry *memmap;
const int *irqmap;
+ bool use_highmem;
+ int gic_version;
} VirtGuestInfo;
diff --git a/qemu/include/hw/arm/virt.h b/qemu/include/hw/arm/virt.h
index d22fd8e50..ecd858960 100644
--- a/qemu/include/hw/arm/virt.h
+++ b/qemu/include/hw/arm/virt.h
@@ -46,6 +46,9 @@ enum {
VIRT_CPUPERIPHS,
VIRT_GIC_DIST,
VIRT_GIC_CPU,
+ VIRT_GIC_V2M,
+ VIRT_GIC_ITS,
+ VIRT_GIC_REDIST,
VIRT_UART,
VIRT_MMIO,
VIRT_RTC,
@@ -54,8 +57,11 @@ enum {
VIRT_PCIE_MMIO,
VIRT_PCIE_PIO,
VIRT_PCIE_ECAM,
- VIRT_GIC_V2M,
VIRT_PLATFORM_BUS,
+ VIRT_PCIE_MMIO_HIGH,
+ VIRT_GPIO,
+ VIRT_SECURE_UART,
+ VIRT_SECURE_MEM,
};
typedef struct MemMapEntry {
diff --git a/qemu/include/hw/arm/xlnx-zynqmp.h b/qemu/include/hw/arm/xlnx-zynqmp.h
index c379632f2..2332596b4 100644
--- a/qemu/include/hw/arm/xlnx-zynqmp.h
+++ b/qemu/include/hw/arm/xlnx-zynqmp.h
@@ -22,6 +22,10 @@
#include "hw/intc/arm_gic.h"
#include "hw/net/cadence_gem.h"
#include "hw/char/cadence_uart.h"
+#include "hw/ide/pci.h"
+#include "hw/ide/ahci.h"
+#include "hw/sd/sdhci.h"
+#include "hw/ssi/xilinx_spips.h"
#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
@@ -31,6 +35,12 @@
#define XLNX_ZYNQMP_NUM_RPU_CPUS 2
#define XLNX_ZYNQMP_NUM_GEMS 4
#define XLNX_ZYNQMP_NUM_UARTS 2
+#define XLNX_ZYNQMP_NUM_SDHCI 2
+#define XLNX_ZYNQMP_NUM_SPIS 2
+
+#define XLNX_ZYNQMP_NUM_OCM_BANKS 4
+#define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
+#define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000
#define XLNX_ZYNQMP_GIC_REGIONS 2
@@ -40,9 +50,17 @@
* number of memory region aliases.
*/
-#define XLNX_ZYNQMP_GIC_REGION_SIZE 0x4000
+#define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000
#define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1)
+#define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE 0x80000000ull
+
+#define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE 0x800000000ull
+#define XLNX_ZYNQMP_HIGH_RAM_START 0x800000000ull
+
+#define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
+ XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
+
typedef struct XlnxZynqMPState {
/*< private >*/
DeviceState parent_obj;
@@ -52,8 +70,17 @@ typedef struct XlnxZynqMPState {
ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS];
GICState gic;
MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
+
+ MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS];
+
+ MemoryRegion *ddr_ram;
+ MemoryRegion ddr_ram_low, ddr_ram_high;
+
CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
+ SysbusAHCIState sata;
+ SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
+ XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
char *boot_cpu;
ARMCPU *boot_cpu_ptr;
diff --git a/qemu/include/hw/block/block.h b/qemu/include/hw/block/block.h
index 8d7c4b413..984660efd 100644
--- a/qemu/include/hw/block/block.h
+++ b/qemu/include/hw/block/block.h
@@ -12,7 +12,6 @@
#define HW_BLOCK_COMMON_H
#include "qemu-common.h"
-#include "qapi/error.h"
/* Configuration */
diff --git a/qemu/include/hw/block/fdc.h b/qemu/include/hw/block/fdc.h
index d48b2f860..1749dabf2 100644
--- a/qemu/include/hw/block/fdc.h
+++ b/qemu/include/hw/block/fdc.h
@@ -6,13 +6,6 @@
/* fdc.c */
#define MAX_FD 2
-typedef enum FDriveType {
- FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */
- FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */
- FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */
- FDRIVE_DRV_NONE = 0x03, /* No drive connected */
-} FDriveType;
-
#define TYPE_ISA_FDC "isa-fdc"
ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds);
@@ -21,6 +14,8 @@ void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
DriveInfo **fds, qemu_irq *fdc_tc);
-FDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i);
+FloppyDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i);
+void isa_fdc_get_drive_max_chs(FloppyDriveType type,
+ uint8_t *maxc, uint8_t *maxh, uint8_t *maxs);
#endif
diff --git a/qemu/include/hw/boards.h b/qemu/include/hw/boards.h
index 2aec9cbb1..8d4fe56b5 100644
--- a/qemu/include/hw/boards.h
+++ b/qemu/include/hw/boards.h
@@ -3,43 +3,23 @@
#ifndef HW_BOARDS_H
#define HW_BOARDS_H
-#include "qemu/typedefs.h"
#include "sysemu/blockdev.h"
#include "sysemu/accel.h"
#include "hw/qdev.h"
#include "qom/object.h"
-
-
-typedef void QEMUMachineInitFunc(MachineState *ms);
-
-typedef void QEMUMachineResetFunc(void);
-
-typedef void QEMUMachineHotAddCPUFunc(const int64_t id, Error **errp);
-
-typedef int QEMUMachineGetKvmtypeFunc(const char *arg);
-
-struct QEMUMachine {
- const char *name;
- const char *desc;
- QEMUMachineInitFunc *init;
- QEMUMachineGetKvmtypeFunc *kvm_type;
- BlockInterfaceType block_default_type;
- int max_cpus;
- unsigned int
- no_sdcard:1,
- has_dynamic_sysbus:1;
- int is_default;
- const char *default_machine_opts;
- const char *default_boot_order;
-};
+#include "qom/cpu.h"
void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner,
const char *name,
uint64_t ram_size);
-int qemu_register_machine(QEMUMachine *m);
-
#define TYPE_MACHINE_SUFFIX "-machine"
+
+/* Machine class name that needs to be used for class-name-based machine
+ * type lookup to work.
+ */
+#define MACHINE_TYPE_NAME(machinename) (machinename TYPE_MACHINE_SUFFIX)
+
#define TYPE_MACHINE "machine"
#undef MACHINE /* BSD defines it and QEMU does not use it */
#define MACHINE(obj) \
@@ -53,17 +33,36 @@ MachineClass *find_default_machine(void);
extern MachineState *current_machine;
bool machine_usb(MachineState *machine);
-bool machine_iommu(MachineState *machine);
bool machine_kernel_irqchip_allowed(MachineState *machine);
bool machine_kernel_irqchip_required(MachineState *machine);
+bool machine_kernel_irqchip_split(MachineState *machine);
int machine_kvm_shadow_mem(MachineState *machine);
int machine_phandle_start(MachineState *machine);
bool machine_dump_guest_core(MachineState *machine);
bool machine_mem_merge(MachineState *machine);
/**
+ * CPUArchId:
+ * @arch_id - architecture-dependent CPU ID of present or possible CPU
+ * @cpu - pointer to corresponding CPU object if it's present on NULL otherwise
+ */
+typedef struct {
+ uint64_t arch_id;
+ struct CPUState *cpu;
+} CPUArchId;
+
+/**
+ * CPUArchIdList:
+ * @len - number of @CPUArchId items in @cpus array
+ * @cpus - array of present or possible CPUs for current machine configuration
+ */
+typedef struct {
+ int len;
+ CPUArchId cpus[0];
+} CPUArchIdList;
+
+/**
* MachineClass:
- * @qemu_machine: #QEMUMachine
* @get_hotplug_handler: this function is called during bus-less
* device hotplug. If defined it returns pointer to an instance
* of HotplugHandler object, which handles hotplug operation
@@ -73,6 +72,15 @@ bool machine_mem_merge(MachineState *machine);
* used to provide @cpu_index to socket number mapping, allowing
* a machine to group CPU threads belonging to the same socket/package
* Returns: socket number given cpu_index belongs to.
+ * @hw_version:
+ * Value of QEMU_VERSION when the machine was added to QEMU.
+ * Set only by old machines because they need to keep
+ * compatibility on code that exposed QEMU_VERSION to guests in
+ * the past (and now use qemu_hw_version()).
+ * @possible_cpu_arch_ids:
+ * Returns an array of @CPUArchId architecture-dependent CPU IDs
+ * which includes CPU IDs for present and possible to hotplug CPUs.
+ * Caller is responsible for freeing returned list.
*/
struct MachineClass {
/*< private >*/
@@ -100,7 +108,8 @@ struct MachineClass {
no_cdrom:1,
no_sdcard:1,
has_dynamic_sysbus:1,
- no_tco:1;
+ pci_allow_0_address:1,
+ legacy_fw_cfg_order:1;
int is_default;
const char *default_machine_opts;
const char *default_boot_order;
@@ -108,10 +117,13 @@ struct MachineClass {
GlobalProperty *compat_props;
const char *hw_version;
ram_addr_t default_ram_size;
+ bool option_rom_has_mr;
+ bool rom_file_has_mr;
HotplugHandler *(*get_hotplug_handler)(MachineState *machine,
DeviceState *dev);
unsigned (*cpu_index_to_socket_id)(unsigned cpu_index);
+ CPUArchIdList *(*possible_cpu_arch_ids)(MachineState *machine);
};
/**
@@ -127,6 +139,7 @@ struct MachineState {
char *accel;
bool kernel_irqchip_allowed;
bool kernel_irqchip_required;
+ bool kernel_irqchip_split;
int kvm_shadow_mem;
char *dtb;
char *dumpdtb;
@@ -136,9 +149,11 @@ struct MachineState {
bool mem_merge;
bool usb;
bool usb_disabled;
+ bool igd_gfx_passthru;
char *firmware;
bool iommu;
bool suppress_vmdesc;
+ bool enforce_config_section;
ram_addr_t ram_size;
ram_addr_t maxram_size;
@@ -151,4 +166,30 @@ struct MachineState {
AccelState *accelerator;
};
+#define DEFINE_MACHINE(namestr, machine_initfn) \
+ static void machine_initfn##_class_init(ObjectClass *oc, void *data) \
+ { \
+ MachineClass *mc = MACHINE_CLASS(oc); \
+ machine_initfn(mc); \
+ } \
+ static const TypeInfo machine_initfn##_typeinfo = { \
+ .name = MACHINE_TYPE_NAME(namestr), \
+ .parent = TYPE_MACHINE, \
+ .class_init = machine_initfn##_class_init, \
+ }; \
+ static void machine_initfn##_register_types(void) \
+ { \
+ type_register_static(&machine_initfn##_typeinfo); \
+ } \
+ type_init(machine_initfn##_register_types)
+
+#define SET_MACHINE_COMPAT(m, COMPAT) \
+ do { \
+ static GlobalProperty props[] = { \
+ COMPAT \
+ { /* end of list */ } \
+ }; \
+ (m)->compat_props = props; \
+ } while (0)
+
#endif
diff --git a/qemu/include/hw/bt.h b/qemu/include/hw/bt.h
index cb2a7e657..c7c7909a3 100644
--- a/qemu/include/hw/bt.h
+++ b/qemu/include/hw/bt.h
@@ -504,7 +504,6 @@ typedef struct {
#define OCF_CREATE_CONN_CANCEL 0x0008
typedef struct {
- uint8_t status;
bdaddr_t bdaddr;
} QEMU_PACKED create_conn_cancel_cp;
#define CREATE_CONN_CANCEL_CP_SIZE 6
@@ -1266,13 +1265,13 @@ typedef struct {
uint8_t status;
uint16_t handle;
} QEMU_PACKED reset_failed_contact_counter_rp;
-#define RESET_FAILED_CONTACT_COUNTER_RP_SIZE 4
+#define RESET_FAILED_CONTACT_COUNTER_RP_SIZE 3
#define OCF_READ_LINK_QUALITY 0x0003
typedef struct {
uint16_t handle;
} QEMU_PACKED read_link_quality_cp;
-#define READ_LINK_QUALITY_CP_SIZE 4
+#define READ_LINK_QUALITY_CP_SIZE 2
typedef struct {
uint8_t status;
@@ -1332,7 +1331,7 @@ typedef struct {
uint8_t dev_class[3];
uint16_t clock_offset;
} QEMU_PACKED inquiry_info;
-#define INQUIRY_INFO_SIZE 14
+#define INQUIRY_INFO_SIZE 15
#define EVT_CONN_COMPLETE 0x03
typedef struct {
@@ -1381,7 +1380,7 @@ typedef struct {
uint16_t handle;
uint8_t encrypt;
} QEMU_PACKED evt_encrypt_change;
-#define EVT_ENCRYPT_CHANGE_SIZE 5
+#define EVT_ENCRYPT_CHANGE_SIZE 4
#define EVT_CHANGE_CONN_LINK_KEY_COMPLETE 0x09
typedef struct {
@@ -1629,18 +1628,6 @@ typedef struct {
} QEMU_PACKED evt_sniff_subrate;
#define EVT_SNIFF_SUBRATE_SIZE 11
-#define EVT_EXTENDED_INQUIRY_RESULT 0x2F
-typedef struct {
- bdaddr_t bdaddr;
- uint8_t pscan_rep_mode;
- uint8_t pscan_period_mode;
- uint8_t dev_class[3];
- uint16_t clock_offset;
- int8_t rssi;
- uint8_t data[240];
-} QEMU_PACKED extended_inquiry_info;
-#define EXTENDED_INQUIRY_INFO_SIZE 254
-
#define EVT_TESTING 0xFE
#define EVT_VENDOR 0xFF
diff --git a/qemu/include/hw/char/bcm2835_aux.h b/qemu/include/hw/char/bcm2835_aux.h
new file mode 100644
index 000000000..42f0ee7a9
--- /dev/null
+++ b/qemu/include/hw/char/bcm2835_aux.h
@@ -0,0 +1,33 @@
+/*
+ * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
+ * Written by Andrew Baumann
+ *
+ * This code is licensed under the GNU GPLv2 and later.
+ */
+
+#ifndef BCM2835_AUX_H
+#define BCM2835_AUX_H
+
+#include "hw/sysbus.h"
+#include "sysemu/char.h"
+
+#define TYPE_BCM2835_AUX "bcm2835-aux"
+#define BCM2835_AUX(obj) OBJECT_CHECK(BCM2835AuxState, (obj), TYPE_BCM2835_AUX)
+
+#define BCM2835_AUX_RX_FIFO_LEN 8
+
+typedef struct {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ MemoryRegion iomem;
+ CharDriverState *chr;
+ qemu_irq irq;
+
+ uint8_t read_fifo[BCM2835_AUX_RX_FIFO_LEN];
+ uint8_t read_pos, read_count;
+ uint8_t ier, iir;
+} BCM2835AuxState;
+
+#endif
diff --git a/qemu/include/hw/char/digic-uart.h b/qemu/include/hw/char/digic-uart.h
index ef83a3059..7b3f14537 100644
--- a/qemu/include/hw/char/digic-uart.h
+++ b/qemu/include/hw/char/digic-uart.h
@@ -19,7 +19,6 @@
#define HW_CHAR_DIGIC_UART_H
#include "hw/sysbus.h"
-#include "qemu/typedefs.h"
#define TYPE_DIGIC_UART "digic-uart"
#define DIGIC_UART(obj) \
diff --git a/qemu/include/hw/char/imx_serial.h b/qemu/include/hw/char/imx_serial.h
new file mode 100644
index 000000000..6cd75c0ba
--- /dev/null
+++ b/qemu/include/hw/char/imx_serial.h
@@ -0,0 +1,102 @@
+/*
+ * Device model for i.MX UART
+ *
+ * Copyright (c) 2008 OKL
+ * Originally Written by Hans Jiang
+ * Copyright (c) 2011 NICTA Pty Ltd.
+ * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef IMX_SERIAL_H
+#define IMX_SERIAL_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_IMX_SERIAL "imx.serial"
+#define IMX_SERIAL(obj) OBJECT_CHECK(IMXSerialState, (obj), TYPE_IMX_SERIAL)
+
+#define URXD_CHARRDY (1<<15) /* character read is valid */
+#define URXD_ERR (1<<14) /* Character has error */
+#define URXD_BRK (1<<11) /* Break received */
+
+#define USR1_PARTYER (1<<15) /* Parity Error */
+#define USR1_RTSS (1<<14) /* RTS pin status */
+#define USR1_TRDY (1<<13) /* Tx ready */
+#define USR1_RTSD (1<<12) /* RTS delta: pin changed state */
+#define USR1_ESCF (1<<11) /* Escape sequence interrupt */
+#define USR1_FRAMERR (1<<10) /* Framing error */
+#define USR1_RRDY (1<<9) /* receiver ready */
+#define USR1_AGTIM (1<<8) /* Aging timer interrupt */
+#define USR1_DTRD (1<<7) /* DTR changed */
+#define USR1_RXDS (1<<6) /* Receiver is idle */
+#define USR1_AIRINT (1<<5) /* Aysnch IR interrupt */
+#define USR1_AWAKE (1<<4) /* Falling edge detected on RXd pin */
+
+#define USR2_ADET (1<<15) /* Autobaud complete */
+#define USR2_TXFE (1<<14) /* Transmit FIFO empty */
+#define USR2_DTRF (1<<13) /* DTR/DSR transition */
+#define USR2_IDLE (1<<12) /* UART has been idle for too long */
+#define USR2_ACST (1<<11) /* Autobaud counter stopped */
+#define USR2_RIDELT (1<<10) /* Ring Indicator delta */
+#define USR2_RIIN (1<<9) /* Ring Indicator Input */
+#define USR2_IRINT (1<<8) /* Serial Infrared Interrupt */
+#define USR2_WAKE (1<<7) /* Start bit detected */
+#define USR2_DCDDELT (1<<6) /* Data Carrier Detect delta */
+#define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
+#define USR2_RTSF (1<<4) /* RTS transition */
+#define USR2_TXDC (1<<3) /* Transmission complete */
+#define USR2_BRCD (1<<2) /* Break condition detected */
+#define USR2_ORE (1<<1) /* Overrun error */
+#define USR2_RDR (1<<0) /* Receive data ready */
+
+#define UCR1_TRDYEN (1<<13) /* Tx Ready Interrupt Enable */
+#define UCR1_RRDYEN (1<<9) /* Rx Ready Interrupt Enable */
+#define UCR1_TXMPTYEN (1<<6) /* Tx Empty Interrupt Enable */
+#define UCR1_UARTEN (1<<0) /* UART Enable */
+
+#define UCR2_TXEN (1<<2) /* Transmitter enable */
+#define UCR2_RXEN (1<<1) /* Receiver enable */
+#define UCR2_SRST (1<<0) /* Reset complete */
+
+#define UTS1_TXEMPTY (1<<6)
+#define UTS1_RXEMPTY (1<<5)
+#define UTS1_TXFULL (1<<4)
+#define UTS1_RXFULL (1<<3)
+
+typedef struct IMXSerialState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion iomem;
+ int32_t readbuff;
+
+ uint32_t usr1;
+ uint32_t usr2;
+ uint32_t ucr1;
+ uint32_t ucr2;
+ uint32_t uts1;
+
+ /*
+ * The registers below are implemented just so that the
+ * guest OS sees what it has written
+ */
+ uint32_t onems;
+ uint32_t ufcr;
+ uint32_t ubmr;
+ uint32_t ubrc;
+ uint32_t ucr3;
+
+ qemu_irq irq;
+ CharDriverState *chr;
+} IMXSerialState;
+
+#endif
diff --git a/qemu/include/hw/compat.h b/qemu/include/hw/compat.h
index 94c8097d0..a5dbbf898 100644
--- a/qemu/include/hw/compat.h
+++ b/qemu/include/hw/compat.h
@@ -1,61 +1,112 @@
#ifndef HW_COMPAT_H
#define HW_COMPAT_H
+#define HW_COMPAT_2_5 \
+ {\
+ .driver = "isa-fdc",\
+ .property = "fallback",\
+ .value = "144",\
+ },{\
+ .driver = "pvscsi",\
+ .property = "x-old-pci-configuration",\
+ .value = "on",\
+ },{\
+ .driver = "pvscsi",\
+ .property = "x-disable-pcie",\
+ .value = "on",\
+ },\
+ {\
+ .driver = "vmxnet3",\
+ .property = "x-old-msi-offsets",\
+ .value = "on",\
+ },{\
+ .driver = "vmxnet3",\
+ .property = "x-disable-pcie",\
+ .value = "on",\
+ },
+
+#define HW_COMPAT_2_4 \
+ {\
+ .driver = "virtio-blk-device",\
+ .property = "scsi",\
+ .value = "true",\
+ },{\
+ .driver = "e1000",\
+ .property = "extra_mac_registers",\
+ .value = "off",\
+ },{\
+ .driver = "virtio-pci",\
+ .property = "x-disable-pcie",\
+ .value = "on",\
+ },{\
+ .driver = "virtio-pci",\
+ .property = "migrate-extra",\
+ .value = "off",\
+ },{\
+ .driver = "fw_cfg_mem",\
+ .property = "dma_enabled",\
+ .value = "off",\
+ },{\
+ .driver = "fw_cfg_io",\
+ .property = "dma_enabled",\
+ .value = "off",\
+ },
+
#define HW_COMPAT_2_3 \
- {\
- .driver = "virtio-blk-pci",\
- .property = "any_layout",\
- .value = "off",\
- },{\
- .driver = "virtio-balloon-pci",\
- .property = "any_layout",\
- .value = "off",\
- },{\
- .driver = "virtio-serial-pci",\
- .property = "any_layout",\
- .value = "off",\
- },{\
- .driver = "virtio-9p-pci",\
- .property = "any_layout",\
- .value = "off",\
- },{\
- .driver = "virtio-rng-pci",\
- .property = "any_layout",\
- .value = "off",\
- },
+ {\
+ .driver = "virtio-blk-pci",\
+ .property = "any_layout",\
+ .value = "off",\
+ },{\
+ .driver = "virtio-balloon-pci",\
+ .property = "any_layout",\
+ .value = "off",\
+ },{\
+ .driver = "virtio-serial-pci",\
+ .property = "any_layout",\
+ .value = "off",\
+ },{\
+ .driver = "virtio-9p-pci",\
+ .property = "any_layout",\
+ .value = "off",\
+ },{\
+ .driver = "virtio-rng-pci",\
+ .property = "any_layout",\
+ .value = "off",\
+ },
#define HW_COMPAT_2_2 \
- /* empty */
+ /* empty */
#define HW_COMPAT_2_1 \
- {\
- .driver = "intel-hda",\
- .property = "old_msi_addr",\
- .value = "on",\
- },{\
- .driver = "VGA",\
- .property = "qemu-extended-regs",\
- .value = "off",\
- },{\
- .driver = "secondary-vga",\
- .property = "qemu-extended-regs",\
- .value = "off",\
- },{\
- .driver = "virtio-scsi-pci",\
- .property = "any_layout",\
- .value = "off",\
- },{\
- .driver = "usb-mouse",\
- .property = "usb_version",\
- .value = stringify(1),\
- },{\
- .driver = "usb-kbd",\
- .property = "usb_version",\
- .value = stringify(1),\
- },{\
- .driver = "virtio-pci",\
- .property = "virtio-pci-bus-master-bug-migration",\
- .value = "on",\
- },
+ {\
+ .driver = "intel-hda",\
+ .property = "old_msi_addr",\
+ .value = "on",\
+ },{\
+ .driver = "VGA",\
+ .property = "qemu-extended-regs",\
+ .value = "off",\
+ },{\
+ .driver = "secondary-vga",\
+ .property = "qemu-extended-regs",\
+ .value = "off",\
+ },{\
+ .driver = "virtio-scsi-pci",\
+ .property = "any_layout",\
+ .value = "off",\
+ },{\
+ .driver = "usb-mouse",\
+ .property = "usb_version",\
+ .value = stringify(1),\
+ },{\
+ .driver = "usb-kbd",\
+ .property = "usb_version",\
+ .value = stringify(1),\
+ },{\
+ .driver = "virtio-pci",\
+ .property = "virtio-pci-bus-master-bug-migration",\
+ .value = "on",\
+ },
#endif /* HW_COMPAT_H */
diff --git a/qemu/include/hw/cpu/icc_bus.h b/qemu/include/hw/cpu/icc_bus.h
deleted file mode 100644
index 98a979fa1..000000000
--- a/qemu/include/hw/cpu/icc_bus.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* icc_bus.h
- * emulate x86 ICC (Interrupt Controller Communications) bus
- *
- * Copyright (c) 2013 Red Hat, Inc
- *
- * Authors:
- * Igor Mammedov <imammedo@redhat.com>
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>
- */
-#ifndef ICC_BUS_H
-#define ICC_BUS_H
-
-#include "exec/memory.h"
-#include "hw/qdev-core.h"
-
-#define TYPE_ICC_BUS "icc-bus"
-
-#ifndef CONFIG_USER_ONLY
-
-/**
- * ICCBus:
- *
- * ICC bus
- */
-typedef struct ICCBus {
- /*< private >*/
- BusState parent_obj;
- /*< public >*/
-
- MemoryRegion *apic_address_space;
-} ICCBus;
-
-#define ICC_BUS(obj) OBJECT_CHECK(ICCBus, (obj), TYPE_ICC_BUS)
-
-/**
- * ICCDevice:
- *
- * ICC device
- */
-typedef struct ICCDevice {
- /*< private >*/
- DeviceState qdev;
- /*< public >*/
-} ICCDevice;
-
-/**
- * ICCDeviceClass:
- * @init: Initialization callback for derived classes.
- *
- * ICC device class
- */
-typedef struct ICCDeviceClass {
- /*< private >*/
- DeviceClass parent_class;
- /*< public >*/
-
- DeviceRealize realize;
-} ICCDeviceClass;
-
-#define TYPE_ICC_DEVICE "icc-device"
-#define ICC_DEVICE(obj) OBJECT_CHECK(ICCDevice, (obj), TYPE_ICC_DEVICE)
-#define ICC_DEVICE_CLASS(klass) \
- OBJECT_CLASS_CHECK(ICCDeviceClass, (klass), TYPE_ICC_DEVICE)
-#define ICC_DEVICE_GET_CLASS(obj) \
- OBJECT_GET_CLASS(ICCDeviceClass, (obj), TYPE_ICC_DEVICE)
-
-#define TYPE_ICC_BRIDGE "icc-bridge"
-
-#endif /* CONFIG_USER_ONLY */
-#endif
diff --git a/qemu/include/hw/display/bcm2835_fb.h b/qemu/include/hw/display/bcm2835_fb.h
new file mode 100644
index 000000000..9a12d7afa
--- /dev/null
+++ b/qemu/include/hw/display/bcm2835_fb.h
@@ -0,0 +1,47 @@
+/*
+ * Raspberry Pi emulation (c) 2012 Gregory Estrade
+ * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
+ *
+ * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
+ * Written by Andrew Baumann
+ *
+ * This code is licensed under the GNU GPLv2 and later.
+ */
+
+#ifndef BCM2835_FB_H
+#define BCM2835_FB_H
+
+#include "hw/sysbus.h"
+#include "exec/address-spaces.h"
+#include "ui/console.h"
+
+#define TYPE_BCM2835_FB "bcm2835-fb"
+#define BCM2835_FB(obj) OBJECT_CHECK(BCM2835FBState, (obj), TYPE_BCM2835_FB)
+
+typedef struct {
+ /*< private >*/
+ SysBusDevice busdev;
+ /*< public >*/
+
+ uint32_t vcram_base, vcram_size;
+ MemoryRegion *dma_mr;
+ AddressSpace dma_as;
+ MemoryRegion iomem;
+ MemoryRegionSection fbsection;
+ QemuConsole *con;
+ qemu_irq mbox_irq;
+
+ bool lock, invalidate, pending;
+ uint32_t xres, yres;
+ uint32_t xres_virtual, yres_virtual;
+ uint32_t xoffset, yoffset;
+ uint32_t bpp;
+ uint32_t base, pitch, size;
+ uint32_t pixo, alpha;
+} BCM2835FBState;
+
+void bcm2835_fb_reconfigure(BCM2835FBState *s, uint32_t *xres, uint32_t *yres,
+ uint32_t *xoffset, uint32_t *yoffset, uint32_t *bpp,
+ uint32_t *pixo, uint32_t *alpha);
+
+#endif
diff --git a/qemu/include/hw/dma/bcm2835_dma.h b/qemu/include/hw/dma/bcm2835_dma.h
new file mode 100644
index 000000000..75312e2e1
--- /dev/null
+++ b/qemu/include/hw/dma/bcm2835_dma.h
@@ -0,0 +1,47 @@
+/*
+ * Raspberry Pi emulation (c) 2012 Gregory Estrade
+ * This code is licensed under the GNU GPLv2 and later.
+ */
+
+#ifndef BCM2835_DMA_H
+#define BCM2835_DMA_H
+
+#include "qemu-common.h"
+#include "exec/address-spaces.h"
+#include "hw/sysbus.h"
+
+typedef struct {
+ uint32_t cs;
+ uint32_t conblk_ad;
+ uint32_t ti;
+ uint32_t source_ad;
+ uint32_t dest_ad;
+ uint32_t txfr_len;
+ uint32_t stride;
+ uint32_t nextconbk;
+ uint32_t debug;
+
+ qemu_irq irq;
+} BCM2835DMAChan;
+
+#define TYPE_BCM2835_DMA "bcm2835-dma"
+#define BCM2835_DMA(obj) \
+ OBJECT_CHECK(BCM2835DMAState, (obj), TYPE_BCM2835_DMA)
+
+#define BCM2835_DMA_NCHANS 16
+
+typedef struct {
+ /*< private >*/
+ SysBusDevice busdev;
+ /*< public >*/
+
+ MemoryRegion iomem0, iomem15;
+ MemoryRegion *dma_mr;
+ AddressSpace dma_as;
+
+ BCM2835DMAChan chan[BCM2835_DMA_NCHANS];
+ uint32_t int_status;
+ uint32_t enable;
+} BCM2835DMAState;
+
+#endif
diff --git a/qemu/include/hw/elf_ops.h b/qemu/include/hw/elf_ops.h
index bd7196814..f510e7ec2 100644
--- a/qemu/include/hw/elf_ops.h
+++ b/qemu/include/hw/elf_ops.h
@@ -263,7 +263,7 @@ static int glue(load_elf, SZ)(const char *name, int fd,
void *translate_opaque,
int must_swab, uint64_t *pentry,
uint64_t *lowaddr, uint64_t *highaddr,
- int elf_machine, int clear_lsb)
+ int elf_machine, int clear_lsb, int data_swab)
{
struct elfhdr ehdr;
struct elf_phdr *phdr = NULL, *ph;
@@ -282,25 +282,36 @@ static int glue(load_elf, SZ)(const char *name, int fd,
switch (elf_machine) {
case EM_PPC64:
- if (EM_PPC64 != ehdr.e_machine)
- if (EM_PPC != ehdr.e_machine) {
+ if (ehdr.e_machine != EM_PPC64) {
+ if (ehdr.e_machine != EM_PPC) {
ret = ELF_LOAD_WRONG_ARCH;
goto fail;
}
+ }
break;
case EM_X86_64:
- if (EM_X86_64 != ehdr.e_machine)
- if (EM_386 != ehdr.e_machine) {
+ if (ehdr.e_machine != EM_X86_64) {
+ if (ehdr.e_machine != EM_386) {
ret = ELF_LOAD_WRONG_ARCH;
goto fail;
}
+ }
break;
case EM_MICROBLAZE:
- if (EM_MICROBLAZE != ehdr.e_machine)
- if (EM_MICROBLAZE_OLD != ehdr.e_machine) {
+ if (ehdr.e_machine != EM_MICROBLAZE) {
+ if (ehdr.e_machine != EM_MICROBLAZE_OLD) {
ret = ELF_LOAD_WRONG_ARCH;
goto fail;
}
+ }
+ break;
+ case EM_MOXIE:
+ if (ehdr.e_machine != EM_MOXIE) {
+ if (ehdr.e_machine != EM_MOXIE_OLD) {
+ ret = ELF_LOAD_WRONG_ARCH;
+ goto fail;
+ }
+ }
break;
default:
if (elf_machine != ehdr.e_machine) {
@@ -355,6 +366,26 @@ static int glue(load_elf, SZ)(const char *name, int fd,
addr = ph->p_paddr;
}
+ if (data_swab) {
+ int j;
+ for (j = 0; j < file_size; j += (1 << data_swab)) {
+ uint8_t *dp = data + j;
+ switch (data_swab) {
+ case (1):
+ *(uint16_t *)dp = bswap16(*(uint16_t *)dp);
+ break;
+ case (2):
+ *(uint32_t *)dp = bswap32(*(uint32_t *)dp);
+ break;
+ case (3):
+ *(uint64_t *)dp = bswap64(*(uint64_t *)dp);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
+ }
+
/* the entry pointer in the ELF header is a virtual
* address, if the text segments paddr and vaddr differ
* we need to adjust the entry */
diff --git a/qemu/include/hw/gpio/imx_gpio.h b/qemu/include/hw/gpio/imx_gpio.h
new file mode 100644
index 000000000..b15a09fbc
--- /dev/null
+++ b/qemu/include/hw/gpio/imx_gpio.h
@@ -0,0 +1,63 @@
+/*
+ * i.MX processors GPIO registers definition.
+ *
+ * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __IMX_GPIO_H_
+#define __IMX_GPIO_H_
+
+#include <hw/sysbus.h>
+
+#define TYPE_IMX_GPIO "imx.gpio"
+#define IMX_GPIO(obj) OBJECT_CHECK(IMXGPIOState, (obj), TYPE_IMX_GPIO)
+
+#define IMX_GPIO_MEM_SIZE 0x20
+
+/* i.MX GPIO memory map */
+#define DR_ADDR 0x00 /* DATA REGISTER */
+#define GDIR_ADDR 0x04 /* DIRECTION REGISTER */
+#define PSR_ADDR 0x08 /* PAD STATUS REGISTER */
+#define ICR1_ADDR 0x0c /* INTERRUPT CONFIGURATION REGISTER 1 */
+#define ICR2_ADDR 0x10 /* INTERRUPT CONFIGURATION REGISTER 2 */
+#define IMR_ADDR 0x14 /* INTERRUPT MASK REGISTER */
+#define ISR_ADDR 0x18 /* INTERRUPT STATUS REGISTER */
+#define EDGE_SEL_ADDR 0x1c /* EDGE SEL REGISTER */
+
+#define IMX_GPIO_PIN_COUNT 32
+
+typedef struct IMXGPIOState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion iomem;
+
+ uint32_t dr;
+ uint32_t gdir;
+ uint32_t psr;
+ uint64_t icr;
+ uint32_t imr;
+ uint32_t isr;
+ bool has_edge_sel;
+ uint32_t edge_sel;
+ bool has_upper_pin_irq;
+
+ qemu_irq irq[2];
+ qemu_irq output[IMX_GPIO_PIN_COUNT];
+} IMXGPIOState;
+
+#endif /* __IMX_GPIO_H_ */
diff --git a/qemu/include/hw/hotplug.h b/qemu/include/hw/hotplug.h
index 2db025d0b..da1d0e4ab 100644
--- a/qemu/include/hw/hotplug.h
+++ b/qemu/include/hw/hotplug.h
@@ -13,7 +13,6 @@
#define HOTPLUG_H
#include "qom/object.h"
-#include "qemu/typedefs.h"
#define TYPE_HOTPLUG_HANDLER "hotplug-handler"
diff --git a/qemu/include/hw/hw.h b/qemu/include/hw/hw.h
index c78adae06..2cb69d5f5 100644
--- a/qemu/include/hw/hw.h
+++ b/qemu/include/hw/hw.h
@@ -2,7 +2,6 @@
#ifndef QEMU_HW_H
#define QEMU_HW_H
-#include "qemu-common.h"
#if !defined(CONFIG_USER_ONLY) && !defined(NEED_CPU_H)
#include "exec/cpu-common.h"
@@ -13,6 +12,7 @@
#include "block/aio.h"
#include "migration/vmstate.h"
#include "qemu/log.h"
+#include "qemu/module.h"
#ifdef NEED_CPU_H
#if TARGET_LONG_BITS == 64
@@ -41,6 +41,8 @@ typedef void QEMUResetHandler(void *opaque);
void qemu_register_reset(QEMUResetHandler *func, void *opaque);
void qemu_unregister_reset(QEMUResetHandler *func, void *opaque);
+void QEMU_NORETURN hw_error(const char *fmt, ...) GCC_FMT_ATTR(1, 2);
+
#ifdef NEED_CPU_H
#if TARGET_LONG_BITS == 64
#define VMSTATE_UINTTL_V(_f, _s, _v) \
@@ -49,6 +51,7 @@ void qemu_unregister_reset(QEMUResetHandler *func, void *opaque);
VMSTATE_UINT64_EQUAL_V(_f, _s, _v)
#define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \
VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v)
+#define vmstate_info_uinttl vmstate_info_uint64
#else
#define VMSTATE_UINTTL_V(_f, _s, _v) \
VMSTATE_UINT32_V(_f, _s, _v)
@@ -56,6 +59,7 @@ void qemu_unregister_reset(QEMUResetHandler *func, void *opaque);
VMSTATE_UINT32_EQUAL_V(_f, _s, _v)
#define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \
VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v)
+#define vmstate_info_uinttl vmstate_info_uint32
#endif
#define VMSTATE_UINTTL(_f, _s) \
VMSTATE_UINTTL_V(_f, _s, 0)
diff --git a/qemu/include/hw/i2c/imx_i2c.h b/qemu/include/hw/i2c/imx_i2c.h
new file mode 100644
index 000000000..e2ee8eaee
--- /dev/null
+++ b/qemu/include/hw/i2c/imx_i2c.h
@@ -0,0 +1,87 @@
+/*
+ * i.MX I2C Bus Serial Interface registers definition
+ *
+ * Copyright (C) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef __IMX_I2C_H_
+#define __IMX_I2C_H_
+
+#include <hw/sysbus.h>
+
+#define TYPE_IMX_I2C "imx.i2c"
+#define IMX_I2C(obj) OBJECT_CHECK(IMXI2CState, (obj), TYPE_IMX_I2C)
+
+#define IMX_I2C_MEM_SIZE 0x14
+
+/* i.MX I2C memory map */
+#define IADR_ADDR 0x00 /* address register */
+#define IFDR_ADDR 0x04 /* frequency divider register */
+#define I2CR_ADDR 0x08 /* control register */
+#define I2SR_ADDR 0x0c /* status register */
+#define I2DR_ADDR 0x10 /* data register */
+
+#define IADR_MASK 0xFE
+#define IADR_RESET 0
+
+#define IFDR_MASK 0x3F
+#define IFDR_RESET 0
+
+#define I2CR_IEN (1 << 7)
+#define I2CR_IIEN (1 << 6)
+#define I2CR_MSTA (1 << 5)
+#define I2CR_MTX (1 << 4)
+#define I2CR_TXAK (1 << 3)
+#define I2CR_RSTA (1 << 2)
+#define I2CR_MASK 0xFC
+#define I2CR_RESET 0
+
+#define I2SR_ICF (1 << 7)
+#define I2SR_IAAF (1 << 6)
+#define I2SR_IBB (1 << 5)
+#define I2SR_IAL (1 << 4)
+#define I2SR_SRW (1 << 2)
+#define I2SR_IIF (1 << 1)
+#define I2SR_RXAK (1 << 0)
+#define I2SR_MASK 0xE9
+#define I2SR_RESET 0x81
+
+#define I2DR_MASK 0xFF
+#define I2DR_RESET 0
+
+#define ADDR_RESET 0xFF00
+
+typedef struct IMXI2CState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion iomem;
+ I2CBus *bus;
+ qemu_irq irq;
+
+ uint16_t address;
+
+ uint16_t iadr;
+ uint16_t ifdr;
+ uint16_t i2cr;
+ uint16_t i2sr;
+ uint16_t i2dr_read;
+ uint16_t i2dr_write;
+} IMXI2CState;
+
+#endif /* __IMX_I2C_H_ */
diff --git a/qemu/include/hw/i386/apic_internal.h b/qemu/include/hw/i386/apic_internal.h
index dc7a89d98..74fe935e8 100644
--- a/qemu/include/hw/i386/apic_internal.h
+++ b/qemu/include/hw/i386/apic_internal.h
@@ -20,8 +20,8 @@
#ifndef QEMU_APIC_INTERNAL_H
#define QEMU_APIC_INTERNAL_H
+#include "cpu.h"
#include "exec/memory.h"
-#include "hw/cpu/icc_bus.h"
#include "qemu/timer.h"
/* APIC Local Vector Table */
@@ -49,17 +49,73 @@
#define APIC_TRIGGER_EDGE 0
#define APIC_TRIGGER_LEVEL 1
-#define APIC_LVT_TIMER_PERIODIC (1<<17)
-#define APIC_LVT_MASKED (1<<16)
-#define APIC_LVT_LEVEL_TRIGGER (1<<15)
-#define APIC_LVT_REMOTE_IRR (1<<14)
-#define APIC_INPUT_POLARITY (1<<13)
-#define APIC_SEND_PENDING (1<<12)
-
-#define ESR_ILLEGAL_ADDRESS (1 << 7)
-
-#define APIC_SV_DIRECTED_IO (1<<12)
-#define APIC_SV_ENABLE (1<<8)
+#define APIC_VECTOR_MASK 0xff
+#define APIC_DCR_MASK 0xf
+
+#define APIC_LVT_TIMER_SHIFT 17
+#define APIC_LVT_MASKED_SHIFT 16
+#define APIC_LVT_LEVEL_TRIGGER_SHIFT 15
+#define APIC_LVT_REMOTE_IRR_SHIFT 14
+#define APIC_LVT_INT_POLARITY_SHIFT 13
+#define APIC_LVT_DELIV_STS_SHIFT 12
+#define APIC_LVT_DELIV_MOD_SHIFT 8
+
+#define APIC_LVT_TIMER_TSCDEADLINE (2 << APIC_LVT_TIMER_SHIFT)
+#define APIC_LVT_TIMER_PERIODIC (1 << APIC_LVT_TIMER_SHIFT)
+#define APIC_LVT_MASKED (1 << APIC_LVT_MASKED_SHIFT)
+#define APIC_LVT_LEVEL_TRIGGER (1 << APIC_LVT_LEVEL_TRIGGER_SHIFT)
+#define APIC_LVT_REMOTE_IRR (1 << APIC_LVT_REMOTE_IRR_SHIFT)
+#define APIC_LVT_INT_POLARITY (1 << APIC_LVT_INT_POLARITY_SHIFT)
+#define APIC_LVT_DELIV_STS (1 << APIC_LVT_DELIV_STS_SHIFT)
+#define APIC_LVT_DELIV_MOD (7 << APIC_LVT_DELIV_MOD_SHIFT)
+
+#define APIC_ESR_ILL_ADDRESS_SHIFT 7
+#define APIC_ESR_RECV_ILL_VECT_SHIFT 6
+#define APIC_ESR_SEND_ILL_VECT_SHIFT 5
+#define APIC_ESR_RECV_ACCEPT_SHIFT 3
+#define APIC_ESR_SEND_ACCEPT_SHIFT 2
+#define APIC_ESR_RECV_CHECK_SUM_SHIFT 1
+
+#define APIC_ESR_ILLEGAL_ADDRESS (1 << APIC_ESR_ILL_ADDRESS_SHIFT)
+#define APIC_ESR_RECV_ILLEGAL_VECT (1 << APIC_ESR_RECV_ILL_VECT_SHIFT)
+#define APIC_ESR_SEND_ILLEGAL_VECT (1 << APIC_ESR_SEND_ILL_VECT_SHIFT)
+#define APIC_ESR_RECV_ACCEPT (1 << APIC_ESR_RECV_ACCEPT_SHIFT)
+#define APIC_ESR_SEND_ACCEPT (1 << APIC_ESR_SEND_ACCEPT_SHIFT)
+#define APIC_ESR_RECV_CHECK_SUM (1 << APIC_ESR_RECV_CHECK_SUM_SHIFT)
+#define APIC_ESR_SEND_CHECK_SUM 1
+
+#define APIC_ICR_DEST_SHIFT 24
+#define APIC_ICR_DEST_SHORT_SHIFT 18
+#define APIC_ICR_TRIGGER_MOD_SHIFT 15
+#define APIC_ICR_LEVEL_SHIFT 14
+#define APIC_ICR_DELIV_STS_SHIFT 12
+#define APIC_ICR_DEST_MOD_SHIFT 11
+#define APIC_ICR_DELIV_MOD_SHIFT 8
+
+#define APIC_ICR_DEST_SHORT (3 << APIC_ICR_DEST_SHORT_SHIFT)
+#define APIC_ICR_TRIGGER_MOD (1 << APIC_ICR_TRIGGER_MOD_SHIFT)
+#define APIC_ICR_LEVEL (1 << APIC_ICR_LEVEL_SHIFT)
+#define APIC_ICR_DELIV_STS (1 << APIC_ICR_DELIV_STS_SHIFT)
+#define APIC_ICR_DEST_MOD (1 << APIC_ICR_DEST_MOD_SHIFT)
+#define APIC_ICR_DELIV_MOD (7 << APIC_ICR_DELIV_MOD_SHIFT)
+
+#define APIC_PR_CLASS_SHIFT 4
+#define APIC_PR_SUB_CLASS 0xf
+
+#define APIC_LOGDEST_XAPIC_SHIFT 4
+#define APIC_LOGDEST_XAPIC_ID 0xf
+
+#define APIC_LOGDEST_X2APIC_SHIFT 16
+#define APIC_LOGDEST_X2APIC_ID 0xffff
+
+#define APIC_SPURIO_FOCUS_SHIFT 9
+#define APIC_SPURIO_ENABLED_SHIFT 8
+
+#define APIC_SPURIO_FOCUS (1 << APIC_SPURIO_FOCUS_SHIFT)
+#define APIC_SPURIO_ENABLED (1 << APIC_SPURIO_ENABLED_SHIFT)
+
+#define APIC_SV_DIRECTED_IO (1 << 12)
+#define APIC_SV_ENABLE (1 << 8)
#define VAPIC_ENABLE_BIT 0
#define VAPIC_ENABLE_MASK (1 << VAPIC_ENABLE_BIT)
@@ -78,7 +134,7 @@ typedef struct APICCommonState APICCommonState;
typedef struct APICCommonClass
{
- ICCDeviceClass parent_class;
+ DeviceClass parent_class;
DeviceRealize realize;
void (*set_base)(APICCommonState *s, uint64_t val);
@@ -93,7 +149,9 @@ typedef struct APICCommonClass
} APICCommonClass;
struct APICCommonState {
- ICCDevice busdev;
+ /*< private >*/
+ DeviceState parent_obj;
+ /*< public >*/
MemoryRegion io_memory;
X86CPU *cpu;
@@ -146,4 +204,22 @@ void apic_enable_vapic(DeviceState *d, hwaddr paddr);
void vapic_report_tpr_access(DeviceState *dev, CPUState *cpu, target_ulong ip,
TPRAccess access);
+int apic_get_ppr(APICCommonState *s);
+
+static inline void apic_set_bit(uint32_t *tab, int index)
+{
+ int i, mask;
+ i = index >> 5;
+ mask = 1 << (index & 0x1f);
+ tab[i] |= mask;
+}
+
+static inline int apic_get_bit(uint32_t *tab, int index)
+{
+ int i, mask;
+ i = index >> 5;
+ mask = 1 << (index & 0x1f);
+ return !!(tab[i] & mask);
+}
+
#endif /* !QEMU_APIC_INTERNAL_H */
diff --git a/qemu/include/hw/i386/ich9.h b/qemu/include/hw/i386/ich9.h
index b9d2b04b6..d04dcdcfb 100644
--- a/qemu/include/hw/i386/ich9.h
+++ b/qemu/include/hw/i386/ich9.h
@@ -17,13 +17,13 @@
void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
-void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled, bool enable_tco);
+void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled);
I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
void ich9_generate_smi(void);
void ich9_generate_nmi(void);
-#define ICH9_CC_SIZE (16 * 1024) /* 16KB */
+#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */
#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
#define ICH9_LPC_DEVICE(obj) \
@@ -65,7 +65,7 @@ typedef struct ICH9LPCState {
/* isa bus */
ISABus *isa_bus;
- MemoryRegion rbca_mem;
+ MemoryRegion rcrb_mem; /* root complex register block */
Notifier machine_ready;
qemu_irq *pic;
diff --git a/qemu/include/hw/i386/intel_iommu.h b/qemu/include/hw/i386/intel_iommu.h
index e321ee4fb..b024ffa72 100644
--- a/qemu/include/hw/i386/intel_iommu.h
+++ b/qemu/include/hw/i386/intel_iommu.h
@@ -49,6 +49,7 @@ typedef struct VTDContextCacheEntry VTDContextCacheEntry;
typedef struct IntelIOMMUState IntelIOMMUState;
typedef struct VTDAddressSpace VTDAddressSpace;
typedef struct VTDIOTLBEntry VTDIOTLBEntry;
+typedef struct VTDBus VTDBus;
/* Context-Entry */
struct VTDContextEntry {
@@ -65,7 +66,7 @@ struct VTDContextCacheEntry {
};
struct VTDAddressSpace {
- uint8_t bus_num;
+ PCIBus *bus;
uint8_t devfn;
AddressSpace as;
MemoryRegion iommu;
@@ -73,10 +74,16 @@ struct VTDAddressSpace {
VTDContextCacheEntry context_cache_entry;
};
+struct VTDBus {
+ PCIBus* bus; /* A reference to the bus to provide translation for */
+ VTDAddressSpace *dev_as[0]; /* A table of VTDAddressSpace objects indexed by devfn */
+};
+
struct VTDIOTLBEntry {
uint64_t gfn;
uint16_t domain_id;
uint64_t slpte;
+ uint64_t mask;
bool read_flags;
bool write_flags;
};
@@ -114,7 +121,13 @@ struct IntelIOMMUState {
GHashTable *iotlb; /* IOTLB */
MemoryRegionIOMMUOps iommu_ops;
- VTDAddressSpace **address_spaces[VTD_PCI_BUS_MAX];
+ GHashTable *vtd_as_by_busptr; /* VTDBus objects indexed by PCIBus* reference */
+ VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */
};
+/* Find the VTD Address space associated with the given bus pointer,
+ * create a new one if none exists
+ */
+VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn);
+
#endif
diff --git a/qemu/include/hw/i386/ioapic_internal.h b/qemu/include/hw/i386/ioapic_internal.h
index 3be335218..797ed4730 100644
--- a/qemu/include/hw/i386/ioapic_internal.h
+++ b/qemu/include/hw/i386/ioapic_internal.h
@@ -40,7 +40,12 @@
#define IOAPIC_LVT_DELIV_MODE_SHIFT 8
#define IOAPIC_LVT_MASKED (1 << IOAPIC_LVT_MASKED_SHIFT)
+#define IOAPIC_LVT_TRIGGER_MODE (1 << IOAPIC_LVT_TRIGGER_MODE_SHIFT)
#define IOAPIC_LVT_REMOTE_IRR (1 << IOAPIC_LVT_REMOTE_IRR_SHIFT)
+#define IOAPIC_LVT_POLARITY (1 << IOAPIC_LVT_POLARITY_SHIFT)
+#define IOAPIC_LVT_DELIV_STATUS (1 << IOAPIC_LVT_DELIV_STATUS_SHIFT)
+#define IOAPIC_LVT_DEST_MODE (1 << IOAPIC_LVT_DEST_MODE_SHIFT)
+#define IOAPIC_LVT_DELIV_MODE (7 << IOAPIC_LVT_DELIV_MODE_SHIFT)
#define IOAPIC_TRIGGER_EDGE 0
#define IOAPIC_TRIGGER_LEVEL 1
@@ -100,4 +105,6 @@ struct IOAPICCommonState {
void ioapic_reset_common(DeviceState *dev);
+void ioapic_print_redtbl(Monitor *mon, IOAPICCommonState *s);
+
#endif /* !QEMU_IOAPIC_INTERNAL_H */
diff --git a/qemu/include/hw/i386/pc.h b/qemu/include/hw/i386/pc.h
index 954203d22..96f0b66c7 100644
--- a/qemu/include/hw/i386/pc.h
+++ b/qemu/include/hw/i386/pc.h
@@ -16,29 +16,62 @@
#include "hw/boards.h"
#include "hw/compat.h"
#include "hw/mem/pc-dimm.h"
+#include "hw/mem/nvdimm.h"
#define HPET_INTCAP "hpet-intcap"
+#ifdef CONFIG_KVM
+#define kvm_pit_in_kernel() \
+ (kvm_irqchip_in_kernel() && !kvm_irqchip_is_split())
+#define kvm_pic_in_kernel() \
+ (kvm_irqchip_in_kernel() && !kvm_irqchip_is_split())
+#define kvm_ioapic_in_kernel() \
+ (kvm_irqchip_in_kernel() && !kvm_irqchip_is_split())
+#else
+#define kvm_pit_in_kernel() 0
+#define kvm_pic_in_kernel() 0
+#define kvm_ioapic_in_kernel() 0
+#endif
+
/**
* PCMachineState:
* @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
- * @enforce_aligned_dimm: check that DIMM's address/size is aligned by
- * backend's alignment value if provided
*/
struct PCMachineState {
/*< private >*/
MachineState parent_obj;
/* <public> */
+
+ /* State for other subsystems/APIs: */
MemoryHotplugState hotplug_memory;
+ Notifier machine_done;
+ /* Pointers to devices and objects: */
HotplugHandler *acpi_dev;
ISADevice *rtc;
+ PCIBus *bus;
+ FWCfgState *fw_cfg;
+ /* Configuration options: */
uint64_t max_ram_below_4g;
OnOffAuto vmport;
OnOffAuto smm;
- bool enforce_aligned_dimm;
+
+ AcpiNVDIMMState acpi_nvdimm_state;
+
+ /* RAM information (sizes, addresses, configuration): */
+ ram_addr_t below_4g_mem_size, above_4g_mem_size;
+
+ /* CPU and apic information: */
+ bool apic_xrupt_override;
+ unsigned apic_id_limit;
+ CPUArchIdList *possible_cpus;
+
+ /* NUMA information: */
+ uint64_t numa_nodes;
+ uint64_t *node_mem;
+ uint64_t *node_cpu;
};
#define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
@@ -46,23 +79,64 @@ struct PCMachineState {
#define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
#define PC_MACHINE_VMPORT "vmport"
#define PC_MACHINE_SMM "smm"
-#define PC_MACHINE_ENFORCE_ALIGNED_DIMM "enforce-aligned-dimm"
+#define PC_MACHINE_NVDIMM "nvdimm"
/**
* PCMachineClass:
+ *
+ * Methods:
+ *
* @get_hotplug_handler: pointer to parent class callback @get_hotplug_handler
+ *
+ * Compat fields:
+ *
+ * @enforce_aligned_dimm: check that DIMM's address/size is aligned by
+ * backend's alignment value if provided
+ * @acpi_data_size: Size of the chunk of memory at the top of RAM
+ * for the BIOS ACPI tables and other BIOS
+ * datastructures.
+ * @gigabyte_align: Make sure that guest addresses aligned at
+ * 1Gbyte boundaries get mapped to host
+ * addresses aligned at 1Gbyte boundaries. This
+ * way we can use 1GByte pages in the host.
+ *
*/
struct PCMachineClass {
/*< private >*/
MachineClass parent_class;
/*< public >*/
+
+ /* Methods: */
HotplugHandler *(*get_hotplug_handler)(MachineState *machine,
DeviceState *dev);
-};
-typedef struct PCMachineState PCMachineState;
-typedef struct PCMachineClass PCMachineClass;
+ /* Device configuration: */
+ bool pci_enabled;
+ bool kvmclock_enabled;
+
+ /* Compat options: */
+
+ /* ACPI compat: */
+ bool has_acpi_build;
+ bool rsdp_in_ram;
+ int legacy_acpi_table_size;
+ unsigned acpi_data_size;
+
+ /* SMBIOS compat: */
+ bool smbios_defaults;
+ bool smbios_legacy_mode;
+ bool smbios_uuid_encoded;
+
+ /* RAM / address space compat: */
+ bool gigabyte_align;
+ bool has_reserved_memory;
+ bool enforce_aligned_dimm;
+ bool broken_reserved_end;
+
+ /* TSC rate migration: */
+ bool save_tsc_khz;
+};
#define TYPE_PC_MACHINE "generic-pc-machine"
#define PC_MACHINE(obj) \
@@ -90,21 +164,6 @@ typedef struct PcPciInfo {
#define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len"
#define ACPI_PM_PROP_TCO_ENABLED "enable_tco"
-struct PcGuestInfo {
- bool isapc_ram_fw;
- hwaddr ram_size, ram_size_below_4g;
- unsigned apic_id_limit;
- bool apic_xrupt_override;
- uint64_t numa_nodes;
- uint64_t *node_mem;
- uint64_t *node_cpu;
- FWCfgState *fw_cfg;
- int legacy_acpi_table_size;
- bool has_acpi_build;
- bool has_reserved_memory;
- bool rsdp_in_ram;
-};
-
/* parallel.c */
void parallel_hds_isa_init(ISABus *bus, int n);
@@ -123,6 +182,11 @@ int pic_get_output(DeviceState *d);
void hmp_info_pic(Monitor *mon, const QDict *qdict);
void hmp_info_irq(Monitor *mon, const QDict *qdict);
+/* ioapic.c */
+
+void kvm_ioapic_dump_state(Monitor *mon, const QDict *qdict);
+void ioapic_dump_state(Monitor *mon, const QDict *qdict);
+
/* Global System Interrupts */
#define GSI_NUM_PINS IOAPIC_NUM_PINS
@@ -162,14 +226,11 @@ bool pc_machine_is_smm_enabled(PCMachineState *pcms);
void pc_register_ferr_irq(qemu_irq irq);
void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
-void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge);
+void pc_cpus_init(PCMachineState *pcms);
void pc_hot_add_cpu(const int64_t id, Error **errp);
void pc_acpi_init(const char *default_dsdt);
-PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
- ram_addr_t above_4g_mem_size);
-
-void pc_set_legacy_acpi_data_size(void);
+void pc_guest_info_init(PCMachineState *pcms);
#define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start"
#define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end"
@@ -182,28 +243,20 @@ void pc_set_legacy_acpi_data_size(void);
void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
MemoryRegion *pci_address_space);
-FWCfgState *xen_load_linux(const char *kernel_filename,
- const char *kernel_cmdline,
- const char *initrd_filename,
- ram_addr_t below_4g_mem_size,
- PcGuestInfo *guest_info);
-FWCfgState *pc_memory_init(MachineState *machine,
- MemoryRegion *system_memory,
- ram_addr_t below_4g_mem_size,
- ram_addr_t above_4g_mem_size,
- MemoryRegion *rom_memory,
- MemoryRegion **ram_memory,
- PcGuestInfo *guest_info);
+void xen_load_linux(PCMachineState *pcms);
+void pc_memory_init(PCMachineState *pcms,
+ MemoryRegion *system_memory,
+ MemoryRegion *rom_memory,
+ MemoryRegion **ram_memory);
qemu_irq pc_allocate_cpu_irq(void);
DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
ISADevice **rtc_state,
bool create_fdctrl,
bool no_vmport,
- uint32 hpet_irqs);
+ uint32_t hpet_irqs);
void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
-void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
- const char *boot_device, MachineState *machine,
+void pc_cmos_init(PCMachineState *pcms,
BusState *ide0, BusState *ide1,
ISADevice *s);
void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
@@ -213,6 +266,11 @@ typedef void (*cpu_set_smm_t)(int smm, void *arg);
void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
+ISADevice *pc_find_fdc0(void);
+int cmos_get_fd_drive_type(FloppyDriveType fd0);
+
+#define FW_CFG_IO_BASE 0x510
+
/* acpi_piix.c */
I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
@@ -227,7 +285,13 @@ extern int no_hpet;
struct PCII440FXState;
typedef struct PCII440FXState PCII440FXState;
-PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
+#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
+#define TYPE_I440FX_PCI_DEVICE "i440FX"
+
+#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
+
+PCIBus *i440fx_init(const char *host_type, const char *pci_type,
+ PCII440FXState **pi440fx_state, int *piix_devfn,
ISABus **isa_bus, qemu_irq *pic,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
@@ -292,316 +356,489 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t);
int e820_get_num_entries(void);
bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
+#define PC_COMPAT_2_5 \
+ HW_COMPAT_2_5
+
+#define PC_COMPAT_2_4 \
+ PC_COMPAT_2_5 \
+ HW_COMPAT_2_4 \
+ {\
+ .driver = "Haswell-" TYPE_X86_CPU,\
+ .property = "abm",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Haswell-noTSX-" TYPE_X86_CPU,\
+ .property = "abm",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Broadwell-" TYPE_X86_CPU,\
+ .property = "abm",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Broadwell-noTSX-" TYPE_X86_CPU,\
+ .property = "abm",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "host" "-" TYPE_X86_CPU,\
+ .property = "host-cache-info",\
+ .value = "on",\
+ },\
+ {\
+ .driver = TYPE_X86_CPU,\
+ .property = "check",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "qemu64" "-" TYPE_X86_CPU,\
+ .property = "sse4a",\
+ .value = "on",\
+ },\
+ {\
+ .driver = "qemu64" "-" TYPE_X86_CPU,\
+ .property = "abm",\
+ .value = "on",\
+ },\
+ {\
+ .driver = "qemu64" "-" TYPE_X86_CPU,\
+ .property = "popcnt",\
+ .value = "on",\
+ },\
+ {\
+ .driver = "qemu32" "-" TYPE_X86_CPU,\
+ .property = "popcnt",\
+ .value = "on",\
+ },{\
+ .driver = "Opteron_G2" "-" TYPE_X86_CPU,\
+ .property = "rdtscp",\
+ .value = "on",\
+ },{\
+ .driver = "Opteron_G3" "-" TYPE_X86_CPU,\
+ .property = "rdtscp",\
+ .value = "on",\
+ },{\
+ .driver = "Opteron_G4" "-" TYPE_X86_CPU,\
+ .property = "rdtscp",\
+ .value = "on",\
+ },{\
+ .driver = "Opteron_G5" "-" TYPE_X86_CPU,\
+ .property = "rdtscp",\
+ .value = "on",\
+ },
+
+
#define PC_COMPAT_2_3 \
- HW_COMPAT_2_3 \
- {\
- .driver = TYPE_X86_CPU,\
- .property = "arat",\
- .value = "off",\
- },{\
- .driver = "qemu64" "-" TYPE_X86_CPU,\
- .property = "level",\
- .value = stringify(4),\
- },{\
- .driver = "kvm64" "-" TYPE_X86_CPU,\
- .property = "level",\
- .value = stringify(5),\
- },{\
- .driver = "pentium3" "-" TYPE_X86_CPU,\
- .property = "level",\
- .value = stringify(2),\
- },{\
- .driver = "n270" "-" TYPE_X86_CPU,\
- .property = "level",\
- .value = stringify(5),\
- },{\
- .driver = "Conroe" "-" TYPE_X86_CPU,\
- .property = "level",\
- .value = stringify(4),\
- },{\
- .driver = "Penryn" "-" TYPE_X86_CPU,\
- .property = "level",\
- .value = stringify(4),\
- },{\
- .driver = "Nehalem" "-" TYPE_X86_CPU,\
- .property = "level",\
- .value = stringify(4),\
- },{\
- .driver = "n270" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
- .value = stringify(0x8000000a),\
- },{\
- .driver = "Penryn" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
- .value = stringify(0x8000000a),\
- },{\
- .driver = "Conroe" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
- .value = stringify(0x8000000a),\
- },{\
- .driver = "Nehalem" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
- .value = stringify(0x8000000a),\
- },{\
- .driver = "Westmere" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
- .value = stringify(0x8000000a),\
- },{\
- .driver = "SandyBridge" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
- .value = stringify(0x8000000a),\
- },{\
- .driver = "IvyBridge" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
- .value = stringify(0x8000000a),\
- },{\
- .driver = "Haswell" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
- .value = stringify(0x8000000a),\
- },{\
- .driver = "Haswell-noTSX" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
- .value = stringify(0x8000000a),\
- },{\
- .driver = "Broadwell" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
- .value = stringify(0x8000000a),\
- },{\
- .driver = "Broadwell-noTSX" "-" TYPE_X86_CPU,\
- .property = "xlevel",\
- .value = stringify(0x8000000a),\
- },
+ PC_COMPAT_2_4 \
+ HW_COMPAT_2_3 \
+ {\
+ .driver = TYPE_X86_CPU,\
+ .property = "arat",\
+ .value = "off",\
+ },{\
+ .driver = "qemu64" "-" TYPE_X86_CPU,\
+ .property = "level",\
+ .value = stringify(4),\
+ },{\
+ .driver = "kvm64" "-" TYPE_X86_CPU,\
+ .property = "level",\
+ .value = stringify(5),\
+ },{\
+ .driver = "pentium3" "-" TYPE_X86_CPU,\
+ .property = "level",\
+ .value = stringify(2),\
+ },{\
+ .driver = "n270" "-" TYPE_X86_CPU,\
+ .property = "level",\
+ .value = stringify(5),\
+ },{\
+ .driver = "Conroe" "-" TYPE_X86_CPU,\
+ .property = "level",\
+ .value = stringify(4),\
+ },{\
+ .driver = "Penryn" "-" TYPE_X86_CPU,\
+ .property = "level",\
+ .value = stringify(4),\
+ },{\
+ .driver = "Nehalem" "-" TYPE_X86_CPU,\
+ .property = "level",\
+ .value = stringify(4),\
+ },{\
+ .driver = "n270" "-" TYPE_X86_CPU,\
+ .property = "xlevel",\
+ .value = stringify(0x8000000a),\
+ },{\
+ .driver = "Penryn" "-" TYPE_X86_CPU,\
+ .property = "xlevel",\
+ .value = stringify(0x8000000a),\
+ },{\
+ .driver = "Conroe" "-" TYPE_X86_CPU,\
+ .property = "xlevel",\
+ .value = stringify(0x8000000a),\
+ },{\
+ .driver = "Nehalem" "-" TYPE_X86_CPU,\
+ .property = "xlevel",\
+ .value = stringify(0x8000000a),\
+ },{\
+ .driver = "Westmere" "-" TYPE_X86_CPU,\
+ .property = "xlevel",\
+ .value = stringify(0x8000000a),\
+ },{\
+ .driver = "SandyBridge" "-" TYPE_X86_CPU,\
+ .property = "xlevel",\
+ .value = stringify(0x8000000a),\
+ },{\
+ .driver = "IvyBridge" "-" TYPE_X86_CPU,\
+ .property = "xlevel",\
+ .value = stringify(0x8000000a),\
+ },{\
+ .driver = "Haswell" "-" TYPE_X86_CPU,\
+ .property = "xlevel",\
+ .value = stringify(0x8000000a),\
+ },{\
+ .driver = "Haswell-noTSX" "-" TYPE_X86_CPU,\
+ .property = "xlevel",\
+ .value = stringify(0x8000000a),\
+ },{\
+ .driver = "Broadwell" "-" TYPE_X86_CPU,\
+ .property = "xlevel",\
+ .value = stringify(0x8000000a),\
+ },{\
+ .driver = "Broadwell-noTSX" "-" TYPE_X86_CPU,\
+ .property = "xlevel",\
+ .value = stringify(0x8000000a),\
+ },
#define PC_COMPAT_2_2 \
- PC_COMPAT_2_3 \
- HW_COMPAT_2_2
+ PC_COMPAT_2_3 \
+ HW_COMPAT_2_2 \
+ {\
+ .driver = "kvm64" "-" TYPE_X86_CPU,\
+ .property = "vme",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "kvm32" "-" TYPE_X86_CPU,\
+ .property = "vme",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Conroe" "-" TYPE_X86_CPU,\
+ .property = "vme",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Penryn" "-" TYPE_X86_CPU,\
+ .property = "vme",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Nehalem" "-" TYPE_X86_CPU,\
+ .property = "vme",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Westmere" "-" TYPE_X86_CPU,\
+ .property = "vme",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "SandyBridge" "-" TYPE_X86_CPU,\
+ .property = "vme",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Haswell" "-" TYPE_X86_CPU,\
+ .property = "vme",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Broadwell" "-" TYPE_X86_CPU,\
+ .property = "vme",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Opteron_G1" "-" TYPE_X86_CPU,\
+ .property = "vme",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Opteron_G2" "-" TYPE_X86_CPU,\
+ .property = "vme",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Opteron_G3" "-" TYPE_X86_CPU,\
+ .property = "vme",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Opteron_G4" "-" TYPE_X86_CPU,\
+ .property = "vme",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Opteron_G5" "-" TYPE_X86_CPU,\
+ .property = "vme",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Haswell" "-" TYPE_X86_CPU,\
+ .property = "f16c",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Haswell" "-" TYPE_X86_CPU,\
+ .property = "rdrand",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Broadwell" "-" TYPE_X86_CPU,\
+ .property = "f16c",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Broadwell" "-" TYPE_X86_CPU,\
+ .property = "rdrand",\
+ .value = "off",\
+ },
#define PC_COMPAT_2_1 \
- PC_COMPAT_2_2 \
- HW_COMPAT_2_1
+ PC_COMPAT_2_2 \
+ HW_COMPAT_2_1 \
+ {\
+ .driver = "coreduo" "-" TYPE_X86_CPU,\
+ .property = "vmx",\
+ .value = "on",\
+ },\
+ {\
+ .driver = "core2duo" "-" TYPE_X86_CPU,\
+ .property = "vmx",\
+ .value = "on",\
+ },
#define PC_COMPAT_2_0 \
- PC_COMPAT_2_1 \
- {\
- .driver = "virtio-scsi-pci",\
- .property = "any_layout",\
- .value = "off",\
- },{\
- .driver = "PIIX4_PM",\
- .property = "memory-hotplug-support",\
- .value = "off",\
- },\
- {\
- .driver = "apic",\
- .property = "version",\
- .value = stringify(0x11),\
- },\
- {\
- .driver = "nec-usb-xhci",\
- .property = "superspeed-ports-first",\
- .value = "off",\
- },\
- {\
- .driver = "nec-usb-xhci",\
- .property = "force-pcie-endcap",\
- .value = "on",\
- },\
- {\
- .driver = "pci-serial",\
- .property = "prog_if",\
- .value = stringify(0),\
- },\
- {\
- .driver = "pci-serial-2x",\
- .property = "prog_if",\
- .value = stringify(0),\
- },\
- {\
- .driver = "pci-serial-4x",\
- .property = "prog_if",\
- .value = stringify(0),\
- },\
- {\
- .driver = "virtio-net-pci",\
- .property = "guest_announce",\
- .value = "off",\
- },\
- {\
- .driver = "ICH9-LPC",\
- .property = "memory-hotplug-support",\
- .value = "off",\
- },{\
- .driver = "xio3130-downstream",\
- .property = COMPAT_PROP_PCP,\
- .value = "off",\
- },{\
- .driver = "ioh3420",\
- .property = COMPAT_PROP_PCP,\
- .value = "off",\
- },
+ PC_COMPAT_2_1 \
+ {\
+ .driver = "virtio-scsi-pci",\
+ .property = "any_layout",\
+ .value = "off",\
+ },{\
+ .driver = "PIIX4_PM",\
+ .property = "memory-hotplug-support",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "apic",\
+ .property = "version",\
+ .value = stringify(0x11),\
+ },\
+ {\
+ .driver = "nec-usb-xhci",\
+ .property = "superspeed-ports-first",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "nec-usb-xhci",\
+ .property = "force-pcie-endcap",\
+ .value = "on",\
+ },\
+ {\
+ .driver = "pci-serial",\
+ .property = "prog_if",\
+ .value = stringify(0),\
+ },\
+ {\
+ .driver = "pci-serial-2x",\
+ .property = "prog_if",\
+ .value = stringify(0),\
+ },\
+ {\
+ .driver = "pci-serial-4x",\
+ .property = "prog_if",\
+ .value = stringify(0),\
+ },\
+ {\
+ .driver = "virtio-net-pci",\
+ .property = "guest_announce",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "ICH9-LPC",\
+ .property = "memory-hotplug-support",\
+ .value = "off",\
+ },{\
+ .driver = "xio3130-downstream",\
+ .property = COMPAT_PROP_PCP,\
+ .value = "off",\
+ },{\
+ .driver = "ioh3420",\
+ .property = COMPAT_PROP_PCP,\
+ .value = "off",\
+ },
#define PC_COMPAT_1_7 \
- PC_COMPAT_2_0 \
- {\
- .driver = TYPE_USB_DEVICE,\
- .property = "msos-desc",\
- .value = "no",\
- },\
- {\
- .driver = "PIIX4_PM",\
- .property = "acpi-pci-hotplug-with-bridge-support",\
- .value = "off",\
- },\
- {\
- .driver = "hpet",\
- .property = HPET_INTCAP,\
- .value = stringify(4),\
- },
+ PC_COMPAT_2_0 \
+ {\
+ .driver = TYPE_USB_DEVICE,\
+ .property = "msos-desc",\
+ .value = "no",\
+ },\
+ {\
+ .driver = "PIIX4_PM",\
+ .property = "acpi-pci-hotplug-with-bridge-support",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "hpet",\
+ .property = HPET_INTCAP,\
+ .value = stringify(4),\
+ },
#define PC_COMPAT_1_6 \
- PC_COMPAT_1_7 \
- {\
- .driver = "e1000",\
- .property = "mitigation",\
- .value = "off",\
- },{\
- .driver = "qemu64-" TYPE_X86_CPU,\
- .property = "model",\
- .value = stringify(2),\
- },{\
- .driver = "qemu32-" TYPE_X86_CPU,\
- .property = "model",\
- .value = stringify(3),\
- },{\
- .driver = "i440FX-pcihost",\
- .property = "short_root_bus",\
- .value = stringify(1),\
- },{\
- .driver = "q35-pcihost",\
- .property = "short_root_bus",\
- .value = stringify(1),\
- },
+ PC_COMPAT_1_7 \
+ {\
+ .driver = "e1000",\
+ .property = "mitigation",\
+ .value = "off",\
+ },{\
+ .driver = "qemu64-" TYPE_X86_CPU,\
+ .property = "model",\
+ .value = stringify(2),\
+ },{\
+ .driver = "qemu32-" TYPE_X86_CPU,\
+ .property = "model",\
+ .value = stringify(3),\
+ },{\
+ .driver = "i440FX-pcihost",\
+ .property = "short_root_bus",\
+ .value = stringify(1),\
+ },{\
+ .driver = "q35-pcihost",\
+ .property = "short_root_bus",\
+ .value = stringify(1),\
+ },
#define PC_COMPAT_1_5 \
- PC_COMPAT_1_6 \
- {\
- .driver = "Conroe-" TYPE_X86_CPU,\
- .property = "model",\
- .value = stringify(2),\
- },{\
- .driver = "Conroe-" TYPE_X86_CPU,\
- .property = "level",\
- .value = stringify(2),\
- },{\
- .driver = "Penryn-" TYPE_X86_CPU,\
- .property = "model",\
- .value = stringify(2),\
- },{\
- .driver = "Penryn-" TYPE_X86_CPU,\
- .property = "level",\
- .value = stringify(2),\
- },{\
- .driver = "Nehalem-" TYPE_X86_CPU,\
- .property = "model",\
- .value = stringify(2),\
- },{\
- .driver = "Nehalem-" TYPE_X86_CPU,\
- .property = "level",\
- .value = stringify(2),\
- },{\
- .driver = "virtio-net-pci",\
- .property = "any_layout",\
- .value = "off",\
- },{\
- .driver = TYPE_X86_CPU,\
- .property = "pmu",\
- .value = "on",\
- },{\
- .driver = "i440FX-pcihost",\
- .property = "short_root_bus",\
- .value = stringify(0),\
- },{\
- .driver = "q35-pcihost",\
- .property = "short_root_bus",\
- .value = stringify(0),\
- },
+ PC_COMPAT_1_6 \
+ {\
+ .driver = "Conroe-" TYPE_X86_CPU,\
+ .property = "model",\
+ .value = stringify(2),\
+ },{\
+ .driver = "Conroe-" TYPE_X86_CPU,\
+ .property = "level",\
+ .value = stringify(2),\
+ },{\
+ .driver = "Penryn-" TYPE_X86_CPU,\
+ .property = "model",\
+ .value = stringify(2),\
+ },{\
+ .driver = "Penryn-" TYPE_X86_CPU,\
+ .property = "level",\
+ .value = stringify(2),\
+ },{\
+ .driver = "Nehalem-" TYPE_X86_CPU,\
+ .property = "model",\
+ .value = stringify(2),\
+ },{\
+ .driver = "Nehalem-" TYPE_X86_CPU,\
+ .property = "level",\
+ .value = stringify(2),\
+ },{\
+ .driver = "virtio-net-pci",\
+ .property = "any_layout",\
+ .value = "off",\
+ },{\
+ .driver = TYPE_X86_CPU,\
+ .property = "pmu",\
+ .value = "on",\
+ },{\
+ .driver = "i440FX-pcihost",\
+ .property = "short_root_bus",\
+ .value = stringify(0),\
+ },{\
+ .driver = "q35-pcihost",\
+ .property = "short_root_bus",\
+ .value = stringify(0),\
+ },
#define PC_COMPAT_1_4 \
- PC_COMPAT_1_5 \
- {\
- .driver = "scsi-hd",\
- .property = "discard_granularity",\
- .value = stringify(0),\
- },{\
- .driver = "scsi-cd",\
- .property = "discard_granularity",\
- .value = stringify(0),\
- },{\
- .driver = "scsi-disk",\
- .property = "discard_granularity",\
- .value = stringify(0),\
- },{\
- .driver = "ide-hd",\
- .property = "discard_granularity",\
- .value = stringify(0),\
- },{\
- .driver = "ide-cd",\
- .property = "discard_granularity",\
- .value = stringify(0),\
- },{\
- .driver = "ide-drive",\
- .property = "discard_granularity",\
- .value = stringify(0),\
- },{\
- .driver = "virtio-blk-pci",\
- .property = "discard_granularity",\
- .value = stringify(0),\
- },{\
- .driver = "virtio-serial-pci",\
- .property = "vectors",\
- /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\
- .value = stringify(0xFFFFFFFF),\
- },{ \
- .driver = "virtio-net-pci", \
- .property = "ctrl_guest_offloads", \
- .value = "off", \
- },{\
- .driver = "e1000",\
- .property = "romfile",\
- .value = "pxe-e1000.rom",\
- },{\
- .driver = "ne2k_pci",\
- .property = "romfile",\
- .value = "pxe-ne2k_pci.rom",\
- },{\
- .driver = "pcnet",\
- .property = "romfile",\
- .value = "pxe-pcnet.rom",\
- },{\
- .driver = "rtl8139",\
- .property = "romfile",\
- .value = "pxe-rtl8139.rom",\
- },{\
- .driver = "virtio-net-pci",\
- .property = "romfile",\
- .value = "pxe-virtio.rom",\
- },{\
- .driver = "486-" TYPE_X86_CPU,\
- .property = "model",\
- .value = stringify(0),\
- },
-
-static inline void pc_common_machine_options(MachineClass *m)
-{
- m->default_boot_order = "cad";
-}
-
-static inline void pc_default_machine_options(MachineClass *m)
-{
- pc_common_machine_options(m);
- m->hot_add_cpu = pc_hot_add_cpu;
- m->max_cpus = 255;
-}
+ PC_COMPAT_1_5 \
+ {\
+ .driver = "scsi-hd",\
+ .property = "discard_granularity",\
+ .value = stringify(0),\
+ },{\
+ .driver = "scsi-cd",\
+ .property = "discard_granularity",\
+ .value = stringify(0),\
+ },{\
+ .driver = "scsi-disk",\
+ .property = "discard_granularity",\
+ .value = stringify(0),\
+ },{\
+ .driver = "ide-hd",\
+ .property = "discard_granularity",\
+ .value = stringify(0),\
+ },{\
+ .driver = "ide-cd",\
+ .property = "discard_granularity",\
+ .value = stringify(0),\
+ },{\
+ .driver = "ide-drive",\
+ .property = "discard_granularity",\
+ .value = stringify(0),\
+ },{\
+ .driver = "virtio-blk-pci",\
+ .property = "discard_granularity",\
+ .value = stringify(0),\
+ },{\
+ .driver = "virtio-serial-pci",\
+ .property = "vectors",\
+ /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\
+ .value = stringify(0xFFFFFFFF),\
+ },{ \
+ .driver = "virtio-net-pci", \
+ .property = "ctrl_guest_offloads", \
+ .value = "off", \
+ },{\
+ .driver = "e1000",\
+ .property = "romfile",\
+ .value = "pxe-e1000.rom",\
+ },{\
+ .driver = "ne2k_pci",\
+ .property = "romfile",\
+ .value = "pxe-ne2k_pci.rom",\
+ },{\
+ .driver = "pcnet",\
+ .property = "romfile",\
+ .value = "pxe-pcnet.rom",\
+ },{\
+ .driver = "rtl8139",\
+ .property = "romfile",\
+ .value = "pxe-rtl8139.rom",\
+ },{\
+ .driver = "virtio-net-pci",\
+ .property = "romfile",\
+ .value = "pxe-virtio.rom",\
+ },{\
+ .driver = "486-" TYPE_X86_CPU,\
+ .property = "model",\
+ .value = stringify(0),\
+ },\
+ {\
+ .driver = "n270" "-" TYPE_X86_CPU,\
+ .property = "movbe",\
+ .value = "off",\
+ },\
+ {\
+ .driver = "Westmere" "-" TYPE_X86_CPU,\
+ .property = "pclmulqdq",\
+ .value = "off",\
+ },
#define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \
@@ -620,14 +857,7 @@ static inline void pc_default_machine_options(MachineClass *m)
{ \
type_register(&pc_machine_type_##suffix); \
} \
- machine_init(pc_machine_init_##suffix)
-
-#define SET_MACHINE_COMPAT(m, COMPAT) do { \
- static GlobalProperty props[] = { \
- COMPAT \
- { /* end of list */ } \
- }; \
- (m)->compat_props = props; \
-} while (0)
+ type_init(pc_machine_init_##suffix)
+extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id);
#endif
diff --git a/qemu/include/hw/i386/topology.h b/qemu/include/hw/i386/topology.h
index 9c6f3a937..fc9557239 100644
--- a/qemu/include/hw/i386/topology.h
+++ b/qemu/include/hw/i386/topology.h
@@ -38,8 +38,6 @@
* CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_width().
*/
-#include <stdint.h>
-#include <string.h>
#include "qemu/bitops.h"
@@ -47,6 +45,12 @@
*/
typedef uint32_t apic_id_t;
+typedef struct X86CPUTopoInfo {
+ unsigned pkg_id;
+ unsigned core_id;
+ unsigned smt_id;
+} X86CPUTopoInfo;
+
/* Return the bit width needed for 'count' IDs
*/
static unsigned apicid_bitwidth_for_count(unsigned count)
@@ -92,13 +96,11 @@ static inline unsigned apicid_pkg_offset(unsigned nr_cores, unsigned nr_threads)
*/
static inline apic_id_t apicid_from_topo_ids(unsigned nr_cores,
unsigned nr_threads,
- unsigned pkg_id,
- unsigned core_id,
- unsigned smt_id)
+ const X86CPUTopoInfo *topo)
{
- return (pkg_id << apicid_pkg_offset(nr_cores, nr_threads)) |
- (core_id << apicid_core_offset(nr_cores, nr_threads)) |
- smt_id;
+ return (topo->pkg_id << apicid_pkg_offset(nr_cores, nr_threads)) |
+ (topo->core_id << apicid_core_offset(nr_cores, nr_threads)) |
+ topo->smt_id;
}
/* Calculate thread/core/package IDs for a specific topology,
@@ -107,14 +109,12 @@ static inline apic_id_t apicid_from_topo_ids(unsigned nr_cores,
static inline void x86_topo_ids_from_idx(unsigned nr_cores,
unsigned nr_threads,
unsigned cpu_index,
- unsigned *pkg_id,
- unsigned *core_id,
- unsigned *smt_id)
+ X86CPUTopoInfo *topo)
{
unsigned core_index = cpu_index / nr_threads;
- *smt_id = cpu_index % nr_threads;
- *core_id = core_index % nr_cores;
- *pkg_id = core_index / nr_cores;
+ topo->smt_id = cpu_index % nr_threads;
+ topo->core_id = core_index % nr_cores;
+ topo->pkg_id = core_index / nr_cores;
}
/* Make APIC ID for the CPU 'cpu_index'
@@ -125,10 +125,9 @@ static inline apic_id_t x86_apicid_from_cpu_idx(unsigned nr_cores,
unsigned nr_threads,
unsigned cpu_index)
{
- unsigned pkg_id, core_id, smt_id;
- x86_topo_ids_from_idx(nr_cores, nr_threads, cpu_index,
- &pkg_id, &core_id, &smt_id);
- return apicid_from_topo_ids(nr_cores, nr_threads, pkg_id, core_id, smt_id);
+ X86CPUTopoInfo topo;
+ x86_topo_ids_from_idx(nr_cores, nr_threads, cpu_index, &topo);
+ return apicid_from_topo_ids(nr_cores, nr_threads, &topo);
}
#endif /* HW_I386_TOPOLOGY_H */
diff --git a/qemu/include/hw/input/adb.h b/qemu/include/hw/input/adb.h
index bdfccd404..db51d0380 100644
--- a/qemu/include/hw/input/adb.h
+++ b/qemu/include/hw/input/adb.h
@@ -79,7 +79,7 @@ struct ADBBusState {
int adb_request(ADBBusState *s, uint8_t *buf_out,
const uint8_t *buf, int len);
-int adb_poll(ADBBusState *s, uint8_t *buf_out);
+int adb_poll(ADBBusState *s, uint8_t *buf_out, uint16_t poll_mask);
#define TYPE_ADB_KEYBOARD "adb-keyboard"
#define TYPE_ADB_MOUSE "adb-mouse"
diff --git a/qemu/include/hw/intc/arm_gic_common.h b/qemu/include/hw/intc/arm_gic_common.h
index 899db3d7a..f4c349a2e 100644
--- a/qemu/include/hw/intc/arm_gic_common.h
+++ b/qemu/include/hw/intc/arm_gic_common.h
@@ -68,7 +68,6 @@ typedef struct GICState {
uint8_t irq_target[GIC_MAXIRQ];
uint8_t priority1[GIC_INTERNAL][GIC_NCPU];
uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL];
- uint16_t last_active[GIC_MAXIRQ][GIC_NCPU];
/* For each SGI on the target CPU, we store 8 bits
* indicating which source CPUs have made this SGI
* pending on the target CPU. These correspond to
@@ -78,7 +77,6 @@ typedef struct GICState {
uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU];
uint16_t priority_mask[GIC_NCPU];
- uint16_t running_irq[GIC_NCPU];
uint16_t running_priority[GIC_NCPU];
uint16_t current_pending[GIC_NCPU];
@@ -96,16 +94,9 @@ typedef struct GICState {
* If an interrupt for preemption level X is active, then
* APRn[X mod 32] == 0b1, where n = X / 32
* otherwise the bit is clear.
- *
- * TODO: rewrite the interrupt acknowlege/complete routines to use
- * the APR registers to track the necessary information to update
- * s->running_priority[] on interrupt completion (ie completely remove
- * last_active[][] and running_irq[]). This will be necessary if we ever
- * want to support TCG<->KVM migration, or TCG guests which can
- * do power management involving powering down and restarting
- * the GIC.
*/
uint32_t apr[GIC_NR_APRS][GIC_NCPU];
+ uint32_t nsapr[GIC_NR_APRS][GIC_NCPU];
uint32_t num_cpu;
@@ -118,7 +109,9 @@ typedef struct GICState {
uint32_t num_irq;
uint32_t revision;
bool security_extn;
+ bool irq_reset_nonsecure; /* configure IRQs as group 1 (NS) on reset? */
int dev_fd; /* kvm device fd if backed by kvm vgic support */
+ Error *migration_blocker;
} GICState;
#define TYPE_ARM_GIC_COMMON "arm_gic_common"
@@ -138,4 +131,7 @@ typedef struct ARMGICCommonClass {
void (*post_load)(GICState *s);
} ARMGICCommonClass;
+void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
+ const MemoryRegionOps *ops);
+
#endif
diff --git a/qemu/include/hw/intc/arm_gicv3_common.h b/qemu/include/hw/intc/arm_gicv3_common.h
new file mode 100644
index 000000000..c2fd8da4e
--- /dev/null
+++ b/qemu/include/hw/intc/arm_gicv3_common.h
@@ -0,0 +1,68 @@
+/*
+ * ARM GIC support
+ *
+ * Copyright (c) 2012 Linaro Limited
+ * Copyright (c) 2015 Huawei.
+ * Written by Peter Maydell
+ * Extended to 64 cores by Shlomo Pongratz
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_ARM_GICV3_COMMON_H
+#define HW_ARM_GICV3_COMMON_H
+
+#include "hw/sysbus.h"
+#include "hw/intc/arm_gic_common.h"
+
+typedef struct GICv3State {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ qemu_irq *parent_irq;
+ qemu_irq *parent_fiq;
+
+ MemoryRegion iomem_dist; /* Distributor */
+ MemoryRegion iomem_redist; /* Redistributors */
+
+ uint32_t num_cpu;
+ uint32_t num_irq;
+ uint32_t revision;
+ bool security_extn;
+
+ int dev_fd; /* kvm device fd if backed by kvm vgic support */
+} GICv3State;
+
+#define TYPE_ARM_GICV3_COMMON "arm-gicv3-common"
+#define ARM_GICV3_COMMON(obj) \
+ OBJECT_CHECK(GICv3State, (obj), TYPE_ARM_GICV3_COMMON)
+#define ARM_GICV3_COMMON_CLASS(klass) \
+ OBJECT_CLASS_CHECK(ARMGICv3CommonClass, (klass), TYPE_ARM_GICV3_COMMON)
+#define ARM_GICV3_COMMON_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(ARMGICv3CommonClass, (obj), TYPE_ARM_GICV3_COMMON)
+
+typedef struct ARMGICv3CommonClass {
+ /*< private >*/
+ SysBusDeviceClass parent_class;
+ /*< public >*/
+
+ void (*pre_save)(GICv3State *s);
+ void (*post_load)(GICv3State *s);
+} ARMGICv3CommonClass;
+
+void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
+ const MemoryRegionOps *ops);
+
+#endif
diff --git a/qemu/include/hw/intc/aspeed_vic.h b/qemu/include/hw/intc/aspeed_vic.h
new file mode 100644
index 000000000..107ff17c3
--- /dev/null
+++ b/qemu/include/hw/intc/aspeed_vic.h
@@ -0,0 +1,48 @@
+/*
+ * ASPEED Interrupt Controller (New)
+ *
+ * Andrew Jeffery <andrew@aj.id.au>
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * Need to add SVIC and CVIC support
+ */
+#ifndef ASPEED_VIC_H
+#define ASPEED_VIC_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_ASPEED_VIC "aspeed.vic"
+#define ASPEED_VIC(obj) OBJECT_CHECK(AspeedVICState, (obj), TYPE_ASPEED_VIC)
+
+#define ASPEED_VIC_NR_IRQS 51
+
+typedef struct AspeedVICState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion iomem;
+ qemu_irq irq;
+ qemu_irq fiq;
+
+ uint64_t level;
+ uint64_t raw;
+ uint64_t select;
+ uint64_t enable;
+ uint64_t trigger;
+
+ /* 0=edge, 1=level */
+ uint64_t sense;
+
+ /* 0=single-edge, 1=dual-edge */
+ uint64_t dual_edge;
+
+ /* 0=low-sensitive/falling-edge, 1=high-sensitive/rising-edge */
+ uint64_t event;
+} AspeedVICState;
+
+#endif /* ASPEED_VIC_H */
diff --git a/qemu/include/hw/intc/bcm2835_ic.h b/qemu/include/hw/intc/bcm2835_ic.h
new file mode 100644
index 000000000..fb75fa006
--- /dev/null
+++ b/qemu/include/hw/intc/bcm2835_ic.h
@@ -0,0 +1,33 @@
+/*
+ * Raspberry Pi emulation (c) 2012 Gregory Estrade
+ * This code is licensed under the GNU GPLv2 and later.
+ */
+
+#ifndef BCM2835_IC_H
+#define BCM2835_IC_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_BCM2835_IC "bcm2835-ic"
+#define BCM2835_IC(obj) OBJECT_CHECK(BCM2835ICState, (obj), TYPE_BCM2835_IC)
+
+#define BCM2835_IC_GPU_IRQ "gpu-irq"
+#define BCM2835_IC_ARM_IRQ "arm-irq"
+
+typedef struct BCM2835ICState {
+ /*< private >*/
+ SysBusDevice busdev;
+ /*< public >*/
+
+ MemoryRegion iomem;
+ qemu_irq irq;
+ qemu_irq fiq;
+
+ /* 64 GPU IRQs + 8 ARM IRQs = 72 total (GPU first) */
+ uint64_t gpu_irq_level, gpu_irq_enable;
+ uint8_t arm_irq_level, arm_irq_enable;
+ bool fiq_enable;
+ uint8_t fiq_select;
+} BCM2835ICState;
+
+#endif
diff --git a/qemu/include/hw/intc/bcm2836_control.h b/qemu/include/hw/intc/bcm2836_control.h
new file mode 100644
index 000000000..613f3c418
--- /dev/null
+++ b/qemu/include/hw/intc/bcm2836_control.h
@@ -0,0 +1,51 @@
+/*
+ * Raspberry Pi emulation (c) 2012 Gregory Estrade
+ * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
+ *
+ * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
+ * Written by Andrew Baumann
+ *
+ * This code is licensed under the GNU GPLv2 and later.
+ */
+
+#ifndef BCM2836_CONTROL_H
+#define BCM2836_CONTROL_H
+
+#include "hw/sysbus.h"
+
+/* 4 mailboxes per core, for 16 total */
+#define BCM2836_NCORES 4
+#define BCM2836_MBPERCORE 4
+
+#define TYPE_BCM2836_CONTROL "bcm2836-control"
+#define BCM2836_CONTROL(obj) \
+ OBJECT_CHECK(BCM2836ControlState, (obj), TYPE_BCM2836_CONTROL)
+
+typedef struct BCM2836ControlState {
+ /*< private >*/
+ SysBusDevice busdev;
+ /*< public >*/
+ MemoryRegion iomem;
+
+ /* mailbox state */
+ uint32_t mailboxes[BCM2836_NCORES * BCM2836_MBPERCORE];
+
+ /* interrupt routing/control registers */
+ uint8_t route_gpu_irq, route_gpu_fiq;
+ uint32_t timercontrol[BCM2836_NCORES];
+ uint32_t mailboxcontrol[BCM2836_NCORES];
+
+ /* interrupt status regs (derived from input pins; not visible to user) */
+ bool gpu_irq, gpu_fiq;
+ uint8_t timerirqs[BCM2836_NCORES];
+
+ /* interrupt source registers, post-routing (also input-derived; visible) */
+ uint32_t irqsrc[BCM2836_NCORES];
+ uint32_t fiqsrc[BCM2836_NCORES];
+
+ /* outputs to CPU cores */
+ qemu_irq irq[BCM2836_NCORES];
+ qemu_irq fiq[BCM2836_NCORES];
+} BCM2836ControlState;
+
+#endif
diff --git a/qemu/include/hw/intc/imx_avic.h b/qemu/include/hw/intc/imx_avic.h
new file mode 100644
index 000000000..1b8076901
--- /dev/null
+++ b/qemu/include/hw/intc/imx_avic.h
@@ -0,0 +1,55 @@
+/*
+ * i.MX31 Vectored Interrupt Controller
+ *
+ * Note this is NOT the PL192 provided by ARM, but
+ * a custom implementation by Freescale.
+ *
+ * Copyright (c) 2008 OKL
+ * Copyright (c) 2011 NICTA Pty Ltd
+ * Originally written by Hans Jiang
+ * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * TODO: implement vectors.
+ */
+#ifndef IMX_AVIC_H
+#define IMX_AVIC_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_IMX_AVIC "imx.avic"
+#define IMX_AVIC(obj) OBJECT_CHECK(IMXAVICState, (obj), TYPE_IMX_AVIC)
+
+#define IMX_AVIC_NUM_IRQS 64
+
+/* Interrupt Control Bits */
+#define ABFLAG (1<<25)
+#define ABFEN (1<<24)
+#define NIDIS (1<<22) /* Normal Interrupt disable */
+#define FIDIS (1<<21) /* Fast interrupt disable */
+#define NIAD (1<<20) /* Normal Interrupt Arbiter Rise ARM level */
+#define FIAD (1<<19) /* Fast Interrupt Arbiter Rise ARM level */
+#define NM (1<<18) /* Normal interrupt mode */
+
+#define PRIO_PER_WORD (sizeof(uint32_t) * 8 / 4)
+#define PRIO_WORDS (IMX_AVIC_NUM_IRQS/PRIO_PER_WORD)
+
+typedef struct IMXAVICState{
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion iomem;
+ uint64_t pending;
+ uint64_t enabled;
+ uint64_t is_fiq;
+ uint32_t intcntl;
+ uint32_t intmask;
+ qemu_irq irq;
+ qemu_irq fiq;
+ uint32_t prio[PRIO_WORDS]; /* Priorities are 4-bits each */
+} IMXAVICState;
+
+#endif /* IMX_AVIC_H */
diff --git a/qemu/include/hw/ipmi/ipmi.h b/qemu/include/hw/ipmi/ipmi.h
new file mode 100644
index 000000000..74a2b5af9
--- /dev/null
+++ b/qemu/include/hw/ipmi/ipmi.h
@@ -0,0 +1,258 @@
+/*
+ * IPMI base class
+ *
+ * Copyright (c) 2015 Corey Minyard, MontaVista Software, LLC
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_IPMI_H
+#define HW_IPMI_H
+
+#include "exec/memory.h"
+#include "qemu-common.h"
+#include "hw/qdev.h"
+
+#define MAX_IPMI_MSG_SIZE 300
+
+enum ipmi_op {
+ IPMI_RESET_CHASSIS,
+ IPMI_POWEROFF_CHASSIS,
+ IPMI_POWERON_CHASSIS,
+ IPMI_POWERCYCLE_CHASSIS,
+ IPMI_PULSE_DIAG_IRQ,
+ IPMI_SHUTDOWN_VIA_ACPI_OVERTEMP,
+ IPMI_SEND_NMI
+};
+
+#define IPMI_CC_INVALID_CMD 0xc1
+#define IPMI_CC_COMMAND_INVALID_FOR_LUN 0xc2
+#define IPMI_CC_TIMEOUT 0xc3
+#define IPMI_CC_OUT_OF_SPACE 0xc4
+#define IPMI_CC_INVALID_RESERVATION 0xc5
+#define IPMI_CC_REQUEST_DATA_TRUNCATED 0xc6
+#define IPMI_CC_REQUEST_DATA_LENGTH_INVALID 0xc7
+#define IPMI_CC_PARM_OUT_OF_RANGE 0xc9
+#define IPMI_CC_CANNOT_RETURN_REQ_NUM_BYTES 0xca
+#define IPMI_CC_REQ_ENTRY_NOT_PRESENT 0xcb
+#define IPMI_CC_INVALID_DATA_FIELD 0xcc
+#define IPMI_CC_BMC_INIT_IN_PROGRESS 0xd2
+#define IPMI_CC_COMMAND_NOT_SUPPORTED 0xd5
+
+#define IPMI_NETFN_APP 0x06
+
+#define IPMI_DEBUG 1
+
+/* Specified in the SMBIOS spec. */
+#define IPMI_SMBIOS_KCS 0x01
+#define IPMI_SMBIOS_SMIC 0x02
+#define IPMI_SMBIOS_BT 0x03
+#define IPMI_SMBIOS_SSIF 0x04
+
+/* IPMI Interface types (KCS, SMIC, BT) are prefixed with this */
+#define TYPE_IPMI_INTERFACE_PREFIX "ipmi-interface-"
+
+/*
+ * An IPMI Interface, the interface for talking between the target
+ * and the BMC.
+ */
+#define TYPE_IPMI_INTERFACE "ipmi-interface"
+#define IPMI_INTERFACE(obj) \
+ INTERFACE_CHECK(IPMIInterface, (obj), TYPE_IPMI_INTERFACE)
+#define IPMI_INTERFACE_CLASS(class) \
+ OBJECT_CLASS_CHECK(IPMIInterfaceClass, (class), TYPE_IPMI_INTERFACE)
+#define IPMI_INTERFACE_GET_CLASS(class) \
+ OBJECT_GET_CLASS(IPMIInterfaceClass, (class), TYPE_IPMI_INTERFACE)
+
+typedef struct IPMIInterface {
+ Object parent;
+} IPMIInterface;
+
+typedef struct IPMIInterfaceClass {
+ InterfaceClass parent;
+
+ void (*init)(struct IPMIInterface *s, Error **errp);
+
+ /*
+ * Perform various operations on the hardware. If checkonly is
+ * true, it will return if the operation can be performed, but it
+ * will not do the operation.
+ */
+ int (*do_hw_op)(struct IPMIInterface *s, enum ipmi_op op, int checkonly);
+
+ /*
+ * Enable/disable irqs on the interface when the BMC requests this.
+ */
+ void (*set_irq_enable)(struct IPMIInterface *s, int val);
+
+ /*
+ * Handle an event that occurred on the interface, generally the.
+ * target writing to a register.
+ */
+ void (*handle_if_event)(struct IPMIInterface *s);
+
+ /*
+ * The interfaces use this to perform certain ops
+ */
+ void (*set_atn)(struct IPMIInterface *s, int val, int irq);
+
+ /*
+ * Got an IPMI warm/cold reset.
+ */
+ void (*reset)(struct IPMIInterface *s, bool is_cold);
+
+ /*
+ * Handle a response from the bmc.
+ */
+ void (*handle_rsp)(struct IPMIInterface *s, uint8_t msg_id,
+ unsigned char *rsp, unsigned int rsp_len);
+
+ /*
+ * Set by the owner to hold the backend data for the interface.
+ */
+ void *(*get_backend_data)(struct IPMIInterface *s);
+} IPMIInterfaceClass;
+
+/*
+ * Define a BMC simulator (or perhaps a connection to a real BMC)
+ */
+#define TYPE_IPMI_BMC "ipmi-bmc"
+#define IPMI_BMC(obj) \
+ OBJECT_CHECK(IPMIBmc, (obj), TYPE_IPMI_BMC)
+#define IPMI_BMC_CLASS(obj_class) \
+ OBJECT_CLASS_CHECK(IPMIBmcClass, (obj_class), TYPE_IPMI_BMC)
+#define IPMI_BMC_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(IPMIBmcClass, (obj), TYPE_IPMI_BMC)
+
+typedef struct IPMIBmc {
+ DeviceState parent;
+
+ uint8_t slave_addr;
+
+ IPMIInterface *intf;
+} IPMIBmc;
+
+typedef struct IPMIBmcClass {
+ DeviceClass parent;
+
+ /* Called when the system resets to report to the bmc. */
+ void (*handle_reset)(struct IPMIBmc *s);
+
+ /*
+ * Handle a command to the bmc.
+ */
+ void (*handle_command)(struct IPMIBmc *s,
+ uint8_t *cmd, unsigned int cmd_len,
+ unsigned int max_cmd_len,
+ uint8_t msg_id);
+} IPMIBmcClass;
+
+/*
+ * Add a link property to obj that points to a BMC.
+ */
+void ipmi_bmc_find_and_link(Object *obj, Object **bmc);
+
+/*
+ * Used for transferring information to interfaces that add
+ * entries to firmware tables.
+ */
+typedef struct IPMIFwInfo {
+ const char *interface_name;
+ int interface_type;
+ uint8_t ipmi_spec_major_revision;
+ uint8_t ipmi_spec_minor_revision;
+ uint8_t i2c_slave_address;
+ uint32_t uuid;
+
+ uint64_t base_address;
+ uint64_t register_length;
+ uint8_t register_spacing;
+ enum {
+ IPMI_MEMSPACE_IO,
+ IPMI_MEMSPACE_MEM32,
+ IPMI_MEMSPACE_MEM64,
+ IPMI_MEMSPACE_SMBUS
+ } memspace;
+
+ int interrupt_number;
+ enum {
+ IPMI_LEVEL_IRQ,
+ IPMI_EDGE_IRQ
+ } irq_type;
+
+ const char *acpi_parent;
+} IPMIFwInfo;
+
+void ipmi_add_fwinfo(IPMIFwInfo *info, Error **errp);
+IPMIFwInfo *ipmi_first_fwinfo(void);
+IPMIFwInfo *ipmi_next_fwinfo(IPMIFwInfo *current);
+
+#ifdef IPMI_DEBUG
+#define ipmi_debug(fs, ...) \
+ fprintf(stderr, "IPMI (%s): " fs, __func__, ##__VA_ARGS__)
+#else
+#define ipmi_debug(fs, ...)
+#endif
+
+struct ipmi_sdr_header {
+ uint8_t rec_id[2];
+ uint8_t sdr_version; /* 0x51 */
+ uint8_t rec_type;
+ uint8_t rec_length;
+};
+#define IPMI_SDR_HEADER_SIZE sizeof(struct ipmi_sdr_header)
+
+#define ipmi_sdr_recid(sdr) ((sdr)->rec_id[0] | ((sdr)->rec_id[1] << 8))
+#define ipmi_sdr_length(sdr) ((sdr)->rec_length + IPMI_SDR_HEADER_SIZE)
+
+/*
+ * 43.2 SDR Type 02h. Compact Sensor Record
+ */
+#define IPMI_SDR_COMPACT_TYPE 2
+
+struct ipmi_sdr_compact {
+ struct ipmi_sdr_header header;
+
+ uint8_t sensor_owner_id;
+ uint8_t sensor_owner_lun;
+ uint8_t sensor_owner_number; /* byte 8 */
+ uint8_t entity_id;
+ uint8_t entity_instance;
+ uint8_t sensor_init;
+ uint8_t sensor_caps;
+ uint8_t sensor_type;
+ uint8_t reading_type;
+ uint8_t assert_mask[2]; /* byte 16 */
+ uint8_t deassert_mask[2];
+ uint8_t discrete_mask[2];
+ uint8_t sensor_unit1;
+ uint8_t sensor_unit2;
+ uint8_t sensor_unit3;
+ uint8_t sensor_direction[2]; /* byte 24 */
+ uint8_t positive_threshold;
+ uint8_t negative_threshold;
+ uint8_t reserved[3];
+ uint8_t oem;
+ uint8_t id_str_len; /* byte 32 */
+ uint8_t id_string[16];
+};
+
+typedef uint8_t ipmi_sdr_compact_buffer[sizeof(struct ipmi_sdr_compact)];
+
+#endif
diff --git a/qemu/include/hw/isa/apm.h b/qemu/include/hw/isa/apm.h
index 3edea5f62..4839ff1df 100644
--- a/qemu/include/hw/isa/apm.h
+++ b/qemu/include/hw/isa/apm.h
@@ -1,7 +1,6 @@
#ifndef APM_H
#define APM_H
-#include <stdint.h>
#include "qemu-common.h"
#include "hw/hw.h"
#include "exec/memory.h"
diff --git a/qemu/include/hw/isa/i8257.h b/qemu/include/hw/isa/i8257.h
new file mode 100644
index 000000000..8c44d3628
--- /dev/null
+++ b/qemu/include/hw/isa/i8257.h
@@ -0,0 +1,42 @@
+#ifndef HW_I8257_H
+#define HW_I8257_H
+
+#define TYPE_I8257 "i8257"
+
+typedef struct I8257Regs {
+ int now[2];
+ uint16_t base[2];
+ uint8_t mode;
+ uint8_t page;
+ uint8_t pageh;
+ uint8_t dack;
+ uint8_t eop;
+ IsaDmaTransferHandler transfer_handler;
+ void *opaque;
+} I8257Regs;
+
+typedef struct I8257State {
+ /* <private> */
+ ISADevice parent_obj;
+
+ /* <public> */
+ int32_t base;
+ int32_t page_base;
+ int32_t pageh_base;
+ int32_t dshift;
+
+ uint8_t status;
+ uint8_t command;
+ uint8_t mask;
+ uint8_t flip_flop;
+ I8257Regs regs[4];
+ MemoryRegion channel_io;
+ MemoryRegion cont_io;
+
+ QEMUBH *dma_bh;
+ bool dma_bh_scheduled;
+ int running;
+} I8257State;
+
+#endif
+
diff --git a/qemu/include/hw/isa/isa.h b/qemu/include/hw/isa/isa.h
index f21ceaafc..ffb2ea7cd 100644
--- a/qemu/include/hw/isa/isa.h
+++ b/qemu/include/hw/isa/isa.h
@@ -34,6 +34,44 @@ static inline uint16_t applesmc_port(void)
return 0;
}
+#define TYPE_ISADMA "isa-dma"
+
+#define ISADMA_CLASS(klass) \
+ OBJECT_CLASS_CHECK(IsaDmaClass, (klass), TYPE_ISADMA)
+#define ISADMA_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(IsaDmaClass, (obj), TYPE_ISADMA)
+#define ISADMA(obj) \
+ INTERFACE_CHECK(IsaDma, (obj), TYPE_ISADMA)
+
+struct IsaDma {
+ Object parent;
+};
+
+typedef enum {
+ ISADMA_TRANSFER_VERIFY,
+ ISADMA_TRANSFER_READ,
+ ISADMA_TRANSFER_WRITE,
+ ISADMA_TRANSFER_ILLEGAL,
+} IsaDmaTransferMode;
+
+typedef int (*IsaDmaTransferHandler)(void *opaque, int nchan, int pos,
+ int size);
+
+typedef struct IsaDmaClass {
+ InterfaceClass parent;
+
+ IsaDmaTransferMode (*get_transfer_mode)(IsaDma *obj, int nchan);
+ bool (*has_autoinitialization)(IsaDma *obj, int nchan);
+ int (*read_memory)(IsaDma *obj, int nchan, void *buf, int pos, int len);
+ int (*write_memory)(IsaDma *obj, int nchan, void *buf, int pos, int len);
+ void (*hold_DREQ)(IsaDma *obj, int nchan);
+ void (*release_DREQ)(IsaDma *obj, int nchan);
+ void (*schedule)(IsaDma *obj);
+ void (*register_channel)(IsaDma *obj, int nchan,
+ IsaDmaTransferHandler transfer_handler,
+ void *opaque);
+} IsaDmaClass;
+
typedef struct ISADeviceClass {
DeviceClass parent_class;
} ISADeviceClass;
@@ -46,6 +84,7 @@ struct ISABus {
MemoryRegion *address_space;
MemoryRegion *address_space_io;
qemu_irq *irqs;
+ IsaDma *dma[2];
};
struct ISADevice {
@@ -59,10 +98,12 @@ struct ISADevice {
};
ISABus *isa_bus_new(DeviceState *dev, MemoryRegion *address_space,
- MemoryRegion *address_space_io);
+ MemoryRegion *address_space_io, Error **errp);
void isa_bus_irqs(ISABus *bus, qemu_irq *irqs);
qemu_irq isa_get_irq(ISADevice *dev, int isairq);
void isa_init_irq(ISADevice *dev, qemu_irq *p, int isairq);
+void isa_bus_dma(ISABus *bus, IsaDma *dma8, IsaDma *dma16);
+IsaDma *isa_get_dma(ISABus *bus, int nchan);
MemoryRegion *isa_address_space(ISADevice *dev);
MemoryRegion *isa_address_space_io(ISADevice *dev);
ISADevice *isa_create(ISABus *bus, const char *name);
@@ -106,15 +147,6 @@ static inline ISABus *isa_bus_from_device(ISADevice *d)
return ISA_BUS(qdev_get_parent_bus(DEVICE(d)));
}
-/* dma.c */
-int DMA_get_channel_mode (int nchan);
-int DMA_read_memory (int nchan, void *buf, int pos, int size);
-int DMA_write_memory (int nchan, void *buf, int pos, int size);
-void DMA_hold_DREQ (int nchan);
-void DMA_release_DREQ (int nchan);
-void DMA_schedule(int nchan);
-void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit);
-void DMA_register_channel (int nchan,
- DMA_transfer_handler transfer_handler,
- void *opaque);
+/* i8257.c */
+void DMA_init(ISABus *bus, int high_page_enable);
#endif
diff --git a/qemu/include/hw/loader.h b/qemu/include/hw/loader.h
index f7b43ab62..4879b63a2 100644
--- a/qemu/include/hw/loader.h
+++ b/qemu/include/hw/loader.h
@@ -16,6 +16,18 @@ int load_image(const char *filename, uint8_t *addr); /* deprecated */
ssize_t load_image_size(const char *filename, void *addr, size_t size);
int load_image_targphys(const char *filename, hwaddr,
uint64_t max_sz);
+/**
+ * load_image_mr: load an image into a memory region
+ * @filename: Path to the image file
+ * @mr: Memory Region to load into
+ *
+ * Load the specified file into the memory region.
+ * The file loaded is registered as a ROM, so its contents will be
+ * reinstated whenever the system is reset.
+ * If the file is larger than the memory region's size the call will fail.
+ * Returns -1 on failure, or the size of the file.
+ */
+int load_image_mr(const char *filename, MemoryRegion *mr);
/* This is the limit on the maximum uncompressed image size that
* load_image_gzipped_buffer() and load_image_gzipped() will read. It prevents
@@ -32,10 +44,49 @@ int load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz);
#define ELF_LOAD_WRONG_ARCH -3
#define ELF_LOAD_WRONG_ENDIAN -4
const char *load_elf_strerror(int error);
+
+/** load_elf:
+ * @filename: Path of ELF file
+ * @translate_fn: optional function to translate load addresses
+ * @translate_opaque: opaque data passed to @translate_fn
+ * @pentry: Populated with program entry point. Ignored if NULL.
+ * @lowaddr: Populated with lowest loaded address. Ignored if NULL.
+ * @highaddr: Populated with highest loaded address. Ignored if NULL.
+ * @bigendian: Expected ELF endianness. 0 for LE otherwise BE
+ * @elf_machine: Expected ELF machine type
+ * @clear_lsb: Set to mask off LSB of addresses (Some architectures use
+ * this for non-address data)
+ * @data_swab: Set to order of byte swapping for data. 0 for no swap, 1
+ * for swapping bytes within halfwords, 2 for bytes within
+ * words and 3 for within doublewords.
+ *
+ * Load an ELF file's contents to the emulated system's address space.
+ * Clients may optionally specify a callback to perform address
+ * translations. @pentry, @lowaddr and @highaddr are optional pointers
+ * which will be populated with various load information. @bigendian and
+ * @elf_machine give the expected endianness and machine for the ELF the
+ * load will fail if the target ELF does not match. Some architectures
+ * have some architecture-specific behaviours that come into effect when
+ * their particular values for @elf_machine are set.
+ */
+
int load_elf(const char *filename, uint64_t (*translate_fn)(void *, uint64_t),
void *translate_opaque, uint64_t *pentry, uint64_t *lowaddr,
uint64_t *highaddr, int big_endian, int elf_machine,
- int clear_lsb);
+ int clear_lsb, int data_swab);
+
+/** load_elf_hdr:
+ * @filename: Path of ELF file
+ * @hdr: Buffer to populate with header data. Header data will not be
+ * filled if set to NULL.
+ * @is64: Set to true if the ELF is 64bit. Ignored if set to NULL
+ * @errp: Populated with an error in failure cases
+ *
+ * Inspect an ELF file's header. Read its full header contents into a
+ * buffer and/or determine if the ELF is 64bit.
+ */
+void load_elf_hdr(const char *filename, void *hdr, bool *is64, Error **errp);
+
int load_aout(const char *filename, hwaddr addr, int max_sz,
int bswap_needed, hwaddr target_page_size);
int load_uimage(const char *filename, hwaddr *ep,
@@ -67,7 +118,7 @@ extern bool rom_file_has_mr;
int rom_add_file(const char *file, const char *fw_dir,
hwaddr addr, int32_t bootindex,
- bool option_rom);
+ bool option_rom, MemoryRegion *mr);
MemoryRegion *rom_add_blob(const char *name, const void *blob, size_t len,
size_t max_len, hwaddr addr,
const char *fw_file_name,
@@ -77,14 +128,18 @@ int rom_add_elf_program(const char *name, void *data, size_t datasize,
size_t romsize, hwaddr addr);
int rom_check_and_register_reset(void);
void rom_set_fw(FWCfgState *f);
+void rom_set_order_override(int order);
+void rom_reset_order_override(void);
int rom_copy(uint8_t *dest, hwaddr addr, size_t size);
void *rom_ptr(hwaddr addr);
void hmp_info_roms(Monitor *mon, const QDict *qdict);
#define rom_add_file_fixed(_f, _a, _i) \
- rom_add_file(_f, NULL, _a, _i, false)
+ rom_add_file(_f, NULL, _a, _i, false, NULL)
#define rom_add_blob_fixed(_f, _b, _l, _a) \
rom_add_blob(_f, _b, _l, _l, _a, NULL, NULL, NULL)
+#define rom_add_file_mr(_f, _mr, _i) \
+ rom_add_file(_f, NULL, 0, _i, false, _mr)
#define PC_ROM_MIN_VGA 0xc0000
#define PC_ROM_MIN_OPTION 0xc8000
diff --git a/qemu/include/hw/mem/nvdimm.h b/qemu/include/hw/mem/nvdimm.h
new file mode 100644
index 000000000..517de9c36
--- /dev/null
+++ b/qemu/include/hw/mem/nvdimm.h
@@ -0,0 +1,62 @@
+/*
+ * Non-Volatile Dual In-line Memory Module Virtualization Implementation
+ *
+ * Copyright(C) 2015 Intel Corporation.
+ *
+ * Author:
+ * Xiao Guangrong <guangrong.xiao@linux.intel.com>
+ *
+ * NVDIMM specifications and some documents can be found at:
+ * NVDIMM ACPI device and NFIT are introduced in ACPI 6:
+ * http://www.uefi.org/sites/default/files/resources/ACPI_6.0.pdf
+ * NVDIMM Namespace specification:
+ * http://pmem.io/documents/NVDIMM_Namespace_Spec.pdf
+ * DSM Interface Example:
+ * http://pmem.io/documents/NVDIMM_DSM_Interface_Example.pdf
+ * Driver Writer's Guide:
+ * http://pmem.io/documents/NVDIMM_Driver_Writers_Guide.pdf
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef QEMU_NVDIMM_H
+#define QEMU_NVDIMM_H
+
+#include "hw/mem/pc-dimm.h"
+
+#define NVDIMM_DEBUG 0
+#define nvdimm_debug(fmt, ...) \
+ do { \
+ if (NVDIMM_DEBUG) { \
+ fprintf(stderr, "nvdimm: " fmt, ## __VA_ARGS__); \
+ } \
+ } while (0)
+
+#define TYPE_NVDIMM "nvdimm"
+
+#define NVDIMM_DSM_MEM_FILE "etc/acpi/nvdimm-mem"
+
+/*
+ * 32 bits IO port starting from 0x0a18 in guest is reserved for
+ * NVDIMM ACPI emulation.
+ */
+#define NVDIMM_ACPI_IO_BASE 0x0a18
+#define NVDIMM_ACPI_IO_LEN 4
+
+struct AcpiNVDIMMState {
+ /* detect if NVDIMM support is enabled. */
+ bool is_enabled;
+
+ /* the data of the fw_cfg file NVDIMM_DSM_MEM_FILE. */
+ GArray *dsm_mem;
+ /* the IO region used by OSPM to transfer control to QEMU. */
+ MemoryRegion io_mr;
+};
+typedef struct AcpiNVDIMMState AcpiNVDIMMState;
+
+void nvdimm_init_acpi_state(AcpiNVDIMMState *state, MemoryRegion *io,
+ FWCfgState *fw_cfg, Object *owner);
+void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data,
+ GArray *linker);
+#endif
diff --git a/qemu/include/hw/mem/pc-dimm.h b/qemu/include/hw/mem/pc-dimm.h
index d83bf30ea..218dfb0ed 100644
--- a/qemu/include/hw/mem/pc-dimm.h
+++ b/qemu/include/hw/mem/pc-dimm.h
@@ -77,7 +77,7 @@ typedef struct PCDIMMDeviceClass {
* @mr: hotplug memory address space container
*/
typedef struct MemoryHotplugState {
- ram_addr_t base;
+ hwaddr base;
MemoryRegion mr;
} MemoryHotplugState;
diff --git a/qemu/include/hw/mips/cps.h b/qemu/include/hw/mips/cps.h
new file mode 100644
index 000000000..4dbae9c8c
--- /dev/null
+++ b/qemu/include/hw/mips/cps.h
@@ -0,0 +1,46 @@
+/*
+ * Coherent Processing System emulation.
+ *
+ * Copyright (c) 2016 Imagination Technologies
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef MIPS_CPS_H
+#define MIPS_CPS_H
+
+#include "hw/sysbus.h"
+#include "hw/misc/mips_cmgcr.h"
+#include "hw/misc/mips_cpc.h"
+#include "hw/misc/mips_itu.h"
+
+#define TYPE_MIPS_CPS "mips-cps"
+#define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS)
+
+typedef struct MIPSCPSState {
+ SysBusDevice parent_obj;
+
+ uint32_t num_vp;
+ uint32_t num_irq;
+ char *cpu_model;
+
+ MemoryRegion container;
+ MIPSGCRState gcr;
+ MIPSCPCState cpc;
+ MIPSITUState itu;
+} MIPSCPSState;
+
+qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number);
+
+#endif
diff --git a/qemu/include/hw/misc/bcm2835_mbox.h b/qemu/include/hw/misc/bcm2835_mbox.h
new file mode 100644
index 000000000..f4e9ff9ef
--- /dev/null
+++ b/qemu/include/hw/misc/bcm2835_mbox.h
@@ -0,0 +1,38 @@
+/*
+ * Raspberry Pi emulation (c) 2012 Gregory Estrade
+ * This code is licensed under the GNU GPLv2 and later.
+ */
+
+#ifndef BCM2835_MBOX_H
+#define BCM2835_MBOX_H
+
+#include "bcm2835_mbox_defs.h"
+#include "hw/sysbus.h"
+#include "exec/address-spaces.h"
+
+#define TYPE_BCM2835_MBOX "bcm2835-mbox"
+#define BCM2835_MBOX(obj) \
+ OBJECT_CHECK(BCM2835MboxState, (obj), TYPE_BCM2835_MBOX)
+
+typedef struct {
+ uint32_t reg[MBOX_SIZE];
+ uint32_t count;
+ uint32_t status;
+ uint32_t config;
+} BCM2835Mbox;
+
+typedef struct {
+ /*< private >*/
+ SysBusDevice busdev;
+ /*< public >*/
+ MemoryRegion *mbox_mr;
+ AddressSpace mbox_as;
+ MemoryRegion iomem;
+ qemu_irq arm_irq;
+
+ bool mbox_irq_disabled;
+ bool available[MBOX_CHAN_COUNT];
+ BCM2835Mbox mbox[2];
+} BCM2835MboxState;
+
+#endif
diff --git a/qemu/include/hw/misc/bcm2835_mbox_defs.h b/qemu/include/hw/misc/bcm2835_mbox_defs.h
new file mode 100644
index 000000000..a18e520b2
--- /dev/null
+++ b/qemu/include/hw/misc/bcm2835_mbox_defs.h
@@ -0,0 +1,27 @@
+/*
+ * Raspberry Pi emulation (c) 2012 Gregory Estrade
+ * This code is licensed under the GNU GPLv2 and later.
+ */
+
+#ifndef BCM2835_MBOX_DEFS_H
+#define BCM2835_MBOX_DEFS_H
+
+/* Constants shared with the ARM identifying separate mailbox channels */
+#define MBOX_CHAN_POWER 0 /* for use by the power management interface */
+#define MBOX_CHAN_FB 1 /* for use by the frame buffer */
+#define MBOX_CHAN_VCHIQ 3 /* for use by the VCHIQ interface */
+#define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */
+#define MBOX_CHAN_COUNT 9
+
+#define MBOX_SIZE 32
+#define MBOX_INVALID_DATA 0x0f
+
+/* Layout of the private address space used for communication between
+ * the mbox device emulation, and child devices: each channel occupies
+ * 16 bytes of address space, but only two registers are presently defined.
+ */
+#define MBOX_AS_CHAN_SHIFT 4
+#define MBOX_AS_DATA 0 /* request / response data (RW at offset 0) */
+#define MBOX_AS_PENDING 4 /* pending response status (RO at offset 4) */
+
+#endif /* BCM2835_MBOX_DEFS_H */
diff --git a/qemu/include/hw/misc/bcm2835_property.h b/qemu/include/hw/misc/bcm2835_property.h
new file mode 100644
index 000000000..edcab603c
--- /dev/null
+++ b/qemu/include/hw/misc/bcm2835_property.h
@@ -0,0 +1,35 @@
+/*
+ * Raspberry Pi emulation (c) 2012 Gregory Estrade
+ * This code is licensed under the GNU GPLv2 and later.
+ */
+
+#ifndef BCM2835_PROPERTY_H
+#define BCM2835_PROPERTY_H
+
+#include "hw/sysbus.h"
+#include "exec/address-spaces.h"
+#include "net/net.h"
+#include "hw/display/bcm2835_fb.h"
+
+#define TYPE_BCM2835_PROPERTY "bcm2835-property"
+#define BCM2835_PROPERTY(obj) \
+ OBJECT_CHECK(BCM2835PropertyState, (obj), TYPE_BCM2835_PROPERTY)
+
+typedef struct {
+ /*< private >*/
+ SysBusDevice busdev;
+ /*< public >*/
+
+ MemoryRegion *dma_mr;
+ AddressSpace dma_as;
+ MemoryRegion iomem;
+ qemu_irq mbox_irq;
+ BCM2835FBState *fbdev;
+
+ MACAddr macaddr;
+ uint32_t board_rev;
+ uint32_t addr;
+ bool pending;
+} BCM2835PropertyState;
+
+#endif
diff --git a/qemu/include/hw/misc/imx25_ccm.h b/qemu/include/hw/misc/imx25_ccm.h
new file mode 100644
index 000000000..296321c61
--- /dev/null
+++ b/qemu/include/hw/misc/imx25_ccm.h
@@ -0,0 +1,79 @@
+/*
+ * IMX25 Clock Control Module
+ *
+ * Copyright (C) 2012 NICTA
+ * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef IMX25_CCM_H
+#define IMX25_CCM_H
+
+#include "hw/misc/imx_ccm.h"
+
+#define IMX25_CCM_MPCTL_REG 0
+#define IMX25_CCM_UPCTL_REG 1
+#define IMX25_CCM_CCTL_REG 2
+#define IMX25_CCM_CGCR0_REG 3
+#define IMX25_CCM_CGCR1_REG 4
+#define IMX25_CCM_CGCR2_REG 5
+#define IMX25_CCM_PCDR0_REG 6
+#define IMX25_CCM_PCDR1_REG 7
+#define IMX25_CCM_PCDR2_REG 8
+#define IMX25_CCM_PCDR3_REG 9
+#define IMX25_CCM_RCSR_REG 10
+#define IMX25_CCM_CRDR_REG 11
+#define IMX25_CCM_DCVR0_REG 12
+#define IMX25_CCM_DCVR1_REG 13
+#define IMX25_CCM_DCVR2_REG 14
+#define IMX25_CCM_DCVR3_REG 15
+#define IMX25_CCM_LTR0_REG 16
+#define IMX25_CCM_LTR1_REG 17
+#define IMX25_CCM_LTR2_REG 18
+#define IMX25_CCM_LTR3_REG 19
+#define IMX25_CCM_LTBR0_REG 20
+#define IMX25_CCM_LTBR1_REG 21
+#define IMX25_CCM_PMCR0_REG 22
+#define IMX25_CCM_PMCR1_REG 23
+#define IMX25_CCM_PMCR2_REG 24
+#define IMX25_CCM_MCR_REG 25
+#define IMX25_CCM_LPIMR0_REG 26
+#define IMX25_CCM_LPIMR1_REG 27
+#define IMX25_CCM_MAX_REG 28
+
+/* CCTL */
+#define CCTL_ARM_CLK_DIV_SHIFT (30)
+#define CCTL_ARM_CLK_DIV_MASK (0x3)
+#define CCTL_AHB_CLK_DIV_SHIFT (28)
+#define CCTL_AHB_CLK_DIV_MASK (0x3)
+#define CCTL_MPLL_BYPASS_SHIFT (22)
+#define CCTL_MPLL_BYPASS_MASK (0x1)
+#define CCTL_USB_DIV_SHIFT (16)
+#define CCTL_USB_DIV_MASK (0x3F)
+#define CCTL_ARM_SRC_SHIFT (13)
+#define CCTL_ARM_SRC_MASK (0x1)
+#define CCTL_UPLL_DIS_SHIFT (23)
+#define CCTL_UPLL_DIS_MASK (0x1)
+
+#define EXTRACT(value, name) (((value) >> CCTL_##name##_SHIFT) \
+ & CCTL_##name##_MASK)
+#define INSERT(value, name) (((value) & CCTL_##name##_MASK) << \
+ CCTL_##name##_SHIFT)
+
+#define TYPE_IMX25_CCM "imx25.ccm"
+#define IMX25_CCM(obj) OBJECT_CHECK(IMX25CCMState, (obj), TYPE_IMX25_CCM)
+
+typedef struct IMX25CCMState {
+ /* <private> */
+ IMXCCMState parent_obj;
+
+ /* <public> */
+ MemoryRegion iomem;
+
+ uint32_t reg[IMX25_CCM_MAX_REG];
+
+} IMX25CCMState;
+
+#endif /* IMX25_CCM_H */
diff --git a/qemu/include/hw/misc/imx31_ccm.h b/qemu/include/hw/misc/imx31_ccm.h
new file mode 100644
index 000000000..c376fad14
--- /dev/null
+++ b/qemu/include/hw/misc/imx31_ccm.h
@@ -0,0 +1,88 @@
+/*
+ * IMX31 Clock Control Module
+ *
+ * Copyright (C) 2012 NICTA
+ * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef IMX31_CCM_H
+#define IMX31_CCM_H
+
+#include "hw/misc/imx_ccm.h"
+
+#define IMX31_CCM_CCMR_REG 0
+#define IMX31_CCM_PDR0_REG 1
+#define IMX31_CCM_PDR1_REG 2
+#define IMX31_CCM_RCSR_REG 3
+#define IMX31_CCM_MPCTL_REG 4
+#define IMX31_CCM_UPCTL_REG 5
+#define IMX31_CCM_SPCTL_REG 6
+#define IMX31_CCM_COSR_REG 7
+#define IMX31_CCM_CGR0_REG 8
+#define IMX31_CCM_CGR1_REG 9
+#define IMX31_CCM_CGR2_REG 10
+#define IMX31_CCM_WIMR_REG 11
+#define IMX31_CCM_LDC_REG 12
+#define IMX31_CCM_DCVR0_REG 13
+#define IMX31_CCM_DCVR1_REG 14
+#define IMX31_CCM_DCVR2_REG 15
+#define IMX31_CCM_DCVR3_REG 16
+#define IMX31_CCM_LTR0_REG 17
+#define IMX31_CCM_LTR1_REG 18
+#define IMX31_CCM_LTR2_REG 19
+#define IMX31_CCM_LTR3_REG 20
+#define IMX31_CCM_LTBR0_REG 21
+#define IMX31_CCM_LTBR1_REG 22
+#define IMX31_CCM_PMCR0_REG 23
+#define IMX31_CCM_PMCR1_REG 24
+#define IMX31_CCM_PDR2_REG 25
+#define IMX31_CCM_MAX_REG 26
+
+/* CCMR */
+#define CCMR_FPME (1<<0)
+#define CCMR_MPE (1<<3)
+#define CCMR_MDS (1<<7)
+#define CCMR_FPMF (1<<26)
+#define CCMR_PRCS (3<<1)
+
+#define PMCR0_DFSUP1 (1<<31)
+
+/* PDR0 */
+#define PDR0_MCU_PODF_SHIFT (0)
+#define PDR0_MCU_PODF_MASK (0x7)
+#define PDR0_MAX_PODF_SHIFT (3)
+#define PDR0_MAX_PODF_MASK (0x7)
+#define PDR0_IPG_PODF_SHIFT (6)
+#define PDR0_IPG_PODF_MASK (0x3)
+#define PDR0_NFC_PODF_SHIFT (8)
+#define PDR0_NFC_PODF_MASK (0x7)
+#define PDR0_HSP_PODF_SHIFT (11)
+#define PDR0_HSP_PODF_MASK (0x7)
+#define PDR0_PER_PODF_SHIFT (16)
+#define PDR0_PER_PODF_MASK (0x1f)
+#define PDR0_CSI_PODF_SHIFT (23)
+#define PDR0_CSI_PODF_MASK (0x1ff)
+
+#define EXTRACT(value, name) (((value) >> PDR0_##name##_PODF_SHIFT) \
+ & PDR0_##name##_PODF_MASK)
+#define INSERT(value, name) (((value) & PDR0_##name##_PODF_MASK) << \
+ PDR0_##name##_PODF_SHIFT)
+
+#define TYPE_IMX31_CCM "imx31.ccm"
+#define IMX31_CCM(obj) OBJECT_CHECK(IMX31CCMState, (obj), TYPE_IMX31_CCM)
+
+typedef struct IMX31CCMState {
+ /* <private> */
+ IMXCCMState parent_obj;
+
+ /* <public> */
+ MemoryRegion iomem;
+
+ uint32_t reg[IMX31_CCM_MAX_REG];
+
+} IMX31CCMState;
+
+#endif /* IMX31_CCM_H */
diff --git a/qemu/include/hw/misc/imx6_ccm.h b/qemu/include/hw/misc/imx6_ccm.h
new file mode 100644
index 000000000..80505809b
--- /dev/null
+++ b/qemu/include/hw/misc/imx6_ccm.h
@@ -0,0 +1,197 @@
+/*
+ * IMX6 Clock Control Module
+ *
+ * Copyright (C) 2012 NICTA
+ * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef IMX6_CCM_H
+#define IMX6_CCM_H
+
+#include "hw/misc/imx_ccm.h"
+#include "qemu/bitops.h"
+
+#define CCM_CCR 0
+#define CCM_CCDR 1
+#define CCM_CSR 2
+#define CCM_CCSR 3
+#define CCM_CACRR 4
+#define CCM_CBCDR 5
+#define CCM_CBCMR 6
+#define CCM_CSCMR1 7
+#define CCM_CSCMR2 8
+#define CCM_CSCDR1 9
+#define CCM_CS1CDR 10
+#define CCM_CS2CDR 11
+#define CCM_CDCDR 12
+#define CCM_CHSCCDR 13
+#define CCM_CSCDR2 14
+#define CCM_CSCDR3 15
+#define CCM_CDHIPR 18
+#define CCM_CTOR 20
+#define CCM_CLPCR 21
+#define CCM_CISR 22
+#define CCM_CIMR 23
+#define CCM_CCOSR 24
+#define CCM_CGPR 25
+#define CCM_CCGR0 26
+#define CCM_CCGR1 27
+#define CCM_CCGR2 28
+#define CCM_CCGR3 29
+#define CCM_CCGR4 30
+#define CCM_CCGR5 31
+#define CCM_CCGR6 32
+#define CCM_CMEOR 34
+#define CCM_MAX 35
+
+#define CCM_ANALOG_PLL_ARM 0
+#define CCM_ANALOG_PLL_ARM_SET 1
+#define CCM_ANALOG_PLL_ARM_CLR 2
+#define CCM_ANALOG_PLL_ARM_TOG 3
+#define CCM_ANALOG_PLL_USB1 4
+#define CCM_ANALOG_PLL_USB1_SET 5
+#define CCM_ANALOG_PLL_USB1_CLR 6
+#define CCM_ANALOG_PLL_USB1_TOG 7
+#define CCM_ANALOG_PLL_USB2 8
+#define CCM_ANALOG_PLL_USB2_SET 9
+#define CCM_ANALOG_PLL_USB2_CLR 10
+#define CCM_ANALOG_PLL_USB2_TOG 11
+#define CCM_ANALOG_PLL_SYS 12
+#define CCM_ANALOG_PLL_SYS_SET 13
+#define CCM_ANALOG_PLL_SYS_CLR 14
+#define CCM_ANALOG_PLL_SYS_TOG 15
+#define CCM_ANALOG_PLL_SYS_SS 16
+#define CCM_ANALOG_PLL_SYS_NUM 20
+#define CCM_ANALOG_PLL_SYS_DENOM 24
+#define CCM_ANALOG_PLL_AUDIO 28
+#define CCM_ANALOG_PLL_AUDIO_SET 29
+#define CCM_ANALOG_PLL_AUDIO_CLR 30
+#define CCM_ANALOG_PLL_AUDIO_TOG 31
+#define CCM_ANALOG_PLL_AUDIO_NUM 32
+#define CCM_ANALOG_PLL_AUDIO_DENOM 36
+#define CCM_ANALOG_PLL_VIDEO 40
+#define CCM_ANALOG_PLL_VIDEO_SET 41
+#define CCM_ANALOG_PLL_VIDEO_CLR 42
+#define CCM_ANALOG_PLL_VIDEO_TOG 44
+#define CCM_ANALOG_PLL_VIDEO_NUM 46
+#define CCM_ANALOG_PLL_VIDEO_DENOM 48
+#define CCM_ANALOG_PLL_MLB 52
+#define CCM_ANALOG_PLL_MLB_SET 53
+#define CCM_ANALOG_PLL_MLB_CLR 54
+#define CCM_ANALOG_PLL_MLB_TOG 55
+#define CCM_ANALOG_PLL_ENET 56
+#define CCM_ANALOG_PLL_ENET_SET 57
+#define CCM_ANALOG_PLL_ENET_CLR 58
+#define CCM_ANALOG_PLL_ENET_TOG 59
+#define CCM_ANALOG_PFD_480 60
+#define CCM_ANALOG_PFD_480_SET 61
+#define CCM_ANALOG_PFD_480_CLR 62
+#define CCM_ANALOG_PFD_480_TOG 63
+#define CCM_ANALOG_PFD_528 64
+#define CCM_ANALOG_PFD_528_SET 65
+#define CCM_ANALOG_PFD_528_CLR 66
+#define CCM_ANALOG_PFD_528_TOG 67
+
+/* PMU registers */
+#define PMU_REG_1P1 68
+#define PMU_REG_3P0 72
+#define PMU_REG_2P5 76
+#define PMU_REG_CORE 80
+
+#define CCM_ANALOG_MISC0 84
+#define PMU_MISC0 84
+#define CCM_ANALOG_MISC0_SET 85
+#define CCM_ANALOG_MISC0_CLR 86
+#define CCM_ANALOG_MISC0_TOG 87
+
+#define PMU_MISC1 88
+#define PMU_MISC1_SET 89
+#define PMU_MISC1_CLR 90
+#define PMU_MISC1_TOG 91
+
+#define CCM_ANALOG_MISC2 92
+#define PMU_MISC2 92
+#define CCM_ANALOG_MISC2_SET 93
+#define CCM_ANALOG_MISC2_CLR 94
+#define CCM_ANALOG_MISC2_TOG 95
+
+#define USB_ANALOG_USB1_VBUS_DETECT 104
+#define USB_ANALOG_USB1_VBUS_DETECT_SET 105
+#define USB_ANALOG_USB1_VBUS_DETECT_CLR 106
+#define USB_ANALOG_USB1_VBUS_DETECT_TOG 107
+#define USB_ANALOG_USB1_CHRG_DETECT 108
+#define USB_ANALOG_USB1_CHRG_DETECT_SET 109
+#define USB_ANALOG_USB1_CHRG_DETECT_CLR 110
+#define USB_ANALOG_USB1_CHRG_DETECT_TOG 111
+#define USB_ANALOG_USB1_VBUS_DETECT_STAT 112
+#define USB_ANALOG_USB1_CHRG_DETECT_STAT 116
+#define USB_ANALOG_USB1_MISC 124
+#define USB_ANALOG_USB1_MISC_SET 125
+#define USB_ANALOG_USB1_MISC_CLR 126
+#define USB_ANALOG_USB1_MISC_TOG 127
+#define USB_ANALOG_USB2_VBUS_DETECT 128
+#define USB_ANALOG_USB2_VBUS_DETECT_SET 129
+#define USB_ANALOG_USB2_VBUS_DETECT_CLR 130
+#define USB_ANALOG_USB2_VBUS_DETECT_TOG 131
+#define USB_ANALOG_USB2_CHRG_DETECT 132
+#define USB_ANALOG_USB2_CHRG_DETECT_SET 133
+#define USB_ANALOG_USB2_CHRG_DETECT_CLR 134
+#define USB_ANALOG_USB2_CHRG_DETECT_TOG 135
+#define USB_ANALOG_USB2_VBUS_DETECT_STAT 136
+#define USB_ANALOG_USB2_CHRG_DETECT_STAT 140
+#define USB_ANALOG_USB2_MISC 148
+#define USB_ANALOG_USB2_MISC_SET 149
+#define USB_ANALOG_USB2_MISC_CLR 150
+#define USB_ANALOG_USB2_MISC_TOG 151
+#define USB_ANALOG_DIGPROG 152
+#define CCM_ANALOG_MAX 153
+
+/* CCM_CBCMR */
+#define PRE_PERIPH_CLK_SEL_SHIFT (18)
+#define PRE_PERIPH_CLK_SEL_LENGTH (2)
+
+/* CCM_CBCDR */
+#define AHB_PODF_SHIFT (10)
+#define AHB_PODF_LENGTH (3)
+#define IPG_PODF_SHIFT (8)
+#define IPG_PODF_LENGTH (2)
+
+/* CCM_CSCMR1 */
+#define PERCLK_PODF_SHIFT (0)
+#define PERCLK_PODF_LENGTH (6)
+
+/* CCM_ANALOG_PFD_528 */
+#define PFD0_FRAC_SHIFT (0)
+#define PFD0_FRAC_LENGTH (6)
+#define PFD2_FRAC_SHIFT (16)
+#define PFD2_FRAC_LENGTH (6)
+
+/* CCM_ANALOG_PLL_SYS */
+#define DIV_SELECT_SHIFT (0)
+#define DIV_SELECT_LENGTH (1)
+
+#define CCM_ANALOG_PLL_LOCK (1 << 31);
+
+#define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH)
+
+#define TYPE_IMX6_CCM "imx6.ccm"
+#define IMX6_CCM(obj) OBJECT_CHECK(IMX6CCMState, (obj), TYPE_IMX6_CCM)
+
+typedef struct IMX6CCMState {
+ /* <private> */
+ IMXCCMState parent_obj;
+
+ /* <public> */
+ MemoryRegion container;
+ MemoryRegion ioccm;
+ MemoryRegion ioanalog;
+
+ uint32_t ccm[CCM_MAX];
+ uint32_t analog[CCM_ANALOG_MAX];
+
+} IMX6CCMState;
+
+#endif /* IMX6_CCM_H */
diff --git a/qemu/include/hw/misc/imx_ccm.h b/qemu/include/hw/misc/imx_ccm.h
new file mode 100644
index 000000000..48a7afad5
--- /dev/null
+++ b/qemu/include/hw/misc/imx_ccm.h
@@ -0,0 +1,64 @@
+/*
+ * IMX Clock Control Module base class
+ *
+ * Copyright (C) 2012 NICTA
+ * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef IMX_CCM_H
+#define IMX_CCM_H
+
+#include "hw/sysbus.h"
+
+#define CKIL_FREQ 32768 /* nominal 32khz clock */
+
+/* PLL control registers */
+#define PD(v) (((v) >> 26) & 0xf)
+#define MFD(v) (((v) >> 16) & 0x3ff)
+#define MFI(v) (((v) >> 10) & 0xf);
+#define MFN(v) ((v) & 0x3ff)
+
+#define PLL_PD(x) (((x) & 0xf) << 26)
+#define PLL_MFD(x) (((x) & 0x3ff) << 16)
+#define PLL_MFI(x) (((x) & 0xf) << 10)
+#define PLL_MFN(x) (((x) & 0x3ff) << 0)
+
+#define TYPE_IMX_CCM "imx.ccm"
+#define IMX_CCM(obj) \
+ OBJECT_CHECK(IMXCCMState, (obj), TYPE_IMX_CCM)
+#define IMX_CCM_CLASS(klass) \
+ OBJECT_CLASS_CHECK(IMXCCMClass, (klass), TYPE_IMX_CCM)
+#define IMX_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(IMXCCMClass, (obj), TYPE_IMX_CCM)
+
+typedef struct IMXCCMState {
+ /* <private> */
+ SysBusDevice parent_obj;
+
+ /* <public> */
+
+} IMXCCMState;
+
+typedef enum {
+ CLK_NONE,
+ CLK_IPG,
+ CLK_IPG_HIGH,
+ CLK_32k
+} IMXClk;
+
+typedef struct IMXCCMClass {
+ /* <private> */
+ SysBusDeviceClass parent_class;
+
+ /* <public> */
+ uint32_t (*get_clock_frequency)(IMXCCMState *s, IMXClk clk);
+} IMXCCMClass;
+
+uint32_t imx_ccm_calc_pll(uint32_t pllreg, uint32_t base_freq);
+
+uint32_t imx_ccm_get_clock_frequency(IMXCCMState *s, IMXClk clock);
+
+#endif /* IMX_CCM_H */
diff --git a/qemu/include/hw/misc/ivshmem.h b/qemu/include/hw/misc/ivshmem.h
new file mode 100644
index 000000000..433ef53d7
--- /dev/null
+++ b/qemu/include/hw/misc/ivshmem.h
@@ -0,0 +1,25 @@
+
+/*
+ * Inter-VM Shared Memory PCI device.
+ *
+ * Author:
+ * Cam Macdonell <cam@cs.ualberta.ca>
+ *
+ * Based On: cirrus_vga.c
+ * Copyright (c) 2004 Fabrice Bellard
+ * Copyright (c) 2004 Makoto Suzuki (suzu)
+ *
+ * and rtl8139.c
+ * Copyright (c) 2006 Igor Kovalenko
+ *
+ * This code is licensed under the GNU GPL v2.
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
+ */
+#ifndef IVSHMEM_H
+#define IVSHMEM_H
+
+#define IVSHMEM_PROTOCOL_VERSION 0
+
+#endif /* IVSHMEM_H */
diff --git a/qemu/include/hw/misc/mips_cmgcr.h b/qemu/include/hw/misc/mips_cmgcr.h
new file mode 100644
index 000000000..cc60eefa5
--- /dev/null
+++ b/qemu/include/hw/misc/mips_cmgcr.h
@@ -0,0 +1,59 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2015 Imagination Technologies
+ *
+ */
+
+#ifndef _MIPS_GCR_H
+#define _MIPS_GCR_H
+
+#define TYPE_MIPS_GCR "mips-gcr"
+#define MIPS_GCR(obj) OBJECT_CHECK(MIPSGCRState, (obj), TYPE_MIPS_GCR)
+
+#define GCR_BASE_ADDR 0x1fbf8000ULL
+#define GCR_ADDRSPACE_SZ 0x8000
+
+/* Offsets to register blocks */
+#define MIPS_GCB_OFS 0x0000 /* Global Control Block */
+#define MIPS_CLCB_OFS 0x2000 /* Core Local Control Block */
+#define MIPS_COCB_OFS 0x4000 /* Core Other Control Block */
+#define MIPS_GDB_OFS 0x6000 /* Global Debug Block */
+
+/* Global Control Block Register Map */
+#define GCR_CONFIG_OFS 0x0000
+#define GCR_BASE_OFS 0x0008
+#define GCR_REV_OFS 0x0030
+#define GCR_CPC_BASE_OFS 0x0088
+#define GCR_CPC_STATUS_OFS 0x00F0
+#define GCR_L2_CONFIG_OFS 0x0130
+
+/* Core Local and Core Other Block Register Map */
+#define GCR_CL_CONFIG_OFS 0x0010
+#define GCR_CL_OTHER_OFS 0x0018
+
+/* GCR_L2_CONFIG register fields */
+#define GCR_L2_CONFIG_BYPASS_SHF 20
+#define GCR_L2_CONFIG_BYPASS_MSK ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF)
+
+/* GCR_CPC_BASE register fields */
+#define GCR_CPC_BASE_CPCEN_MSK 1
+#define GCR_CPC_BASE_CPCBASE_MSK 0xFFFFFFFF8000ULL
+#define GCR_CPC_BASE_MSK (GCR_CPC_BASE_CPCEN_MSK | GCR_CPC_BASE_CPCBASE_MSK)
+
+typedef struct MIPSGCRState MIPSGCRState;
+struct MIPSGCRState {
+ SysBusDevice parent_obj;
+
+ int32_t gcr_rev;
+ int32_t num_vps;
+ hwaddr gcr_base;
+ MemoryRegion iomem;
+ MemoryRegion *cpc_mr;
+
+ uint64_t cpc_base;
+};
+
+#endif /* _MIPS_GCR_H */
diff --git a/qemu/include/hw/misc/mips_cpc.h b/qemu/include/hw/misc/mips_cpc.h
new file mode 100644
index 000000000..72c834e03
--- /dev/null
+++ b/qemu/include/hw/misc/mips_cpc.h
@@ -0,0 +1,47 @@
+/*
+ * Cluster Power Controller emulation
+ *
+ * Copyright (c) 2016 Imagination Technologies
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef MIPS_CPC_H
+#define MIPS_CPC_H
+
+#define CPC_ADDRSPACE_SZ 0x6000
+
+/* CPC blocks offsets relative to base address */
+#define CPC_CL_BASE_OFS 0x2000
+#define CPC_CO_BASE_OFS 0x4000
+
+/* CPC register offsets relative to block offsets */
+#define CPC_VP_STOP_OFS 0x20
+#define CPC_VP_RUN_OFS 0x28
+#define CPC_VP_RUNNING_OFS 0x30
+
+#define TYPE_MIPS_CPC "mips-cpc"
+#define MIPS_CPC(obj) OBJECT_CHECK(MIPSCPCState, (obj), TYPE_MIPS_CPC)
+
+typedef struct MIPSCPCState {
+ SysBusDevice parent_obj;
+
+ uint32_t num_vp;
+ uint64_t vp_start_running; /* VPs running from restart */
+
+ MemoryRegion mr;
+ uint64_t vp_running; /* Indicates which VPs are in the run state */
+} MIPSCPCState;
+
+#endif /* MIPS_CPC_H */
diff --git a/qemu/include/hw/misc/mips_itu.h b/qemu/include/hw/misc/mips_itu.h
new file mode 100644
index 000000000..b3a453203
--- /dev/null
+++ b/qemu/include/hw/misc/mips_itu.h
@@ -0,0 +1,72 @@
+/*
+ * Inter-Thread Communication Unit emulation.
+ *
+ * Copyright (c) 2016 Imagination Technologies
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef MIPS_ITU_H
+#define MIPS_ITU_H
+
+#define TYPE_MIPS_ITU "mips-itu"
+#define MIPS_ITU(obj) OBJECT_CHECK(MIPSITUState, (obj), TYPE_MIPS_ITU)
+
+#define ITC_CELL_DEPTH_SHIFT 2
+#define ITC_CELL_DEPTH (1u << ITC_CELL_DEPTH_SHIFT)
+
+typedef struct ITCStorageCell {
+ struct {
+ uint8_t FIFODepth; /* Log2 of the cell depth */
+ uint8_t FIFOPtr; /* Number of elements in a FIFO cell */
+ uint8_t FIFO; /* 1 - FIFO cell, 0 - Semaphore cell */
+ uint8_t T; /* Trap Bit */
+ uint8_t F; /* Full Bit */
+ uint8_t E; /* Empty Bit */
+ } tag;
+
+ /* Index of the oldest element in the queue */
+ uint8_t fifo_out;
+
+ /* Circular buffer for FIFO. Semaphore cells use index 0 only */
+ uint64_t data[ITC_CELL_DEPTH];
+
+ /* Bitmap tracking blocked threads on the cell.
+ TODO: support >64 threads ? */
+ uint64_t blocked_threads;
+} ITCStorageCell;
+
+#define ITC_ADDRESSMAP_NUM 2
+
+typedef struct MIPSITUState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ int32_t num_fifo;
+ int32_t num_semaphores;
+
+ /* ITC Storage */
+ ITCStorageCell *cell;
+ MemoryRegion storage_io;
+
+ /* ITC Configuration Tags */
+ uint64_t ITCAddressMap[ITC_ADDRESSMAP_NUM];
+ MemoryRegion tag_io;
+} MIPSITUState;
+
+/* Get ITC Configuration Tag memory region. */
+MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu);
+
+#endif /* MIPS_ITU_H */
diff --git a/qemu/include/hw/misc/zynq-xadc.h b/qemu/include/hw/misc/zynq-xadc.h
new file mode 100644
index 000000000..f1a410a37
--- /dev/null
+++ b/qemu/include/hw/misc/zynq-xadc.h
@@ -0,0 +1,46 @@
+/*
+ * Device model for Zynq ADC controller
+ *
+ * Copyright (c) 2015 Guenter Roeck <linux@roeck-us.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef ZYNQ_XADC_H
+#define ZYNQ_XADC_H
+
+#include "hw/sysbus.h"
+
+#define ZYNQ_XADC_MMIO_SIZE 0x0020
+#define ZYNQ_XADC_NUM_IO_REGS (ZYNQ_XADC_MMIO_SIZE / 4)
+#define ZYNQ_XADC_NUM_ADC_REGS 128
+#define ZYNQ_XADC_FIFO_DEPTH 15
+
+#define TYPE_ZYNQ_XADC "xlnx,zynq-xadc"
+#define ZYNQ_XADC(obj) \
+ OBJECT_CHECK(ZynqXADCState, (obj), TYPE_ZYNQ_XADC)
+
+typedef struct ZynqXADCState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion iomem;
+
+ uint32_t regs[ZYNQ_XADC_NUM_IO_REGS];
+ uint16_t xadc_regs[ZYNQ_XADC_NUM_ADC_REGS];
+ uint16_t xadc_read_reg_previous;
+ uint16_t xadc_dfifo[ZYNQ_XADC_FIFO_DEPTH];
+ uint16_t xadc_dfifo_entries;
+
+ struct IRQState *qemu_irq;
+
+} ZynqXADCState;
+
+#endif /* ZYNQ_XADC_H */
diff --git a/qemu/include/hw/net/imx_fec.h b/qemu/include/hw/net/imx_fec.h
new file mode 100644
index 000000000..cbf86509e
--- /dev/null
+++ b/qemu/include/hw/net/imx_fec.h
@@ -0,0 +1,113 @@
+/*
+ * i.MX Fast Ethernet Controller emulation.
+ *
+ * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
+ *
+ * Based on Coldfire Fast Ethernet Controller emulation.
+ *
+ * Copyright (c) 2007 CodeSourcery.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef IMX_FEC_H
+#define IMX_FEC_H
+
+#define TYPE_IMX_FEC "imx.fec"
+#define IMX_FEC(obj) OBJECT_CHECK(IMXFECState, (obj), TYPE_IMX_FEC)
+
+#include "hw/sysbus.h"
+#include "net/net.h"
+
+#define FEC_MAX_FRAME_SIZE 2032
+
+#define FEC_INT_HB (1 << 31)
+#define FEC_INT_BABR (1 << 30)
+#define FEC_INT_BABT (1 << 29)
+#define FEC_INT_GRA (1 << 28)
+#define FEC_INT_TXF (1 << 27)
+#define FEC_INT_TXB (1 << 26)
+#define FEC_INT_RXF (1 << 25)
+#define FEC_INT_RXB (1 << 24)
+#define FEC_INT_MII (1 << 23)
+#define FEC_INT_EBERR (1 << 22)
+#define FEC_INT_LC (1 << 21)
+#define FEC_INT_RL (1 << 20)
+#define FEC_INT_UN (1 << 19)
+
+#define FEC_EN 2
+#define FEC_RESET 1
+
+/* Buffer Descriptor. */
+typedef struct {
+ uint16_t length;
+ uint16_t flags;
+ uint32_t data;
+} IMXFECBufDesc;
+
+#define FEC_BD_R (1 << 15)
+#define FEC_BD_E (1 << 15)
+#define FEC_BD_O1 (1 << 14)
+#define FEC_BD_W (1 << 13)
+#define FEC_BD_O2 (1 << 12)
+#define FEC_BD_L (1 << 11)
+#define FEC_BD_TC (1 << 10)
+#define FEC_BD_ABC (1 << 9)
+#define FEC_BD_M (1 << 8)
+#define FEC_BD_BC (1 << 7)
+#define FEC_BD_MC (1 << 6)
+#define FEC_BD_LG (1 << 5)
+#define FEC_BD_NO (1 << 4)
+#define FEC_BD_CR (1 << 2)
+#define FEC_BD_OV (1 << 1)
+#define FEC_BD_TR (1 << 0)
+
+typedef struct IMXFECState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ NICState *nic;
+ NICConf conf;
+ qemu_irq irq;
+ MemoryRegion iomem;
+
+ uint32_t irq_state;
+ uint32_t eir;
+ uint32_t eimr;
+ uint32_t rx_enabled;
+ uint32_t rx_descriptor;
+ uint32_t tx_descriptor;
+ uint32_t ecr;
+ uint32_t mmfr;
+ uint32_t mscr;
+ uint32_t mibc;
+ uint32_t rcr;
+ uint32_t tcr;
+ uint32_t tfwr;
+ uint32_t frsr;
+ uint32_t erdsr;
+ uint32_t etdsr;
+ uint32_t emrbr;
+ uint32_t miigsk_cfgr;
+ uint32_t miigsk_enr;
+
+ uint32_t phy_status;
+ uint32_t phy_control;
+ uint32_t phy_advertise;
+ uint32_t phy_int;
+ uint32_t phy_int_mask;
+} IMXFECState;
+
+#endif
diff --git a/qemu/include/hw/nvram/fw_cfg.h b/qemu/include/hw/nvram/fw_cfg.h
index e60d3ca21..d00811258 100644
--- a/qemu/include/hw/nvram/fw_cfg.h
+++ b/qemu/include/hw/nvram/fw_cfg.h
@@ -1,54 +1,9 @@
#ifndef FW_CFG_H
#define FW_CFG_H
-#ifndef NO_QEMU_PROTOS
-#include <stdint.h>
-#include <stddef.h>
-
#include "exec/hwaddr.h"
-#include "qemu/typedefs.h"
-#endif
+#include "hw/nvram/fw_cfg_keys.h"
-#define FW_CFG_SIGNATURE 0x00
-#define FW_CFG_ID 0x01
-#define FW_CFG_UUID 0x02
-#define FW_CFG_RAM_SIZE 0x03
-#define FW_CFG_NOGRAPHIC 0x04
-#define FW_CFG_NB_CPUS 0x05
-#define FW_CFG_MACHINE_ID 0x06
-#define FW_CFG_KERNEL_ADDR 0x07
-#define FW_CFG_KERNEL_SIZE 0x08
-#define FW_CFG_KERNEL_CMDLINE 0x09
-#define FW_CFG_INITRD_ADDR 0x0a
-#define FW_CFG_INITRD_SIZE 0x0b
-#define FW_CFG_BOOT_DEVICE 0x0c
-#define FW_CFG_NUMA 0x0d
-#define FW_CFG_BOOT_MENU 0x0e
-#define FW_CFG_MAX_CPUS 0x0f
-#define FW_CFG_KERNEL_ENTRY 0x10
-#define FW_CFG_KERNEL_DATA 0x11
-#define FW_CFG_INITRD_DATA 0x12
-#define FW_CFG_CMDLINE_ADDR 0x13
-#define FW_CFG_CMDLINE_SIZE 0x14
-#define FW_CFG_CMDLINE_DATA 0x15
-#define FW_CFG_SETUP_ADDR 0x16
-#define FW_CFG_SETUP_SIZE 0x17
-#define FW_CFG_SETUP_DATA 0x18
-#define FW_CFG_FILE_DIR 0x19
-
-#define FW_CFG_FILE_FIRST 0x20
-#define FW_CFG_FILE_SLOTS 0x10
-#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST+FW_CFG_FILE_SLOTS)
-
-#define FW_CFG_WRITE_CHANNEL 0x4000
-#define FW_CFG_ARCH_LOCAL 0x8000
-#define FW_CFG_ENTRY_MASK ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL)
-
-#define FW_CFG_INVALID 0xffff
-
-#define FW_CFG_MAX_FILE_PATH 56
-
-#ifndef NO_QEMU_PROTOS
typedef struct FWCfgFile {
uint32_t size; /* file size */
uint16_t select; /* write this to 0x510 to read it */
@@ -56,34 +11,176 @@ typedef struct FWCfgFile {
char name[FW_CFG_MAX_FILE_PATH];
} FWCfgFile;
+#define FW_CFG_ORDER_OVERRIDE_VGA 70
+#define FW_CFG_ORDER_OVERRIDE_NIC 80
+#define FW_CFG_ORDER_OVERRIDE_USER 100
+#define FW_CFG_ORDER_OVERRIDE_DEVICE 110
+
+void fw_cfg_set_order_override(FWCfgState *fw_cfg, int order);
+void fw_cfg_reset_order_override(FWCfgState *fw_cfg);
+
typedef struct FWCfgFiles {
uint32_t count;
FWCfgFile f[];
} FWCfgFiles;
-typedef void (*FWCfgCallback)(void *opaque, uint8_t *data);
-typedef void (*FWCfgReadCallback)(void *opaque, uint32_t offset);
+/* Control as first field allows for different structures selected by this
+ * field, which might be useful in the future
+ */
+typedef struct FWCfgDmaAccess {
+ uint32_t control;
+ uint32_t length;
+ uint64_t address;
+} QEMU_PACKED FWCfgDmaAccess;
+typedef void (*FWCfgReadCallback)(void *opaque);
+
+/**
+ * fw_cfg_add_bytes:
+ * @s: fw_cfg device being modified
+ * @key: selector key value for new fw_cfg item
+ * @data: pointer to start of item data
+ * @len: size of item data
+ *
+ * Add a new fw_cfg item, available by selecting the given key, as a raw
+ * "blob" of the given size. The data referenced by the starting pointer
+ * is only linked, NOT copied, into the data structure of the fw_cfg device.
+ */
void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len);
+
+/**
+ * fw_cfg_add_string:
+ * @s: fw_cfg device being modified
+ * @key: selector key value for new fw_cfg item
+ * @value: NUL-terminated ascii string
+ *
+ * Add a new fw_cfg item, available by selecting the given key. The item
+ * data will consist of a dynamically allocated copy of the provided string,
+ * including its NUL terminator.
+ */
void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value);
+
+/**
+ * fw_cfg_add_i16:
+ * @s: fw_cfg device being modified
+ * @key: selector key value for new fw_cfg item
+ * @value: 16-bit integer
+ *
+ * Add a new fw_cfg item, available by selecting the given key. The item
+ * data will consist of a dynamically allocated copy of the given 16-bit
+ * value, converted to little-endian representation.
+ */
void fw_cfg_add_i16(FWCfgState *s, uint16_t key, uint16_t value);
+
+/**
+ * fw_cfg_modify_i16:
+ * @s: fw_cfg device being modified
+ * @key: selector key value for new fw_cfg item
+ * @value: 16-bit integer
+ *
+ * Replace the fw_cfg item available by selecting the given key. The new
+ * data will consist of a dynamically allocated copy of the given 16-bit
+ * value, converted to little-endian representation. The data being replaced,
+ * assumed to have been dynamically allocated during an earlier call to
+ * either fw_cfg_add_i16() or fw_cfg_modify_i16(), is freed before returning.
+ */
void fw_cfg_modify_i16(FWCfgState *s, uint16_t key, uint16_t value);
+
+/**
+ * fw_cfg_add_i32:
+ * @s: fw_cfg device being modified
+ * @key: selector key value for new fw_cfg item
+ * @value: 32-bit integer
+ *
+ * Add a new fw_cfg item, available by selecting the given key. The item
+ * data will consist of a dynamically allocated copy of the given 32-bit
+ * value, converted to little-endian representation.
+ */
void fw_cfg_add_i32(FWCfgState *s, uint16_t key, uint32_t value);
+
+/**
+ * fw_cfg_add_i64:
+ * @s: fw_cfg device being modified
+ * @key: selector key value for new fw_cfg item
+ * @value: 64-bit integer
+ *
+ * Add a new fw_cfg item, available by selecting the given key. The item
+ * data will consist of a dynamically allocated copy of the given 64-bit
+ * value, converted to little-endian representation.
+ */
void fw_cfg_add_i64(FWCfgState *s, uint16_t key, uint64_t value);
+
+/**
+ * fw_cfg_add_file:
+ * @s: fw_cfg device being modified
+ * @filename: name of new fw_cfg file item
+ * @data: pointer to start of item data
+ * @len: size of item data
+ *
+ * Add a new NAMED fw_cfg item as a raw "blob" of the given size. The data
+ * referenced by the starting pointer is only linked, NOT copied, into the
+ * data structure of the fw_cfg device.
+ * The next available (unused) selector key starting at FW_CFG_FILE_FIRST
+ * will be used; also, a new entry will be added to the file directory
+ * structure residing at key value FW_CFG_FILE_DIR, containing the item name,
+ * data size, and assigned selector key value.
+ */
void fw_cfg_add_file(FWCfgState *s, const char *filename, void *data,
size_t len);
+
+/**
+ * fw_cfg_add_file_callback:
+ * @s: fw_cfg device being modified
+ * @filename: name of new fw_cfg file item
+ * @callback: callback function
+ * @callback_opaque: argument to be passed into callback function
+ * @data: pointer to start of item data
+ * @len: size of item data
+ *
+ * Add a new NAMED fw_cfg item as a raw "blob" of the given size. The data
+ * referenced by the starting pointer is only linked, NOT copied, into the
+ * data structure of the fw_cfg device.
+ * The next available (unused) selector key starting at FW_CFG_FILE_FIRST
+ * will be used; also, a new entry will be added to the file directory
+ * structure residing at key value FW_CFG_FILE_DIR, containing the item name,
+ * data size, and assigned selector key value.
+ * Additionally, set a callback function (and argument) to be called each
+ * time this item is selected (by having its selector key either written to
+ * the fw_cfg control register, or passed to QEMU in FWCfgDmaAccess.control
+ * with FW_CFG_DMA_CTL_SELECT).
+ */
void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
FWCfgReadCallback callback, void *callback_opaque,
void *data, size_t len);
+
+/**
+ * fw_cfg_modify_file:
+ * @s: fw_cfg device being modified
+ * @filename: name of new fw_cfg file item
+ * @data: pointer to start of item data
+ * @len: size of item data
+ *
+ * Replace a NAMED fw_cfg item. If an existing item is found, its callback
+ * information will be cleared, and a pointer to its data will be returned
+ * to the caller, so that it may be freed if necessary. If an existing item
+ * is not found, this call defaults to fw_cfg_add_file(), and NULL is
+ * returned to the caller.
+ * In either case, the new item data is only linked, NOT copied, into the
+ * data structure of the fw_cfg device.
+ *
+ * Returns: pointer to old item's data, or NULL if old item does not exist.
+ */
void *fw_cfg_modify_file(FWCfgState *s, const char *filename, void *data,
size_t len);
+
+FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase,
+ AddressSpace *dma_as);
FWCfgState *fw_cfg_init_io(uint32_t iobase);
FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr);
-FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, hwaddr data_addr,
- uint32_t data_width);
+FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr,
+ hwaddr data_addr, uint32_t data_width,
+ hwaddr dma_addr, AddressSpace *dma_as);
FWCfgState *fw_cfg_find(void);
-#endif /* NO_QEMU_PROTOS */
-
#endif
diff --git a/qemu/include/hw/nvram/fw_cfg_keys.h b/qemu/include/hw/nvram/fw_cfg_keys.h
new file mode 100644
index 000000000..0f3e87188
--- /dev/null
+++ b/qemu/include/hw/nvram/fw_cfg_keys.h
@@ -0,0 +1,46 @@
+#ifndef FW_CFG_KEYS_H
+#define FW_CFG_KEYS_H
+
+#define FW_CFG_SIGNATURE 0x00
+#define FW_CFG_ID 0x01
+#define FW_CFG_UUID 0x02
+#define FW_CFG_RAM_SIZE 0x03
+#define FW_CFG_NOGRAPHIC 0x04
+#define FW_CFG_NB_CPUS 0x05
+#define FW_CFG_MACHINE_ID 0x06
+#define FW_CFG_KERNEL_ADDR 0x07
+#define FW_CFG_KERNEL_SIZE 0x08
+#define FW_CFG_KERNEL_CMDLINE 0x09
+#define FW_CFG_INITRD_ADDR 0x0a
+#define FW_CFG_INITRD_SIZE 0x0b
+#define FW_CFG_BOOT_DEVICE 0x0c
+#define FW_CFG_NUMA 0x0d
+#define FW_CFG_BOOT_MENU 0x0e
+#define FW_CFG_MAX_CPUS 0x0f
+#define FW_CFG_KERNEL_ENTRY 0x10
+#define FW_CFG_KERNEL_DATA 0x11
+#define FW_CFG_INITRD_DATA 0x12
+#define FW_CFG_CMDLINE_ADDR 0x13
+#define FW_CFG_CMDLINE_SIZE 0x14
+#define FW_CFG_CMDLINE_DATA 0x15
+#define FW_CFG_SETUP_ADDR 0x16
+#define FW_CFG_SETUP_SIZE 0x17
+#define FW_CFG_SETUP_DATA 0x18
+#define FW_CFG_FILE_DIR 0x19
+
+#define FW_CFG_FILE_FIRST 0x20
+#define FW_CFG_FILE_SLOTS 0x10
+#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS)
+
+#define FW_CFG_WRITE_CHANNEL 0x4000
+#define FW_CFG_ARCH_LOCAL 0x8000
+#define FW_CFG_ENTRY_MASK (~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL))
+
+#define FW_CFG_INVALID 0xffff
+
+/* width in bytes of fw_cfg control register */
+#define FW_CFG_CTL_SIZE 0x02
+
+#define FW_CFG_MAX_FILE_PATH 56
+
+#endif
diff --git a/qemu/include/hw/pci-host/q35.h b/qemu/include/hw/pci-host/q35.h
index dbe6dc05b..c5c073dde 100644
--- a/qemu/include/hw/pci-host/q35.h
+++ b/qemu/include/hw/pci-host/q35.h
@@ -59,7 +59,6 @@ typedef struct MCHPCIState {
ram_addr_t below_4g_mem_size;
ram_addr_t above_4g_mem_size;
uint64_t pci_hole64_size;
- PcGuestInfo *guest_info;
uint32_t short_root_bus;
IntelIOMMUState *iommu;
} MCHPCIState;
diff --git a/qemu/include/hw/pci-host/spapr.h b/qemu/include/hw/pci-host/spapr.h
index 5322b560e..03ee00640 100644
--- a/qemu/include/hw/pci-host/spapr.h
+++ b/qemu/include/hw/pci-host/spapr.h
@@ -28,32 +28,11 @@
#include "hw/ppc/xics.h"
#define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
-#define TYPE_SPAPR_PCI_VFIO_HOST_BRIDGE "spapr-pci-vfio-host-bridge"
#define SPAPR_PCI_HOST_BRIDGE(obj) \
OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
-#define SPAPR_PCI_VFIO_HOST_BRIDGE(obj) \
- OBJECT_CHECK(sPAPRPHBVFIOState, (obj), TYPE_SPAPR_PCI_VFIO_HOST_BRIDGE)
-
-#define SPAPR_PCI_HOST_BRIDGE_CLASS(klass) \
- OBJECT_CLASS_CHECK(sPAPRPHBClass, (klass), TYPE_SPAPR_PCI_HOST_BRIDGE)
-#define SPAPR_PCI_HOST_BRIDGE_GET_CLASS(obj) \
- OBJECT_GET_CLASS(sPAPRPHBClass, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
-
-typedef struct sPAPRPHBClass sPAPRPHBClass;
typedef struct sPAPRPHBState sPAPRPHBState;
-typedef struct sPAPRPHBVFIOState sPAPRPHBVFIOState;
-
-struct sPAPRPHBClass {
- PCIHostBridgeClass parent_class;
-
- void (*finish_realize)(sPAPRPHBState *sphb, Error **errp);
- int (*eeh_set_option)(sPAPRPHBState *sphb, unsigned int addr, int option);
- int (*eeh_get_state)(sPAPRPHBState *sphb, int *state);
- int (*eeh_reset)(sPAPRPHBState *sphb, int option);
- int (*eeh_configure)(sPAPRPHBState *sphb);
-};
typedef struct spapr_pci_msi {
uint32_t first_irq;
@@ -78,6 +57,7 @@ struct sPAPRPHBState {
MemoryRegion memwindow, iowindow, msiwindow;
uint32_t dma_liobn;
+ hwaddr dma_win_addr, dma_win_size;
AddressSpace iommu_as;
MemoryRegion iommu_root;
@@ -93,12 +73,6 @@ struct sPAPRPHBState {
QLIST_ENTRY(sPAPRPHBState) list;
};
-struct sPAPRPHBVFIOState {
- sPAPRPHBState phb;
-
- int32_t iommugroupid;
-};
-
#define SPAPR_PCI_MAX_INDEX 255
#define SPAPR_PCI_BASE_BUID 0x800000020000000ULL
@@ -115,8 +89,6 @@ struct sPAPRPHBVFIOState {
#define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL
-#define SPAPR_PCI_DMA32_SIZE 0x40000000
-
static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
{
sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
@@ -138,4 +110,41 @@ sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid);
PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid,
uint32_t config_addr);
+/* VFIO EEH hooks */
+#ifdef CONFIG_LINUX
+bool spapr_phb_eeh_available(sPAPRPHBState *sphb);
+int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
+ unsigned int addr, int option);
+int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, int *state);
+int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option);
+int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb);
+void spapr_phb_vfio_reset(DeviceState *qdev);
+#else
+static inline bool spapr_phb_eeh_available(sPAPRPHBState *sphb)
+{
+ return false;
+}
+static inline int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
+ unsigned int addr, int option)
+{
+ return RTAS_OUT_HW_ERROR;
+}
+static inline int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb,
+ int *state)
+{
+ return RTAS_OUT_HW_ERROR;
+}
+static inline int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option)
+{
+ return RTAS_OUT_HW_ERROR;
+}
+static inline int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb)
+{
+ return RTAS_OUT_HW_ERROR;
+}
+static inline void spapr_phb_vfio_reset(DeviceState *qdev)
+{
+}
+#endif
+
#endif /* __HW_SPAPR_PCI_H__ */
diff --git a/qemu/include/hw/pci/msi.h b/qemu/include/hw/pci/msi.h
index 50e452bd0..8124908ab 100644
--- a/qemu/include/hw/pci/msi.h
+++ b/qemu/include/hw/pci/msi.h
@@ -29,7 +29,7 @@ struct MSIMessage {
uint32_t data;
};
-extern bool msi_supported;
+extern bool msi_nonbroken;
void msi_set_message(PCIDevice *dev, MSIMessage msg);
MSIMessage msi_get_message(PCIDevice *dev, unsigned int vector);
diff --git a/qemu/include/hw/pci/msix.h b/qemu/include/hw/pci/msix.h
index 954d82b35..72e5f931c 100644
--- a/qemu/include/hw/pci/msix.h
+++ b/qemu/include/hw/pci/msix.h
@@ -46,12 +46,16 @@ void msix_unset_vector_notifiers(PCIDevice *dev);
extern const VMStateDescription vmstate_msix;
-#define VMSTATE_MSIX(_field, _state) { \
- .name = (stringify(_field)), \
- .size = sizeof(PCIDevice), \
- .vmsd = &vmstate_msix, \
- .flags = VMS_STRUCT, \
- .offset = vmstate_offset_value(_state, _field, PCIDevice), \
+#define VMSTATE_MSIX_TEST(_field, _state, _test) { \
+ .name = (stringify(_field)), \
+ .size = sizeof(PCIDevice), \
+ .vmsd = &vmstate_msix, \
+ .flags = VMS_STRUCT, \
+ .offset = vmstate_offset_value(_state, _field, PCIDevice), \
+ .field_exists = (_test) \
}
+#define VMSTATE_MSIX(_f, _s) \
+ VMSTATE_MSIX_TEST(_f, _s, NULL)
+
#endif
diff --git a/qemu/include/hw/pci/pci-assign.h b/qemu/include/hw/pci/pci-assign.h
new file mode 100644
index 000000000..55f42c56f
--- /dev/null
+++ b/qemu/include/hw/pci/pci-assign.h
@@ -0,0 +1,27 @@
+/*
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ *
+ * Just split from hw/i386/kvm/pci-assign.c.
+ */
+#ifndef PCI_ASSIGN_H
+#define PCI_ASSIGN_H
+
+#include "hw/pci/pci.h"
+
+//#define DEVICE_ASSIGNMENT_DEBUG
+
+#ifdef DEVICE_ASSIGNMENT_DEBUG
+#define DEBUG(fmt, ...) \
+ do { \
+ fprintf(stderr, "%s: " fmt, __func__ , __VA_ARGS__); \
+ } while (0)
+#else
+#define DEBUG(fmt, ...)
+#endif
+
+void *pci_assign_dev_load_option_rom(PCIDevice *dev, struct Object *owner,
+ int *size, unsigned int domain,
+ unsigned int bus, unsigned int slot,
+ unsigned int function);
+#endif /* PCI_ASSIGN_H */
diff --git a/qemu/include/hw/pci/pci.h b/qemu/include/hw/pci/pci.h
index 551cb3d60..ef6ba51f6 100644
--- a/qemu/include/hw/pci/pci.h
+++ b/qemu/include/hw/pci/pci.h
@@ -1,12 +1,9 @@
#ifndef QEMU_PCI_H
#define QEMU_PCI_H
-#include "qemu-common.h"
-
#include "hw/qdev.h"
#include "exec/memory.h"
#include "sysemu/dma.h"
-#include "qapi/error.h"
/* PCI includes legacy ISA access. */
#include "hw/isa/isa.h"
@@ -93,10 +90,20 @@
#define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008
#define PCI_DEVICE_ID_REDHAT_PXB 0x0009
#define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
+#define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b
#define PCI_DEVICE_ID_REDHAT_QXL 0x0100
#define FMT_PCIBUS PRIx64
+typedef uint64_t pcibus_t;
+
+struct PCIHostDeviceAddress {
+ unsigned int domain;
+ unsigned int bus;
+ unsigned int slot;
+ unsigned int function;
+};
+
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
uint32_t address, uint32_t data, int len);
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
@@ -397,6 +404,7 @@ void pci_for_each_bus_depth_first(PCIBus *bus,
void *(*begin)(PCIBus *bus, void *parent_state),
void (*end)(PCIBus *bus, void *state),
void *parent_state);
+PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
/* Use this wrapper when specific scan order is not required. */
static inline
@@ -677,6 +685,11 @@ static inline uint32_t pci_config_size(const PCIDevice *d)
return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
}
+static inline uint16_t pci_requester_id(PCIDevice *dev)
+{
+ return (pci_bus_num(dev->bus) << 8) | dev->devfn;
+}
+
/* DMA access functions */
static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
{
diff --git a/qemu/include/hw/pci/pci_bridge.h b/qemu/include/hw/pci/pci_bridge.h
index 93b621cef..ed4aff6cd 100644
--- a/qemu/include/hw/pci/pci_bridge.h
+++ b/qemu/include/hw/pci/pci_bridge.h
@@ -48,7 +48,7 @@ void pci_bridge_disable_base_limit(PCIDevice *dev);
void pci_bridge_reset_reg(PCIDevice *dev);
void pci_bridge_reset(DeviceState *qdev);
-int pci_bridge_initfn(PCIDevice *pci_dev, const char *typename);
+void pci_bridge_initfn(PCIDevice *pci_dev, const char *typename);
void pci_bridge_exitfn(PCIDevice *pci_dev);
diff --git a/qemu/include/hw/pci/pci_ids.h b/qemu/include/hw/pci/pci_ids.h
index d98e6c915..db85afa03 100644
--- a/qemu/include/hw/pci/pci_ids.h
+++ b/qemu/include/hw/pci/pci_ids.h
@@ -64,6 +64,7 @@
#define PCI_VENDOR_ID_LSI_LOGIC 0x1000
#define PCI_DEVICE_ID_LSI_53C810 0x0001
#define PCI_DEVICE_ID_LSI_53C895A 0x0012
+#define PCI_DEVICE_ID_LSI_SAS1068 0x0054
#define PCI_DEVICE_ID_LSI_SAS1078 0x0060
#define PCI_DEVICE_ID_LSI_SAS0079 0x0079
diff --git a/qemu/include/hw/pci/pcie_aer.h b/qemu/include/hw/pci/pcie_aer.h
index 2fb83882b..c2ee4e2bd 100644
--- a/qemu/include/hw/pci/pcie_aer.h
+++ b/qemu/include/hw/pci/pcie_aer.h
@@ -87,7 +87,7 @@ struct PCIEAERErr {
extern const VMStateDescription vmstate_pcie_aer_log;
-int pcie_aer_init(PCIDevice *dev, uint16_t offset);
+int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size);
void pcie_aer_exit(PCIDevice *dev);
void pcie_aer_write_config(PCIDevice *dev,
uint32_t addr, uint32_t val, int len);
@@ -102,5 +102,6 @@ void pcie_aer_root_write_config(PCIDevice *dev,
/* error injection */
int pcie_aer_inject_error(PCIDevice *dev, const PCIEAERErr *err);
+void pcie_aer_msg(PCIDevice *dev, const PCIEAERMsg *msg);
#endif /* QEMU_PCIE_AER_H */
diff --git a/qemu/include/hw/pci/shpc.h b/qemu/include/hw/pci/shpc.h
index 2c871b947..b2085543d 100644
--- a/qemu/include/hw/pci/shpc.h
+++ b/qemu/include/hw/pci/shpc.h
@@ -4,7 +4,6 @@
#include "qemu-common.h"
#include "exec/memory.h"
#include "migration/vmstate.h"
-#include "qapi/error.h"
#include "hw/hotplug.h"
#include "hw/pci/pci.h"
diff --git a/qemu/include/hw/ppc/mac_dbdma.h b/qemu/include/hw/ppc/mac_dbdma.h
index c6870212e..0cce4e8bb 100644
--- a/qemu/include/hw/ppc/mac_dbdma.h
+++ b/qemu/include/hw/ppc/mac_dbdma.h
@@ -23,6 +23,7 @@
#define HW_MAC_DBDMA_H 1
#include "exec/memory.h"
+#include "qemu/iov.h"
typedef struct DBDMA_io DBDMA_io;
diff --git a/qemu/include/hw/ppc/spapr.h b/qemu/include/hw/ppc/spapr.h
index 91a61abbc..815d5eec4 100644
--- a/qemu/include/hw/ppc/spapr.h
+++ b/qemu/include/hw/ppc/spapr.h
@@ -5,6 +5,7 @@
#include "hw/boards.h"
#include "hw/ppc/xics.h"
#include "hw/ppc/spapr_drc.h"
+#include "hw/mem/pc-dimm.h"
struct VIOsPAPRBus;
struct sPAPRPHBState;
@@ -34,6 +35,8 @@ struct sPAPRMachineClass {
MachineClass parent_class;
/*< public >*/
+ bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */
+ bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */
};
/**
@@ -69,13 +72,13 @@ struct sPAPRMachineState {
int htab_save_index;
bool htab_first_pass;
int htab_fd;
- bool htab_fd_stale;
/* RTAS state */
QTAILQ_HEAD(, sPAPRConfigureConnectorState) ccs_list;
/*< public >*/
char *kvm_type;
+ MemoryHotplugState hotplug_memory;
};
#define H_SUCCESS 0
@@ -201,11 +204,6 @@ struct sPAPRMachineState {
#define H_SET_MODE_ENDIAN_BIG 0
#define H_SET_MODE_ENDIAN_LITTLE 1
-/* Flags for H_SET_MODE_RESOURCE_ADDR_TRANS_MODE */
-#define H_SET_MODE_ADDR_TRANS_NONE 0
-#define H_SET_MODE_ADDR_TRANS_0001_8000 2
-#define H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000 3
-
/* VASI States */
#define H_VASI_INVALID 0
#define H_VASI_ENABLED 1
@@ -331,6 +329,7 @@ struct sPAPRMachineState {
#define H_SET_MPP 0x2D0
#define H_GET_MPP 0x2D4
#define H_XIRR_X 0x2FC
+#define H_RANDOM 0x300
#define H_SET_MODE 0x31C
#define MAX_HCALL_OPCODE H_SET_MODE
@@ -353,15 +352,10 @@ typedef struct sPAPRDeviceTreeUpdateHeader {
uint32_t version_id;
} sPAPRDeviceTreeUpdateHeader;
-/*#define DEBUG_SPAPR_HCALLS*/
-
-#ifdef DEBUG_SPAPR_HCALLS
-#define hcall_dprintf(fmt, ...) \
- do { fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); } while (0)
-#else
#define hcall_dprintf(fmt, ...) \
- do { } while (0)
-#endif
+ do { \
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
+ } while (0)
typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
target_ulong opcode,
@@ -408,13 +402,15 @@ int spapr_allocate_irq_block(int num, bool lsi, bool msi);
#define RTAS_SLOT_PERM_ERR_LOG 2
/* RTAS return codes */
-#define RTAS_OUT_SUCCESS 0
-#define RTAS_OUT_NO_ERRORS_FOUND 1
-#define RTAS_OUT_HW_ERROR -1
-#define RTAS_OUT_BUSY -2
-#define RTAS_OUT_PARAM_ERROR -3
-#define RTAS_OUT_NOT_SUPPORTED -3
-#define RTAS_OUT_NOT_AUTHORIZED -9002
+#define RTAS_OUT_SUCCESS 0
+#define RTAS_OUT_NO_ERRORS_FOUND 1
+#define RTAS_OUT_HW_ERROR -1
+#define RTAS_OUT_BUSY -2
+#define RTAS_OUT_PARAM_ERROR -3
+#define RTAS_OUT_NOT_SUPPORTED -3
+#define RTAS_OUT_NO_SUCH_INDICATOR -3
+#define RTAS_OUT_NOT_AUTHORIZED -9002
+#define RTAS_OUT_SYSPARM_PARAM_ERROR -9999
/* RTAS tokens */
#define RTAS_TOKEN_BASE 0x2000
@@ -494,28 +490,14 @@ static inline uint32_t rtas_ld(target_ulong phys, int n)
return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
}
-static inline void rtas_st(target_ulong phys, int n, uint32_t val)
-{
- stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
-}
-
-static inline void rtas_st_buffer_direct(target_ulong phys,
- target_ulong phys_len,
- uint8_t *buffer, uint16_t buffer_len)
+static inline uint64_t rtas_ldq(target_ulong phys, int n)
{
- cpu_physical_memory_write(ppc64_phys_to_real(phys), buffer,
- MIN(buffer_len, phys_len));
+ return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
}
-static inline void rtas_st_buffer(target_ulong phys, target_ulong phys_len,
- uint8_t *buffer, uint16_t buffer_len)
+static inline void rtas_st(target_ulong phys, int n, uint32_t val)
{
- if (phys_len < 2) {
- return;
- }
- stw_be_phys(&address_space_memory,
- ppc64_phys_to_real(phys), buffer_len);
- rtas_st_buffer_direct(phys + 2, phys_len - 2, buffer, buffer_len);
+ stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
}
typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
@@ -558,7 +540,7 @@ struct sPAPRTCETable {
uint32_t page_shift;
uint64_t *table;
bool bypass;
- bool vfio_accel;
+ bool need_vfio;
int fd;
MemoryRegion iommu;
struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */
@@ -577,20 +559,27 @@ struct sPAPREventLogEntry {
void spapr_events_init(sPAPRMachineState *sm);
void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq);
int spapr_h_cas_compose_response(sPAPRMachineState *sm,
- target_ulong addr, target_ulong size);
+ target_ulong addr, target_ulong size,
+ bool cpu_update, bool memory_update);
sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn,
uint64_t bus_offset,
uint32_t page_shift,
uint32_t nb_table,
- bool vfio_accel);
+ bool need_vfio);
+void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio);
+
MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet);
int spapr_dma_dt(void *fdt, int node_off, const char *propname,
uint32_t liobn, uint64_t window, uint32_t size);
int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
sPAPRTCETable *tcet);
void spapr_pci_switch_vga(bool big_endian);
-void spapr_hotplug_req_add_event(sPAPRDRConnector *drc);
-void spapr_hotplug_req_remove_event(sPAPRDRConnector *drc);
+void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc);
+void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc);
+void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type,
+ uint32_t count);
+void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type,
+ uint32_t count);
/* rtas-configure-connector state */
struct sPAPRConfigureConnectorState {
@@ -603,10 +592,35 @@ struct sPAPRConfigureConnectorState {
void spapr_ccs_reset_hook(void *opaque);
#define TYPE_SPAPR_RTC "spapr-rtc"
+#define TYPE_SPAPR_RNG "spapr-rng"
void spapr_rtc_read(DeviceState *dev, struct tm *tm, uint32_t *ns);
int spapr_rtc_import_offset(DeviceState *dev, int64_t legacy_offset);
+int spapr_rng_populate_dt(void *fdt);
+
#define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */
+/*
+ * This defines the maximum number of DIMM slots we can have for sPAPR
+ * guest. This is not defined by sPAPR but we are defining it to 32 slots
+ * based on default number of slots provided by PowerPC kernel.
+ */
+#define SPAPR_MAX_RAM_SLOTS 32
+
+/* 1GB alignment for hotplug memory region */
+#define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30)
+
+/*
+ * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory
+ * property under ibm,dynamic-reconfiguration-memory node.
+ */
+#define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
+
+/*
+ * This flag value defines the LMB as assigned in ibm,dynamic-memory
+ * property under ibm,dynamic-reconfiguration-memory node.
+ */
+#define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
+
#endif /* !defined (__HW_SPAPR_H__) */
diff --git a/qemu/include/hw/ppc/spapr_drc.h b/qemu/include/hw/ppc/spapr_drc.h
index 60cda35ed..fa21ba044 100644
--- a/qemu/include/hw/ppc/spapr_drc.h
+++ b/qemu/include/hw/ppc/spapr_drc.h
@@ -119,13 +119,14 @@ typedef enum {
} sPAPRDREntitySense;
typedef enum {
- SPAPR_DR_CC_RESPONSE_NEXT_SIB = 1, /* currently unused */
- SPAPR_DR_CC_RESPONSE_NEXT_CHILD = 2,
- SPAPR_DR_CC_RESPONSE_NEXT_PROPERTY = 3,
- SPAPR_DR_CC_RESPONSE_PREV_PARENT = 4,
- SPAPR_DR_CC_RESPONSE_SUCCESS = 0,
- SPAPR_DR_CC_RESPONSE_ERROR = -1,
- SPAPR_DR_CC_RESPONSE_CONTINUE = -2,
+ SPAPR_DR_CC_RESPONSE_NEXT_SIB = 1, /* currently unused */
+ SPAPR_DR_CC_RESPONSE_NEXT_CHILD = 2,
+ SPAPR_DR_CC_RESPONSE_NEXT_PROPERTY = 3,
+ SPAPR_DR_CC_RESPONSE_PREV_PARENT = 4,
+ SPAPR_DR_CC_RESPONSE_SUCCESS = 0,
+ SPAPR_DR_CC_RESPONSE_ERROR = -1,
+ SPAPR_DR_CC_RESPONSE_CONTINUE = -2,
+ SPAPR_DR_CC_RESPONSE_NOT_CONFIGURABLE = -9003,
} sPAPRDRCCResponse;
typedef void (spapr_drc_detach_cb)(DeviceState *d, void *opaque);
@@ -150,6 +151,7 @@ typedef struct sPAPRDRConnector {
bool configured;
bool awaiting_release;
+ bool signalled;
/* device pointer, via link property */
DeviceState *dev;
@@ -164,17 +166,17 @@ typedef struct sPAPRDRConnectorClass {
/*< public >*/
/* accessors for guest-visible (generally via RTAS) DR state */
- int (*set_isolation_state)(sPAPRDRConnector *drc,
- sPAPRDRIsolationState state);
- int (*set_indicator_state)(sPAPRDRConnector *drc,
- sPAPRDRIndicatorState state);
- int (*set_allocation_state)(sPAPRDRConnector *drc,
- sPAPRDRAllocationState state);
+ uint32_t (*set_isolation_state)(sPAPRDRConnector *drc,
+ sPAPRDRIsolationState state);
+ uint32_t (*set_indicator_state)(sPAPRDRConnector *drc,
+ sPAPRDRIndicatorState state);
+ uint32_t (*set_allocation_state)(sPAPRDRConnector *drc,
+ sPAPRDRAllocationState state);
uint32_t (*get_index)(sPAPRDRConnector *drc);
uint32_t (*get_type)(sPAPRDRConnector *drc);
const char *(*get_name)(sPAPRDRConnector *drc);
- sPAPRDREntitySense (*entity_sense)(sPAPRDRConnector *drc);
+ uint32_t (*entity_sense)(sPAPRDRConnector *drc, sPAPRDREntitySense *state);
/* QEMU interfaces for managing FDT/configure-connector */
const void *(*get_fdt)(sPAPRDRConnector *drc, int *fdt_start_offset);
@@ -187,6 +189,7 @@ typedef struct sPAPRDRConnectorClass {
spapr_drc_detach_cb *detach_cb,
void *detach_cb_opaque, Error **errp);
bool (*release_pending)(sPAPRDRConnector *drc);
+ void (*set_signalled)(sPAPRDRConnector *drc);
} sPAPRDRConnectorClass;
sPAPRDRConnector *spapr_dr_connector_new(Object *owner,
diff --git a/qemu/include/hw/ppc/spapr_vio.h b/qemu/include/hw/ppc/spapr_vio.h
index 2299a5405..c9733e755 100644
--- a/qemu/include/hw/ppc/spapr_vio.h
+++ b/qemu/include/hw/ppc/spapr_vio.h
@@ -34,7 +34,7 @@
#define TYPE_SPAPR_VIO_BUS "spapr-vio-bus"
#define SPAPR_VIO_BUS(obj) OBJECT_CHECK(VIOsPAPRBus, (obj), TYPE_SPAPR_VIO_BUS)
-struct VIOsPAPRDevice;
+#define TYPE_SPAPR_VIO_BRIDGE "spapr-vio-bridge"
typedef struct VIOsPAPR_CRQ {
uint64_t qladdr;
diff --git a/qemu/include/hw/ppc/xics.h b/qemu/include/hw/ppc/xics.h
index 355a96623..f60b06ae8 100644
--- a/qemu/include/hw/ppc/xics.h
+++ b/qemu/include/hw/ppc/xics.h
@@ -161,8 +161,9 @@ struct ICSIRQState {
qemu_irq xics_get_qirq(XICSState *icp, int irq);
void xics_set_irq_type(XICSState *icp, int irq, bool lsi);
-int xics_alloc(XICSState *icp, int src, int irq_hint, bool lsi);
-int xics_alloc_block(XICSState *icp, int src, int num, bool lsi, bool align);
+int xics_alloc(XICSState *icp, int src, int irq_hint, bool lsi, Error **errp);
+int xics_alloc_block(XICSState *icp, int src, int num, bool lsi, bool align,
+ Error **errp);
void xics_free(XICSState *icp, int irq, int num);
void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
diff --git a/qemu/include/hw/qdev-core.h b/qemu/include/hw/qdev-core.h
index 038b54d94..1ce02b20d 100644
--- a/qemu/include/hw/qdev-core.h
+++ b/qemu/include/hw/qdev-core.h
@@ -3,11 +3,9 @@
#include "qemu/queue.h"
#include "qemu/option.h"
-#include "qemu/typedefs.h"
#include "qemu/bitmap.h"
#include "qom/object.h"
#include "hw/irq.h"
-#include "qapi/error.h"
#include "hw/hotplug.h"
enum {
@@ -114,6 +112,19 @@ typedef struct DeviceClass {
* TODO remove once we're there
*/
bool cannot_instantiate_with_device_add_yet;
+ /*
+ * Does this device model survive object_unref(object_new(TNAME))?
+ * All device models should, and this flag shouldn't exist. Some
+ * devices crash in object_new(), some crash or hang in
+ * object_unref(). Makes introspecting properties with
+ * qmp_device_list_properties() dangerous. Bad, because it's used
+ * by -device FOO,help. This flag serves to protect that code.
+ * It should never be set without a comment explaining why it is
+ * set.
+ * TODO remove once we're there
+ */
+ bool cannot_destroy_with_object_finalize_yet;
+
bool hotpluggable;
/* callbacks */
@@ -224,9 +235,9 @@ struct BusState {
struct Property {
const char *name;
PropertyInfo *info;
- int offset;
+ ptrdiff_t offset;
uint8_t bitnr;
- qtype_code qtype;
+ QType qtype;
int64_t defval;
int arrayoffset;
PropertyInfo *arrayinfo;
@@ -324,6 +335,7 @@ int qdev_walk_children(DeviceState *dev,
void *opaque);
void qdev_reset_all(DeviceState *dev);
+void qdev_reset_all_fn(void *opaque);
/**
* @qbus_reset_all:
diff --git a/qemu/include/hw/qdev-properties.h b/qemu/include/hw/qdev-properties.h
index 77538a8ca..0586cacce 100644
--- a/qemu/include/hw/qdev-properties.h
+++ b/qemu/include/hw/qdev-properties.h
@@ -18,8 +18,10 @@ extern PropertyInfo qdev_prop_string;
extern PropertyInfo qdev_prop_chr;
extern PropertyInfo qdev_prop_ptr;
extern PropertyInfo qdev_prop_macaddr;
+extern PropertyInfo qdev_prop_on_off_auto;
extern PropertyInfo qdev_prop_losttickpolicy;
extern PropertyInfo qdev_prop_bios_chs_trans;
+extern PropertyInfo qdev_prop_fdc_drive_type;
extern PropertyInfo qdev_prop_drive;
extern PropertyInfo qdev_prop_netdev;
extern PropertyInfo qdev_prop_vlan;
@@ -154,6 +156,8 @@ extern PropertyInfo qdev_prop_arraylen;
DEFINE_PROP(_n, _s, _f, qdev_prop_drive, BlockBackend *)
#define DEFINE_PROP_MACADDR(_n, _s, _f) \
DEFINE_PROP(_n, _s, _f, qdev_prop_macaddr, MACAddr)
+#define DEFINE_PROP_ON_OFF_AUTO(_n, _s, _f, _d) \
+ DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_on_off_auto, OnOffAuto)
#define DEFINE_PROP_LOSTTICKPOLICY(_n, _s, _f, _d) \
DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_losttickpolicy, \
LostTickPolicy)
@@ -180,8 +184,6 @@ void qdev_prop_set_chr(DeviceState *dev, const char *name, CharDriverState *valu
void qdev_prop_set_netdev(DeviceState *dev, const char *name, NetClientState *value);
void qdev_prop_set_drive(DeviceState *dev, const char *name,
BlockBackend *value, Error **errp);
-void qdev_prop_set_drive_nofail(DeviceState *dev, const char *name,
- BlockBackend *value);
void qdev_prop_set_macaddr(DeviceState *dev, const char *name, uint8_t *value);
void qdev_prop_set_enum(DeviceState *dev, const char *name, int value);
/* FIXME: Remove opaque pointer properties. */
diff --git a/qemu/include/hw/s390x/event-facility.h b/qemu/include/hw/s390x/event-facility.h
index 6a062b668..dd8881838 100644
--- a/qemu/include/hw/s390x/event-facility.h
+++ b/qemu/include/hw/s390x/event-facility.h
@@ -47,6 +47,7 @@
OBJECT_GET_CLASS(SCLPEventClass, (obj), TYPE_SCLP_EVENT)
#define TYPE_SCLP_CPU_HOTPLUG "sclp-cpu-hotplug"
+#define TYPE_SCLP_QUIESCE "sclpquiesce"
typedef struct WriteEventMask {
SCCBHeader h;
@@ -146,8 +147,10 @@ typedef struct WriteEventData {
typedef struct ReadEventData {
SCCBHeader h;
- EventBufferHeader ebh;
- uint32_t mask;
+ union {
+ uint32_t mask;
+ EventBufferHeader ebh;
+ };
} QEMU_PACKED ReadEventData;
typedef struct SCLPEvent {
@@ -186,11 +189,8 @@ typedef struct SCLPEventClass {
OBJECT_GET_CLASS(SCLPEventFacilityClass, (obj), \
TYPE_SCLP_EVENT_FACILITY)
-typedef struct SCLPEventFacility SCLPEventFacility;
-
typedef struct SCLPEventFacilityClass {
- DeviceClass parent_class;
- int (*init)(SCLPEventFacility *ef);
+ SysBusDeviceClass parent_class;
void (*command_handler)(SCLPEventFacility *ef, SCCB *sccb, uint64_t code);
bool (*event_pending)(SCLPEventFacility *ef);
} SCLPEventFacilityClass;
diff --git a/qemu/include/hw/s390x/s390-virtio-ccw.h b/qemu/include/hw/s390x/s390-virtio-ccw.h
new file mode 100644
index 000000000..ab08332fe
--- /dev/null
+++ b/qemu/include/hw/s390x/s390-virtio-ccw.h
@@ -0,0 +1,40 @@
+/*
+ * virtio ccw machine definitions
+ *
+ * Copyright 2012, 2016 IBM Corp.
+ * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or (at
+ * your option) any later version. See the COPYING file in the top-level
+ * directory.
+ */
+#ifndef HW_S390X_S390_VIRTIO_CCW_H
+#define HW_S390X_S390_VIRTIO_CCW_H
+
+#include "hw/boards.h"
+
+#define TYPE_S390_CCW_MACHINE "s390-ccw-machine"
+
+#define S390_CCW_MACHINE(obj) \
+ OBJECT_CHECK(S390CcwMachineState, (obj), TYPE_S390_CCW_MACHINE)
+
+#define S390_MACHINE_CLASS(klass) \
+ OBJECT_CLASS_CHECK(S390CcwMachineClass, (klass), TYPE_S390_CCW_MACHINE)
+
+typedef struct S390CcwMachineState {
+ /*< private >*/
+ MachineState parent_obj;
+
+ /*< public >*/
+ bool aes_key_wrap;
+ bool dea_key_wrap;
+} S390CcwMachineState;
+
+typedef struct S390CcwMachineClass {
+ /*< private >*/
+ MachineClass parent_class;
+
+ /*< public >*/
+} S390CcwMachineClass;
+
+#endif
diff --git a/qemu/include/hw/s390x/sclp.h b/qemu/include/hw/s390x/sclp.h
index e8a64e25b..b0c71b555 100644
--- a/qemu/include/hw/s390x/sclp.h
+++ b/qemu/include/hw/s390x/sclp.h
@@ -163,6 +163,39 @@ typedef struct SCCB {
char data[SCCB_DATA_LEN];
} QEMU_PACKED SCCB;
+#define TYPE_SCLP "sclp"
+#define SCLP(obj) OBJECT_CHECK(SCLPDevice, (obj), TYPE_SCLP)
+#define SCLP_CLASS(oc) OBJECT_CLASS_CHECK(SCLPDeviceClass, (oc), TYPE_SCLP)
+#define SCLP_GET_CLASS(obj) OBJECT_GET_CLASS(SCLPDeviceClass, (obj), TYPE_SCLP)
+
+typedef struct SCLPEventFacility SCLPEventFacility;
+
+typedef struct SCLPDevice {
+ /* private */
+ DeviceState parent_obj;
+ SCLPEventFacility *event_facility;
+ int increment_size;
+
+ /* public */
+} SCLPDevice;
+
+typedef struct SCLPDeviceClass {
+ /* private */
+ DeviceClass parent_class;
+ void (*read_SCP_info)(SCLPDevice *sclp, SCCB *sccb);
+ void (*read_storage_element0_info)(SCLPDevice *sclp, SCCB *sccb);
+ void (*read_storage_element1_info)(SCLPDevice *sclp, SCCB *sccb);
+ void (*attach_storage_element)(SCLPDevice *sclp, SCCB *sccb,
+ uint16_t element);
+ void (*assign_storage)(SCLPDevice *sclp, SCCB *sccb);
+ void (*unassign_storage)(SCLPDevice *sclp, SCCB *sccb);
+ void (*read_cpu_info)(SCLPDevice *sclp, SCCB *sccb);
+
+ /* public */
+ void (*execute)(SCLPDevice *sclp, SCCB *sccb, uint32_t code);
+ void (*service_interrupt)(SCLPDevice *sclp, uint32_t sccb);
+} SCLPDeviceClass;
+
typedef struct sclpMemoryHotplugDev sclpMemoryHotplugDev;
#define TYPE_SCLP_MEMORY_HOTPLUG_DEV "sclp-memory-hotplug-dev"
diff --git a/qemu/include/hw/s390x/storage-keys.h b/qemu/include/hw/s390x/storage-keys.h
new file mode 100644
index 000000000..72b850cb1
--- /dev/null
+++ b/qemu/include/hw/s390x/storage-keys.h
@@ -0,0 +1,60 @@
+/*
+ * s390 storage key device
+ *
+ * Copyright 2015 IBM Corp.
+ * Author(s): Jason J. Herne <jjherne@linux.vnet.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or (at
+ * your option) any later version. See the COPYING file in the top-level
+ * directory.
+ */
+
+#ifndef __S390_STORAGE_KEYS_H
+#define __S390_STORAGE_KEYS_H
+
+#include <hw/qdev.h>
+#include "monitor/monitor.h"
+
+#define TYPE_S390_SKEYS "s390-skeys"
+#define S390_SKEYS(obj) \
+ OBJECT_CHECK(S390SKeysState, (obj), TYPE_S390_SKEYS)
+
+typedef struct S390SKeysState {
+ DeviceState parent_obj;
+ bool migration_enabled;
+
+} S390SKeysState;
+
+#define S390_SKEYS_CLASS(klass) \
+ OBJECT_CLASS_CHECK(S390SKeysClass, (klass), TYPE_S390_SKEYS)
+#define S390_SKEYS_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(S390SKeysClass, (obj), TYPE_S390_SKEYS)
+
+typedef struct S390SKeysClass {
+ DeviceClass parent_class;
+ int (*skeys_enabled)(S390SKeysState *ks);
+ int (*get_skeys)(S390SKeysState *ks, uint64_t start_gfn, uint64_t count,
+ uint8_t *keys);
+ int (*set_skeys)(S390SKeysState *ks, uint64_t start_gfn, uint64_t count,
+ uint8_t *keys);
+} S390SKeysClass;
+
+#define TYPE_KVM_S390_SKEYS "s390-skeys-kvm"
+#define TYPE_QEMU_S390_SKEYS "s390-skeys-qemu"
+#define QEMU_S390_SKEYS(obj) \
+ OBJECT_CHECK(QEMUS390SKeysState, (obj), TYPE_QEMU_S390_SKEYS)
+
+typedef struct QEMUS390SKeysState {
+ S390SKeysState parent_obj;
+ uint8_t *keydata;
+ uint32_t key_count;
+} QEMUS390SKeysState;
+
+void s390_skeys_init(void);
+
+S390SKeysState *s390_get_skeys_device(void);
+
+void hmp_dump_skeys(Monitor *mon, const QDict *qdict);
+void hmp_info_skeys(Monitor *mon, const QDict *qdict);
+
+#endif /* __S390_STORAGE_KEYS_H */
diff --git a/qemu/include/hw/scsi/scsi.h b/qemu/include/hw/scsi/scsi.h
index cdaf0f8eb..8acd3fa99 100644
--- a/qemu/include/hw/scsi/scsi.h
+++ b/qemu/include/hw/scsi/scsi.h
@@ -2,7 +2,6 @@
#define QEMU_HW_SCSI_H
#include "hw/qdev.h"
-#include "qemu/typedefs.h"
#include "hw/block/block.h"
#include "sysemu/sysemu.h"
#include "qemu/notify.h"
@@ -108,6 +107,8 @@ struct SCSIDevice
int blocksize;
int type;
uint64_t max_lba;
+ uint64_t wwn;
+ uint64_t port_wwn;
};
extern const VMStateDescription vmstate_scsi_device;
@@ -250,7 +251,6 @@ SCSIRequest *scsi_req_alloc(const SCSIReqOps *reqops, SCSIDevice *d,
SCSIRequest *scsi_req_new(SCSIDevice *d, uint32_t tag, uint32_t lun,
uint8_t *buf, void *hba_private);
int32_t scsi_req_enqueue(SCSIRequest *req);
-void scsi_req_free(SCSIRequest *req);
SCSIRequest *scsi_req_ref(SCSIRequest *req);
void scsi_req_unref(SCSIRequest *req);
@@ -272,6 +272,7 @@ void scsi_device_purge_requests(SCSIDevice *sdev, SCSISense sense);
void scsi_device_set_ua(SCSIDevice *sdev, SCSISense sense);
void scsi_device_report_change(SCSIDevice *dev, SCSISense sense);
void scsi_device_unit_attention_reported(SCSIDevice *dev);
+void scsi_generic_read_device_identification(SCSIDevice *dev);
int scsi_device_get_sense(SCSIDevice *dev, uint8_t *buf, int len, bool fixed);
SCSIDevice *scsi_device_find(SCSIBus *bus, int channel, int target, int lun);
diff --git a/qemu/include/hw/sd.h b/qemu/include/hw/sd/sd.h
index 79adb5bb4..d5d273a44 100644
--- a/qemu/include/hw/sd.h
+++ b/qemu/include/hw/sd/sd.h
@@ -67,7 +67,51 @@ typedef struct {
} SDRequest;
typedef struct SDState SDState;
+typedef struct SDBus SDBus;
+#define TYPE_SD_CARD "sd-card"
+#define SD_CARD(obj) OBJECT_CHECK(SDState, (obj), TYPE_SD_CARD)
+#define SD_CARD_CLASS(klass) \
+ OBJECT_CLASS_CHECK(SDCardClass, (klass), TYPE_SD_CARD)
+#define SD_CARD_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(SDCardClass, (obj), TYPE_SD_CARD)
+
+typedef struct {
+ /*< private >*/
+ DeviceClass parent_class;
+ /*< public >*/
+
+ int (*do_command)(SDState *sd, SDRequest *req, uint8_t *response);
+ void (*write_data)(SDState *sd, uint8_t value);
+ uint8_t (*read_data)(SDState *sd);
+ bool (*data_ready)(SDState *sd);
+ void (*enable)(SDState *sd, bool enable);
+ bool (*get_inserted)(SDState *sd);
+ bool (*get_readonly)(SDState *sd);
+} SDCardClass;
+
+#define TYPE_SD_BUS "sd-bus"
+#define SD_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SD_BUS)
+#define SD_BUS_CLASS(klass) OBJECT_CLASS_CHECK(SDBusClass, (klass), TYPE_SD_BUS)
+#define SD_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(SDBusClass, (obj), TYPE_SD_BUS)
+
+struct SDBus {
+ BusState qbus;
+};
+
+typedef struct {
+ /*< private >*/
+ BusClass parent_class;
+ /*< public >*/
+
+ /* These methods are called by the SD device to notify the controller
+ * when the card insertion or readonly status changes
+ */
+ void (*set_inserted)(DeviceState *dev, bool inserted);
+ void (*set_readonly)(DeviceState *dev, bool readonly);
+} SDBusClass;
+
+/* Legacy functions to be used only by non-qdevified callers */
SDState *sd_init(BlockBackend *bs, bool is_spi);
int sd_do_command(SDState *sd, SDRequest *req,
uint8_t *response);
@@ -75,6 +119,27 @@ void sd_write_data(SDState *sd, uint8_t value);
uint8_t sd_read_data(SDState *sd);
void sd_set_cb(SDState *sd, qemu_irq readonly, qemu_irq insert);
bool sd_data_ready(SDState *sd);
+/* sd_enable should not be used -- it is only used on the nseries boards,
+ * where it is part of a broken implementation of the MMC card slot switch
+ * (there should be two card slots which are multiplexed to a single MMC
+ * controller, but instead we model it with one card and controller and
+ * disable the card when the second slot is selected, so it looks like the
+ * second slot is always empty).
+ */
void sd_enable(SDState *sd, bool enable);
+/* Functions to be used by qdevified callers (working via
+ * an SDBus rather than directly with SDState)
+ */
+int sdbus_do_command(SDBus *sd, SDRequest *req, uint8_t *response);
+void sdbus_write_data(SDBus *sd, uint8_t value);
+uint8_t sdbus_read_data(SDBus *sd);
+bool sdbus_data_ready(SDBus *sd);
+bool sdbus_get_inserted(SDBus *sd);
+bool sdbus_get_readonly(SDBus *sd);
+
+/* Functions to be used by SD devices to report back to qdevified controllers */
+void sdbus_set_inserted(SDBus *sd, bool inserted);
+void sdbus_set_readonly(SDBus *sd, bool inserted);
+
#endif /* __hw_sd_h */
diff --git a/qemu/include/hw/sd/sdhci.h b/qemu/include/hw/sd/sdhci.h
new file mode 100644
index 000000000..0f0c3f1e6
--- /dev/null
+++ b/qemu/include/hw/sd/sdhci.h
@@ -0,0 +1,95 @@
+/*
+ * SD Association Host Standard Specification v2.0 controller emulation
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * Mitsyanko Igor <i.mitsyanko@samsung.com>
+ * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
+ *
+ * Based on MMC controller for Samsung S5PC1xx-based board emulation
+ * by Alexey Merkulov and Vladimir Monakhov.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU _General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef SDHCI_H
+#define SDHCI_H
+
+#include "qemu-common.h"
+#include "hw/block/block.h"
+#include "hw/pci/pci.h"
+#include "hw/sysbus.h"
+#include "hw/sd/sd.h"
+
+/* SD/MMC host controller state */
+typedef struct SDHCIState {
+ union {
+ PCIDevice pcidev;
+ SysBusDevice busdev;
+ };
+ SDBus sdbus;
+ MemoryRegion iomem;
+
+ QEMUTimer *insert_timer; /* timer for 'changing' sd card. */
+ QEMUTimer *transfer_timer;
+ qemu_irq eject_cb;
+ qemu_irq ro_cb;
+ qemu_irq irq;
+
+ uint32_t sdmasysad; /* SDMA System Address register */
+ uint16_t blksize; /* Host DMA Buff Boundary and Transfer BlkSize Reg */
+ uint16_t blkcnt; /* Blocks count for current transfer */
+ uint32_t argument; /* Command Argument Register */
+ uint16_t trnmod; /* Transfer Mode Setting Register */
+ uint16_t cmdreg; /* Command Register */
+ uint32_t rspreg[4]; /* Response Registers 0-3 */
+ uint32_t prnsts; /* Present State Register */
+ uint8_t hostctl; /* Host Control Register */
+ uint8_t pwrcon; /* Power control Register */
+ uint8_t blkgap; /* Block Gap Control Register */
+ uint8_t wakcon; /* WakeUp Control Register */
+ uint16_t clkcon; /* Clock control Register */
+ uint8_t timeoutcon; /* Timeout Control Register */
+ uint8_t admaerr; /* ADMA Error Status Register */
+ uint16_t norintsts; /* Normal Interrupt Status Register */
+ uint16_t errintsts; /* Error Interrupt Status Register */
+ uint16_t norintstsen; /* Normal Interrupt Status Enable Register */
+ uint16_t errintstsen; /* Error Interrupt Status Enable Register */
+ uint16_t norintsigen; /* Normal Interrupt Signal Enable Register */
+ uint16_t errintsigen; /* Error Interrupt Signal Enable Register */
+ uint16_t acmd12errsts; /* Auto CMD12 error status register */
+ uint64_t admasysaddr; /* ADMA System Address Register */
+
+ uint32_t capareg; /* Capabilities Register */
+ uint32_t maxcurr; /* Maximum Current Capabilities Register */
+ uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */
+ uint32_t buf_maxsz;
+ uint16_t data_count; /* current element in FIFO buffer */
+ uint8_t stopped_state;/* Current SDHC state */
+ bool pending_insert_quirk;/* Quirk for Raspberry Pi card insert int */
+ bool pending_insert_state;
+ /* Buffer Data Port Register - virtual access point to R and W buffers */
+ /* Software Reset Register - always reads as 0 */
+ /* Force Event Auto CMD12 Error Interrupt Reg - write only */
+ /* Force Event Error Interrupt Register- write only */
+ /* RO Host Controller Version Register always reads as 0x2401 */
+} SDHCIState;
+
+#define TYPE_PCI_SDHCI "sdhci-pci"
+#define PCI_SDHCI(obj) OBJECT_CHECK(SDHCIState, (obj), TYPE_PCI_SDHCI)
+
+#define TYPE_SYSBUS_SDHCI "generic-sdhci"
+#define SYSBUS_SDHCI(obj) \
+ OBJECT_CHECK(SDHCIState, (obj), TYPE_SYSBUS_SDHCI)
+
+#endif /* SDHCI_H */
diff --git a/qemu/include/hw/i386/smbios.h b/qemu/include/hw/smbios/smbios.h
index d2850bed2..76ccf7098 100644
--- a/qemu/include/hw/i386/smbios.h
+++ b/qemu/include/hw/smbios/smbios.h
@@ -17,23 +17,33 @@
#define SMBIOS_MAX_TYPE 127
-void smbios_entry_add(QemuOpts *opts);
-void smbios_set_cpuid(uint32_t version, uint32_t features);
-void smbios_set_defaults(const char *manufacturer, const char *product,
- const char *version, bool legacy_mode,
- bool uuid_encoded);
-uint8_t *smbios_get_table_legacy(size_t *length);
-void smbios_get_tables(uint8_t **tables, size_t *tables_len,
- uint8_t **anchor, size_t *anchor_len);
+/* memory area description, used by type 19 table */
+struct smbios_phys_mem_area {
+ uint64_t address;
+ uint64_t length;
+};
/*
* SMBIOS spec defined tables
*/
+typedef enum SmbiosEntryPointType {
+ SMBIOS_ENTRY_POINT_21,
+ SMBIOS_ENTRY_POINT_30,
+} SmbiosEntryPointType;
-/* SMBIOS entry point (anchor).
- * BIOS must place this at a 16-bit-aligned address between 0xf0000 and 0xfffff.
+/* SMBIOS Entry Point
+ * There are two types of entry points defined in the SMBIOS specification
+ * (see below). BIOS must place the entry point(s) at a 16-bit-aligned
+ * address between 0xf0000 and 0xfffff. Note that either entry point type
+ * can be used in a 64-bit target system, except that SMBIOS 2.1 entry point
+ * only allows the SMBIOS struct table to reside below 4GB address space.
*/
-struct smbios_entry_point {
+
+/* SMBIOS 2.1 (32-bit) Entry Point
+ * - introduced since SMBIOS 2.1
+ * - supports structure table below 4GB only
+ */
+struct smbios_21_entry_point {
uint8_t anchor_string[4];
uint8_t checksum;
uint8_t length;
@@ -50,6 +60,28 @@ struct smbios_entry_point {
uint8_t smbios_bcd_revision;
} QEMU_PACKED;
+/* SMBIOS 3.0 (64-bit) Entry Point
+ * - introduced since SMBIOS 3.0
+ * - supports structure table at 64-bit address space
+ */
+struct smbios_30_entry_point {
+ uint8_t anchor_string[5];
+ uint8_t checksum;
+ uint8_t length;
+ uint8_t smbios_major_version;
+ uint8_t smbios_minor_version;
+ uint8_t smbios_doc_rev;
+ uint8_t entry_point_revision;
+ uint8_t reserved;
+ uint32_t structure_table_max_size;
+ uint64_t structure_table_address;
+} QEMU_PACKED;
+
+typedef union {
+ struct smbios_21_entry_point ep21;
+ struct smbios_30_entry_point ep30;
+} QEMU_PACKED SmbiosEntryPoint;
+
/* This goes at the beginning of every SMBIOS structure. */
struct smbios_structure_header {
uint8_t type;
@@ -224,4 +256,14 @@ struct smbios_type_127 {
struct smbios_structure_header header;
} QEMU_PACKED;
+void smbios_entry_add(QemuOpts *opts);
+void smbios_set_cpuid(uint32_t version, uint32_t features);
+void smbios_set_defaults(const char *manufacturer, const char *product,
+ const char *version, bool legacy_mode,
+ bool uuid_encoded, SmbiosEntryPointType ep_type);
+uint8_t *smbios_get_table_legacy(size_t *length);
+void smbios_get_tables(const struct smbios_phys_mem_area *mem_array,
+ const unsigned int mem_array_size,
+ uint8_t **tables, size_t *tables_len,
+ uint8_t **anchor, size_t *anchor_len);
#endif /*QEMU_SMBIOS_H */
diff --git a/qemu/include/hw/ssi.h b/qemu/include/hw/ssi/ssi.h
index df0f83851..4a0a53903 100644
--- a/qemu/include/hw/ssi.h
+++ b/qemu/include/hw/ssi/ssi.h
@@ -14,6 +14,8 @@
#include "hw/qdev.h"
typedef struct SSISlave SSISlave;
+typedef struct SSISlaveClass SSISlaveClass;
+typedef enum SSICSMode SSICSMode;
#define TYPE_SSI_SLAVE "ssi-slave"
#define SSI_SLAVE(obj) \
@@ -25,14 +27,14 @@ typedef struct SSISlave SSISlave;
#define SSI_GPIO_CS "ssi-gpio-cs"
-typedef enum {
+enum SSICSMode {
SSI_CS_NONE = 0,
SSI_CS_LOW,
SSI_CS_HIGH,
-} SSICSMode;
+};
/* Slave devices. */
-typedef struct SSISlaveClass {
+struct SSISlaveClass {
DeviceClass parent_class;
int (*init)(SSISlave *dev);
@@ -55,7 +57,7 @@ typedef struct SSISlaveClass {
* always be called for the device for every txrx access to the parent bus
*/
uint32_t (*transfer_raw)(SSISlave *dev, uint32_t val);
-} SSISlaveClass;
+};
struct SSISlave {
DeviceState parent_obj;
diff --git a/qemu/include/hw/ssi/xilinx_spips.h b/qemu/include/hw/ssi/xilinx_spips.h
new file mode 100644
index 000000000..dbb9eefba
--- /dev/null
+++ b/qemu/include/hw/ssi/xilinx_spips.h
@@ -0,0 +1,72 @@
+/*
+ * Header file for the Xilinx Zynq SPI controller
+ *
+ * Copyright (C) 2015 Xilinx Inc
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef XLNX_SPIPS_H
+#define XLNX_SPIPS_H
+
+#include "hw/ssi/ssi.h"
+#include "qemu/fifo8.h"
+
+typedef struct XilinxSPIPS XilinxSPIPS;
+
+#define XLNX_SPIPS_R_MAX (0x100 / 4)
+
+struct XilinxSPIPS {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+ MemoryRegion mmlqspi;
+
+ qemu_irq irq;
+ int irqline;
+
+ uint8_t num_cs;
+ uint8_t num_busses;
+
+ uint8_t snoop_state;
+ qemu_irq *cs_lines;
+ SSIBus **spi;
+
+ Fifo8 rx_fifo;
+ Fifo8 tx_fifo;
+
+ uint8_t num_txrx_bytes;
+
+ uint32_t regs[XLNX_SPIPS_R_MAX];
+};
+
+#define TYPE_XILINX_SPIPS "xlnx.ps7-spi"
+#define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi"
+
+#define XILINX_SPIPS(obj) \
+ OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS)
+#define XILINX_SPIPS_CLASS(klass) \
+ OBJECT_CLASS_CHECK(XilinxSPIPSClass, (klass), TYPE_XILINX_SPIPS)
+#define XILINX_SPIPS_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(XilinxSPIPSClass, (obj), TYPE_XILINX_SPIPS)
+
+#define XILINX_QSPIPS(obj) \
+ OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS)
+
+#endif /* XLNX_SPIPS_H */
diff --git a/qemu/include/hw/timer/aspeed_timer.h b/qemu/include/hw/timer/aspeed_timer.h
new file mode 100644
index 000000000..44dc2f89d
--- /dev/null
+++ b/qemu/include/hw/timer/aspeed_timer.h
@@ -0,0 +1,59 @@
+/*
+ * ASPEED AST2400 Timer
+ *
+ * Andrew Jeffery <andrew@aj.id.au>
+ *
+ * Copyright (C) 2016 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef ASPEED_TIMER_H
+#define ASPEED_TIMER_H
+
+#include "hw/ptimer.h"
+
+#define ASPEED_TIMER(obj) \
+ OBJECT_CHECK(AspeedTimerCtrlState, (obj), TYPE_ASPEED_TIMER);
+#define TYPE_ASPEED_TIMER "aspeed.timer"
+#define ASPEED_TIMER_NR_TIMERS 8
+
+typedef struct AspeedTimer {
+ qemu_irq irq;
+
+ uint8_t id;
+
+ /**
+ * Track the line level as the ASPEED timers implement edge triggered
+ * interrupts, signalling with both the rising and falling edge.
+ */
+ int32_t level;
+ ptimer_state *timer;
+ uint32_t reload;
+ uint32_t match[2];
+} AspeedTimer;
+
+typedef struct AspeedTimerCtrlState {
+ /*< private >*/
+ SysBusDevice parent;
+
+ /*< public >*/
+ MemoryRegion iomem;
+
+ uint32_t ctrl;
+ uint32_t ctrl2;
+ AspeedTimer timers[ASPEED_TIMER_NR_TIMERS];
+} AspeedTimerCtrlState;
+
+#endif /* ASPEED_TIMER_H */
diff --git a/qemu/include/hw/timer/digic-timer.h b/qemu/include/hw/timer/digic-timer.h
index ae913482c..d9e67fe29 100644
--- a/qemu/include/hw/timer/digic-timer.h
+++ b/qemu/include/hw/timer/digic-timer.h
@@ -19,7 +19,6 @@
#define HW_TIMER_DIGIC_TIMER_H
#include "hw/sysbus.h"
-#include "qemu/typedefs.h"
#include "hw/ptimer.h"
#define TYPE_DIGIC_TIMER "digic-timer"
diff --git a/qemu/include/hw/timer/hpet.h b/qemu/include/hw/timer/hpet.h
index 773953be7..f38bcfecd 100644
--- a/qemu/include/hw/timer/hpet.h
+++ b/qemu/include/hw/timer/hpet.h
@@ -16,9 +16,10 @@
#include "qom/object.h"
#define HPET_BASE 0xfed00000
-#define HPET_CLK_PERIOD 10000000ULL /* 10000000 femtoseconds == 10ns*/
+#define HPET_LEN 0x400
+#define HPET_CLK_PERIOD 10 /* 10 ns*/
-#define FS_PER_NS 1000000
+#define FS_PER_NS 1000000 /* 1000000 femtoseconds == 1 ns */
#define HPET_MIN_TIMERS 3
#define HPET_MAX_TIMERS 32
diff --git a/qemu/include/hw/timer/imx_epit.h b/qemu/include/hw/timer/imx_epit.h
new file mode 100644
index 000000000..0730ac35e
--- /dev/null
+++ b/qemu/include/hw/timer/imx_epit.h
@@ -0,0 +1,80 @@
+/*
+ * i.MX EPIT Timer
+ *
+ * Copyright (c) 2008 OK Labs
+ * Copyright (c) 2011 NICTA Pty Ltd
+ * Originally written by Hans Jiang
+ * Updated by Peter Chubb
+ * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef IMX_EPIT_H
+#define IMX_EPIT_H
+
+#include "hw/sysbus.h"
+#include "hw/ptimer.h"
+#include "hw/misc/imx_ccm.h"
+
+/*
+ * EPIT: Enhanced periodic interrupt timer
+ */
+
+#define CR_EN (1 << 0)
+#define CR_ENMOD (1 << 1)
+#define CR_OCIEN (1 << 2)
+#define CR_RLD (1 << 3)
+#define CR_PRESCALE_SHIFT (4)
+#define CR_PRESCALE_MASK (0xfff)
+#define CR_SWR (1 << 16)
+#define CR_IOVW (1 << 17)
+#define CR_DBGEN (1 << 18)
+#define CR_WAITEN (1 << 19)
+#define CR_DOZEN (1 << 20)
+#define CR_STOPEN (1 << 21)
+#define CR_CLKSRC_SHIFT (24)
+#define CR_CLKSRC_MASK (0x3 << CR_CLKSRC_SHIFT)
+
+#define EPIT_TIMER_MAX 0XFFFFFFFFUL
+
+#define TYPE_IMX_EPIT "imx.epit"
+#define IMX_EPIT(obj) OBJECT_CHECK(IMXEPITState, (obj), TYPE_IMX_EPIT)
+
+typedef struct IMXEPITState{
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ ptimer_state *timer_reload;
+ ptimer_state *timer_cmp;
+ MemoryRegion iomem;
+ IMXCCMState *ccm;
+
+ uint32_t cr;
+ uint32_t sr;
+ uint32_t lr;
+ uint32_t cmp;
+ uint32_t cnt;
+
+ uint32_t freq;
+ qemu_irq irq;
+} IMXEPITState;
+
+#endif /* IMX_EPIT_H */
diff --git a/qemu/include/hw/timer/imx_gpt.h b/qemu/include/hw/timer/imx_gpt.h
new file mode 100644
index 000000000..461adbe53
--- /dev/null
+++ b/qemu/include/hw/timer/imx_gpt.h
@@ -0,0 +1,108 @@
+/*
+ * i.MX GPT Timer
+ *
+ * Copyright (c) 2008 OK Labs
+ * Copyright (c) 2011 NICTA Pty Ltd
+ * Originally written by Hans Jiang
+ * Updated by Peter Chubb
+ * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef IMX_GPT_H
+#define IMX_GPT_H
+
+#include "hw/sysbus.h"
+#include "hw/ptimer.h"
+#include "hw/misc/imx_ccm.h"
+
+/*
+ * GPT : General purpose timer
+ *
+ * This timer counts up continuously while it is enabled, resetting itself
+ * to 0 when it reaches GPT_TIMER_MAX (in freerun mode) or when it
+ * reaches the value of one of the ocrX (in periodic mode).
+ */
+
+#define GPT_TIMER_MAX 0XFFFFFFFFUL
+
+/* Control register. Not all of these bits have any effect (yet) */
+#define GPT_CR_EN (1 << 0) /* GPT Enable */
+#define GPT_CR_ENMOD (1 << 1) /* GPT Enable Mode */
+#define GPT_CR_DBGEN (1 << 2) /* GPT Debug mode enable */
+#define GPT_CR_WAITEN (1 << 3) /* GPT Wait Mode Enable */
+#define GPT_CR_DOZEN (1 << 4) /* GPT Doze mode enable */
+#define GPT_CR_STOPEN (1 << 5) /* GPT Stop Mode Enable */
+#define GPT_CR_CLKSRC_SHIFT (6)
+#define GPT_CR_CLKSRC_MASK (0x7)
+
+#define GPT_CR_FRR (1 << 9) /* Freerun or Restart */
+#define GPT_CR_SWR (1 << 15) /* Software Reset */
+#define GPT_CR_IM1 (3 << 16) /* Input capture channel 1 mode (2 bits) */
+#define GPT_CR_IM2 (3 << 18) /* Input capture channel 2 mode (2 bits) */
+#define GPT_CR_OM1 (7 << 20) /* Output Compare Channel 1 Mode (3 bits) */
+#define GPT_CR_OM2 (7 << 23) /* Output Compare Channel 2 Mode (3 bits) */
+#define GPT_CR_OM3 (7 << 26) /* Output Compare Channel 3 Mode (3 bits) */
+#define GPT_CR_FO1 (1 << 29) /* Force Output Compare Channel 1 */
+#define GPT_CR_FO2 (1 << 30) /* Force Output Compare Channel 2 */
+#define GPT_CR_FO3 (1 << 31) /* Force Output Compare Channel 3 */
+
+#define GPT_SR_OF1 (1 << 0)
+#define GPT_SR_OF2 (1 << 1)
+#define GPT_SR_OF3 (1 << 2)
+#define GPT_SR_ROV (1 << 5)
+
+#define GPT_IR_OF1IE (1 << 0)
+#define GPT_IR_OF2IE (1 << 1)
+#define GPT_IR_OF3IE (1 << 2)
+#define GPT_IR_ROVIE (1 << 5)
+
+#define TYPE_IMX_GPT "imx.gpt"
+#define IMX_GPT(obj) OBJECT_CHECK(IMXGPTState, (obj), TYPE_IMX_GPT)
+
+typedef struct IMXGPTState{
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ ptimer_state *timer;
+ MemoryRegion iomem;
+ IMXCCMState *ccm;
+
+ uint32_t cr;
+ uint32_t pr;
+ uint32_t sr;
+ uint32_t ir;
+ uint32_t ocr1;
+ uint32_t ocr2;
+ uint32_t ocr3;
+ uint32_t icr1;
+ uint32_t icr2;
+ uint32_t cnt;
+
+ uint32_t next_timeout;
+ uint32_t next_int;
+
+ uint32_t freq;
+
+ qemu_irq irq;
+} IMXGPTState;
+
+#endif /* IMX_GPT_H */
diff --git a/qemu/include/hw/usb.h b/qemu/include/hw/usb.h
index c8b6e7b57..163fe0490 100644
--- a/qemu/include/hw/usb.h
+++ b/qemu/include/hw/usb.h
@@ -26,6 +26,7 @@
*/
#include "hw/qdev.h"
+#include "qemu/iov.h"
#include "qemu/queue.h"
/* Constants related to the USB / PCI interaction */
diff --git a/qemu/include/hw/vfio/vfio-amd-xgbe.h b/qemu/include/hw/vfio/vfio-amd-xgbe.h
new file mode 100644
index 000000000..9fff65e99
--- /dev/null
+++ b/qemu/include/hw/vfio/vfio-amd-xgbe.h
@@ -0,0 +1,51 @@
+/*
+ * VFIO AMD XGBE device
+ *
+ * Copyright Linaro Limited, 2015
+ *
+ * Authors:
+ * Eric Auger <eric.auger@linaro.org>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef HW_VFIO_VFIO_AMD_XGBE_H
+#define HW_VFIO_VFIO_AMD_XGBE_H
+
+#include "hw/vfio/vfio-platform.h"
+
+#define TYPE_VFIO_AMD_XGBE "vfio-amd-xgbe"
+
+/**
+ * This device exposes:
+ * - 5 MMIO regions: MAC, PCS, SerDes Rx/Tx regs,
+ SerDes Integration Registers 1/2 & 2/2
+ * - 2 level sensitive IRQs and optional DMA channel IRQs
+ */
+struct VFIOAmdXgbeDevice {
+ VFIOPlatformDevice vdev;
+};
+
+typedef struct VFIOAmdXgbeDevice VFIOAmdXgbeDevice;
+
+struct VFIOAmdXgbeDeviceClass {
+ /*< private >*/
+ VFIOPlatformDeviceClass parent_class;
+ /*< public >*/
+ DeviceRealize parent_realize;
+};
+
+typedef struct VFIOAmdXgbeDeviceClass VFIOAmdXgbeDeviceClass;
+
+#define VFIO_AMD_XGBE_DEVICE(obj) \
+ OBJECT_CHECK(VFIOAmdXgbeDevice, (obj), TYPE_VFIO_AMD_XGBE)
+#define VFIO_AMD_XGBE_DEVICE_CLASS(klass) \
+ OBJECT_CLASS_CHECK(VFIOAmdXgbeDeviceClass, (klass), \
+ TYPE_VFIO_AMD_XGBE)
+#define VFIO_AMD_XGBE_DEVICE_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(VFIOAmdXgbeDeviceClass, (obj), \
+ TYPE_VFIO_AMD_XGBE)
+
+#endif
diff --git a/qemu/include/hw/vfio/vfio-common.h b/qemu/include/hw/vfio/vfio-common.h
index 59a321d47..eb0e1b034 100644
--- a/qemu/include/hw/vfio/vfio-common.h
+++ b/qemu/include/hw/vfio/vfio-common.h
@@ -25,6 +25,9 @@
#include "exec/memory.h"
#include "qemu/queue.h"
#include "qemu/notify.h"
+#ifdef CONFIG_LINUX
+#include <linux/vfio.h>
+#endif
/*#define DEBUG_VFIO*/
#ifdef DEBUG_VFIO
@@ -35,24 +38,26 @@
do { } while (0)
#endif
-/* Extra debugging, trap acceleration paths for more logging */
-#define VFIO_ALLOW_KVM_INTX 1
-#define VFIO_ALLOW_KVM_MSI 1
-#define VFIO_ALLOW_KVM_MSIX 1
-
enum {
VFIO_DEVICE_TYPE_PCI = 0,
VFIO_DEVICE_TYPE_PLATFORM = 1,
};
+typedef struct VFIOMmap {
+ MemoryRegion mem;
+ void *mmap;
+ off_t offset;
+ size_t size;
+} VFIOMmap;
+
typedef struct VFIORegion {
struct VFIODevice *vbasedev;
off_t fd_offset; /* offset of region within device fd */
- MemoryRegion mem; /* slow, read/write access */
- MemoryRegion mmap_mem; /* direct mapped access */
- void *mmap;
+ MemoryRegion *mem; /* slow, read/write access */
size_t size;
uint32_t flags; /* VFIO region flags (rd/wr/mmap) */
+ uint32_t nr_mmaps;
+ VFIOMmap *mmaps;
uint8_t nr; /* cache the region number for debug */
} VFIORegion;
@@ -64,22 +69,19 @@ typedef struct VFIOAddressSpace {
struct VFIOGroup;
-typedef struct VFIOType1 {
- MemoryListener listener;
- int error;
- bool initialized;
-} VFIOType1;
-
typedef struct VFIOContainer {
VFIOAddressSpace *space;
int fd; /* /dev/vfio/vfio, empowered by the attached groups */
- struct {
- /* enable abstraction to support various iommu backends */
- union {
- VFIOType1 type1;
- };
- void (*release)(struct VFIOContainer *);
- } iommu_data;
+ MemoryListener listener;
+ int error;
+ bool initialized;
+ /*
+ * This assumes the host IOMMU can support only a single
+ * contiguous IOVA window. We may need to generalize that in
+ * future
+ */
+ hwaddr min_iova, max_iova;
+ uint64_t iova_pgsizes;
QLIST_HEAD(, VFIOGuestIOMMU) giommu_list;
QLIST_HEAD(, VFIOGroup) group_list;
QLIST_ENTRY(VFIOContainer) next;
@@ -97,12 +99,13 @@ typedef struct VFIODeviceOps VFIODeviceOps;
typedef struct VFIODevice {
QLIST_ENTRY(VFIODevice) next;
struct VFIOGroup *group;
+ char *sysfsdev;
char *name;
int fd;
int type;
bool reset_works;
bool needs_reset;
- bool allow_mmap;
+ bool no_mmap;
VFIODeviceOps *ops;
unsigned int num_irqs;
unsigned int num_regions;
@@ -132,10 +135,12 @@ void vfio_region_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size);
uint64_t vfio_region_read(void *opaque,
hwaddr addr, unsigned size);
-int vfio_mmap_region(Object *vdev, VFIORegion *region,
- MemoryRegion *mem, MemoryRegion *submem,
- void **map, size_t size, off_t offset,
- const char *name);
+int vfio_region_setup(Object *obj, VFIODevice *vbasedev, VFIORegion *region,
+ int index, const char *name);
+int vfio_region_mmap(VFIORegion *region);
+void vfio_region_mmaps_set_enabled(VFIORegion *region, bool enabled);
+void vfio_region_exit(VFIORegion *region);
+void vfio_region_finalize(VFIORegion *region);
void vfio_reset_handler(void *opaque);
VFIOGroup *vfio_get_group(int groupid, AddressSpace *as);
void vfio_put_group(VFIOGroup *group);
@@ -146,4 +151,8 @@ extern const MemoryRegionOps vfio_region_ops;
extern QLIST_HEAD(vfio_group_head, VFIOGroup) vfio_group_list;
extern QLIST_HEAD(vfio_as_head, VFIOAddressSpace) vfio_address_spaces;
+#ifdef CONFIG_LINUX
+int vfio_get_region_info(VFIODevice *vbasedev, int index,
+ struct vfio_region_info **info);
+#endif
#endif /* !HW_VFIO_VFIO_COMMON_H */
diff --git a/qemu/include/hw/vfio/vfio-platform.h b/qemu/include/hw/vfio/vfio-platform.h
index c5cf1d79f..b468f80b1 100644
--- a/qemu/include/hw/vfio/vfio-platform.h
+++ b/qemu/include/hw/vfio/vfio-platform.h
@@ -34,8 +34,8 @@ enum {
typedef struct VFIOINTp {
QLIST_ENTRY(VFIOINTp) next; /* entry for IRQ list */
QSIMPLEQ_ENTRY(VFIOINTp) pqnext; /* entry for pending IRQ queue */
- EventNotifier interrupt; /* eventfd triggered on interrupt */
- EventNotifier unmask; /* eventfd for unmask on QEMU bypass */
+ EventNotifier *interrupt; /* eventfd triggered on interrupt */
+ EventNotifier *unmask; /* eventfd for unmask on QEMU bypass */
qemu_irq qemuirq;
struct VFIOPlatformDevice *vdev; /* back pointer to device */
int state; /* inactive, pending, active */
diff --git a/qemu/include/hw/vfio/vfio.h b/qemu/include/hw/vfio/vfio.h
index 0b26cd8e1..f27d59922 100644
--- a/qemu/include/hw/vfio/vfio.h
+++ b/qemu/include/hw/vfio/vfio.h
@@ -1,9 +1,7 @@
#ifndef VFIO_API_H
#define VFIO_API_H
-#include "qemu/typedefs.h"
-
-extern int vfio_container_ioctl(AddressSpace *as, int32_t groupid,
- int req, void *param);
+bool vfio_eeh_as_ok(AddressSpace *as);
+int vfio_eeh_as_op(AddressSpace *as, uint32_t op);
#endif
diff --git a/qemu/include/hw/virtio/dataplane/vring-accessors.h b/qemu/include/hw/virtio/dataplane/vring-accessors.h
deleted file mode 100644
index 815c19b6e..000000000
--- a/qemu/include/hw/virtio/dataplane/vring-accessors.h
+++ /dev/null
@@ -1,75 +0,0 @@
-#ifndef VRING_ACCESSORS_H
-#define VRING_ACCESSORS_H
-
-#include "standard-headers/linux/virtio_ring.h"
-#include "hw/virtio/virtio.h"
-#include "hw/virtio/virtio-access.h"
-
-static inline uint16_t vring_get_used_idx(VirtIODevice *vdev, Vring *vring)
-{
- return virtio_tswap16(vdev, vring->vr.used->idx);
-}
-
-static inline void vring_set_used_idx(VirtIODevice *vdev, Vring *vring,
- uint16_t idx)
-{
- vring->vr.used->idx = virtio_tswap16(vdev, idx);
-}
-
-static inline uint16_t vring_get_avail_idx(VirtIODevice *vdev, Vring *vring)
-{
- return virtio_tswap16(vdev, vring->vr.avail->idx);
-}
-
-static inline uint16_t vring_get_avail_ring(VirtIODevice *vdev, Vring *vring,
- int i)
-{
- return virtio_tswap16(vdev, vring->vr.avail->ring[i]);
-}
-
-static inline void vring_set_used_ring_id(VirtIODevice *vdev, Vring *vring,
- int i, uint32_t id)
-{
- vring->vr.used->ring[i].id = virtio_tswap32(vdev, id);
-}
-
-static inline void vring_set_used_ring_len(VirtIODevice *vdev, Vring *vring,
- int i, uint32_t len)
-{
- vring->vr.used->ring[i].len = virtio_tswap32(vdev, len);
-}
-
-static inline uint16_t vring_get_used_flags(VirtIODevice *vdev, Vring *vring)
-{
- return virtio_tswap16(vdev, vring->vr.used->flags);
-}
-
-static inline uint16_t vring_get_avail_flags(VirtIODevice *vdev, Vring *vring)
-{
- return virtio_tswap16(vdev, vring->vr.avail->flags);
-}
-
-static inline void vring_set_used_flags(VirtIODevice *vdev, Vring *vring,
- uint16_t flags)
-{
- vring->vr.used->flags |= virtio_tswap16(vdev, flags);
-}
-
-static inline void vring_clear_used_flags(VirtIODevice *vdev, Vring *vring,
- uint16_t flags)
-{
- vring->vr.used->flags &= virtio_tswap16(vdev, ~flags);
-}
-
-static inline unsigned int vring_get_num(Vring *vring)
-{
- return vring->vr.num;
-}
-
-/* Are there more descriptors available? */
-static inline bool vring_more_avail(VirtIODevice *vdev, Vring *vring)
-{
- return vring_get_avail_idx(vdev, vring) != vring->last_avail_idx;
-}
-
-#endif
diff --git a/qemu/include/hw/virtio/dataplane/vring.h b/qemu/include/hw/virtio/dataplane/vring.h
deleted file mode 100644
index 8d97db9e2..000000000
--- a/qemu/include/hw/virtio/dataplane/vring.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Copyright 2012 Red Hat, Inc. and/or its affiliates
- * Copyright IBM, Corp. 2012
- *
- * Based on Linux 2.6.39 vhost code:
- * Copyright (C) 2009 Red Hat, Inc.
- * Copyright (C) 2006 Rusty Russell IBM Corporation
- *
- * Author: Michael S. Tsirkin <mst@redhat.com>
- * Stefan Hajnoczi <stefanha@redhat.com>
- *
- * Inspiration, some code, and most witty comments come from
- * Documentation/virtual/lguest/lguest.c, by Rusty Russell
- *
- * This work is licensed under the terms of the GNU GPL, version 2.
- */
-
-#ifndef VRING_H
-#define VRING_H
-
-#include "qemu-common.h"
-#include "standard-headers/linux/virtio_ring.h"
-#include "hw/virtio/virtio.h"
-
-typedef struct {
- MemoryRegion *mr; /* memory region containing the vring */
- struct vring vr; /* virtqueue vring mapped to host memory */
- uint16_t last_avail_idx; /* last processed avail ring index */
- uint16_t last_used_idx; /* last processed used ring index */
- uint16_t signalled_used; /* EVENT_IDX state */
- bool signalled_used_valid;
- bool broken; /* was there a fatal error? */
-} Vring;
-
-/* Fail future vring_pop() and vring_push() calls until reset */
-static inline void vring_set_broken(Vring *vring)
-{
- vring->broken = true;
-}
-
-bool vring_setup(Vring *vring, VirtIODevice *vdev, int n);
-void vring_teardown(Vring *vring, VirtIODevice *vdev, int n);
-void vring_disable_notification(VirtIODevice *vdev, Vring *vring);
-bool vring_enable_notification(VirtIODevice *vdev, Vring *vring);
-bool vring_should_notify(VirtIODevice *vdev, Vring *vring);
-int vring_pop(VirtIODevice *vdev, Vring *vring, VirtQueueElement *elem);
-void vring_push(VirtIODevice *vdev, Vring *vring, VirtQueueElement *elem,
- int len);
-
-#endif /* VRING_H */
diff --git a/qemu/include/hw/virtio/vhost-backend.h b/qemu/include/hw/virtio/vhost-backend.h
index e472f2971..95fcc9667 100644
--- a/qemu/include/hw/virtio/vhost-backend.h
+++ b/qemu/include/hw/virtio/vhost-backend.h
@@ -11,6 +11,7 @@
#ifndef VHOST_BACKEND_H_
#define VHOST_BACKEND_H_
+
typedef enum VhostBackendType {
VHOST_BACKEND_TYPE_NONE = 0,
VHOST_BACKEND_TYPE_KERNEL = 1,
@@ -19,17 +20,86 @@ typedef enum VhostBackendType {
} VhostBackendType;
struct vhost_dev;
+struct vhost_log;
+struct vhost_memory;
+struct vhost_vring_file;
+struct vhost_vring_state;
+struct vhost_vring_addr;
+struct vhost_scsi_target;
-typedef int (*vhost_call)(struct vhost_dev *dev, unsigned long int request,
- void *arg);
typedef int (*vhost_backend_init)(struct vhost_dev *dev, void *opaque);
typedef int (*vhost_backend_cleanup)(struct vhost_dev *dev);
+typedef int (*vhost_backend_memslots_limit)(struct vhost_dev *dev);
+
+typedef int (*vhost_net_set_backend_op)(struct vhost_dev *dev,
+ struct vhost_vring_file *file);
+typedef int (*vhost_scsi_set_endpoint_op)(struct vhost_dev *dev,
+ struct vhost_scsi_target *target);
+typedef int (*vhost_scsi_clear_endpoint_op)(struct vhost_dev *dev,
+ struct vhost_scsi_target *target);
+typedef int (*vhost_scsi_get_abi_version_op)(struct vhost_dev *dev,
+ int *version);
+typedef int (*vhost_set_log_base_op)(struct vhost_dev *dev, uint64_t base,
+ struct vhost_log *log);
+typedef int (*vhost_set_mem_table_op)(struct vhost_dev *dev,
+ struct vhost_memory *mem);
+typedef int (*vhost_set_vring_addr_op)(struct vhost_dev *dev,
+ struct vhost_vring_addr *addr);
+typedef int (*vhost_set_vring_endian_op)(struct vhost_dev *dev,
+ struct vhost_vring_state *ring);
+typedef int (*vhost_set_vring_num_op)(struct vhost_dev *dev,
+ struct vhost_vring_state *ring);
+typedef int (*vhost_set_vring_base_op)(struct vhost_dev *dev,
+ struct vhost_vring_state *ring);
+typedef int (*vhost_get_vring_base_op)(struct vhost_dev *dev,
+ struct vhost_vring_state *ring);
+typedef int (*vhost_set_vring_kick_op)(struct vhost_dev *dev,
+ struct vhost_vring_file *file);
+typedef int (*vhost_set_vring_call_op)(struct vhost_dev *dev,
+ struct vhost_vring_file *file);
+typedef int (*vhost_set_features_op)(struct vhost_dev *dev,
+ uint64_t features);
+typedef int (*vhost_get_features_op)(struct vhost_dev *dev,
+ uint64_t *features);
+typedef int (*vhost_set_owner_op)(struct vhost_dev *dev);
+typedef int (*vhost_reset_device_op)(struct vhost_dev *dev);
+typedef int (*vhost_get_vq_index_op)(struct vhost_dev *dev, int idx);
+typedef int (*vhost_set_vring_enable_op)(struct vhost_dev *dev,
+ int enable);
+typedef bool (*vhost_requires_shm_log_op)(struct vhost_dev *dev);
+typedef int (*vhost_migration_done_op)(struct vhost_dev *dev,
+ char *mac_addr);
+typedef bool (*vhost_backend_can_merge_op)(struct vhost_dev *dev,
+ uint64_t start1, uint64_t size1,
+ uint64_t start2, uint64_t size2);
typedef struct VhostOps {
VhostBackendType backend_type;
- vhost_call vhost_call;
vhost_backend_init vhost_backend_init;
vhost_backend_cleanup vhost_backend_cleanup;
+ vhost_backend_memslots_limit vhost_backend_memslots_limit;
+ vhost_net_set_backend_op vhost_net_set_backend;
+ vhost_scsi_set_endpoint_op vhost_scsi_set_endpoint;
+ vhost_scsi_clear_endpoint_op vhost_scsi_clear_endpoint;
+ vhost_scsi_get_abi_version_op vhost_scsi_get_abi_version;
+ vhost_set_log_base_op vhost_set_log_base;
+ vhost_set_mem_table_op vhost_set_mem_table;
+ vhost_set_vring_addr_op vhost_set_vring_addr;
+ vhost_set_vring_endian_op vhost_set_vring_endian;
+ vhost_set_vring_num_op vhost_set_vring_num;
+ vhost_set_vring_base_op vhost_set_vring_base;
+ vhost_get_vring_base_op vhost_get_vring_base;
+ vhost_set_vring_kick_op vhost_set_vring_kick;
+ vhost_set_vring_call_op vhost_set_vring_call;
+ vhost_set_features_op vhost_set_features;
+ vhost_get_features_op vhost_get_features;
+ vhost_set_owner_op vhost_set_owner;
+ vhost_reset_device_op vhost_reset_device;
+ vhost_get_vq_index_op vhost_get_vq_index;
+ vhost_set_vring_enable_op vhost_set_vring_enable;
+ vhost_requires_shm_log_op vhost_requires_shm_log;
+ vhost_migration_done_op vhost_migration_done;
+ vhost_backend_can_merge_op vhost_backend_can_merge;
} VhostOps;
extern const VhostOps user_ops;
diff --git a/qemu/include/hw/virtio/vhost-scsi.h b/qemu/include/hw/virtio/vhost-scsi.h
index 701bfee61..9fd63df12 100644
--- a/qemu/include/hw/virtio/vhost-scsi.h
+++ b/qemu/include/hw/virtio/vhost-scsi.h
@@ -19,37 +19,12 @@
#include "hw/virtio/virtio-scsi.h"
#include "hw/virtio/vhost.h"
-/*
- * Used by QEMU userspace to ensure a consistent vhost-scsi ABI.
- *
- * ABI Rev 0: July 2012 version starting point for v3.6-rc merge candidate +
- * RFC-v2 vhost-scsi userspace. Add GET_ABI_VERSION ioctl usage
- * ABI Rev 1: January 2013. Ignore vhost_tpgt filed in struct vhost_scsi_target.
- * All the targets under vhost_wwpn can be seen and used by guest.
- */
-
-#define VHOST_SCSI_ABI_VERSION 1
-
-/* TODO #include <linux/vhost.h> properly */
-/* For VHOST_SCSI_SET_ENDPOINT/VHOST_SCSI_CLEAR_ENDPOINT ioctl */
-struct vhost_scsi_target {
- int abi_version;
- char vhost_wwpn[224];
- unsigned short vhost_tpgt;
- unsigned short reserved;
-};
-
enum vhost_scsi_vq_list {
VHOST_SCSI_VQ_CONTROL = 0,
VHOST_SCSI_VQ_EVENT = 1,
VHOST_SCSI_VQ_NUM_FIXED = 2,
};
-#define VHOST_VIRTIO 0xAF
-#define VHOST_SCSI_SET_ENDPOINT _IOW(VHOST_VIRTIO, 0x40, struct vhost_scsi_target)
-#define VHOST_SCSI_CLEAR_ENDPOINT _IOW(VHOST_VIRTIO, 0x41, struct vhost_scsi_target)
-#define VHOST_SCSI_GET_ABI_VERSION _IOW(VHOST_VIRTIO, 0x42, int)
-
#define TYPE_VHOST_SCSI "vhost-scsi"
#define VHOST_SCSI(obj) \
OBJECT_CHECK(VHostSCSI, (obj), TYPE_VHOST_SCSI)
diff --git a/qemu/include/hw/virtio/vhost.h b/qemu/include/hw/virtio/vhost.h
index dd510509e..b60d7585b 100644
--- a/qemu/include/hw/virtio/vhost.h
+++ b/qemu/include/hw/virtio/vhost.h
@@ -31,7 +31,8 @@ typedef unsigned long vhost_log_chunk_t;
struct vhost_log {
unsigned long long size;
int refcnt;
- vhost_log_chunk_t log[0];
+ int fd;
+ vhost_log_chunk_t *log;
};
struct vhost_memory;
@@ -44,12 +45,14 @@ struct vhost_dev {
int nvqs;
/* the first virtqueue which would be used by this vhost dev */
int vq_index;
- unsigned long long features;
- unsigned long long acked_features;
- unsigned long long backend_features;
+ uint64_t features;
+ uint64_t acked_features;
+ uint64_t backend_features;
+ uint64_t protocol_features;
+ uint64_t max_queues;
bool started;
bool log_enabled;
- unsigned long long log_size;
+ uint64_t log_size;
Error *migration_blocker;
bool memory_changed;
hwaddr mem_changed_start_addr;
@@ -57,12 +60,12 @@ struct vhost_dev {
const VhostOps *vhost_ops;
void *opaque;
struct vhost_log *log;
+ QLIST_ENTRY(vhost_dev) entry;
};
int vhost_dev_init(struct vhost_dev *hdev, void *opaque,
VhostBackendType backend_type);
void vhost_dev_cleanup(struct vhost_dev *hdev);
-bool vhost_dev_query(struct vhost_dev *hdev, VirtIODevice *vdev);
int vhost_dev_start(struct vhost_dev *hdev, VirtIODevice *vdev);
void vhost_dev_stop(struct vhost_dev *hdev, VirtIODevice *vdev);
int vhost_dev_enable_notifiers(struct vhost_dev *hdev, VirtIODevice *vdev);
@@ -81,4 +84,5 @@ uint64_t vhost_get_features(struct vhost_dev *hdev, const int *feature_bits,
uint64_t features);
void vhost_ack_features(struct vhost_dev *hdev, const int *feature_bits,
uint64_t features);
+bool vhost_has_free_slot(void);
#endif
diff --git a/qemu/include/hw/virtio/virtio-9p.h b/qemu/include/hw/virtio/virtio-9p.h
deleted file mode 100644
index 65789db13..000000000
--- a/qemu/include/hw/virtio/virtio-9p.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Virtio 9p
- *
- * Copyright IBM, Corp. 2010
- *
- * Authors:
- * Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
- *
- * This work is licensed under the terms of the GNU GPL, version 2. See
- * the COPYING file in the top-level directory.
- *
- */
-
-#ifndef QEMU_VIRTIO_9P_DEVICE_H
-#define QEMU_VIRTIO_9P_DEVICE_H
-
-typedef struct V9fsConf
-{
- /* tag name for the device */
- char *tag;
- char *fsdev_id;
-} V9fsConf;
-
-#endif
diff --git a/qemu/include/hw/virtio/virtio-access.h b/qemu/include/hw/virtio/virtio-access.h
index 1ec1dfdb6..8dc84f520 100644
--- a/qemu/include/hw/virtio/virtio-access.h
+++ b/qemu/include/hw/virtio/virtio-access.h
@@ -19,32 +19,19 @@
static inline bool virtio_access_is_big_endian(VirtIODevice *vdev)
{
- if (virtio_has_feature(vdev, VIRTIO_F_VERSION_1)) {
- /* Devices conforming to VIRTIO 1.0 or later are always LE. */
- return false;
- }
#if defined(TARGET_IS_BIENDIAN)
return virtio_is_big_endian(vdev);
#elif defined(TARGET_WORDS_BIGENDIAN)
+ if (virtio_vdev_has_feature(vdev, VIRTIO_F_VERSION_1)) {
+ /* Devices conforming to VIRTIO 1.0 or later are always LE. */
+ return false;
+ }
return true;
#else
return false;
#endif
}
-static inline bool virtio_legacy_is_cross_endian(VirtIODevice *vdev)
-{
-#ifdef TARGET_IS_BIENDIAN
-#ifdef HOST_WORDS_BIGENDIAN
- return !virtio_is_big_endian(vdev);
-#else
- return virtio_is_big_endian(vdev);
-#endif
-#else
- return false;
-#endif
-}
-
static inline uint16_t virtio_lduw_phys(VirtIODevice *vdev, hwaddr pa)
{
if (virtio_access_is_big_endian(vdev)) {
@@ -143,15 +130,6 @@ static inline uint64_t virtio_ldq_p(VirtIODevice *vdev, const void *ptr)
}
}
-static inline bool virtio_needs_swap(VirtIODevice *vdev)
-{
-#ifdef HOST_WORDS_BIGENDIAN
- return virtio_access_is_big_endian(vdev) ? false : true;
-#else
- return virtio_access_is_big_endian(vdev) ? true : false;
-#endif
-}
-
static inline uint16_t virtio_tswap16(VirtIODevice *vdev, uint16_t s)
{
#ifdef HOST_WORDS_BIGENDIAN
diff --git a/qemu/include/hw/virtio/virtio-balloon.h b/qemu/include/hw/virtio/virtio-balloon.h
index 09c2ce4dc..35f62ac11 100644
--- a/qemu/include/hw/virtio/virtio-balloon.h
+++ b/qemu/include/hw/virtio/virtio-balloon.h
@@ -37,7 +37,7 @@ typedef struct VirtIOBalloon {
uint32_t num_pages;
uint32_t actual;
uint64_t stats[VIRTIO_BALLOON_S_NR];
- VirtQueueElement stats_vq_elem;
+ VirtQueueElement *stats_vq_elem;
size_t stats_vq_offset;
QEMUTimer *stats_timer;
int64_t stats_last_update;
diff --git a/qemu/include/hw/virtio/virtio-blk.h b/qemu/include/hw/virtio/virtio-blk.h
index 6bf5905c5..8f2b05651 100644
--- a/qemu/include/hw/virtio/virtio-blk.h
+++ b/qemu/include/hw/virtio/virtio-blk.h
@@ -37,7 +37,6 @@ struct VirtIOBlkConf
char *serial;
uint32_t scsi;
uint32_t config_wce;
- uint32_t data_plane;
uint32_t request_merging;
};
@@ -54,16 +53,15 @@ typedef struct VirtIOBlock {
unsigned short sector_mask;
bool original_wce;
VMChangeStateEntry *change;
- /* Function to push to vq and notify guest */
- void (*complete_request)(struct VirtIOBlockReq *req, unsigned char status);
- Notifier migration_state_notifier;
+ bool dataplane_disabled;
+ bool dataplane_started;
struct VirtIOBlockDataPlane *dataplane;
} VirtIOBlock;
typedef struct VirtIOBlockReq {
+ VirtQueueElement elem;
int64_t sector_num;
VirtIOBlock *dev;
- VirtQueueElement elem;
struct virtio_blk_inhdr *in;
struct virtio_blk_outhdr out;
QEMUIOVector qiov;
@@ -81,12 +79,13 @@ typedef struct MultiReqBuffer {
bool is_write;
} MultiReqBuffer;
-VirtIOBlockReq *virtio_blk_alloc_request(VirtIOBlock *s);
-
+void virtio_blk_init_request(VirtIOBlock *s, VirtIOBlockReq *req);
void virtio_blk_free_request(VirtIOBlockReq *req);
void virtio_blk_handle_request(VirtIOBlockReq *req, MultiReqBuffer *mrb);
void virtio_blk_submit_multireq(BlockBackend *blk, MultiReqBuffer *mrb);
+void virtio_blk_handle_vq(VirtIOBlock *s, VirtQueue *vq);
+
#endif
diff --git a/qemu/include/hw/virtio/virtio-bus.h b/qemu/include/hw/virtio/virtio-bus.h
index 8811415fa..3f2c1363d 100644
--- a/qemu/include/hw/virtio/virtio-bus.h
+++ b/qemu/include/hw/virtio/virtio-bus.h
@@ -44,9 +44,12 @@ typedef struct VirtioBusClass {
void (*notify)(DeviceState *d, uint16_t vector);
void (*save_config)(DeviceState *d, QEMUFile *f);
void (*save_queue)(DeviceState *d, int n, QEMUFile *f);
+ void (*save_extra_state)(DeviceState *d, QEMUFile *f);
int (*load_config)(DeviceState *d, QEMUFile *f);
int (*load_queue)(DeviceState *d, int n, QEMUFile *f);
int (*load_done)(DeviceState *d, QEMUFile *f);
+ int (*load_extra_state)(DeviceState *d, QEMUFile *f);
+ bool (*has_extra_state)(DeviceState *d);
bool (*query_guest_notifiers)(DeviceState *d);
int (*set_guest_notifiers)(DeviceState *d, int nvqs, bool assign);
int (*set_host_notifier)(DeviceState *d, int n, bool assigned);
@@ -57,6 +60,11 @@ typedef struct VirtioBusClass {
*/
void (*device_plugged)(DeviceState *d, Error **errp);
/*
+ * Re-evaluate setup after feature bits have been validated
+ * by the device backend.
+ */
+ void (*post_plugged)(DeviceState *d, Error **errp);
+ /*
* transport independent exit function.
* This is called by virtio-bus just before the device is unplugged.
*/
diff --git a/qemu/include/hw/virtio/virtio-gpu.h b/qemu/include/hw/virtio/virtio-gpu.h
index 889676147..13b0ab084 100644
--- a/qemu/include/hw/virtio/virtio-gpu.h
+++ b/qemu/include/hw/virtio/virtio-gpu.h
@@ -56,8 +56,19 @@ struct virtio_gpu_requested_state {
int x, y;
};
+enum virtio_gpu_conf_flags {
+ VIRTIO_GPU_FLAG_VIRGL_ENABLED = 1,
+ VIRTIO_GPU_FLAG_STATS_ENABLED,
+};
+
+#define virtio_gpu_virgl_enabled(_cfg) \
+ (_cfg.flags & (1 << VIRTIO_GPU_FLAG_VIRGL_ENABLED))
+#define virtio_gpu_stats_enabled(_cfg) \
+ (_cfg.flags & (1 << VIRTIO_GPU_FLAG_STATS_ENABLED))
+
struct virtio_gpu_conf {
uint32_t max_outputs;
+ uint32_t flags;
};
struct virtio_gpu_ctrl_command {
@@ -65,6 +76,7 @@ struct virtio_gpu_ctrl_command {
VirtQueue *vq;
struct virtio_gpu_ctrl_hdr cmd_hdr;
uint32_t error;
+ bool waiting;
bool finished;
QTAILQ_ENTRY(virtio_gpu_ctrl_command) next;
};
@@ -83,6 +95,7 @@ typedef struct VirtIOGPU {
DeviceState *qdev;
QTAILQ_HEAD(, virtio_gpu_simple_resource) reslist;
+ QTAILQ_HEAD(, virtio_gpu_ctrl_command) cmdq;
QTAILQ_HEAD(, virtio_gpu_ctrl_command) fenceq;
struct virtio_gpu_scanout scanout[VIRTIO_GPU_MAX_SCANOUT];
@@ -92,11 +105,14 @@ typedef struct VirtIOGPU {
int enabled_output_bitmask;
struct virtio_gpu_config virtio_config;
+ bool use_virgl_renderer;
+ bool renderer_inited;
+ bool renderer_blocked;
QEMUTimer *fence_poll;
QEMUTimer *print_stats;
+ uint32_t inflight;
struct {
- uint32_t inflight;
uint32_t max_inflight;
uint32_t requests;
uint32_t req_3d;
@@ -138,5 +154,13 @@ int virtio_gpu_create_mapping_iov(struct virtio_gpu_resource_attach_backing *ab,
struct virtio_gpu_ctrl_command *cmd,
struct iovec **iov);
void virtio_gpu_cleanup_mapping_iov(struct iovec *iov, uint32_t count);
+void virtio_gpu_process_cmdq(VirtIOGPU *g);
+
+/* virtio-gpu-3d.c */
+void virtio_gpu_virgl_process_cmd(VirtIOGPU *g,
+ struct virtio_gpu_ctrl_command *cmd);
+void virtio_gpu_virgl_fence_poll(VirtIOGPU *g);
+void virtio_gpu_virgl_reset(VirtIOGPU *g);
+int virtio_gpu_virgl_init(VirtIOGPU *g);
#endif
diff --git a/qemu/include/hw/virtio/virtio-input.h b/qemu/include/hw/virtio/virtio-input.h
index af1c207ab..bddbd4b28 100644
--- a/qemu/include/hw/virtio/virtio-input.h
+++ b/qemu/include/hw/virtio/virtio-input.h
@@ -13,20 +13,6 @@ typedef struct virtio_input_absinfo virtio_input_absinfo;
typedef struct virtio_input_config virtio_input_config;
typedef struct virtio_input_event virtio_input_event;
-#if defined(HOST_WORDS_BIGENDIAN)
-# define const_le32(_x) \
- (((_x & 0x000000ffU) << 24) | \
- ((_x & 0x0000ff00U) << 8) | \
- ((_x & 0x00ff0000U) >> 8) | \
- ((_x & 0xff000000U) >> 24))
-# define const_le16(_x) \
- (((_x & 0x00ff) << 8) | \
- ((_x & 0xff00) >> 8))
-#else
-# define const_le32(_x) (_x)
-# define const_le16(_x) (_x)
-#endif
-
/* ----------------------------------------------------------------- */
/* qemu internals */
@@ -111,6 +97,9 @@ struct VirtIOInputHost {
void virtio_input_send(VirtIOInput *vinput, virtio_input_event *event);
void virtio_input_init_config(VirtIOInput *vinput,
virtio_input_config *config);
+virtio_input_config *virtio_input_find_config(VirtIOInput *vinput,
+ uint8_t select,
+ uint8_t subsel);
void virtio_input_add_config(VirtIOInput *vinput,
virtio_input_config *config);
void virtio_input_idstr_config(VirtIOInput *vinput,
diff --git a/qemu/include/hw/virtio/virtio-net.h b/qemu/include/hw/virtio/virtio-net.h
index 60b11d5c2..0cabdb682 100644
--- a/qemu/include/hw/virtio/virtio-net.h
+++ b/qemu/include/hw/virtio/virtio-net.h
@@ -47,8 +47,7 @@ typedef struct VirtIONetQueue {
QEMUBH *tx_bh;
int tx_waiting;
struct {
- VirtQueueElement elem;
- ssize_t len;
+ VirtQueueElement *elem;
} async_tx;
struct VirtIONet *n;
} VirtIONetQueue;
@@ -95,6 +94,7 @@ typedef struct VirtIONet {
uint64_t curr_guest_offloads;
QEMUTimer *announce_timer;
int announce_counter;
+ bool needs_vnet_hdr_swap;
} VirtIONet;
void virtio_net_set_netclient_name(VirtIONet *n, const char *name,
diff --git a/qemu/include/hw/virtio/virtio-scsi.h b/qemu/include/hw/virtio/virtio-scsi.h
index 088fe9f4b..ba2f5ce07 100644
--- a/qemu/include/hw/virtio/virtio-scsi.h
+++ b/qemu/include/hw/virtio/virtio-scsi.h
@@ -22,7 +22,6 @@
#include "hw/pci/pci.h"
#include "hw/scsi/scsi.h"
#include "sysemu/iothread.h"
-#include "hw/virtio/dataplane/vring.h"
#define TYPE_VIRTIO_SCSI_COMMON "virtio-scsi-common"
#define VIRTIO_SCSI_COMMON(obj) \
@@ -58,13 +57,6 @@ struct VirtIOSCSIConf {
struct VirtIOSCSI;
-typedef struct {
- struct VirtIOSCSI *parent;
- Vring vring;
- EventNotifier host_notifier;
- EventNotifier guest_notifier;
-} VirtIOSCSIVring;
-
typedef struct VirtIOSCSICommon {
VirtIODevice parent_obj;
VirtIOSCSIConf conf;
@@ -76,6 +68,13 @@ typedef struct VirtIOSCSICommon {
VirtQueue **cmd_vqs;
} VirtIOSCSICommon;
+typedef struct VirtIOSCSIBlkChangeNotifier {
+ Notifier n;
+ struct VirtIOSCSI *s;
+ SCSIDevice *sd;
+ QTAILQ_ENTRY(VirtIOSCSIBlkChangeNotifier) next;
+} VirtIOSCSIBlkChangeNotifier;
+
typedef struct VirtIOSCSI {
VirtIOSCSICommon parent_obj;
@@ -86,37 +85,29 @@ typedef struct VirtIOSCSI {
/* Fields for dataplane below */
AioContext *ctx; /* one iothread per virtio-scsi-pci for now */
- /* Vring is used instead of vq in dataplane code, because of the underlying
- * memory layer thread safety */
- VirtIOSCSIVring *ctrl_vring;
- VirtIOSCSIVring *event_vring;
- VirtIOSCSIVring **cmd_vrings;
+ QTAILQ_HEAD(, VirtIOSCSIBlkChangeNotifier) insert_notifiers;
+ QTAILQ_HEAD(, VirtIOSCSIBlkChangeNotifier) remove_notifiers;
+
bool dataplane_started;
bool dataplane_starting;
bool dataplane_stopping;
- bool dataplane_disabled;
bool dataplane_fenced;
Error *blocker;
- Notifier migration_state_notifier;
uint32_t host_features;
} VirtIOSCSI;
typedef struct VirtIOSCSIReq {
+ /* Note:
+ * - fields up to resp_iov are initialized by virtio_scsi_init_req;
+ * - fields starting at vring are zeroed by virtio_scsi_init_req.
+ * */
+ VirtQueueElement elem;
+
VirtIOSCSI *dev;
VirtQueue *vq;
QEMUSGList qsgl;
QEMUIOVector resp_iov;
- /* Note:
- * - fields before elem are initialized by virtio_scsi_init_req;
- * - elem is uninitialized at the time of allocation.
- * - fields after elem are zeroed by virtio_scsi_init_req.
- * */
-
- VirtQueueElement elem;
- /* Set by dataplane code. */
- VirtIOSCSIVring *vring;
-
union {
/* Used for two-stage request submission */
QTAILQ_ENTRY(VirtIOSCSIReq) next;
@@ -148,10 +139,10 @@ void virtio_scsi_common_realize(DeviceState *dev, Error **errp,
HandleOutput cmd);
void virtio_scsi_common_unrealize(DeviceState *dev, Error **errp);
-void virtio_scsi_handle_ctrl_req(VirtIOSCSI *s, VirtIOSCSIReq *req);
-bool virtio_scsi_handle_cmd_req_prepare(VirtIOSCSI *s, VirtIOSCSIReq *req);
-void virtio_scsi_handle_cmd_req_submit(VirtIOSCSI *s, VirtIOSCSIReq *req);
-VirtIOSCSIReq *virtio_scsi_init_req(VirtIOSCSI *s, VirtQueue *vq);
+void virtio_scsi_handle_event_vq(VirtIOSCSI *s, VirtQueue *vq);
+void virtio_scsi_handle_cmd_vq(VirtIOSCSI *s, VirtQueue *vq);
+void virtio_scsi_handle_ctrl_vq(VirtIOSCSI *s, VirtQueue *vq);
+void virtio_scsi_init_req(VirtIOSCSI *s, VirtQueue *vq, VirtIOSCSIReq *req);
void virtio_scsi_free_req(VirtIOSCSIReq *req);
void virtio_scsi_push_event(VirtIOSCSI *s, SCSIDevice *dev,
uint32_t event, uint32_t reason);
@@ -159,8 +150,6 @@ void virtio_scsi_push_event(VirtIOSCSI *s, SCSIDevice *dev,
void virtio_scsi_set_iothread(VirtIOSCSI *s, IOThread *iothread);
void virtio_scsi_dataplane_start(VirtIOSCSI *s);
void virtio_scsi_dataplane_stop(VirtIOSCSI *s);
-void virtio_scsi_vring_push_notify(VirtIOSCSIReq *req);
-VirtIOSCSIReq *virtio_scsi_pop_req_vring(VirtIOSCSI *s,
- VirtIOSCSIVring *vring);
+void virtio_scsi_dataplane_notify(VirtIODevice *vdev, VirtIOSCSIReq *req);
#endif /* _QEMU_VIRTIO_SCSI_H */
diff --git a/qemu/include/hw/virtio/virtio-serial.h b/qemu/include/hw/virtio/virtio-serial.h
index 527d0bf62..12a55a19e 100644
--- a/qemu/include/hw/virtio/virtio-serial.h
+++ b/qemu/include/hw/virtio/virtio-serial.h
@@ -122,7 +122,7 @@ struct VirtIOSerialPort {
* element popped and continue consuming it once the backend
* becomes writable again.
*/
- VirtQueueElement elem;
+ VirtQueueElement *elem;
/*
* The index and the offset into the iov buffer that was popped in
diff --git a/qemu/include/hw/virtio/virtio.h b/qemu/include/hw/virtio/virtio.h
index cccae89d8..6a37065c2 100644
--- a/qemu/include/hw/virtio/virtio.h
+++ b/qemu/include/hw/virtio/virtio.h
@@ -46,10 +46,10 @@ typedef struct VirtQueueElement
unsigned int index;
unsigned int out_num;
unsigned int in_num;
- hwaddr in_addr[VIRTQUEUE_MAX_SIZE];
- hwaddr out_addr[VIRTQUEUE_MAX_SIZE];
- struct iovec in_sg[VIRTQUEUE_MAX_SIZE];
- struct iovec out_sg[VIRTQUEUE_MAX_SIZE];
+ hwaddr *in_addr;
+ hwaddr *out_addr;
+ struct iovec *in_sg;
+ struct iovec *out_sg;
} VirtQueueElement;
#define VIRTIO_QUEUE_MAX 1024
@@ -90,6 +90,7 @@ struct VirtIODevice
VMChangeStateEntry *vmstate;
char *bus_name;
uint8_t device_endian;
+ bool use_guest_notifier_mask;
QLIST_HEAD(, VirtQueue) *vector_queues;
};
@@ -143,21 +144,26 @@ VirtQueue *virtio_add_queue(VirtIODevice *vdev, int queue_size,
void virtio_del_queue(VirtIODevice *vdev, int n);
+void *virtqueue_alloc_element(size_t sz, unsigned out_num, unsigned in_num);
void virtqueue_push(VirtQueue *vq, const VirtQueueElement *elem,
unsigned int len);
void virtqueue_flush(VirtQueue *vq, unsigned int count);
+void virtqueue_discard(VirtQueue *vq, const VirtQueueElement *elem,
+ unsigned int len);
void virtqueue_fill(VirtQueue *vq, const VirtQueueElement *elem,
unsigned int len, unsigned int idx);
-void virtqueue_map_sg(struct iovec *sg, hwaddr *addr,
- size_t num_sg, int is_write);
-int virtqueue_pop(VirtQueue *vq, VirtQueueElement *elem);
+void virtqueue_map(VirtQueueElement *elem);
+void *virtqueue_pop(VirtQueue *vq, size_t sz);
+void *qemu_get_virtqueue_element(QEMUFile *f, size_t sz);
+void qemu_put_virtqueue_element(QEMUFile *f, VirtQueueElement *elem);
int virtqueue_avail_bytes(VirtQueue *vq, unsigned int in_bytes,
unsigned int out_bytes);
void virtqueue_get_avail_bytes(VirtQueue *vq, unsigned int *in_bytes,
unsigned int *out_bytes,
unsigned max_in_bytes, unsigned max_out_bytes);
+bool virtio_should_notify(VirtIODevice *vdev, VirtQueue *vq);
void virtio_notify(VirtIODevice *vdev, VirtQueue *vq);
void virtio_save(VirtIODevice *vdev, QEMUFile *f);
@@ -244,7 +250,9 @@ void virtio_queue_set_guest_notifier_fd_handler(VirtQueue *vq, bool assign,
EventNotifier *virtio_queue_get_host_notifier(VirtQueue *vq);
void virtio_queue_set_host_notifier_fd_handler(VirtQueue *vq, bool assign,
bool set_handler);
-void virtio_queue_notify_vq(VirtQueue *vq);
+void virtio_queue_aio_set_host_notifier_handler(VirtQueue *vq, AioContext *ctx,
+ void (*fn)(VirtIODevice *,
+ VirtQueue *));
void virtio_irq(VirtQueue *vq);
VirtQueue *virtio_vector_first_queue(VirtIODevice *vdev, uint16_t vector);
VirtQueue *virtio_vector_next_queue(VirtQueue *vq);
@@ -261,26 +269,27 @@ static inline void virtio_clear_feature(uint64_t *features, unsigned int fbit)
*features &= ~(1ULL << fbit);
}
-static inline bool __virtio_has_feature(uint64_t features, unsigned int fbit)
+static inline bool virtio_has_feature(uint64_t features, unsigned int fbit)
{
assert(fbit < 64);
return !!(features & (1ULL << fbit));
}
-static inline bool virtio_has_feature(VirtIODevice *vdev, unsigned int fbit)
+static inline bool virtio_vdev_has_feature(VirtIODevice *vdev,
+ unsigned int fbit)
{
- return __virtio_has_feature(vdev->guest_features, fbit);
+ return virtio_has_feature(vdev->guest_features, fbit);
}
static inline bool virtio_host_has_feature(VirtIODevice *vdev,
unsigned int fbit)
{
- return __virtio_has_feature(vdev->host_features, fbit);
+ return virtio_has_feature(vdev->host_features, fbit);
}
static inline bool virtio_is_big_endian(VirtIODevice *vdev)
{
- if (!virtio_has_feature(vdev, VIRTIO_F_VERSION_1)) {
+ if (!virtio_vdev_has_feature(vdev, VIRTIO_F_VERSION_1)) {
assert(vdev->device_endian != VIRTIO_DEVICE_ENDIAN_UNKNOWN);
return vdev->device_endian == VIRTIO_DEVICE_ENDIAN_BIG;
}
diff --git a/qemu/include/hw/xen/xen.h b/qemu/include/hw/xen/xen.h
index 4356af456..6eb815aac 100644
--- a/qemu/include/hw/xen/xen.h
+++ b/qemu/include/hw/xen/xen.h
@@ -6,7 +6,6 @@
* must not depend on any xen headers being present in
* /usr/include/xen, so it can be included unconditionally.
*/
-#include <inttypes.h>
#include "hw/irq.h"
#include "qemu-common.h"
@@ -32,23 +31,19 @@ int xen_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num);
void xen_piix3_set_irq(void *opaque, int irq_num, int level);
void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len);
void xen_hvm_inject_msi(uint64_t addr, uint32_t data);
+int xen_is_pirq_msi(uint32_t msi_data);
qemu_irq *xen_interrupt_controller_init(void);
void xenstore_store_pv_console_info(int i, struct CharDriverState *chr);
#if defined(NEED_CPU_H) && !defined(CONFIG_USER_ONLY)
-int xen_hvm_init(ram_addr_t *below_4g_mem_size, ram_addr_t *above_4g_mem_size,
- MemoryRegion **ram_memory);
+void xen_hvm_init(PCMachineState *pcms, MemoryRegion **ram_memory);
void xen_ram_alloc(ram_addr_t ram_addr, ram_addr_t size,
- struct MemoryRegion *mr);
+ struct MemoryRegion *mr, Error **errp);
void xen_modified_memory(ram_addr_t start, ram_addr_t length);
#endif
void xen_register_framebuffer(struct MemoryRegion *mr);
-#if defined(CONFIG_XEN) && CONFIG_XEN_CTRL_INTERFACE_VERSION < 400
-# define HVM_MAX_VCPUS 32
-#endif
-
#endif /* QEMU_HW_XEN_H */
diff --git a/qemu/include/hw/xen/xen_backend.h b/qemu/include/hw/xen/xen_backend.h
index 3b4125e39..c839eeb48 100644
--- a/qemu/include/hw/xen/xen_backend.h
+++ b/qemu/include/hw/xen/xen_backend.h
@@ -46,8 +46,8 @@ struct XenDevice {
int remote_port;
int local_port;
- XenEvtchn evtchndev;
- XenGnttab gnttabdev;
+ xenevtchn_handle *evtchndev;
+ xengnttab_handle *gnttabdev;
struct XenDevOps *ops;
QTAILQ_ENTRY(XenDevice) next;
@@ -56,7 +56,8 @@ struct XenDevice {
/* ------------------------------------------------------------- */
/* variables */
-extern XenXC xen_xc;
+extern xc_interface *xen_xc;
+extern xenforeignmemory_handle *xen_fmem;
extern struct xs_handle *xenstore;
extern const char *xen_protocol;
diff --git a/qemu/include/hw/xen/xen_common.h b/qemu/include/hw/xen/xen_common.h
index ed5fd3e1a..bd65e6705 100644
--- a/qemu/include/hw/xen/xen_common.h
+++ b/qemu/include/hw/xen/xen_common.h
@@ -1,17 +1,19 @@
#ifndef QEMU_HW_XEN_COMMON_H
#define QEMU_HW_XEN_COMMON_H 1
-#include "config-host.h"
-#include <stddef.h>
-#include <inttypes.h>
+
+/*
+ * If we have new enough libxenctrl then we do not want/need these compat
+ * interfaces, despite what the user supplied cflags might say. They
+ * must be undefined before including xenctrl.h
+ */
+#undef XC_WANT_COMPAT_EVTCHN_API
+#undef XC_WANT_COMPAT_GNTTAB_API
+#undef XC_WANT_COMPAT_MAP_FOREIGN_API
#include <xenctrl.h>
-#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 420
-# include <xs.h>
-#else
-# include <xenstore.h>
-#endif
+#include <xenstore.h>
#include <xen/io/xenbus.h>
#include "hw/hw.h"
@@ -21,144 +23,54 @@
#include "trace.h"
/*
- * We don't support Xen prior to 3.3.0.
+ * We don't support Xen prior to 4.2.0.
*/
-/* Xen before 4.0 */
-#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 400
-static inline void *xc_map_foreign_bulk(int xc_handle, uint32_t dom, int prot,
- xen_pfn_t *arr, int *err,
- unsigned int num)
-{
- return xc_map_foreign_batch(xc_handle, dom, prot, arr, num);
-}
-#endif
-
-
-/* Xen before 4.1 */
-#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 410
-
-typedef int XenXC;
-typedef int XenEvtchn;
-typedef int XenGnttab;
-
-# define XC_INTERFACE_FMT "%i"
-# define XC_HANDLER_INITIAL_VALUE -1
-
-static inline XenEvtchn xen_xc_evtchn_open(void *logger,
- unsigned int open_flags)
-{
- return xc_evtchn_open();
-}
-
-static inline XenGnttab xen_xc_gnttab_open(void *logger,
- unsigned int open_flags)
-{
- return xc_gnttab_open();
-}
-
-static inline XenXC xen_xc_interface_open(void *logger, void *dombuild_logger,
- unsigned int open_flags)
-{
- return xc_interface_open();
-}
-
-static inline int xc_fd(int xen_xc)
-{
- return xen_xc;
-}
-
-
-static inline int xc_domain_populate_physmap_exact
- (XenXC xc_handle, uint32_t domid, unsigned long nr_extents,
- unsigned int extent_order, unsigned int mem_flags, xen_pfn_t *extent_start)
-{
- return xc_domain_memory_populate_physmap
- (xc_handle, domid, nr_extents, extent_order, mem_flags, extent_start);
-}
-
-static inline int xc_domain_add_to_physmap(int xc_handle, uint32_t domid,
- unsigned int space, unsigned long idx,
- xen_pfn_t gpfn)
-{
- struct xen_add_to_physmap xatp = {
- .domid = domid,
- .space = space,
- .idx = idx,
- .gpfn = gpfn,
- };
-
- return xc_memory_op(xc_handle, XENMEM_add_to_physmap, &xatp);
-}
-
-static inline struct xs_handle *xs_open(unsigned long flags)
-{
- return xs_daemon_open();
-}
-
-static inline void xs_close(struct xs_handle *xsh)
-{
- if (xsh != NULL) {
- xs_daemon_close(xsh);
- }
-}
+/* Xen 4.2 thru 4.6 */
+#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 471
+typedef xc_interface xenforeignmemory_handle;
+typedef xc_evtchn xenevtchn_handle;
+typedef xc_gnttab xengnttab_handle;
-/* Xen 4.1 */
-#else
+#define xenevtchn_open(l, f) xc_evtchn_open(l, f);
+#define xenevtchn_close(h) xc_evtchn_close(h)
+#define xenevtchn_fd(h) xc_evtchn_fd(h)
+#define xenevtchn_pending(h) xc_evtchn_pending(h)
+#define xenevtchn_notify(h, p) xc_evtchn_notify(h, p)
+#define xenevtchn_bind_interdomain(h, d, p) xc_evtchn_bind_interdomain(h, d, p)
+#define xenevtchn_unmask(h, p) xc_evtchn_unmask(h, p)
+#define xenevtchn_unbind(h, p) xc_evtchn_unbind(h, p)
-typedef xc_interface *XenXC;
-typedef xc_evtchn *XenEvtchn;
-typedef xc_gnttab *XenGnttab;
+#define xengnttab_open(l, f) xc_gnttab_open(l, f)
+#define xengnttab_close(h) xc_gnttab_close(h)
+#define xengnttab_set_max_grants(h, n) xc_gnttab_set_max_grants(h, n)
+#define xengnttab_map_grant_ref(h, d, r, p) xc_gnttab_map_grant_ref(h, d, r, p)
+#define xengnttab_unmap(h, a, n) xc_gnttab_munmap(h, a, n)
+#define xengnttab_map_grant_refs(h, c, d, r, p) \
+ xc_gnttab_map_grant_refs(h, c, d, r, p)
-# define XC_INTERFACE_FMT "%p"
-# define XC_HANDLER_INITIAL_VALUE NULL
+#define xenforeignmemory_open(l, f) xen_xc
-static inline XenEvtchn xen_xc_evtchn_open(void *logger,
- unsigned int open_flags)
+static inline void *xenforeignmemory_map(xc_interface *h, uint32_t dom,
+ int prot, size_t pages,
+ const xen_pfn_t arr[/*pages*/],
+ int err[/*pages*/])
{
- return xc_evtchn_open(logger, open_flags);
+ if (err)
+ return xc_map_foreign_bulk(h, dom, prot, arr, err, pages);
+ else
+ return xc_map_foreign_pages(h, dom, prot, arr, pages);
}
-static inline XenGnttab xen_xc_gnttab_open(void *logger,
- unsigned int open_flags)
-{
- return xc_gnttab_open(logger, open_flags);
-}
+#define xenforeignmemory_unmap(h, p, s) munmap(p, s * XC_PAGE_SIZE)
-static inline XenXC xen_xc_interface_open(void *logger, void *dombuild_logger,
- unsigned int open_flags)
-{
- return xc_interface_open(logger, dombuild_logger, open_flags);
-}
+#else /* CONFIG_XEN_CTRL_INTERFACE_VERSION >= 471 */
-/* FIXME There is now way to have the xen fd */
-static inline int xc_fd(xc_interface *xen_xc)
-{
- return -1;
-}
-#endif
+#include <xenevtchn.h>
+#include <xengnttab.h>
+#include <xenforeignmemory.h>
-/* Xen before 4.2 */
-#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 420
-static inline int xen_xc_hvm_inject_msi(XenXC xen_xc, domid_t dom,
- uint64_t addr, uint32_t data)
-{
- return -ENOSYS;
-}
-/* The followings are only to compile op_discard related code on older
- * Xen releases. */
-#define BLKIF_OP_DISCARD 5
-struct blkif_request_discard {
- uint64_t nr_sectors;
- uint64_t sector_number;
-};
-#else
-static inline int xen_xc_hvm_inject_msi(XenXC xen_xc, domid_t dom,
- uint64_t addr, uint32_t data)
-{
- return xc_hvm_inject_msi(xen_xc, dom, addr, data);
-}
#endif
void destroy_hvm_domain(bool reboot);
@@ -167,7 +79,7 @@ void destroy_hvm_domain(bool reboot);
void xen_shutdown_fatal_error(const char *fmt, ...) GCC_FMT_ATTR(1, 2);
#ifdef HVM_PARAM_VMPORT_REGS_PFN
-static inline int xen_get_vmport_regs_pfn(XenXC xc, domid_t dom,
+static inline int xen_get_vmport_regs_pfn(xc_interface *xc, domid_t dom,
xen_pfn_t *vmport_regs_pfn)
{
int rc;
@@ -179,13 +91,22 @@ static inline int xen_get_vmport_regs_pfn(XenXC xc, domid_t dom,
return rc;
}
#else
-static inline int xen_get_vmport_regs_pfn(XenXC xc, domid_t dom,
+static inline int xen_get_vmport_regs_pfn(xc_interface *xc, domid_t dom,
xen_pfn_t *vmport_regs_pfn)
{
return -ENOSYS;
}
#endif
+/* Xen before 4.6 */
+#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 460
+
+#ifndef HVM_IOREQSRV_BUFIOREQ_ATOMIC
+#define HVM_IOREQSRV_BUFIOREQ_ATOMIC 2
+#endif
+
+#endif
+
/* Xen before 4.5 */
#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 450
@@ -197,54 +118,54 @@ static inline int xen_get_vmport_regs_pfn(XenXC xc, domid_t dom,
typedef uint16_t ioservid_t;
-static inline void xen_map_memory_section(XenXC xc, domid_t dom,
+static inline void xen_map_memory_section(xc_interface *xc, domid_t dom,
ioservid_t ioservid,
MemoryRegionSection *section)
{
}
-static inline void xen_unmap_memory_section(XenXC xc, domid_t dom,
+static inline void xen_unmap_memory_section(xc_interface *xc, domid_t dom,
ioservid_t ioservid,
MemoryRegionSection *section)
{
}
-static inline void xen_map_io_section(XenXC xc, domid_t dom,
+static inline void xen_map_io_section(xc_interface *xc, domid_t dom,
ioservid_t ioservid,
MemoryRegionSection *section)
{
}
-static inline void xen_unmap_io_section(XenXC xc, domid_t dom,
+static inline void xen_unmap_io_section(xc_interface *xc, domid_t dom,
ioservid_t ioservid,
MemoryRegionSection *section)
{
}
-static inline void xen_map_pcidev(XenXC xc, domid_t dom,
+static inline void xen_map_pcidev(xc_interface *xc, domid_t dom,
ioservid_t ioservid,
PCIDevice *pci_dev)
{
}
-static inline void xen_unmap_pcidev(XenXC xc, domid_t dom,
+static inline void xen_unmap_pcidev(xc_interface *xc, domid_t dom,
ioservid_t ioservid,
PCIDevice *pci_dev)
{
}
-static inline int xen_create_ioreq_server(XenXC xc, domid_t dom,
+static inline int xen_create_ioreq_server(xc_interface *xc, domid_t dom,
ioservid_t *ioservid)
{
return 0;
}
-static inline void xen_destroy_ioreq_server(XenXC xc, domid_t dom,
+static inline void xen_destroy_ioreq_server(xc_interface *xc, domid_t dom,
ioservid_t ioservid)
{
}
-static inline int xen_get_ioreq_server_info(XenXC xc, domid_t dom,
+static inline int xen_get_ioreq_server_info(xc_interface *xc, domid_t dom,
ioservid_t ioservid,
xen_pfn_t *ioreq_pfn,
xen_pfn_t *bufioreq_pfn,
@@ -281,7 +202,7 @@ static inline int xen_get_ioreq_server_info(XenXC xc, domid_t dom,
return 0;
}
-static inline int xen_set_ioreq_server_state(XenXC xc, domid_t dom,
+static inline int xen_set_ioreq_server_state(xc_interface *xc, domid_t dom,
ioservid_t ioservid,
bool enable)
{
@@ -291,7 +212,7 @@ static inline int xen_set_ioreq_server_state(XenXC xc, domid_t dom,
/* Xen 4.5 */
#else
-static inline void xen_map_memory_section(XenXC xc, domid_t dom,
+static inline void xen_map_memory_section(xc_interface *xc, domid_t dom,
ioservid_t ioservid,
MemoryRegionSection *section)
{
@@ -304,7 +225,7 @@ static inline void xen_map_memory_section(XenXC xc, domid_t dom,
start_addr, end_addr);
}
-static inline void xen_unmap_memory_section(XenXC xc, domid_t dom,
+static inline void xen_unmap_memory_section(xc_interface *xc, domid_t dom,
ioservid_t ioservid,
MemoryRegionSection *section)
{
@@ -317,7 +238,7 @@ static inline void xen_unmap_memory_section(XenXC xc, domid_t dom,
start_addr, end_addr);
}
-static inline void xen_map_io_section(XenXC xc, domid_t dom,
+static inline void xen_map_io_section(xc_interface *xc, domid_t dom,
ioservid_t ioservid,
MemoryRegionSection *section)
{
@@ -330,7 +251,7 @@ static inline void xen_map_io_section(XenXC xc, domid_t dom,
start_addr, end_addr);
}
-static inline void xen_unmap_io_section(XenXC xc, domid_t dom,
+static inline void xen_unmap_io_section(xc_interface *xc, domid_t dom,
ioservid_t ioservid,
MemoryRegionSection *section)
{
@@ -343,7 +264,7 @@ static inline void xen_unmap_io_section(XenXC xc, domid_t dom,
start_addr, end_addr);
}
-static inline void xen_map_pcidev(XenXC xc, domid_t dom,
+static inline void xen_map_pcidev(xc_interface *xc, domid_t dom,
ioservid_t ioservid,
PCIDevice *pci_dev)
{
@@ -355,7 +276,7 @@ static inline void xen_map_pcidev(XenXC xc, domid_t dom,
PCI_FUNC(pci_dev->devfn));
}
-static inline void xen_unmap_pcidev(XenXC xc, domid_t dom,
+static inline void xen_unmap_pcidev(xc_interface *xc, domid_t dom,
ioservid_t ioservid,
PCIDevice *pci_dev)
{
@@ -367,10 +288,11 @@ static inline void xen_unmap_pcidev(XenXC xc, domid_t dom,
PCI_FUNC(pci_dev->devfn));
}
-static inline int xen_create_ioreq_server(XenXC xc, domid_t dom,
+static inline int xen_create_ioreq_server(xc_interface *xc, domid_t dom,
ioservid_t *ioservid)
{
- int rc = xc_hvm_create_ioreq_server(xc, dom, 1, ioservid);
+ int rc = xc_hvm_create_ioreq_server(xc, dom, HVM_IOREQSRV_BUFIOREQ_ATOMIC,
+ ioservid);
if (rc == 0) {
trace_xen_ioreq_server_create(*ioservid);
@@ -379,14 +301,14 @@ static inline int xen_create_ioreq_server(XenXC xc, domid_t dom,
return rc;
}
-static inline void xen_destroy_ioreq_server(XenXC xc, domid_t dom,
+static inline void xen_destroy_ioreq_server(xc_interface *xc, domid_t dom,
ioservid_t ioservid)
{
trace_xen_ioreq_server_destroy(ioservid);
xc_hvm_destroy_ioreq_server(xc, dom, ioservid);
}
-static inline int xen_get_ioreq_server_info(XenXC xc, domid_t dom,
+static inline int xen_get_ioreq_server_info(xc_interface *xc, domid_t dom,
ioservid_t ioservid,
xen_pfn_t *ioreq_pfn,
xen_pfn_t *bufioreq_pfn,
@@ -397,7 +319,7 @@ static inline int xen_get_ioreq_server_info(XenXC xc, domid_t dom,
bufioreq_evtchn);
}
-static inline int xen_set_ioreq_server_state(XenXC xc, domid_t dom,
+static inline int xen_set_ioreq_server_state(xc_interface *xc, domid_t dom,
ioservid_t ioservid,
bool enable)
{
@@ -407,4 +329,44 @@ static inline int xen_set_ioreq_server_state(XenXC xc, domid_t dom,
#endif
+#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 460
+static inline int xen_xc_domain_add_to_physmap(xc_interface *xch, uint32_t domid,
+ unsigned int space,
+ unsigned long idx,
+ xen_pfn_t gpfn)
+{
+ return xc_domain_add_to_physmap(xch, domid, space, idx, gpfn);
+}
+#else
+static inline int xen_xc_domain_add_to_physmap(xc_interface *xch, uint32_t domid,
+ unsigned int space,
+ unsigned long idx,
+ xen_pfn_t gpfn)
+{
+ /* In Xen 4.6 rc is -1 and errno contains the error value. */
+ int rc = xc_domain_add_to_physmap(xch, domid, space, idx, gpfn);
+ if (rc == -1)
+ return errno;
+ return rc;
+}
+#endif
+
+#ifdef CONFIG_XEN_PV_DOMAIN_BUILD
+#if CONFIG_XEN_CTRL_INTERFACE_VERSION < 470
+static inline int xen_domain_create(xc_interface *xc, uint32_t ssidref,
+ xen_domain_handle_t handle, uint32_t flags,
+ uint32_t *pdomid)
+{
+ return xc_domain_create(xc, ssidref, handle, flags, pdomid);
+}
+#else
+static inline int xen_domain_create(xc_interface *xc, uint32_t ssidref,
+ xen_domain_handle_t handle, uint32_t flags,
+ uint32_t *pdomid)
+{
+ return xc_domain_create(xc, ssidref, handle, flags, pdomid, NULL);
+}
+#endif
+#endif
+
#endif /* QEMU_HW_XEN_COMMON_H */