diff options
Diffstat (limited to 'qemu/include/hw/net')
| -rw-r--r-- | qemu/include/hw/net/allwinner_emac.h | 173 | ||||
| -rw-r--r-- | qemu/include/hw/net/cadence_gem.h | 73 | ||||
| -rw-r--r-- | qemu/include/hw/net/imx_fec.h | 113 | ||||
| -rw-r--r-- | qemu/include/hw/net/mii.h | 76 |
4 files changed, 0 insertions, 435 deletions
diff --git a/qemu/include/hw/net/allwinner_emac.h b/qemu/include/hw/net/allwinner_emac.h deleted file mode 100644 index 9f21aa7e4..000000000 --- a/qemu/include/hw/net/allwinner_emac.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Emulation of Allwinner EMAC Fast Ethernet controller and - * Realtek RTL8201CP PHY - * - * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> - * - * Allwinner EMAC register definitions from Linux kernel are: - * Copyright 2012 Stefan Roese <sr@denx.de> - * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com> - * Copyright 1997 Sten Wang - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#ifndef AW_EMAC_H -#define AW_EMAC_H - -#include "net/net.h" -#include "qemu/fifo8.h" -#include "hw/net/mii.h" - -#define TYPE_AW_EMAC "allwinner-emac" -#define AW_EMAC(obj) OBJECT_CHECK(AwEmacState, (obj), TYPE_AW_EMAC) - -/* - * Allwinner EMAC register list - */ -#define EMAC_CTL_REG 0x00 - -#define EMAC_TX_MODE_REG 0x04 -#define EMAC_TX_FLOW_REG 0x08 -#define EMAC_TX_CTL0_REG 0x0C -#define EMAC_TX_CTL1_REG 0x10 -#define EMAC_TX_INS_REG 0x14 -#define EMAC_TX_PL0_REG 0x18 -#define EMAC_TX_PL1_REG 0x1C -#define EMAC_TX_STA_REG 0x20 -#define EMAC_TX_IO_DATA_REG 0x24 -#define EMAC_TX_IO_DATA1_REG 0x28 -#define EMAC_TX_TSVL0_REG 0x2C -#define EMAC_TX_TSVH0_REG 0x30 -#define EMAC_TX_TSVL1_REG 0x34 -#define EMAC_TX_TSVH1_REG 0x38 - -#define EMAC_RX_CTL_REG 0x3C -#define EMAC_RX_HASH0_REG 0x40 -#define EMAC_RX_HASH1_REG 0x44 -#define EMAC_RX_STA_REG 0x48 -#define EMAC_RX_IO_DATA_REG 0x4C -#define EMAC_RX_FBC_REG 0x50 - -#define EMAC_INT_CTL_REG 0x54 -#define EMAC_INT_STA_REG 0x58 - -#define EMAC_MAC_CTL0_REG 0x5C -#define EMAC_MAC_CTL1_REG 0x60 -#define EMAC_MAC_IPGT_REG 0x64 -#define EMAC_MAC_IPGR_REG 0x68 -#define EMAC_MAC_CLRT_REG 0x6C -#define EMAC_MAC_MAXF_REG 0x70 -#define EMAC_MAC_SUPP_REG 0x74 -#define EMAC_MAC_TEST_REG 0x78 -#define EMAC_MAC_MCFG_REG 0x7C -#define EMAC_MAC_MCMD_REG 0x80 -#define EMAC_MAC_MADR_REG 0x84 -#define EMAC_MAC_MWTD_REG 0x88 -#define EMAC_MAC_MRDD_REG 0x8C -#define EMAC_MAC_MIND_REG 0x90 -#define EMAC_MAC_SSRR_REG 0x94 -#define EMAC_MAC_A0_REG 0x98 -#define EMAC_MAC_A1_REG 0x9C -#define EMAC_MAC_A2_REG 0xA0 - -#define EMAC_SAFX_L_REG0 0xA4 -#define EMAC_SAFX_H_REG0 0xA8 -#define EMAC_SAFX_L_REG1 0xAC -#define EMAC_SAFX_H_REG1 0xB0 -#define EMAC_SAFX_L_REG2 0xB4 -#define EMAC_SAFX_H_REG2 0xB8 -#define EMAC_SAFX_L_REG3 0xBC -#define EMAC_SAFX_H_REG3 0xC0 - -/* CTL register fields */ -#define EMAC_CTL_RESET (1 << 0) -#define EMAC_CTL_TX_EN (1 << 1) -#define EMAC_CTL_RX_EN (1 << 2) - -/* TX MODE register fields */ -#define EMAC_TX_MODE_ABORTED_FRAME_EN (1 << 0) -#define EMAC_TX_MODE_DMA_EN (1 << 1) - -/* RX CTL register fields */ -#define EMAC_RX_CTL_AUTO_DRQ_EN (1 << 1) -#define EMAC_RX_CTL_DMA_EN (1 << 2) -#define EMAC_RX_CTL_PASS_ALL_EN (1 << 4) -#define EMAC_RX_CTL_PASS_CTL_EN (1 << 5) -#define EMAC_RX_CTL_PASS_CRC_ERR_EN (1 << 6) -#define EMAC_RX_CTL_PASS_LEN_ERR_EN (1 << 7) -#define EMAC_RX_CTL_PASS_LEN_OOR_EN (1 << 8) -#define EMAC_RX_CTL_ACCEPT_UNICAST_EN (1 << 16) -#define EMAC_RX_CTL_DA_FILTER_EN (1 << 17) -#define EMAC_RX_CTL_ACCEPT_MULTICAST_EN (1 << 20) -#define EMAC_RX_CTL_HASH_FILTER_EN (1 << 21) -#define EMAC_RX_CTL_ACCEPT_BROADCAST_EN (1 << 22) -#define EMAC_RX_CTL_SA_FILTER_EN (1 << 24) -#define EMAC_RX_CTL_SA_FILTER_INVERT_EN (1 << 25) - -/* RX IO DATA register fields */ -#define EMAC_RX_HEADER(len, status) (((len) & 0xffff) | ((status) << 16)) -#define EMAC_RX_IO_DATA_STATUS_CRC_ERR (1 << 4) -#define EMAC_RX_IO_DATA_STATUS_LEN_ERR (3 << 5) -#define EMAC_RX_IO_DATA_STATUS_OK (1 << 7) -#define EMAC_UNDOCUMENTED_MAGIC 0x0143414d /* header for RX frames */ - -/* INT CTL and INT STA registers fields */ -#define EMAC_INT_TX_CHAN(x) (1 << (x)) -#define EMAC_INT_RX (1 << 8) - -/* Due to lack of specifications, size of fifos is chosen arbitrarily */ -#define TX_FIFO_SIZE (4 * 1024) -#define RX_FIFO_SIZE (32 * 1024) - -#define NUM_TX_FIFOS 2 -#define RX_HDR_SIZE 8 -#define CRC_SIZE 4 - -#define PHY_REG_SHIFT 0 -#define PHY_ADDR_SHIFT 8 - -typedef struct RTL8201CPState { - uint16_t bmcr; - uint16_t bmsr; - uint16_t anar; - uint16_t anlpar; -} RTL8201CPState; - -typedef struct AwEmacState { - /*< private >*/ - SysBusDevice parent_obj; - /*< public >*/ - - MemoryRegion iomem; - qemu_irq irq; - NICState *nic; - NICConf conf; - RTL8201CPState mii; - uint8_t phy_addr; - - uint32_t ctl; - uint32_t tx_mode; - uint32_t rx_ctl; - uint32_t int_ctl; - uint32_t int_sta; - uint32_t phy_target; - - Fifo8 rx_fifo; - uint32_t rx_num_packets; - uint32_t rx_packet_size; - uint32_t rx_packet_pos; - - Fifo8 tx_fifo[NUM_TX_FIFOS]; - uint32_t tx_length[NUM_TX_FIFOS]; - uint32_t tx_channel; -} AwEmacState; - -#endif diff --git a/qemu/include/hw/net/cadence_gem.h b/qemu/include/hw/net/cadence_gem.h deleted file mode 100644 index f2e08e357..000000000 --- a/qemu/include/hw/net/cadence_gem.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * QEMU Cadence GEM emulation - * - * Copyright (c) 2011 Xilinx, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef CADENCE_GEM_H - -#define TYPE_CADENCE_GEM "cadence_gem" -#define CADENCE_GEM(obj) OBJECT_CHECK(CadenceGEMState, (obj), TYPE_CADENCE_GEM) - -#include "net/net.h" -#include "hw/sysbus.h" - -#define CADENCE_GEM_MAXREG (0x00000640/4) /* Last valid GEM address */ - -typedef struct CadenceGEMState { - /*< private >*/ - SysBusDevice parent_obj; - - /*< public >*/ - MemoryRegion iomem; - NICState *nic; - NICConf conf; - qemu_irq irq; - - /* GEM registers backing store */ - uint32_t regs[CADENCE_GEM_MAXREG]; - /* Mask of register bits which are write only */ - uint32_t regs_wo[CADENCE_GEM_MAXREG]; - /* Mask of register bits which are read only */ - uint32_t regs_ro[CADENCE_GEM_MAXREG]; - /* Mask of register bits which are clear on read */ - uint32_t regs_rtc[CADENCE_GEM_MAXREG]; - /* Mask of register bits which are write 1 to clear */ - uint32_t regs_w1c[CADENCE_GEM_MAXREG]; - - /* PHY registers backing store */ - uint16_t phy_regs[32]; - - uint8_t phy_loop; /* Are we in phy loopback? */ - - /* The current DMA descriptor pointers */ - uint32_t rx_desc_addr; - uint32_t tx_desc_addr; - - uint8_t can_rx_state; /* Debug only */ - - unsigned rx_desc[2]; - - bool sar_active[4]; -} CadenceGEMState; - -#define CADENCE_GEM_H -#endif diff --git a/qemu/include/hw/net/imx_fec.h b/qemu/include/hw/net/imx_fec.h deleted file mode 100644 index cbf86509e..000000000 --- a/qemu/include/hw/net/imx_fec.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * i.MX Fast Ethernet Controller emulation. - * - * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net> - * - * Based on Coldfire Fast Ethernet Controller emulation. - * - * Copyright (c) 2007 CodeSourcery. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef IMX_FEC_H -#define IMX_FEC_H - -#define TYPE_IMX_FEC "imx.fec" -#define IMX_FEC(obj) OBJECT_CHECK(IMXFECState, (obj), TYPE_IMX_FEC) - -#include "hw/sysbus.h" -#include "net/net.h" - -#define FEC_MAX_FRAME_SIZE 2032 - -#define FEC_INT_HB (1 << 31) -#define FEC_INT_BABR (1 << 30) -#define FEC_INT_BABT (1 << 29) -#define FEC_INT_GRA (1 << 28) -#define FEC_INT_TXF (1 << 27) -#define FEC_INT_TXB (1 << 26) -#define FEC_INT_RXF (1 << 25) -#define FEC_INT_RXB (1 << 24) -#define FEC_INT_MII (1 << 23) -#define FEC_INT_EBERR (1 << 22) -#define FEC_INT_LC (1 << 21) -#define FEC_INT_RL (1 << 20) -#define FEC_INT_UN (1 << 19) - -#define FEC_EN 2 -#define FEC_RESET 1 - -/* Buffer Descriptor. */ -typedef struct { - uint16_t length; - uint16_t flags; - uint32_t data; -} IMXFECBufDesc; - -#define FEC_BD_R (1 << 15) -#define FEC_BD_E (1 << 15) -#define FEC_BD_O1 (1 << 14) -#define FEC_BD_W (1 << 13) -#define FEC_BD_O2 (1 << 12) -#define FEC_BD_L (1 << 11) -#define FEC_BD_TC (1 << 10) -#define FEC_BD_ABC (1 << 9) -#define FEC_BD_M (1 << 8) -#define FEC_BD_BC (1 << 7) -#define FEC_BD_MC (1 << 6) -#define FEC_BD_LG (1 << 5) -#define FEC_BD_NO (1 << 4) -#define FEC_BD_CR (1 << 2) -#define FEC_BD_OV (1 << 1) -#define FEC_BD_TR (1 << 0) - -typedef struct IMXFECState { - /*< private >*/ - SysBusDevice parent_obj; - - /*< public >*/ - NICState *nic; - NICConf conf; - qemu_irq irq; - MemoryRegion iomem; - - uint32_t irq_state; - uint32_t eir; - uint32_t eimr; - uint32_t rx_enabled; - uint32_t rx_descriptor; - uint32_t tx_descriptor; - uint32_t ecr; - uint32_t mmfr; - uint32_t mscr; - uint32_t mibc; - uint32_t rcr; - uint32_t tcr; - uint32_t tfwr; - uint32_t frsr; - uint32_t erdsr; - uint32_t etdsr; - uint32_t emrbr; - uint32_t miigsk_cfgr; - uint32_t miigsk_enr; - - uint32_t phy_status; - uint32_t phy_control; - uint32_t phy_advertise; - uint32_t phy_int; - uint32_t phy_int_mask; -} IMXFECState; - -#endif diff --git a/qemu/include/hw/net/mii.h b/qemu/include/hw/net/mii.h deleted file mode 100644 index 9fdd7bbe7..000000000 --- a/qemu/include/hw/net/mii.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Common network MII address and register definitions. - * - * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> - * - * Allwinner EMAC register definitions from Linux kernel are: - * Copyright 2012 Stefan Roese <sr@denx.de> - * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com> - * Copyright 1997 Sten Wang - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#ifndef MII_H -#define MII_H - -/* PHY registers */ -#define MII_BMCR 0 -#define MII_BMSR 1 -#define MII_PHYID1 2 -#define MII_PHYID2 3 -#define MII_ANAR 4 -#define MII_ANLPAR 5 -#define MII_ANER 6 -#define MII_NSR 16 -#define MII_LBREMR 17 -#define MII_REC 18 -#define MII_SNRDR 19 -#define MII_TEST 25 - -/* PHY registers fields */ -#define MII_BMCR_RESET (1 << 15) -#define MII_BMCR_LOOPBACK (1 << 14) -#define MII_BMCR_SPEED (1 << 13) -#define MII_BMCR_AUTOEN (1 << 12) -#define MII_BMCR_FD (1 << 8) - -#define MII_BMSR_100TX_FD (1 << 14) -#define MII_BMSR_100TX_HD (1 << 13) -#define MII_BMSR_10T_FD (1 << 12) -#define MII_BMSR_10T_HD (1 << 11) -#define MII_BMSR_MFPS (1 << 6) -#define MII_BMSR_AN_COMP (1 << 5) -#define MII_BMSR_AUTONEG (1 << 3) -#define MII_BMSR_LINK_ST (1 << 2) - -#define MII_ANAR_TXFD (1 << 8) -#define MII_ANAR_TX (1 << 7) -#define MII_ANAR_10FD (1 << 6) -#define MII_ANAR_10 (1 << 5) -#define MII_ANAR_CSMACD (1 << 0) - -#define MII_ANLPAR_ACK (1 << 14) -#define MII_ANLPAR_TXFD (1 << 8) -#define MII_ANLPAR_TX (1 << 7) -#define MII_ANLPAR_10FD (1 << 6) -#define MII_ANLPAR_10 (1 << 5) -#define MII_ANLPAR_CSMACD (1 << 0) - -/* List of vendor identifiers */ -/* RealTek 8201 */ -#define RTL8201CP_PHYID1 0x0000 -#define RTL8201CP_PHYID2 0x8201 - -/* National Semiconductor DP83848 */ -#define DP83848_PHYID1 0x2000 -#define DP83848_PHYID2 0x5c90 - -#endif /* MII_H */ |