diff options
Diffstat (limited to 'qemu/hw/cpu')
-rw-r--r-- | qemu/hw/cpu/Makefile.objs | 5 | ||||
-rw-r--r-- | qemu/hw/cpu/a15mpcore.c | 158 | ||||
-rw-r--r-- | qemu/hw/cpu/a9mpcore.c | 192 | ||||
-rw-r--r-- | qemu/hw/cpu/arm11mpcore.c | 174 | ||||
-rw-r--r-- | qemu/hw/cpu/realview_mpcore.c | 141 |
5 files changed, 0 insertions, 670 deletions
diff --git a/qemu/hw/cpu/Makefile.objs b/qemu/hw/cpu/Makefile.objs deleted file mode 100644 index 0954a1872..000000000 --- a/qemu/hw/cpu/Makefile.objs +++ /dev/null @@ -1,5 +0,0 @@ -obj-$(CONFIG_ARM11MPCORE) += arm11mpcore.o -obj-$(CONFIG_REALVIEW) += realview_mpcore.o -obj-$(CONFIG_A9MPCORE) += a9mpcore.o -obj-$(CONFIG_A15MPCORE) += a15mpcore.o - diff --git a/qemu/hw/cpu/a15mpcore.c b/qemu/hw/cpu/a15mpcore.c deleted file mode 100644 index bc05152fd..000000000 --- a/qemu/hw/cpu/a15mpcore.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Cortex-A15MPCore internal peripheral emulation. - * - * Copyright (c) 2012 Linaro Limited. - * Written by Peter Maydell. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, see <http://www.gnu.org/licenses/>. - */ - -#include "qemu/osdep.h" -#include "qapi/error.h" -#include "hw/cpu/a15mpcore.h" -#include "sysemu/kvm.h" -#include "kvm_arm.h" - -static void a15mp_priv_set_irq(void *opaque, int irq, int level) -{ - A15MPPrivState *s = (A15MPPrivState *)opaque; - - qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); -} - -static void a15mp_priv_initfn(Object *obj) -{ - SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - A15MPPrivState *s = A15MPCORE_PRIV(obj); - DeviceState *gicdev; - - memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000); - sysbus_init_mmio(sbd, &s->container); - - object_initialize(&s->gic, sizeof(s->gic), gic_class_name()); - gicdev = DEVICE(&s->gic); - qdev_set_parent_bus(gicdev, sysbus_get_default()); - qdev_prop_set_uint32(gicdev, "revision", 2); -} - -static void a15mp_priv_realize(DeviceState *dev, Error **errp) -{ - SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - A15MPPrivState *s = A15MPCORE_PRIV(dev); - DeviceState *gicdev; - SysBusDevice *busdev; - int i; - Error *err = NULL; - bool has_el3; - Object *cpuobj; - - gicdev = DEVICE(&s->gic); - qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); - qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); - - if (!kvm_irqchip_in_kernel()) { - /* Make the GIC's TZ support match the CPUs. We assume that - * either all the CPUs have TZ, or none do. - */ - cpuobj = OBJECT(qemu_get_cpu(0)); - has_el3 = object_property_find(cpuobj, "has_el3", NULL) && - object_property_get_bool(cpuobj, "has_el3", &error_abort); - qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); - } - - object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); - if (err != NULL) { - error_propagate(errp, err); - return; - } - busdev = SYS_BUS_DEVICE(&s->gic); - - /* Pass through outbound IRQ lines from the GIC */ - sysbus_pass_irq(sbd, busdev); - - /* Pass through inbound GPIO lines to the GIC */ - qdev_init_gpio_in(dev, a15mp_priv_set_irq, s->num_irq - 32); - - /* Wire the outputs from each CPU's generic timer to the - * appropriate GIC PPI inputs - */ - for (i = 0; i < s->num_cpu; i++) { - DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); - int ppibase = s->num_irq - 32 + i * 32; - int irq; - /* Mapping from the output timer irq lines from the CPU to the - * GIC PPI inputs used on the A15: - */ - const int timer_irq[] = { - [GTIMER_PHYS] = 30, - [GTIMER_VIRT] = 27, - [GTIMER_HYP] = 26, - [GTIMER_SEC] = 29, - }; - for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { - qdev_connect_gpio_out(cpudev, irq, - qdev_get_gpio_in(gicdev, - ppibase + timer_irq[irq])); - } - } - - /* Memory map (addresses are offsets from PERIPHBASE): - * 0x0000-0x0fff -- reserved - * 0x1000-0x1fff -- GIC Distributor - * 0x2000-0x3fff -- GIC CPU interface - * 0x4000-0x4fff -- GIC virtual interface control (not modelled) - * 0x5000-0x5fff -- GIC virtual interface control (not modelled) - * 0x6000-0x7fff -- GIC virtual CPU interface (not modelled) - */ - memory_region_add_subregion(&s->container, 0x1000, - sysbus_mmio_get_region(busdev, 0)); - memory_region_add_subregion(&s->container, 0x2000, - sysbus_mmio_get_region(busdev, 1)); -} - -static Property a15mp_priv_properties[] = { - DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1), - /* The Cortex-A15MP may have anything from 0 to 224 external interrupt - * IRQ lines (with another 32 internal). We default to 128+32, which - * is the number provided by the Cortex-A15MP test chip in the - * Versatile Express A15 development board. - * Other boards may differ and should set this property appropriately. - */ - DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160), - DEFINE_PROP_END_OF_LIST(), -}; - -static void a15mp_priv_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - - dc->realize = a15mp_priv_realize; - dc->props = a15mp_priv_properties; - /* We currently have no savable state */ -} - -static const TypeInfo a15mp_priv_info = { - .name = TYPE_A15MPCORE_PRIV, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(A15MPPrivState), - .instance_init = a15mp_priv_initfn, - .class_init = a15mp_priv_class_init, -}; - -static void a15mp_register_types(void) -{ - type_register_static(&a15mp_priv_info); -} - -type_init(a15mp_register_types) diff --git a/qemu/hw/cpu/a9mpcore.c b/qemu/hw/cpu/a9mpcore.c deleted file mode 100644 index 5459ae8c1..000000000 --- a/qemu/hw/cpu/a9mpcore.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Cortex-A9MPCore internal peripheral emulation. - * - * Copyright (c) 2009 CodeSourcery. - * Copyright (c) 2011 Linaro Limited. - * Written by Paul Brook, Peter Maydell. - * - * This code is licensed under the GPL. - */ - -#include "qemu/osdep.h" -#include "qapi/error.h" -#include "hw/cpu/a9mpcore.h" - -static void a9mp_priv_set_irq(void *opaque, int irq, int level) -{ - A9MPPrivState *s = (A9MPPrivState *)opaque; - - qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); -} - -static void a9mp_priv_initfn(Object *obj) -{ - A9MPPrivState *s = A9MPCORE_PRIV(obj); - - memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); - sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); - - object_initialize(&s->scu, sizeof(s->scu), TYPE_A9_SCU); - qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); - - object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); - qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); - - object_initialize(&s->gtimer, sizeof(s->gtimer), TYPE_A9_GTIMER); - qdev_set_parent_bus(DEVICE(&s->gtimer), sysbus_get_default()); - - object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER); - qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default()); - - object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ARM_MPTIMER); - qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default()); -} - -static void a9mp_priv_realize(DeviceState *dev, Error **errp) -{ - SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - A9MPPrivState *s = A9MPCORE_PRIV(dev); - DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev; - SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev, - *wdtbusdev; - Error *err = NULL; - int i; - bool has_el3; - Object *cpuobj; - - scudev = DEVICE(&s->scu); - qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); - object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); - if (err != NULL) { - error_propagate(errp, err); - return; - } - scubusdev = SYS_BUS_DEVICE(&s->scu); - - gicdev = DEVICE(&s->gic); - qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); - qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); - - /* Make the GIC's TZ support match the CPUs. We assume that - * either all the CPUs have TZ, or none do. - */ - cpuobj = OBJECT(qemu_get_cpu(0)); - has_el3 = object_property_find(cpuobj, "has_el3", NULL) && - object_property_get_bool(cpuobj, "has_el3", &error_abort); - qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); - - object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); - if (err != NULL) { - error_propagate(errp, err); - return; - } - gicbusdev = SYS_BUS_DEVICE(&s->gic); - - /* Pass through outbound IRQ lines from the GIC */ - sysbus_pass_irq(sbd, gicbusdev); - - /* Pass through inbound GPIO lines to the GIC */ - qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32); - - gtimerdev = DEVICE(&s->gtimer); - qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu); - object_property_set_bool(OBJECT(&s->gtimer), true, "realized", &err); - if (err != NULL) { - error_propagate(errp, err); - return; - } - gtimerbusdev = SYS_BUS_DEVICE(&s->gtimer); - - mptimerdev = DEVICE(&s->mptimer); - qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); - object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err); - if (err != NULL) { - error_propagate(errp, err); - return; - } - mptimerbusdev = SYS_BUS_DEVICE(&s->mptimer); - - wdtdev = DEVICE(&s->wdt); - qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu); - object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err); - if (err != NULL) { - error_propagate(errp, err); - return; - } - wdtbusdev = SYS_BUS_DEVICE(&s->wdt); - - /* Memory map (addresses are offsets from PERIPHBASE): - * 0x0000-0x00ff -- Snoop Control Unit - * 0x0100-0x01ff -- GIC CPU interface - * 0x0200-0x02ff -- Global Timer - * 0x0300-0x05ff -- nothing - * 0x0600-0x06ff -- private timers and watchdogs - * 0x0700-0x0fff -- nothing - * 0x1000-0x1fff -- GIC Distributor - */ - memory_region_add_subregion(&s->container, 0, - sysbus_mmio_get_region(scubusdev, 0)); - /* GIC CPU interface */ - memory_region_add_subregion(&s->container, 0x100, - sysbus_mmio_get_region(gicbusdev, 1)); - memory_region_add_subregion(&s->container, 0x200, - sysbus_mmio_get_region(gtimerbusdev, 0)); - /* Note that the A9 exposes only the "timer/watchdog for this core" - * memory region, not the "timer/watchdog for core X" ones 11MPcore has. - */ - memory_region_add_subregion(&s->container, 0x600, - sysbus_mmio_get_region(mptimerbusdev, 0)); - memory_region_add_subregion(&s->container, 0x620, - sysbus_mmio_get_region(wdtbusdev, 0)); - memory_region_add_subregion(&s->container, 0x1000, - sysbus_mmio_get_region(gicbusdev, 0)); - - /* Wire up the interrupt from each watchdog and timer. - * For each core the global timer is PPI 27, the private - * timer is PPI 29 and the watchdog PPI 30. - */ - for (i = 0; i < s->num_cpu; i++) { - int ppibase = (s->num_irq - 32) + i * 32; - sysbus_connect_irq(gtimerbusdev, i, - qdev_get_gpio_in(gicdev, ppibase + 27)); - sysbus_connect_irq(mptimerbusdev, i, - qdev_get_gpio_in(gicdev, ppibase + 29)); - sysbus_connect_irq(wdtbusdev, i, - qdev_get_gpio_in(gicdev, ppibase + 30)); - } -} - -static Property a9mp_priv_properties[] = { - DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), - /* The Cortex-A9MP may have anything from 0 to 224 external interrupt - * IRQ lines (with another 32 internal). We default to 64+32, which - * is the number provided by the Cortex-A9MP test chip in the - * Realview PBX-A9 and Versatile Express A9 development boards. - * Other boards may differ and should set this property appropriately. - */ - DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), - DEFINE_PROP_END_OF_LIST(), -}; - -static void a9mp_priv_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - - dc->realize = a9mp_priv_realize; - dc->props = a9mp_priv_properties; -} - -static const TypeInfo a9mp_priv_info = { - .name = TYPE_A9MPCORE_PRIV, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(A9MPPrivState), - .instance_init = a9mp_priv_initfn, - .class_init = a9mp_priv_class_init, -}; - -static void a9mp_register_types(void) -{ - type_register_static(&a9mp_priv_info); -} - -type_init(a9mp_register_types) diff --git a/qemu/hw/cpu/arm11mpcore.c b/qemu/hw/cpu/arm11mpcore.c deleted file mode 100644 index eb244658b..000000000 --- a/qemu/hw/cpu/arm11mpcore.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * ARM11MPCore internal peripheral emulation. - * - * Copyright (c) 2006-2007 CodeSourcery. - * Written by Paul Brook - * - * This code is licensed under the GPL. - */ - -#include "qemu/osdep.h" -#include "qapi/error.h" -#include "hw/cpu/arm11mpcore.h" -#include "hw/intc/realview_gic.h" - - -static void mpcore_priv_set_irq(void *opaque, int irq, int level) -{ - ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; - - qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); -} - -static void mpcore_priv_map_setup(ARM11MPCorePriveState *s) -{ - int i; - SysBusDevice *scubusdev = SYS_BUS_DEVICE(&s->scu); - DeviceState *gicdev = DEVICE(&s->gic); - SysBusDevice *gicbusdev = SYS_BUS_DEVICE(&s->gic); - SysBusDevice *timerbusdev = SYS_BUS_DEVICE(&s->mptimer); - SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(&s->wdtimer); - - memory_region_add_subregion(&s->container, 0, - sysbus_mmio_get_region(scubusdev, 0)); - /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs - * at 0x200, 0x300... - */ - for (i = 0; i < (s->num_cpu + 1); i++) { - hwaddr offset = 0x100 + (i * 0x100); - memory_region_add_subregion(&s->container, offset, - sysbus_mmio_get_region(gicbusdev, i + 1)); - } - /* Add the regions for timer and watchdog for "current CPU" and - * for each specific CPU. - */ - for (i = 0; i < (s->num_cpu + 1); i++) { - /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */ - hwaddr offset = 0x600 + i * 0x100; - memory_region_add_subregion(&s->container, offset, - sysbus_mmio_get_region(timerbusdev, i)); - memory_region_add_subregion(&s->container, offset + 0x20, - sysbus_mmio_get_region(wdtbusdev, i)); - } - memory_region_add_subregion(&s->container, 0x1000, - sysbus_mmio_get_region(gicbusdev, 0)); - /* Wire up the interrupt from each watchdog and timer. - * For each core the timer is PPI 29 and the watchdog PPI 30. - */ - for (i = 0; i < s->num_cpu; i++) { - int ppibase = (s->num_irq - 32) + i * 32; - sysbus_connect_irq(timerbusdev, i, - qdev_get_gpio_in(gicdev, ppibase + 29)); - sysbus_connect_irq(wdtbusdev, i, - qdev_get_gpio_in(gicdev, ppibase + 30)); - } -} - -static void mpcore_priv_realize(DeviceState *dev, Error **errp) -{ - SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev); - DeviceState *scudev = DEVICE(&s->scu); - DeviceState *gicdev = DEVICE(&s->gic); - DeviceState *mptimerdev = DEVICE(&s->mptimer); - DeviceState *wdtimerdev = DEVICE(&s->wdtimer); - Error *err = NULL; - - qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); - object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); - if (err != NULL) { - error_propagate(errp, err); - return; - } - - qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); - qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); - object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); - if (err != NULL) { - error_propagate(errp, err); - return; - } - - /* Pass through outbound IRQ lines from the GIC */ - sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic)); - - /* Pass through inbound GPIO lines to the GIC */ - qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32); - - qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); - object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err); - if (err != NULL) { - error_propagate(errp, err); - return; - } - - qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu); - object_property_set_bool(OBJECT(&s->wdtimer), true, "realized", &err); - if (err != NULL) { - error_propagate(errp, err); - return; - } - - mpcore_priv_map_setup(s); -} - -static void mpcore_priv_initfn(Object *obj) -{ - SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj); - - memory_region_init(&s->container, OBJECT(s), - "mpcore-priv-container", 0x2000); - sysbus_init_mmio(sbd, &s->container); - - object_initialize(&s->scu, sizeof(s->scu), TYPE_ARM11_SCU); - qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); - - object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); - qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); - /* Request the legacy 11MPCore GIC behaviour: */ - qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0); - - object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER); - qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default()); - - object_initialize(&s->wdtimer, sizeof(s->wdtimer), TYPE_ARM_MPTIMER); - qdev_set_parent_bus(DEVICE(&s->wdtimer), sysbus_get_default()); -} - -static Property mpcore_priv_properties[] = { - DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1), - /* The ARM11 MPCORE TRM says the on-chip controller may have - * anything from 0 to 224 external interrupt IRQ lines (with another - * 32 internal). We default to 32+32, which is the number provided by - * the ARM11 MPCore test chip in the Realview Versatile Express - * coretile. Other boards may differ and should set this property - * appropriately. Some Linux kernels may not boot if the hardware - * has more IRQ lines than the kernel expects. - */ - DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64), - DEFINE_PROP_END_OF_LIST(), -}; - -static void mpcore_priv_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - - dc->realize = mpcore_priv_realize; - dc->props = mpcore_priv_properties; -} - -static const TypeInfo mpcore_priv_info = { - .name = TYPE_ARM11MPCORE_PRIV, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(ARM11MPCorePriveState), - .instance_init = mpcore_priv_initfn, - .class_init = mpcore_priv_class_init, -}; - -static void arm11mpcore_register_types(void) -{ - type_register_static(&mpcore_priv_info); -} - -type_init(arm11mpcore_register_types) diff --git a/qemu/hw/cpu/realview_mpcore.c b/qemu/hw/cpu/realview_mpcore.c deleted file mode 100644 index 39d4ebeb1..000000000 --- a/qemu/hw/cpu/realview_mpcore.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * RealView ARM11MPCore internal peripheral emulation - * - * Copyright (c) 2006-2007 CodeSourcery. - * Copyright (c) 2013 SUSE LINUX Products GmbH - * Written by Paul Brook and Andreas Färber - * - * This code is licensed under the GPL. - */ - -#include "qemu/osdep.h" -#include "qapi/error.h" -#include "hw/cpu/arm11mpcore.h" -#include "hw/intc/realview_gic.h" - -#define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore" -#define REALVIEW_MPCORE_RIRQ(obj) \ - OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ) - -/* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ - controllers. The output of these, plus some of the raw input lines - are fed into a single SMP-aware interrupt controller on the CPU. */ -typedef struct { - SysBusDevice parent_obj; - - qemu_irq cpuic[32]; - qemu_irq rvic[4][64]; - uint32_t num_cpu; - - ARM11MPCorePriveState priv; - RealViewGICState gic[4]; -} mpcore_rirq_state; - -/* Map baseboard IRQs onto CPU IRQ lines. */ -static const int mpcore_irq_map[32] = { - -1, -1, -1, -1, 1, 2, -1, -1, - -1, -1, 6, -1, 4, 5, -1, -1, - -1, 14, 15, 0, 7, 8, -1, -1, - -1, -1, -1, -1, 9, 3, -1, -1, -}; - -static void mpcore_rirq_set_irq(void *opaque, int irq, int level) -{ - mpcore_rirq_state *s = (mpcore_rirq_state *)opaque; - int i; - - for (i = 0; i < 4; i++) { - qemu_set_irq(s->rvic[i][irq], level); - } - if (irq < 32) { - irq = mpcore_irq_map[irq]; - if (irq >= 0) { - qemu_set_irq(s->cpuic[irq], level); - } - } -} - -static void realview_mpcore_realize(DeviceState *dev, Error **errp) -{ - SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev); - DeviceState *priv = DEVICE(&s->priv); - DeviceState *gic; - SysBusDevice *gicbusdev; - Error *err = NULL; - int n; - int i; - - qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu); - object_property_set_bool(OBJECT(&s->priv), true, "realized", &err); - if (err != NULL) { - error_propagate(errp, err); - return; - } - sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->priv)); - for (i = 0; i < 32; i++) { - s->cpuic[i] = qdev_get_gpio_in(priv, i); - } - /* ??? IRQ routing is hardcoded to "normal" mode. */ - for (n = 0; n < 4; n++) { - object_property_set_bool(OBJECT(&s->gic[n]), true, "realized", &err); - if (err != NULL) { - error_propagate(errp, err); - return; - } - gic = DEVICE(&s->gic[n]); - gicbusdev = SYS_BUS_DEVICE(&s->gic[n]); - sysbus_mmio_map(gicbusdev, 0, 0x10040000 + n * 0x10000); - sysbus_connect_irq(gicbusdev, 0, s->cpuic[10 + n]); - for (i = 0; i < 64; i++) { - s->rvic[n][i] = qdev_get_gpio_in(gic, i); - } - } - qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64); -} - -static void mpcore_rirq_init(Object *obj) -{ - SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(obj); - SysBusDevice *privbusdev; - int i; - - object_initialize(&s->priv, sizeof(s->priv), TYPE_ARM11MPCORE_PRIV); - qdev_set_parent_bus(DEVICE(&s->priv), sysbus_get_default()); - privbusdev = SYS_BUS_DEVICE(&s->priv); - sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0)); - - for (i = 0; i < 4; i++) { - object_initialize(&s->gic[i], sizeof(s->gic[i]), TYPE_REALVIEW_GIC); - qdev_set_parent_bus(DEVICE(&s->gic[i]), sysbus_get_default()); - } -} - -static Property mpcore_rirq_properties[] = { - DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1), - DEFINE_PROP_END_OF_LIST(), -}; - -static void mpcore_rirq_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - - dc->realize = realview_mpcore_realize; - dc->props = mpcore_rirq_properties; -} - -static const TypeInfo mpcore_rirq_info = { - .name = TYPE_REALVIEW_MPCORE_RIRQ, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(mpcore_rirq_state), - .instance_init = mpcore_rirq_init, - .class_init = mpcore_rirq_class_init, -}; - -static void realview_mpcore_register_types(void) -{ - type_register_static(&mpcore_rirq_info); -} - -type_init(realview_mpcore_register_types) |