diff options
Diffstat (limited to 'kernel/drivers/staging/fbtft/fb_ili9320.c')
| -rw-r--r-- | kernel/drivers/staging/fbtft/fb_ili9320.c | 137 |
1 files changed, 90 insertions, 47 deletions
diff --git a/kernel/drivers/staging/fbtft/fb_ili9320.c b/kernel/drivers/staging/fbtft/fb_ili9320.c index 3a02edd44..3ed50febe 100644 --- a/kernel/drivers/staging/fbtft/fb_ili9320.c +++ b/kernel/drivers/staging/fbtft/fb_ili9320.c @@ -12,10 +12,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include <linux/module.h> @@ -33,7 +29,6 @@ #define DEFAULT_GAMMA "07 07 6 0 0 0 5 5 4 0\n" \ "07 08 4 7 5 1 2 0 7 7" - static unsigned read_devicecode(struct fbtft_par *par) { int ret; @@ -48,8 +43,6 @@ static int init_display(struct fbtft_par *par) { unsigned devcode; - fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__); - par->fbtftops.reset(par); devcode = read_devicecode(par); @@ -63,43 +56,100 @@ static int init_display(struct fbtft_par *par) /* Initialization sequence from ILI9320 Application Notes */ /* *********** Start Initial Sequence ********* */ - write_reg(par, 0x00E5, 0x8000); /* Set the Vcore voltage and this setting is must. */ - write_reg(par, 0x0000, 0x0001); /* Start internal OSC. */ - write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */ - write_reg(par, 0x0002, 0x0700); /* set 1 line inversion */ - write_reg(par, 0x0004, 0x0000); /* Resize register */ - write_reg(par, 0x0008, 0x0202); /* set the back and front porch */ - write_reg(par, 0x0009, 0x0000); /* set non-display area refresh cycle */ - write_reg(par, 0x000A, 0x0000); /* FMARK function */ - write_reg(par, 0x000C, 0x0000); /* RGB interface setting */ - write_reg(par, 0x000D, 0x0000); /* Frame marker Position */ - write_reg(par, 0x000F, 0x0000); /* RGB interface polarity */ + /* Set the Vcore voltage and this setting is must. */ + write_reg(par, 0x00E5, 0x8000); + + /* Start internal OSC. */ + write_reg(par, 0x0000, 0x0001); + + /* set SS and SM bit */ + write_reg(par, 0x0001, 0x0100); + + /* set 1 line inversion */ + write_reg(par, 0x0002, 0x0700); + + /* Resize register */ + write_reg(par, 0x0004, 0x0000); + + /* set the back and front porch */ + write_reg(par, 0x0008, 0x0202); + + /* set non-display area refresh cycle */ + write_reg(par, 0x0009, 0x0000); + + /* FMARK function */ + write_reg(par, 0x000A, 0x0000); + + /* RGB interface setting */ + write_reg(par, 0x000C, 0x0000); + + /* Frame marker Position */ + write_reg(par, 0x000D, 0x0000); + + /* RGB interface polarity */ + write_reg(par, 0x000F, 0x0000); /* ***********Power On sequence *************** */ - write_reg(par, 0x0010, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - write_reg(par, 0x0011, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */ - write_reg(par, 0x0012, 0x0000); /* VREG1OUT voltage */ - write_reg(par, 0x0013, 0x0000); /* VDV[4:0] for VCOM amplitude */ - mdelay(200); /* Dis-charge capacitor power voltage */ - write_reg(par, 0x0010, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - write_reg(par, 0x0011, 0x0031); /* R11h=0x0031 at VCI=3.3V DC1[2:0], DC0[2:0], VC[2:0] */ + /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + write_reg(par, 0x0010, 0x0000); + + /* DC1[2:0], DC0[2:0], VC[2:0] */ + write_reg(par, 0x0011, 0x0007); + + /* VREG1OUT voltage */ + write_reg(par, 0x0012, 0x0000); + + /* VDV[4:0] for VCOM amplitude */ + write_reg(par, 0x0013, 0x0000); + + /* Dis-charge capacitor power voltage */ + mdelay(200); + + /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + write_reg(par, 0x0010, 0x17B0); + + /* R11h=0x0031 at VCI=3.3V DC1[2:0], DC0[2:0], VC[2:0] */ + write_reg(par, 0x0011, 0x0031); mdelay(50); - write_reg(par, 0x0012, 0x0138); /* R12h=0x0138 at VCI=3.3V VREG1OUT voltage */ + + /* R12h=0x0138 at VCI=3.3V VREG1OUT voltage */ + write_reg(par, 0x0012, 0x0138); mdelay(50); - write_reg(par, 0x0013, 0x1800); /* R13h=0x1800 at VCI=3.3V VDV[4:0] for VCOM amplitude */ - write_reg(par, 0x0029, 0x0008); /* R29h=0x0008 at VCI=3.3V VCM[4:0] for VCOMH */ + + /* R13h=0x1800 at VCI=3.3V VDV[4:0] for VCOM amplitude */ + write_reg(par, 0x0013, 0x1800); + + /* R29h=0x0008 at VCI=3.3V VCM[4:0] for VCOMH */ + write_reg(par, 0x0029, 0x0008); mdelay(50); - write_reg(par, 0x0020, 0x0000); /* GRAM horizontal Address */ - write_reg(par, 0x0021, 0x0000); /* GRAM Vertical Address */ + + /* GRAM horizontal Address */ + write_reg(par, 0x0020, 0x0000); + + /* GRAM Vertical Address */ + write_reg(par, 0x0021, 0x0000); /* ------------------ Set GRAM area --------------- */ - write_reg(par, 0x0050, 0x0000); /* Horizontal GRAM Start Address */ - write_reg(par, 0x0051, 0x00EF); /* Horizontal GRAM End Address */ - write_reg(par, 0x0052, 0x0000); /* Vertical GRAM Start Address */ - write_reg(par, 0x0053, 0x013F); /* Vertical GRAM Start Address */ - write_reg(par, 0x0060, 0x2700); /* Gate Scan Line */ - write_reg(par, 0x0061, 0x0001); /* NDL,VLE, REV */ - write_reg(par, 0x006A, 0x0000); /* set scrolling line */ + /* Horizontal GRAM Start Address */ + write_reg(par, 0x0050, 0x0000); + + /* Horizontal GRAM End Address */ + write_reg(par, 0x0051, 0x00EF); + + /* Vertical GRAM Start Address */ + write_reg(par, 0x0052, 0x0000); + + /* Vertical GRAM End Address */ + write_reg(par, 0x0053, 0x013F); + + /* Gate Scan Line */ + write_reg(par, 0x0060, 0x2700); + + /* NDL,VLE, REV */ + write_reg(par, 0x0061, 0x0001); + + /* set scrolling line */ + write_reg(par, 0x006A, 0x0000); /* -------------- Partial Display Control --------- */ write_reg(par, 0x0080, 0x0000); @@ -123,9 +173,6 @@ static int init_display(struct fbtft_par *par) static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye) { - fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par, - "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye); - switch (par->info->var.rotate) { /* R20h = Horizontal GRAM Start Address */ /* R21h = Vertical GRAM Start Address */ @@ -151,8 +198,6 @@ static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye) static int set_var(struct fbtft_par *par) { - fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__); - switch (par->info->var.rotate) { case 0: write_reg(par, 0x3, (par->bgr << 12) | 0x30); @@ -175,7 +220,7 @@ static int set_var(struct fbtft_par *par) VRP0 VRP1 RP0 RP1 KP0 KP1 KP2 KP3 KP4 KP5 VRN0 VRN1 RN0 RN1 KN0 KN1 KN2 KN3 KN4 KN5 */ -#define CURVE(num, idx) curves[num*par->gamma.num_values + idx] +#define CURVE(num, idx) curves[num * par->gamma.num_values + idx] static int set_gamma(struct fbtft_par *par, unsigned long *curves) { unsigned long mask[] = { @@ -184,12 +229,10 @@ static int set_gamma(struct fbtft_par *par, unsigned long *curves) }; int i, j; - fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__); - /* apply mask */ for (i = 0; i < 2; i++) for (j = 0; j < 10; j++) - CURVE(i, j) &= mask[i*par->gamma.num_values + j]; + CURVE(i, j) &= mask[i * par->gamma.num_values + j]; write_reg(par, 0x0030, CURVE(0, 5) << 8 | CURVE(0, 4)); write_reg(par, 0x0031, CURVE(0, 7) << 8 | CURVE(0, 6)); @@ -207,7 +250,6 @@ static int set_gamma(struct fbtft_par *par, unsigned long *curves) } #undef CURVE - static struct fbtft_display display = { .regwidth = 16, .width = WIDTH, @@ -222,6 +264,7 @@ static struct fbtft_display display = { .set_gamma = set_gamma, }, }; + FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9320", &display); MODULE_ALIAS("spi:" DRVNAME); |