diff options
Diffstat (limited to 'kernel/drivers/pwm')
29 files changed, 2274 insertions, 163 deletions
diff --git a/kernel/drivers/pwm/Kconfig b/kernel/drivers/pwm/Kconfig index b1541f40f..2f4641a0e 100644 --- a/kernel/drivers/pwm/Kconfig +++ b/kernel/drivers/pwm/Kconfig @@ -92,6 +92,15 @@ config PWM_BCM2835 To compile this driver as a module, choose M here: the module will be called pwm-bcm2835. +config PWM_BERLIN + tristate "Marvell Berlin PWM support" + depends on ARCH_BERLIN + help + PWM framework driver for Marvell Berlin SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-berlin. + config PWM_BFIN tristate "Blackfin PWM support" depends on BFIN_GPTIMERS @@ -101,6 +110,16 @@ config PWM_BFIN To compile this driver as a module, choose M here: the module will be called pwm-bfin. +config PWM_BRCMSTB + tristate "Broadcom STB PWM support" + depends on ARCH_BRCMSTB || BMIPS_GENERIC + help + Generic PWM framework driver for the Broadcom Set-top-Box + SoCs (BCM7xxx). + + To compile this driver as a module, choose M Here: the module + will be called pwm-brcmstb.c. + config PWM_CLPS711X tristate "CLPS711X PWM support" depends on ARCH_CLPS711X || COMPILE_TEST @@ -111,6 +130,13 @@ config PWM_CLPS711X To compile this driver as a module, choose M here: the module will be called pwm-clps711x. +config PWM_CRC + bool "Intel Crystalcove (CRC) PWM support" + depends on X86 && INTEL_SOC_PMIC + help + Generic PWM framework driver for Crystalcove (CRC) PMIC based PWM + control. + config PWM_EP93XX tristate "Cirrus Logic EP93xx PWM support" depends on ARCH_EP93XX @@ -173,6 +199,18 @@ config PWM_LP3943 To compile this driver as a module, choose M here: the module will be called pwm-lp3943. +config PWM_LPC18XX_SCT + tristate "LPC18xx/43xx PWM/SCT support" + depends on ARCH_LPC18XX + help + Generic PWM framework driver for NXP LPC18xx PWM/SCT which + supports 16 channels. + A maximum of 15 channels can be requested simultaneously and + must have the same period. + + To compile this driver as a module, choose M here: the module + will be called pwm-lpc18xx-sct. + config PWM_LPC32XX tristate "LPC32XX PWM support" depends on ARCH_LPC32XX @@ -211,6 +249,17 @@ config PWM_LPSS_PLATFORM To compile this driver as a module, choose M here: the module will be called pwm-lpss-platform. +config PWM_MTK_DISP + tristate "MediaTek display PWM driver" + depends on ARCH_MEDIATEK || COMPILE_TEST + depends on HAS_IOMEM + help + Generic PWM framework driver for MediaTek disp-pwm device. + The PWM is used to control the backlight brightness for display. + + To compile this driver as a module, choose M here: the module + will be called pwm-mtk-disp. + config PWM_MXS tristate "Freescale MXS PWM support" depends on ARCH_MXS && OF @@ -223,7 +272,7 @@ config PWM_MXS config PWM_PCA9685 tristate "NXP PCA9685 PWM driver" - depends on OF && I2C + depends on I2C select REGMAP_I2C help Generic PWM framework driver for NXP PCA9685 LED controller. @@ -249,6 +298,17 @@ config PWM_PXA To compile this driver as a module, choose M here: the module will be called pwm-pxa. +config PWM_RCAR + tristate "Renesas R-Car PWM support" + depends on ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || COMPILE_TEST + depends on HAS_IOMEM + help + This driver exposes the PWM Timer controller found in Renesas + R-Car chips through the PWM API. + + To compile this driver as a module, choose M here: the module + will be called pwm-rcar. + config PWM_RENESAS_TPU tristate "Renesas TPU PWM support" depends on ARCH_SHMOBILE || COMPILE_TEST @@ -319,7 +379,7 @@ config PWM_TEGRA config PWM_TIECAP tristate "ECAP PWM support" - depends on SOC_AM33XX || ARCH_DAVINCI_DA8XX + depends on ARCH_OMAP2PLUS || ARCH_DAVINCI_DA8XX help PWM driver support for the ECAP APWM controller found on AM33XX TI SOC @@ -329,7 +389,7 @@ config PWM_TIECAP config PWM_TIEHRPWM tristate "EHRPWM PWM support" - depends on SOC_AM33XX || ARCH_DAVINCI_DA8XX + depends on ARCH_OMAP2PLUS || ARCH_DAVINCI_DA8XX help PWM driver support for the EHRPWM controller found on AM33XX TI SOC @@ -339,7 +399,7 @@ config PWM_TIEHRPWM config PWM_TIPWMSS bool - default y if SOC_AM33XX && (PWM_TIECAP || PWM_TIEHRPWM) + default y if (ARCH_OMAP2PLUS) && (PWM_TIECAP || PWM_TIEHRPWM) help PWM Subsystem driver support for AM33xx SOC. diff --git a/kernel/drivers/pwm/Makefile b/kernel/drivers/pwm/Makefile index ec50eb5b5..69b8275f3 100644 --- a/kernel/drivers/pwm/Makefile +++ b/kernel/drivers/pwm/Makefile @@ -6,22 +6,28 @@ obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o obj-$(CONFIG_PWM_BCM_KONA) += pwm-bcm-kona.o obj-$(CONFIG_PWM_BCM2835) += pwm-bcm2835.o +obj-$(CONFIG_PWM_BERLIN) += pwm-berlin.o obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o +obj-$(CONFIG_PWM_BRCMSTB) += pwm-brcmstb.o obj-$(CONFIG_PWM_CLPS711X) += pwm-clps711x.o +obj-$(CONFIG_PWM_CRC) += pwm-crc.o obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o obj-$(CONFIG_PWM_FSL_FTM) += pwm-fsl-ftm.o obj-$(CONFIG_PWM_IMG) += pwm-img.o obj-$(CONFIG_PWM_IMX) += pwm-imx.o obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o obj-$(CONFIG_PWM_LP3943) += pwm-lp3943.o +obj-$(CONFIG_PWM_LPC18XX_SCT) += pwm-lpc18xx-sct.o obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx.o obj-$(CONFIG_PWM_LPSS) += pwm-lpss.o obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-pci.o obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o +obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o obj-$(CONFIG_PWM_MXS) += pwm-mxs.o obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o obj-$(CONFIG_PWM_PUV3) += pwm-puv3.o obj-$(CONFIG_PWM_PXA) += pwm-pxa.o +obj-$(CONFIG_PWM_RCAR) += pwm-rcar.o obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o diff --git a/kernel/drivers/pwm/core.c b/kernel/drivers/pwm/core.c index ba34c7d89..d24ca5f28 100644 --- a/kernel/drivers/pwm/core.c +++ b/kernel/drivers/pwm/core.c @@ -200,6 +200,8 @@ static void of_pwmchip_remove(struct pwm_chip *chip) * pwm_set_chip_data() - set private chip data for a PWM * @pwm: PWM device * @data: pointer to chip-specific data + * + * Returns: 0 on success or a negative error code on failure. */ int pwm_set_chip_data(struct pwm_device *pwm, void *data) { @@ -215,6 +217,8 @@ EXPORT_SYMBOL_GPL(pwm_set_chip_data); /** * pwm_get_chip_data() - get private chip data for a PWM * @pwm: PWM device + * + * Returns: A pointer to the chip-private data for the PWM device. */ void *pwm_get_chip_data(struct pwm_device *pwm) { @@ -223,13 +227,18 @@ void *pwm_get_chip_data(struct pwm_device *pwm) EXPORT_SYMBOL_GPL(pwm_get_chip_data); /** - * pwmchip_add() - register a new PWM chip + * pwmchip_add_with_polarity() - register a new PWM chip * @chip: the PWM chip to add + * @polarity: initial polarity of PWM channels * * Register a new PWM chip. If chip->base < 0 then a dynamically assigned base - * will be used. + * will be used. The initial polarity for all channels is specified by the + * @polarity parameter. + * + * Returns: 0 on success or a negative error code on failure. */ -int pwmchip_add(struct pwm_chip *chip) +int pwmchip_add_with_polarity(struct pwm_chip *chip, + enum pwm_polarity polarity) { struct pwm_device *pwm; unsigned int i; @@ -259,6 +268,8 @@ int pwmchip_add(struct pwm_chip *chip) pwm->chip = chip; pwm->pwm = chip->base + i; pwm->hwpwm = i; + pwm->polarity = polarity; + mutex_init(&pwm->lock); radix_tree_insert(&pwm_tree, pwm->pwm, pwm); } @@ -279,6 +290,21 @@ out: mutex_unlock(&pwm_lock); return ret; } +EXPORT_SYMBOL_GPL(pwmchip_add_with_polarity); + +/** + * pwmchip_add() - register a new PWM chip + * @chip: the PWM chip to add + * + * Register a new PWM chip. If chip->base < 0 then a dynamically assigned base + * will be used. The initial polarity for all channels is normal. + * + * Returns: 0 on success or a negative error code on failure. + */ +int pwmchip_add(struct pwm_chip *chip) +{ + return pwmchip_add_with_polarity(chip, PWM_POLARITY_NORMAL); +} EXPORT_SYMBOL_GPL(pwmchip_add); /** @@ -287,6 +313,8 @@ EXPORT_SYMBOL_GPL(pwmchip_add); * * Removes a PWM chip. This function may return busy if the PWM chip provides * a PWM device that is still requested. + * + * Returns: 0 on success or a negative error code on failure. */ int pwmchip_remove(struct pwm_chip *chip) { @@ -321,10 +349,13 @@ EXPORT_SYMBOL_GPL(pwmchip_remove); /** * pwm_request() - request a PWM device - * @pwm_id: global PWM device index + * @pwm: global PWM device index * @label: PWM device label * * This function is deprecated, use pwm_get() instead. + * + * Returns: A pointer to a PWM device or an ERR_PTR()-encoded error code on + * failure. */ struct pwm_device *pwm_request(int pwm, const char *label) { @@ -359,9 +390,9 @@ EXPORT_SYMBOL_GPL(pwm_request); * @index: per-chip index of the PWM to request * @label: a literal description string of this PWM * - * Returns the PWM at the given index of the given PWM chip. A negative error - * code is returned if the index is not valid for the specified PWM chip or - * if the PWM device cannot be requested. + * Returns: A pointer to the PWM device at the given index of the given PWM + * chip. A negative error code is returned if the index is not valid for the + * specified PWM chip or if the PWM device cannot be requested. */ struct pwm_device *pwm_request_from_chip(struct pwm_chip *chip, unsigned int index, @@ -402,6 +433,8 @@ EXPORT_SYMBOL_GPL(pwm_free); * @pwm: PWM device * @duty_ns: "on" time (in nanoseconds) * @period_ns: duration (in nanoseconds) of one cycle + * + * Returns: 0 on success or a negative error code on failure. */ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) { @@ -426,7 +459,10 @@ EXPORT_SYMBOL_GPL(pwm_config); * @pwm: PWM device * @polarity: new polarity of the PWM signal * - * Note that the polarity cannot be configured while the PWM device is enabled + * Note that the polarity cannot be configured while the PWM device is + * enabled. + * + * Returns: 0 on success or a negative error code on failure. */ int pwm_set_polarity(struct pwm_device *pwm, enum pwm_polarity polarity) { @@ -438,29 +474,49 @@ int pwm_set_polarity(struct pwm_device *pwm, enum pwm_polarity polarity) if (!pwm->chip->ops->set_polarity) return -ENOSYS; - if (test_bit(PWMF_ENABLED, &pwm->flags)) - return -EBUSY; + mutex_lock(&pwm->lock); + + if (pwm_is_enabled(pwm)) { + err = -EBUSY; + goto unlock; + } err = pwm->chip->ops->set_polarity(pwm->chip, pwm, polarity); if (err) - return err; + goto unlock; pwm->polarity = polarity; - return 0; +unlock: + mutex_unlock(&pwm->lock); + return err; } EXPORT_SYMBOL_GPL(pwm_set_polarity); /** * pwm_enable() - start a PWM output toggling * @pwm: PWM device + * + * Returns: 0 on success or a negative error code on failure. */ int pwm_enable(struct pwm_device *pwm) { - if (pwm && !test_and_set_bit(PWMF_ENABLED, &pwm->flags)) - return pwm->chip->ops->enable(pwm->chip, pwm); + int err = 0; - return pwm ? 0 : -EINVAL; + if (!pwm) + return -EINVAL; + + mutex_lock(&pwm->lock); + + if (!test_and_set_bit(PWMF_ENABLED, &pwm->flags)) { + err = pwm->chip->ops->enable(pwm->chip, pwm); + if (err) + clear_bit(PWMF_ENABLED, &pwm->flags); + } + + mutex_unlock(&pwm->lock); + + return err; } EXPORT_SYMBOL_GPL(pwm_enable); @@ -507,6 +563,9 @@ static struct pwm_chip *of_node_to_pwmchip(struct device_node *np) * lookup of the PWM index. This also means that the "pwm-names" property * becomes mandatory for devices that look up the PWM device via the con_id * parameter. + * + * Returns: A pointer to the requested PWM device or an ERR_PTR()-encoded + * error code on failure. */ struct pwm_device *of_pwm_get(struct device_node *np, const char *con_id) { @@ -586,6 +645,23 @@ void pwm_add_table(struct pwm_lookup *table, size_t num) } /** + * pwm_remove_table() - unregister PWM device consumers + * @table: array of consumers to unregister + * @num: number of consumers in table + */ +void pwm_remove_table(struct pwm_lookup *table, size_t num) +{ + mutex_lock(&pwm_lookup_lock); + + while (num--) { + list_del(&table->list); + table++; + } + + mutex_unlock(&pwm_lookup_lock); +} + +/** * pwm_get() - look up and request a PWM device * @dev: device for PWM consumer * @con_id: consumer name @@ -596,6 +672,9 @@ void pwm_add_table(struct pwm_lookup *table, size_t num) * * Once a PWM chip has been found the specified PWM device will be requested * and is ready to be used. + * + * Returns: A pointer to the requested PWM device or an ERR_PTR()-encoded + * error code on failure. */ struct pwm_device *pwm_get(struct device *dev, const char *con_id) { @@ -659,8 +738,10 @@ struct pwm_device *pwm_get(struct device *dev, const char *con_id) } } - if (!chosen) + if (!chosen) { + pwm = ERR_PTR(-ENODEV); goto out; + } chip = pwmchip_find_by_name(chosen->provider); if (!chip) @@ -718,6 +799,9 @@ static void devm_pwm_release(struct device *dev, void *res) * * This function performs like pwm_get() but the acquired PWM device will * automatically be released on driver detach. + * + * Returns: A pointer to the requested PWM device or an ERR_PTR()-encoded + * error code on failure. */ struct pwm_device *devm_pwm_get(struct device *dev, const char *con_id) { @@ -747,6 +831,9 @@ EXPORT_SYMBOL_GPL(devm_pwm_get); * * This function performs like of_pwm_get() but the acquired PWM device will * automatically be released on driver detach. + * + * Returns: A pointer to the requested PWM device or an ERR_PTR()-encoded + * error code on failure. */ struct pwm_device *devm_of_pwm_get(struct device *dev, struct device_node *np, const char *con_id) @@ -798,7 +885,7 @@ EXPORT_SYMBOL_GPL(devm_pwm_put); * pwm_can_sleep() - report whether PWM access will sleep * @pwm: PWM device * - * It returns true if accessing the PWM can sleep, false otherwise. + * Returns: True if accessing the PWM can sleep, false otherwise. */ bool pwm_can_sleep(struct pwm_device *pwm) { @@ -819,7 +906,7 @@ static void pwm_dbg_show(struct pwm_chip *chip, struct seq_file *s) if (test_bit(PWMF_REQUESTED, &pwm->flags)) seq_puts(s, " requested"); - if (test_bit(PWMF_ENABLED, &pwm->flags)) + if (pwm_is_enabled(pwm)) seq_puts(s, " enabled"); seq_puts(s, "\n"); @@ -890,6 +977,5 @@ static int __init pwm_debugfs_init(void) return 0; } - subsys_initcall(pwm_debugfs_init); #endif /* CONFIG_DEBUG_FS */ diff --git a/kernel/drivers/pwm/pwm-atmel-hlcdc.c b/kernel/drivers/pwm/pwm-atmel-hlcdc.c index fa5feaba2..f994c7eaf 100644 --- a/kernel/drivers/pwm/pwm-atmel-hlcdc.c +++ b/kernel/drivers/pwm/pwm-atmel-hlcdc.c @@ -218,10 +218,18 @@ static const struct atmel_hlcdc_pwm_errata atmel_hlcdc_pwm_sama5d3_errata = { static const struct of_device_id atmel_hlcdc_dt_ids[] = { { + .compatible = "atmel,at91sam9n12-hlcdc", + /* 9n12 has same errata as 9x5 HLCDC PWM */ + .data = &atmel_hlcdc_pwm_at91sam9x5_errata, + }, + { .compatible = "atmel,at91sam9x5-hlcdc", .data = &atmel_hlcdc_pwm_at91sam9x5_errata, }, { + .compatible = "atmel,sama5d2-hlcdc", + }, + { .compatible = "atmel,sama5d3-hlcdc", .data = &atmel_hlcdc_pwm_sama5d3_errata, }, @@ -231,6 +239,7 @@ static const struct of_device_id atmel_hlcdc_dt_ids[] = { }, { /* sentinel */ }, }; +MODULE_DEVICE_TABLE(of, atmel_hlcdc_dt_ids); static int atmel_hlcdc_pwm_probe(struct platform_device *pdev) { diff --git a/kernel/drivers/pwm/pwm-atmel-tcb.c b/kernel/drivers/pwm/pwm-atmel-tcb.c index d14e0677c..75db585a2 100644 --- a/kernel/drivers/pwm/pwm-atmel-tcb.c +++ b/kernel/drivers/pwm/pwm-atmel-tcb.c @@ -305,7 +305,7 @@ static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, */ if (i == 5) { i = slowclk; - rate = 32768; + rate = clk_get_rate(tc->slow_clk); min = div_u64(NSEC_PER_SEC, rate); max = min << tc->tcb_config->counter_width; @@ -347,7 +347,7 @@ static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, tcbpwm->duty = duty; /* If the PWM is enabled, call enable to apply the new conf */ - if (test_bit(PWMF_ENABLED, &pwm->flags)) + if (pwm_is_enabled(pwm)) atmel_tcb_pwm_enable(chip, pwm); return 0; @@ -387,9 +387,9 @@ static int atmel_tcb_pwm_probe(struct platform_device *pdev) tcbpwm = devm_kzalloc(&pdev->dev, sizeof(*tcbpwm), GFP_KERNEL); if (tcbpwm == NULL) { - atmel_tc_free(tc); + err = -ENOMEM; dev_err(&pdev->dev, "failed to allocate memory\n"); - return -ENOMEM; + goto err_free_tc; } tcbpwm->chip.dev = &pdev->dev; @@ -400,17 +400,27 @@ static int atmel_tcb_pwm_probe(struct platform_device *pdev) tcbpwm->chip.npwm = NPWM; tcbpwm->tc = tc; + err = clk_prepare_enable(tc->slow_clk); + if (err) + goto err_free_tc; + spin_lock_init(&tcbpwm->lock); err = pwmchip_add(&tcbpwm->chip); - if (err < 0) { - atmel_tc_free(tc); - return err; - } + if (err < 0) + goto err_disable_clk; platform_set_drvdata(pdev, tcbpwm); return 0; + +err_disable_clk: + clk_disable_unprepare(tcbpwm->tc->slow_clk); + +err_free_tc: + atmel_tc_free(tc); + + return err; } static int atmel_tcb_pwm_remove(struct platform_device *pdev) @@ -418,6 +428,8 @@ static int atmel_tcb_pwm_remove(struct platform_device *pdev) struct atmel_tcb_pwm_chip *tcbpwm = platform_get_drvdata(pdev); int err; + clk_disable_unprepare(tcbpwm->tc->slow_clk); + err = pwmchip_remove(&tcbpwm->chip); if (err < 0) return err; diff --git a/kernel/drivers/pwm/pwm-atmel.c b/kernel/drivers/pwm/pwm-atmel.c index d3c22de9e..0e4bd4e8e 100644 --- a/kernel/drivers/pwm/pwm-atmel.c +++ b/kernel/drivers/pwm/pwm-atmel.c @@ -8,9 +8,11 @@ */ #include <linux/clk.h> +#include <linux/delay.h> #include <linux/err.h> #include <linux/io.h> #include <linux/module.h> +#include <linux/mutex.h> #include <linux/of.h> #include <linux/of_device.h> #include <linux/platform_device.h> @@ -21,6 +23,7 @@ #define PWM_ENA 0x04 #define PWM_DIS 0x08 #define PWM_SR 0x0C +#define PWM_ISR 0x1C /* Bit field in SR */ #define PWM_SR_ALL_CH_ON 0x0F @@ -60,6 +63,9 @@ struct atmel_pwm_chip { struct clk *clk; void __iomem *base; + unsigned int updated_pwms; + struct mutex isr_lock; /* ISR is cleared when read, ensure only one thread does that */ + void (*config)(struct pwm_chip *chip, struct pwm_device *pwm, unsigned long dty, unsigned long prd); }; @@ -108,7 +114,7 @@ static int atmel_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, u32 val; int ret; - if (test_bit(PWMF_ENABLED, &pwm->flags) && (period_ns != pwm->period)) { + if (pwm_is_enabled(pwm) && (period_ns != pwm_get_period(pwm))) { dev_err(chip->dev, "cannot change PWM period while enabled\n"); return -EBUSY; } @@ -144,6 +150,10 @@ static int atmel_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK); atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); atmel_pwm->config(chip, pwm, dty, prd); + mutex_lock(&atmel_pwm->isr_lock); + atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR); + atmel_pwm->updated_pwms &= ~(1 << pwm->hwpwm); + mutex_unlock(&atmel_pwm->isr_lock); clk_disable(atmel_pwm->clk); return ret; @@ -155,24 +165,25 @@ static void atmel_pwm_config_v1(struct pwm_chip *chip, struct pwm_device *pwm, struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); unsigned int val; - if (test_bit(PWMF_ENABLED, &pwm->flags)) { - /* - * If the PWM channel is enabled, using the update register, - * it needs to set bit 10 of CMR to 0 - */ - atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CUPD, dty); - val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); - val &= ~PWM_CMR_UPD_CDTY; - atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); - } else { - /* - * If the PWM channel is disabled, write value to duty and - * period registers directly. - */ - atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CDTY, dty); - atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CPRD, prd); - } + atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CUPD, dty); + + val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); + val &= ~PWM_CMR_UPD_CDTY; + atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); + + /* + * If the PWM channel is enabled, only update CDTY by using the update + * register, it needs to set bit 10 of CMR to 0 + */ + if (pwm_is_enabled(pwm)) + return; + /* + * If the PWM channel is disabled, write value to duty and period + * registers directly. + */ + atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CDTY, dty); + atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CPRD, prd); } static void atmel_pwm_config_v2(struct pwm_chip *chip, struct pwm_device *pwm, @@ -180,7 +191,7 @@ static void atmel_pwm_config_v2(struct pwm_chip *chip, struct pwm_device *pwm, { struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); - if (test_bit(PWMF_ENABLED, &pwm->flags)) { + if (pwm_is_enabled(pwm)) { /* * If the PWM channel is enabled, using the duty update register * to update the value. @@ -242,7 +253,22 @@ static int atmel_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) { struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); + unsigned long timeout = jiffies + 2 * HZ; + + /* + * Wait for at least a complete period to have passed before disabling a + * channel to be sure that CDTY has been updated + */ + mutex_lock(&atmel_pwm->isr_lock); + atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR); + + while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) && + time_before(jiffies, timeout)) { + usleep_range(10, 100); + atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR); + } + mutex_unlock(&atmel_pwm->isr_lock); atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm); clk_disable(atmel_pwm->clk); @@ -357,6 +383,8 @@ static int atmel_pwm_probe(struct platform_device *pdev) atmel_pwm->chip.npwm = 4; atmel_pwm->chip.can_sleep = true; atmel_pwm->config = data->config; + atmel_pwm->updated_pwms = 0; + mutex_init(&atmel_pwm->isr_lock); ret = pwmchip_add(&atmel_pwm->chip); if (ret < 0) { @@ -378,6 +406,7 @@ static int atmel_pwm_remove(struct platform_device *pdev) struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev); clk_unprepare(atmel_pwm->clk); + mutex_destroy(&atmel_pwm->isr_lock); return pwmchip_remove(&atmel_pwm->chip); } diff --git a/kernel/drivers/pwm/pwm-bcm-kona.c b/kernel/drivers/pwm/pwm-bcm-kona.c index 02bc04889..c63418322 100644 --- a/kernel/drivers/pwm/pwm-bcm-kona.c +++ b/kernel/drivers/pwm/pwm-bcm-kona.c @@ -76,19 +76,36 @@ static inline struct kona_pwmc *to_kona_pwmc(struct pwm_chip *_chip) return container_of(_chip, struct kona_pwmc, chip); } -static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int chan) +/* + * Clear trigger bit but set smooth bit to maintain old output. + */ +static void kona_pwmc_prepare_for_settings(struct kona_pwmc *kp, + unsigned int chan) { unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET); - /* Clear trigger bit but set smooth bit to maintain old output */ value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan); value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan)); writel(value, kp->base + PWM_CONTROL_OFFSET); + /* + * There must be a min 400ns delay between clearing trigger and setting + * it. Failing to do this may result in no PWM signal. + */ + ndelay(400); +} + +static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int chan) +{ + unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET); + /* Set trigger bit and clear smooth bit to apply new settings */ value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan)); value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan); writel(value, kp->base + PWM_CONTROL_OFFSET); + + /* Trigger bit must be held high for at least 400 ns. */ + ndelay(400); } static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm, @@ -133,8 +150,14 @@ static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm, return -EINVAL; } - /* If the PWM channel is enabled, write the settings to the HW */ - if (test_bit(PWMF_ENABLED, &pwm->flags)) { + /* + * Don't apply settings if disabled. The period and duty cycle are + * always calculated above to ensure the new values are + * validated immediately instead of on enable. + */ + if (pwm_is_enabled(pwm)) { + kona_pwmc_prepare_for_settings(kp, chan); + value = readl(kp->base + PRESCALE_OFFSET); value &= ~PRESCALE_MASK(chan); value |= prescale << PRESCALE_SHIFT(chan); @@ -164,6 +187,8 @@ static int kona_pwmc_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, return ret; } + kona_pwmc_prepare_for_settings(kp, chan); + value = readl(kp->base + PWM_CONTROL_OFFSET); if (polarity == PWM_POLARITY_NORMAL) @@ -175,9 +200,6 @@ static int kona_pwmc_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, kona_pwmc_apply_settings(kp, chan); - /* Wait for waveform to settle before gating off the clock */ - ndelay(400); - clk_disable_unprepare(kp->clk); return 0; @@ -194,7 +216,8 @@ static int kona_pwmc_enable(struct pwm_chip *chip, struct pwm_device *pwm) return ret; } - ret = kona_pwmc_config(chip, pwm, pwm->duty_cycle, pwm->period); + ret = kona_pwmc_config(chip, pwm, pwm_get_duty_cycle(pwm), + pwm_get_period(pwm)); if (ret < 0) { clk_disable_unprepare(kp->clk); return ret; @@ -207,13 +230,20 @@ static void kona_pwmc_disable(struct pwm_chip *chip, struct pwm_device *pwm) { struct kona_pwmc *kp = to_kona_pwmc(chip); unsigned int chan = pwm->hwpwm; + unsigned int value; + + kona_pwmc_prepare_for_settings(kp, chan); /* Simulate a disable by configuring for zero duty */ writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan)); - kona_pwmc_apply_settings(kp, chan); + writel(0, kp->base + PERIOD_COUNT_OFFSET(chan)); - /* Wait for waveform to settle before gating off the clock */ - ndelay(400); + /* Set prescale to 0 for this channel */ + value = readl(kp->base + PRESCALE_OFFSET); + value &= ~PRESCALE_MASK(chan); + writel(value, kp->base + PRESCALE_OFFSET); + + kona_pwmc_apply_settings(kp, chan); clk_disable_unprepare(kp->clk); } @@ -266,18 +296,15 @@ static int kona_pwmc_probe(struct platform_device *pdev) return ret; } - /* Set smooth mode, push/pull, and normal polarity for all channels */ - for (chan = 0; chan < kp->chip.npwm; chan++) { - value |= (1 << PWM_CONTROL_SMOOTH_SHIFT(chan)); + /* Set push/pull for all channels */ + for (chan = 0; chan < kp->chip.npwm; chan++) value |= (1 << PWM_CONTROL_TYPE_SHIFT(chan)); - value |= (1 << PWM_CONTROL_POLARITY_SHIFT(chan)); - } writel(value, kp->base + PWM_CONTROL_OFFSET); clk_disable_unprepare(kp->clk); - ret = pwmchip_add(&kp->chip); + ret = pwmchip_add_with_polarity(&kp->chip, PWM_POLARITY_INVERSED); if (ret < 0) dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); @@ -290,7 +317,7 @@ static int kona_pwmc_remove(struct platform_device *pdev) unsigned int chan; for (chan = 0; chan < kp->chip.npwm; chan++) - if (test_bit(PWMF_ENABLED, &kp->chip.pwms[chan].flags)) + if (pwm_is_enabled(&kp->chip.pwms[chan])) clk_disable_unprepare(kp->clk); return pwmchip_remove(&kp->chip); diff --git a/kernel/drivers/pwm/pwm-berlin.c b/kernel/drivers/pwm/pwm-berlin.c new file mode 100644 index 000000000..65108129d --- /dev/null +++ b/kernel/drivers/pwm/pwm-berlin.c @@ -0,0 +1,219 @@ +/* + * Marvell Berlin PWM driver + * + * Copyright (C) 2015 Marvell Technology Group Ltd. + * + * Author: Antoine Tenart <antoine.tenart@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pwm.h> + +#define BERLIN_PWM_EN 0x0 +#define BERLIN_PWM_ENABLE BIT(0) +#define BERLIN_PWM_CONTROL 0x4 +#define BERLIN_PWM_PRESCALE_MASK 0x7 +#define BERLIN_PWM_PRESCALE_MAX 4096 +#define BERLIN_PWM_INVERT_POLARITY BIT(3) +#define BERLIN_PWM_DUTY 0x8 +#define BERLIN_PWM_TCNT 0xc +#define BERLIN_PWM_MAX_TCNT 65535 + +struct berlin_pwm_chip { + struct pwm_chip chip; + struct clk *clk; + void __iomem *base; +}; + +static inline struct berlin_pwm_chip *to_berlin_pwm_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct berlin_pwm_chip, chip); +} + +static const u32 prescaler_table[] = { + 1, 4, 8, 16, 64, 256, 1024, 4096 +}; + +static inline u32 berlin_pwm_readl(struct berlin_pwm_chip *chip, + unsigned int channel, unsigned long offset) +{ + return readl_relaxed(chip->base + channel * 0x10 + offset); +} + +static inline void berlin_pwm_writel(struct berlin_pwm_chip *chip, + unsigned int channel, u32 value, + unsigned long offset) +{ + writel_relaxed(value, chip->base + channel * 0x10 + offset); +} + +static int berlin_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm_dev, + int duty_ns, int period_ns) +{ + struct berlin_pwm_chip *pwm = to_berlin_pwm_chip(chip); + unsigned int prescale; + u32 value, duty, period; + u64 cycles, tmp; + + cycles = clk_get_rate(pwm->clk); + cycles *= period_ns; + do_div(cycles, NSEC_PER_SEC); + + for (prescale = 0; prescale < ARRAY_SIZE(prescaler_table); prescale++) { + tmp = cycles; + do_div(tmp, prescaler_table[prescale]); + + if (tmp <= BERLIN_PWM_MAX_TCNT) + break; + } + + if (tmp > BERLIN_PWM_MAX_TCNT) + return -ERANGE; + + period = tmp; + cycles = tmp * duty_ns; + do_div(cycles, period_ns); + duty = cycles; + + value = berlin_pwm_readl(pwm, pwm_dev->hwpwm, BERLIN_PWM_CONTROL); + value &= ~BERLIN_PWM_PRESCALE_MASK; + value |= prescale; + berlin_pwm_writel(pwm, pwm_dev->hwpwm, value, BERLIN_PWM_CONTROL); + + berlin_pwm_writel(pwm, pwm_dev->hwpwm, duty, BERLIN_PWM_DUTY); + berlin_pwm_writel(pwm, pwm_dev->hwpwm, period, BERLIN_PWM_TCNT); + + return 0; +} + +static int berlin_pwm_set_polarity(struct pwm_chip *chip, + struct pwm_device *pwm_dev, + enum pwm_polarity polarity) +{ + struct berlin_pwm_chip *pwm = to_berlin_pwm_chip(chip); + u32 value; + + value = berlin_pwm_readl(pwm, pwm_dev->hwpwm, BERLIN_PWM_CONTROL); + + if (polarity == PWM_POLARITY_NORMAL) + value &= ~BERLIN_PWM_INVERT_POLARITY; + else + value |= BERLIN_PWM_INVERT_POLARITY; + + berlin_pwm_writel(pwm, pwm_dev->hwpwm, value, BERLIN_PWM_CONTROL); + + return 0; +} + +static int berlin_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm_dev) +{ + struct berlin_pwm_chip *pwm = to_berlin_pwm_chip(chip); + u32 value; + + value = berlin_pwm_readl(pwm, pwm_dev->hwpwm, BERLIN_PWM_EN); + value |= BERLIN_PWM_ENABLE; + berlin_pwm_writel(pwm, pwm_dev->hwpwm, value, BERLIN_PWM_EN); + + return 0; +} + +static void berlin_pwm_disable(struct pwm_chip *chip, + struct pwm_device *pwm_dev) +{ + struct berlin_pwm_chip *pwm = to_berlin_pwm_chip(chip); + u32 value; + + value = berlin_pwm_readl(pwm, pwm_dev->hwpwm, BERLIN_PWM_EN); + value &= ~BERLIN_PWM_ENABLE; + berlin_pwm_writel(pwm, pwm_dev->hwpwm, value, BERLIN_PWM_EN); +} + +static const struct pwm_ops berlin_pwm_ops = { + .config = berlin_pwm_config, + .set_polarity = berlin_pwm_set_polarity, + .enable = berlin_pwm_enable, + .disable = berlin_pwm_disable, + .owner = THIS_MODULE, +}; + +static const struct of_device_id berlin_pwm_match[] = { + { .compatible = "marvell,berlin-pwm" }, + { }, +}; +MODULE_DEVICE_TABLE(of, berlin_pwm_match); + +static int berlin_pwm_probe(struct platform_device *pdev) +{ + struct berlin_pwm_chip *pwm; + struct resource *res; + int ret; + + pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); + if (!pwm) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pwm->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pwm->base)) + return PTR_ERR(pwm->base); + + pwm->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(pwm->clk)) + return PTR_ERR(pwm->clk); + + ret = clk_prepare_enable(pwm->clk); + if (ret) + return ret; + + pwm->chip.dev = &pdev->dev; + pwm->chip.ops = &berlin_pwm_ops; + pwm->chip.base = -1; + pwm->chip.npwm = 4; + pwm->chip.can_sleep = true; + pwm->chip.of_xlate = of_pwm_xlate_with_flags; + pwm->chip.of_pwm_n_cells = 3; + + ret = pwmchip_add(&pwm->chip); + if (ret < 0) { + dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); + clk_disable_unprepare(pwm->clk); + return ret; + } + + platform_set_drvdata(pdev, pwm); + + return 0; +} + +static int berlin_pwm_remove(struct platform_device *pdev) +{ + struct berlin_pwm_chip *pwm = platform_get_drvdata(pdev); + int ret; + + ret = pwmchip_remove(&pwm->chip); + clk_disable_unprepare(pwm->clk); + + return ret; +} + +static struct platform_driver berlin_pwm_driver = { + .probe = berlin_pwm_probe, + .remove = berlin_pwm_remove, + .driver = { + .name = "berlin-pwm", + .of_match_table = berlin_pwm_match, + }, +}; +module_platform_driver(berlin_pwm_driver); + +MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>"); +MODULE_DESCRIPTION("Marvell Berlin PWM driver"); +MODULE_LICENSE("GPL v2"); diff --git a/kernel/drivers/pwm/pwm-brcmstb.c b/kernel/drivers/pwm/pwm-brcmstb.c new file mode 100644 index 000000000..423ce087c --- /dev/null +++ b/kernel/drivers/pwm/pwm-brcmstb.c @@ -0,0 +1,343 @@ +/* + * Broadcom BCM7038 PWM driver + * Author: Florian Fainelli + * + * Copyright (C) 2015 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include <linux/clk.h> +#include <linux/export.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pwm.h> +#include <linux/spinlock.h> + +#define PWM_CTRL 0x00 +#define CTRL_START BIT(0) +#define CTRL_OEB BIT(1) +#define CTRL_FORCE_HIGH BIT(2) +#define CTRL_OPENDRAIN BIT(3) +#define CTRL_CHAN_OFFS 4 + +#define PWM_CTRL2 0x04 +#define CTRL2_OUT_SELECT BIT(0) + +#define PWM_CH_SIZE 0x8 + +#define PWM_CWORD_MSB(ch) (0x08 + ((ch) * PWM_CH_SIZE)) +#define PWM_CWORD_LSB(ch) (0x0c + ((ch) * PWM_CH_SIZE)) + +/* Number of bits for the CWORD value */ +#define CWORD_BIT_SIZE 16 + +/* + * Maximum control word value allowed when variable-frequency PWM is used as a + * clock for the constant-frequency PMW. + */ +#define CONST_VAR_F_MAX 32768 +#define CONST_VAR_F_MIN 1 + +#define PWM_ON(ch) (0x18 + ((ch) * PWM_CH_SIZE)) +#define PWM_ON_MIN 1 +#define PWM_PERIOD(ch) (0x1c + ((ch) * PWM_CH_SIZE)) +#define PWM_PERIOD_MIN 0 + +#define PWM_ON_PERIOD_MAX 0xff + +struct brcmstb_pwm { + void __iomem *base; + spinlock_t lock; + struct clk *clk; + struct pwm_chip chip; +}; + +static inline u32 brcmstb_pwm_readl(struct brcmstb_pwm *p, + unsigned int offset) +{ + if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) + return __raw_readl(p->base + offset); + else + return readl_relaxed(p->base + offset); +} + +static inline void brcmstb_pwm_writel(struct brcmstb_pwm *p, u32 value, + unsigned int offset) +{ + if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) + __raw_writel(value, p->base + offset); + else + writel_relaxed(value, p->base + offset); +} + +static inline struct brcmstb_pwm *to_brcmstb_pwm(struct pwm_chip *chip) +{ + return container_of(chip, struct brcmstb_pwm, chip); +} + +/* + * Fv is derived from the variable frequency output. The variable frequency + * output is configured using this formula: + * + * W = cword, if cword < 2 ^ 15 else 16-bit 2's complement of cword + * + * Fv = W x 2 ^ -16 x 27Mhz (reference clock) + * + * The period is: (period + 1) / Fv and "on" time is on / (period + 1) + * + * The PWM core framework specifies that the "duty_ns" parameter is in fact the + * "on" time, so this translates directly into our HW programming here. + */ +static int brcmstb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct brcmstb_pwm *p = to_brcmstb_pwm(chip); + unsigned long pc, dc, cword = CONST_VAR_F_MAX; + unsigned int channel = pwm->hwpwm; + u32 value; + + /* + * If asking for a duty_ns equal to period_ns, we need to substract + * the period value by 1 to make it shorter than the "on" time and + * produce a flat 100% duty cycle signal, and max out the "on" time + */ + if (duty_ns == period_ns) { + dc = PWM_ON_PERIOD_MAX; + pc = PWM_ON_PERIOD_MAX - 1; + goto done; + } + + while (1) { + u64 rate, tmp; + + /* + * Calculate the base rate from base frequency and current + * cword + */ + rate = (u64)clk_get_rate(p->clk) * (u64)cword; + do_div(rate, 1 << CWORD_BIT_SIZE); + + tmp = period_ns * rate; + do_div(tmp, NSEC_PER_SEC); + pc = tmp; + + tmp = (duty_ns + 1) * rate; + do_div(tmp, NSEC_PER_SEC); + dc = tmp; + + /* + * We can be called with separate duty and period updates, + * so do not reject dc == 0 right away + */ + if (pc == PWM_PERIOD_MIN || (dc < PWM_ON_MIN && duty_ns)) + return -EINVAL; + + /* We converged on a calculation */ + if (pc <= PWM_ON_PERIOD_MAX && dc <= PWM_ON_PERIOD_MAX) + break; + + /* + * The cword needs to be a power of 2 for the variable + * frequency generator to output a 50% duty cycle variable + * frequency which is used as input clock to the fixed + * frequency generator. + */ + cword >>= 1; + + /* + * Desired periods are too large, we do not have a divider + * for them + */ + if (cword < CONST_VAR_F_MIN) + return -EINVAL; + } + +done: + /* + * Configure the defined "cword" value to have the variable frequency + * generator output a base frequency for the constant frequency + * generator to derive from. + */ + spin_lock(&p->lock); + brcmstb_pwm_writel(p, cword >> 8, PWM_CWORD_MSB(channel)); + brcmstb_pwm_writel(p, cword & 0xff, PWM_CWORD_LSB(channel)); + + /* Select constant frequency signal output */ + value = brcmstb_pwm_readl(p, PWM_CTRL2); + value |= CTRL2_OUT_SELECT << (channel * CTRL_CHAN_OFFS); + brcmstb_pwm_writel(p, value, PWM_CTRL2); + + /* Configure on and period value */ + brcmstb_pwm_writel(p, pc, PWM_PERIOD(channel)); + brcmstb_pwm_writel(p, dc, PWM_ON(channel)); + spin_unlock(&p->lock); + + return 0; +} + +static inline void brcmstb_pwm_enable_set(struct brcmstb_pwm *p, + unsigned int channel, bool enable) +{ + unsigned int shift = channel * CTRL_CHAN_OFFS; + u32 value; + + spin_lock(&p->lock); + value = brcmstb_pwm_readl(p, PWM_CTRL); + + if (enable) { + value &= ~(CTRL_OEB << shift); + value |= (CTRL_START | CTRL_OPENDRAIN) << shift; + } else { + value &= ~((CTRL_START | CTRL_OPENDRAIN) << shift); + value |= CTRL_OEB << shift; + } + + brcmstb_pwm_writel(p, value, PWM_CTRL); + spin_unlock(&p->lock); +} + +static int brcmstb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct brcmstb_pwm *p = to_brcmstb_pwm(chip); + + brcmstb_pwm_enable_set(p, pwm->hwpwm, true); + + return 0; +} + +static void brcmstb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct brcmstb_pwm *p = to_brcmstb_pwm(chip); + + brcmstb_pwm_enable_set(p, pwm->hwpwm, false); +} + +static const struct pwm_ops brcmstb_pwm_ops = { + .config = brcmstb_pwm_config, + .enable = brcmstb_pwm_enable, + .disable = brcmstb_pwm_disable, + .owner = THIS_MODULE, +}; + +static const struct of_device_id brcmstb_pwm_of_match[] = { + { .compatible = "brcm,bcm7038-pwm", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, brcmstb_pwm_of_match); + +static int brcmstb_pwm_probe(struct platform_device *pdev) +{ + struct brcmstb_pwm *p; + struct resource *res; + int ret; + + p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); + if (!p) + return -ENOMEM; + + spin_lock_init(&p->lock); + + p->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(p->clk)) { + dev_err(&pdev->dev, "failed to obtain clock\n"); + return PTR_ERR(p->clk); + } + + ret = clk_prepare_enable(p->clk); + if (ret < 0) { + dev_err(&pdev->dev, "failed to enable clock: %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, p); + + p->chip.dev = &pdev->dev; + p->chip.ops = &brcmstb_pwm_ops; + p->chip.base = -1; + p->chip.npwm = 2; + p->chip.can_sleep = true; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + p->base = devm_ioremap_resource(&pdev->dev, res); + if (!p->base) { + ret = -ENOMEM; + goto out_clk; + } + + ret = pwmchip_add(&p->chip); + if (ret) { + dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); + goto out_clk; + } + + return 0; + +out_clk: + clk_disable_unprepare(p->clk); + return ret; +} + +static int brcmstb_pwm_remove(struct platform_device *pdev) +{ + struct brcmstb_pwm *p = platform_get_drvdata(pdev); + int ret; + + ret = pwmchip_remove(&p->chip); + clk_disable_unprepare(p->clk); + + return ret; +} + +#ifdef CONFIG_PM_SLEEP +static int brcmstb_pwm_suspend(struct device *dev) +{ + struct brcmstb_pwm *p = dev_get_drvdata(dev); + + clk_disable(p->clk); + + return 0; +} + +static int brcmstb_pwm_resume(struct device *dev) +{ + struct brcmstb_pwm *p = dev_get_drvdata(dev); + + clk_enable(p->clk); + + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(brcmstb_pwm_pm_ops, brcmstb_pwm_suspend, + brcmstb_pwm_resume); + +static struct platform_driver brcmstb_pwm_driver = { + .probe = brcmstb_pwm_probe, + .remove = brcmstb_pwm_remove, + .driver = { + .name = "pwm-brcmstb", + .of_match_table = brcmstb_pwm_of_match, + .pm = &brcmstb_pwm_pm_ops, + }, +}; +module_platform_driver(brcmstb_pwm_driver); + +MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>"); +MODULE_DESCRIPTION("Broadcom STB PWM driver"); +MODULE_ALIAS("platform:pwm-brcmstb"); +MODULE_LICENSE("GPL"); diff --git a/kernel/drivers/pwm/pwm-crc.c b/kernel/drivers/pwm/pwm-crc.c new file mode 100644 index 000000000..7101c7020 --- /dev/null +++ b/kernel/drivers/pwm/pwm-crc.c @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2015 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Author: Shobhit Kumar <shobhit.kumar@intel.com> + */ + +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/mfd/intel_soc_pmic.h> +#include <linux/pwm.h> + +#define PWM0_CLK_DIV 0x4B +#define PWM_OUTPUT_ENABLE BIT(7) +#define PWM_DIV_CLK_0 0x00 /* DIVIDECLK = BASECLK */ +#define PWM_DIV_CLK_100 0x63 /* DIVIDECLK = BASECLK/100 */ +#define PWM_DIV_CLK_128 0x7F /* DIVIDECLK = BASECLK/128 */ + +#define PWM0_DUTY_CYCLE 0x4E +#define BACKLIGHT_EN 0x51 + +#define PWM_MAX_LEVEL 0xFF + +#define PWM_BASE_CLK 6000000 /* 6 MHz */ +#define PWM_MAX_PERIOD_NS 21333 /* 46.875KHz */ + +/** + * struct crystalcove_pwm - Crystal Cove PWM controller + * @chip: the abstract pwm_chip structure. + * @regmap: the regmap from the parent device. + */ +struct crystalcove_pwm { + struct pwm_chip chip; + struct regmap *regmap; +}; + +static inline struct crystalcove_pwm *to_crc_pwm(struct pwm_chip *pc) +{ + return container_of(pc, struct crystalcove_pwm, chip); +} + +static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm) +{ + struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); + + regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1); + + return 0; +} + +static void crc_pwm_disable(struct pwm_chip *c, struct pwm_device *pwm) +{ + struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); + + regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0); +} + +static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); + struct device *dev = crc_pwm->chip.dev; + int level; + + if (period_ns > PWM_MAX_PERIOD_NS) { + dev_err(dev, "un-supported period_ns\n"); + return -EINVAL; + } + + if (pwm->period != period_ns) { + int clk_div; + + /* changing the clk divisor, need to disable fisrt */ + crc_pwm_disable(c, pwm); + clk_div = PWM_BASE_CLK * period_ns / NSEC_PER_SEC; + + regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, + clk_div | PWM_OUTPUT_ENABLE); + + /* enable back */ + crc_pwm_enable(c, pwm); + } + + /* change the pwm duty cycle */ + level = duty_ns * PWM_MAX_LEVEL / period_ns; + regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level); + + return 0; +} + +static const struct pwm_ops crc_pwm_ops = { + .config = crc_pwm_config, + .enable = crc_pwm_enable, + .disable = crc_pwm_disable, +}; + +static int crystalcove_pwm_probe(struct platform_device *pdev) +{ + struct crystalcove_pwm *pwm; + struct device *dev = pdev->dev.parent; + struct intel_soc_pmic *pmic = dev_get_drvdata(dev); + + pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); + if (!pwm) + return -ENOMEM; + + pwm->chip.dev = &pdev->dev; + pwm->chip.ops = &crc_pwm_ops; + pwm->chip.base = -1; + pwm->chip.npwm = 1; + + /* get the PMIC regmap */ + pwm->regmap = pmic->regmap; + + platform_set_drvdata(pdev, pwm); + + return pwmchip_add(&pwm->chip); +} + +static int crystalcove_pwm_remove(struct platform_device *pdev) +{ + struct crystalcove_pwm *pwm = platform_get_drvdata(pdev); + + return pwmchip_remove(&pwm->chip); +} + +static struct platform_driver crystalcove_pwm_driver = { + .probe = crystalcove_pwm_probe, + .remove = crystalcove_pwm_remove, + .driver = { + .name = "crystal_cove_pwm", + }, +}; + +builtin_platform_driver(crystalcove_pwm_driver); diff --git a/kernel/drivers/pwm/pwm-ep93xx.c b/kernel/drivers/pwm/pwm-ep93xx.c index e593e9c45..bbf10ae02 100644 --- a/kernel/drivers/pwm/pwm-ep93xx.c +++ b/kernel/drivers/pwm/pwm-ep93xx.c @@ -82,7 +82,7 @@ static int ep93xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * The clock needs to be enabled to access the PWM registers. * Configuration can be changed at any time. */ - if (!test_bit(PWMF_ENABLED, &pwm->flags)) { + if (!pwm_is_enabled(pwm)) { ret = clk_enable(ep93xx_pwm->clk); if (ret) return ret; @@ -113,7 +113,7 @@ static int ep93xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, ret = -EINVAL; } - if (!test_bit(PWMF_ENABLED, &pwm->flags)) + if (!pwm_is_enabled(pwm)) clk_disable(ep93xx_pwm->clk); return ret; diff --git a/kernel/drivers/pwm/pwm-imx.c b/kernel/drivers/pwm/pwm-imx.c index 66d6f0c5c..d600fd5cd 100644 --- a/kernel/drivers/pwm/pwm-imx.c +++ b/kernel/drivers/pwm/pwm-imx.c @@ -114,7 +114,7 @@ static int imx_pwm_config_v2(struct pwm_chip *chip, unsigned long long c; unsigned long period_cycles, duty_cycles, prescale; unsigned int period_ms; - bool enable = test_bit(PWMF_ENABLED, &pwm->flags); + bool enable = pwm_is_enabled(pwm); int wait_count = 0, fifoav; u32 cr, sr; @@ -129,7 +129,8 @@ static int imx_pwm_config_v2(struct pwm_chip *chip, sr = readl(imx->mmio_base + MX3_PWMSR); fifoav = sr & MX3_PWMSR_FIFOAV_MASK; if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) { - period_ms = DIV_ROUND_UP(pwm->period, NSEC_PER_MSEC); + period_ms = DIV_ROUND_UP(pwm_get_period(pwm), + NSEC_PER_MSEC); msleep(period_ms); sr = readl(imx->mmio_base + MX3_PWMSR); diff --git a/kernel/drivers/pwm/pwm-lpc18xx-sct.c b/kernel/drivers/pwm/pwm-lpc18xx-sct.c new file mode 100644 index 000000000..916308510 --- /dev/null +++ b/kernel/drivers/pwm/pwm-lpc18xx-sct.c @@ -0,0 +1,465 @@ +/* + * NXP LPC18xx State Configurable Timer - Pulse Width Modulator driver + * + * Copyright (c) 2015 Ariel D'Alessandro <ariel@vanguardiasur.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * Notes + * ===== + * NXP LPC18xx provides a State Configurable Timer (SCT) which can be configured + * as a Pulse Width Modulator. + * + * SCT supports 16 outputs, 16 events and 16 registers. Each event will be + * triggered when its related register matches the SCT counter value, and it + * will set or clear a selected output. + * + * One of the events is preselected to generate the period, thus the maximum + * number of simultaneous channels is limited to 15. Notice that period is + * global to all the channels, thus PWM driver will refuse setting different + * values to it, unless there's only one channel requested. + */ + +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pwm.h> + +/* LPC18xx SCT registers */ +#define LPC18XX_PWM_CONFIG 0x000 +#define LPC18XX_PWM_CONFIG_UNIFY BIT(0) +#define LPC18XX_PWM_CONFIG_NORELOAD BIT(7) + +#define LPC18XX_PWM_CTRL 0x004 +#define LPC18XX_PWM_CTRL_HALT BIT(2) +#define LPC18XX_PWM_BIDIR BIT(4) +#define LPC18XX_PWM_PRE_SHIFT 5 +#define LPC18XX_PWM_PRE_MASK (0xff << LPC18XX_PWM_PRE_SHIFT) +#define LPC18XX_PWM_PRE(x) (x << LPC18XX_PWM_PRE_SHIFT) + +#define LPC18XX_PWM_LIMIT 0x008 + +#define LPC18XX_PWM_RES_BASE 0x058 +#define LPC18XX_PWM_RES_SHIFT(_ch) (_ch * 2) +#define LPC18XX_PWM_RES(_ch, _action) (_action << LPC18XX_PWM_RES_SHIFT(_ch)) +#define LPC18XX_PWM_RES_MASK(_ch) (0x3 << LPC18XX_PWM_RES_SHIFT(_ch)) + +#define LPC18XX_PWM_MATCH_BASE 0x100 +#define LPC18XX_PWM_MATCH(_ch) (LPC18XX_PWM_MATCH_BASE + _ch * 4) + +#define LPC18XX_PWM_MATCHREL_BASE 0x200 +#define LPC18XX_PWM_MATCHREL(_ch) (LPC18XX_PWM_MATCHREL_BASE + _ch * 4) + +#define LPC18XX_PWM_EVSTATEMSK_BASE 0x300 +#define LPC18XX_PWM_EVSTATEMSK(_ch) (LPC18XX_PWM_EVSTATEMSK_BASE + _ch * 8) +#define LPC18XX_PWM_EVSTATEMSK_ALL 0xffffffff + +#define LPC18XX_PWM_EVCTRL_BASE 0x304 +#define LPC18XX_PWM_EVCTRL(_ev) (LPC18XX_PWM_EVCTRL_BASE + _ev * 8) + +#define LPC18XX_PWM_EVCTRL_MATCH(_ch) _ch + +#define LPC18XX_PWM_EVCTRL_COMB_SHIFT 12 +#define LPC18XX_PWM_EVCTRL_COMB_MATCH (0x1 << LPC18XX_PWM_EVCTRL_COMB_SHIFT) + +#define LPC18XX_PWM_OUTPUTSET_BASE 0x500 +#define LPC18XX_PWM_OUTPUTSET(_ch) (LPC18XX_PWM_OUTPUTSET_BASE + _ch * 8) + +#define LPC18XX_PWM_OUTPUTCL_BASE 0x504 +#define LPC18XX_PWM_OUTPUTCL(_ch) (LPC18XX_PWM_OUTPUTCL_BASE + _ch * 8) + +/* LPC18xx SCT unified counter */ +#define LPC18XX_PWM_TIMER_MAX 0xffffffff + +/* LPC18xx SCT events */ +#define LPC18XX_PWM_EVENT_PERIOD 0 +#define LPC18XX_PWM_EVENT_MAX 16 + +/* SCT conflict resolution */ +enum lpc18xx_pwm_res_action { + LPC18XX_PWM_RES_NONE, + LPC18XX_PWM_RES_SET, + LPC18XX_PWM_RES_CLEAR, + LPC18XX_PWM_RES_TOGGLE, +}; + +struct lpc18xx_pwm_data { + unsigned int duty_event; +}; + +struct lpc18xx_pwm_chip { + struct device *dev; + struct pwm_chip chip; + void __iomem *base; + struct clk *pwm_clk; + unsigned long clk_rate; + unsigned int period_ns; + unsigned int min_period_ns; + unsigned int max_period_ns; + unsigned int period_event; + unsigned long event_map; + struct mutex res_lock; + struct mutex period_lock; +}; + +static inline struct lpc18xx_pwm_chip * +to_lpc18xx_pwm_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct lpc18xx_pwm_chip, chip); +} + +static inline void lpc18xx_pwm_writel(struct lpc18xx_pwm_chip *lpc18xx_pwm, + u32 reg, u32 val) +{ + writel(val, lpc18xx_pwm->base + reg); +} + +static inline u32 lpc18xx_pwm_readl(struct lpc18xx_pwm_chip *lpc18xx_pwm, + u32 reg) +{ + return readl(lpc18xx_pwm->base + reg); +} + +static void lpc18xx_pwm_set_conflict_res(struct lpc18xx_pwm_chip *lpc18xx_pwm, + struct pwm_device *pwm, + enum lpc18xx_pwm_res_action action) +{ + u32 val; + + mutex_lock(&lpc18xx_pwm->res_lock); + + /* + * Simultaneous set and clear may happen on an output, that is the case + * when duty_ns == period_ns. LPC18xx SCT allows to set a conflict + * resolution action to be taken in such a case. + */ + val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_RES_BASE); + val &= ~LPC18XX_PWM_RES_MASK(pwm->hwpwm); + val |= LPC18XX_PWM_RES(pwm->hwpwm, action); + lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_RES_BASE, val); + + mutex_unlock(&lpc18xx_pwm->res_lock); +} + +static void lpc18xx_pwm_config_period(struct pwm_chip *chip, int period_ns) +{ + struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip); + u64 val; + + val = (u64)period_ns * lpc18xx_pwm->clk_rate; + do_div(val, NSEC_PER_SEC); + + lpc18xx_pwm_writel(lpc18xx_pwm, + LPC18XX_PWM_MATCH(lpc18xx_pwm->period_event), + (u32)val - 1); + + lpc18xx_pwm_writel(lpc18xx_pwm, + LPC18XX_PWM_MATCHREL(lpc18xx_pwm->period_event), + (u32)val - 1); +} + +static void lpc18xx_pwm_config_duty(struct pwm_chip *chip, + struct pwm_device *pwm, int duty_ns) +{ + struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip); + struct lpc18xx_pwm_data *lpc18xx_data = pwm_get_chip_data(pwm); + u64 val; + + val = (u64)duty_ns * lpc18xx_pwm->clk_rate; + do_div(val, NSEC_PER_SEC); + + lpc18xx_pwm_writel(lpc18xx_pwm, + LPC18XX_PWM_MATCH(lpc18xx_data->duty_event), + (u32)val); + + lpc18xx_pwm_writel(lpc18xx_pwm, + LPC18XX_PWM_MATCHREL(lpc18xx_data->duty_event), + (u32)val); +} + +static int lpc18xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip); + int requested_events, i; + + if (period_ns < lpc18xx_pwm->min_period_ns || + period_ns > lpc18xx_pwm->max_period_ns) { + dev_err(chip->dev, "period %d not in range\n", period_ns); + return -ERANGE; + } + + mutex_lock(&lpc18xx_pwm->period_lock); + + requested_events = bitmap_weight(&lpc18xx_pwm->event_map, + LPC18XX_PWM_EVENT_MAX); + + /* + * The PWM supports only a single period for all PWM channels. + * Once the period is set, it can only be changed if no more than one + * channel is requested at that moment. + */ + if (requested_events > 2 && lpc18xx_pwm->period_ns != period_ns && + lpc18xx_pwm->period_ns) { + dev_err(chip->dev, "conflicting period requested for PWM %u\n", + pwm->hwpwm); + mutex_unlock(&lpc18xx_pwm->period_lock); + return -EBUSY; + } + + if ((requested_events <= 2 && lpc18xx_pwm->period_ns != period_ns) || + !lpc18xx_pwm->period_ns) { + lpc18xx_pwm->period_ns = period_ns; + for (i = 0; i < chip->npwm; i++) + pwm_set_period(&chip->pwms[i], period_ns); + lpc18xx_pwm_config_period(chip, period_ns); + } + + mutex_unlock(&lpc18xx_pwm->period_lock); + + lpc18xx_pwm_config_duty(chip, pwm, duty_ns); + + return 0; +} + +static int lpc18xx_pwm_set_polarity(struct pwm_chip *chip, + struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + return 0; +} + +static int lpc18xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip); + struct lpc18xx_pwm_data *lpc18xx_data = pwm_get_chip_data(pwm); + enum lpc18xx_pwm_res_action res_action; + unsigned int set_event, clear_event; + + lpc18xx_pwm_writel(lpc18xx_pwm, + LPC18XX_PWM_EVCTRL(lpc18xx_data->duty_event), + LPC18XX_PWM_EVCTRL_MATCH(lpc18xx_data->duty_event) | + LPC18XX_PWM_EVCTRL_COMB_MATCH); + + lpc18xx_pwm_writel(lpc18xx_pwm, + LPC18XX_PWM_EVSTATEMSK(lpc18xx_data->duty_event), + LPC18XX_PWM_EVSTATEMSK_ALL); + + if (pwm->polarity == PWM_POLARITY_NORMAL) { + set_event = lpc18xx_pwm->period_event; + clear_event = lpc18xx_data->duty_event; + res_action = LPC18XX_PWM_RES_SET; + } else { + set_event = lpc18xx_data->duty_event; + clear_event = lpc18xx_pwm->period_event; + res_action = LPC18XX_PWM_RES_CLEAR; + } + + lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm), + BIT(set_event)); + lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm), + BIT(clear_event)); + lpc18xx_pwm_set_conflict_res(lpc18xx_pwm, pwm, res_action); + + return 0; +} + +static void lpc18xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip); + struct lpc18xx_pwm_data *lpc18xx_data = pwm_get_chip_data(pwm); + + lpc18xx_pwm_writel(lpc18xx_pwm, + LPC18XX_PWM_EVCTRL(lpc18xx_data->duty_event), 0); + lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm), 0); + lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm), 0); +} + +static int lpc18xx_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip); + struct lpc18xx_pwm_data *lpc18xx_data = pwm_get_chip_data(pwm); + unsigned long event; + + event = find_first_zero_bit(&lpc18xx_pwm->event_map, + LPC18XX_PWM_EVENT_MAX); + + if (event >= LPC18XX_PWM_EVENT_MAX) { + dev_err(lpc18xx_pwm->dev, + "maximum number of simultaneous channels reached\n"); + return -EBUSY; + }; + + set_bit(event, &lpc18xx_pwm->event_map); + lpc18xx_data->duty_event = event; + lpc18xx_pwm_config_duty(chip, pwm, pwm_get_duty_cycle(pwm)); + + return 0; +} + +static void lpc18xx_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip); + struct lpc18xx_pwm_data *lpc18xx_data = pwm_get_chip_data(pwm); + + pwm_disable(pwm); + pwm_set_duty_cycle(pwm, 0); + clear_bit(lpc18xx_data->duty_event, &lpc18xx_pwm->event_map); +} + +static const struct pwm_ops lpc18xx_pwm_ops = { + .config = lpc18xx_pwm_config, + .set_polarity = lpc18xx_pwm_set_polarity, + .enable = lpc18xx_pwm_enable, + .disable = lpc18xx_pwm_disable, + .request = lpc18xx_pwm_request, + .free = lpc18xx_pwm_free, + .owner = THIS_MODULE, +}; + +static const struct of_device_id lpc18xx_pwm_of_match[] = { + { .compatible = "nxp,lpc1850-sct-pwm" }, + {} +}; +MODULE_DEVICE_TABLE(of, lpc18xx_pwm_of_match); + +static int lpc18xx_pwm_probe(struct platform_device *pdev) +{ + struct lpc18xx_pwm_chip *lpc18xx_pwm; + struct pwm_device *pwm; + struct resource *res; + int ret, i; + u64 val; + + lpc18xx_pwm = devm_kzalloc(&pdev->dev, sizeof(*lpc18xx_pwm), + GFP_KERNEL); + if (!lpc18xx_pwm) + return -ENOMEM; + + lpc18xx_pwm->dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + lpc18xx_pwm->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(lpc18xx_pwm->base)) + return PTR_ERR(lpc18xx_pwm->base); + + lpc18xx_pwm->pwm_clk = devm_clk_get(&pdev->dev, "pwm"); + if (IS_ERR(lpc18xx_pwm->pwm_clk)) { + dev_err(&pdev->dev, "failed to get pwm clock\n"); + return PTR_ERR(lpc18xx_pwm->pwm_clk); + } + + ret = clk_prepare_enable(lpc18xx_pwm->pwm_clk); + if (ret < 0) { + dev_err(&pdev->dev, "could not prepare or enable pwm clock\n"); + return ret; + } + + lpc18xx_pwm->clk_rate = clk_get_rate(lpc18xx_pwm->pwm_clk); + + mutex_init(&lpc18xx_pwm->res_lock); + mutex_init(&lpc18xx_pwm->period_lock); + + val = (u64)NSEC_PER_SEC * LPC18XX_PWM_TIMER_MAX; + do_div(val, lpc18xx_pwm->clk_rate); + lpc18xx_pwm->max_period_ns = val; + + lpc18xx_pwm->min_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, + lpc18xx_pwm->clk_rate); + + lpc18xx_pwm->chip.dev = &pdev->dev; + lpc18xx_pwm->chip.ops = &lpc18xx_pwm_ops; + lpc18xx_pwm->chip.base = -1; + lpc18xx_pwm->chip.npwm = 16; + lpc18xx_pwm->chip.of_xlate = of_pwm_xlate_with_flags; + lpc18xx_pwm->chip.of_pwm_n_cells = 3; + + /* SCT counter must be in unify (32 bit) mode */ + lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CONFIG, + LPC18XX_PWM_CONFIG_UNIFY); + + /* + * Everytime the timer counter reaches the period value, the related + * event will be triggered and the counter reset to 0. + */ + set_bit(LPC18XX_PWM_EVENT_PERIOD, &lpc18xx_pwm->event_map); + lpc18xx_pwm->period_event = LPC18XX_PWM_EVENT_PERIOD; + + lpc18xx_pwm_writel(lpc18xx_pwm, + LPC18XX_PWM_EVSTATEMSK(lpc18xx_pwm->period_event), + LPC18XX_PWM_EVSTATEMSK_ALL); + + val = LPC18XX_PWM_EVCTRL_MATCH(lpc18xx_pwm->period_event) | + LPC18XX_PWM_EVCTRL_COMB_MATCH; + lpc18xx_pwm_writel(lpc18xx_pwm, + LPC18XX_PWM_EVCTRL(lpc18xx_pwm->period_event), val); + + lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_LIMIT, + BIT(lpc18xx_pwm->period_event)); + + ret = pwmchip_add(&lpc18xx_pwm->chip); + if (ret < 0) { + dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret); + goto disable_pwmclk; + } + + for (i = 0; i < lpc18xx_pwm->chip.npwm; i++) { + pwm = &lpc18xx_pwm->chip.pwms[i]; + pwm->chip_data = devm_kzalloc(lpc18xx_pwm->dev, + sizeof(struct lpc18xx_pwm_data), + GFP_KERNEL); + if (!pwm->chip_data) { + ret = -ENOMEM; + goto remove_pwmchip; + } + } + + platform_set_drvdata(pdev, lpc18xx_pwm); + + val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_CTRL); + val &= ~LPC18XX_PWM_BIDIR; + val &= ~LPC18XX_PWM_CTRL_HALT; + val &= ~LPC18XX_PWM_PRE_MASK; + val |= LPC18XX_PWM_PRE(0); + lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CTRL, val); + + return 0; + +remove_pwmchip: + pwmchip_remove(&lpc18xx_pwm->chip); +disable_pwmclk: + clk_disable_unprepare(lpc18xx_pwm->pwm_clk); + return ret; +} + +static int lpc18xx_pwm_remove(struct platform_device *pdev) +{ + struct lpc18xx_pwm_chip *lpc18xx_pwm = platform_get_drvdata(pdev); + u32 val; + + val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_CTRL); + lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CTRL, + val | LPC18XX_PWM_CTRL_HALT); + + clk_disable_unprepare(lpc18xx_pwm->pwm_clk); + + return pwmchip_remove(&lpc18xx_pwm->chip); +} + +static struct platform_driver lpc18xx_pwm_driver = { + .driver = { + .name = "lpc18xx-sct-pwm", + .of_match_table = lpc18xx_pwm_of_match, + }, + .probe = lpc18xx_pwm_probe, + .remove = lpc18xx_pwm_remove, +}; +module_platform_driver(lpc18xx_pwm_driver); + +MODULE_AUTHOR("Ariel D'Alessandro <ariel@vanguardiasur.com.ar>"); +MODULE_DESCRIPTION("NXP LPC18xx PWM driver"); +MODULE_LICENSE("GPL v2"); diff --git a/kernel/drivers/pwm/pwm-lpss-pci.c b/kernel/drivers/pwm/pwm-lpss-pci.c index cf20d2bea..7160e8ab3 100644 --- a/kernel/drivers/pwm/pwm-lpss-pci.c +++ b/kernel/drivers/pwm/pwm-lpss-pci.c @@ -13,6 +13,7 @@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/pci.h> +#include <linux/pm_runtime.h> #include "pwm-lpss.h" @@ -33,6 +34,10 @@ static int pwm_lpss_probe_pci(struct pci_dev *pdev, return PTR_ERR(lpwm); pci_set_drvdata(pdev, lpwm); + + pm_runtime_put(&pdev->dev); + pm_runtime_allow(&pdev->dev); + return 0; } @@ -40,14 +45,41 @@ static void pwm_lpss_remove_pci(struct pci_dev *pdev) { struct pwm_lpss_chip *lpwm = pci_get_drvdata(pdev); + pm_runtime_forbid(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + pwm_lpss_remove(lpwm); } +#ifdef CONFIG_PM +static int pwm_lpss_runtime_suspend_pci(struct device *dev) +{ + /* + * The PCI core will handle transition to D3 automatically. We only + * need to provide runtime PM hooks for that to happen. + */ + return 0; +} + +static int pwm_lpss_runtime_resume_pci(struct device *dev) +{ + return 0; +} +#endif + +static const struct dev_pm_ops pwm_lpss_pci_pm = { + SET_RUNTIME_PM_OPS(pwm_lpss_runtime_suspend_pci, + pwm_lpss_runtime_resume_pci, NULL) +}; + static const struct pci_device_id pwm_lpss_pci_ids[] = { + { PCI_VDEVICE(INTEL, 0x0ac8), (unsigned long)&pwm_lpss_bxt_info}, { PCI_VDEVICE(INTEL, 0x0f08), (unsigned long)&pwm_lpss_byt_info}, { PCI_VDEVICE(INTEL, 0x0f09), (unsigned long)&pwm_lpss_byt_info}, + { PCI_VDEVICE(INTEL, 0x1ac8), (unsigned long)&pwm_lpss_bxt_info}, { PCI_VDEVICE(INTEL, 0x2288), (unsigned long)&pwm_lpss_bsw_info}, { PCI_VDEVICE(INTEL, 0x2289), (unsigned long)&pwm_lpss_bsw_info}, + { PCI_VDEVICE(INTEL, 0x5ac8), (unsigned long)&pwm_lpss_bxt_info}, { }, }; MODULE_DEVICE_TABLE(pci, pwm_lpss_pci_ids); @@ -57,6 +89,9 @@ static struct pci_driver pwm_lpss_driver_pci = { .id_table = pwm_lpss_pci_ids, .probe = pwm_lpss_probe_pci, .remove = pwm_lpss_remove_pci, + .driver = { + .pm = &pwm_lpss_pci_pm, + }, }; module_pci_driver(pwm_lpss_driver_pci); diff --git a/kernel/drivers/pwm/pwm-lpss-platform.c b/kernel/drivers/pwm/pwm-lpss-platform.c index 18a9c880a..54433fc6d 100644 --- a/kernel/drivers/pwm/pwm-lpss-platform.c +++ b/kernel/drivers/pwm/pwm-lpss-platform.c @@ -14,6 +14,7 @@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_runtime.h> #include "pwm-lpss.h" @@ -36,6 +37,10 @@ static int pwm_lpss_probe_platform(struct platform_device *pdev) return PTR_ERR(lpwm); platform_set_drvdata(pdev, lpwm); + + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + return 0; } @@ -43,12 +48,14 @@ static int pwm_lpss_remove_platform(struct platform_device *pdev) { struct pwm_lpss_chip *lpwm = platform_get_drvdata(pdev); + pm_runtime_disable(&pdev->dev); return pwm_lpss_remove(lpwm); } static const struct acpi_device_id pwm_lpss_acpi_match[] = { { "80860F09", (unsigned long)&pwm_lpss_byt_info }, { "80862288", (unsigned long)&pwm_lpss_bsw_info }, + { "80865AC8", (unsigned long)&pwm_lpss_bxt_info }, { }, }; MODULE_DEVICE_TABLE(acpi, pwm_lpss_acpi_match); diff --git a/kernel/drivers/pwm/pwm-lpss.c b/kernel/drivers/pwm/pwm-lpss.c index e9798253a..250441040 100644 --- a/kernel/drivers/pwm/pwm-lpss.c +++ b/kernel/drivers/pwm/pwm-lpss.c @@ -16,6 +16,7 @@ #include <linux/io.h> #include <linux/kernel.h> #include <linux/module.h> +#include <linux/pm_runtime.h> #include "pwm-lpss.h" @@ -29,6 +30,9 @@ #define PWM_LIMIT (0x8000 + PWM_DIVISION_CORRECTION) #define NSECS_PER_SEC 1000000000UL +/* Size of each PWM register space if multiple */ +#define PWM_SIZE 0x400 + struct pwm_lpss_chip { struct pwm_chip chip; void __iomem *regs; @@ -37,21 +41,44 @@ struct pwm_lpss_chip { /* BayTrail */ const struct pwm_lpss_boardinfo pwm_lpss_byt_info = { - .clk_rate = 25000000 + .clk_rate = 25000000, + .npwm = 1, }; EXPORT_SYMBOL_GPL(pwm_lpss_byt_info); /* Braswell */ const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = { - .clk_rate = 19200000 + .clk_rate = 19200000, + .npwm = 1, }; EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info); +/* Broxton */ +const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = { + .clk_rate = 19200000, + .npwm = 4, +}; +EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info); + static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip) { return container_of(chip, struct pwm_lpss_chip, chip); } +static inline u32 pwm_lpss_read(const struct pwm_device *pwm) +{ + struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); + + return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); +} + +static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value) +{ + struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); + + writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); +} + static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm, int duty_ns, int period_ns) { @@ -79,38 +106,36 @@ static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm, duty_ns = 1; on_time_div = 255 - (255 * duty_ns / period_ns); - ctrl = readl(lpwm->regs + PWM); + pm_runtime_get_sync(chip->dev); + + ctrl = pwm_lpss_read(pwm); ctrl &= ~(PWM_BASE_UNIT_MASK | PWM_ON_TIME_DIV_MASK); ctrl |= (u16) base_unit << PWM_BASE_UNIT_SHIFT; ctrl |= on_time_div; /* request PWM to update on next cycle */ ctrl |= PWM_SW_UPDATE; - writel(ctrl, lpwm->regs + PWM); + pwm_lpss_write(pwm, ctrl); + + pm_runtime_put(chip->dev); return 0; } static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm) { - struct pwm_lpss_chip *lpwm = to_lpwm(chip); - u32 ctrl; - - ctrl = readl(lpwm->regs + PWM); - writel(ctrl | PWM_ENABLE, lpwm->regs + PWM); - + pm_runtime_get_sync(chip->dev); + pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE); return 0; } static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm) { - struct pwm_lpss_chip *lpwm = to_lpwm(chip); - u32 ctrl; - - ctrl = readl(lpwm->regs + PWM); - writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM); + pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE); + pm_runtime_put(chip->dev); } static const struct pwm_ops pwm_lpss_ops = { + .free = pwm_lpss_disable, .config = pwm_lpss_config, .enable = pwm_lpss_enable, .disable = pwm_lpss_disable, @@ -135,7 +160,7 @@ struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r, lpwm->chip.dev = dev; lpwm->chip.ops = &pwm_lpss_ops; lpwm->chip.base = -1; - lpwm->chip.npwm = 1; + lpwm->chip.npwm = info->npwm; ret = pwmchip_add(&lpwm->chip); if (ret) { @@ -149,11 +174,6 @@ EXPORT_SYMBOL_GPL(pwm_lpss_probe); int pwm_lpss_remove(struct pwm_lpss_chip *lpwm) { - u32 ctrl; - - ctrl = readl(lpwm->regs + PWM); - writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM); - return pwmchip_remove(&lpwm->chip); } EXPORT_SYMBOL_GPL(pwm_lpss_remove); diff --git a/kernel/drivers/pwm/pwm-lpss.h b/kernel/drivers/pwm/pwm-lpss.h index aa041bb1b..e8cf337ae 100644 --- a/kernel/drivers/pwm/pwm-lpss.h +++ b/kernel/drivers/pwm/pwm-lpss.h @@ -20,10 +20,12 @@ struct pwm_lpss_chip; struct pwm_lpss_boardinfo { unsigned long clk_rate; + unsigned int npwm; }; extern const struct pwm_lpss_boardinfo pwm_lpss_byt_info; extern const struct pwm_lpss_boardinfo pwm_lpss_bsw_info; +extern const struct pwm_lpss_boardinfo pwm_lpss_bxt_info; struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r, const struct pwm_lpss_boardinfo *info); diff --git a/kernel/drivers/pwm/pwm-mtk-disp.c b/kernel/drivers/pwm/pwm-mtk-disp.c new file mode 100644 index 000000000..0ad338529 --- /dev/null +++ b/kernel/drivers/pwm/pwm-mtk-disp.c @@ -0,0 +1,243 @@ +/* + * MediaTek display pulse-width-modulation controller driver. + * Copyright (c) 2015 MediaTek Inc. + * Author: YH Huang <yh.huang@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pwm.h> +#include <linux/slab.h> + +#define DISP_PWM_EN 0x00 +#define PWM_ENABLE_MASK BIT(0) + +#define DISP_PWM_COMMIT 0x08 +#define PWM_COMMIT_MASK BIT(0) + +#define DISP_PWM_CON_0 0x10 +#define PWM_CLKDIV_SHIFT 16 +#define PWM_CLKDIV_MAX 0x3ff +#define PWM_CLKDIV_MASK (PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT) + +#define DISP_PWM_CON_1 0x14 +#define PWM_PERIOD_BIT_WIDTH 12 +#define PWM_PERIOD_MASK ((1 << PWM_PERIOD_BIT_WIDTH) - 1) + +#define PWM_HIGH_WIDTH_SHIFT 16 +#define PWM_HIGH_WIDTH_MASK (0x1fff << PWM_HIGH_WIDTH_SHIFT) + +struct mtk_disp_pwm { + struct pwm_chip chip; + struct clk *clk_main; + struct clk *clk_mm; + void __iomem *base; +}; + +static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip) +{ + return container_of(chip, struct mtk_disp_pwm, chip); +} + +static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset, + u32 mask, u32 data) +{ + void __iomem *address = mdp->base + offset; + u32 value; + + value = readl(address); + value &= ~mask; + value |= data; + writel(value, address); +} + +static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip); + u32 clk_div, period, high_width, value; + u64 div, rate; + int err; + + /* + * Find period, high_width and clk_div to suit duty_ns and period_ns. + * Calculate proper div value to keep period value in the bound. + * + * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE + * duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE + * + * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1 + * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1)) + */ + rate = clk_get_rate(mdp->clk_main); + clk_div = div_u64(rate * period_ns, NSEC_PER_SEC) >> + PWM_PERIOD_BIT_WIDTH; + if (clk_div > PWM_CLKDIV_MAX) + return -EINVAL; + + div = NSEC_PER_SEC * (clk_div + 1); + period = div64_u64(rate * period_ns, div); + if (period > 0) + period--; + + high_width = div64_u64(rate * duty_ns, div); + value = period | (high_width << PWM_HIGH_WIDTH_SHIFT); + + err = clk_enable(mdp->clk_main); + if (err < 0) + return err; + + err = clk_enable(mdp->clk_mm); + if (err < 0) { + clk_disable(mdp->clk_main); + return err; + } + + mtk_disp_pwm_update_bits(mdp, DISP_PWM_CON_0, PWM_CLKDIV_MASK, + clk_div << PWM_CLKDIV_SHIFT); + mtk_disp_pwm_update_bits(mdp, DISP_PWM_CON_1, + PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK, value); + mtk_disp_pwm_update_bits(mdp, DISP_PWM_COMMIT, PWM_COMMIT_MASK, 1); + mtk_disp_pwm_update_bits(mdp, DISP_PWM_COMMIT, PWM_COMMIT_MASK, 0); + + clk_disable(mdp->clk_mm); + clk_disable(mdp->clk_main); + + return 0; +} + +static int mtk_disp_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip); + int err; + + err = clk_enable(mdp->clk_main); + if (err < 0) + return err; + + err = clk_enable(mdp->clk_mm); + if (err < 0) { + clk_disable(mdp->clk_main); + return err; + } + + mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, PWM_ENABLE_MASK, 1); + + return 0; +} + +static void mtk_disp_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip); + + mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, PWM_ENABLE_MASK, 0); + + clk_disable(mdp->clk_mm); + clk_disable(mdp->clk_main); +} + +static const struct pwm_ops mtk_disp_pwm_ops = { + .config = mtk_disp_pwm_config, + .enable = mtk_disp_pwm_enable, + .disable = mtk_disp_pwm_disable, + .owner = THIS_MODULE, +}; + +static int mtk_disp_pwm_probe(struct platform_device *pdev) +{ + struct mtk_disp_pwm *mdp; + struct resource *r; + int ret; + + mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL); + if (!mdp) + return -ENOMEM; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mdp->base = devm_ioremap_resource(&pdev->dev, r); + if (IS_ERR(mdp->base)) + return PTR_ERR(mdp->base); + + mdp->clk_main = devm_clk_get(&pdev->dev, "main"); + if (IS_ERR(mdp->clk_main)) + return PTR_ERR(mdp->clk_main); + + mdp->clk_mm = devm_clk_get(&pdev->dev, "mm"); + if (IS_ERR(mdp->clk_mm)) + return PTR_ERR(mdp->clk_mm); + + ret = clk_prepare(mdp->clk_main); + if (ret < 0) + return ret; + + ret = clk_prepare(mdp->clk_mm); + if (ret < 0) + goto disable_clk_main; + + mdp->chip.dev = &pdev->dev; + mdp->chip.ops = &mtk_disp_pwm_ops; + mdp->chip.base = -1; + mdp->chip.npwm = 1; + + ret = pwmchip_add(&mdp->chip); + if (ret < 0) { + dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); + goto disable_clk_mm; + } + + platform_set_drvdata(pdev, mdp); + + return 0; + +disable_clk_mm: + clk_unprepare(mdp->clk_mm); +disable_clk_main: + clk_unprepare(mdp->clk_main); + return ret; +} + +static int mtk_disp_pwm_remove(struct platform_device *pdev) +{ + struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev); + int ret; + + ret = pwmchip_remove(&mdp->chip); + clk_unprepare(mdp->clk_mm); + clk_unprepare(mdp->clk_main); + + return ret; +} + +static const struct of_device_id mtk_disp_pwm_of_match[] = { + { .compatible = "mediatek,mt8173-disp-pwm" }, + { .compatible = "mediatek,mt6595-disp-pwm" }, + { } +}; +MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match); + +static struct platform_driver mtk_disp_pwm_driver = { + .driver = { + .name = "mediatek-disp-pwm", + .of_match_table = mtk_disp_pwm_of_match, + }, + .probe = mtk_disp_pwm_probe, + .remove = mtk_disp_pwm_remove, +}; +module_platform_driver(mtk_disp_pwm_driver); + +MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>"); +MODULE_DESCRIPTION("MediaTek SoC display PWM driver"); +MODULE_LICENSE("GPL v2"); diff --git a/kernel/drivers/pwm/pwm-mxs.c b/kernel/drivers/pwm/pwm-mxs.c index b430811e1..9a596324e 100644 --- a/kernel/drivers/pwm/pwm-mxs.c +++ b/kernel/drivers/pwm/pwm-mxs.c @@ -77,7 +77,7 @@ static int mxs_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * If the PWM channel is disabled, make sure to turn on the clock * before writing the register. Otherwise, keep it enabled. */ - if (!test_bit(PWMF_ENABLED, &pwm->flags)) { + if (!pwm_is_enabled(pwm)) { ret = clk_prepare_enable(mxs->clk); if (ret) return ret; @@ -92,7 +92,7 @@ static int mxs_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, /* * If the PWM is not enabled, turn the clock off again to save power. */ - if (!test_bit(PWMF_ENABLED, &pwm->flags)) + if (!pwm_is_enabled(pwm)) clk_disable_unprepare(mxs->clk); return 0; diff --git a/kernel/drivers/pwm/pwm-pca9685.c b/kernel/drivers/pwm/pwm-pca9685.c index 34b5c275a..117fccf79 100644 --- a/kernel/drivers/pwm/pwm-pca9685.c +++ b/kernel/drivers/pwm/pwm-pca9685.c @@ -2,6 +2,7 @@ * Driver for PCA9685 16-channel 12-bit PWM LED controller * * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * Copyright (C) 2015 Clemens Gruber <clemens.gruber@pqgruber.com> * * based on the pwm-twl-led.c driver * @@ -18,12 +19,23 @@ * this program. If not, see <http://www.gnu.org/licenses/>. */ +#include <linux/acpi.h> #include <linux/i2c.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/property.h> #include <linux/pwm.h> #include <linux/regmap.h> #include <linux/slab.h> +#include <linux/delay.h> + +/* + * Because the PCA9685 has only one prescaler per chip, changing the period of + * one channel affects the period of all 16 PWM outputs! + * However, the ratio between each configured duty cycle and the chip-wide + * period remains constant, because the OFF time is set in proportion to the + * counter range. + */ #define PCA9685_MODE1 0x00 #define PCA9685_MODE2 0x01 @@ -42,10 +54,18 @@ #define PCA9685_ALL_LED_OFF_H 0xFD #define PCA9685_PRESCALE 0xFE +#define PCA9685_PRESCALE_MIN 0x03 /* => max. frequency of 1526 Hz */ +#define PCA9685_PRESCALE_MAX 0xFF /* => min. frequency of 24 Hz */ + +#define PCA9685_COUNTER_RANGE 4096 +#define PCA9685_DEFAULT_PERIOD 5000000 /* Default period_ns = 1/200 Hz */ +#define PCA9685_OSC_CLOCK_MHZ 25 /* Internal oscillator with 25 MHz */ + #define PCA9685_NUMREGS 0xFF #define PCA9685_MAXCHAN 0x10 #define LED_FULL (1 << 4) +#define MODE1_RESTART (1 << 7) #define MODE1_SLEEP (1 << 4) #define MODE2_INVRT (1 << 4) #define MODE2_OUTDRV (1 << 2) @@ -59,6 +79,8 @@ struct pca9685 { struct pwm_chip chip; struct regmap *regmap; int active_cnt; + int duty_ns; + int period_ns; }; static inline struct pca9685 *to_pca(struct pwm_chip *chip) @@ -72,6 +94,47 @@ static int pca9685_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, struct pca9685 *pca = to_pca(chip); unsigned long long duty; unsigned int reg; + int prescale; + + if (period_ns != pca->period_ns) { + prescale = DIV_ROUND_CLOSEST(PCA9685_OSC_CLOCK_MHZ * period_ns, + PCA9685_COUNTER_RANGE * 1000) - 1; + + if (prescale >= PCA9685_PRESCALE_MIN && + prescale <= PCA9685_PRESCALE_MAX) { + /* Put chip into sleep mode */ + regmap_update_bits(pca->regmap, PCA9685_MODE1, + MODE1_SLEEP, MODE1_SLEEP); + + /* Change the chip-wide output frequency */ + regmap_write(pca->regmap, PCA9685_PRESCALE, prescale); + + /* Wake the chip up */ + regmap_update_bits(pca->regmap, PCA9685_MODE1, + MODE1_SLEEP, 0x0); + + /* Wait 500us for the oscillator to be back up */ + udelay(500); + + pca->period_ns = period_ns; + + /* + * If the duty cycle did not change, restart PWM with + * the same duty cycle to period ratio and return. + */ + if (duty_ns == pca->duty_ns) { + regmap_update_bits(pca->regmap, PCA9685_MODE1, + MODE1_RESTART, 0x1); + return 0; + } + } else { + dev_err(chip->dev, + "prescaler not set: period out of bounds!\n"); + return -EINVAL; + } + } + + pca->duty_ns = duty_ns; if (duty_ns < 1) { if (pwm->hwpwm >= PCA9685_MAXCHAN) @@ -85,6 +148,22 @@ static int pca9685_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, } if (duty_ns == period_ns) { + /* Clear both OFF registers */ + if (pwm->hwpwm >= PCA9685_MAXCHAN) + reg = PCA9685_ALL_LED_OFF_L; + else + reg = LED_N_OFF_L(pwm->hwpwm); + + regmap_write(pca->regmap, reg, 0x0); + + if (pwm->hwpwm >= PCA9685_MAXCHAN) + reg = PCA9685_ALL_LED_OFF_H; + else + reg = LED_N_OFF_H(pwm->hwpwm); + + regmap_write(pca->regmap, reg, 0x0); + + /* Set the full ON bit */ if (pwm->hwpwm >= PCA9685_MAXCHAN) reg = PCA9685_ALL_LED_ON_H; else @@ -95,7 +174,7 @@ static int pca9685_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, return 0; } - duty = 4096 * (unsigned long long)duty_ns; + duty = PCA9685_COUNTER_RANGE * (unsigned long long)duty_ns; duty = DIV_ROUND_UP_ULL(duty, period_ns); if (pwm->hwpwm >= PCA9685_MAXCHAN) @@ -112,6 +191,14 @@ static int pca9685_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, regmap_write(pca->regmap, reg, ((int)duty >> 8) & 0xf); + /* Clear the full ON bit, otherwise the set OFF time has no effect */ + if (pwm->hwpwm >= PCA9685_MAXCHAN) + reg = PCA9685_ALL_LED_ON_H; + else + reg = LED_N_ON_H(pwm->hwpwm); + + regmap_write(pca->regmap, reg, 0); + return 0; } @@ -212,7 +299,6 @@ static const struct regmap_config pca9685_regmap_i2c_config = { static int pca9685_pwm_probe(struct i2c_client *client, const struct i2c_device_id *id) { - struct device_node *np = client->dev.of_node; struct pca9685 *pca; int ret; int mode2; @@ -228,17 +314,19 @@ static int pca9685_pwm_probe(struct i2c_client *client, ret); return ret; } + pca->duty_ns = 0; + pca->period_ns = PCA9685_DEFAULT_PERIOD; i2c_set_clientdata(client, pca); regmap_read(pca->regmap, PCA9685_MODE2, &mode2); - if (of_property_read_bool(np, "invert")) + if (device_property_read_bool(&client->dev, "invert")) mode2 |= MODE2_INVRT; else mode2 &= ~MODE2_INVRT; - if (of_property_read_bool(np, "open-drain")) + if (device_property_read_bool(&client->dev, "open-drain")) mode2 &= ~MODE2_OUTDRV; else mode2 |= MODE2_OUTDRV; @@ -276,17 +364,27 @@ static const struct i2c_device_id pca9685_id[] = { }; MODULE_DEVICE_TABLE(i2c, pca9685_id); +#ifdef CONFIG_ACPI +static const struct acpi_device_id pca9685_acpi_ids[] = { + { "INT3492", 0 }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(acpi, pca9685_acpi_ids); +#endif + +#ifdef CONFIG_OF static const struct of_device_id pca9685_dt_ids[] = { { .compatible = "nxp,pca9685-pwm", }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, pca9685_dt_ids); +#endif static struct i2c_driver pca9685_i2c_driver = { .driver = { .name = "pca9685-pwm", - .owner = THIS_MODULE, - .of_match_table = pca9685_dt_ids, + .acpi_match_table = ACPI_PTR(pca9685_acpi_ids), + .of_match_table = of_match_ptr(pca9685_dt_ids), }, .probe = pca9685_pwm_probe, .remove = pca9685_pwm_remove, diff --git a/kernel/drivers/pwm/pwm-rcar.c b/kernel/drivers/pwm/pwm-rcar.c new file mode 100644 index 000000000..6e99a63ff --- /dev/null +++ b/kernel/drivers/pwm/pwm-rcar.c @@ -0,0 +1,274 @@ +/* + * R-Car PWM Timer driver + * + * Copyright (C) 2015 Renesas Electronics Corporation + * + * This is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + */ + +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/pwm.h> +#include <linux/slab.h> + +#define RCAR_PWM_MAX_DIVISION 24 +#define RCAR_PWM_MAX_CYCLE 1023 + +#define RCAR_PWMCR 0x00 +#define RCAR_PWMCR_CC0_MASK 0x000f0000 +#define RCAR_PWMCR_CC0_SHIFT 16 +#define RCAR_PWMCR_CCMD BIT(15) +#define RCAR_PWMCR_SYNC BIT(11) +#define RCAR_PWMCR_SS0 BIT(4) +#define RCAR_PWMCR_EN0 BIT(0) + +#define RCAR_PWMCNT 0x04 +#define RCAR_PWMCNT_CYC0_MASK 0x03ff0000 +#define RCAR_PWMCNT_CYC0_SHIFT 16 +#define RCAR_PWMCNT_PH0_MASK 0x000003ff +#define RCAR_PWMCNT_PH0_SHIFT 0 + +struct rcar_pwm_chip { + struct pwm_chip chip; + void __iomem *base; + struct clk *clk; +}; + +static inline struct rcar_pwm_chip *to_rcar_pwm_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct rcar_pwm_chip, chip); +} + +static void rcar_pwm_write(struct rcar_pwm_chip *rp, u32 data, + unsigned int offset) +{ + writel(data, rp->base + offset); +} + +static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset) +{ + return readl(rp->base + offset); +} + +static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data, + unsigned int offset) +{ + u32 value; + + value = rcar_pwm_read(rp, offset); + value &= ~mask; + value |= data & mask; + rcar_pwm_write(rp, value, offset); +} + +static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns) +{ + unsigned long clk_rate = clk_get_rate(rp->clk); + unsigned long long max; /* max cycle / nanoseconds */ + unsigned int div; + + if (clk_rate == 0) + return -EINVAL; + + for (div = 0; div <= RCAR_PWM_MAX_DIVISION; div++) { + max = (unsigned long long)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE * + (1 << div); + do_div(max, clk_rate); + if (period_ns < max) + break; + } + + return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE; +} + +static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp, + unsigned int div) +{ + u32 value; + + value = rcar_pwm_read(rp, RCAR_PWMCR); + value &= ~(RCAR_PWMCR_CCMD | RCAR_PWMCR_CC0_MASK); + + if (div & 1) + value |= RCAR_PWMCR_CCMD; + + div >>= 1; + + value |= div << RCAR_PWMCR_CC0_SHIFT; + rcar_pwm_write(rp, value, RCAR_PWMCR); +} + +static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns, + int period_ns) +{ + unsigned long long one_cycle, tmp; /* 0.01 nanoseconds */ + unsigned long clk_rate = clk_get_rate(rp->clk); + u32 cyc, ph; + + one_cycle = (unsigned long long)NSEC_PER_SEC * 100ULL * (1 << div); + do_div(one_cycle, clk_rate); + + tmp = period_ns * 100ULL; + do_div(tmp, one_cycle); + cyc = (tmp << RCAR_PWMCNT_CYC0_SHIFT) & RCAR_PWMCNT_CYC0_MASK; + + tmp = duty_ns * 100ULL; + do_div(tmp, one_cycle); + ph = tmp & RCAR_PWMCNT_PH0_MASK; + + /* Avoid prohibited setting */ + if (cyc == 0 || ph == 0) + return -EINVAL; + + rcar_pwm_write(rp, cyc | ph, RCAR_PWMCNT); + + return 0; +} + +static int rcar_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip); + + return clk_prepare_enable(rp->clk); +} + +static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip); + + clk_disable_unprepare(rp->clk); +} + +static int rcar_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip); + int div, ret; + + div = rcar_pwm_get_clock_division(rp, period_ns); + if (div < 0) + return div; + + /* Let the core driver set pwm->period if disabled and duty_ns == 0 */ + if (!test_bit(PWMF_ENABLED, &pwm->flags) && !duty_ns) + return 0; + + rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR); + + ret = rcar_pwm_set_counter(rp, div, duty_ns, period_ns); + if (!ret) + rcar_pwm_set_clock_control(rp, div); + + /* The SYNC should be set to 0 even if rcar_pwm_set_counter failed */ + rcar_pwm_update(rp, RCAR_PWMCR_SYNC, 0, RCAR_PWMCR); + + return ret; +} + +static int rcar_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip); + u32 value; + + /* Don't enable the PWM device if CYC0 or PH0 is 0 */ + value = rcar_pwm_read(rp, RCAR_PWMCNT); + if ((value & RCAR_PWMCNT_CYC0_MASK) == 0 || + (value & RCAR_PWMCNT_PH0_MASK) == 0) + return -EINVAL; + + rcar_pwm_update(rp, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, RCAR_PWMCR); + + return 0; +} + +static void rcar_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip); + + rcar_pwm_update(rp, RCAR_PWMCR_EN0, 0, RCAR_PWMCR); +} + +static const struct pwm_ops rcar_pwm_ops = { + .request = rcar_pwm_request, + .free = rcar_pwm_free, + .config = rcar_pwm_config, + .enable = rcar_pwm_enable, + .disable = rcar_pwm_disable, + .owner = THIS_MODULE, +}; + +static int rcar_pwm_probe(struct platform_device *pdev) +{ + struct rcar_pwm_chip *rcar_pwm; + struct resource *res; + int ret; + + rcar_pwm = devm_kzalloc(&pdev->dev, sizeof(*rcar_pwm), GFP_KERNEL); + if (rcar_pwm == NULL) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + rcar_pwm->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(rcar_pwm->base)) + return PTR_ERR(rcar_pwm->base); + + rcar_pwm->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(rcar_pwm->clk)) { + dev_err(&pdev->dev, "cannot get clock\n"); + return PTR_ERR(rcar_pwm->clk); + } + + platform_set_drvdata(pdev, rcar_pwm); + + rcar_pwm->chip.dev = &pdev->dev; + rcar_pwm->chip.ops = &rcar_pwm_ops; + rcar_pwm->chip.base = -1; + rcar_pwm->chip.npwm = 1; + + ret = pwmchip_add(&rcar_pwm->chip); + if (ret < 0) { + dev_err(&pdev->dev, "failed to register PWM chip: %d\n", ret); + return ret; + } + + pm_runtime_enable(&pdev->dev); + + return 0; +} + +static int rcar_pwm_remove(struct platform_device *pdev) +{ + struct rcar_pwm_chip *rcar_pwm = platform_get_drvdata(pdev); + + pm_runtime_disable(&pdev->dev); + + return pwmchip_remove(&rcar_pwm->chip); +} + +static const struct of_device_id rcar_pwm_of_table[] = { + { .compatible = "renesas,pwm-rcar", }, + { }, +}; +MODULE_DEVICE_TABLE(of, rcar_pwm_of_table); + +static struct platform_driver rcar_pwm_driver = { + .probe = rcar_pwm_probe, + .remove = rcar_pwm_remove, + .driver = { + .name = "pwm-rcar", + .of_match_table = of_match_ptr(rcar_pwm_of_table), + } +}; +module_platform_driver(rcar_pwm_driver); + +MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>"); +MODULE_DESCRIPTION("Renesas PWM Timer Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:pwm-rcar"); diff --git a/kernel/drivers/pwm/pwm-renesas-tpu.c b/kernel/drivers/pwm/pwm-renesas-tpu.c index ee63f9e9d..075c1a764 100644 --- a/kernel/drivers/pwm/pwm-renesas-tpu.c +++ b/kernel/drivers/pwm/pwm-renesas-tpu.c @@ -301,7 +301,7 @@ static int tpu_pwm_config(struct pwm_chip *chip, struct pwm_device *_pwm, pwm->duty = duty; /* If the channel is disabled we're done. */ - if (!test_bit(PWMF_ENABLED, &_pwm->flags)) + if (!pwm_is_enabled(_pwm)) return 0; if (duty_only && pwm->timer_on) { diff --git a/kernel/drivers/pwm/pwm-rockchip.c b/kernel/drivers/pwm/pwm-rockchip.c index 9442df244..7d9cc9049 100644 --- a/kernel/drivers/pwm/pwm-rockchip.c +++ b/kernel/drivers/pwm/pwm-rockchip.c @@ -83,7 +83,7 @@ static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip, PWM_CONTINUOUS; u32 val; - if (pwm->polarity == PWM_POLARITY_INVERSED) + if (pwm_get_polarity(pwm) == PWM_POLARITY_INVERSED) enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE; else enable_conf |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE; diff --git a/kernel/drivers/pwm/pwm-samsung.c b/kernel/drivers/pwm/pwm-samsung.c index ff201e1b9..ada2d326d 100644 --- a/kernel/drivers/pwm/pwm-samsung.c +++ b/kernel/drivers/pwm/pwm-samsung.c @@ -456,6 +456,7 @@ static const struct of_device_id samsung_pwm_matches[] = { { .compatible = "samsung,exynos4210-pwm", .data = &s5p64x0_variant }, {}, }; +MODULE_DEVICE_TABLE(of, samsung_pwm_matches); static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip) { diff --git a/kernel/drivers/pwm/pwm-sun4i.c b/kernel/drivers/pwm/pwm-sun4i.c index cd9dde563..67af9f623 100644 --- a/kernel/drivers/pwm/pwm-sun4i.c +++ b/kernel/drivers/pwm/pwm-sun4i.c @@ -68,6 +68,7 @@ static const u32 prescaler_table[] = { struct sun4i_pwm_data { bool has_prescaler_bypass; bool has_rdy; + unsigned int npwm; }; struct sun4i_pwm_chip { @@ -114,7 +115,7 @@ static int sun4i_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * is not an integer so round it half up instead of * truncating to get less surprising values. */ - div = clk_rate * period_ns + NSEC_PER_SEC/2; + div = clk_rate * period_ns + NSEC_PER_SEC / 2; do_div(div, NSEC_PER_SEC); if (div - 1 > PWM_PRD_MASK) prescaler = 0; @@ -262,11 +263,25 @@ static const struct pwm_ops sun4i_pwm_ops = { static const struct sun4i_pwm_data sun4i_pwm_data_a10 = { .has_prescaler_bypass = false, .has_rdy = false, + .npwm = 2, +}; + +static const struct sun4i_pwm_data sun4i_pwm_data_a10s = { + .has_prescaler_bypass = true, + .has_rdy = true, + .npwm = 2, +}; + +static const struct sun4i_pwm_data sun4i_pwm_data_a13 = { + .has_prescaler_bypass = true, + .has_rdy = true, + .npwm = 1, }; static const struct sun4i_pwm_data sun4i_pwm_data_a20 = { .has_prescaler_bypass = true, .has_rdy = true, + .npwm = 2, }; static const struct of_device_id sun4i_pwm_dt_ids[] = { @@ -274,6 +289,12 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = { .compatible = "allwinner,sun4i-a10-pwm", .data = &sun4i_pwm_data_a10, }, { + .compatible = "allwinner,sun5i-a10s-pwm", + .data = &sun4i_pwm_data_a10s, + }, { + .compatible = "allwinner,sun5i-a13-pwm", + .data = &sun4i_pwm_data_a13, + }, { .compatible = "allwinner,sun7i-a20-pwm", .data = &sun4i_pwm_data_a20, }, { @@ -305,14 +326,14 @@ static int sun4i_pwm_probe(struct platform_device *pdev) if (IS_ERR(pwm->clk)) return PTR_ERR(pwm->clk); + pwm->data = match->data; pwm->chip.dev = &pdev->dev; pwm->chip.ops = &sun4i_pwm_ops; pwm->chip.base = -1; - pwm->chip.npwm = 2; + pwm->chip.npwm = pwm->data->npwm; pwm->chip.can_sleep = true; pwm->chip.of_xlate = of_pwm_xlate_with_flags; pwm->chip.of_pwm_n_cells = 3; - pwm->data = match->data; spin_lock_init(&pwm->ctrl_lock); diff --git a/kernel/drivers/pwm/pwm-tegra.c b/kernel/drivers/pwm/pwm-tegra.c index cabd7d8e0..d4de0607b 100644 --- a/kernel/drivers/pwm/pwm-tegra.c +++ b/kernel/drivers/pwm/pwm-tegra.c @@ -112,7 +112,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * If the PWM channel is disabled, make sure to turn on the clock * before writing the register. Otherwise, keep it enabled. */ - if (!test_bit(PWMF_ENABLED, &pwm->flags)) { + if (!pwm_is_enabled(pwm)) { err = clk_prepare_enable(pc->clk); if (err < 0) return err; @@ -124,7 +124,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, /* * If the PWM is not enabled, turn the clock off again to save power. */ - if (!test_bit(PWMF_ENABLED, &pwm->flags)) + if (!pwm_is_enabled(pwm)) clk_disable_unprepare(pc->clk); return 0; @@ -214,7 +214,7 @@ static int tegra_pwm_remove(struct platform_device *pdev) for (i = 0; i < NUM_PWM; i++) { struct pwm_device *pwm = &pc->chip.pwms[i]; - if (!test_bit(PWMF_ENABLED, &pwm->flags)) + if (!pwm_is_enabled(pwm)) if (clk_prepare_enable(pc->clk) < 0) continue; diff --git a/kernel/drivers/pwm/pwm-tiecap.c b/kernel/drivers/pwm/pwm-tiecap.c index e557befdf..616af764a 100644 --- a/kernel/drivers/pwm/pwm-tiecap.c +++ b/kernel/drivers/pwm/pwm-tiecap.c @@ -97,7 +97,7 @@ static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, writew(reg_val, pc->mmio_base + ECCTL2); - if (!test_bit(PWMF_ENABLED, &pwm->flags)) { + if (!pwm_is_enabled(pwm)) { /* Update active registers if not running */ writel(duty_cycles, pc->mmio_base + CAP2); writel(period_cycles, pc->mmio_base + CAP1); @@ -111,7 +111,7 @@ static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, writel(period_cycles, pc->mmio_base + CAP3); } - if (!test_bit(PWMF_ENABLED, &pwm->flags)) { + if (!pwm_is_enabled(pwm)) { reg_val = readw(pc->mmio_base + ECCTL2); /* Disable APWM mode to put APWM output Low */ reg_val &= ~ECCTL2_APWM_MODE; @@ -179,7 +179,7 @@ static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) static void ecap_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) { - if (test_bit(PWMF_ENABLED, &pwm->flags)) { + if (pwm_is_enabled(pwm)) { dev_warn(chip->dev, "Removing PWM device without disabling\n"); pm_runtime_put_sync(chip->dev); } @@ -306,7 +306,7 @@ static int ecap_pwm_suspend(struct device *dev) ecap_pwm_save_context(pc); /* Disable explicitly if PWM is running */ - if (test_bit(PWMF_ENABLED, &pwm->flags)) + if (pwm_is_enabled(pwm)) pm_runtime_put_sync(dev); return 0; @@ -318,7 +318,7 @@ static int ecap_pwm_resume(struct device *dev) struct pwm_device *pwm = pc->chip.pwms; /* Enable explicitly if PWM was running */ - if (test_bit(PWMF_ENABLED, &pwm->flags)) + if (pwm_is_enabled(pwm)) pm_runtime_get_sync(dev); ecap_pwm_restore_context(pc); diff --git a/kernel/drivers/pwm/pwm-tiehrpwm.c b/kernel/drivers/pwm/pwm-tiehrpwm.c index 694b3cf76..6a41e6601 100644 --- a/kernel/drivers/pwm/pwm-tiehrpwm.c +++ b/kernel/drivers/pwm/pwm-tiehrpwm.c @@ -407,7 +407,7 @@ static void ehrpwm_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) { struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); - if (test_bit(PWMF_ENABLED, &pwm->flags)) { + if (pwm_is_enabled(pwm)) { dev_warn(chip->dev, "Removing PWM device without disabling\n"); pm_runtime_put_sync(chip->dev); } @@ -565,7 +565,7 @@ static int ehrpwm_pwm_suspend(struct device *dev) for (i = 0; i < pc->chip.npwm; i++) { struct pwm_device *pwm = &pc->chip.pwms[i]; - if (!test_bit(PWMF_ENABLED, &pwm->flags)) + if (!pwm_is_enabled(pwm)) continue; /* Disable explicitly if PWM is running */ @@ -582,7 +582,7 @@ static int ehrpwm_pwm_resume(struct device *dev) for (i = 0; i < pc->chip.npwm; i++) { struct pwm_device *pwm = &pc->chip.pwms[i]; - if (!test_bit(PWMF_ENABLED, &pwm->flags)) + if (!pwm_is_enabled(pwm)) continue; /* Enable explicitly if PWM was running */ diff --git a/kernel/drivers/pwm/sysfs.c b/kernel/drivers/pwm/sysfs.c index 4bd0c639e..9c90886f4 100644 --- a/kernel/drivers/pwm/sysfs.c +++ b/kernel/drivers/pwm/sysfs.c @@ -40,18 +40,18 @@ static struct pwm_device *child_to_pwm_device(struct device *child) return export->pwm; } -static ssize_t pwm_period_show(struct device *child, - struct device_attribute *attr, - char *buf) +static ssize_t period_show(struct device *child, + struct device_attribute *attr, + char *buf) { const struct pwm_device *pwm = child_to_pwm_device(child); - return sprintf(buf, "%u\n", pwm->period); + return sprintf(buf, "%u\n", pwm_get_period(pwm)); } -static ssize_t pwm_period_store(struct device *child, - struct device_attribute *attr, - const char *buf, size_t size) +static ssize_t period_store(struct device *child, + struct device_attribute *attr, + const char *buf, size_t size) { struct pwm_device *pwm = child_to_pwm_device(child); unsigned int val; @@ -61,23 +61,23 @@ static ssize_t pwm_period_store(struct device *child, if (ret) return ret; - ret = pwm_config(pwm, pwm->duty_cycle, val); + ret = pwm_config(pwm, pwm_get_duty_cycle(pwm), val); return ret ? : size; } -static ssize_t pwm_duty_cycle_show(struct device *child, - struct device_attribute *attr, - char *buf) +static ssize_t duty_cycle_show(struct device *child, + struct device_attribute *attr, + char *buf) { const struct pwm_device *pwm = child_to_pwm_device(child); - return sprintf(buf, "%u\n", pwm->duty_cycle); + return sprintf(buf, "%u\n", pwm_get_duty_cycle(pwm)); } -static ssize_t pwm_duty_cycle_store(struct device *child, - struct device_attribute *attr, - const char *buf, size_t size) +static ssize_t duty_cycle_store(struct device *child, + struct device_attribute *attr, + const char *buf, size_t size) { struct pwm_device *pwm = child_to_pwm_device(child); unsigned int val; @@ -87,24 +87,23 @@ static ssize_t pwm_duty_cycle_store(struct device *child, if (ret) return ret; - ret = pwm_config(pwm, val, pwm->period); + ret = pwm_config(pwm, val, pwm_get_period(pwm)); return ret ? : size; } -static ssize_t pwm_enable_show(struct device *child, - struct device_attribute *attr, - char *buf) +static ssize_t enable_show(struct device *child, + struct device_attribute *attr, + char *buf) { const struct pwm_device *pwm = child_to_pwm_device(child); - int enabled = test_bit(PWMF_ENABLED, &pwm->flags); - return sprintf(buf, "%d\n", enabled); + return sprintf(buf, "%d\n", pwm_is_enabled(pwm)); } -static ssize_t pwm_enable_store(struct device *child, - struct device_attribute *attr, - const char *buf, size_t size) +static ssize_t enable_store(struct device *child, + struct device_attribute *attr, + const char *buf, size_t size) { struct pwm_device *pwm = child_to_pwm_device(child); int val, ret; @@ -128,18 +127,29 @@ static ssize_t pwm_enable_store(struct device *child, return ret ? : size; } -static ssize_t pwm_polarity_show(struct device *child, - struct device_attribute *attr, - char *buf) +static ssize_t polarity_show(struct device *child, + struct device_attribute *attr, + char *buf) { const struct pwm_device *pwm = child_to_pwm_device(child); + const char *polarity = "unknown"; + + switch (pwm_get_polarity(pwm)) { + case PWM_POLARITY_NORMAL: + polarity = "normal"; + break; - return sprintf(buf, "%s\n", pwm->polarity ? "inversed" : "normal"); + case PWM_POLARITY_INVERSED: + polarity = "inversed"; + break; + } + + return sprintf(buf, "%s\n", polarity); } -static ssize_t pwm_polarity_store(struct device *child, - struct device_attribute *attr, - const char *buf, size_t size) +static ssize_t polarity_store(struct device *child, + struct device_attribute *attr, + const char *buf, size_t size) { struct pwm_device *pwm = child_to_pwm_device(child); enum pwm_polarity polarity; @@ -157,10 +167,10 @@ static ssize_t pwm_polarity_store(struct device *child, return ret ? : size; } -static DEVICE_ATTR(period, 0644, pwm_period_show, pwm_period_store); -static DEVICE_ATTR(duty_cycle, 0644, pwm_duty_cycle_show, pwm_duty_cycle_store); -static DEVICE_ATTR(enable, 0644, pwm_enable_show, pwm_enable_store); -static DEVICE_ATTR(polarity, 0644, pwm_polarity_show, pwm_polarity_store); +static DEVICE_ATTR_RW(period); +static DEVICE_ATTR_RW(duty_cycle); +static DEVICE_ATTR_RW(enable); +static DEVICE_ATTR_RW(polarity); static struct attribute *pwm_attrs[] = { &dev_attr_period.attr, @@ -234,9 +244,9 @@ static int pwm_unexport_child(struct device *parent, struct pwm_device *pwm) return 0; } -static ssize_t pwm_export_store(struct device *parent, - struct device_attribute *attr, - const char *buf, size_t len) +static ssize_t export_store(struct device *parent, + struct device_attribute *attr, + const char *buf, size_t len) { struct pwm_chip *chip = dev_get_drvdata(parent); struct pwm_device *pwm; @@ -260,11 +270,11 @@ static ssize_t pwm_export_store(struct device *parent, return ret ? : len; } -static DEVICE_ATTR(export, 0200, NULL, pwm_export_store); +static DEVICE_ATTR_WO(export); -static ssize_t pwm_unexport_store(struct device *parent, - struct device_attribute *attr, - const char *buf, size_t len) +static ssize_t unexport_store(struct device *parent, + struct device_attribute *attr, + const char *buf, size_t len) { struct pwm_chip *chip = dev_get_drvdata(parent); unsigned int hwpwm; @@ -281,7 +291,7 @@ static ssize_t pwm_unexport_store(struct device *parent, return ret ? : len; } -static DEVICE_ATTR(unexport, 0200, NULL, pwm_unexport_store); +static DEVICE_ATTR_WO(unexport); static ssize_t npwm_show(struct device *parent, struct device_attribute *attr, char *buf) @@ -301,9 +311,9 @@ static struct attribute *pwm_chip_attrs[] = { ATTRIBUTE_GROUPS(pwm_chip); static struct class pwm_class = { - .name = "pwm", - .owner = THIS_MODULE, - .dev_groups = pwm_chip_groups, + .name = "pwm", + .owner = THIS_MODULE, + .dev_groups = pwm_chip_groups, }; static int pwmchip_sysfs_match(struct device *parent, const void *data) |