diff options
Diffstat (limited to 'kernel/drivers/pinctrl/pinctrl-zynq.c')
| -rw-r--r-- | kernel/drivers/pinctrl/pinctrl-zynq.c | 100 |
1 files changed, 83 insertions, 17 deletions
diff --git a/kernel/drivers/pinctrl/pinctrl-zynq.c b/kernel/drivers/pinctrl/pinctrl-zynq.c index 8c51a3c65..d57b5eca7 100644 --- a/kernel/drivers/pinctrl/pinctrl-zynq.c +++ b/kernel/drivers/pinctrl/pinctrl-zynq.c @@ -3,7 +3,7 @@ * * Copyright (C) 2014 Xilinx * - * Sören Brinkmann <soren.brinkmann@xilinx.com> + * Sören Brinkmann <soren.brinkmann@xilinx.com> * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -101,6 +101,8 @@ enum zynq_pinmux_functions { ZYNQ_PMUX_qspi_cs1, ZYNQ_PMUX_spi0, ZYNQ_PMUX_spi1, + ZYNQ_PMUX_spi0_ss, + ZYNQ_PMUX_spi1_ss, ZYNQ_PMUX_sdio0, ZYNQ_PMUX_sdio0_pc, ZYNQ_PMUX_sdio0_cd, @@ -123,7 +125,7 @@ enum zynq_pinmux_functions { ZYNQ_PMUX_MAX_FUNC }; -const struct pinctrl_pin_desc zynq_pins[] = { +static const struct pinctrl_pin_desc zynq_pins[] = { PINCTRL_PIN(0, "MIO0"), PINCTRL_PIN(1, "MIO1"), PINCTRL_PIN(2, "MIO2"), @@ -196,13 +198,35 @@ static const unsigned int qspi0_0_pins[] = {1, 2, 3, 4, 5, 6}; static const unsigned int qspi1_0_pins[] = {9, 10, 11, 12, 13}; static const unsigned int qspi_cs1_pins[] = {0}; static const unsigned int qspi_fbclk_pins[] = {8}; -static const unsigned int spi0_0_pins[] = {16, 17, 18, 19, 20, 21}; -static const unsigned int spi0_1_pins[] = {28, 29, 30, 31, 32, 33}; -static const unsigned int spi0_2_pins[] = {40, 41, 42, 43, 44, 45}; -static const unsigned int spi1_0_pins[] = {10, 11, 12, 13, 14, 15}; -static const unsigned int spi1_1_pins[] = {22, 23, 24, 25, 26, 27}; -static const unsigned int spi1_2_pins[] = {34, 35, 36, 37, 38, 39}; -static const unsigned int spi1_3_pins[] = {46, 47, 48, 49, 40, 51}; +static const unsigned int spi0_0_pins[] = {16, 17, 21}; +static const unsigned int spi0_0_ss0_pins[] = {18}; +static const unsigned int spi0_0_ss1_pins[] = {19}; +static const unsigned int spi0_0_ss2_pins[] = {20,}; +static const unsigned int spi0_1_pins[] = {28, 29, 33}; +static const unsigned int spi0_1_ss0_pins[] = {30}; +static const unsigned int spi0_1_ss1_pins[] = {31}; +static const unsigned int spi0_1_ss2_pins[] = {32}; +static const unsigned int spi0_2_pins[] = {40, 41, 45}; +static const unsigned int spi0_2_ss0_pins[] = {42}; +static const unsigned int spi0_2_ss1_pins[] = {43}; +static const unsigned int spi0_2_ss2_pins[] = {44}; +static const unsigned int spi1_0_pins[] = {10, 11, 12}; +static const unsigned int spi1_0_ss0_pins[] = {13}; +static const unsigned int spi1_0_ss1_pins[] = {14}; +static const unsigned int spi1_0_ss2_pins[] = {15}; +static const unsigned int spi1_1_pins[] = {22, 23, 24}; +static const unsigned int spi1_1_ss0_pins[] = {25}; +static const unsigned int spi1_1_ss1_pins[] = {26}; +static const unsigned int spi1_1_ss2_pins[] = {27}; +static const unsigned int spi1_2_pins[] = {34, 35, 36}; +static const unsigned int spi1_2_ss0_pins[] = {37}; +static const unsigned int spi1_2_ss1_pins[] = {38}; +static const unsigned int spi1_2_ss2_pins[] = {39}; +static const unsigned int spi1_3_pins[] = {46, 47, 48, 49}; +static const unsigned int spi1_3_ss0_pins[] = {49}; +static const unsigned int spi1_3_ss1_pins[] = {50}; +static const unsigned int spi1_3_ss2_pins[] = {51}; + static const unsigned int sdio0_0_pins[] = {16, 17, 18, 19, 20, 21}; static const unsigned int sdio0_1_pins[] = {28, 29, 30, 31, 32, 33}; static const unsigned int sdio0_2_pins[] = {40, 41, 42, 43, 44, 45}; @@ -369,7 +393,7 @@ static const unsigned int usb1_0_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48, .npins = ARRAY_SIZE(nm ## _pins), \ } -struct zynq_pctrl_group zynq_pctrl_groups[] = { +static const struct zynq_pctrl_group zynq_pctrl_groups[] = { DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0), DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0), DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0), @@ -379,12 +403,33 @@ struct zynq_pctrl_group zynq_pctrl_groups[] = { DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk), DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1), DEFINE_ZYNQ_PINCTRL_GRP(spi0_0), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi0_1), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi0_2), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi1_0), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi1_1), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi1_2), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss2), DEFINE_ZYNQ_PINCTRL_GRP(spi1_3), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss0), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss1), + DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss2), DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0), DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1), DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2), @@ -552,6 +597,15 @@ static const char * const spi0_groups[] = {"spi0_0_grp", "spi0_1_grp", "spi0_2_grp"}; static const char * const spi1_groups[] = {"spi1_0_grp", "spi1_1_grp", "spi1_2_grp", "spi1_3_grp"}; +static const char * const spi0_ss_groups[] = {"spi0_0_ss0_grp", + "spi0_0_ss1_grp", "spi0_0_ss2_grp", "spi0_1_ss0_grp", + "spi0_1_ss1_grp", "spi0_1_ss2_grp", "spi0_2_ss0_grp", + "spi0_2_ss1_grp", "spi0_2_ss2_grp"}; +static const char * const spi1_ss_groups[] = {"spi1_0_ss0_grp", + "spi1_0_ss1_grp", "spi1_0_ss2_grp", "spi1_1_ss0_grp", + "spi1_1_ss1_grp", "spi1_1_ss2_grp", "spi1_2_ss0_grp", + "spi1_2_ss1_grp", "spi1_2_ss2_grp", "spi1_3_ss0_grp", + "spi1_3_ss1_grp", "spi1_3_ss2_grp"}; static const char * const sdio0_groups[] = {"sdio0_0_grp", "sdio0_1_grp", "sdio0_2_grp"}; static const char * const sdio1_groups[] = {"sdio1_0_grp", "sdio1_1_grp", @@ -652,10 +706,10 @@ static const char * const sdio1_wp_groups[] = {"gpio0_0_grp", "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp", "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp", "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_wp_grp"}; -static const char * const smc0_nor_groups[] = {"smc0_nor"}; +static const char * const smc0_nor_groups[] = {"smc0_nor_grp"}; static const char * const smc0_nor_cs1_groups[] = {"smc0_nor_cs1_grp"}; static const char * const smc0_nor_addr25_groups[] = {"smc0_nor_addr25_grp"}; -static const char * const smc0_nand_groups[] = {"smc0_nand"}; +static const char * const smc0_nand_groups[] = {"smc0_nand_grp"}; static const char * const can0_groups[] = {"can0_0_grp", "can0_1_grp", "can0_2_grp", "can0_3_grp", "can0_4_grp", "can0_5_grp", "can0_6_grp", "can0_7_grp", "can0_8_grp", "can0_9_grp", @@ -743,6 +797,8 @@ static const struct zynq_pinmux_function zynq_pmux_functions[] = { DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_cs1, 1), DEFINE_ZYNQ_PINMUX_FUNCTION(spi0, 0x50), DEFINE_ZYNQ_PINMUX_FUNCTION(spi1, 0x50), + DEFINE_ZYNQ_PINMUX_FUNCTION(spi0_ss, 0x50), + DEFINE_ZYNQ_PINMUX_FUNCTION(spi1_ss, 0x50), DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40), DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc), DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 0x130, ZYNQ_SDIO_WP_MASK, @@ -1140,8 +1196,8 @@ static int zynq_pinctrl_probe(struct platform_device *pdev) pctrl->nfuncs = ARRAY_SIZE(zynq_pmux_functions); pctrl->pctrl = pinctrl_register(&zynq_desc, &pdev->dev, pctrl); - if (!pctrl->pctrl) - return -ENOMEM; + if (IS_ERR(pctrl->pctrl)) + return PTR_ERR(pctrl->pctrl); platform_set_drvdata(pdev, pctrl); @@ -1150,7 +1206,7 @@ static int zynq_pinctrl_probe(struct platform_device *pdev) return 0; } -int zynq_pinctrl_remove(struct platform_device *pdev) +static int zynq_pinctrl_remove(struct platform_device *pdev) { struct zynq_pinctrl *pctrl = platform_get_drvdata(pdev); @@ -1174,8 +1230,18 @@ static struct platform_driver zynq_pinctrl_driver = { .remove = zynq_pinctrl_remove, }; -module_platform_driver(zynq_pinctrl_driver); +static int __init zynq_pinctrl_init(void) +{ + return platform_driver_register(&zynq_pinctrl_driver); +} +arch_initcall(zynq_pinctrl_init); + +static void __exit zynq_pinctrl_exit(void) +{ + platform_driver_unregister(&zynq_pinctrl_driver); +} +module_exit(zynq_pinctrl_exit); -MODULE_AUTHOR("Sören Brinkmann <soren.brinkmann@xilinx.com>"); +MODULE_AUTHOR("Sören Brinkmann <soren.brinkmann@xilinx.com>"); MODULE_DESCRIPTION("Xilinx Zynq pinctrl driver"); MODULE_LICENSE("GPL"); |