diff options
Diffstat (limited to 'kernel/drivers/gpu/drm/imx')
| -rw-r--r-- | kernel/drivers/gpu/drm/imx/Kconfig | 56 | ||||
| -rw-r--r-- | kernel/drivers/gpu/drm/imx/Makefile | 12 | ||||
| -rw-r--r-- | kernel/drivers/gpu/drm/imx/dw_hdmi-imx.c | 284 | ||||
| -rw-r--r-- | kernel/drivers/gpu/drm/imx/imx-drm-core.c | 644 | ||||
| -rw-r--r-- | kernel/drivers/gpu/drm/imx/imx-drm.h | 56 | ||||
| -rw-r--r-- | kernel/drivers/gpu/drm/imx/imx-ldb.c | 690 | ||||
| -rw-r--r-- | kernel/drivers/gpu/drm/imx/imx-tve.c | 739 | ||||
| -rw-r--r-- | kernel/drivers/gpu/drm/imx/ipuv3-crtc.c | 515 | ||||
| -rw-r--r-- | kernel/drivers/gpu/drm/imx/ipuv3-plane.c | 397 | ||||
| -rw-r--r-- | kernel/drivers/gpu/drm/imx/ipuv3-plane.h | 57 | ||||
| -rw-r--r-- | kernel/drivers/gpu/drm/imx/parallel-display.c | 303 |
11 files changed, 3753 insertions, 0 deletions
diff --git a/kernel/drivers/gpu/drm/imx/Kconfig b/kernel/drivers/gpu/drm/imx/Kconfig new file mode 100644 index 000000000..2b81a417c --- /dev/null +++ b/kernel/drivers/gpu/drm/imx/Kconfig @@ -0,0 +1,56 @@ +config DRM_IMX + tristate "DRM Support for Freescale i.MX" + select DRM_KMS_HELPER + select DRM_KMS_FB_HELPER + select VIDEOMODE_HELPERS + select DRM_GEM_CMA_HELPER + select DRM_KMS_CMA_HELPER + depends on DRM && (ARCH_MXC || ARCH_MULTIPLATFORM) && HAVE_DMA_ATTRS + depends on IMX_IPUV3_CORE + help + enable i.MX graphics support + +config DRM_IMX_FB_HELPER + tristate "provide legacy framebuffer /dev/fb0" + select DRM_KMS_CMA_HELPER + depends on DRM_IMX + help + The DRM framework can provide a legacy /dev/fb0 framebuffer + for your device. This is necessary to get a framebuffer console + and also for applications using the legacy framebuffer API + +config DRM_IMX_PARALLEL_DISPLAY + tristate "Support for parallel displays" + select DRM_PANEL + depends on DRM_IMX + select VIDEOMODE_HELPERS + +config DRM_IMX_TVE + tristate "Support for TV and VGA displays" + depends on DRM_IMX + select REGMAP_MMIO + help + Choose this to enable the internal Television Encoder (TVe) + found on i.MX53 processors. + +config DRM_IMX_LDB + tristate "Support for LVDS displays" + depends on DRM_IMX && MFD_SYSCON + select DRM_PANEL + help + Choose this to enable the internal LVDS Display Bridge (LDB) + found on i.MX53 and i.MX6 processors. + +config DRM_IMX_IPUV3 + tristate + depends on DRM_IMX + depends on IMX_IPUV3_CORE + default y if DRM_IMX=y + default m if DRM_IMX=m + +config DRM_IMX_HDMI + tristate "Freescale i.MX DRM HDMI" + select DRM_DW_HDMI + depends on DRM_IMX + help + Choose this if you want to use HDMI on i.MX6. diff --git a/kernel/drivers/gpu/drm/imx/Makefile b/kernel/drivers/gpu/drm/imx/Makefile new file mode 100644 index 000000000..f3ecd8903 --- /dev/null +++ b/kernel/drivers/gpu/drm/imx/Makefile @@ -0,0 +1,12 @@ + +imxdrm-objs := imx-drm-core.o + +obj-$(CONFIG_DRM_IMX) += imxdrm.o + +obj-$(CONFIG_DRM_IMX_PARALLEL_DISPLAY) += parallel-display.o +obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o +obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o + +imx-ipuv3-crtc-objs := ipuv3-crtc.o ipuv3-plane.o +obj-$(CONFIG_DRM_IMX_IPUV3) += imx-ipuv3-crtc.o +obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o diff --git a/kernel/drivers/gpu/drm/imx/dw_hdmi-imx.c b/kernel/drivers/gpu/drm/imx/dw_hdmi-imx.c new file mode 100644 index 000000000..a3ecf1069 --- /dev/null +++ b/kernel/drivers/gpu/drm/imx/dw_hdmi-imx.c @@ -0,0 +1,284 @@ +/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc. + * + * derived from imx-hdmi.c(renamed to bridge/dw_hdmi.c now) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/component.h> +#include <linux/mfd/syscon.h> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> +#include <drm/bridge/dw_hdmi.h> +#include <video/imx-ipu-v3.h> +#include <linux/regmap.h> +#include <drm/drm_of.h> +#include <drm/drmP.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_edid.h> +#include <drm/drm_encoder_slave.h> + +#include "imx-drm.h" + +struct imx_hdmi { + struct device *dev; + struct drm_encoder encoder; + struct regmap *regmap; +}; + +static const struct dw_hdmi_mpll_config imx_mpll_cfg[] = { + { + 45250000, { + { 0x01e0, 0x0000 }, + { 0x21e1, 0x0000 }, + { 0x41e2, 0x0000 } + }, + }, { + 92500000, { + { 0x0140, 0x0005 }, + { 0x2141, 0x0005 }, + { 0x4142, 0x0005 }, + }, + }, { + 148500000, { + { 0x00a0, 0x000a }, + { 0x20a1, 0x000a }, + { 0x40a2, 0x000a }, + }, + }, { + ~0UL, { + { 0x00a0, 0x000a }, + { 0x2001, 0x000f }, + { 0x4002, 0x000f }, + }, + } +}; + +static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = { + /* pixelclk bpp8 bpp10 bpp12 */ + { + 54000000, { 0x091c, 0x091c, 0x06dc }, + }, { + 58400000, { 0x091c, 0x06dc, 0x06dc }, + }, { + 72000000, { 0x06dc, 0x06dc, 0x091c }, + }, { + 74250000, { 0x06dc, 0x0b5c, 0x091c }, + }, { + 118800000, { 0x091c, 0x091c, 0x06dc }, + }, { + 216000000, { 0x06dc, 0x0b5c, 0x091c }, + }, { + ~0UL, { 0x0000, 0x0000, 0x0000 }, + }, +}; + +static const struct dw_hdmi_phy_config imx_phy_config[] = { + /*pixelclk symbol term vlev */ + { 148500000, 0x800d, 0x0005, 0x01ad}, + { ~0UL, 0x0000, 0x0000, 0x0000} +}; + +static int dw_hdmi_imx_parse_dt(struct imx_hdmi *hdmi) +{ + struct device_node *np = hdmi->dev->of_node; + + hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr"); + if (IS_ERR(hdmi->regmap)) { + dev_err(hdmi->dev, "Unable to get gpr\n"); + return PTR_ERR(hdmi->regmap); + } + + return 0; +} + +static void dw_hdmi_imx_encoder_disable(struct drm_encoder *encoder) +{ +} + +static bool dw_hdmi_imx_encoder_mode_fixup(struct drm_encoder *encoder, + const struct drm_display_mode *mode, + struct drm_display_mode *adj_mode) +{ + return true; +} + +static void dw_hdmi_imx_encoder_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adj_mode) +{ +} + +static void dw_hdmi_imx_encoder_commit(struct drm_encoder *encoder) +{ + struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder); + int mux = imx_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder); + + regmap_update_bits(hdmi->regmap, IOMUXC_GPR3, + IMX6Q_GPR3_HDMI_MUX_CTL_MASK, + mux << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT); +} + +static void dw_hdmi_imx_encoder_prepare(struct drm_encoder *encoder) +{ + imx_drm_set_bus_format(encoder, MEDIA_BUS_FMT_RGB888_1X24); +} + +static struct drm_encoder_helper_funcs dw_hdmi_imx_encoder_helper_funcs = { + .mode_fixup = dw_hdmi_imx_encoder_mode_fixup, + .mode_set = dw_hdmi_imx_encoder_mode_set, + .prepare = dw_hdmi_imx_encoder_prepare, + .commit = dw_hdmi_imx_encoder_commit, + .disable = dw_hdmi_imx_encoder_disable, +}; + +static struct drm_encoder_funcs dw_hdmi_imx_encoder_funcs = { + .destroy = drm_encoder_cleanup, +}; + +static enum drm_mode_status imx6q_hdmi_mode_valid(struct drm_connector *con, + struct drm_display_mode *mode) +{ + if (mode->clock < 13500) + return MODE_CLOCK_LOW; + if (mode->clock > 266000) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + +static enum drm_mode_status imx6dl_hdmi_mode_valid(struct drm_connector *con, + struct drm_display_mode *mode) +{ + if (mode->clock < 13500) + return MODE_CLOCK_LOW; + if (mode->clock > 270000) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + +static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = { + .mpll_cfg = imx_mpll_cfg, + .cur_ctr = imx_cur_ctr, + .phy_config = imx_phy_config, + .dev_type = IMX6Q_HDMI, + .mode_valid = imx6q_hdmi_mode_valid, +}; + +static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = { + .mpll_cfg = imx_mpll_cfg, + .cur_ctr = imx_cur_ctr, + .phy_config = imx_phy_config, + .dev_type = IMX6DL_HDMI, + .mode_valid = imx6dl_hdmi_mode_valid, +}; + +static const struct of_device_id dw_hdmi_imx_dt_ids[] = { + { .compatible = "fsl,imx6q-hdmi", + .data = &imx6q_hdmi_drv_data + }, { + .compatible = "fsl,imx6dl-hdmi", + .data = &imx6dl_hdmi_drv_data + }, + {}, +}; +MODULE_DEVICE_TABLE(of, dw_hdmi_imx_dt_ids); + +static int dw_hdmi_imx_bind(struct device *dev, struct device *master, + void *data) +{ + struct platform_device *pdev = to_platform_device(dev); + const struct dw_hdmi_plat_data *plat_data; + const struct of_device_id *match; + struct drm_device *drm = data; + struct drm_encoder *encoder; + struct imx_hdmi *hdmi; + struct resource *iores; + int irq; + int ret; + + if (!pdev->dev.of_node) + return -ENODEV; + + hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); + if (!hdmi) + return -ENOMEM; + + match = of_match_node(dw_hdmi_imx_dt_ids, pdev->dev.of_node); + plat_data = match->data; + hdmi->dev = &pdev->dev; + encoder = &hdmi->encoder; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!iores) + return -ENXIO; + + platform_set_drvdata(pdev, hdmi); + + encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); + /* + * If we failed to find the CRTC(s) which this encoder is + * supposed to be connected to, it's because the CRTC has + * not been registered yet. Defer probing, and hope that + * the required CRTC is added later. + */ + if (encoder->possible_crtcs == 0) + return -EPROBE_DEFER; + + ret = dw_hdmi_imx_parse_dt(hdmi); + if (ret < 0) + return ret; + + drm_encoder_helper_add(encoder, &dw_hdmi_imx_encoder_helper_funcs); + drm_encoder_init(drm, encoder, &dw_hdmi_imx_encoder_funcs, + DRM_MODE_ENCODER_TMDS); + + return dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data); +} + +static void dw_hdmi_imx_unbind(struct device *dev, struct device *master, + void *data) +{ + return dw_hdmi_unbind(dev, master, data); +} + +static const struct component_ops dw_hdmi_imx_ops = { + .bind = dw_hdmi_imx_bind, + .unbind = dw_hdmi_imx_unbind, +}; + +static int dw_hdmi_imx_probe(struct platform_device *pdev) +{ + return component_add(&pdev->dev, &dw_hdmi_imx_ops); +} + +static int dw_hdmi_imx_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &dw_hdmi_imx_ops); + + return 0; +} + +static struct platform_driver dw_hdmi_imx_platform_driver = { + .probe = dw_hdmi_imx_probe, + .remove = dw_hdmi_imx_remove, + .driver = { + .name = "dwhdmi-imx", + .of_match_table = dw_hdmi_imx_dt_ids, + }, +}; + +module_platform_driver(dw_hdmi_imx_platform_driver); + +MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); +MODULE_DESCRIPTION("IMX6 Specific DW-HDMI Driver Extension"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:dwhdmi-imx"); diff --git a/kernel/drivers/gpu/drm/imx/imx-drm-core.c b/kernel/drivers/gpu/drm/imx/imx-drm-core.c new file mode 100644 index 000000000..74f505b0d --- /dev/null +++ b/kernel/drivers/gpu/drm/imx/imx-drm-core.c @@ -0,0 +1,644 @@ +/* + * Freescale i.MX drm driver + * + * Copyright (C) 2011 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include <linux/component.h> +#include <linux/device.h> +#include <linux/fb.h> +#include <linux/module.h> +#include <linux/of_graph.h> +#include <linux/platform_device.h> +#include <drm/drmP.h> +#include <drm/drm_fb_helper.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_gem_cma_helper.h> +#include <drm/drm_fb_cma_helper.h> +#include <drm/drm_plane_helper.h> +#include <drm/drm_of.h> + +#include "imx-drm.h" + +#define MAX_CRTC 4 + +struct imx_drm_component { + struct device_node *of_node; + struct list_head list; +}; + +struct imx_drm_device { + struct drm_device *drm; + struct imx_drm_crtc *crtc[MAX_CRTC]; + int pipes; + struct drm_fbdev_cma *fbhelper; +}; + +struct imx_drm_crtc { + struct drm_crtc *crtc; + int pipe; + struct imx_drm_crtc_helper_funcs imx_drm_helper_funcs; +}; + +static int legacyfb_depth = 16; +module_param(legacyfb_depth, int, 0444); + +int imx_drm_crtc_id(struct imx_drm_crtc *crtc) +{ + return crtc->pipe; +} +EXPORT_SYMBOL_GPL(imx_drm_crtc_id); + +static void imx_drm_driver_lastclose(struct drm_device *drm) +{ +#if IS_ENABLED(CONFIG_DRM_IMX_FB_HELPER) + struct imx_drm_device *imxdrm = drm->dev_private; + + if (imxdrm->fbhelper) + drm_fbdev_cma_restore_mode(imxdrm->fbhelper); +#endif +} + +static int imx_drm_driver_unload(struct drm_device *drm) +{ +#if IS_ENABLED(CONFIG_DRM_IMX_FB_HELPER) + struct imx_drm_device *imxdrm = drm->dev_private; +#endif + + drm_kms_helper_poll_fini(drm); + +#if IS_ENABLED(CONFIG_DRM_IMX_FB_HELPER) + if (imxdrm->fbhelper) + drm_fbdev_cma_fini(imxdrm->fbhelper); +#endif + + component_unbind_all(drm->dev, drm); + + drm_vblank_cleanup(drm); + drm_mode_config_cleanup(drm); + + platform_set_drvdata(drm->platformdev, NULL); + + return 0; +} + +static struct imx_drm_crtc *imx_drm_find_crtc(struct drm_crtc *crtc) +{ + struct imx_drm_device *imxdrm = crtc->dev->dev_private; + unsigned i; + + for (i = 0; i < MAX_CRTC; i++) + if (imxdrm->crtc[i] && imxdrm->crtc[i]->crtc == crtc) + return imxdrm->crtc[i]; + + return NULL; +} + +int imx_drm_set_bus_format_pins(struct drm_encoder *encoder, u32 bus_format, + int hsync_pin, int vsync_pin) +{ + struct imx_drm_crtc_helper_funcs *helper; + struct imx_drm_crtc *imx_crtc; + + imx_crtc = imx_drm_find_crtc(encoder->crtc); + if (!imx_crtc) + return -EINVAL; + + helper = &imx_crtc->imx_drm_helper_funcs; + if (helper->set_interface_pix_fmt) + return helper->set_interface_pix_fmt(encoder->crtc, + bus_format, hsync_pin, vsync_pin); + return 0; +} +EXPORT_SYMBOL_GPL(imx_drm_set_bus_format_pins); + +int imx_drm_set_bus_format(struct drm_encoder *encoder, u32 bus_format) +{ + return imx_drm_set_bus_format_pins(encoder, bus_format, 2, 3); +} +EXPORT_SYMBOL_GPL(imx_drm_set_bus_format); + +int imx_drm_crtc_vblank_get(struct imx_drm_crtc *imx_drm_crtc) +{ + return drm_vblank_get(imx_drm_crtc->crtc->dev, imx_drm_crtc->pipe); +} +EXPORT_SYMBOL_GPL(imx_drm_crtc_vblank_get); + +void imx_drm_crtc_vblank_put(struct imx_drm_crtc *imx_drm_crtc) +{ + drm_vblank_put(imx_drm_crtc->crtc->dev, imx_drm_crtc->pipe); +} +EXPORT_SYMBOL_GPL(imx_drm_crtc_vblank_put); + +void imx_drm_handle_vblank(struct imx_drm_crtc *imx_drm_crtc) +{ + drm_handle_vblank(imx_drm_crtc->crtc->dev, imx_drm_crtc->pipe); +} +EXPORT_SYMBOL_GPL(imx_drm_handle_vblank); + +static int imx_drm_enable_vblank(struct drm_device *drm, int crtc) +{ + struct imx_drm_device *imxdrm = drm->dev_private; + struct imx_drm_crtc *imx_drm_crtc = imxdrm->crtc[crtc]; + int ret; + + if (!imx_drm_crtc) + return -EINVAL; + + if (!imx_drm_crtc->imx_drm_helper_funcs.enable_vblank) + return -ENOSYS; + + ret = imx_drm_crtc->imx_drm_helper_funcs.enable_vblank( + imx_drm_crtc->crtc); + + return ret; +} + +static void imx_drm_disable_vblank(struct drm_device *drm, int crtc) +{ + struct imx_drm_device *imxdrm = drm->dev_private; + struct imx_drm_crtc *imx_drm_crtc = imxdrm->crtc[crtc]; + + if (!imx_drm_crtc) + return; + + if (!imx_drm_crtc->imx_drm_helper_funcs.disable_vblank) + return; + + imx_drm_crtc->imx_drm_helper_funcs.disable_vblank(imx_drm_crtc->crtc); +} + +static void imx_drm_driver_preclose(struct drm_device *drm, + struct drm_file *file) +{ + int i; + + if (!file->is_master) + return; + + for (i = 0; i < MAX_CRTC; i++) + imx_drm_disable_vblank(drm, i); +} + +static const struct file_operations imx_drm_driver_fops = { + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .unlocked_ioctl = drm_ioctl, + .mmap = drm_gem_cma_mmap, + .poll = drm_poll, + .read = drm_read, + .llseek = noop_llseek, +}; + +void imx_drm_connector_destroy(struct drm_connector *connector) +{ + drm_connector_unregister(connector); + drm_connector_cleanup(connector); +} +EXPORT_SYMBOL_GPL(imx_drm_connector_destroy); + +void imx_drm_encoder_destroy(struct drm_encoder *encoder) +{ + drm_encoder_cleanup(encoder); +} +EXPORT_SYMBOL_GPL(imx_drm_encoder_destroy); + +static void imx_drm_output_poll_changed(struct drm_device *drm) +{ +#if IS_ENABLED(CONFIG_DRM_IMX_FB_HELPER) + struct imx_drm_device *imxdrm = drm->dev_private; + + drm_fbdev_cma_hotplug_event(imxdrm->fbhelper); +#endif +} + +static struct drm_mode_config_funcs imx_drm_mode_config_funcs = { + .fb_create = drm_fb_cma_create, + .output_poll_changed = imx_drm_output_poll_changed, +}; + +/* + * Main DRM initialisation. This binds, initialises and registers + * with DRM the subcomponents of the driver. + */ +static int imx_drm_driver_load(struct drm_device *drm, unsigned long flags) +{ + struct imx_drm_device *imxdrm; + struct drm_connector *connector; + int ret; + + imxdrm = devm_kzalloc(drm->dev, sizeof(*imxdrm), GFP_KERNEL); + if (!imxdrm) + return -ENOMEM; + + imxdrm->drm = drm; + + drm->dev_private = imxdrm; + + /* + * enable drm irq mode. + * - with irq_enabled = true, we can use the vblank feature. + * + * P.S. note that we wouldn't use drm irq handler but + * just specific driver own one instead because + * drm framework supports only one irq handler and + * drivers can well take care of their interrupts + */ + drm->irq_enabled = true; + + /* + * set max width and height as default value(4096x4096). + * this value would be used to check framebuffer size limitation + * at drm_mode_addfb(). + */ + drm->mode_config.min_width = 64; + drm->mode_config.min_height = 64; + drm->mode_config.max_width = 4096; + drm->mode_config.max_height = 4096; + drm->mode_config.funcs = &imx_drm_mode_config_funcs; + + drm_mode_config_init(drm); + + ret = drm_vblank_init(drm, MAX_CRTC); + if (ret) + goto err_kms; + + /* + * with vblank_disable_allowed = true, vblank interrupt will be + * disabled by drm timer once a current process gives up ownership + * of vblank event. (after drm_vblank_put function is called) + */ + drm->vblank_disable_allowed = true; + + platform_set_drvdata(drm->platformdev, drm); + + /* Now try and bind all our sub-components */ + ret = component_bind_all(drm->dev, drm); + if (ret) + goto err_vblank; + + /* + * All components are now added, we can publish the connector sysfs + * entries to userspace. This will generate hotplug events and so + * userspace will expect to be able to access DRM at this point. + */ + list_for_each_entry(connector, &drm->mode_config.connector_list, head) { + ret = drm_connector_register(connector); + if (ret) { + dev_err(drm->dev, + "[CONNECTOR:%d:%s] drm_connector_register failed: %d\n", + connector->base.id, + connector->name, ret); + goto err_unbind; + } + } + + /* + * All components are now initialised, so setup the fb helper. + * The fb helper takes copies of key hardware information, so the + * crtcs/connectors/encoders must not change after this point. + */ +#if IS_ENABLED(CONFIG_DRM_IMX_FB_HELPER) + if (legacyfb_depth != 16 && legacyfb_depth != 32) { + dev_warn(drm->dev, "Invalid legacyfb_depth. Defaulting to 16bpp\n"); + legacyfb_depth = 16; + } + imxdrm->fbhelper = drm_fbdev_cma_init(drm, legacyfb_depth, + drm->mode_config.num_crtc, MAX_CRTC); + if (IS_ERR(imxdrm->fbhelper)) { + ret = PTR_ERR(imxdrm->fbhelper); + imxdrm->fbhelper = NULL; + goto err_unbind; + } +#endif + + drm_kms_helper_poll_init(drm); + + return 0; + +err_unbind: + component_unbind_all(drm->dev, drm); +err_vblank: + drm_vblank_cleanup(drm); +err_kms: + drm_mode_config_cleanup(drm); + + return ret; +} + +/* + * imx_drm_add_crtc - add a new crtc + */ +int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc, + struct imx_drm_crtc **new_crtc, + const struct imx_drm_crtc_helper_funcs *imx_drm_helper_funcs, + struct device_node *port) +{ + struct imx_drm_device *imxdrm = drm->dev_private; + struct imx_drm_crtc *imx_drm_crtc; + int ret; + + /* + * The vblank arrays are dimensioned by MAX_CRTC - we can't + * pass IDs greater than this to those functions. + */ + if (imxdrm->pipes >= MAX_CRTC) + return -EINVAL; + + if (imxdrm->drm->open_count) + return -EBUSY; + + imx_drm_crtc = kzalloc(sizeof(*imx_drm_crtc), GFP_KERNEL); + if (!imx_drm_crtc) + return -ENOMEM; + + imx_drm_crtc->imx_drm_helper_funcs = *imx_drm_helper_funcs; + imx_drm_crtc->pipe = imxdrm->pipes++; + imx_drm_crtc->crtc = crtc; + + crtc->port = port; + + imxdrm->crtc[imx_drm_crtc->pipe] = imx_drm_crtc; + + *new_crtc = imx_drm_crtc; + + ret = drm_mode_crtc_set_gamma_size(imx_drm_crtc->crtc, 256); + if (ret) + goto err_register; + + drm_crtc_helper_add(crtc, + imx_drm_crtc->imx_drm_helper_funcs.crtc_helper_funcs); + + drm_crtc_init(drm, crtc, + imx_drm_crtc->imx_drm_helper_funcs.crtc_funcs); + + return 0; + +err_register: + imxdrm->crtc[imx_drm_crtc->pipe] = NULL; + kfree(imx_drm_crtc); + return ret; +} +EXPORT_SYMBOL_GPL(imx_drm_add_crtc); + +/* + * imx_drm_remove_crtc - remove a crtc + */ +int imx_drm_remove_crtc(struct imx_drm_crtc *imx_drm_crtc) +{ + struct imx_drm_device *imxdrm = imx_drm_crtc->crtc->dev->dev_private; + + drm_crtc_cleanup(imx_drm_crtc->crtc); + + imxdrm->crtc[imx_drm_crtc->pipe] = NULL; + + kfree(imx_drm_crtc); + + return 0; +} +EXPORT_SYMBOL_GPL(imx_drm_remove_crtc); + +int imx_drm_encoder_parse_of(struct drm_device *drm, + struct drm_encoder *encoder, struct device_node *np) +{ + uint32_t crtc_mask = drm_of_find_possible_crtcs(drm, np); + + /* + * If we failed to find the CRTC(s) which this encoder is + * supposed to be connected to, it's because the CRTC has + * not been registered yet. Defer probing, and hope that + * the required CRTC is added later. + */ + if (crtc_mask == 0) + return -EPROBE_DEFER; + + encoder->possible_crtcs = crtc_mask; + + /* FIXME: this is the mask of outputs which can clone this output. */ + encoder->possible_clones = ~0; + + return 0; +} +EXPORT_SYMBOL_GPL(imx_drm_encoder_parse_of); + +/* + * @node: device tree node containing encoder input ports + * @encoder: drm_encoder + */ +int imx_drm_encoder_get_mux_id(struct device_node *node, + struct drm_encoder *encoder) +{ + struct imx_drm_crtc *imx_crtc = imx_drm_find_crtc(encoder->crtc); + struct device_node *ep; + struct of_endpoint endpoint; + struct device_node *port; + int ret; + + if (!node || !imx_crtc) + return -EINVAL; + + for_each_endpoint_of_node(node, ep) { + port = of_graph_get_remote_port(ep); + of_node_put(port); + if (port == imx_crtc->crtc->port) { + ret = of_graph_parse_endpoint(ep, &endpoint); + of_node_put(ep); + return ret ? ret : endpoint.port; + } + } + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(imx_drm_encoder_get_mux_id); + +static const struct drm_ioctl_desc imx_drm_ioctls[] = { + /* none so far */ +}; + +static struct drm_driver imx_drm_driver = { + .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME, + .load = imx_drm_driver_load, + .unload = imx_drm_driver_unload, + .lastclose = imx_drm_driver_lastclose, + .preclose = imx_drm_driver_preclose, + .set_busid = drm_platform_set_busid, + .gem_free_object = drm_gem_cma_free_object, + .gem_vm_ops = &drm_gem_cma_vm_ops, + .dumb_create = drm_gem_cma_dumb_create, + .dumb_map_offset = drm_gem_cma_dumb_map_offset, + .dumb_destroy = drm_gem_dumb_destroy, + + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, + .gem_prime_import = drm_gem_prime_import, + .gem_prime_export = drm_gem_prime_export, + .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, + .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, + .gem_prime_vmap = drm_gem_cma_prime_vmap, + .gem_prime_vunmap = drm_gem_cma_prime_vunmap, + .gem_prime_mmap = drm_gem_cma_prime_mmap, + .get_vblank_counter = drm_vblank_count, + .enable_vblank = imx_drm_enable_vblank, + .disable_vblank = imx_drm_disable_vblank, + .ioctls = imx_drm_ioctls, + .num_ioctls = ARRAY_SIZE(imx_drm_ioctls), + .fops = &imx_drm_driver_fops, + .name = "imx-drm", + .desc = "i.MX DRM graphics", + .date = "20120507", + .major = 1, + .minor = 0, + .patchlevel = 0, +}; + +static int compare_of(struct device *dev, void *data) +{ + struct device_node *np = data; + + /* Special case for LDB, one device for two channels */ + if (of_node_cmp(np->name, "lvds-channel") == 0) { + np = of_get_parent(np); + of_node_put(np); + } + + return dev->of_node == np; +} + +static int imx_drm_bind(struct device *dev) +{ + return drm_platform_init(&imx_drm_driver, to_platform_device(dev)); +} + +static void imx_drm_unbind(struct device *dev) +{ + drm_put_dev(dev_get_drvdata(dev)); +} + +static const struct component_master_ops imx_drm_ops = { + .bind = imx_drm_bind, + .unbind = imx_drm_unbind, +}; + +static int imx_drm_platform_probe(struct platform_device *pdev) +{ + struct device_node *ep, *port, *remote; + struct component_match *match = NULL; + int ret; + int i; + + /* + * Bind the IPU display interface ports first, so that + * imx_drm_encoder_parse_of called from encoder .bind callbacks + * works as expected. + */ + for (i = 0; ; i++) { + port = of_parse_phandle(pdev->dev.of_node, "ports", i); + if (!port) + break; + + component_match_add(&pdev->dev, &match, compare_of, port); + } + + if (i == 0) { + dev_err(&pdev->dev, "missing 'ports' property\n"); + return -ENODEV; + } + + /* Then bind all encoders */ + for (i = 0; ; i++) { + port = of_parse_phandle(pdev->dev.of_node, "ports", i); + if (!port) + break; + + for_each_child_of_node(port, ep) { + remote = of_graph_get_remote_port_parent(ep); + if (!remote || !of_device_is_available(remote)) { + of_node_put(remote); + continue; + } else if (!of_device_is_available(remote->parent)) { + dev_warn(&pdev->dev, "parent device of %s is not available\n", + remote->full_name); + of_node_put(remote); + continue; + } + + component_match_add(&pdev->dev, &match, compare_of, + remote); + of_node_put(remote); + } + of_node_put(port); + } + + ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); + if (ret) + return ret; + + return component_master_add_with_match(&pdev->dev, &imx_drm_ops, match); +} + +static int imx_drm_platform_remove(struct platform_device *pdev) +{ + component_master_del(&pdev->dev, &imx_drm_ops); + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int imx_drm_suspend(struct device *dev) +{ + struct drm_device *drm_dev = dev_get_drvdata(dev); + + /* The drm_dev is NULL before .load hook is called */ + if (drm_dev == NULL) + return 0; + + drm_kms_helper_poll_disable(drm_dev); + + return 0; +} + +static int imx_drm_resume(struct device *dev) +{ + struct drm_device *drm_dev = dev_get_drvdata(dev); + + if (drm_dev == NULL) + return 0; + + drm_helper_resume_force_mode(drm_dev); + drm_kms_helper_poll_enable(drm_dev); + + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(imx_drm_pm_ops, imx_drm_suspend, imx_drm_resume); + +static const struct of_device_id imx_drm_dt_ids[] = { + { .compatible = "fsl,imx-display-subsystem", }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, imx_drm_dt_ids); + +static struct platform_driver imx_drm_pdrv = { + .probe = imx_drm_platform_probe, + .remove = imx_drm_platform_remove, + .driver = { + .name = "imx-drm", + .pm = &imx_drm_pm_ops, + .of_match_table = imx_drm_dt_ids, + }, +}; +module_platform_driver(imx_drm_pdrv); + +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); +MODULE_DESCRIPTION("i.MX drm driver core"); +MODULE_LICENSE("GPL"); diff --git a/kernel/drivers/gpu/drm/imx/imx-drm.h b/kernel/drivers/gpu/drm/imx/imx-drm.h new file mode 100644 index 000000000..28e776d8d --- /dev/null +++ b/kernel/drivers/gpu/drm/imx/imx-drm.h @@ -0,0 +1,56 @@ +#ifndef _IMX_DRM_H_ +#define _IMX_DRM_H_ + +struct device_node; +struct drm_crtc; +struct drm_connector; +struct drm_device; +struct drm_display_mode; +struct drm_encoder; +struct drm_fbdev_cma; +struct drm_framebuffer; +struct imx_drm_crtc; +struct platform_device; + +int imx_drm_crtc_id(struct imx_drm_crtc *crtc); + +struct imx_drm_crtc_helper_funcs { + int (*enable_vblank)(struct drm_crtc *crtc); + void (*disable_vblank)(struct drm_crtc *crtc); + int (*set_interface_pix_fmt)(struct drm_crtc *crtc, + u32 bus_format, int hsync_pin, int vsync_pin); + const struct drm_crtc_helper_funcs *crtc_helper_funcs; + const struct drm_crtc_funcs *crtc_funcs; +}; + +int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc, + struct imx_drm_crtc **new_crtc, + const struct imx_drm_crtc_helper_funcs *imx_helper_funcs, + struct device_node *port); +int imx_drm_remove_crtc(struct imx_drm_crtc *); +int imx_drm_init_drm(struct platform_device *pdev, + int preferred_bpp); +int imx_drm_exit_drm(void); + +int imx_drm_crtc_vblank_get(struct imx_drm_crtc *imx_drm_crtc); +void imx_drm_crtc_vblank_put(struct imx_drm_crtc *imx_drm_crtc); +void imx_drm_handle_vblank(struct imx_drm_crtc *imx_drm_crtc); + +void imx_drm_mode_config_init(struct drm_device *drm); + +struct drm_gem_cma_object *imx_drm_fb_get_obj(struct drm_framebuffer *fb); + +int imx_drm_set_bus_format_pins(struct drm_encoder *encoder, + u32 bus_format, int hsync_pin, int vsync_pin); +int imx_drm_set_bus_format(struct drm_encoder *encoder, + u32 bus_format); + +int imx_drm_encoder_get_mux_id(struct device_node *node, + struct drm_encoder *encoder); +int imx_drm_encoder_parse_of(struct drm_device *drm, + struct drm_encoder *encoder, struct device_node *np); + +void imx_drm_connector_destroy(struct drm_connector *connector); +void imx_drm_encoder_destroy(struct drm_encoder *encoder); + +#endif /* _IMX_DRM_H_ */ diff --git a/kernel/drivers/gpu/drm/imx/imx-ldb.c b/kernel/drivers/gpu/drm/imx/imx-ldb.c new file mode 100644 index 000000000..abacc8f67 --- /dev/null +++ b/kernel/drivers/gpu/drm/imx/imx-ldb.c @@ -0,0 +1,690 @@ +/* + * i.MX drm driver - LVDS display bridge + * + * Copyright (C) 2012 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/clk.h> +#include <linux/component.h> +#include <drm/drmP.h> +#include <drm/drm_fb_helper.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_panel.h> +#include <linux/mfd/syscon.h> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> +#include <linux/of_device.h> +#include <linux/of_graph.h> +#include <video/of_videomode.h> +#include <linux/regmap.h> +#include <linux/videodev2.h> + +#include "imx-drm.h" + +#define DRIVER_NAME "imx-ldb" + +#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0) +#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0) +#define LDB_CH0_MODE_EN_MASK (3 << 0) +#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2) +#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2) +#define LDB_CH1_MODE_EN_MASK (3 << 2) +#define LDB_SPLIT_MODE_EN (1 << 4) +#define LDB_DATA_WIDTH_CH0_24 (1 << 5) +#define LDB_BIT_MAP_CH0_JEIDA (1 << 6) +#define LDB_DATA_WIDTH_CH1_24 (1 << 7) +#define LDB_BIT_MAP_CH1_JEIDA (1 << 8) +#define LDB_DI0_VS_POL_ACT_LOW (1 << 9) +#define LDB_DI1_VS_POL_ACT_LOW (1 << 10) +#define LDB_BGREF_RMODE_INT (1 << 15) + +#define con_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, connector) +#define enc_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, encoder) + +struct imx_ldb; + +struct imx_ldb_channel { + struct imx_ldb *ldb; + struct drm_connector connector; + struct drm_encoder encoder; + struct drm_panel *panel; + struct device_node *child; + int chno; + void *edid; + int edid_len; + struct drm_display_mode mode; + int mode_valid; + int bus_format; +}; + +struct bus_mux { + int reg; + int shift; + int mask; +}; + +struct imx_ldb { + struct regmap *regmap; + struct device *dev; + struct imx_ldb_channel channel[2]; + struct clk *clk[2]; /* our own clock */ + struct clk *clk_sel[4]; /* parent of display clock */ + struct clk *clk_parent[4]; /* original parent of clk_sel */ + struct clk *clk_pll[2]; /* upstream clock we can adjust */ + u32 ldb_ctrl; + const struct bus_mux *lvds_mux; +}; + +static enum drm_connector_status imx_ldb_connector_detect( + struct drm_connector *connector, bool force) +{ + return connector_status_connected; +} + +static int imx_ldb_connector_get_modes(struct drm_connector *connector) +{ + struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector); + int num_modes = 0; + + if (imx_ldb_ch->panel && imx_ldb_ch->panel->funcs && + imx_ldb_ch->panel->funcs->get_modes) { + struct drm_display_info *di = &connector->display_info; + + num_modes = imx_ldb_ch->panel->funcs->get_modes(imx_ldb_ch->panel); + if (!imx_ldb_ch->bus_format && di->num_bus_formats) + imx_ldb_ch->bus_format = di->bus_formats[0]; + if (num_modes > 0) + return num_modes; + } + + if (imx_ldb_ch->edid) { + drm_mode_connector_update_edid_property(connector, + imx_ldb_ch->edid); + num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid); + } + + if (imx_ldb_ch->mode_valid) { + struct drm_display_mode *mode; + + mode = drm_mode_create(connector->dev); + if (!mode) + return -EINVAL; + drm_mode_copy(mode, &imx_ldb_ch->mode); + mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; + drm_mode_probed_add(connector, mode); + num_modes++; + } + + return num_modes; +} + +static struct drm_encoder *imx_ldb_connector_best_encoder( + struct drm_connector *connector) +{ + struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector); + + return &imx_ldb_ch->encoder; +} + +static void imx_ldb_encoder_dpms(struct drm_encoder *encoder, int mode) +{ +} + +static bool imx_ldb_encoder_mode_fixup(struct drm_encoder *encoder, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + return true; +} + +static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno, + unsigned long serial_clk, unsigned long di_clk) +{ + int ret; + + dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__, + clk_get_rate(ldb->clk_pll[chno]), serial_clk); + clk_set_rate(ldb->clk_pll[chno], serial_clk); + + dev_dbg(ldb->dev, "%s after: %ld\n", __func__, + clk_get_rate(ldb->clk_pll[chno])); + + dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__, + clk_get_rate(ldb->clk[chno]), + (long int)di_clk); + clk_set_rate(ldb->clk[chno], di_clk); + + dev_dbg(ldb->dev, "%s after: %ld\n", __func__, + clk_get_rate(ldb->clk[chno])); + + /* set display clock mux to LDB input clock */ + ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]); + if (ret) + dev_err(ldb->dev, + "unable to set di%d parent clock to ldb_di%d\n", mux, + chno); +} + +static void imx_ldb_encoder_prepare(struct drm_encoder *encoder) +{ + struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); + struct imx_ldb *ldb = imx_ldb_ch->ldb; + int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; + u32 bus_format; + + switch (imx_ldb_ch->bus_format) { + default: + dev_warn(ldb->dev, + "could not determine data mapping, default to 18-bit \"spwg\"\n"); + /* fallthrough */ + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: + bus_format = MEDIA_BUS_FMT_RGB666_1X18; + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: + bus_format = MEDIA_BUS_FMT_RGB888_1X24; + if (imx_ldb_ch->chno == 0 || dual) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24; + if (imx_ldb_ch->chno == 1 || dual) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24; + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: + bus_format = MEDIA_BUS_FMT_RGB888_1X24; + if (imx_ldb_ch->chno == 0 || dual) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 | + LDB_BIT_MAP_CH0_JEIDA; + if (imx_ldb_ch->chno == 1 || dual) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 | + LDB_BIT_MAP_CH1_JEIDA; + break; + } + + imx_drm_set_bus_format(encoder, bus_format); +} + +static void imx_ldb_encoder_commit(struct drm_encoder *encoder) +{ + struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); + struct imx_ldb *ldb = imx_ldb_ch->ldb; + int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; + int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder); + + drm_panel_prepare(imx_ldb_ch->panel); + + if (dual) { + clk_prepare_enable(ldb->clk[0]); + clk_prepare_enable(ldb->clk[1]); + } + + if (imx_ldb_ch == &ldb->channel[0] || dual) { + ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; + if (mux == 0 || ldb->lvds_mux) + ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0; + else if (mux == 1) + ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1; + } + if (imx_ldb_ch == &ldb->channel[1] || dual) { + ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; + if (mux == 1 || ldb->lvds_mux) + ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1; + else if (mux == 0) + ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0; + } + + if (ldb->lvds_mux) { + const struct bus_mux *lvds_mux = NULL; + + if (imx_ldb_ch == &ldb->channel[0]) + lvds_mux = &ldb->lvds_mux[0]; + else if (imx_ldb_ch == &ldb->channel[1]) + lvds_mux = &ldb->lvds_mux[1]; + + regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask, + mux << lvds_mux->shift); + } + + regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl); + + drm_panel_enable(imx_ldb_ch->panel); +} + +static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *orig_mode, + struct drm_display_mode *mode) +{ + struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); + struct imx_ldb *ldb = imx_ldb_ch->ldb; + int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; + unsigned long serial_clk; + unsigned long di_clk = mode->clock * 1000; + int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder); + + if (mode->clock > 170000) { + dev_warn(ldb->dev, + "%s: mode exceeds 170 MHz pixel clock\n", __func__); + } + if (mode->clock > 85000 && !dual) { + dev_warn(ldb->dev, + "%s: mode exceeds 85 MHz pixel clock\n", __func__); + } + + if (dual) { + serial_clk = 3500UL * mode->clock; + imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk); + imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk); + } else { + serial_clk = 7000UL * mode->clock; + imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk, + di_clk); + } + + /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */ + if (imx_ldb_ch == &ldb->channel[0]) { + if (mode->flags & DRM_MODE_FLAG_NVSYNC) + ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW; + else if (mode->flags & DRM_MODE_FLAG_PVSYNC) + ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW; + } + if (imx_ldb_ch == &ldb->channel[1]) { + if (mode->flags & DRM_MODE_FLAG_NVSYNC) + ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW; + else if (mode->flags & DRM_MODE_FLAG_PVSYNC) + ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW; + } +} + +static void imx_ldb_encoder_disable(struct drm_encoder *encoder) +{ + struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); + struct imx_ldb *ldb = imx_ldb_ch->ldb; + int mux, ret; + + /* + * imx_ldb_encoder_disable is called by + * drm_helper_disable_unused_functions without + * the encoder being enabled before. + */ + if (imx_ldb_ch == &ldb->channel[0] && + (ldb->ldb_ctrl & LDB_CH0_MODE_EN_MASK) == 0) + return; + else if (imx_ldb_ch == &ldb->channel[1] && + (ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0) + return; + + drm_panel_disable(imx_ldb_ch->panel); + + if (imx_ldb_ch == &ldb->channel[0]) + ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; + else if (imx_ldb_ch == &ldb->channel[1]) + ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; + + regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl); + + if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) { + clk_disable_unprepare(ldb->clk[0]); + clk_disable_unprepare(ldb->clk[1]); + } + + if (ldb->lvds_mux) { + const struct bus_mux *lvds_mux = NULL; + + if (imx_ldb_ch == &ldb->channel[0]) + lvds_mux = &ldb->lvds_mux[0]; + else if (imx_ldb_ch == &ldb->channel[1]) + lvds_mux = &ldb->lvds_mux[1]; + + regmap_read(ldb->regmap, lvds_mux->reg, &mux); + mux &= lvds_mux->mask; + mux >>= lvds_mux->shift; + } else { + mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1; + } + + /* set display clock mux back to original input clock */ + ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]); + if (ret) + dev_err(ldb->dev, + "unable to set di%d parent clock to original parent\n", + mux); + + drm_panel_unprepare(imx_ldb_ch->panel); +} + +static struct drm_connector_funcs imx_ldb_connector_funcs = { + .dpms = drm_helper_connector_dpms, + .fill_modes = drm_helper_probe_single_connector_modes, + .detect = imx_ldb_connector_detect, + .destroy = imx_drm_connector_destroy, +}; + +static struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = { + .get_modes = imx_ldb_connector_get_modes, + .best_encoder = imx_ldb_connector_best_encoder, +}; + +static struct drm_encoder_funcs imx_ldb_encoder_funcs = { + .destroy = imx_drm_encoder_destroy, +}; + +static struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = { + .dpms = imx_ldb_encoder_dpms, + .mode_fixup = imx_ldb_encoder_mode_fixup, + .prepare = imx_ldb_encoder_prepare, + .commit = imx_ldb_encoder_commit, + .mode_set = imx_ldb_encoder_mode_set, + .disable = imx_ldb_encoder_disable, +}; + +static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno) +{ + char clkname[16]; + + snprintf(clkname, sizeof(clkname), "di%d", chno); + ldb->clk[chno] = devm_clk_get(ldb->dev, clkname); + if (IS_ERR(ldb->clk[chno])) + return PTR_ERR(ldb->clk[chno]); + + snprintf(clkname, sizeof(clkname), "di%d_pll", chno); + ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname); + + return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]); +} + +static int imx_ldb_register(struct drm_device *drm, + struct imx_ldb_channel *imx_ldb_ch) +{ + struct imx_ldb *ldb = imx_ldb_ch->ldb; + int ret; + + ret = imx_drm_encoder_parse_of(drm, &imx_ldb_ch->encoder, + imx_ldb_ch->child); + if (ret) + return ret; + + ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno); + if (ret) + return ret; + + if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) { + ret = imx_ldb_get_clk(ldb, 1); + if (ret) + return ret; + } + + drm_encoder_helper_add(&imx_ldb_ch->encoder, + &imx_ldb_encoder_helper_funcs); + drm_encoder_init(drm, &imx_ldb_ch->encoder, &imx_ldb_encoder_funcs, + DRM_MODE_ENCODER_LVDS); + + drm_connector_helper_add(&imx_ldb_ch->connector, + &imx_ldb_connector_helper_funcs); + drm_connector_init(drm, &imx_ldb_ch->connector, + &imx_ldb_connector_funcs, DRM_MODE_CONNECTOR_LVDS); + + if (imx_ldb_ch->panel) + drm_panel_attach(imx_ldb_ch->panel, &imx_ldb_ch->connector); + + drm_mode_connector_attach_encoder(&imx_ldb_ch->connector, + &imx_ldb_ch->encoder); + + return 0; +} + +enum { + LVDS_BIT_MAP_SPWG, + LVDS_BIT_MAP_JEIDA +}; + +struct imx_ldb_bit_mapping { + u32 bus_format; + u32 datawidth; + const char * const mapping; +}; + +static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = { + { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" }, + { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" }, + { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" }, +}; + +static u32 of_get_bus_format(struct device *dev, struct device_node *np) +{ + const char *bm; + u32 datawidth = 0; + int ret, i; + + ret = of_property_read_string(np, "fsl,data-mapping", &bm); + if (ret < 0) + return ret; + + of_property_read_u32(np, "fsl,data-width", &datawidth); + + for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) { + if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) && + datawidth == imx_ldb_bit_mappings[i].datawidth) + return imx_ldb_bit_mappings[i].bus_format; + } + + dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm); + + return -ENOENT; +} + +static struct bus_mux imx6q_lvds_mux[2] = { + { + .reg = IOMUXC_GPR3, + .shift = 6, + .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK, + }, { + .reg = IOMUXC_GPR3, + .shift = 8, + .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK, + } +}; + +/* + * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb", + * of_match_device will walk through this list and take the first entry + * matching any of its compatible values. Therefore, the more generic + * entries (in this case fsl,imx53-ldb) need to be ordered last. + */ +static const struct of_device_id imx_ldb_dt_ids[] = { + { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, }, + { .compatible = "fsl,imx53-ldb", .data = NULL, }, + { } +}; +MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids); + +static int imx_ldb_bind(struct device *dev, struct device *master, void *data) +{ + struct drm_device *drm = data; + struct device_node *np = dev->of_node; + const struct of_device_id *of_id = + of_match_device(imx_ldb_dt_ids, dev); + struct device_node *child; + const u8 *edidp; + struct imx_ldb *imx_ldb; + int dual; + int ret; + int i; + + imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL); + if (!imx_ldb) + return -ENOMEM; + + imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr"); + if (IS_ERR(imx_ldb->regmap)) { + dev_err(dev, "failed to get parent regmap\n"); + return PTR_ERR(imx_ldb->regmap); + } + + imx_ldb->dev = dev; + + if (of_id) + imx_ldb->lvds_mux = of_id->data; + + dual = of_property_read_bool(np, "fsl,dual-channel"); + if (dual) + imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN; + + /* + * There are three different possible clock mux configurations: + * i.MX53: ipu1_di0_sel, ipu1_di1_sel + * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel + * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel + * Map them all to di0_sel...di3_sel. + */ + for (i = 0; i < 4; i++) { + char clkname[16]; + + sprintf(clkname, "di%d_sel", i); + imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname); + if (IS_ERR(imx_ldb->clk_sel[i])) { + ret = PTR_ERR(imx_ldb->clk_sel[i]); + imx_ldb->clk_sel[i] = NULL; + break; + } + + imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]); + } + if (i == 0) + return ret; + + for_each_child_of_node(np, child) { + struct imx_ldb_channel *channel; + struct device_node *port; + + ret = of_property_read_u32(child, "reg", &i); + if (ret || i < 0 || i > 1) + return -EINVAL; + + if (dual && i > 0) { + dev_warn(dev, "dual-channel mode, ignoring second output\n"); + continue; + } + + if (!of_device_is_available(child)) + continue; + + channel = &imx_ldb->channel[i]; + channel->ldb = imx_ldb; + channel->chno = i; + channel->child = child; + + /* + * The output port is port@4 with an external 4-port mux or + * port@2 with the internal 2-port mux. + */ + port = of_graph_get_port_by_id(child, imx_ldb->lvds_mux ? 4 : 2); + if (port) { + struct device_node *endpoint, *remote; + + endpoint = of_get_child_by_name(port, "endpoint"); + if (endpoint) { + remote = of_graph_get_remote_port_parent(endpoint); + if (remote) + channel->panel = of_drm_find_panel(remote); + else + return -EPROBE_DEFER; + if (!channel->panel) { + dev_err(dev, "panel not found: %s\n", + remote->full_name); + return -EPROBE_DEFER; + } + } + } + + edidp = of_get_property(child, "edid", &channel->edid_len); + if (edidp) { + channel->edid = kmemdup(edidp, channel->edid_len, + GFP_KERNEL); + } else if (!channel->panel) { + ret = of_get_drm_display_mode(child, &channel->mode, 0); + if (!ret) + channel->mode_valid = 1; + } + + channel->bus_format = of_get_bus_format(dev, child); + if (channel->bus_format == -EINVAL) { + /* + * If no bus format was specified in the device tree, + * we can still get it from the connected panel later. + */ + if (channel->panel && channel->panel->funcs && + channel->panel->funcs->get_modes) + channel->bus_format = 0; + } + if (channel->bus_format < 0) { + dev_err(dev, "could not determine data mapping: %d\n", + channel->bus_format); + return channel->bus_format; + } + + ret = imx_ldb_register(drm, channel); + if (ret) + return ret; + } + + dev_set_drvdata(dev, imx_ldb); + + return 0; +} + +static void imx_ldb_unbind(struct device *dev, struct device *master, + void *data) +{ + struct imx_ldb *imx_ldb = dev_get_drvdata(dev); + int i; + + for (i = 0; i < 2; i++) { + struct imx_ldb_channel *channel = &imx_ldb->channel[i]; + + if (!channel->connector.funcs) + continue; + + channel->connector.funcs->destroy(&channel->connector); + channel->encoder.funcs->destroy(&channel->encoder); + + kfree(channel->edid); + } +} + +static const struct component_ops imx_ldb_ops = { + .bind = imx_ldb_bind, + .unbind = imx_ldb_unbind, +}; + +static int imx_ldb_probe(struct platform_device *pdev) +{ + return component_add(&pdev->dev, &imx_ldb_ops); +} + +static int imx_ldb_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &imx_ldb_ops); + return 0; +} + +static struct platform_driver imx_ldb_driver = { + .probe = imx_ldb_probe, + .remove = imx_ldb_remove, + .driver = { + .of_match_table = imx_ldb_dt_ids, + .name = DRIVER_NAME, + }, +}; + +module_platform_driver(imx_ldb_driver); + +MODULE_DESCRIPTION("i.MX LVDS driver"); +MODULE_AUTHOR("Sascha Hauer, Pengutronix"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:" DRIVER_NAME); diff --git a/kernel/drivers/gpu/drm/imx/imx-tve.c b/kernel/drivers/gpu/drm/imx/imx-tve.c new file mode 100644 index 000000000..214eceefc --- /dev/null +++ b/kernel/drivers/gpu/drm/imx/imx-tve.c @@ -0,0 +1,739 @@ +/* + * i.MX drm driver - Television Encoder (TVEv2) + * + * Copyright (C) 2013 Philipp Zabel, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/component.h> +#include <linux/module.h> +#include <linux/i2c.h> +#include <linux/regmap.h> +#include <linux/regulator/consumer.h> +#include <linux/spinlock.h> +#include <linux/videodev2.h> +#include <drm/drmP.h> +#include <drm/drm_fb_helper.h> +#include <drm/drm_crtc_helper.h> +#include <video/imx-ipu-v3.h> + +#include "imx-drm.h" + +#define TVE_COM_CONF_REG 0x00 +#define TVE_TVDAC0_CONT_REG 0x28 +#define TVE_TVDAC1_CONT_REG 0x2c +#define TVE_TVDAC2_CONT_REG 0x30 +#define TVE_CD_CONT_REG 0x34 +#define TVE_INT_CONT_REG 0x64 +#define TVE_STAT_REG 0x68 +#define TVE_TST_MODE_REG 0x6c +#define TVE_MV_CONT_REG 0xdc + +/* TVE_COM_CONF_REG */ +#define TVE_SYNC_CH_2_EN BIT(22) +#define TVE_SYNC_CH_1_EN BIT(21) +#define TVE_SYNC_CH_0_EN BIT(20) +#define TVE_TV_OUT_MODE_MASK (0x7 << 12) +#define TVE_TV_OUT_DISABLE (0x0 << 12) +#define TVE_TV_OUT_CVBS_0 (0x1 << 12) +#define TVE_TV_OUT_CVBS_2 (0x2 << 12) +#define TVE_TV_OUT_CVBS_0_2 (0x3 << 12) +#define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12) +#define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12) +#define TVE_TV_OUT_YPBPR (0x6 << 12) +#define TVE_TV_OUT_RGB (0x7 << 12) +#define TVE_TV_STAND_MASK (0xf << 8) +#define TVE_TV_STAND_HD_1080P30 (0xc << 8) +#define TVE_P2I_CONV_EN BIT(7) +#define TVE_INP_VIDEO_FORM BIT(6) +#define TVE_INP_YCBCR_422 (0x0 << 6) +#define TVE_INP_YCBCR_444 (0x1 << 6) +#define TVE_DATA_SOURCE_MASK (0x3 << 4) +#define TVE_DATA_SOURCE_BUS1 (0x0 << 4) +#define TVE_DATA_SOURCE_BUS2 (0x1 << 4) +#define TVE_DATA_SOURCE_EXT (0x2 << 4) +#define TVE_DATA_SOURCE_TESTGEN (0x3 << 4) +#define TVE_IPU_CLK_EN_OFS 3 +#define TVE_IPU_CLK_EN BIT(3) +#define TVE_DAC_SAMP_RATE_OFS 1 +#define TVE_DAC_SAMP_RATE_WIDTH 2 +#define TVE_DAC_SAMP_RATE_MASK (0x3 << 1) +#define TVE_DAC_FULL_RATE (0x0 << 1) +#define TVE_DAC_DIV2_RATE (0x1 << 1) +#define TVE_DAC_DIV4_RATE (0x2 << 1) +#define TVE_EN BIT(0) + +/* TVE_TVDACx_CONT_REG */ +#define TVE_TVDAC_GAIN_MASK (0x3f << 0) + +/* TVE_CD_CONT_REG */ +#define TVE_CD_CH_2_SM_EN BIT(22) +#define TVE_CD_CH_1_SM_EN BIT(21) +#define TVE_CD_CH_0_SM_EN BIT(20) +#define TVE_CD_CH_2_LM_EN BIT(18) +#define TVE_CD_CH_1_LM_EN BIT(17) +#define TVE_CD_CH_0_LM_EN BIT(16) +#define TVE_CD_CH_2_REF_LVL BIT(10) +#define TVE_CD_CH_1_REF_LVL BIT(9) +#define TVE_CD_CH_0_REF_LVL BIT(8) +#define TVE_CD_EN BIT(0) + +/* TVE_INT_CONT_REG */ +#define TVE_FRAME_END_IEN BIT(13) +#define TVE_CD_MON_END_IEN BIT(2) +#define TVE_CD_SM_IEN BIT(1) +#define TVE_CD_LM_IEN BIT(0) + +/* TVE_TST_MODE_REG */ +#define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0) + +#define con_to_tve(x) container_of(x, struct imx_tve, connector) +#define enc_to_tve(x) container_of(x, struct imx_tve, encoder) + +enum { + TVE_MODE_TVOUT, + TVE_MODE_VGA, +}; + +struct imx_tve { + struct drm_connector connector; + struct drm_encoder encoder; + struct device *dev; + spinlock_t lock; /* register lock */ + bool enabled; + int mode; + + struct regmap *regmap; + struct regulator *dac_reg; + struct i2c_adapter *ddc; + struct clk *clk; + struct clk *di_sel_clk; + struct clk_hw clk_hw_di; + struct clk *di_clk; + int vsync_pin; + int hsync_pin; +}; + +static void tve_lock(void *__tve) +__acquires(&tve->lock) +{ + struct imx_tve *tve = __tve; + + spin_lock(&tve->lock); +} + +static void tve_unlock(void *__tve) +__releases(&tve->lock) +{ + struct imx_tve *tve = __tve; + + spin_unlock(&tve->lock); +} + +static void tve_enable(struct imx_tve *tve) +{ + int ret; + + if (!tve->enabled) { + tve->enabled = true; + clk_prepare_enable(tve->clk); + ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, + TVE_IPU_CLK_EN | TVE_EN, + TVE_IPU_CLK_EN | TVE_EN); + } + + /* clear interrupt status register */ + regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff); + + /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */ + if (tve->mode == TVE_MODE_VGA) + regmap_write(tve->regmap, TVE_INT_CONT_REG, 0); + else + regmap_write(tve->regmap, TVE_INT_CONT_REG, + TVE_CD_SM_IEN | + TVE_CD_LM_IEN | + TVE_CD_MON_END_IEN); +} + +static void tve_disable(struct imx_tve *tve) +{ + int ret; + + if (tve->enabled) { + tve->enabled = false; + ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, + TVE_IPU_CLK_EN | TVE_EN, 0); + clk_disable_unprepare(tve->clk); + } +} + +static int tve_setup_tvout(struct imx_tve *tve) +{ + return -ENOTSUPP; +} + +static int tve_setup_vga(struct imx_tve *tve) +{ + unsigned int mask; + unsigned int val; + int ret; + + /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */ + ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG, + TVE_TVDAC_GAIN_MASK, 0x0a); + if (ret) + return ret; + + ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG, + TVE_TVDAC_GAIN_MASK, 0x0a); + if (ret) + return ret; + + ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG, + TVE_TVDAC_GAIN_MASK, 0x0a); + if (ret) + return ret; + + /* set configuration register */ + mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM; + val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444; + mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN; + val |= TVE_TV_STAND_HD_1080P30 | 0; + mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN; + val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN; + ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val); + if (ret) + return ret; + + /* set test mode (as documented) */ + return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG, + TVE_TVDAC_TEST_MODE_MASK, 1); +} + +static enum drm_connector_status imx_tve_connector_detect( + struct drm_connector *connector, bool force) +{ + return connector_status_connected; +} + +static int imx_tve_connector_get_modes(struct drm_connector *connector) +{ + struct imx_tve *tve = con_to_tve(connector); + struct edid *edid; + int ret = 0; + + if (!tve->ddc) + return 0; + + edid = drm_get_edid(connector, tve->ddc); + if (edid) { + drm_mode_connector_update_edid_property(connector, edid); + ret = drm_add_edid_modes(connector, edid); + kfree(edid); + } + + return ret; +} + +static int imx_tve_connector_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + struct imx_tve *tve = con_to_tve(connector); + unsigned long rate; + + /* pixel clock with 2x oversampling */ + rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000; + if (rate == mode->clock) + return MODE_OK; + + /* pixel clock without oversampling */ + rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000; + if (rate == mode->clock) + return MODE_OK; + + dev_warn(tve->dev, "ignoring mode %dx%d\n", + mode->hdisplay, mode->vdisplay); + + return MODE_BAD; +} + +static struct drm_encoder *imx_tve_connector_best_encoder( + struct drm_connector *connector) +{ + struct imx_tve *tve = con_to_tve(connector); + + return &tve->encoder; +} + +static void imx_tve_encoder_dpms(struct drm_encoder *encoder, int mode) +{ + struct imx_tve *tve = enc_to_tve(encoder); + int ret; + + ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, + TVE_TV_OUT_MODE_MASK, TVE_TV_OUT_DISABLE); + if (ret < 0) + dev_err(tve->dev, "failed to disable TVOUT: %d\n", ret); +} + +static bool imx_tve_encoder_mode_fixup(struct drm_encoder *encoder, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + return true; +} + +static void imx_tve_encoder_prepare(struct drm_encoder *encoder) +{ + struct imx_tve *tve = enc_to_tve(encoder); + + tve_disable(tve); + + switch (tve->mode) { + case TVE_MODE_VGA: + imx_drm_set_bus_format_pins(encoder, MEDIA_BUS_FMT_YUV8_1X24, + tve->hsync_pin, tve->vsync_pin); + break; + case TVE_MODE_TVOUT: + imx_drm_set_bus_format(encoder, MEDIA_BUS_FMT_YUV8_1X24); + break; + } +} + +static void imx_tve_encoder_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *orig_mode, + struct drm_display_mode *mode) +{ + struct imx_tve *tve = enc_to_tve(encoder); + unsigned long rounded_rate; + unsigned long rate; + int div = 1; + int ret; + + /* + * FIXME + * we should try 4k * mode->clock first, + * and enable 4x oversampling for lower resolutions + */ + rate = 2000UL * mode->clock; + clk_set_rate(tve->clk, rate); + rounded_rate = clk_get_rate(tve->clk); + if (rounded_rate >= rate) + div = 2; + clk_set_rate(tve->di_clk, rounded_rate / div); + + ret = clk_set_parent(tve->di_sel_clk, tve->di_clk); + if (ret < 0) { + dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n", + ret); + } + + if (tve->mode == TVE_MODE_VGA) + ret = tve_setup_vga(tve); + else + ret = tve_setup_tvout(tve); + if (ret) + dev_err(tve->dev, "failed to set configuration: %d\n", ret); +} + +static void imx_tve_encoder_commit(struct drm_encoder *encoder) +{ + struct imx_tve *tve = enc_to_tve(encoder); + + tve_enable(tve); +} + +static void imx_tve_encoder_disable(struct drm_encoder *encoder) +{ + struct imx_tve *tve = enc_to_tve(encoder); + + tve_disable(tve); +} + +static struct drm_connector_funcs imx_tve_connector_funcs = { + .dpms = drm_helper_connector_dpms, + .fill_modes = drm_helper_probe_single_connector_modes, + .detect = imx_tve_connector_detect, + .destroy = imx_drm_connector_destroy, +}; + +static struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = { + .get_modes = imx_tve_connector_get_modes, + .best_encoder = imx_tve_connector_best_encoder, + .mode_valid = imx_tve_connector_mode_valid, +}; + +static struct drm_encoder_funcs imx_tve_encoder_funcs = { + .destroy = imx_drm_encoder_destroy, +}; + +static struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = { + .dpms = imx_tve_encoder_dpms, + .mode_fixup = imx_tve_encoder_mode_fixup, + .prepare = imx_tve_encoder_prepare, + .mode_set = imx_tve_encoder_mode_set, + .commit = imx_tve_encoder_commit, + .disable = imx_tve_encoder_disable, +}; + +static irqreturn_t imx_tve_irq_handler(int irq, void *data) +{ + struct imx_tve *tve = data; + unsigned int val; + + regmap_read(tve->regmap, TVE_STAT_REG, &val); + + /* clear interrupt status register */ + regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff); + + return IRQ_HANDLED; +} + +static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di); + unsigned int val; + int ret; + + ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val); + if (ret < 0) + return 0; + + switch (val & TVE_DAC_SAMP_RATE_MASK) { + case TVE_DAC_DIV4_RATE: + return parent_rate / 4; + case TVE_DAC_DIV2_RATE: + return parent_rate / 2; + case TVE_DAC_FULL_RATE: + default: + return parent_rate; + } + + return 0; +} + +static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + unsigned long div; + + div = *prate / rate; + if (div >= 4) + return *prate / 4; + else if (div >= 2) + return *prate / 2; + return *prate; +} + +static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di); + unsigned long div; + u32 val; + int ret; + + div = parent_rate / rate; + if (div >= 4) + val = TVE_DAC_DIV4_RATE; + else if (div >= 2) + val = TVE_DAC_DIV2_RATE; + else + val = TVE_DAC_FULL_RATE; + + ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, + TVE_DAC_SAMP_RATE_MASK, val); + + if (ret < 0) { + dev_err(tve->dev, "failed to set divider: %d\n", ret); + return ret; + } + + return 0; +} + +static struct clk_ops clk_tve_di_ops = { + .round_rate = clk_tve_di_round_rate, + .set_rate = clk_tve_di_set_rate, + .recalc_rate = clk_tve_di_recalc_rate, +}; + +static int tve_clk_init(struct imx_tve *tve, void __iomem *base) +{ + const char *tve_di_parent[1]; + struct clk_init_data init = { + .name = "tve_di", + .ops = &clk_tve_di_ops, + .num_parents = 1, + .flags = 0, + }; + + tve_di_parent[0] = __clk_get_name(tve->clk); + init.parent_names = (const char **)&tve_di_parent; + + tve->clk_hw_di.init = &init; + tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di); + if (IS_ERR(tve->di_clk)) { + dev_err(tve->dev, "failed to register TVE output clock: %ld\n", + PTR_ERR(tve->di_clk)); + return PTR_ERR(tve->di_clk); + } + + return 0; +} + +static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve) +{ + int encoder_type; + int ret; + + encoder_type = tve->mode == TVE_MODE_VGA ? + DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC; + + ret = imx_drm_encoder_parse_of(drm, &tve->encoder, + tve->dev->of_node); + if (ret) + return ret; + + drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs); + drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs, + encoder_type); + + drm_connector_helper_add(&tve->connector, + &imx_tve_connector_helper_funcs); + drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs, + DRM_MODE_CONNECTOR_VGA); + + drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder); + + return 0; +} + +static bool imx_tve_readable_reg(struct device *dev, unsigned int reg) +{ + return (reg % 4 == 0) && (reg <= 0xdc); +} + +static struct regmap_config tve_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + + .readable_reg = imx_tve_readable_reg, + + .lock = tve_lock, + .unlock = tve_unlock, + + .max_register = 0xdc, +}; + +static const char * const imx_tve_modes[] = { + [TVE_MODE_TVOUT] = "tvout", + [TVE_MODE_VGA] = "vga", +}; + +static const int of_get_tve_mode(struct device_node *np) +{ + const char *bm; + int ret, i; + + ret = of_property_read_string(np, "fsl,tve-mode", &bm); + if (ret < 0) + return ret; + + for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++) + if (!strcasecmp(bm, imx_tve_modes[i])) + return i; + + return -EINVAL; +} + +static int imx_tve_bind(struct device *dev, struct device *master, void *data) +{ + struct platform_device *pdev = to_platform_device(dev); + struct drm_device *drm = data; + struct device_node *np = dev->of_node; + struct device_node *ddc_node; + struct imx_tve *tve; + struct resource *res; + void __iomem *base; + unsigned int val; + int irq; + int ret; + + tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL); + if (!tve) + return -ENOMEM; + + tve->dev = dev; + spin_lock_init(&tve->lock); + + ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); + if (ddc_node) { + tve->ddc = of_find_i2c_adapter_by_node(ddc_node); + of_node_put(ddc_node); + } + + tve->mode = of_get_tve_mode(np); + if (tve->mode != TVE_MODE_VGA) { + dev_err(dev, "only VGA mode supported, currently\n"); + return -EINVAL; + } + + if (tve->mode == TVE_MODE_VGA) { + ret = of_property_read_u32(np, "fsl,hsync-pin", + &tve->hsync_pin); + + if (ret < 0) { + dev_err(dev, "failed to get vsync pin\n"); + return ret; + } + + ret |= of_property_read_u32(np, "fsl,vsync-pin", + &tve->vsync_pin); + + if (ret < 0) { + dev_err(dev, "failed to get vsync pin\n"); + return ret; + } + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + tve_regmap_config.lock_arg = tve; + tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base, + &tve_regmap_config); + if (IS_ERR(tve->regmap)) { + dev_err(dev, "failed to init regmap: %ld\n", + PTR_ERR(tve->regmap)); + return PTR_ERR(tve->regmap); + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "failed to get irq\n"); + return irq; + } + + ret = devm_request_threaded_irq(dev, irq, NULL, + imx_tve_irq_handler, IRQF_ONESHOT, + "imx-tve", tve); + if (ret < 0) { + dev_err(dev, "failed to request irq: %d\n", ret); + return ret; + } + + tve->dac_reg = devm_regulator_get(dev, "dac"); + if (!IS_ERR(tve->dac_reg)) { + regulator_set_voltage(tve->dac_reg, 2750000, 2750000); + ret = regulator_enable(tve->dac_reg); + if (ret) + return ret; + } + + tve->clk = devm_clk_get(dev, "tve"); + if (IS_ERR(tve->clk)) { + dev_err(dev, "failed to get high speed tve clock: %ld\n", + PTR_ERR(tve->clk)); + return PTR_ERR(tve->clk); + } + + /* this is the IPU DI clock input selector, can be parented to tve_di */ + tve->di_sel_clk = devm_clk_get(dev, "di_sel"); + if (IS_ERR(tve->di_sel_clk)) { + dev_err(dev, "failed to get ipu di mux clock: %ld\n", + PTR_ERR(tve->di_sel_clk)); + return PTR_ERR(tve->di_sel_clk); + } + + ret = tve_clk_init(tve, base); + if (ret < 0) + return ret; + + ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val); + if (ret < 0) { + dev_err(dev, "failed to read configuration register: %d\n", + ret); + return ret; + } + if (val != 0x00100000) { + dev_err(dev, "configuration register default value indicates this is not a TVEv2\n"); + return -ENODEV; + } + + /* disable cable detection for VGA mode */ + ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0); + if (ret) + return ret; + + ret = imx_tve_register(drm, tve); + if (ret) + return ret; + + dev_set_drvdata(dev, tve); + + return 0; +} + +static void imx_tve_unbind(struct device *dev, struct device *master, + void *data) +{ + struct imx_tve *tve = dev_get_drvdata(dev); + + tve->connector.funcs->destroy(&tve->connector); + tve->encoder.funcs->destroy(&tve->encoder); + + if (!IS_ERR(tve->dac_reg)) + regulator_disable(tve->dac_reg); +} + +static const struct component_ops imx_tve_ops = { + .bind = imx_tve_bind, + .unbind = imx_tve_unbind, +}; + +static int imx_tve_probe(struct platform_device *pdev) +{ + return component_add(&pdev->dev, &imx_tve_ops); +} + +static int imx_tve_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &imx_tve_ops); + return 0; +} + +static const struct of_device_id imx_tve_dt_ids[] = { + { .compatible = "fsl,imx53-tve", }, + { /* sentinel */ } +}; + +static struct platform_driver imx_tve_driver = { + .probe = imx_tve_probe, + .remove = imx_tve_remove, + .driver = { + .of_match_table = imx_tve_dt_ids, + .name = "imx-tve", + }, +}; + +module_platform_driver(imx_tve_driver); + +MODULE_DESCRIPTION("i.MX Television Encoder driver"); +MODULE_AUTHOR("Philipp Zabel, Pengutronix"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:imx-tve"); diff --git a/kernel/drivers/gpu/drm/imx/ipuv3-crtc.c b/kernel/drivers/gpu/drm/imx/ipuv3-crtc.c new file mode 100644 index 000000000..7bc8301fa --- /dev/null +++ b/kernel/drivers/gpu/drm/imx/ipuv3-crtc.c @@ -0,0 +1,515 @@ +/* + * i.MX IPUv3 Graphics driver + * + * Copyright (C) 2011 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/component.h> +#include <linux/module.h> +#include <linux/export.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <drm/drmP.h> +#include <drm/drm_crtc_helper.h> +#include <linux/fb.h> +#include <linux/clk.h> +#include <linux/errno.h> +#include <drm/drm_gem_cma_helper.h> +#include <drm/drm_fb_cma_helper.h> + +#include <video/imx-ipu-v3.h> +#include "imx-drm.h" +#include "ipuv3-plane.h" + +#define DRIVER_DESC "i.MX IPUv3 Graphics" + +struct ipu_crtc { + struct device *dev; + struct drm_crtc base; + struct imx_drm_crtc *imx_crtc; + + /* plane[0] is the full plane, plane[1] is the partial plane */ + struct ipu_plane *plane[2]; + + struct ipu_dc *dc; + struct ipu_di *di; + int enabled; + struct drm_pending_vblank_event *page_flip_event; + struct drm_framebuffer *newfb; + int irq; + u32 bus_format; + int di_hsync_pin; + int di_vsync_pin; +}; + +#define to_ipu_crtc(x) container_of(x, struct ipu_crtc, base) + +static void ipu_fb_enable(struct ipu_crtc *ipu_crtc) +{ + struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); + + if (ipu_crtc->enabled) + return; + + ipu_dc_enable(ipu); + ipu_plane_enable(ipu_crtc->plane[0]); + /* Start DC channel and DI after IDMAC */ + ipu_dc_enable_channel(ipu_crtc->dc); + ipu_di_enable(ipu_crtc->di); + + ipu_crtc->enabled = 1; +} + +static void ipu_fb_disable(struct ipu_crtc *ipu_crtc) +{ + struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); + + if (!ipu_crtc->enabled) + return; + + /* Stop DC channel and DI before IDMAC */ + ipu_dc_disable_channel(ipu_crtc->dc); + ipu_di_disable(ipu_crtc->di); + ipu_plane_disable(ipu_crtc->plane[0]); + ipu_dc_disable(ipu); + + ipu_crtc->enabled = 0; +} + +static void ipu_crtc_dpms(struct drm_crtc *crtc, int mode) +{ + struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); + + dev_dbg(ipu_crtc->dev, "%s mode: %d\n", __func__, mode); + + switch (mode) { + case DRM_MODE_DPMS_ON: + ipu_fb_enable(ipu_crtc); + break; + case DRM_MODE_DPMS_STANDBY: + case DRM_MODE_DPMS_SUSPEND: + case DRM_MODE_DPMS_OFF: + ipu_fb_disable(ipu_crtc); + break; + } +} + +static int ipu_page_flip(struct drm_crtc *crtc, + struct drm_framebuffer *fb, + struct drm_pending_vblank_event *event, + uint32_t page_flip_flags) +{ + struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); + int ret; + + if (ipu_crtc->newfb) + return -EBUSY; + + ret = imx_drm_crtc_vblank_get(ipu_crtc->imx_crtc); + if (ret) { + dev_dbg(ipu_crtc->dev, "failed to acquire vblank counter\n"); + list_del(&event->base.link); + + return ret; + } + + ipu_crtc->newfb = fb; + ipu_crtc->page_flip_event = event; + crtc->primary->fb = fb; + + return 0; +} + +static const struct drm_crtc_funcs ipu_crtc_funcs = { + .set_config = drm_crtc_helper_set_config, + .destroy = drm_crtc_cleanup, + .page_flip = ipu_page_flip, +}; + +static int ipu_crtc_mode_set(struct drm_crtc *crtc, + struct drm_display_mode *orig_mode, + struct drm_display_mode *mode, + int x, int y, + struct drm_framebuffer *old_fb) +{ + struct drm_device *dev = crtc->dev; + struct drm_encoder *encoder; + struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); + struct ipu_di_signal_cfg sig_cfg = {}; + unsigned long encoder_types = 0; + int ret; + + dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__, + mode->hdisplay); + dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__, + mode->vdisplay); + + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) + if (encoder->crtc == crtc) + encoder_types |= BIT(encoder->encoder_type); + + dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n", + __func__, encoder_types); + + /* + * If we have DAC or LDB, then we need the IPU DI clock to be + * the same as the LDB DI clock. For TVDAC, derive the IPU DI + * clock from 27 MHz TVE_DI clock, but allow to divide it. + */ + if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) | + BIT(DRM_MODE_ENCODER_LVDS))) + sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT; + else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC)) + sig_cfg.clkflags = IPU_DI_CLKMODE_EXT; + else + sig_cfg.clkflags = 0; + + sig_cfg.enable_pol = 1; + sig_cfg.clk_pol = 0; + sig_cfg.bus_format = ipu_crtc->bus_format; + sig_cfg.v_to_h_sync = 0; + sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin; + sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin; + + drm_display_mode_to_videomode(mode, &sig_cfg.mode); + + ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di, + mode->flags & DRM_MODE_FLAG_INTERLACE, + ipu_crtc->bus_format, mode->hdisplay); + if (ret) { + dev_err(ipu_crtc->dev, + "initializing display controller failed with %d\n", + ret); + return ret; + } + + ret = ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg); + if (ret) { + dev_err(ipu_crtc->dev, + "initializing panel failed with %d\n", ret); + return ret; + } + + return ipu_plane_mode_set(ipu_crtc->plane[0], crtc, mode, + crtc->primary->fb, + 0, 0, mode->hdisplay, mode->vdisplay, + x, y, mode->hdisplay, mode->vdisplay, + mode->flags & DRM_MODE_FLAG_INTERLACE); +} + +static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc) +{ + unsigned long flags; + struct drm_device *drm = ipu_crtc->base.dev; + + spin_lock_irqsave(&drm->event_lock, flags); + if (ipu_crtc->page_flip_event) + drm_send_vblank_event(drm, -1, ipu_crtc->page_flip_event); + ipu_crtc->page_flip_event = NULL; + imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc); + spin_unlock_irqrestore(&drm->event_lock, flags); +} + +static irqreturn_t ipu_irq_handler(int irq, void *dev_id) +{ + struct ipu_crtc *ipu_crtc = dev_id; + + imx_drm_handle_vblank(ipu_crtc->imx_crtc); + + if (ipu_crtc->newfb) { + struct ipu_plane *plane = ipu_crtc->plane[0]; + + ipu_crtc->newfb = NULL; + ipu_plane_set_base(plane, ipu_crtc->base.primary->fb, + plane->x, plane->y); + ipu_crtc_handle_pageflip(ipu_crtc); + } + + return IRQ_HANDLED; +} + +static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); + struct videomode vm; + int ret; + + drm_display_mode_to_videomode(adjusted_mode, &vm); + + ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm); + if (ret) + return false; + + drm_display_mode_from_videomode(&vm, adjusted_mode); + + return true; +} + +static void ipu_crtc_prepare(struct drm_crtc *crtc) +{ + struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); + + ipu_fb_disable(ipu_crtc); +} + +static void ipu_crtc_commit(struct drm_crtc *crtc) +{ + struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); + + ipu_fb_enable(ipu_crtc); +} + +static struct drm_crtc_helper_funcs ipu_helper_funcs = { + .dpms = ipu_crtc_dpms, + .mode_fixup = ipu_crtc_mode_fixup, + .mode_set = ipu_crtc_mode_set, + .prepare = ipu_crtc_prepare, + .commit = ipu_crtc_commit, +}; + +static int ipu_enable_vblank(struct drm_crtc *crtc) +{ + return 0; +} + +static void ipu_disable_vblank(struct drm_crtc *crtc) +{ + struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); + + ipu_crtc->page_flip_event = NULL; + ipu_crtc->newfb = NULL; +} + +static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc, + u32 bus_format, int hsync_pin, int vsync_pin) +{ + struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); + + ipu_crtc->bus_format = bus_format; + ipu_crtc->di_hsync_pin = hsync_pin; + ipu_crtc->di_vsync_pin = vsync_pin; + + return 0; +} + +static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = { + .enable_vblank = ipu_enable_vblank, + .disable_vblank = ipu_disable_vblank, + .set_interface_pix_fmt = ipu_set_interface_pix_fmt, + .crtc_funcs = &ipu_crtc_funcs, + .crtc_helper_funcs = &ipu_helper_funcs, +}; + +static void ipu_put_resources(struct ipu_crtc *ipu_crtc) +{ + if (!IS_ERR_OR_NULL(ipu_crtc->dc)) + ipu_dc_put(ipu_crtc->dc); + if (!IS_ERR_OR_NULL(ipu_crtc->di)) + ipu_di_put(ipu_crtc->di); +} + +static int ipu_get_resources(struct ipu_crtc *ipu_crtc, + struct ipu_client_platformdata *pdata) +{ + struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); + int ret; + + ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc); + if (IS_ERR(ipu_crtc->dc)) { + ret = PTR_ERR(ipu_crtc->dc); + goto err_out; + } + + ipu_crtc->di = ipu_di_get(ipu, pdata->di); + if (IS_ERR(ipu_crtc->di)) { + ret = PTR_ERR(ipu_crtc->di); + goto err_out; + } + + return 0; +err_out: + ipu_put_resources(ipu_crtc); + + return ret; +} + +static int ipu_crtc_init(struct ipu_crtc *ipu_crtc, + struct ipu_client_platformdata *pdata, struct drm_device *drm) +{ + struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); + int dp = -EINVAL; + int ret; + int id; + + ret = ipu_get_resources(ipu_crtc, pdata); + if (ret) { + dev_err(ipu_crtc->dev, "getting resources failed with %d.\n", + ret); + return ret; + } + + ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc, + &ipu_crtc_helper_funcs, ipu_crtc->dev->of_node); + if (ret) { + dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret); + goto err_put_resources; + } + + if (pdata->dp >= 0) + dp = IPU_DP_FLOW_SYNC_BG; + id = imx_drm_crtc_id(ipu_crtc->imx_crtc); + ipu_crtc->plane[0] = ipu_plane_init(ipu_crtc->base.dev, ipu, + pdata->dma[0], dp, BIT(id), true); + ret = ipu_plane_get_resources(ipu_crtc->plane[0]); + if (ret) { + dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n", + ret); + goto err_remove_crtc; + } + + /* If this crtc is using the DP, add an overlay plane */ + if (pdata->dp >= 0 && pdata->dma[1] > 0) { + ipu_crtc->plane[1] = ipu_plane_init(ipu_crtc->base.dev, ipu, + pdata->dma[1], + IPU_DP_FLOW_SYNC_FG, + BIT(id), false); + if (IS_ERR(ipu_crtc->plane[1])) + ipu_crtc->plane[1] = NULL; + } + + ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]); + ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0, + "imx_drm", ipu_crtc); + if (ret < 0) { + dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret); + goto err_put_plane_res; + } + + return 0; + +err_put_plane_res: + ipu_plane_put_resources(ipu_crtc->plane[0]); +err_remove_crtc: + imx_drm_remove_crtc(ipu_crtc->imx_crtc); +err_put_resources: + ipu_put_resources(ipu_crtc); + + return ret; +} + +static struct device_node *ipu_drm_get_port_by_id(struct device_node *parent, + int port_id) +{ + struct device_node *port; + int id, ret; + + port = of_get_child_by_name(parent, "port"); + while (port) { + ret = of_property_read_u32(port, "reg", &id); + if (!ret && id == port_id) + return port; + + do { + port = of_get_next_child(parent, port); + if (!port) + return NULL; + } while (of_node_cmp(port->name, "port")); + } + + return NULL; +} + +static int ipu_drm_bind(struct device *dev, struct device *master, void *data) +{ + struct ipu_client_platformdata *pdata = dev->platform_data; + struct drm_device *drm = data; + struct ipu_crtc *ipu_crtc; + int ret; + + ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL); + if (!ipu_crtc) + return -ENOMEM; + + ipu_crtc->dev = dev; + + ret = ipu_crtc_init(ipu_crtc, pdata, drm); + if (ret) + return ret; + + dev_set_drvdata(dev, ipu_crtc); + + return 0; +} + +static void ipu_drm_unbind(struct device *dev, struct device *master, + void *data) +{ + struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev); + + imx_drm_remove_crtc(ipu_crtc->imx_crtc); + + ipu_plane_put_resources(ipu_crtc->plane[0]); + ipu_put_resources(ipu_crtc); +} + +static const struct component_ops ipu_crtc_ops = { + .bind = ipu_drm_bind, + .unbind = ipu_drm_unbind, +}; + +static int ipu_drm_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ipu_client_platformdata *pdata = dev->platform_data; + int ret; + + if (!dev->platform_data) + return -EINVAL; + + if (!dev->of_node) { + /* Associate crtc device with the corresponding DI port node */ + dev->of_node = ipu_drm_get_port_by_id(dev->parent->of_node, + pdata->di + 2); + if (!dev->of_node) { + dev_err(dev, "missing port@%d node in %s\n", + pdata->di + 2, dev->parent->of_node->full_name); + return -ENODEV; + } + } + + ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); + if (ret) + return ret; + + return component_add(dev, &ipu_crtc_ops); +} + +static int ipu_drm_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &ipu_crtc_ops); + return 0; +} + +static struct platform_driver ipu_drm_driver = { + .driver = { + .name = "imx-ipuv3-crtc", + }, + .probe = ipu_drm_probe, + .remove = ipu_drm_remove, +}; +module_platform_driver(ipu_drm_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:imx-ipuv3-crtc"); diff --git a/kernel/drivers/gpu/drm/imx/ipuv3-plane.c b/kernel/drivers/gpu/drm/imx/ipuv3-plane.c new file mode 100644 index 000000000..878a643d7 --- /dev/null +++ b/kernel/drivers/gpu/drm/imx/ipuv3-plane.c @@ -0,0 +1,397 @@ +/* + * i.MX IPUv3 DP Overlay Planes + * + * Copyright (C) 2013 Philipp Zabel, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drm/drmP.h> +#include <drm/drm_fb_cma_helper.h> +#include <drm/drm_gem_cma_helper.h> + +#include "video/imx-ipu-v3.h" +#include "ipuv3-plane.h" + +#define to_ipu_plane(x) container_of(x, struct ipu_plane, base) + +static const uint32_t ipu_plane_formats[] = { + DRM_FORMAT_XRGB1555, + DRM_FORMAT_XBGR1555, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_YUYV, + DRM_FORMAT_YVYU, + DRM_FORMAT_YUV420, + DRM_FORMAT_YVU420, +}; + +int ipu_plane_irq(struct ipu_plane *ipu_plane) +{ + return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch, + IPU_IRQ_EOF); +} + +static int calc_vref(struct drm_display_mode *mode) +{ + unsigned long htotal, vtotal; + + htotal = mode->htotal; + vtotal = mode->vtotal; + + if (!htotal || !vtotal) + return 60; + + return DIV_ROUND_UP(mode->clock * 1000, vtotal * htotal); +} + +static inline int calc_bandwidth(int width, int height, unsigned int vref) +{ + return width * height * vref; +} + +int ipu_plane_set_base(struct ipu_plane *ipu_plane, struct drm_framebuffer *fb, + int x, int y) +{ + struct drm_gem_cma_object *cma_obj; + unsigned long eba; + int active; + + cma_obj = drm_fb_cma_get_gem_obj(fb, 0); + if (!cma_obj) { + DRM_DEBUG_KMS("entry is null.\n"); + return -EFAULT; + } + + dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d", + &cma_obj->paddr, x, y); + + eba = cma_obj->paddr + fb->offsets[0] + + fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x; + + if (ipu_plane->enabled) { + active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch); + ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba); + ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active); + } else { + ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba); + ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba); + } + + /* cache offsets for subsequent pageflips */ + ipu_plane->x = x; + ipu_plane->y = y; + + return 0; +} + +int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc, + struct drm_display_mode *mode, + struct drm_framebuffer *fb, int crtc_x, int crtc_y, + unsigned int crtc_w, unsigned int crtc_h, + uint32_t src_x, uint32_t src_y, + uint32_t src_w, uint32_t src_h, bool interlaced) +{ + struct device *dev = ipu_plane->base.dev->dev; + int ret; + + /* no scaling */ + if (src_w != crtc_w || src_h != crtc_h) + return -EINVAL; + + /* clip to crtc bounds */ + if (crtc_x < 0) { + if (-crtc_x > crtc_w) + return -EINVAL; + src_x += -crtc_x; + src_w -= -crtc_x; + crtc_w -= -crtc_x; + crtc_x = 0; + } + if (crtc_y < 0) { + if (-crtc_y > crtc_h) + return -EINVAL; + src_y += -crtc_y; + src_h -= -crtc_y; + crtc_h -= -crtc_y; + crtc_y = 0; + } + if (crtc_x + crtc_w > mode->hdisplay) { + if (crtc_x > mode->hdisplay) + return -EINVAL; + crtc_w = mode->hdisplay - crtc_x; + src_w = crtc_w; + } + if (crtc_y + crtc_h > mode->vdisplay) { + if (crtc_y > mode->vdisplay) + return -EINVAL; + crtc_h = mode->vdisplay - crtc_y; + src_h = crtc_h; + } + /* full plane minimum width is 13 pixels */ + if (crtc_w < 13 && (ipu_plane->dp_flow != IPU_DP_FLOW_SYNC_FG)) + return -EINVAL; + if (crtc_h < 2) + return -EINVAL; + + /* + * since we cannot touch active IDMAC channels, we do not support + * resizing the enabled plane or changing its format + */ + if (ipu_plane->enabled) { + if (src_w != ipu_plane->w || src_h != ipu_plane->h || + fb->pixel_format != ipu_plane->base.fb->pixel_format) + return -EINVAL; + + return ipu_plane_set_base(ipu_plane, fb, src_x, src_y); + } + + switch (ipu_plane->dp_flow) { + case IPU_DP_FLOW_SYNC_BG: + ret = ipu_dp_setup_channel(ipu_plane->dp, + IPUV3_COLORSPACE_RGB, + IPUV3_COLORSPACE_RGB); + if (ret) { + dev_err(dev, + "initializing display processor failed with %d\n", + ret); + return ret; + } + ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true); + break; + case IPU_DP_FLOW_SYNC_FG: + ipu_dp_setup_channel(ipu_plane->dp, + ipu_drm_fourcc_to_colorspace(fb->pixel_format), + IPUV3_COLORSPACE_UNKNOWN); + ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y); + /* Enable local alpha on partial plane */ + switch (fb->pixel_format) { + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_ABGR8888: + ipu_dp_set_global_alpha(ipu_plane->dp, false, 0, false); + break; + default: + break; + } + } + + ret = ipu_dmfc_init_channel(ipu_plane->dmfc, crtc_w); + if (ret) { + dev_err(dev, "initializing dmfc channel failed with %d\n", ret); + return ret; + } + + ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc, + calc_bandwidth(crtc_w, crtc_h, + calc_vref(mode)), 64); + if (ret) { + dev_err(dev, "allocating dmfc bandwidth failed with %d\n", ret); + return ret; + } + + ipu_cpmem_zero(ipu_plane->ipu_ch); + ipu_cpmem_set_resolution(ipu_plane->ipu_ch, src_w, src_h); + ret = ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->pixel_format); + if (ret < 0) { + dev_err(dev, "unsupported pixel format 0x%08x\n", + fb->pixel_format); + return ret; + } + ipu_cpmem_set_high_priority(ipu_plane->ipu_ch); + ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1); + ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]); + + ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y); + if (ret < 0) + return ret; + if (interlaced) + ipu_cpmem_interlaced_scan(ipu_plane->ipu_ch, fb->pitches[0]); + + ipu_plane->w = src_w; + ipu_plane->h = src_h; + + return 0; +} + +void ipu_plane_put_resources(struct ipu_plane *ipu_plane) +{ + if (!IS_ERR_OR_NULL(ipu_plane->dp)) + ipu_dp_put(ipu_plane->dp); + if (!IS_ERR_OR_NULL(ipu_plane->dmfc)) + ipu_dmfc_put(ipu_plane->dmfc); + if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch)) + ipu_idmac_put(ipu_plane->ipu_ch); +} + +int ipu_plane_get_resources(struct ipu_plane *ipu_plane) +{ + int ret; + + ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma); + if (IS_ERR(ipu_plane->ipu_ch)) { + ret = PTR_ERR(ipu_plane->ipu_ch); + DRM_ERROR("failed to get idmac channel: %d\n", ret); + return ret; + } + + ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma); + if (IS_ERR(ipu_plane->dmfc)) { + ret = PTR_ERR(ipu_plane->dmfc); + DRM_ERROR("failed to get dmfc: ret %d\n", ret); + goto err_out; + } + + if (ipu_plane->dp_flow >= 0) { + ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow); + if (IS_ERR(ipu_plane->dp)) { + ret = PTR_ERR(ipu_plane->dp); + DRM_ERROR("failed to get dp flow: %d\n", ret); + goto err_out; + } + } + + return 0; +err_out: + ipu_plane_put_resources(ipu_plane); + + return ret; +} + +void ipu_plane_enable(struct ipu_plane *ipu_plane) +{ + if (ipu_plane->dp) + ipu_dp_enable(ipu_plane->ipu); + ipu_dmfc_enable_channel(ipu_plane->dmfc); + ipu_idmac_enable_channel(ipu_plane->ipu_ch); + if (ipu_plane->dp) + ipu_dp_enable_channel(ipu_plane->dp); + + ipu_plane->enabled = true; +} + +void ipu_plane_disable(struct ipu_plane *ipu_plane) +{ + ipu_plane->enabled = false; + + ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50); + + if (ipu_plane->dp) + ipu_dp_disable_channel(ipu_plane->dp); + ipu_idmac_disable_channel(ipu_plane->ipu_ch); + ipu_dmfc_disable_channel(ipu_plane->dmfc); + if (ipu_plane->dp) + ipu_dp_disable(ipu_plane->ipu); +} + +/* + * drm_plane API + */ + +static int ipu_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, + struct drm_framebuffer *fb, int crtc_x, int crtc_y, + unsigned int crtc_w, unsigned int crtc_h, + uint32_t src_x, uint32_t src_y, + uint32_t src_w, uint32_t src_h) +{ + struct ipu_plane *ipu_plane = to_ipu_plane(plane); + int ret = 0; + + DRM_DEBUG_KMS("plane - %p\n", plane); + + if (!ipu_plane->enabled) + ret = ipu_plane_get_resources(ipu_plane); + if (ret < 0) + return ret; + + ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb, + crtc_x, crtc_y, crtc_w, crtc_h, + src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16, + false); + if (ret < 0) { + ipu_plane_put_resources(ipu_plane); + return ret; + } + + if (crtc != plane->crtc) + dev_info(plane->dev->dev, "crtc change: %p -> %p\n", + plane->crtc, crtc); + plane->crtc = crtc; + + if (!ipu_plane->enabled) + ipu_plane_enable(ipu_plane); + + return 0; +} + +static int ipu_disable_plane(struct drm_plane *plane) +{ + struct ipu_plane *ipu_plane = to_ipu_plane(plane); + + DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__); + + if (ipu_plane->enabled) + ipu_plane_disable(ipu_plane); + + ipu_plane_put_resources(ipu_plane); + + return 0; +} + +static void ipu_plane_destroy(struct drm_plane *plane) +{ + struct ipu_plane *ipu_plane = to_ipu_plane(plane); + + DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__); + + ipu_disable_plane(plane); + drm_plane_cleanup(plane); + kfree(ipu_plane); +} + +static struct drm_plane_funcs ipu_plane_funcs = { + .update_plane = ipu_update_plane, + .disable_plane = ipu_disable_plane, + .destroy = ipu_plane_destroy, +}; + +struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu, + int dma, int dp, unsigned int possible_crtcs, + bool priv) +{ + struct ipu_plane *ipu_plane; + int ret; + + DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n", + dma, dp, possible_crtcs); + + ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL); + if (!ipu_plane) { + DRM_ERROR("failed to allocate plane\n"); + return ERR_PTR(-ENOMEM); + } + + ipu_plane->ipu = ipu; + ipu_plane->dma = dma; + ipu_plane->dp_flow = dp; + + ret = drm_plane_init(dev, &ipu_plane->base, possible_crtcs, + &ipu_plane_funcs, ipu_plane_formats, + ARRAY_SIZE(ipu_plane_formats), + priv); + if (ret) { + DRM_ERROR("failed to initialize plane\n"); + kfree(ipu_plane); + return ERR_PTR(ret); + } + + return ipu_plane; +} diff --git a/kernel/drivers/gpu/drm/imx/ipuv3-plane.h b/kernel/drivers/gpu/drm/imx/ipuv3-plane.h new file mode 100644 index 000000000..9b5eff18f --- /dev/null +++ b/kernel/drivers/gpu/drm/imx/ipuv3-plane.h @@ -0,0 +1,57 @@ +#ifndef __IPUV3_PLANE_H__ +#define __IPUV3_PLANE_H__ + +#include <drm/drm_crtc.h> /* drm_plane */ + +struct drm_plane; +struct drm_device; +struct ipu_soc; +struct drm_crtc; +struct drm_framebuffer; + +struct ipuv3_channel; +struct dmfc_channel; +struct ipu_dp; + +struct ipu_plane { + struct drm_plane base; + + struct ipu_soc *ipu; + struct ipuv3_channel *ipu_ch; + struct dmfc_channel *dmfc; + struct ipu_dp *dp; + + int dma; + int dp_flow; + + int x; + int y; + int w; + int h; + + bool enabled; +}; + +struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu, + int dma, int dp, unsigned int possible_crtcs, + bool priv); + +/* Init IDMAC, DMFC, DP */ +int ipu_plane_mode_set(struct ipu_plane *plane, struct drm_crtc *crtc, + struct drm_display_mode *mode, + struct drm_framebuffer *fb, int crtc_x, int crtc_y, + unsigned int crtc_w, unsigned int crtc_h, + uint32_t src_x, uint32_t src_y, uint32_t src_w, + uint32_t src_h, bool interlaced); + +void ipu_plane_enable(struct ipu_plane *plane); +void ipu_plane_disable(struct ipu_plane *plane); +int ipu_plane_set_base(struct ipu_plane *plane, struct drm_framebuffer *fb, + int x, int y); + +int ipu_plane_get_resources(struct ipu_plane *plane); +void ipu_plane_put_resources(struct ipu_plane *plane); + +int ipu_plane_irq(struct ipu_plane *plane); + +#endif diff --git a/kernel/drivers/gpu/drm/imx/parallel-display.c b/kernel/drivers/gpu/drm/imx/parallel-display.c new file mode 100644 index 000000000..74a9ce40d --- /dev/null +++ b/kernel/drivers/gpu/drm/imx/parallel-display.c @@ -0,0 +1,303 @@ +/* + * i.MX drm driver - parallel display implementation + * + * Copyright (C) 2012 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/component.h> +#include <linux/module.h> +#include <drm/drmP.h> +#include <drm/drm_fb_helper.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_panel.h> +#include <linux/videodev2.h> +#include <video/of_display_timing.h> + +#include "imx-drm.h" + +#define con_to_imxpd(x) container_of(x, struct imx_parallel_display, connector) +#define enc_to_imxpd(x) container_of(x, struct imx_parallel_display, encoder) + +struct imx_parallel_display { + struct drm_connector connector; + struct drm_encoder encoder; + struct device *dev; + void *edid; + int edid_len; + u32 bus_format; + int mode_valid; + struct drm_display_mode mode; + struct drm_panel *panel; +}; + +static enum drm_connector_status imx_pd_connector_detect( + struct drm_connector *connector, bool force) +{ + return connector_status_connected; +} + +static int imx_pd_connector_get_modes(struct drm_connector *connector) +{ + struct imx_parallel_display *imxpd = con_to_imxpd(connector); + struct device_node *np = imxpd->dev->of_node; + int num_modes = 0; + + if (imxpd->panel && imxpd->panel->funcs && + imxpd->panel->funcs->get_modes) { + num_modes = imxpd->panel->funcs->get_modes(imxpd->panel); + if (num_modes > 0) + return num_modes; + } + + if (imxpd->edid) { + drm_mode_connector_update_edid_property(connector, imxpd->edid); + num_modes = drm_add_edid_modes(connector, imxpd->edid); + } + + if (imxpd->mode_valid) { + struct drm_display_mode *mode = drm_mode_create(connector->dev); + + if (!mode) + return -EINVAL; + drm_mode_copy(mode, &imxpd->mode); + mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, + drm_mode_probed_add(connector, mode); + num_modes++; + } + + if (np) { + struct drm_display_mode *mode = drm_mode_create(connector->dev); + + if (!mode) + return -EINVAL; + of_get_drm_display_mode(np, &imxpd->mode, OF_USE_NATIVE_MODE); + drm_mode_copy(mode, &imxpd->mode); + mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, + drm_mode_probed_add(connector, mode); + num_modes++; + } + + return num_modes; +} + +static struct drm_encoder *imx_pd_connector_best_encoder( + struct drm_connector *connector) +{ + struct imx_parallel_display *imxpd = con_to_imxpd(connector); + + return &imxpd->encoder; +} + +static void imx_pd_encoder_dpms(struct drm_encoder *encoder, int mode) +{ + struct imx_parallel_display *imxpd = enc_to_imxpd(encoder); + + if (mode != DRM_MODE_DPMS_ON) + drm_panel_disable(imxpd->panel); + else + drm_panel_enable(imxpd->panel); +} + +static bool imx_pd_encoder_mode_fixup(struct drm_encoder *encoder, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + return true; +} + +static void imx_pd_encoder_prepare(struct drm_encoder *encoder) +{ + struct imx_parallel_display *imxpd = enc_to_imxpd(encoder); + + imx_drm_set_bus_format(encoder, imxpd->bus_format); +} + +static void imx_pd_encoder_commit(struct drm_encoder *encoder) +{ + struct imx_parallel_display *imxpd = enc_to_imxpd(encoder); + + drm_panel_prepare(imxpd->panel); + drm_panel_enable(imxpd->panel); +} + +static void imx_pd_encoder_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *orig_mode, + struct drm_display_mode *mode) +{ +} + +static void imx_pd_encoder_disable(struct drm_encoder *encoder) +{ + struct imx_parallel_display *imxpd = enc_to_imxpd(encoder); + + drm_panel_disable(imxpd->panel); + drm_panel_unprepare(imxpd->panel); +} + +static struct drm_connector_funcs imx_pd_connector_funcs = { + .dpms = drm_helper_connector_dpms, + .fill_modes = drm_helper_probe_single_connector_modes, + .detect = imx_pd_connector_detect, + .destroy = imx_drm_connector_destroy, +}; + +static struct drm_connector_helper_funcs imx_pd_connector_helper_funcs = { + .get_modes = imx_pd_connector_get_modes, + .best_encoder = imx_pd_connector_best_encoder, +}; + +static struct drm_encoder_funcs imx_pd_encoder_funcs = { + .destroy = imx_drm_encoder_destroy, +}; + +static struct drm_encoder_helper_funcs imx_pd_encoder_helper_funcs = { + .dpms = imx_pd_encoder_dpms, + .mode_fixup = imx_pd_encoder_mode_fixup, + .prepare = imx_pd_encoder_prepare, + .commit = imx_pd_encoder_commit, + .mode_set = imx_pd_encoder_mode_set, + .disable = imx_pd_encoder_disable, +}; + +static int imx_pd_register(struct drm_device *drm, + struct imx_parallel_display *imxpd) +{ + int ret; + + ret = imx_drm_encoder_parse_of(drm, &imxpd->encoder, + imxpd->dev->of_node); + if (ret) + return ret; + + /* set the connector's dpms to OFF so that + * drm_helper_connector_dpms() won't return + * immediately since the current state is ON + * at this point. + */ + imxpd->connector.dpms = DRM_MODE_DPMS_OFF; + + drm_encoder_helper_add(&imxpd->encoder, &imx_pd_encoder_helper_funcs); + drm_encoder_init(drm, &imxpd->encoder, &imx_pd_encoder_funcs, + DRM_MODE_ENCODER_NONE); + + drm_connector_helper_add(&imxpd->connector, + &imx_pd_connector_helper_funcs); + drm_connector_init(drm, &imxpd->connector, &imx_pd_connector_funcs, + DRM_MODE_CONNECTOR_VGA); + + if (imxpd->panel) + drm_panel_attach(imxpd->panel, &imxpd->connector); + + drm_mode_connector_attach_encoder(&imxpd->connector, &imxpd->encoder); + + imxpd->connector.encoder = &imxpd->encoder; + + return 0; +} + +static int imx_pd_bind(struct device *dev, struct device *master, void *data) +{ + struct drm_device *drm = data; + struct device_node *np = dev->of_node; + struct device_node *panel_node; + const u8 *edidp; + struct imx_parallel_display *imxpd; + int ret; + const char *fmt; + + imxpd = devm_kzalloc(dev, sizeof(*imxpd), GFP_KERNEL); + if (!imxpd) + return -ENOMEM; + + edidp = of_get_property(np, "edid", &imxpd->edid_len); + if (edidp) + imxpd->edid = kmemdup(edidp, imxpd->edid_len, GFP_KERNEL); + + ret = of_property_read_string(np, "interface-pix-fmt", &fmt); + if (!ret) { + if (!strcmp(fmt, "rgb24")) + imxpd->bus_format = MEDIA_BUS_FMT_RGB888_1X24; + else if (!strcmp(fmt, "rgb565")) + imxpd->bus_format = MEDIA_BUS_FMT_RGB565_1X16; + else if (!strcmp(fmt, "bgr666")) + imxpd->bus_format = MEDIA_BUS_FMT_RGB666_1X18; + else if (!strcmp(fmt, "lvds666")) + imxpd->bus_format = MEDIA_BUS_FMT_RGB666_1X24_CPADHI; + } + + panel_node = of_parse_phandle(np, "fsl,panel", 0); + if (panel_node) { + imxpd->panel = of_drm_find_panel(panel_node); + if (!imxpd->panel) + return -EPROBE_DEFER; + } + + imxpd->dev = dev; + + ret = imx_pd_register(drm, imxpd); + if (ret) + return ret; + + dev_set_drvdata(dev, imxpd); + + return 0; +} + +static void imx_pd_unbind(struct device *dev, struct device *master, + void *data) +{ + struct imx_parallel_display *imxpd = dev_get_drvdata(dev); + + imxpd->encoder.funcs->destroy(&imxpd->encoder); + imxpd->connector.funcs->destroy(&imxpd->connector); + + kfree(imxpd->edid); +} + +static const struct component_ops imx_pd_ops = { + .bind = imx_pd_bind, + .unbind = imx_pd_unbind, +}; + +static int imx_pd_probe(struct platform_device *pdev) +{ + return component_add(&pdev->dev, &imx_pd_ops); +} + +static int imx_pd_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &imx_pd_ops); + + return 0; +} + +static const struct of_device_id imx_pd_dt_ids[] = { + { .compatible = "fsl,imx-parallel-display", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_pd_dt_ids); + +static struct platform_driver imx_pd_driver = { + .probe = imx_pd_probe, + .remove = imx_pd_remove, + .driver = { + .of_match_table = imx_pd_dt_ids, + .name = "imx-parallel-display", + }, +}; + +module_platform_driver(imx_pd_driver); + +MODULE_DESCRIPTION("i.MX parallel display driver"); +MODULE_AUTHOR("Sascha Hauer, Pengutronix"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:imx-parallel-display"); |