diff options
Diffstat (limited to 'kernel/drivers/clk/samsung')
25 files changed, 1084 insertions, 357 deletions
diff --git a/kernel/drivers/clk/samsung/Makefile b/kernel/drivers/clk/samsung/Makefile index a17683b2c..5f6833ea3 100644 --- a/kernel/drivers/clk/samsung/Makefile +++ b/kernel/drivers/clk/samsung/Makefile @@ -2,7 +2,7 @@ # Samsung Clock specific Makefile # -obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o +obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o obj-$(CONFIG_SOC_EXYNOS4415) += clk-exynos4415.o diff --git a/kernel/drivers/clk/samsung/clk-cpu.c b/kernel/drivers/clk/samsung/clk-cpu.c new file mode 100644 index 000000000..813003d6c --- /dev/null +++ b/kernel/drivers/clk/samsung/clk-cpu.c @@ -0,0 +1,354 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * Author: Thomas Abraham <thomas.ab@samsung.com> + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd. + * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This file contains the utility function to register CPU clock for Samsung + * Exynos platforms. A CPU clock is defined as a clock supplied to a CPU or a + * group of CPUs. The CPU clock is typically derived from a hierarchy of clock + * blocks which includes mux and divider blocks. There are a number of other + * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI + * clock for CPU domain. The rates of these auxiliary clocks are related to the + * CPU clock rate and this relation is usually specified in the hardware manual + * of the SoC or supplied after the SoC characterization. + * + * The below implementation of the CPU clock allows the rate changes of the CPU + * clock and the corresponding rate changes of the auxillary clocks of the CPU + * domain. The platform clock driver provides a clock register configuration + * for each configurable rate which is then used to program the clock hardware + * registers to acheive a fast co-oridinated rate change for all the CPU domain + * clocks. + * + * On a rate change request for the CPU clock, the rate change is propagated + * upto the PLL supplying the clock to the CPU domain clock blocks. While the + * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an + * alternate clock source. If required, the alternate clock source is divided + * down in order to keep the output clock rate within the previous OPP limits. +*/ + +#include <linux/errno.h> +#include <linux/slab.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include "clk-cpu.h" + +#define E4210_SRC_CPU 0x0 +#define E4210_STAT_CPU 0x200 +#define E4210_DIV_CPU0 0x300 +#define E4210_DIV_CPU1 0x304 +#define E4210_DIV_STAT_CPU0 0x400 +#define E4210_DIV_STAT_CPU1 0x404 + +#define E4210_DIV0_RATIO0_MASK 0x7 +#define E4210_DIV1_HPM_MASK (0x7 << 4) +#define E4210_DIV1_COPY_MASK (0x7 << 0) +#define E4210_MUX_HPM_MASK (1 << 20) +#define E4210_DIV0_ATB_SHIFT 16 +#define E4210_DIV0_ATB_MASK (DIV_MASK << E4210_DIV0_ATB_SHIFT) + +#define MAX_DIV 8 +#define DIV_MASK 7 +#define DIV_MASK_ALL 0xffffffff +#define MUX_MASK 7 + +/* + * Helper function to wait until divider(s) have stabilized after the divider + * value has changed. + */ +static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(10); + + do { + if (!(readl(div_reg) & mask)) + return; + } while (time_before(jiffies, timeout)); + + if (!(readl(div_reg) & mask)) + return; + + pr_err("%s: timeout in divider stablization\n", __func__); +} + +/* + * Helper function to wait until mux has stabilized after the mux selection + * value was changed. + */ +static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos, + unsigned long mux_value) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(10); + + do { + if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value) + return; + } while (time_before(jiffies, timeout)); + + if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value) + return; + + pr_err("%s: re-parenting mux timed-out\n", __func__); +} + +/* common round rate callback useable for all types of CPU clocks */ +static long exynos_cpuclk_round_rate(struct clk_hw *hw, + unsigned long drate, unsigned long *prate) +{ + struct clk_hw *parent = clk_hw_get_parent(hw); + *prate = clk_hw_round_rate(parent, drate); + return *prate; +} + +/* common recalc rate callback useable for all types of CPU clocks */ +static unsigned long exynos_cpuclk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + /* + * The CPU clock output (armclk) rate is the same as its parent + * rate. Although there exist certain dividers inside the CPU + * clock block that could be used to divide the parent clock, + * the driver does not make use of them currently, except during + * frequency transitions. + */ + return parent_rate; +} + +static const struct clk_ops exynos_cpuclk_clk_ops = { + .recalc_rate = exynos_cpuclk_recalc_rate, + .round_rate = exynos_cpuclk_round_rate, +}; + +/* + * Helper function to set the 'safe' dividers for the CPU clock. The parameters + * div and mask contain the divider value and the register bit mask of the + * dividers to be programmed. + */ +static void exynos_set_safe_div(void __iomem *base, unsigned long div, + unsigned long mask) +{ + unsigned long div0; + + div0 = readl(base + E4210_DIV_CPU0); + div0 = (div0 & ~mask) | (div & mask); + writel(div0, base + E4210_DIV_CPU0); + wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, mask); +} + +/* handler for pre-rate change notification from parent clock */ +static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, + struct exynos_cpuclk *cpuclk, void __iomem *base) +{ + const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg; + unsigned long alt_prate = clk_get_rate(cpuclk->alt_parent); + unsigned long alt_div = 0, alt_div_mask = DIV_MASK; + unsigned long div0, div1 = 0, mux_reg; + unsigned long flags; + + /* find out the divider values to use for clock data */ + while ((cfg_data->prate * 1000) != ndata->new_rate) { + if (cfg_data->prate == 0) + return -EINVAL; + cfg_data++; + } + + spin_lock_irqsave(cpuclk->lock, flags); + + /* + * For the selected PLL clock frequency, get the pre-defined divider + * values. If the clock for sclk_hpm is not sourced from apll, then + * the values for DIV_COPY and DIV_HPM dividers need not be set. + */ + div0 = cfg_data->div0; + if (cpuclk->flags & CLK_CPU_HAS_DIV1) { + div1 = cfg_data->div1; + if (readl(base + E4210_SRC_CPU) & E4210_MUX_HPM_MASK) + div1 = readl(base + E4210_DIV_CPU1) & + (E4210_DIV1_HPM_MASK | E4210_DIV1_COPY_MASK); + } + + /* + * If the old parent clock speed is less than the clock speed of + * the alternate parent, then it should be ensured that at no point + * the armclk speed is more than the old_prate until the dividers are + * set. Also workaround the issue of the dividers being set to lower + * values before the parent clock speed is set to new lower speed + * (this can result in too high speed of armclk output clocks). + */ + if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) { + unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate); + + alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1; + WARN_ON(alt_div >= MAX_DIV); + + if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) { + /* + * In Exynos4210, ATB clock parent is also mout_core. So + * ATB clock also needs to be mantained at safe speed. + */ + alt_div |= E4210_DIV0_ATB_MASK; + alt_div_mask |= E4210_DIV0_ATB_MASK; + } + exynos_set_safe_div(base, alt_div, alt_div_mask); + div0 |= alt_div; + } + + /* select sclk_mpll as the alternate parent */ + mux_reg = readl(base + E4210_SRC_CPU); + writel(mux_reg | (1 << 16), base + E4210_SRC_CPU); + wait_until_mux_stable(base + E4210_STAT_CPU, 16, 2); + + /* alternate parent is active now. set the dividers */ + writel(div0, base + E4210_DIV_CPU0); + wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, DIV_MASK_ALL); + + if (cpuclk->flags & CLK_CPU_HAS_DIV1) { + writel(div1, base + E4210_DIV_CPU1); + wait_until_divider_stable(base + E4210_DIV_STAT_CPU1, + DIV_MASK_ALL); + } + + spin_unlock_irqrestore(cpuclk->lock, flags); + return 0; +} + +/* handler for post-rate change notification from parent clock */ +static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata, + struct exynos_cpuclk *cpuclk, void __iomem *base) +{ + const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg; + unsigned long div = 0, div_mask = DIV_MASK; + unsigned long mux_reg; + unsigned long flags; + + /* find out the divider values to use for clock data */ + if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) { + while ((cfg_data->prate * 1000) != ndata->new_rate) { + if (cfg_data->prate == 0) + return -EINVAL; + cfg_data++; + } + } + + spin_lock_irqsave(cpuclk->lock, flags); + + /* select mout_apll as the alternate parent */ + mux_reg = readl(base + E4210_SRC_CPU); + writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU); + wait_until_mux_stable(base + E4210_STAT_CPU, 16, 1); + + if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) { + div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK); + div_mask |= E4210_DIV0_ATB_MASK; + } + + exynos_set_safe_div(base, div, div_mask); + spin_unlock_irqrestore(cpuclk->lock, flags); + return 0; +} + +/* + * This notifier function is called for the pre-rate and post-rate change + * notifications of the parent clock of cpuclk. + */ +static int exynos_cpuclk_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct clk_notifier_data *ndata = data; + struct exynos_cpuclk *cpuclk; + void __iomem *base; + int err = 0; + + cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb); + base = cpuclk->ctrl_base; + + if (event == PRE_RATE_CHANGE) + err = exynos_cpuclk_pre_rate_change(ndata, cpuclk, base); + else if (event == POST_RATE_CHANGE) + err = exynos_cpuclk_post_rate_change(ndata, cpuclk, base); + + return notifier_from_errno(err); +} + +/* helper function to register a CPU clock */ +int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, + unsigned int lookup_id, const char *name, const char *parent, + const char *alt_parent, unsigned long offset, + const struct exynos_cpuclk_cfg_data *cfg, + unsigned long num_cfgs, unsigned long flags) +{ + struct exynos_cpuclk *cpuclk; + struct clk_init_data init; + struct clk *clk; + int ret = 0; + + cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL); + if (!cpuclk) + return -ENOMEM; + + init.name = name; + init.flags = CLK_SET_RATE_PARENT; + init.parent_names = &parent; + init.num_parents = 1; + init.ops = &exynos_cpuclk_clk_ops; + + cpuclk->hw.init = &init; + cpuclk->ctrl_base = ctx->reg_base + offset; + cpuclk->lock = &ctx->lock; + cpuclk->flags = flags; + cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb; + + cpuclk->alt_parent = __clk_lookup(alt_parent); + if (!cpuclk->alt_parent) { + pr_err("%s: could not lookup alternate parent %s\n", + __func__, alt_parent); + ret = -EINVAL; + goto free_cpuclk; + } + + clk = __clk_lookup(parent); + if (!clk) { + pr_err("%s: could not lookup parent clock %s\n", + __func__, parent); + ret = -EINVAL; + goto free_cpuclk; + } + + ret = clk_notifier_register(clk, &cpuclk->clk_nb); + if (ret) { + pr_err("%s: failed to register clock notifier for %s\n", + __func__, name); + goto free_cpuclk; + } + + cpuclk->cfg = kmemdup(cfg, sizeof(*cfg) * num_cfgs, GFP_KERNEL); + if (!cpuclk->cfg) { + pr_err("%s: could not allocate memory for cpuclk data\n", + __func__); + ret = -ENOMEM; + goto unregister_clk_nb; + } + + clk = clk_register(NULL, &cpuclk->hw); + if (IS_ERR(clk)) { + pr_err("%s: could not register cpuclk %s\n", __func__, name); + ret = PTR_ERR(clk); + goto free_cpuclk_data; + } + + samsung_clk_add_lookup(ctx, clk, lookup_id); + return 0; + +free_cpuclk_data: + kfree(cpuclk->cfg); +unregister_clk_nb: + clk_notifier_unregister(__clk_lookup(parent), &cpuclk->clk_nb); +free_cpuclk: + kfree(cpuclk); + return ret; +} diff --git a/kernel/drivers/clk/samsung/clk-cpu.h b/kernel/drivers/clk/samsung/clk-cpu.h new file mode 100644 index 000000000..37874d3c3 --- /dev/null +++ b/kernel/drivers/clk/samsung/clk-cpu.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common Clock Framework support for all PLL's in Samsung platforms +*/ + +#ifndef __SAMSUNG_CLK_CPU_H +#define __SAMSUNG_CLK_CPU_H + +#include "clk.h" + +/** + * struct exynos_cpuclk_data: config data to setup cpu clocks. + * @prate: frequency of the primary parent clock (in KHz). + * @div0: value to be programmed in the div_cpu0 register. + * @div1: value to be programmed in the div_cpu1 register. + * + * This structure holds the divider configuration data for dividers in the CPU + * clock domain. The parent frequency at which these divider values are valid is + * specified in @prate. The @prate is the frequency of the primary parent clock. + * For CPU clock domains that do not have a DIV1 register, the @div1 member + * value is not used. + */ +struct exynos_cpuclk_cfg_data { + unsigned long prate; + unsigned long div0; + unsigned long div1; +}; + +/** + * struct exynos_cpuclk: information about clock supplied to a CPU core. + * @hw: handle between CCF and CPU clock. + * @alt_parent: alternate parent clock to use when switching the speed + * of the primary parent clock. + * @ctrl_base: base address of the clock controller. + * @lock: cpu clock domain register access lock. + * @cfg: cpu clock rate configuration data. + * @num_cfgs: number of array elements in @cfg array. + * @clk_nb: clock notifier registered for changes in clock speed of the + * primary parent clock. + * @flags: configuration flags for the CPU clock. + * + * This structure holds information required for programming the CPU clock for + * various clock speeds. + */ +struct exynos_cpuclk { + struct clk_hw hw; + struct clk *alt_parent; + void __iomem *ctrl_base; + spinlock_t *lock; + const struct exynos_cpuclk_cfg_data *cfg; + const unsigned long num_cfgs; + struct notifier_block clk_nb; + unsigned long flags; + +/* The CPU clock registers has DIV1 configuration register */ +#define CLK_CPU_HAS_DIV1 (1 << 0) +/* When ALT parent is active, debug clocks need safe divider values */ +#define CLK_CPU_NEEDS_DEBUG_ALT_DIV (1 << 1) +}; + +extern int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, + unsigned int lookup_id, const char *name, + const char *parent, const char *alt_parent, + unsigned long offset, + const struct exynos_cpuclk_cfg_data *cfg, + unsigned long num_cfgs, unsigned long flags); + +#endif /* __SAMSUNG_CLK_CPU_H */ diff --git a/kernel/drivers/clk/samsung/clk-exynos-audss.c b/kernel/drivers/clk/samsung/clk-exynos-audss.c index 454b02ae4..4e9584d79 100644 --- a/kernel/drivers/clk/samsung/clk-exynos-audss.c +++ b/kernel/drivers/clk/samsung/clk-exynos-audss.c @@ -9,8 +9,9 @@ * Common Clock Framework support for Audio Subsystem Clock Controller. */ -#include <linux/clkdev.h> +#include <linux/slab.h> #include <linux/io.h> +#include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/of_address.h> #include <linux/syscore_ops.h> diff --git a/kernel/drivers/clk/samsung/clk-exynos-clkout.c b/kernel/drivers/clk/samsung/clk-exynos-clkout.c index 03a52228b..7cd02ff37 100644 --- a/kernel/drivers/clk/samsung/clk-exynos-clkout.c +++ b/kernel/drivers/clk/samsung/clk-exynos-clkout.c @@ -9,8 +9,8 @@ * Clock driver for Exynos clock output */ +#include <linux/slab.h> #include <linux/clk.h> -#include <linux/clkdev.h> #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> diff --git a/kernel/drivers/clk/samsung/clk-exynos3250.c b/kernel/drivers/clk/samsung/clk-exynos3250.c index 538de66a7..fdd41b17a 100644 --- a/kernel/drivers/clk/samsung/clk-exynos3250.c +++ b/kernel/drivers/clk/samsung/clk-exynos3250.c @@ -8,8 +8,6 @@ * Common Clock Framework support for Exynos3250 SoC. */ -#include <linux/clk.h> -#include <linux/clkdev.h> #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> @@ -19,6 +17,7 @@ #include <dt-bindings/clock/exynos3250.h> #include "clk.h" +#include "clk-cpu.h" #include "clk-pll.h" #define SRC_LEFTBUS 0x4200 @@ -319,8 +318,10 @@ static struct samsung_mux_clock mux_clks[] __initdata = { MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p, SRC_CPU, 24, 1), MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1), - MUX(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1), - MUX(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), + MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1, + CLK_SET_RATE_PARENT, 0), + MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, + CLK_SET_RATE_PARENT, 0), }; static struct samsung_div_clock div_clks[] __initdata = { @@ -772,6 +773,26 @@ static struct samsung_cmu_info cmu_info __initdata = { .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs), }; +#define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \ + (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ + ((corem) << 4)) +#define E3250_CPU_DIV1(hpm, copy) \ + (((hpm) << 4) | ((copy) << 0)) + +static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = { + { 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), }, + { 900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), }, + { 100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), }, + { 0 }, +}; + static void __init exynos3250_cmu_init(struct device_node *np) { struct samsung_clk_provider *ctx; @@ -780,6 +801,11 @@ static void __init exynos3250_cmu_init(struct device_node *np) if (!ctx) return; + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", + mout_core_p[0], mout_core_p[1], 0x14200, + e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d), + CLK_CPU_HAS_DIV1); + exynos3_core_down_clock(ctx->reg_base); } CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init); diff --git a/kernel/drivers/clk/samsung/clk-exynos4.c b/kernel/drivers/clk/samsung/clk-exynos4.c index f7890bf65..7f370d3e0 100644 --- a/kernel/drivers/clk/samsung/clk-exynos4.c +++ b/kernel/drivers/clk/samsung/clk-exynos4.c @@ -11,14 +11,15 @@ */ #include <dt-bindings/clock/exynos4.h> +#include <linux/slab.h> #include <linux/clk.h> -#include <linux/clkdev.h> #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/syscore_ops.h> #include "clk.h" +#include "clk-cpu.h" /* Exynos4 clock controller register offsets */ #define SRC_LEFTBUS 0x4200 @@ -535,7 +536,8 @@ static struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initda /* list of mux clocks supported in all exynos4 soc's */ static struct samsung_mux_clock exynos4_mux_clks[] __initdata = { MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, - CLK_SET_RATE_PARENT, 0, "mout_apll"), + CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0, + "mout_apll"), MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1), MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), @@ -1380,6 +1382,61 @@ static void __init exynos4x12_core_down_clock(void) __raw_writel(0x0, reg_base + E4X12_PWR_CTRL2); } +#define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0) \ + (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ + ((periph) << 12) | ((corem1) << 8) | ((corem0) << 4)) +#define E4210_CPU_DIV1(hpm, copy) \ + (((hpm) << 4) | ((copy) << 0)) + +static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = { + { 1200000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), }, + { 1000000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), }, + { 800000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), }, + { 500000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), }, + { 400000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), }, + { 200000, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), }, + { 0 }, +}; + +static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = { + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), }, + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), }, + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), }, + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), }, + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), }, + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), }, + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), }, + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), }, + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), }, + { 0 }, +}; + +#define E4412_CPU_DIV1(cores, hpm, copy) \ + (((cores) << 8) | ((hpm) << 4) | ((copy) << 0)) + +static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = { + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), }, + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), }, + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), }, + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), }, + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), }, + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), }, + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), }, + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), }, + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), }, + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), }, + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), }, + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), }, + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), }, + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), }, + { 0 }, +}; + /* register exynos4 clocks */ static void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc soc) @@ -1457,6 +1514,10 @@ static void __init exynos4_clk_init(struct device_node *np, samsung_clk_register_fixed_factor(ctx, exynos4210_fixed_factor_clks, ARRAY_SIZE(exynos4210_fixed_factor_clks)); + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", + mout_core_p4210[0], mout_core_p4210[1], 0x14200, + e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d), + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); } else { samsung_clk_register_mux(ctx, exynos4x12_mux_clks, ARRAY_SIZE(exynos4x12_mux_clks)); @@ -1469,6 +1530,17 @@ static void __init exynos4_clk_init(struct device_node *np, samsung_clk_register_fixed_factor(ctx, exynos4x12_fixed_factor_clks, ARRAY_SIZE(exynos4x12_fixed_factor_clks)); + if (of_machine_is_compatible("samsung,exynos4412")) { + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", + mout_core_p4x12[0], mout_core_p4x12[1], 0x14200, + e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d), + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); + } else { + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", + mout_core_p4x12[0], mout_core_p4x12[1], 0x14200, + e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d), + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); + } } samsung_clk_register_alias(ctx, exynos4_aliases, diff --git a/kernel/drivers/clk/samsung/clk-exynos4415.c b/kernel/drivers/clk/samsung/clk-exynos4415.c index 6c78b09c8..92c39f6ef 100644 --- a/kernel/drivers/clk/samsung/clk-exynos4415.c +++ b/kernel/drivers/clk/samsung/clk-exynos4415.c @@ -9,8 +9,6 @@ * Common Clock Framework support for Exynos4415 SoC. */ -#include <linux/clk.h> -#include <linux/clkdev.h> #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> diff --git a/kernel/drivers/clk/samsung/clk-exynos5250.c b/kernel/drivers/clk/samsung/clk-exynos5250.c index 70ec3d260..5bebf8cb0 100644 --- a/kernel/drivers/clk/samsung/clk-exynos5250.c +++ b/kernel/drivers/clk/samsung/clk-exynos5250.c @@ -11,14 +11,13 @@ */ #include <dt-bindings/clock/exynos5250.h> -#include <linux/clk.h> -#include <linux/clkdev.h> #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/syscore_ops.h> #include "clk.h" +#include "clk-cpu.h" #define APLL_LOCK 0x0 #define APLL_CON0 0x100 @@ -223,9 +222,13 @@ PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" }; PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" }; PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" }; PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" }; +PNAME(mout_aclk300_p) = { "mout_aclk300_disp1_mid", + "mout_aclk300_disp1_mid1" }; PNAME(mout_aclk400_p) = { "mout_aclk400_g3d_mid", "mout_gpll" }; PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" }; PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" }; +PNAME(mout_aclk300_sub_p) = { "fin_pll", "div_aclk300_disp" }; +PNAME(mout_aclk300_disp1_mid1_p) = { "mout_vpll", "mout_cpll" }; PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" }; PNAME(mout_aclk400_isp_sub_p) = { "fin_pll", "div_aclk400_isp" }; PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" }; @@ -304,9 +307,13 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { */ MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1), MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1), + MUX(0, "mout_aclk300_disp1_mid", mout_aclk200_p, SRC_TOP0, 14, 1), + MUX(0, "mout_aclk300", mout_aclk300_p, SRC_TOP0, 15, 1), MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1), MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1), + MUX(0, "mout_aclk300_disp1_mid1", mout_aclk300_disp1_mid1_p, SRC_TOP1, + 8, 1), MUX(0, "mout_aclk400_isp", mout_aclk200_p, SRC_TOP1, 24, 1), MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1), @@ -317,7 +324,10 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1), MUX(CLK_MOUT_GPLL, "mout_gpll", mout_gpll_p, SRC_TOP2, 28, 1), - MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1), + MUX(CLK_MOUT_ACLK200_DISP1_SUB, "mout_aclk200_disp1_sub", + mout_aclk200_sub_p, SRC_TOP3, 4, 1), + MUX(CLK_MOUT_ACLK300_DISP1_SUB, "mout_aclk300_disp1_sub", + mout_aclk300_sub_p, SRC_TOP3, 6, 1), MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1), MUX(0, "mout_aclk_266_isp_sub", mout_aclk266_sub_p, SRC_TOP3, 16, 1), MUX(0, "mout_aclk_400_isp_sub", mout_aclk400_isp_sub_p, @@ -393,6 +403,7 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = { DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3), DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0, 24, 3), + DIV(0, "div_aclk300_disp", "mout_aclk300", DIV_TOP0, 28, 3), DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1, 20, 3), DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3), @@ -748,6 +759,32 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = { VPLL_LOCK, VPLL_CON0, NULL), }; +#define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud) \ + ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ + ((periph) << 12) | ((acp) << 8) | ((cpud) << 4))) +#define E5250_CPU_DIV1(hpm, copy) \ + (((hpm) << 4) | (copy)) + +static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = { + { 1700000, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), }, + { 1600000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), }, + { 1500000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), }, + { 1400000, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), }, + { 1300000, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), }, + { 1200000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), }, + { 1100000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), }, + { 1000000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 900000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 800000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 700000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 600000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 500000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 400000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 300000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 200000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, + { 0 }, +}; + static const struct of_device_id ext_clk_match[] __initconst = { { .compatible = "samsung,clock-xxti", .data = (void *)0, }, { }, @@ -797,6 +834,10 @@ static void __init exynos5250_clk_init(struct device_node *np) ARRAY_SIZE(exynos5250_div_clks)); samsung_clk_register_gate(ctx, exynos5250_gate_clks, ARRAY_SIZE(exynos5250_gate_clks)); + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", + mout_cpu_p[0], mout_cpu_p[1], 0x200, + exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d), + CLK_CPU_HAS_DIV1); /* * Enable arm clock down (in idle) and set arm divider diff --git a/kernel/drivers/clk/samsung/clk-exynos5260.c b/kernel/drivers/clk/samsung/clk-exynos5260.c index e2e5193d1..d1a29f6c1 100644 --- a/kernel/drivers/clk/samsung/clk-exynos5260.c +++ b/kernel/drivers/clk/samsung/clk-exynos5260.c @@ -9,8 +9,6 @@ * Common Clock Framework support for Exynos5260 SoC. */ -#include <linux/clk.h> -#include <linux/clkdev.h> #include <linux/of.h> #include <linux/of_address.h> @@ -94,7 +92,7 @@ PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"}; PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user", "ioclk_i2s_cdclk"}; PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user", "ioclk_pcm_extclk"}; -struct samsung_mux_clock aud_mux_clks[] __initdata = { +static struct samsung_mux_clock aud_mux_clks[] __initdata = { MUX(AUD_MOUT_AUD_PLL_USER, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 0, 1), MUX(AUD_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p, @@ -103,7 +101,7 @@ struct samsung_mux_clock aud_mux_clks[] __initdata = { MUX_SEL_AUD, 8, 1), }; -struct samsung_div_clock aud_div_clks[] __initdata = { +static struct samsung_div_clock aud_div_clks[] __initdata = { DIV(AUD_DOUT_ACLK_AUD_131, "dout_aclk_aud_131", "mout_aud_pll_user", DIV_AUD0, 0, 4), @@ -115,7 +113,7 @@ struct samsung_div_clock aud_div_clks[] __initdata = { DIV_AUD1, 12, 4), }; -struct samsung_gate_clock aud_gate_clks[] __initdata = { +static struct samsung_gate_clock aud_gate_clks[] __initdata = { GATE(AUD_SCLK_I2S, "sclk_aud_i2s", "dout_sclk_aud_i2s", EN_SCLK_AUD, 0, CLK_SET_RATE_PARENT, 0), GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm", @@ -135,7 +133,7 @@ struct samsung_gate_clock aud_gate_clks[] __initdata = { static void __init exynos5260_clk_aud_init(struct device_node *np) { - struct samsung_cmu_info cmu = {0}; + struct samsung_cmu_info cmu = { NULL }; cmu.mux_clks = aud_mux_clks; cmu.nr_mux_clks = ARRAY_SIZE(aud_mux_clks); @@ -203,7 +201,7 @@ PNAME(mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p) = {"fin_pll", PNAME(mout_sclk_hdmi_spdif_p) = {"fin_pll", "ioclk_spdif_extclk", "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"}; -struct samsung_mux_clock disp_mux_clks[] __initdata = { +static struct samsung_mux_clock disp_mux_clks[] __initdata = { MUX(DISP_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user", mout_aclk_disp_333_user_p, MUX_SEL_DISP0, 0, 1), @@ -272,7 +270,7 @@ struct samsung_mux_clock disp_mux_clks[] __initdata = { MUX_SEL_DISP4, 4, 2), }; -struct samsung_div_clock disp_div_clks[] __initdata = { +static struct samsung_div_clock disp_div_clks[] __initdata = { DIV(DISP_DOUT_PCLK_DISP_111, "dout_pclk_disp_111", "mout_aclk_disp_222_user", DIV_DISP, 8, 4), @@ -285,7 +283,7 @@ struct samsung_div_clock disp_div_clks[] __initdata = { DIV_DISP, 16, 4), }; -struct samsung_gate_clock disp_gate_clks[] __initdata = { +static struct samsung_gate_clock disp_gate_clks[] __initdata = { GATE(DISP_MOUT_HDMI_PHY_PIXEL_USER, "sclk_hdmi_link_i_pixel", "mout_phyclk_hdmi_phy_pixel_clko_user", EN_SCLK_DISP0, 26, CLK_SET_RATE_PARENT, 0), @@ -325,7 +323,7 @@ struct samsung_gate_clock disp_gate_clks[] __initdata = { static void __init exynos5260_clk_disp_init(struct device_node *np) { - struct samsung_cmu_info cmu = {0}; + struct samsung_cmu_info cmu = { NULL }; cmu.mux_clks = disp_mux_clks; cmu.nr_mux_clks = ARRAY_SIZE(disp_mux_clks); @@ -363,13 +361,13 @@ static unsigned long egl_clk_regs[] __initdata = { PNAME(mout_egl_b_p) = {"mout_egl_pll", "dout_bus_pll"}; PNAME(mout_egl_pll_p) = {"fin_pll", "fout_egl_pll"}; -struct samsung_mux_clock egl_mux_clks[] __initdata = { +static struct samsung_mux_clock egl_mux_clks[] __initdata = { MUX(EGL_MOUT_EGL_PLL, "mout_egl_pll", mout_egl_pll_p, MUX_SEL_EGL, 4, 1), MUX(EGL_MOUT_EGL_B, "mout_egl_b", mout_egl_b_p, MUX_SEL_EGL, 16, 1), }; -struct samsung_div_clock egl_div_clks[] __initdata = { +static struct samsung_div_clock egl_div_clks[] __initdata = { DIV(EGL_DOUT_EGL1, "dout_egl1", "mout_egl_b", DIV_EGL, 0, 3), DIV(EGL_DOUT_EGL2, "dout_egl2", "dout_egl1", DIV_EGL, 4, 3), DIV(EGL_DOUT_ACLK_EGL, "dout_aclk_egl", "dout_egl2", DIV_EGL, 8, 3), @@ -389,7 +387,7 @@ static struct samsung_pll_clock egl_pll_clks[] __initdata = { static void __init exynos5260_clk_egl_init(struct device_node *np) { - struct samsung_cmu_info cmu = {0}; + struct samsung_cmu_info cmu = { NULL }; cmu.pll_clks = egl_pll_clks; cmu.nr_pll_clks = ARRAY_SIZE(egl_pll_clks); @@ -433,7 +431,7 @@ PNAME(mout_phyclk_usbdrd30_pipe_pclk_user_p) = {"fin_pll", PNAME(mout_phyclk_usbdrd30_phyclock_user_p) = {"fin_pll", "phyclk_usbdrd30_udrd30_phyclock"}; -struct samsung_mux_clock fsys_mux_clks[] __initdata = { +static struct samsung_mux_clock fsys_mux_clks[] __initdata = { MUX(FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER, "mout_phyclk_usbdrd30_phyclock_user", mout_phyclk_usbdrd30_phyclock_user_p, @@ -456,7 +454,7 @@ struct samsung_mux_clock fsys_mux_clks[] __initdata = { MUX_SEL_FSYS1, 16, 1), }; -struct samsung_gate_clock fsys_gate_clks[] __initdata = { +static struct samsung_gate_clock fsys_gate_clks[] __initdata = { GATE(FSYS_PHYCLK_USBHOST20, "phyclk_usbhost20_phyclock", "mout_phyclk_usbdrd30_phyclock_user", EN_SCLK_FSYS, 1, 0, 0), @@ -491,7 +489,7 @@ struct samsung_gate_clock fsys_gate_clks[] __initdata = { static void __init exynos5260_clk_fsys_init(struct device_node *np) { - struct samsung_cmu_info cmu = {0}; + struct samsung_cmu_info cmu = { NULL }; cmu.mux_clks = fsys_mux_clks; cmu.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks); @@ -537,18 +535,18 @@ static unsigned long g2d_clk_regs[] __initdata = { PNAME(mout_aclk_g2d_333_user_p) = {"fin_pll", "dout_aclk_g2d_333"}; -struct samsung_mux_clock g2d_mux_clks[] __initdata = { +static struct samsung_mux_clock g2d_mux_clks[] __initdata = { MUX(G2D_MOUT_ACLK_G2D_333_USER, "mout_aclk_g2d_333_user", mout_aclk_g2d_333_user_p, MUX_SEL_G2D, 0, 1), }; -struct samsung_div_clock g2d_div_clks[] __initdata = { +static struct samsung_div_clock g2d_div_clks[] __initdata = { DIV(G2D_DOUT_PCLK_G2D_83, "dout_pclk_g2d_83", "mout_aclk_g2d_333_user", DIV_G2D, 0, 3), }; -struct samsung_gate_clock g2d_gate_clks[] __initdata = { +static struct samsung_gate_clock g2d_gate_clks[] __initdata = { GATE(G2D_CLK_G2D, "clk_g2d", "mout_aclk_g2d_333_user", EN_IP_G2D, 4, 0, 0), GATE(G2D_CLK_JPEG, "clk_jpeg", "mout_aclk_g2d_333_user", @@ -580,7 +578,7 @@ struct samsung_gate_clock g2d_gate_clks[] __initdata = { static void __init exynos5260_clk_g2d_init(struct device_node *np) { - struct samsung_cmu_info cmu = {0}; + struct samsung_cmu_info cmu = { NULL }; cmu.mux_clks = g2d_mux_clks; cmu.nr_mux_clks = ARRAY_SIZE(g2d_mux_clks); @@ -617,17 +615,17 @@ static unsigned long g3d_clk_regs[] __initdata = { PNAME(mout_g3d_pll_p) = {"fin_pll", "fout_g3d_pll"}; -struct samsung_mux_clock g3d_mux_clks[] __initdata = { +static struct samsung_mux_clock g3d_mux_clks[] __initdata = { MUX(G3D_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, MUX_SEL_G3D, 0, 1), }; -struct samsung_div_clock g3d_div_clks[] __initdata = { +static struct samsung_div_clock g3d_div_clks[] __initdata = { DIV(G3D_DOUT_PCLK_G3D, "dout_pclk_g3d", "dout_aclk_g3d", DIV_G3D, 0, 3), DIV(G3D_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_g3d_pll", DIV_G3D, 4, 3), }; -struct samsung_gate_clock g3d_gate_clks[] __initdata = { +static struct samsung_gate_clock g3d_gate_clks[] __initdata = { GATE(G3D_CLK_G3D, "clk_g3d", "dout_aclk_g3d", EN_IP_G3D, 2, 0, 0), GATE(G3D_CLK_G3D_HPM, "clk_g3d_hpm", "dout_aclk_g3d", EN_IP_G3D, 3, 0, 0), @@ -641,7 +639,7 @@ static struct samsung_pll_clock g3d_pll_clks[] __initdata = { static void __init exynos5260_clk_g3d_init(struct device_node *np) { - struct samsung_cmu_info cmu = {0}; + struct samsung_cmu_info cmu = { NULL }; cmu.pll_clks = g3d_pll_clks; cmu.nr_pll_clks = ARRAY_SIZE(g3d_pll_clks); @@ -694,7 +692,7 @@ PNAME(mout_aclk_m2m_400_user_p) = {"fin_pll", "dout_aclk_gscl_400"}; PNAME(mout_aclk_gscl_fimc_user_p) = {"fin_pll", "dout_aclk_gscl_400"}; PNAME(mout_aclk_csis_p) = {"dout_aclk_csis_200", "mout_aclk_gscl_fimc_user"}; -struct samsung_mux_clock gscl_mux_clks[] __initdata = { +static struct samsung_mux_clock gscl_mux_clks[] __initdata = { MUX(GSCL_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user", mout_aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1), @@ -708,7 +706,7 @@ struct samsung_mux_clock gscl_mux_clks[] __initdata = { MUX_SEL_GSCL, 24, 1), }; -struct samsung_div_clock gscl_div_clks[] __initdata = { +static struct samsung_div_clock gscl_div_clks[] __initdata = { DIV(GSCL_DOUT_PCLK_M2M_100, "dout_pclk_m2m_100", "mout_aclk_m2m_400_user", DIV_GSCL, 0, 3), @@ -717,7 +715,7 @@ struct samsung_div_clock gscl_div_clks[] __initdata = { DIV_GSCL, 4, 3), }; -struct samsung_gate_clock gscl_gate_clks[] __initdata = { +static struct samsung_gate_clock gscl_gate_clks[] __initdata = { GATE(GSCL_SCLK_CSIS0_WRAP, "sclk_csis0_wrap", "dout_aclk_csis_200", EN_SCLK_GSCL_FIMC, 0, CLK_SET_RATE_PARENT, 0), GATE(GSCL_SCLK_CSIS1_WRAP, "sclk_csis1_wrap", "dout_aclk_csis_200", @@ -776,7 +774,7 @@ struct samsung_gate_clock gscl_gate_clks[] __initdata = { static void __init exynos5260_clk_gscl_init(struct device_node *np) { - struct samsung_cmu_info cmu = {0}; + struct samsung_cmu_info cmu = { NULL }; cmu.mux_clks = gscl_mux_clks; cmu.nr_mux_clks = ARRAY_SIZE(gscl_mux_clks); @@ -813,14 +811,14 @@ static unsigned long isp_clk_regs[] __initdata = { PNAME(mout_isp_400_user_p) = {"fin_pll", "dout_aclk_isp1_400"}; PNAME(mout_isp_266_user_p) = {"fin_pll", "dout_aclk_isp1_266"}; -struct samsung_mux_clock isp_mux_clks[] __initdata = { +static struct samsung_mux_clock isp_mux_clks[] __initdata = { MUX(ISP_MOUT_ISP_266_USER, "mout_isp_266_user", mout_isp_266_user_p, MUX_SEL_ISP0, 0, 1), MUX(ISP_MOUT_ISP_400_USER, "mout_isp_400_user", mout_isp_400_user_p, MUX_SEL_ISP0, 4, 1), }; -struct samsung_div_clock isp_div_clks[] __initdata = { +static struct samsung_div_clock isp_div_clks[] __initdata = { DIV(ISP_DOUT_PCLK_ISP_66, "dout_pclk_isp_66", "mout_kfc", DIV_ISP, 0, 3), DIV(ISP_DOUT_PCLK_ISP_133, "dout_pclk_isp_133", "mout_kfc", @@ -832,7 +830,7 @@ struct samsung_div_clock isp_div_clks[] __initdata = { DIV(ISP_DOUT_SCLK_MPWM, "dout_sclk_mpwm", "mout_kfc", DIV_ISP, 20, 2), }; -struct samsung_gate_clock isp_gate_clks[] __initdata = { +static struct samsung_gate_clock isp_gate_clks[] __initdata = { GATE(ISP_CLK_GIC, "clk_isp_gic", "mout_aclk_isp1_266", EN_IP_ISP0, 15, 0, 0), @@ -895,7 +893,7 @@ struct samsung_gate_clock isp_gate_clks[] __initdata = { static void __init exynos5260_clk_isp_init(struct device_node *np) { - struct samsung_cmu_info cmu = {0}; + struct samsung_cmu_info cmu = { NULL }; cmu.mux_clks = isp_mux_clks; cmu.nr_mux_clks = ARRAY_SIZE(isp_mux_clks); @@ -934,13 +932,13 @@ static unsigned long kfc_clk_regs[] __initdata = { PNAME(mout_kfc_pll_p) = {"fin_pll", "fout_kfc_pll"}; PNAME(mout_kfc_p) = {"mout_kfc_pll", "dout_media_pll"}; -struct samsung_mux_clock kfc_mux_clks[] __initdata = { +static struct samsung_mux_clock kfc_mux_clks[] __initdata = { MUX(KFC_MOUT_KFC_PLL, "mout_kfc_pll", mout_kfc_pll_p, MUX_SEL_KFC0, 0, 1), MUX(KFC_MOUT_KFC, "mout_kfc", mout_kfc_p, MUX_SEL_KFC2, 0, 1), }; -struct samsung_div_clock kfc_div_clks[] __initdata = { +static struct samsung_div_clock kfc_div_clks[] __initdata = { DIV(KFC_DOUT_KFC1, "dout_kfc1", "mout_kfc", DIV_KFC, 0, 3), DIV(KFC_DOUT_KFC2, "dout_kfc2", "dout_kfc1", DIV_KFC, 4, 3), DIV(KFC_DOUT_KFC_ATCLK, "dout_kfc_atclk", "dout_kfc2", DIV_KFC, 8, 3), @@ -959,7 +957,7 @@ static struct samsung_pll_clock kfc_pll_clks[] __initdata = { static void __init exynos5260_clk_kfc_init(struct device_node *np) { - struct samsung_cmu_info cmu = {0}; + struct samsung_cmu_info cmu = { NULL }; cmu.pll_clks = kfc_pll_clks; cmu.nr_pll_clks = ARRAY_SIZE(kfc_pll_clks); @@ -993,18 +991,18 @@ static unsigned long mfc_clk_regs[] __initdata = { PNAME(mout_aclk_mfc_333_user_p) = {"fin_pll", "dout_aclk_mfc_333"}; -struct samsung_mux_clock mfc_mux_clks[] __initdata = { +static struct samsung_mux_clock mfc_mux_clks[] __initdata = { MUX(MFC_MOUT_ACLK_MFC_333_USER, "mout_aclk_mfc_333_user", mout_aclk_mfc_333_user_p, MUX_SEL_MFC, 0, 1), }; -struct samsung_div_clock mfc_div_clks[] __initdata = { +static struct samsung_div_clock mfc_div_clks[] __initdata = { DIV(MFC_DOUT_PCLK_MFC_83, "dout_pclk_mfc_83", "mout_aclk_mfc_333_user", DIV_MFC, 0, 3), }; -struct samsung_gate_clock mfc_gate_clks[] __initdata = { +static struct samsung_gate_clock mfc_gate_clks[] __initdata = { GATE(MFC_CLK_MFC, "clk_mfc", "mout_aclk_mfc_333_user", EN_IP_MFC, 1, 0, 0), GATE(MFC_CLK_SMMU2_MFCM0, "clk_smmu2_mfcm0", "mout_aclk_mfc_333_user", @@ -1015,7 +1013,7 @@ struct samsung_gate_clock mfc_gate_clks[] __initdata = { static void __init exynos5260_clk_mfc_init(struct device_node *np) { - struct samsung_cmu_info cmu = {0}; + struct samsung_cmu_info cmu = { NULL }; cmu.mux_clks = mfc_mux_clks; cmu.nr_mux_clks = ARRAY_SIZE(mfc_mux_clks); @@ -1078,7 +1076,7 @@ PNAME(mout_mif_drex2x_p) = {"dout_mem_pll", "dout_bus_pll"}; PNAME(mout_clkm_phy_p) = {"mout_mif_drex", "dout_media_pll"}; PNAME(mout_clk2x_phy_p) = {"mout_mif_drex2x", "dout_media_pll"}; -struct samsung_mux_clock mif_mux_clks[] __initdata = { +static struct samsung_mux_clock mif_mux_clks[] __initdata = { MUX(MIF_MOUT_MEM_PLL, "mout_mem_pll", mout_mem_pll_p, MUX_SEL_MIF, 0, 1), MUX(MIF_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, @@ -1095,7 +1093,7 @@ struct samsung_mux_clock mif_mux_clks[] __initdata = { MUX_SEL_MIF, 24, 1), }; -struct samsung_div_clock mif_div_clks[] __initdata = { +static struct samsung_div_clock mif_div_clks[] __initdata = { DIV(MIF_DOUT_MEDIA_PLL, "dout_media_pll", "mout_media_pll", DIV_MIF, 0, 3), DIV(MIF_DOUT_MEM_PLL, "dout_mem_pll", "mout_mem_pll", @@ -1114,7 +1112,7 @@ struct samsung_div_clock mif_div_clks[] __initdata = { DIV_MIF, 28, 4), }; -struct samsung_gate_clock mif_gate_clks[] __initdata = { +static struct samsung_gate_clock mif_gate_clks[] __initdata = { GATE(MIF_CLK_LPDDR3PHY_WRAP0, "clk_lpddr3phy_wrap0", "dout_clk2x_phy", EN_IP_MIF, 12, CLK_IGNORE_UNUSED, 0), GATE(MIF_CLK_LPDDR3PHY_WRAP1, "clk_lpddr3phy_wrap1", "dout_clk2x_phy", @@ -1162,7 +1160,7 @@ static struct samsung_pll_clock mif_pll_clks[] __initdata = { static void __init exynos5260_clk_mif_init(struct device_node *np) { - struct samsung_cmu_info cmu = {0}; + struct samsung_cmu_info cmu = { NULL }; cmu.pll_clks = mif_pll_clks; cmu.nr_pll_clks = ARRAY_SIZE(mif_pll_clks); @@ -1221,7 +1219,7 @@ PNAME(mout_sclk_i2scod_p) = {"ioclk_i2s_cdclk", "fin_pll", "dout_aclk_peri_aud", PNAME(mout_sclk_spdif_p) = {"ioclk_spdif_extclk", "fin_pll", "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"}; -struct samsung_mux_clock peri_mux_clks[] __initdata = { +static struct samsung_mux_clock peri_mux_clks[] __initdata = { MUX(PERI_MOUT_SCLK_PCM, "mout_sclk_pcm", mout_sclk_pcm_p, MUX_SEL_PERI1, 4, 2), MUX(PERI_MOUT_SCLK_I2SCOD, "mout_sclk_i2scod", mout_sclk_i2scod_p, @@ -1230,12 +1228,12 @@ struct samsung_mux_clock peri_mux_clks[] __initdata = { MUX_SEL_PERI1, 20, 2), }; -struct samsung_div_clock peri_div_clks[] __initdata = { +static struct samsung_div_clock peri_div_clks[] __initdata = { DIV(PERI_DOUT_PCM, "dout_pcm", "mout_sclk_pcm", DIV_PERI, 0, 8), DIV(PERI_DOUT_I2S, "dout_i2s", "mout_sclk_i2scod", DIV_PERI, 8, 6), }; -struct samsung_gate_clock peri_gate_clks[] __initdata = { +static struct samsung_gate_clock peri_gate_clks[] __initdata = { GATE(PERI_SCLK_PCM1, "sclk_pcm1", "dout_pcm", EN_SCLK_PERI, 0, CLK_SET_RATE_PARENT, 0), GATE(PERI_SCLK_I2S, "sclk_i2s", "dout_i2s", EN_SCLK_PERI, 1, @@ -1370,7 +1368,7 @@ struct samsung_gate_clock peri_gate_clks[] __initdata = { static void __init exynos5260_clk_peri_init(struct device_node *np) { - struct samsung_cmu_info cmu = {0}; + struct samsung_cmu_info cmu = { NULL }; cmu.mux_clks = peri_mux_clks; cmu.nr_mux_clks = ARRAY_SIZE(peri_mux_clks); @@ -1432,7 +1430,7 @@ static unsigned long top_clk_regs[] __initdata = { }; /* fixed rate clocks generated inside the soc */ -struct samsung_fixed_rate_clock fixed_rate_clks[] __initdata = { +static struct samsung_fixed_rate_clock fixed_rate_clks[] __initdata = { FRATE(PHYCLK_DPTX_PHY_CH3_TXD_CLK, "phyclk_dptx_phy_ch3_txd_clk", NULL, CLK_IS_ROOT, 270000000), FRATE(PHYCLK_DPTX_PHY_CH2_TXD_CLK, "phyclk_dptx_phy_ch2_txd_clk", NULL, @@ -1519,7 +1517,7 @@ PNAME(mout_sclk_fsys_mmc1_sdclkin_b_p) = {"mout_sclk_fsys_mmc1_sdclkin_a", PNAME(mout_sclk_fsys_mmc2_sdclkin_b_p) = {"mout_sclk_fsys_mmc2_sdclkin_a", "mout_mediatop_pll_user"}; -struct samsung_mux_clock top_mux_clks[] __initdata = { +static struct samsung_mux_clock top_mux_clks[] __initdata = { MUX(TOP_MOUT_MEDIATOP_PLL_USER, "mout_mediatop_pll_user", mout_mediatop_pll_user_p, MUX_SEL_TOP_PLL0, 0, 1), @@ -1679,7 +1677,7 @@ struct samsung_mux_clock top_mux_clks[] __initdata = { MUX_SEL_TOP_GSCL, 20, 1), }; -struct samsung_div_clock top_div_clks[] __initdata = { +static struct samsung_div_clock top_div_clks[] __initdata = { DIV(TOP_DOUT_ACLK_G2D_333, "dout_aclk_g2d_333", "mout_aclk_g2d_333", DIV_TOP_G2D_MFC, 0, 3), DIV(TOP_DOUT_ACLK_MFC_333, "dout_aclk_mfc_333", "mout_aclk_mfc_333", @@ -1800,7 +1798,7 @@ struct samsung_div_clock top_div_clks[] __initdata = { }; -struct samsung_gate_clock top_gate_clks[] __initdata = { +static struct samsung_gate_clock top_gate_clks[] __initdata = { GATE(TOP_SCLK_MMC0, "sclk_fsys_mmc0_sdclkin", "dout_sclk_fsys_mmc0_sdclkin_b", EN_SCLK_TOP, 7, CLK_SET_RATE_PARENT, 0), @@ -1826,7 +1824,7 @@ static struct samsung_pll_clock top_pll_clks[] __initdata = { static void __init exynos5260_clk_top_init(struct device_node *np) { - struct samsung_cmu_info cmu = {0}; + struct samsung_cmu_info cmu = { NULL }; cmu.pll_clks = top_pll_clks; cmu.nr_pll_clks = ARRAY_SIZE(top_pll_clks); diff --git a/kernel/drivers/clk/samsung/clk-exynos5410.c b/kernel/drivers/clk/samsung/clk-exynos5410.c index 231475bc2..d5d5dcabc 100644 --- a/kernel/drivers/clk/samsung/clk-exynos5410.c +++ b/kernel/drivers/clk/samsung/clk-exynos5410.c @@ -11,8 +11,6 @@ #include <dt-bindings/clock/exynos5410.h> -#include <linux/clk.h> -#include <linux/clkdev.h> #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> diff --git a/kernel/drivers/clk/samsung/clk-exynos5420.c b/kernel/drivers/clk/samsung/clk-exynos5420.c index bea4a173e..389af3c15 100644 --- a/kernel/drivers/clk/samsung/clk-exynos5420.c +++ b/kernel/drivers/clk/samsung/clk-exynos5420.c @@ -11,8 +11,7 @@ */ #include <dt-bindings/clock/exynos5420.h> -#include <linux/clk.h> -#include <linux/clkdev.h> +#include <linux/slab.h> #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> @@ -504,7 +503,7 @@ static struct samsung_fixed_factor_clock FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), }; -struct samsung_mux_clock exynos5800_mux_clks[] __initdata = { +static struct samsung_mux_clock exynos5800_mux_clks[] __initdata = { MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3), MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3), MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3), @@ -553,7 +552,7 @@ struct samsung_mux_clock exynos5800_mux_clks[] __initdata = { MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3), }; -struct samsung_div_clock exynos5800_div_clks[] __initdata = { +static struct samsung_div_clock exynos5800_div_clks[] __initdata = { DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3), DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", @@ -569,14 +568,14 @@ struct samsung_div_clock exynos5800_div_clks[] __initdata = { DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6), }; -struct samsung_gate_clock exynos5800_gate_clks[] __initdata = { +static struct samsung_gate_clock exynos5800_gate_clks[] __initdata = { GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", GATE_BUS_TOP, 24, 0, 0), GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", GATE_BUS_TOP, 27, 0, 0), }; -struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { +static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1), MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p, TOP_SPARE2, 4, 1), @@ -606,7 +605,7 @@ struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), }; -struct samsung_div_clock exynos5420_div_clks[] __initdata = { +static struct samsung_div_clock exynos5420_div_clks[] __initdata = { DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3), }; diff --git a/kernel/drivers/clk/samsung/clk-exynos5433.c b/kernel/drivers/clk/samsung/clk-exynos5433.c index 9e04ae2bb..cee062c58 100644 --- a/kernel/drivers/clk/samsung/clk-exynos5433.c +++ b/kernel/drivers/clk/samsung/clk-exynos5433.c @@ -9,8 +9,6 @@ * Common Clock Framework support for Exynos5443 SoC. */ -#include <linux/clk.h> -#include <linux/clkdev.h> #include <linux/clk-provider.h> #include <linux/of.h> @@ -835,6 +833,7 @@ static unsigned long cpif_clk_regs[] __initdata = { MPHY_PLL_CON1, MPHY_PLL_FREQ_DET, MUX_SEL_CPIF0, + DIV_CPIF, ENABLE_SCLK_CPIF, }; @@ -1389,7 +1388,7 @@ static struct samsung_gate_clock mif_gate_clks[] __initdata = { /* ENABLE_ACLK_MIF2 */ GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266", - ENABLE_ACLK_MIF2, 20, 0, 0), + ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1", ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1", @@ -1832,39 +1831,39 @@ static struct samsung_gate_clock peris_gate_clks[] __initdata = { /* ENABLE_PCLK_PERIS_SECURE_TZPC */ GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66", - ENABLE_PCLK_PERIS_SECURE_TZPC, 12, 0, 0), + ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66", - ENABLE_PCLK_PERIS_SECURE_TZPC, 11, 0, 0), + ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66", - ENABLE_PCLK_PERIS_SECURE_TZPC, 10, 0, 0), + ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66", - ENABLE_PCLK_PERIS_SECURE_TZPC, 9, 0, 0), + ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66", - ENABLE_PCLK_PERIS_SECURE_TZPC, 8, 0, 0), + ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66", - ENABLE_PCLK_PERIS_SECURE_TZPC, 7, 0, 0), + ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66", - ENABLE_PCLK_PERIS_SECURE_TZPC, 6, 0, 0), + ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66", - ENABLE_PCLK_PERIS_SECURE_TZPC, 5, 0, 0), + ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66", - ENABLE_PCLK_PERIS_SECURE_TZPC, 4, 0, 0), + ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66", - ENABLE_PCLK_PERIS_SECURE_TZPC, 3, 0, 0), + ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66", - ENABLE_PCLK_PERIS_SECURE_TZPC, 2, 0, 0), + ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66", - ENABLE_PCLK_PERIS_SECURE_TZPC, 1, 0, 0), + ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0), GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66", - ENABLE_PCLK_PERIS_SECURE_TZPC, 0, 0, 0), + ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0), /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */ GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66", - ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, 0, 0), + ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0), /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */ GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66", - ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, 0, 0), + ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0), /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */ GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66", @@ -1895,11 +1894,11 @@ static struct samsung_gate_clock peris_gate_clks[] __initdata = { /* ENABLE_SCLK_PERIS_SECURE_SECKEY */ GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common", - ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, 0, 0), + ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0), /* ENABLE_SCLK_PERIS_SECURE_CHIPID */ GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common", - ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0), + ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0), /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */ GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common", @@ -3286,10 +3285,10 @@ static struct samsung_pll_clock g3d_pll_clks[] __initdata = { static struct samsung_mux_clock g3d_mux_clks[] __initdata = { /* MUX_SEL_G3D */ - MUX(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p, - MUX_SEL_G3D, 8, 1), - MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, - MUX_SEL_G3D, 0, 1), + MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p, + MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0), + MUX_F(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, + MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0), }; static struct samsung_div_clock g3d_div_clks[] __initdata = { @@ -3298,8 +3297,8 @@ static struct samsung_div_clock g3d_div_clks[] __initdata = { 8, 2), DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D, 4, 3), - DIV(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D, - 0, 3), + DIV_F(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D, + 0, 3, CLK_SET_RATE_PARENT, 0), }; static struct samsung_gate_clock g3d_gate_clks[] __initdata = { @@ -3309,9 +3308,9 @@ static struct samsung_gate_clock g3d_gate_clks[] __initdata = { GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d", ENABLE_ACLK_G3D, 6, 0, 0), GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d", - ENABLE_ACLK_G3D, 5, 0, 0), + ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d", - ENABLE_ACLK_G3D, 4, 0, 0), + ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d", ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d", @@ -3319,7 +3318,7 @@ static struct samsung_gate_clock g3d_gate_clks[] __initdata = { GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d", ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d", - ENABLE_ACLK_G3D, 0, 0, 0), + ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0), /* ENABLE_PCLK_G3D */ GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d", @@ -3582,7 +3581,7 @@ static struct samsung_pll_clock apollo_pll_clks[] __initdata = { static struct samsung_mux_clock apollo_mux_clks[] __initdata = { /* MUX_SEL_APOLLO0 */ MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p, - MUX_SEL_APOLLO0, 0, 1, 0, CLK_MUX_READ_ONLY), + MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT, 0), /* MUX_SEL_APOLLO1 */ MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user", @@ -3590,7 +3589,7 @@ static struct samsung_mux_clock apollo_mux_clks[] __initdata = { /* MUX_SEL_APOLLO2 */ MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2, - 0, 1, 0, CLK_MUX_READ_ONLY), + 0, 1, CLK_SET_RATE_PARENT, 0), }; static struct samsung_div_clock apollo_div_clks[] __initdata = { @@ -3611,11 +3610,9 @@ static struct samsung_div_clock apollo_div_clks[] __initdata = { DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1", - DIV_APOLLO0, 4, 3, CLK_GET_RATE_NOCACHE, - CLK_DIVIDER_READ_ONLY), + DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0), DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo", - DIV_APOLLO0, 0, 3, CLK_GET_RATE_NOCACHE, - CLK_DIVIDER_READ_ONLY), + DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0), /* DIV_APOLLO1 */ DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo", @@ -3666,7 +3663,8 @@ static struct samsung_gate_clock apollo_gate_clks[] __initdata = { GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo", ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo2", - ENABLE_SCLK_APOLLO, 0, CLK_IGNORE_UNUSED, 0), + ENABLE_SCLK_APOLLO, 0, + CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), }; static struct samsung_cmu_info apollo_cmu_info __initdata = { @@ -3775,7 +3773,7 @@ static struct samsung_pll_clock atlas_pll_clks[] __initdata = { static struct samsung_mux_clock atlas_mux_clks[] __initdata = { /* MUX_SEL_ATLAS0 */ MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p, - MUX_SEL_ATLAS0, 0, 1, 0, CLK_MUX_READ_ONLY), + MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT, 0), /* MUX_SEL_ATLAS1 */ MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user", @@ -3783,7 +3781,7 @@ static struct samsung_mux_clock atlas_mux_clks[] __initdata = { /* MUX_SEL_ATLAS2 */ MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2, - 0, 1, 0, CLK_MUX_READ_ONLY), + 0, 1, CLK_SET_RATE_PARENT, 0), }; static struct samsung_div_clock atlas_div_clks[] __initdata = { @@ -3804,11 +3802,9 @@ static struct samsung_div_clock atlas_div_clks[] __initdata = { DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1", - DIV_ATLAS0, 4, 3, CLK_GET_RATE_NOCACHE, - CLK_DIVIDER_READ_ONLY), + DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0), DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas", - DIV_ATLAS0, 0, 3, CLK_GET_RATE_NOCACHE, - CLK_DIVIDER_READ_ONLY), + DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0), /* DIV_ATLAS1 */ DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas", @@ -3885,7 +3881,8 @@ static struct samsung_gate_clock atlas_gate_clks[] __initdata = { GATE(CLK_ATCLK, "atclk", "div_atclk_atlas", ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_ATLAS, "sclk_atlas", "div_atlas2", - ENABLE_SCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0), + ENABLE_SCLK_ATLAS, 0, + CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), }; static struct samsung_cmu_info atlas_cmu_info __initdata = { diff --git a/kernel/drivers/clk/samsung/clk-exynos5440.c b/kernel/drivers/clk/samsung/clk-exynos5440.c index 979e81389..590813871 100644 --- a/kernel/drivers/clk/samsung/clk-exynos5440.c +++ b/kernel/drivers/clk/samsung/clk-exynos5440.c @@ -10,8 +10,6 @@ */ #include <dt-bindings/clock/exynos5440.h> -#include <linux/clk.h> -#include <linux/clkdev.h> #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> diff --git a/kernel/drivers/clk/samsung/clk-exynos7.c b/kernel/drivers/clk/samsung/clk-exynos7.c index 03d36e847..55f8e2e24 100644 --- a/kernel/drivers/clk/samsung/clk-exynos7.c +++ b/kernel/drivers/clk/samsung/clk-exynos7.c @@ -8,8 +8,6 @@ * */ -#include <linux/clk.h> -#include <linux/clkdev.h> #include <linux/clk-provider.h> #include <linux/of.h> @@ -34,39 +32,41 @@ #define DIV_TOPC0 0x0600 #define DIV_TOPC1 0x0604 #define DIV_TOPC3 0x060C +#define ENABLE_ACLK_TOPC0 0x0800 #define ENABLE_ACLK_TOPC1 0x0804 +#define ENABLE_SCLK_TOPC1 0x0A04 static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = { - FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0), + FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0), FFACTOR(0, "ffac_topc_bus0_pll_div4", "ffac_topc_bus0_pll_div2", 1, 2, 0), - FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0), - FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0), - FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0), + FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_topc_bus1_pll", 1, 2, 0), + FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_topc_cc_pll", 1, 2, 0), + FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_topc_mfc_pll", 1, 2, 0), }; /* List of parent clocks for Muxes in CMU_TOPC */ -PNAME(mout_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" }; -PNAME(mout_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" }; -PNAME(mout_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" }; -PNAME(mout_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" }; -PNAME(mout_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" }; +PNAME(mout_topc_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" }; +PNAME(mout_topc_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" }; +PNAME(mout_topc_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" }; +PNAME(mout_topc_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" }; +PNAME(mout_topc_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" }; -PNAME(mout_topc_group2) = { "mout_sclk_bus0_pll_cmuc", - "mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc", - "mout_sclk_mfc_pll_cmuc" }; +PNAME(mout_topc_group2) = { "mout_topc_bus0_pll_half", + "mout_topc_bus1_pll_half", "mout_topc_cc_pll_half", + "mout_topc_mfc_pll_half" }; -PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl", +PNAME(mout_topc_bus0_pll_half_p) = { "mout_topc_bus0_pll", "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"}; -PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl", +PNAME(mout_topc_bus1_pll_half_p) = { "mout_topc_bus1_pll", "ffac_topc_bus1_pll_div2"}; -PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl", +PNAME(mout_topc_cc_pll_half_p) = { "mout_topc_cc_pll", "ffac_topc_cc_pll_div2"}; -PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl", +PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll", "ffac_topc_mfc_pll_div2"}; -PNAME(mout_sclk_bus0_pll_out_p) = {"mout_bus0_pll_ctrl", +PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll", "ffac_topc_bus0_pll_div2"}; static unsigned long topc_clk_regs[] __initdata = { @@ -90,23 +90,27 @@ static unsigned long topc_clk_regs[] __initdata = { }; static struct samsung_mux_clock topc_mux_clks[] __initdata = { - MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1), - MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1), - MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1), - MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1), - - MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p, + MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p, + MUX_SEL_TOPC0, 0, 1), + MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p, + MUX_SEL_TOPC0, 4, 1), + MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p, + MUX_SEL_TOPC0, 8, 1), + MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p, + MUX_SEL_TOPC0, 12, 1), + MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p, MUX_SEL_TOPC0, 16, 2), - MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p, + MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p, MUX_SEL_TOPC0, 20, 1), - MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p, + MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p, MUX_SEL_TOPC0, 24, 1), - MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p, + MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p, MUX_SEL_TOPC0, 28, 1), - MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p, + MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p, + MUX_SEL_TOPC1, 0, 1), + MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p, MUX_SEL_TOPC1, 16, 1), - MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1), MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2), @@ -123,16 +127,16 @@ static struct samsung_div_clock topc_div_clks[] __initdata = { DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66", DIV_TOPC1, 24, 4), - DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out", - DIV_TOPC3, 0, 3), - DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl", - DIV_TOPC3, 8, 3), - DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl", - DIV_TOPC3, 12, 3), - DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl", - DIV_TOPC3, 16, 3), - DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_aud_pll_ctrl", - DIV_TOPC3, 28, 3), + DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_topc_bus0_pll_out", + DIV_TOPC3, 0, 4), + DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_topc_bus1_pll", + DIV_TOPC3, 8, 4), + DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_topc_cc_pll", + DIV_TOPC3, 12, 4), + DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_topc_mfc_pll", + DIV_TOPC3, 16, 4), + DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_topc_aud_pll", + DIV_TOPC3, 28, 4), }; static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = { @@ -141,8 +145,33 @@ static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = { }; static struct samsung_gate_clock topc_gate_clks[] __initdata = { + GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133", + ENABLE_ACLK_TOPC0, 4, 0, 0), + GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532", ENABLE_ACLK_TOPC1, 20, 0, 0), + + GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66", + ENABLE_ACLK_TOPC1, 24, 0, 0), + + GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll", + ENABLE_SCLK_TOPC1, 20, 0, 0), + GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll", + ENABLE_SCLK_TOPC1, 17, 0, 0), + GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll", + ENABLE_SCLK_TOPC1, 16, 0, 0), + GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll", + ENABLE_SCLK_TOPC1, 13, 0, 0), + GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll", + ENABLE_SCLK_TOPC1, 12, 0, 0), + GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll", + ENABLE_SCLK_TOPC1, 5, 0, 0), + GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll", + ENABLE_SCLK_TOPC1, 4, 0, 0), + GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll", + ENABLE_SCLK_TOPC1, 1, 0, 0), + GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll", + ENABLE_SCLK_TOPC1, 0, 0, 0), }; static struct samsung_pll_clock topc_pll_clks[] __initdata = { @@ -195,36 +224,37 @@ CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc", #define DIV_TOP0_PERIC1 0x0634 #define DIV_TOP0_PERIC2 0x0638 #define DIV_TOP0_PERIC3 0x063C +#define ENABLE_ACLK_TOP03 0x080C #define ENABLE_SCLK_TOP0_PERIC0 0x0A30 #define ENABLE_SCLK_TOP0_PERIC1 0x0A34 #define ENABLE_SCLK_TOP0_PERIC2 0x0A38 #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C /* List of parent clocks for Muxes in CMU_TOP0 */ -PNAME(mout_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" }; -PNAME(mout_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll" }; -PNAME(mout_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll" }; -PNAME(mout_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll" }; -PNAME(mout_aud_pll_p) = { "fin_pll", "dout_sclk_aud_pll" }; +PNAME(mout_top0_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_a" }; +PNAME(mout_top0_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_a" }; +PNAME(mout_top0_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_a" }; +PNAME(mout_top0_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_a" }; +PNAME(mout_top0_aud_pll_user_p) = { "fin_pll", "sclk_aud_pll" }; -PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll", +PNAME(mout_top0_bus0_pll_half_p) = {"mout_top0_bus0_pll_user", "ffac_top0_bus0_pll_div2"}; -PNAME(mout_top0_half_bus1_pll_p) = {"mout_top0_bus1_pll", +PNAME(mout_top0_bus1_pll_half_p) = {"mout_top0_bus1_pll_user", "ffac_top0_bus1_pll_div2"}; -PNAME(mout_top0_half_cc_pll_p) = {"mout_top0_cc_pll", +PNAME(mout_top0_cc_pll_half_p) = {"mout_top0_cc_pll_user", "ffac_top0_cc_pll_div2"}; -PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll", +PNAME(mout_top0_mfc_pll_half_p) = {"mout_top0_mfc_pll_user", "ffac_top0_mfc_pll_div2"}; -PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll", - "mout_top0_half_bus1_pll", "mout_top0_half_cc_pll", - "mout_top0_half_mfc_pll"}; +PNAME(mout_top0_group1) = {"mout_top0_bus0_pll_half", + "mout_top0_bus1_pll_half", "mout_top0_cc_pll_half", + "mout_top0_mfc_pll_half"}; PNAME(mout_top0_group3) = {"ioclk_audiocdclk0", "ioclk_audiocdclk1", "ioclk_spdif_extclk", - "mout_top0_aud_pll", "mout_top0_half_bus0_pll", - "mout_top0_half_bus1_pll"}; -PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll", - "mout_top0_half_bus0_pll", "mout_top0_half_bus1_pll"}; + "mout_top0_aud_pll_user", "mout_top0_bus0_pll_half", + "mout_top0_bus1_pll_half"}; +PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll_user", + "mout_top0_bus0_pll_half", "mout_top0_bus1_pll_half"}; static unsigned long top0_clk_regs[] __initdata = { MUX_SEL_TOP00, @@ -246,19 +276,24 @@ static unsigned long top0_clk_regs[] __initdata = { }; static struct samsung_mux_clock top0_mux_clks[] __initdata = { - MUX(0, "mout_top0_aud_pll", mout_aud_pll_p, MUX_SEL_TOP00, 0, 1), - MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1), - MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1), - MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1), - MUX(0, "mout_top0_bus0_pll", mout_bus0_pll_p, MUX_SEL_TOP00, 16, 1), - - MUX(0, "mout_top0_half_mfc_pll", mout_top0_half_mfc_pll_p, + MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p, + MUX_SEL_TOP00, 0, 1), + MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p, + MUX_SEL_TOP00, 4, 1), + MUX(0, "mout_top0_cc_pll_user", mout_top0_cc_pll_user_p, + MUX_SEL_TOP00, 8, 1), + MUX(0, "mout_top0_bus1_pll_user", mout_top0_bus1_pll_user_p, + MUX_SEL_TOP00, 12, 1), + MUX(0, "mout_top0_bus0_pll_user", mout_top0_bus0_pll_user_p, + MUX_SEL_TOP00, 16, 1), + + MUX(0, "mout_top0_mfc_pll_half", mout_top0_mfc_pll_half_p, MUX_SEL_TOP01, 4, 1), - MUX(0, "mout_top0_half_cc_pll", mout_top0_half_cc_pll_p, + MUX(0, "mout_top0_cc_pll_half", mout_top0_cc_pll_half_p, MUX_SEL_TOP01, 8, 1), - MUX(0, "mout_top0_half_bus1_pll", mout_top0_half_bus1_pll_p, + MUX(0, "mout_top0_bus1_pll_half", mout_top0_bus1_pll_half_p, MUX_SEL_TOP01, 12, 1), - MUX(0, "mout_top0_half_bus0_pll", mout_top0_half_bus0_pll_p, + MUX(0, "mout_top0_bus0_pll_half", mout_top0_bus0_pll_half_p, MUX_SEL_TOP01, 16, 1), MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2), @@ -304,6 +339,11 @@ static struct samsung_div_clock top0_div_clks[] __initdata = { }; static struct samsung_gate_clock top0_gate_clks[] __initdata = { + GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66", + ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0), + GATE(CLK_ACLK_PERIC1_66, "aclk_peric1_66", "dout_aclk_peric1_66", + ENABLE_ACLK_TOP03, 12, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif", ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1", @@ -333,10 +373,12 @@ static struct samsung_gate_clock top0_gate_clks[] __initdata = { }; static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = { - FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll", 1, 2, 0), - FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll", 1, 2, 0), - FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll", 1, 2, 0), - FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll", 1, 2, 0), + FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll_user", + 1, 2, 0), + FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll_user", + 1, 2, 0), + FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll_user", 1, 2, 0), + FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0), }; static struct samsung_cmu_info top0_cmu_info __initdata = { @@ -367,31 +409,34 @@ CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0", #define MUX_SEL_TOP13 0x020C #define MUX_SEL_TOP1_FSYS0 0x0224 #define MUX_SEL_TOP1_FSYS1 0x0228 +#define MUX_SEL_TOP1_FSYS11 0x022C #define DIV_TOP13 0x060C #define DIV_TOP1_FSYS0 0x0624 #define DIV_TOP1_FSYS1 0x0628 +#define DIV_TOP1_FSYS11 0x062C #define ENABLE_ACLK_TOP13 0x080C #define ENABLE_SCLK_TOP1_FSYS0 0x0A24 #define ENABLE_SCLK_TOP1_FSYS1 0x0A28 +#define ENABLE_SCLK_TOP1_FSYS11 0x0A2C /* List of parent clocks for Muxes in CMU_TOP1 */ -PNAME(mout_top1_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" }; -PNAME(mout_top1_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll_b" }; -PNAME(mout_top1_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll_b" }; -PNAME(mout_top1_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll_b" }; +PNAME(mout_top1_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_b" }; +PNAME(mout_top1_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_b" }; +PNAME(mout_top1_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_b" }; +PNAME(mout_top1_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_b" }; -PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll", +PNAME(mout_top1_bus0_pll_half_p) = {"mout_top1_bus0_pll_user", "ffac_top1_bus0_pll_div2"}; -PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll", +PNAME(mout_top1_bus1_pll_half_p) = {"mout_top1_bus1_pll_user", "ffac_top1_bus1_pll_div2"}; -PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll", +PNAME(mout_top1_cc_pll_half_p) = {"mout_top1_cc_pll_user", "ffac_top1_cc_pll_div2"}; -PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll", +PNAME(mout_top1_mfc_pll_half_p) = {"mout_top1_mfc_pll_user", "ffac_top1_mfc_pll_div2"}; -PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll", - "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll", - "mout_top1_half_mfc_pll"}; +PNAME(mout_top1_group1) = {"mout_top1_bus0_pll_half", + "mout_top1_bus1_pll_half", "mout_top1_cc_pll_half", + "mout_top1_mfc_pll_half"}; static unsigned long top1_clk_regs[] __initdata = { MUX_SEL_TOP10, @@ -399,40 +444,54 @@ static unsigned long top1_clk_regs[] __initdata = { MUX_SEL_TOP13, MUX_SEL_TOP1_FSYS0, MUX_SEL_TOP1_FSYS1, + MUX_SEL_TOP1_FSYS11, DIV_TOP13, DIV_TOP1_FSYS0, DIV_TOP1_FSYS1, + DIV_TOP1_FSYS11, ENABLE_ACLK_TOP13, ENABLE_SCLK_TOP1_FSYS0, ENABLE_SCLK_TOP1_FSYS1, + ENABLE_SCLK_TOP1_FSYS11, }; static struct samsung_mux_clock top1_mux_clks[] __initdata = { - MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1), - MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1), - MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p, + MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p, + MUX_SEL_TOP10, 4, 1), + MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p, + MUX_SEL_TOP10, 8, 1), + MUX(0, "mout_top1_bus1_pll_user", mout_top1_bus1_pll_user_p, MUX_SEL_TOP10, 12, 1), - MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p, + MUX(0, "mout_top1_bus0_pll_user", mout_top1_bus0_pll_user_p, MUX_SEL_TOP10, 16, 1), - MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p, + MUX(0, "mout_top1_mfc_pll_half", mout_top1_mfc_pll_half_p, MUX_SEL_TOP11, 4, 1), - MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p, + MUX(0, "mout_top1_cc_pll_half", mout_top1_cc_pll_half_p, MUX_SEL_TOP11, 8, 1), - MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p, + MUX(0, "mout_top1_bus1_pll_half", mout_top1_bus1_pll_half_p, MUX_SEL_TOP11, 12, 1), - MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p, + MUX(0, "mout_top1_bus0_pll_half", mout_top1_bus0_pll_half_p, MUX_SEL_TOP11, 16, 1), MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2), MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2), - MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2), + MUX(0, "mout_sclk_phy_fsys0_26m", mout_top1_group1, + MUX_SEL_TOP1_FSYS0, 0, 2), + MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2), MUX(0, "mout_sclk_usbdrd300", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 28, 2), - MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2), - MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2), + MUX(0, "mout_sclk_phy_fsys1", mout_top1_group1, + MUX_SEL_TOP1_FSYS1, 0, 2), + MUX(0, "mout_sclk_ufsunipro20", mout_top1_group1, + MUX_SEL_TOP1_FSYS1, 16, 2), + + MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2), + MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2), + MUX(0, "mout_sclk_phy_fsys1_26m", mout_top1_group1, + MUX_SEL_TOP1_FSYS11, 24, 2), }; static struct samsung_div_clock top1_div_clks[] __initdata = { @@ -441,34 +500,61 @@ static struct samsung_div_clock top1_div_clks[] __initdata = { DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200", DIV_TOP13, 28, 4), + DIV(DOUT_SCLK_PHY_FSYS1, "dout_sclk_phy_fsys1", + "mout_sclk_phy_fsys1", DIV_TOP1_FSYS1, 0, 6), + + DIV(DOUT_SCLK_UFSUNIPRO20, "dout_sclk_ufsunipro20", + "mout_sclk_ufsunipro20", + DIV_TOP1_FSYS1, 16, 6), + DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2", - DIV_TOP1_FSYS0, 24, 4), + DIV_TOP1_FSYS0, 16, 10), DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300", DIV_TOP1_FSYS0, 28, 4), DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1", - DIV_TOP1_FSYS1, 24, 4), + DIV_TOP1_FSYS11, 0, 10), DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0", - DIV_TOP1_FSYS1, 28, 4), + DIV_TOP1_FSYS11, 12, 10), + + DIV(DOUT_SCLK_PHY_FSYS1_26M, "dout_sclk_phy_fsys1_26m", + "mout_sclk_phy_fsys1_26m", DIV_TOP1_FSYS11, 24, 6), }; static struct samsung_gate_clock top1_gate_clks[] __initdata = { GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2", - ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0), + ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0), GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300", ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0), + GATE(CLK_SCLK_PHY_FSYS1, "sclk_phy_fsys1", "dout_sclk_phy_fsys1", + ENABLE_SCLK_TOP1_FSYS1, 0, CLK_SET_RATE_PARENT, 0), + + GATE(CLK_SCLK_UFSUNIPRO20, "sclk_ufsunipro20", "dout_sclk_ufsunipro20", + ENABLE_SCLK_TOP1_FSYS1, 16, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1", - ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0), + ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0", - ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0), + ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0), + + GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200", + ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT, 0), + GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200", + ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0), + + GATE(CLK_SCLK_PHY_FSYS1_26M, "sclk_phy_fsys1_26m", + "dout_sclk_phy_fsys1_26m", ENABLE_SCLK_TOP1_FSYS11, + 24, CLK_SET_RATE_PARENT, 0), }; static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = { - FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0), - FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0), - FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0), - FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0), + FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll_user", + 1, 2, 0), + FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll_user", + 1, 2, 0), + FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll_user", 1, 2, 0), + FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0), }; static struct samsung_cmu_info top1_cmu_info __initdata = { @@ -503,7 +589,7 @@ CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1", /* * List of parent clocks for Muxes in CMU_CCORE */ -PNAME(mout_aclk_ccore_133_p) = { "fin_pll", "dout_aclk_ccore_133" }; +PNAME(mout_aclk_ccore_133_user_p) = { "fin_pll", "aclk_ccore_133" }; static unsigned long ccore_clk_regs[] __initdata = { MUX_SEL_CCORE, @@ -511,7 +597,7 @@ static unsigned long ccore_clk_regs[] __initdata = { }; static struct samsung_mux_clock ccore_mux_clks[] __initdata = { - MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p, + MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p, MUX_SEL_CCORE, 1, 1), }; @@ -544,8 +630,8 @@ CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore", #define ENABLE_SCLK_PERIC0 0x0A00 /* List of parent clocks for Muxes in CMU_PERIC0 */ -PNAME(mout_aclk_peric0_66_p) = { "fin_pll", "dout_aclk_peric0_66" }; -PNAME(mout_sclk_uart0_p) = { "fin_pll", "sclk_uart0" }; +PNAME(mout_aclk_peric0_66_user_p) = { "fin_pll", "aclk_peric0_66" }; +PNAME(mout_sclk_uart0_user_p) = { "fin_pll", "sclk_uart0" }; static unsigned long peric0_clk_regs[] __initdata = { MUX_SEL_PERIC0, @@ -554,9 +640,9 @@ static unsigned long peric0_clk_regs[] __initdata = { }; static struct samsung_mux_clock peric0_mux_clks[] __initdata = { - MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_p, + MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p, MUX_SEL_PERIC0, 0, 1), - MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p, + MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p, MUX_SEL_PERIC0, 16, 1), }; @@ -613,15 +699,15 @@ CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0", exynos7_clk_peric0_init); /* List of parent clocks for Muxes in CMU_PERIC1 */ -PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" }; -PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" }; -PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" }; -PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" }; -PNAME(mout_sclk_spi0_p) = { "fin_pll", "sclk_spi0" }; -PNAME(mout_sclk_spi1_p) = { "fin_pll", "sclk_spi1" }; -PNAME(mout_sclk_spi2_p) = { "fin_pll", "sclk_spi2" }; -PNAME(mout_sclk_spi3_p) = { "fin_pll", "sclk_spi3" }; -PNAME(mout_sclk_spi4_p) = { "fin_pll", "sclk_spi4" }; +PNAME(mout_aclk_peric1_66_user_p) = { "fin_pll", "aclk_peric1_66" }; +PNAME(mout_sclk_uart1_user_p) = { "fin_pll", "sclk_uart1" }; +PNAME(mout_sclk_uart2_user_p) = { "fin_pll", "sclk_uart2" }; +PNAME(mout_sclk_uart3_user_p) = { "fin_pll", "sclk_uart3" }; +PNAME(mout_sclk_spi0_user_p) = { "fin_pll", "sclk_spi0" }; +PNAME(mout_sclk_spi1_user_p) = { "fin_pll", "sclk_spi1" }; +PNAME(mout_sclk_spi2_user_p) = { "fin_pll", "sclk_spi2" }; +PNAME(mout_sclk_spi3_user_p) = { "fin_pll", "sclk_spi3" }; +PNAME(mout_sclk_spi4_user_p) = { "fin_pll", "sclk_spi4" }; static unsigned long peric1_clk_regs[] __initdata = { MUX_SEL_PERIC10, @@ -632,24 +718,24 @@ static unsigned long peric1_clk_regs[] __initdata = { }; static struct samsung_mux_clock peric1_mux_clks[] __initdata = { - MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p, + MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p, MUX_SEL_PERIC10, 0, 1), - MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_p, + MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_user_p, MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0), - MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_p, + MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_user_p, MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0), - MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_p, + MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_user_p, MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0), - MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_p, + MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_user_p, MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0), - MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_p, + MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_user_p, MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0), - MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p, + MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_user_p, MUX_SEL_PERIC11, 20, 1), - MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p, + MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_user_p, MUX_SEL_PERIC11, 24, 1), - MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p, + MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_user_p, MUX_SEL_PERIC11, 28, 1), }; @@ -737,7 +823,7 @@ CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1", #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10 /* List of parent clocks for Muxes in CMU_PERIS */ -PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" }; +PNAME(mout_aclk_peris_66_user_p) = { "fin_pll", "aclk_peris_66" }; static unsigned long peris_clk_regs[] __initdata = { MUX_SEL_PERIS, @@ -749,7 +835,7 @@ static unsigned long peris_clk_regs[] __initdata = { static struct samsung_mux_clock peris_mux_clks[] __initdata = { MUX(0, "mout_aclk_peris_66_user", - mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1), + mout_aclk_peris_66_user_p, MUX_SEL_PERIS, 0, 1), }; static struct samsung_gate_clock peris_gate_clks[] __initdata = { @@ -797,17 +883,17 @@ CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris", /* * List of parent clocks for Muxes in CMU_FSYS0 */ -PNAME(mout_aclk_fsys0_200_p) = { "fin_pll", "dout_aclk_fsys0_200" }; -PNAME(mout_sclk_mmc2_p) = { "fin_pll", "sclk_mmc2" }; +PNAME(mout_aclk_fsys0_200_user_p) = { "fin_pll", "aclk_fsys0_200" }; +PNAME(mout_sclk_mmc2_user_p) = { "fin_pll", "sclk_mmc2" }; -PNAME(mout_sclk_usbdrd300_p) = { "fin_pll", "sclk_usbdrd300" }; -PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_p) = { "fin_pll", +PNAME(mout_sclk_usbdrd300_user_p) = { "fin_pll", "sclk_usbdrd300" }; +PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_user_p) = { "fin_pll", "phyclk_usbdrd300_udrd30_phyclock" }; -PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_p) = { "fin_pll", +PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p) = { "fin_pll", "phyclk_usbdrd300_udrd30_pipe_pclk" }; /* fixed rate clocks used in the FSYS0 block */ -struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = { +static struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = { FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, CLK_IS_ROOT, 60000000), FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, @@ -826,29 +912,30 @@ static unsigned long fsys0_clk_regs[] __initdata = { }; static struct samsung_mux_clock fsys0_mux_clks[] __initdata = { - MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p, + MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p, MUX_SEL_FSYS00, 24, 1), - MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1), - MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_p, + MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_user_p, + MUX_SEL_FSYS01, 24, 1), + MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_user_p, MUX_SEL_FSYS01, 28, 1), MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user", - mout_phyclk_usbdrd300_udrd30_pipe_pclk_p, + mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p, MUX_SEL_FSYS02, 24, 1), MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user", - mout_phyclk_usbdrd300_udrd30_phyclk_p, + mout_phyclk_usbdrd300_udrd30_phyclk_user_p, MUX_SEL_FSYS02, 28, 1), }; static struct samsung_gate_clock fsys0_gate_clks[] __initdata = { - GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x", - "mout_aclk_fsys0_200_user", - ENABLE_ACLK_FSYS00, 19, 0, 0), GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user", ENABLE_ACLK_FSYS00, 3, 0, 0), GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user", ENABLE_ACLK_FSYS00, 4, 0, 0), + GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x", + "mout_aclk_fsys0_200_user", + ENABLE_ACLK_FSYS00, 19, 0, 0), GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user", ENABLE_ACLK_FSYS01, 29, 0, 0), @@ -876,11 +963,13 @@ static struct samsung_gate_clock fsys0_gate_clks[] __initdata = { }; static struct samsung_cmu_info fsys0_cmu_info __initdata = { + .fixed_clks = fixed_rate_clks_fsys0, + .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys0), .mux_clks = fsys0_mux_clks, .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), .gate_clks = fsys0_gate_clks, .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), - .nr_clk_ids = TOP1_NR_CLK, + .nr_clk_ids = FSYS0_NR_CLK, .clk_regs = fsys0_clk_regs, .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), }; @@ -896,42 +985,122 @@ CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0", /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */ #define MUX_SEL_FSYS10 0x0200 #define MUX_SEL_FSYS11 0x0204 +#define MUX_SEL_FSYS12 0x0208 +#define DIV_FSYS1 0x0600 #define ENABLE_ACLK_FSYS1 0x0800 +#define ENABLE_PCLK_FSYS1 0x0900 +#define ENABLE_SCLK_FSYS11 0x0A04 +#define ENABLE_SCLK_FSYS12 0x0A08 +#define ENABLE_SCLK_FSYS13 0x0A0C /* * List of parent clocks for Muxes in CMU_FSYS1 */ -PNAME(mout_aclk_fsys1_200_p) = { "fin_pll", "dout_aclk_fsys1_200" }; -PNAME(mout_sclk_mmc0_p) = { "fin_pll", "sclk_mmc0" }; -PNAME(mout_sclk_mmc1_p) = { "fin_pll", "sclk_mmc1" }; +PNAME(mout_aclk_fsys1_200_user_p) = { "fin_pll", "aclk_fsys1_200" }; +PNAME(mout_fsys1_group_p) = { "fin_pll", "fin_pll_26m", + "sclk_phy_fsys1_26m" }; +PNAME(mout_sclk_mmc0_user_p) = { "fin_pll", "sclk_mmc0" }; +PNAME(mout_sclk_mmc1_user_p) = { "fin_pll", "sclk_mmc1" }; +PNAME(mout_sclk_ufsunipro20_user_p) = { "fin_pll", "sclk_ufsunipro20" }; +PNAME(mout_phyclk_ufs20_tx0_user_p) = { "fin_pll", "phyclk_ufs20_tx0_symbol" }; +PNAME(mout_phyclk_ufs20_rx0_user_p) = { "fin_pll", "phyclk_ufs20_rx0_symbol" }; +PNAME(mout_phyclk_ufs20_rx1_user_p) = { "fin_pll", "phyclk_ufs20_rx1_symbol" }; + +/* fixed rate clocks used in the FSYS1 block */ +static struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initdata = { + FRATE(PHYCLK_UFS20_TX0_SYMBOL, "phyclk_ufs20_tx0_symbol", NULL, + CLK_IS_ROOT, 300000000), + FRATE(PHYCLK_UFS20_RX0_SYMBOL, "phyclk_ufs20_rx0_symbol", NULL, + CLK_IS_ROOT, 300000000), + FRATE(PHYCLK_UFS20_RX1_SYMBOL, "phyclk_ufs20_rx1_symbol", NULL, + CLK_IS_ROOT, 300000000), +}; static unsigned long fsys1_clk_regs[] __initdata = { MUX_SEL_FSYS10, MUX_SEL_FSYS11, + MUX_SEL_FSYS12, + DIV_FSYS1, ENABLE_ACLK_FSYS1, + ENABLE_PCLK_FSYS1, + ENABLE_SCLK_FSYS11, + ENABLE_SCLK_FSYS12, + ENABLE_SCLK_FSYS13, }; static struct samsung_mux_clock fsys1_mux_clks[] __initdata = { - MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p, + MUX(MOUT_FSYS1_PHYCLK_SEL1, "mout_fsys1_phyclk_sel1", + mout_fsys1_group_p, MUX_SEL_FSYS10, 16, 2), + MUX(0, "mout_fsys1_phyclk_sel0", mout_fsys1_group_p, + MUX_SEL_FSYS10, 20, 2), + MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_user_p, MUX_SEL_FSYS10, 28, 1), - MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1), - MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1), + MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_user_p, + MUX_SEL_FSYS11, 24, 1), + MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_user_p, + MUX_SEL_FSYS11, 28, 1), + MUX(0, "mout_sclk_ufsunipro20_user", mout_sclk_ufsunipro20_user_p, + MUX_SEL_FSYS11, 20, 1), + + MUX(0, "mout_phyclk_ufs20_rx1_symbol_user", + mout_phyclk_ufs20_rx1_user_p, MUX_SEL_FSYS12, 16, 1), + MUX(0, "mout_phyclk_ufs20_rx0_symbol_user", + mout_phyclk_ufs20_rx0_user_p, MUX_SEL_FSYS12, 24, 1), + MUX(0, "mout_phyclk_ufs20_tx0_symbol_user", + mout_phyclk_ufs20_tx0_user_p, MUX_SEL_FSYS12, 28, 1), +}; + +static struct samsung_div_clock fsys1_div_clks[] __initdata = { + DIV(DOUT_PCLK_FSYS1, "dout_pclk_fsys1", "mout_aclk_fsys1_200_user", + DIV_FSYS1, 0, 2), }; static struct samsung_gate_clock fsys1_gate_clks[] __initdata = { + GATE(SCLK_UFSUNIPRO20_USER, "sclk_ufsunipro20_user", + "mout_sclk_ufsunipro20_user", + ENABLE_SCLK_FSYS11, 20, 0, 0), + GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user", ENABLE_ACLK_FSYS1, 29, 0, 0), GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user", ENABLE_ACLK_FSYS1, 30, 0, 0), + + GATE(ACLK_UFS20_LINK, "aclk_ufs20_link", "dout_pclk_fsys1", + ENABLE_ACLK_FSYS1, 31, 0, 0), + GATE(PCLK_GPIO_FSYS1, "pclk_gpio_fsys1", "mout_aclk_fsys1_200_user", + ENABLE_PCLK_FSYS1, 30, 0, 0), + + GATE(PHYCLK_UFS20_RX1_SYMBOL_USER, "phyclk_ufs20_rx1_symbol_user", + "mout_phyclk_ufs20_rx1_symbol_user", + ENABLE_SCLK_FSYS12, 16, 0, 0), + GATE(PHYCLK_UFS20_RX0_SYMBOL_USER, "phyclk_ufs20_rx0_symbol_user", + "mout_phyclk_ufs20_rx0_symbol_user", + ENABLE_SCLK_FSYS12, 24, 0, 0), + GATE(PHYCLK_UFS20_TX0_SYMBOL_USER, "phyclk_ufs20_tx0_symbol_user", + "mout_phyclk_ufs20_tx0_symbol_user", + ENABLE_SCLK_FSYS12, 28, 0, 0), + + GATE(OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY, + "oscclk_phy_clkout_embedded_combo_phy", + "fin_pll", + ENABLE_SCLK_FSYS12, 4, CLK_IGNORE_UNUSED, 0), + + GATE(SCLK_COMBO_PHY_EMBEDDED_26M, "sclk_combo_phy_embedded_26m", + "mout_fsys1_phyclk_sel1", + ENABLE_SCLK_FSYS13, 24, CLK_IGNORE_UNUSED, 0), }; static struct samsung_cmu_info fsys1_cmu_info __initdata = { + .fixed_clks = fixed_rate_clks_fsys1, + .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys1), .mux_clks = fsys1_mux_clks, .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks), + .div_clks = fsys1_div_clks, + .nr_div_clks = ARRAY_SIZE(fsys1_div_clks), .gate_clks = fsys1_gate_clks, .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), - .nr_clk_ids = TOP1_NR_CLK, + .nr_clk_ids = FSYS1_NR_CLK, .clk_regs = fsys1_clk_regs, .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), }; diff --git a/kernel/drivers/clk/samsung/clk-pll.c b/kernel/drivers/clk/samsung/clk-pll.c index 9d70e5c03..b7dd39610 100644 --- a/kernel/drivers/clk/samsung/clk-pll.c +++ b/kernel/drivers/clk/samsung/clk-pll.c @@ -12,6 +12,8 @@ #include <linux/errno.h> #include <linux/hrtimer.h> #include <linux/delay.h> +#include <linux/slab.h> +#include <linux/clkdev.h> #include "clk.h" #include "clk-pll.h" @@ -180,7 +182,7 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, rate = samsung_get_pll_settings(pll, drate); if (!rate) { pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, - drate, __clk_get_name(hw->clk)); + drate, clk_hw_get_name(hw)); return -EINVAL; } @@ -288,7 +290,7 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, rate = samsung_get_pll_settings(pll, drate); if (!rate) { pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, - drate, __clk_get_name(hw->clk)); + drate, clk_hw_get_name(hw)); return -EINVAL; } @@ -403,7 +405,7 @@ static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate, rate = samsung_get_pll_settings(pll, drate); if (!rate) { pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, - drate, __clk_get_name(hw->clk)); + drate, clk_hw_get_name(hw)); return -EINVAL; } @@ -455,7 +457,7 @@ static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate, if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) { pr_err("%s: could not lock PLL %s\n", - __func__, __clk_get_name(hw->clk)); + __func__, clk_hw_get_name(hw)); return -EFAULT; } @@ -554,7 +556,7 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, rate = samsung_get_pll_settings(pll, drate); if (!rate) { pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, - drate, __clk_get_name(hw->clk)); + drate, clk_hw_get_name(hw)); return -EINVAL; } @@ -614,7 +616,7 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) { pr_err("%s: could not lock PLL %s\n", - __func__, __clk_get_name(hw->clk)); + __func__, clk_hw_get_name(hw)); return -EFAULT; } @@ -772,7 +774,7 @@ static int samsung_s3c2410_pll_set_rate(struct clk_hw *hw, unsigned long drate, rate = samsung_get_pll_settings(pll, drate); if (!rate) { pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, - drate, __clk_get_name(hw->clk)); + drate, clk_hw_get_name(hw)); return -EINVAL; } @@ -1013,7 +1015,7 @@ static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, rate = samsung_get_pll_settings(pll, drate); if (!rate) { pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, - drate, __clk_get_name(hw->clk)); + drate, clk_hw_get_name(hw)); return -EINVAL; } @@ -1111,7 +1113,7 @@ static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate, rate = samsung_get_pll_settings(pll, drate); if (!rate) { pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, - drate, __clk_get_name(hw->clk)); + drate, clk_hw_get_name(hw)); return -EINVAL; } @@ -1156,7 +1158,7 @@ static const struct clk_ops samsung_pll2650xx_clk_min_ops = { }; static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, - struct samsung_pll_clock *pll_clk, + const struct samsung_pll_clock *pll_clk, void __iomem *base) { struct samsung_clk_pll *pll; @@ -1303,7 +1305,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, } void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, - struct samsung_pll_clock *pll_list, + const struct samsung_pll_clock *pll_list, unsigned int nr_pll, void __iomem *base) { int cnt; diff --git a/kernel/drivers/clk/samsung/clk-s3c2410-dclk.c b/kernel/drivers/clk/samsung/clk-s3c2410-dclk.c index f4f29ed6b..e9eb935d7 100644 --- a/kernel/drivers/clk/samsung/clk-s3c2410-dclk.c +++ b/kernel/drivers/clk/samsung/clk-s3c2410-dclk.c @@ -8,6 +8,10 @@ * Common Clock Framework support for s3c24xx external clock output. */ +#include <linux/clkdev.h> +#include <linux/slab.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/platform_device.h> #include <linux/module.h> #include "clk.h" @@ -57,7 +61,7 @@ struct s3c24xx_clkout { static u8 s3c24xx_clkout_get_parent(struct clk_hw *hw) { struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw); - int num_parents = __clk_get_num_parents(hw->clk); + int num_parents = clk_hw_get_num_parents(hw); u32 val; val = readl_relaxed(S3C24XX_MISCCR) >> clkout->shift; @@ -81,13 +85,13 @@ static int s3c24xx_clkout_set_parent(struct clk_hw *hw, u8 index) return ret; } -const struct clk_ops s3c24xx_clkout_ops = { +static const struct clk_ops s3c24xx_clkout_ops = { .get_parent = s3c24xx_clkout_get_parent, .set_parent = s3c24xx_clkout_set_parent, .determine_rate = __clk_mux_determine_rate, }; -struct clk *s3c24xx_register_clkout(struct device *dev, const char *name, +static struct clk *s3c24xx_register_clkout(struct device *dev, const char *name, const char **parent_names, u8 num_parents, u8 shift, u32 mask) { @@ -404,7 +408,7 @@ static struct s3c24xx_dclk_drv_data dclk_variants[] = { }, }; -static struct platform_device_id s3c24xx_dclk_driver_ids[] = { +static const struct platform_device_id s3c24xx_dclk_driver_ids[] = { { .name = "s3c2410-dclk", .driver_data = (kernel_ulong_t)&dclk_variants[S3C2410], diff --git a/kernel/drivers/clk/samsung/clk-s3c2410.c b/kernel/drivers/clk/samsung/clk-s3c2410.c index 5d2f03461..0945a8852 100644 --- a/kernel/drivers/clk/samsung/clk-s3c2410.c +++ b/kernel/drivers/clk/samsung/clk-s3c2410.c @@ -8,8 +8,6 @@ * Common Clock Framework support for S3C2410 and following SoCs. */ -#include <linux/clk.h> -#include <linux/clkdev.h> #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> diff --git a/kernel/drivers/clk/samsung/clk-s3c2412.c b/kernel/drivers/clk/samsung/clk-s3c2412.c index 2ceedaf8c..44d6a9f4f 100644 --- a/kernel/drivers/clk/samsung/clk-s3c2412.c +++ b/kernel/drivers/clk/samsung/clk-s3c2412.c @@ -8,8 +8,6 @@ * Common Clock Framework support for S3C2412 and S3C2413. */ -#include <linux/clk.h> -#include <linux/clkdev.h> #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> diff --git a/kernel/drivers/clk/samsung/clk-s3c2443.c b/kernel/drivers/clk/samsung/clk-s3c2443.c index 0c3c182b9..2c0a1ea3c 100644 --- a/kernel/drivers/clk/samsung/clk-s3c2443.c +++ b/kernel/drivers/clk/samsung/clk-s3c2443.c @@ -8,8 +8,6 @@ * Common Clock Framework support for S3C2443 and following SoCs. */ -#include <linux/clk.h> -#include <linux/clkdev.h> #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> diff --git a/kernel/drivers/clk/samsung/clk-s3c64xx.c b/kernel/drivers/clk/samsung/clk-s3c64xx.c index 0f590e555..d325ed1e1 100644 --- a/kernel/drivers/clk/samsung/clk-s3c64xx.c +++ b/kernel/drivers/clk/samsung/clk-s3c64xx.c @@ -8,8 +8,7 @@ * Common Clock Framework support for all S3C64xx SoCs. */ -#include <linux/clk.h> -#include <linux/clkdev.h> +#include <linux/slab.h> #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> diff --git a/kernel/drivers/clk/samsung/clk-s5pv210-audss.c b/kernel/drivers/clk/samsung/clk-s5pv210-audss.c index de4455b75..eefb84b22 100644 --- a/kernel/drivers/clk/samsung/clk-s5pv210-audss.c +++ b/kernel/drivers/clk/samsung/clk-s5pv210-audss.c @@ -13,8 +13,8 @@ * Driver for Audio Subsystem Clock Controller of S5PV210-compatible SoCs. */ -#include <linux/clkdev.h> #include <linux/io.h> +#include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/of_address.h> #include <linux/syscore_ops.h> diff --git a/kernel/drivers/clk/samsung/clk-s5pv210.c b/kernel/drivers/clk/samsung/clk-s5pv210.c index bdd284249..759aaf342 100644 --- a/kernel/drivers/clk/samsung/clk-s5pv210.c +++ b/kernel/drivers/clk/samsung/clk-s5pv210.c @@ -11,8 +11,6 @@ * Common Clock Framework support for all S5PC110/S5PV210 SoCs. */ -#include <linux/clk.h> -#include <linux/clkdev.h> #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> @@ -169,44 +167,44 @@ static inline void s5pv210_clk_sleep_init(void) { } #endif /* Mux parent lists. */ -static const char *fin_pll_p[] __initdata = { +static const char *const fin_pll_p[] __initconst = { "xxti", "xusbxti" }; -static const char *mout_apll_p[] __initdata = { +static const char *const mout_apll_p[] __initconst = { "fin_pll", "fout_apll" }; -static const char *mout_mpll_p[] __initdata = { +static const char *const mout_mpll_p[] __initconst = { "fin_pll", "fout_mpll" }; -static const char *mout_epll_p[] __initdata = { +static const char *const mout_epll_p[] __initconst = { "fin_pll", "fout_epll" }; -static const char *mout_vpllsrc_p[] __initdata = { +static const char *const mout_vpllsrc_p[] __initconst = { "fin_pll", "sclk_hdmi27m" }; -static const char *mout_vpll_p[] __initdata = { +static const char *const mout_vpll_p[] __initconst = { "mout_vpllsrc", "fout_vpll" }; -static const char *mout_group1_p[] __initdata = { +static const char *const mout_group1_p[] __initconst = { "dout_a2m", "mout_mpll", "mout_epll", "mout_vpll" }; -static const char *mout_group2_p[] __initdata = { +static const char *const mout_group2_p[] __initconst = { "xxti", "xusbxti", "sclk_hdmi27m", @@ -218,7 +216,7 @@ static const char *mout_group2_p[] __initdata = { "mout_vpll", }; -static const char *mout_audio0_p[] __initdata = { +static const char *const mout_audio0_p[] __initconst = { "xxti", "pcmcdclk0", "sclk_hdmi27m", @@ -230,7 +228,7 @@ static const char *mout_audio0_p[] __initdata = { "mout_vpll", }; -static const char *mout_audio1_p[] __initdata = { +static const char *const mout_audio1_p[] __initconst = { "i2scdclk1", "pcmcdclk1", "sclk_hdmi27m", @@ -242,7 +240,7 @@ static const char *mout_audio1_p[] __initdata = { "mout_vpll", }; -static const char *mout_audio2_p[] __initdata = { +static const char *const mout_audio2_p[] __initconst = { "i2scdclk2", "pcmcdclk2", "sclk_hdmi27m", @@ -254,63 +252,63 @@ static const char *mout_audio2_p[] __initdata = { "mout_vpll", }; -static const char *mout_spdif_p[] __initdata = { +static const char *const mout_spdif_p[] __initconst = { "dout_audio0", "dout_audio1", "dout_audio3", }; -static const char *mout_group3_p[] __initdata = { +static const char *const mout_group3_p[] __initconst = { "mout_apll", "mout_mpll" }; -static const char *mout_group4_p[] __initdata = { +static const char *const mout_group4_p[] __initconst = { "mout_mpll", "dout_a2m" }; -static const char *mout_flash_p[] __initdata = { +static const char *const mout_flash_p[] __initconst = { "dout_hclkd", "dout_hclkp" }; -static const char *mout_dac_p[] __initdata = { +static const char *const mout_dac_p[] __initconst = { "mout_vpll", "sclk_hdmiphy" }; -static const char *mout_hdmi_p[] __initdata = { +static const char *const mout_hdmi_p[] __initconst = { "sclk_hdmiphy", "dout_tblk" }; -static const char *mout_mixer_p[] __initdata = { +static const char *const mout_mixer_p[] __initconst = { "mout_dac", "mout_hdmi" }; -static const char *mout_vpll_6442_p[] __initdata = { +static const char *const mout_vpll_6442_p[] __initconst = { "fin_pll", "fout_vpll" }; -static const char *mout_mixer_6442_p[] __initdata = { +static const char *const mout_mixer_6442_p[] __initconst = { "mout_vpll", "dout_mixer" }; -static const char *mout_d0sync_6442_p[] __initdata = { +static const char *const mout_d0sync_6442_p[] __initconst = { "mout_dsys", "div_apll" }; -static const char *mout_d1sync_6442_p[] __initdata = { +static const char *const mout_d1sync_6442_p[] __initconst = { "mout_psys", "div_apll" }; -static const char *mout_group2_6442_p[] __initdata = { +static const char *const mout_group2_6442_p[] __initconst = { "fin_pll", "none", "none", @@ -322,7 +320,7 @@ static const char *mout_group2_6442_p[] __initdata = { "mout_vpll", }; -static const char *mout_audio0_6442_p[] __initdata = { +static const char *const mout_audio0_6442_p[] __initconst = { "fin_pll", "pcmcdclk0", "none", @@ -334,7 +332,7 @@ static const char *mout_audio0_6442_p[] __initdata = { "mout_vpll", }; -static const char *mout_audio1_6442_p[] __initdata = { +static const char *const mout_audio1_6442_p[] __initconst = { "i2scdclk1", "pcmcdclk1", "none", @@ -347,7 +345,7 @@ static const char *mout_audio1_6442_p[] __initdata = { "fin_pll", }; -static const char *mout_clksel_p[] __initdata = { +static const char *const mout_clksel_p[] __initconst = { "fout_apll_clkout", "fout_mpll_clkout", "fout_epll", @@ -370,7 +368,7 @@ static const char *mout_clksel_p[] __initdata = { "div_dclk" }; -static const char *mout_clksel_6442_p[] __initdata = { +static const char *const mout_clksel_6442_p[] __initconst = { "fout_apll_clkout", "fout_mpll_clkout", "fout_epll", @@ -393,7 +391,7 @@ static const char *mout_clksel_6442_p[] __initdata = { "div_dclk" }; -static const char *mout_clkout_p[] __initdata = { +static const char *const mout_clkout_p[] __initconst = { "dout_clkout", "none", "xxti", @@ -401,20 +399,20 @@ static const char *mout_clkout_p[] __initdata = { }; /* Common fixed factor clocks. */ -static struct samsung_fixed_factor_clock ffactor_clks[] __initdata = { +static const struct samsung_fixed_factor_clock ffactor_clks[] __initconst = { FFACTOR(FOUT_APLL_CLKOUT, "fout_apll_clkout", "fout_apll", 1, 4, 0), FFACTOR(FOUT_MPLL_CLKOUT, "fout_mpll_clkout", "fout_mpll", 1, 2, 0), FFACTOR(DOUT_APLL_CLKOUT, "dout_apll_clkout", "dout_apll", 1, 4, 0), }; /* PLL input mux (fin_pll), which needs to be registered before PLLs. */ -static struct samsung_mux_clock early_mux_clks[] __initdata = { +static const struct samsung_mux_clock early_mux_clks[] __initconst = { MUX_F(FIN_PLL, "fin_pll", fin_pll_p, OM_STAT, 0, 1, CLK_MUX_READ_ONLY, 0), }; /* Common clock muxes. */ -static struct samsung_mux_clock mux_clks[] __initdata = { +static const struct samsung_mux_clock mux_clks[] __initconst = { MUX(MOUT_FLASH, "mout_flash", mout_flash_p, CLK_SRC0, 28, 1), MUX(MOUT_PSYS, "mout_psys", mout_group4_p, CLK_SRC0, 24, 1), MUX(MOUT_DSYS, "mout_dsys", mout_group4_p, CLK_SRC0, 20, 1), @@ -427,7 +425,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = { }; /* S5PV210-specific clock muxes. */ -static struct samsung_mux_clock s5pv210_mux_clks[] __initdata = { +static const struct samsung_mux_clock s5pv210_mux_clks[] __initconst = { MUX(MOUT_VPLL, "mout_vpll", mout_vpll_p, CLK_SRC0, 12, 1), MUX(MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, CLK_SRC1, 28, 1), @@ -472,7 +470,7 @@ static struct samsung_mux_clock s5pv210_mux_clks[] __initdata = { }; /* S5P6442-specific clock muxes. */ -static struct samsung_mux_clock s5p6442_mux_clks[] __initdata = { +static const struct samsung_mux_clock s5p6442_mux_clks[] __initconst = { MUX(MOUT_VPLL, "mout_vpll", mout_vpll_6442_p, CLK_SRC0, 12, 1), MUX(MOUT_FIMD, "mout_fimd", mout_group2_6442_p, CLK_SRC1, 20, 4), @@ -504,7 +502,7 @@ static struct samsung_mux_clock s5p6442_mux_clks[] __initdata = { }; /* S5PV210-specific fixed rate clocks generated inside the SoC. */ -static struct samsung_fixed_rate_clock s5pv210_frate_clks[] __initdata = { +static const struct samsung_fixed_rate_clock s5pv210_frate_clks[] __initconst = { FRATE(SCLK_HDMI27M, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000), FRATE(SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), @@ -512,12 +510,12 @@ static struct samsung_fixed_rate_clock s5pv210_frate_clks[] __initdata = { }; /* S5P6442-specific fixed rate clocks generated inside the SoC. */ -static struct samsung_fixed_rate_clock s5p6442_frate_clks[] __initdata = { +static const struct samsung_fixed_rate_clock s5p6442_frate_clks[] __initconst = { FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 30000000), }; /* Common clock dividers. */ -static struct samsung_div_clock div_clks[] __initdata = { +static const struct samsung_div_clock div_clks[] __initconst = { DIV(DOUT_PCLKP, "dout_pclkp", "dout_hclkp", CLK_DIV0, 28, 3), DIV(DOUT_PCLKD, "dout_pclkd", "dout_hclkd", CLK_DIV0, 20, 3), DIV(DOUT_A2M, "dout_a2m", "mout_apll", CLK_DIV0, 4, 3), @@ -549,7 +547,7 @@ static struct samsung_div_clock div_clks[] __initdata = { }; /* S5PV210-specific clock dividers. */ -static struct samsung_div_clock s5pv210_div_clks[] __initdata = { +static const struct samsung_div_clock s5pv210_div_clks[] __initconst = { DIV(DOUT_HCLKP, "dout_hclkp", "mout_psys", CLK_DIV0, 24, 4), DIV(DOUT_HCLKD, "dout_hclkd", "mout_dsys", CLK_DIV0, 16, 4), DIV(DOUT_PCLKM, "dout_pclkm", "dout_hclkm", CLK_DIV0, 12, 3), @@ -578,7 +576,7 @@ static struct samsung_div_clock s5pv210_div_clks[] __initdata = { }; /* S5P6442-specific clock dividers. */ -static struct samsung_div_clock s5p6442_div_clks[] __initdata = { +static const struct samsung_div_clock s5p6442_div_clks[] __initconst = { DIV(DOUT_HCLKP, "dout_hclkp", "mout_d1sync", CLK_DIV0, 24, 4), DIV(DOUT_HCLKD, "dout_hclkd", "mout_d0sync", CLK_DIV0, 16, 4), @@ -586,7 +584,7 @@ static struct samsung_div_clock s5p6442_div_clks[] __initdata = { }; /* Common clock gates. */ -static struct samsung_gate_clock gate_clks[] __initdata = { +static const struct samsung_gate_clock gate_clks[] __initconst = { GATE(CLK_ROTATOR, "rotator", "dout_hclkd", CLK_GATE_IP0, 29, 0, 0), GATE(CLK_FIMC2, "fimc2", "dout_hclkd", CLK_GATE_IP0, 26, 0, 0), GATE(CLK_FIMC1, "fimc1", "dout_hclkd", CLK_GATE_IP0, 25, 0, 0), @@ -666,7 +664,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = { }; /* S5PV210-specific clock gates. */ -static struct samsung_gate_clock s5pv210_gate_clks[] __initdata = { +static const struct samsung_gate_clock s5pv210_gate_clks[] __initconst = { GATE(CLK_CSIS, "clk_csis", "dout_hclkd", CLK_GATE_IP0, 31, 0, 0), GATE(CLK_MFC, "mfc", "dout_hclkm", CLK_GATE_IP0, 16, 0, 0), GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0), @@ -728,7 +726,7 @@ static struct samsung_gate_clock s5pv210_gate_clks[] __initdata = { }; /* S5P6442-specific clock gates. */ -static struct samsung_gate_clock s5p6442_gate_clks[] __initdata = { +static const struct samsung_gate_clock s5p6442_gate_clks[] __initconst = { GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP0, 28, 0, 0), GATE(CLK_MFC, "mfc", "dout_hclkd", CLK_GATE_IP0, 16, 0, 0), GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0), @@ -748,14 +746,14 @@ static struct samsung_gate_clock s5p6442_gate_clks[] __initdata = { * Clock aliases for legacy clkdev look-up. * NOTE: Needed only to support legacy board files. */ -static struct samsung_clock_alias s5pv210_aliases[] = { +static const struct samsung_clock_alias s5pv210_aliases[] __initconst = { ALIAS(DOUT_APLL, NULL, "armclk"), ALIAS(DOUT_HCLKM, NULL, "hclk_msys"), ALIAS(MOUT_DMC0, NULL, "sclk_dmc0"), }; /* S5PV210-specific PLLs. */ -static struct samsung_pll_clock s5pv210_pll_clks[] __initdata = { +static const struct samsung_pll_clock s5pv210_pll_clks[] __initconst = { [apll] = PLL(pll_4508, FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, NULL), [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll", @@ -767,7 +765,7 @@ static struct samsung_pll_clock s5pv210_pll_clks[] __initdata = { }; /* S5P6442-specific PLLs. */ -static struct samsung_pll_clock s5p6442_pll_clks[] __initdata = { +static const struct samsung_pll_clock s5p6442_pll_clks[] __initconst = { [apll] = PLL(pll_4502, FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, NULL), [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll", diff --git a/kernel/drivers/clk/samsung/clk.c b/kernel/drivers/clk/samsung/clk.c index 9e1f88c04..f38a6c49f 100644 --- a/kernel/drivers/clk/samsung/clk.c +++ b/kernel/drivers/clk/samsung/clk.c @@ -11,6 +11,10 @@ * clock framework for Samsung platforms. */ +#include <linux/slab.h> +#include <linux/clkdev.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> #include <linux/of_address.h> #include <linux/syscore_ops.h> @@ -98,7 +102,7 @@ void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk, /* register a list of aliases */ void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx, - struct samsung_clock_alias *list, + const struct samsung_clock_alias *list, unsigned int nr_clk) { struct clk *clk; @@ -132,7 +136,8 @@ void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx, /* register a list of fixed clocks */ void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx, - struct samsung_fixed_rate_clock *list, unsigned int nr_clk) + const struct samsung_fixed_rate_clock *list, + unsigned int nr_clk) { struct clk *clk; unsigned int idx, ret; @@ -161,7 +166,7 @@ void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx, /* register a list of fixed factor clocks */ void __init samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx, - struct samsung_fixed_factor_clock *list, unsigned int nr_clk) + const struct samsung_fixed_factor_clock *list, unsigned int nr_clk) { struct clk *clk; unsigned int idx; @@ -181,7 +186,7 @@ void __init samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx, /* register a list of mux clocks */ void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, - struct samsung_mux_clock *list, + const struct samsung_mux_clock *list, unsigned int nr_clk) { struct clk *clk; @@ -213,7 +218,7 @@ void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, /* register a list of div clocks */ void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, - struct samsung_div_clock *list, + const struct samsung_div_clock *list, unsigned int nr_clk) { struct clk *clk; @@ -252,7 +257,7 @@ void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, /* register a list of gate clocks */ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, - struct samsung_gate_clock *list, + const struct samsung_gate_clock *list, unsigned int nr_clk) { struct clk *clk; @@ -389,7 +394,7 @@ struct samsung_clk_provider * __init samsung_cmu_register_one( ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids); if (!ctx) { - panic("%s: unable to alllocate ctx\n", __func__); + panic("%s: unable to allocate ctx\n", __func__); return ctx; } diff --git a/kernel/drivers/clk/samsung/clk.h b/kernel/drivers/clk/samsung/clk.h index e4c75383c..aa872d2c5 100644 --- a/kernel/drivers/clk/samsung/clk.h +++ b/kernel/drivers/clk/samsung/clk.h @@ -13,10 +13,11 @@ #ifndef __SAMSUNG_CLK_H #define __SAMSUNG_CLK_H -#include <linux/clkdev.h> #include <linux/clk-provider.h> #include "clk-pll.h" +struct clk; + /** * struct samsung_clk_provider: information about clock provider * @reg_base: virtual address for the register base. @@ -121,7 +122,7 @@ struct samsung_mux_clock { unsigned int id; const char *dev_name; const char *name; - const char **parent_names; + const char *const *parent_names; u8 num_parents; unsigned long flags; unsigned long offset; @@ -368,28 +369,28 @@ extern void __init samsung_clk_of_register_fixed_ext( extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk, unsigned int id); -extern void samsung_clk_register_alias(struct samsung_clk_provider *ctx, - struct samsung_clock_alias *list, +extern void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx, + const struct samsung_clock_alias *list, unsigned int nr_clk); extern void __init samsung_clk_register_fixed_rate( struct samsung_clk_provider *ctx, - struct samsung_fixed_rate_clock *clk_list, + const struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk); extern void __init samsung_clk_register_fixed_factor( struct samsung_clk_provider *ctx, - struct samsung_fixed_factor_clock *list, + const struct samsung_fixed_factor_clock *list, unsigned int nr_clk); extern void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx, - struct samsung_mux_clock *clk_list, + const struct samsung_mux_clock *clk_list, unsigned int nr_clk); extern void __init samsung_clk_register_div(struct samsung_clk_provider *ctx, - struct samsung_div_clock *clk_list, + const struct samsung_div_clock *clk_list, unsigned int nr_clk); extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx, - struct samsung_gate_clock *clk_list, + const struct samsung_gate_clock *clk_list, unsigned int nr_clk); extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, - struct samsung_pll_clock *pll_list, + const struct samsung_pll_clock *pll_list, unsigned int nr_clk, void __iomem *base); extern struct samsung_clk_provider __init *samsung_cmu_register_one( |