3 files changed, 26 insertions, 3 deletions

diff --git a/kernel/arch/mips/pistachio/Kconfig b/kernel/arch/mips/pistachio/Kconfig
new file mode 100644
index 000000000..97731ea94
--- /dev/null
+++ b/kernel/arch/mips/pistachio/Kconfig
@@ -0,0 +1,13 @@
+config PISTACHIO_GPTIMER_CLKSRC
+	bool "Enable General Purpose Timer based clocksource"
+	depends on MACH_PISTACHIO
+	select CLKSRC_PISTACHIO
+	select MIPS_EXTERNAL_TIMER
+	help
+	  This option enables a clocksource driver based on a Pistachio
+	  SoC General Purpose external timer.
+
+	  If you want to enable the CPUFreq, you need to enable
+	  this option.
+
+	  If you don't want to enable CPUFreq, you can leave this disabled.
diff --git a/kernel/arch/mips/pistachio/init.c b/kernel/arch/mips/pistachio/init.c
index d2dc83652..96ba2cc9a 100644
--- a/kernel/arch/mips/pistachio/init.c
+++ b/kernel/arch/mips/pistachio/init.c
@@ -58,18 +58,23 @@ void __init plat_mem_setup(void)
 		panic("Device-tree not present");
 
 	__dt_setup_arch((void *)fw_arg1);
-	strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
 
 	plat_setup_iocoherency();
 }
 
-#define DEFAULT_CPC_BASE_ADDR 0x1bde0000
+#define DEFAULT_CPC_BASE_ADDR	0x1bde0000
+#define DEFAULT_CDMM_BASE_ADDR	0x1bdd0000
 
 phys_addr_t mips_cpc_default_phys_base(void)
 {
 	return DEFAULT_CPC_BASE_ADDR;
 }
 
+phys_addr_t mips_cdmm_phys_base(void)
+{
+	return DEFAULT_CDMM_BASE_ADDR;
+}
+
 static void __init mips_nmi_setup(void)
 {
 	void *base;
diff --git a/kernel/arch/mips/pistachio/time.c b/kernel/arch/mips/pistachio/time.c
index ab73f6f40..1022201b2 100644
--- a/kernel/arch/mips/pistachio/time.c
+++ b/kernel/arch/mips/pistachio/time.c
@@ -28,13 +28,18 @@ int get_c0_perfcount_int(void)
 }
 EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
 
+int get_c0_fdc_int(void)
+{
+	return gic_get_c0_fdc_int();
+}
+
 void __init plat_time_init(void)
 {
 	struct device_node *np;
 	struct clk *clk;
 
 	of_clk_init(NULL);
-	clocksource_of_init();
+	clocksource_probe();
 
 	np = of_get_cpu_node(0, NULL);
 	if (!np) {