diff options
Diffstat (limited to 'kernel/arch/mips/jz4740')
| -rw-r--r-- | kernel/arch/mips/jz4740/Kconfig | 9 | ||||
| -rw-r--r-- | kernel/arch/mips/jz4740/Makefile | 18 | ||||
| -rw-r--r-- | kernel/arch/mips/jz4740/Platform | 4 | ||||
| -rw-r--r-- | kernel/arch/mips/jz4740/board-qi_lb60.c | 526 | ||||
| -rw-r--r-- | kernel/arch/mips/jz4740/clock-debugfs.c | 108 | ||||
| -rw-r--r-- | kernel/arch/mips/jz4740/clock.c | 924 | ||||
| -rw-r--r-- | kernel/arch/mips/jz4740/clock.h | 76 | ||||
| -rw-r--r-- | kernel/arch/mips/jz4740/gpio.c | 521 | ||||
| -rw-r--r-- | kernel/arch/mips/jz4740/irq.c | 162 | ||||
| -rw-r--r-- | kernel/arch/mips/jz4740/irq.h | 23 | ||||
| -rw-r--r-- | kernel/arch/mips/jz4740/platform.c | 359 | ||||
| -rw-r--r-- | kernel/arch/mips/jz4740/pm.c | 53 | ||||
| -rw-r--r-- | kernel/arch/mips/jz4740/prom.c | 68 | ||||
| -rw-r--r-- | kernel/arch/mips/jz4740/reset.c | 118 | ||||
| -rw-r--r-- | kernel/arch/mips/jz4740/reset.h | 6 | ||||
| -rw-r--r-- | kernel/arch/mips/jz4740/serial.c | 33 | ||||
| -rw-r--r-- | kernel/arch/mips/jz4740/serial.h | 23 | ||||
| -rw-r--r-- | kernel/arch/mips/jz4740/setup.c | 61 | ||||
| -rw-r--r-- | kernel/arch/mips/jz4740/time.c | 151 | ||||
| -rw-r--r-- | kernel/arch/mips/jz4740/timer.c | 50 |
20 files changed, 3293 insertions, 0 deletions
diff --git a/kernel/arch/mips/jz4740/Kconfig b/kernel/arch/mips/jz4740/Kconfig new file mode 100644 index 000000000..468903053 --- /dev/null +++ b/kernel/arch/mips/jz4740/Kconfig @@ -0,0 +1,9 @@ +choice + prompt "Machine type" + depends on MACH_JZ4740 + default JZ4740_QI_LB60 + +config JZ4740_QI_LB60 + bool "Qi Hardware Ben NanoNote" + +endchoice diff --git a/kernel/arch/mips/jz4740/Makefile b/kernel/arch/mips/jz4740/Makefile new file mode 100644 index 000000000..28e5535df --- /dev/null +++ b/kernel/arch/mips/jz4740/Makefile @@ -0,0 +1,18 @@ +# +# Makefile for the Ingenic JZ4740. +# + +# Object file lists. + +obj-y += prom.o irq.o time.o reset.o setup.o \ + gpio.o clock.o platform.o timer.o serial.o + +obj-$(CONFIG_DEBUG_FS) += clock-debugfs.o + +# board specific support + +obj-$(CONFIG_JZ4740_QI_LB60) += board-qi_lb60.o + +# PM support + +obj-$(CONFIG_PM) += pm.o diff --git a/kernel/arch/mips/jz4740/Platform b/kernel/arch/mips/jz4740/Platform new file mode 100644 index 000000000..c41d30080 --- /dev/null +++ b/kernel/arch/mips/jz4740/Platform @@ -0,0 +1,4 @@ +platform-$(CONFIG_MACH_JZ4740) += jz4740/ +cflags-$(CONFIG_MACH_JZ4740) += -I$(srctree)/arch/mips/include/asm/mach-jz4740 +load-$(CONFIG_MACH_JZ4740) += 0xffffffff80010000 +zload-$(CONFIG_MACH_JZ4740) += 0xffffffff80600000 diff --git a/kernel/arch/mips/jz4740/board-qi_lb60.c b/kernel/arch/mips/jz4740/board-qi_lb60.c new file mode 100644 index 000000000..9dd051edb --- /dev/null +++ b/kernel/arch/mips/jz4740/board-qi_lb60.c @@ -0,0 +1,526 @@ +/* + * linux/arch/mips/jz4740/board-qi_lb60.c + * + * QI_LB60 board support + * + * Copyright (c) 2009 Qi Hardware inc., + * Author: Xiangfu Liu <xiangfu@qi-hardware.com> + * Copyright 2010, Lars-Peter Clausen <lars@metafoo.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 or later + * as published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/gpio.h> +#include <linux/gpio/machine.h> + +#include <linux/input.h> +#include <linux/gpio_keys.h> +#include <linux/input/matrix_keypad.h> +#include <linux/spi/spi.h> +#include <linux/spi/spi_gpio.h> +#include <linux/power_supply.h> +#include <linux/power/jz4740-battery.h> +#include <linux/power/gpio-charger.h> + +#include <asm/mach-jz4740/jz4740_fb.h> +#include <asm/mach-jz4740/jz4740_mmc.h> +#include <asm/mach-jz4740/jz4740_nand.h> + +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> + +#include <linux/leds_pwm.h> + +#include <asm/mach-jz4740/platform.h> + +#include "clock.h" + +static bool is_avt2; + +/* GPIOs */ +#define QI_LB60_GPIO_SD_CD JZ_GPIO_PORTD(0) +#define QI_LB60_GPIO_SD_VCC_EN_N JZ_GPIO_PORTD(2) + +#define QI_LB60_GPIO_KEYOUT(x) (JZ_GPIO_PORTC(10) + (x)) +#define QI_LB60_GPIO_KEYIN(x) (JZ_GPIO_PORTD(18) + (x)) +#define QI_LB60_GPIO_KEYIN8 JZ_GPIO_PORTD(26) + +/* NAND */ +static struct nand_ecclayout qi_lb60_ecclayout_1gb = { + .eccbytes = 36, + .eccpos = { + 6, 7, 8, 9, 10, 11, 12, 13, + 14, 15, 16, 17, 18, 19, 20, 21, + 22, 23, 24, 25, 26, 27, 28, 29, + 30, 31, 32, 33, 34, 35, 36, 37, + 38, 39, 40, 41 + }, + .oobfree = { + { .offset = 2, .length = 4 }, + { .offset = 42, .length = 22 } + }, +}; + +/* Early prototypes of the QI LB60 had only 1GB of NAND. + * In order to support these devices as well the partition and ecc layout is + * initialized depending on the NAND size */ +static struct mtd_partition qi_lb60_partitions_1gb[] = { + { + .name = "NAND BOOT partition", + .offset = 0 * 0x100000, + .size = 4 * 0x100000, + }, + { + .name = "NAND KERNEL partition", + .offset = 4 * 0x100000, + .size = 4 * 0x100000, + }, + { + .name = "NAND ROOTFS partition", + .offset = 8 * 0x100000, + .size = (504 + 512) * 0x100000, + }, +}; + +static struct nand_ecclayout qi_lb60_ecclayout_2gb = { + .eccbytes = 72, + .eccpos = { + 12, 13, 14, 15, 16, 17, 18, 19, + 20, 21, 22, 23, 24, 25, 26, 27, + 28, 29, 30, 31, 32, 33, 34, 35, + 36, 37, 38, 39, 40, 41, 42, 43, + 44, 45, 46, 47, 48, 49, 50, 51, + 52, 53, 54, 55, 56, 57, 58, 59, + 60, 61, 62, 63, 64, 65, 66, 67, + 68, 69, 70, 71, 72, 73, 74, 75, + 76, 77, 78, 79, 80, 81, 82, 83 + }, + .oobfree = { + { .offset = 2, .length = 10 }, + { .offset = 84, .length = 44 }, + }, +}; + +static struct mtd_partition qi_lb60_partitions_2gb[] = { + { + .name = "NAND BOOT partition", + .offset = 0 * 0x100000, + .size = 4 * 0x100000, + }, + { + .name = "NAND KERNEL partition", + .offset = 4 * 0x100000, + .size = 4 * 0x100000, + }, + { + .name = "NAND ROOTFS partition", + .offset = 8 * 0x100000, + .size = (504 + 512 + 1024) * 0x100000, + }, +}; + +static void qi_lb60_nand_ident(struct platform_device *pdev, + struct nand_chip *chip, struct mtd_partition **partitions, + int *num_partitions) +{ + if (chip->page_shift == 12) { + chip->ecc.layout = &qi_lb60_ecclayout_2gb; + *partitions = qi_lb60_partitions_2gb; + *num_partitions = ARRAY_SIZE(qi_lb60_partitions_2gb); + } else { + chip->ecc.layout = &qi_lb60_ecclayout_1gb; + *partitions = qi_lb60_partitions_1gb; + *num_partitions = ARRAY_SIZE(qi_lb60_partitions_1gb); + } +} + +static struct jz_nand_platform_data qi_lb60_nand_pdata = { + .ident_callback = qi_lb60_nand_ident, + .banks = { 1 }, +}; + +static struct gpiod_lookup_table qi_lb60_nand_gpio_table = { + .dev_id = "jz4740-nand.0", + .table = { + GPIO_LOOKUP("Bank C", 30, "busy", 0), + { }, + }, +}; + + +/* Keyboard*/ + +#define KEY_QI_QI KEY_F13 +#define KEY_QI_UPRED KEY_RIGHTALT +#define KEY_QI_VOLUP KEY_VOLUMEUP +#define KEY_QI_VOLDOWN KEY_VOLUMEDOWN +#define KEY_QI_FN KEY_LEFTCTRL + +static const uint32_t qi_lb60_keymap[] = { + KEY(0, 0, KEY_F1), /* S2 */ + KEY(0, 1, KEY_F2), /* S3 */ + KEY(0, 2, KEY_F3), /* S4 */ + KEY(0, 3, KEY_F4), /* S5 */ + KEY(0, 4, KEY_F5), /* S6 */ + KEY(0, 5, KEY_F6), /* S7 */ + KEY(0, 6, KEY_F7), /* S8 */ + + KEY(1, 0, KEY_Q), /* S10 */ + KEY(1, 1, KEY_W), /* S11 */ + KEY(1, 2, KEY_E), /* S12 */ + KEY(1, 3, KEY_R), /* S13 */ + KEY(1, 4, KEY_T), /* S14 */ + KEY(1, 5, KEY_Y), /* S15 */ + KEY(1, 6, KEY_U), /* S16 */ + KEY(1, 7, KEY_I), /* S17 */ + KEY(2, 0, KEY_A), /* S18 */ + KEY(2, 1, KEY_S), /* S19 */ + KEY(2, 2, KEY_D), /* S20 */ + KEY(2, 3, KEY_F), /* S21 */ + KEY(2, 4, KEY_G), /* S22 */ + KEY(2, 5, KEY_H), /* S23 */ + KEY(2, 6, KEY_J), /* S24 */ + KEY(2, 7, KEY_K), /* S25 */ + KEY(3, 0, KEY_ESC), /* S26 */ + KEY(3, 1, KEY_Z), /* S27 */ + KEY(3, 2, KEY_X), /* S28 */ + KEY(3, 3, KEY_C), /* S29 */ + KEY(3, 4, KEY_V), /* S30 */ + KEY(3, 5, KEY_B), /* S31 */ + KEY(3, 6, KEY_N), /* S32 */ + KEY(3, 7, KEY_M), /* S33 */ + KEY(4, 0, KEY_TAB), /* S34 */ + KEY(4, 1, KEY_CAPSLOCK), /* S35 */ + KEY(4, 2, KEY_BACKSLASH), /* S36 */ + KEY(4, 3, KEY_APOSTROPHE), /* S37 */ + KEY(4, 4, KEY_COMMA), /* S38 */ + KEY(4, 5, KEY_DOT), /* S39 */ + KEY(4, 6, KEY_SLASH), /* S40 */ + KEY(4, 7, KEY_UP), /* S41 */ + KEY(5, 0, KEY_O), /* S42 */ + KEY(5, 1, KEY_L), /* S43 */ + KEY(5, 2, KEY_EQUAL), /* S44 */ + KEY(5, 3, KEY_QI_UPRED), /* S45 */ + KEY(5, 4, KEY_SPACE), /* S46 */ + KEY(5, 5, KEY_QI_QI), /* S47 */ + KEY(5, 6, KEY_RIGHTCTRL), /* S48 */ + KEY(5, 7, KEY_LEFT), /* S49 */ + KEY(6, 0, KEY_F8), /* S50 */ + KEY(6, 1, KEY_P), /* S51 */ + KEY(6, 2, KEY_BACKSPACE),/* S52 */ + KEY(6, 3, KEY_ENTER), /* S53 */ + KEY(6, 4, KEY_QI_VOLUP), /* S54 */ + KEY(6, 5, KEY_QI_VOLDOWN), /* S55 */ + KEY(6, 6, KEY_DOWN), /* S56 */ + KEY(6, 7, KEY_RIGHT), /* S57 */ + + KEY(7, 0, KEY_LEFTSHIFT), /* S58 */ + KEY(7, 1, KEY_LEFTALT), /* S59 */ + KEY(7, 2, KEY_QI_FN), /* S60 */ +}; + +static const struct matrix_keymap_data qi_lb60_keymap_data = { + .keymap = qi_lb60_keymap, + .keymap_size = ARRAY_SIZE(qi_lb60_keymap), +}; + +static const unsigned int qi_lb60_keypad_cols[] = { + QI_LB60_GPIO_KEYOUT(0), + QI_LB60_GPIO_KEYOUT(1), + QI_LB60_GPIO_KEYOUT(2), + QI_LB60_GPIO_KEYOUT(3), + QI_LB60_GPIO_KEYOUT(4), + QI_LB60_GPIO_KEYOUT(5), + QI_LB60_GPIO_KEYOUT(6), + QI_LB60_GPIO_KEYOUT(7), +}; + +static const unsigned int qi_lb60_keypad_rows[] = { + QI_LB60_GPIO_KEYIN(0), + QI_LB60_GPIO_KEYIN(1), + QI_LB60_GPIO_KEYIN(2), + QI_LB60_GPIO_KEYIN(3), + QI_LB60_GPIO_KEYIN(4), + QI_LB60_GPIO_KEYIN(5), + QI_LB60_GPIO_KEYIN(6), + QI_LB60_GPIO_KEYIN8, +}; + +static struct matrix_keypad_platform_data qi_lb60_pdata = { + .keymap_data = &qi_lb60_keymap_data, + .col_gpios = qi_lb60_keypad_cols, + .row_gpios = qi_lb60_keypad_rows, + .num_col_gpios = ARRAY_SIZE(qi_lb60_keypad_cols), + .num_row_gpios = ARRAY_SIZE(qi_lb60_keypad_rows), + .col_scan_delay_us = 10, + .debounce_ms = 10, + .wakeup = 1, + .active_low = 1, +}; + +static struct platform_device qi_lb60_keypad = { + .name = "matrix-keypad", + .id = -1, + .dev = { + .platform_data = &qi_lb60_pdata, + }, +}; + +/* Display */ +static struct fb_videomode qi_lb60_video_modes[] = { + { + .name = "320x240", + .xres = 320, + .yres = 240, + .refresh = 30, + .left_margin = 140, + .right_margin = 273, + .upper_margin = 20, + .lower_margin = 2, + .hsync_len = 1, + .vsync_len = 1, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +static struct jz4740_fb_platform_data qi_lb60_fb_pdata = { + .width = 60, + .height = 45, + .num_modes = ARRAY_SIZE(qi_lb60_video_modes), + .modes = qi_lb60_video_modes, + .bpp = 24, + .lcd_type = JZ_LCD_TYPE_8BIT_SERIAL, + .pixclk_falling_edge = 1, +}; + +struct spi_gpio_platform_data spigpio_platform_data = { + .sck = JZ_GPIO_PORTC(23), + .mosi = JZ_GPIO_PORTC(22), + .miso = -1, + .num_chipselect = 1, +}; + +static struct platform_device spigpio_device = { + .name = "spi_gpio", + .id = 1, + .dev = { + .platform_data = &spigpio_platform_data, + }, +}; + +static struct spi_board_info qi_lb60_spi_board_info[] = { + { + .modalias = "ili8960", + .controller_data = (void *)JZ_GPIO_PORTC(21), + .chip_select = 0, + .bus_num = 1, + .max_speed_hz = 30 * 1000, + .mode = SPI_3WIRE, + }, +}; + +/* Battery */ +static struct jz_battery_platform_data qi_lb60_battery_pdata = { + .gpio_charge = JZ_GPIO_PORTC(27), + .gpio_charge_active_low = 1, + .info = { + .name = "battery", + .technology = POWER_SUPPLY_TECHNOLOGY_LIPO, + .voltage_max_design = 4200000, + .voltage_min_design = 3600000, + }, +}; + +/* GPIO Key: power */ +static struct gpio_keys_button qi_lb60_gpio_keys_buttons[] = { + [0] = { + .code = KEY_POWER, + .gpio = JZ_GPIO_PORTD(29), + .active_low = 1, + .desc = "Power", + .wakeup = 1, + }, +}; + +static struct gpio_keys_platform_data qi_lb60_gpio_keys_data = { + .nbuttons = ARRAY_SIZE(qi_lb60_gpio_keys_buttons), + .buttons = qi_lb60_gpio_keys_buttons, +}; + +static struct platform_device qi_lb60_gpio_keys = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &qi_lb60_gpio_keys_data, + } +}; + +static struct jz4740_mmc_platform_data qi_lb60_mmc_pdata = { + .gpio_card_detect = QI_LB60_GPIO_SD_CD, + .gpio_read_only = -1, + .gpio_power = QI_LB60_GPIO_SD_VCC_EN_N, + .power_active_low = 1, +}; + +/* OHCI */ +static struct regulator_consumer_supply avt2_usb_regulator_consumer = + REGULATOR_SUPPLY("vbus", "jz4740-ohci"); + +static struct regulator_init_data avt2_usb_regulator_init_data = { + .num_consumer_supplies = 1, + .consumer_supplies = &avt2_usb_regulator_consumer, + .constraints = { + .name = "USB power", + .min_uV = 5000000, + .max_uV = 5000000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, +}; + +static struct fixed_voltage_config avt2_usb_regulator_data = { + .supply_name = "USB power", + .microvolts = 5000000, + .gpio = JZ_GPIO_PORTB(17), + .init_data = &avt2_usb_regulator_init_data, +}; + +static struct platform_device avt2_usb_regulator_device = { + .name = "reg-fixed-voltage", + .id = -1, + .dev = { + .platform_data = &avt2_usb_regulator_data, + } +}; + +/* beeper */ +static struct platform_device qi_lb60_pwm_beeper = { + .name = "pwm-beeper", + .id = -1, + .dev = { + .platform_data = (void *)4, + }, +}; + +/* charger */ +static char *qi_lb60_batteries[] = { + "battery", +}; + +static struct gpio_charger_platform_data qi_lb60_charger_pdata = { + .name = "usb", + .type = POWER_SUPPLY_TYPE_USB, + .gpio = JZ_GPIO_PORTD(28), + .gpio_active_low = 1, + .supplied_to = qi_lb60_batteries, + .num_supplicants = ARRAY_SIZE(qi_lb60_batteries), +}; + +static struct platform_device qi_lb60_charger_device = { + .name = "gpio-charger", + .dev = { + .platform_data = &qi_lb60_charger_pdata, + }, +}; + +/* audio */ +static struct platform_device qi_lb60_audio_device = { + .name = "qi-lb60-audio", + .id = -1, +}; + +static struct gpiod_lookup_table qi_lb60_audio_gpio_table = { + .dev_id = "qi-lb60-audio", + .table = { + GPIO_LOOKUP("Bank B", 29, "snd", 0), + GPIO_LOOKUP("Bank D", 4, "amp", 0), + { }, + }, +}; + +static struct platform_device *jz_platform_devices[] __initdata = { + &jz4740_udc_device, + &jz4740_udc_xceiv_device, + &jz4740_mmc_device, + &jz4740_nand_device, + &qi_lb60_keypad, + &spigpio_device, + &jz4740_framebuffer_device, + &jz4740_pcm_device, + &jz4740_i2s_device, + &jz4740_codec_device, + &jz4740_rtc_device, + &jz4740_adc_device, + &jz4740_pwm_device, + &jz4740_dma_device, + &qi_lb60_gpio_keys, + &qi_lb60_pwm_beeper, + &qi_lb60_charger_device, + &qi_lb60_audio_device, +}; + +static void __init board_gpio_setup(void) +{ + /* We only need to enable/disable pullup here for pins used in generic + * drivers. Everything else is done by the drivers themselves. */ + jz_gpio_disable_pullup(QI_LB60_GPIO_SD_VCC_EN_N); + jz_gpio_disable_pullup(QI_LB60_GPIO_SD_CD); +} + +static int __init qi_lb60_init_platform_devices(void) +{ + jz4740_framebuffer_device.dev.platform_data = &qi_lb60_fb_pdata; + jz4740_nand_device.dev.platform_data = &qi_lb60_nand_pdata; + jz4740_adc_device.dev.platform_data = &qi_lb60_battery_pdata; + jz4740_mmc_device.dev.platform_data = &qi_lb60_mmc_pdata; + + gpiod_add_lookup_table(&qi_lb60_audio_gpio_table); + gpiod_add_lookup_table(&qi_lb60_nand_gpio_table); + + jz4740_serial_device_register(); + + spi_register_board_info(qi_lb60_spi_board_info, + ARRAY_SIZE(qi_lb60_spi_board_info)); + + if (is_avt2) { + platform_device_register(&avt2_usb_regulator_device); + platform_device_register(&jz4740_usb_ohci_device); + } + + return platform_add_devices(jz_platform_devices, + ARRAY_SIZE(jz_platform_devices)); + +} + +struct jz4740_clock_board_data jz4740_clock_bdata = { + .ext_rate = 12000000, + .rtc_rate = 32768, +}; + +static __init int board_avt2(char *str) +{ + qi_lb60_mmc_pdata.card_detect_active_low = 1; + is_avt2 = true; + + return 1; +} +__setup("avt2", board_avt2); + +static int __init qi_lb60_board_setup(void) +{ + printk(KERN_INFO "Qi Hardware JZ4740 QI %s setup\n", + is_avt2 ? "AVT2" : "LB60"); + + board_gpio_setup(); + + if (qi_lb60_init_platform_devices()) + panic("Failed to initialize platform devices"); + + return 0; +} +arch_initcall(qi_lb60_board_setup); diff --git a/kernel/arch/mips/jz4740/clock-debugfs.c b/kernel/arch/mips/jz4740/clock-debugfs.c new file mode 100644 index 000000000..325422d0d --- /dev/null +++ b/kernel/arch/mips/jz4740/clock-debugfs.c @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> + * JZ4740 SoC clock support debugfs entries + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/clk.h> +#include <linux/err.h> + +#include <linux/debugfs.h> +#include <linux/uaccess.h> + +#include <asm/mach-jz4740/clock.h> +#include "clock.h" + +static struct dentry *jz4740_clock_debugfs; + +static int jz4740_clock_debugfs_show_enabled(void *data, uint64_t *value) +{ + struct clk *clk = data; + *value = clk_is_enabled(clk); + + return 0; +} + +static int jz4740_clock_debugfs_set_enabled(void *data, uint64_t value) +{ + struct clk *clk = data; + + if (value) + return clk_enable(clk); + else + clk_disable(clk); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(jz4740_clock_debugfs_ops_enabled, + jz4740_clock_debugfs_show_enabled, + jz4740_clock_debugfs_set_enabled, + "%llu\n"); + +static int jz4740_clock_debugfs_show_rate(void *data, uint64_t *value) +{ + struct clk *clk = data; + *value = clk_get_rate(clk); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(jz4740_clock_debugfs_ops_rate, + jz4740_clock_debugfs_show_rate, + NULL, + "%llu\n"); + +void jz4740_clock_debugfs_add_clk(struct clk *clk) +{ + if (!jz4740_clock_debugfs) + return; + + clk->debugfs_entry = debugfs_create_dir(clk->name, jz4740_clock_debugfs); + debugfs_create_file("rate", S_IWUGO | S_IRUGO, clk->debugfs_entry, clk, + &jz4740_clock_debugfs_ops_rate); + debugfs_create_file("enabled", S_IRUGO, clk->debugfs_entry, clk, + &jz4740_clock_debugfs_ops_enabled); + + if (clk->parent) { + char parent_path[100]; + snprintf(parent_path, 100, "../%s", clk->parent->name); + clk->debugfs_parent_entry = debugfs_create_symlink("parent", + clk->debugfs_entry, + parent_path); + } +} + +/* TODO: Locking */ +void jz4740_clock_debugfs_update_parent(struct clk *clk) +{ + debugfs_remove(clk->debugfs_parent_entry); + + if (clk->parent) { + char parent_path[100]; + snprintf(parent_path, 100, "../%s", clk->parent->name); + clk->debugfs_parent_entry = debugfs_create_symlink("parent", + clk->debugfs_entry, + parent_path); + } else { + clk->debugfs_parent_entry = NULL; + } +} + +void jz4740_clock_debugfs_init(void) +{ + jz4740_clock_debugfs = debugfs_create_dir("jz4740-clock", NULL); + if (IS_ERR(jz4740_clock_debugfs)) + jz4740_clock_debugfs = NULL; +} diff --git a/kernel/arch/mips/jz4740/clock.c b/kernel/arch/mips/jz4740/clock.c new file mode 100644 index 000000000..1b5f55426 --- /dev/null +++ b/kernel/arch/mips/jz4740/clock.c @@ -0,0 +1,924 @@ +/* + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> + * JZ4740 SoC clock support + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/clk.h> +#include <linux/spinlock.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/list.h> +#include <linux/err.h> + +#include <asm/mach-jz4740/clock.h> +#include <asm/mach-jz4740/base.h> + +#include "clock.h" + +#define JZ_REG_CLOCK_CTRL 0x00 +#define JZ_REG_CLOCK_LOW_POWER 0x04 +#define JZ_REG_CLOCK_PLL 0x10 +#define JZ_REG_CLOCK_GATE 0x20 +#define JZ_REG_CLOCK_SLEEP_CTRL 0x24 +#define JZ_REG_CLOCK_I2S 0x60 +#define JZ_REG_CLOCK_LCD 0x64 +#define JZ_REG_CLOCK_MMC 0x68 +#define JZ_REG_CLOCK_UHC 0x6C +#define JZ_REG_CLOCK_SPI 0x74 + +#define JZ_CLOCK_CTRL_I2S_SRC_PLL BIT(31) +#define JZ_CLOCK_CTRL_KO_ENABLE BIT(30) +#define JZ_CLOCK_CTRL_UDC_SRC_PLL BIT(29) +#define JZ_CLOCK_CTRL_UDIV_MASK 0x1f800000 +#define JZ_CLOCK_CTRL_CHANGE_ENABLE BIT(22) +#define JZ_CLOCK_CTRL_PLL_HALF BIT(21) +#define JZ_CLOCK_CTRL_LDIV_MASK 0x001f0000 +#define JZ_CLOCK_CTRL_UDIV_OFFSET 23 +#define JZ_CLOCK_CTRL_LDIV_OFFSET 16 +#define JZ_CLOCK_CTRL_MDIV_OFFSET 12 +#define JZ_CLOCK_CTRL_PDIV_OFFSET 8 +#define JZ_CLOCK_CTRL_HDIV_OFFSET 4 +#define JZ_CLOCK_CTRL_CDIV_OFFSET 0 + +#define JZ_CLOCK_GATE_UART0 BIT(0) +#define JZ_CLOCK_GATE_TCU BIT(1) +#define JZ_CLOCK_GATE_RTC BIT(2) +#define JZ_CLOCK_GATE_I2C BIT(3) +#define JZ_CLOCK_GATE_SPI BIT(4) +#define JZ_CLOCK_GATE_AIC BIT(5) +#define JZ_CLOCK_GATE_I2S BIT(6) +#define JZ_CLOCK_GATE_MMC BIT(7) +#define JZ_CLOCK_GATE_ADC BIT(8) +#define JZ_CLOCK_GATE_CIM BIT(9) +#define JZ_CLOCK_GATE_LCD BIT(10) +#define JZ_CLOCK_GATE_UDC BIT(11) +#define JZ_CLOCK_GATE_DMAC BIT(12) +#define JZ_CLOCK_GATE_IPU BIT(13) +#define JZ_CLOCK_GATE_UHC BIT(14) +#define JZ_CLOCK_GATE_UART1 BIT(15) + +#define JZ_CLOCK_I2S_DIV_MASK 0x01ff + +#define JZ_CLOCK_LCD_DIV_MASK 0x01ff + +#define JZ_CLOCK_MMC_DIV_MASK 0x001f + +#define JZ_CLOCK_UHC_DIV_MASK 0x000f + +#define JZ_CLOCK_SPI_SRC_PLL BIT(31) +#define JZ_CLOCK_SPI_DIV_MASK 0x000f + +#define JZ_CLOCK_PLL_M_MASK 0x01ff +#define JZ_CLOCK_PLL_N_MASK 0x001f +#define JZ_CLOCK_PLL_OD_MASK 0x0003 +#define JZ_CLOCK_PLL_STABLE BIT(10) +#define JZ_CLOCK_PLL_BYPASS BIT(9) +#define JZ_CLOCK_PLL_ENABLED BIT(8) +#define JZ_CLOCK_PLL_STABLIZE_MASK 0x000f +#define JZ_CLOCK_PLL_M_OFFSET 23 +#define JZ_CLOCK_PLL_N_OFFSET 18 +#define JZ_CLOCK_PLL_OD_OFFSET 16 + +#define JZ_CLOCK_LOW_POWER_MODE_DOZE BIT(2) +#define JZ_CLOCK_LOW_POWER_MODE_SLEEP BIT(0) + +#define JZ_CLOCK_SLEEP_CTRL_SUSPEND_UHC BIT(7) +#define JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC BIT(6) + +static void __iomem *jz_clock_base; +static spinlock_t jz_clock_lock; +static LIST_HEAD(jz_clocks); + +struct main_clk { + struct clk clk; + uint32_t div_offset; +}; + +struct divided_clk { + struct clk clk; + uint32_t reg; + uint32_t mask; +}; + +struct static_clk { + struct clk clk; + unsigned long rate; +}; + +static uint32_t jz_clk_reg_read(int reg) +{ + return readl(jz_clock_base + reg); +} + +static void jz_clk_reg_write_mask(int reg, uint32_t val, uint32_t mask) +{ + uint32_t val2; + + spin_lock(&jz_clock_lock); + val2 = readl(jz_clock_base + reg); + val2 &= ~mask; + val2 |= val; + writel(val2, jz_clock_base + reg); + spin_unlock(&jz_clock_lock); +} + +static void jz_clk_reg_set_bits(int reg, uint32_t mask) +{ + uint32_t val; + + spin_lock(&jz_clock_lock); + val = readl(jz_clock_base + reg); + val |= mask; + writel(val, jz_clock_base + reg); + spin_unlock(&jz_clock_lock); +} + +static void jz_clk_reg_clear_bits(int reg, uint32_t mask) +{ + uint32_t val; + + spin_lock(&jz_clock_lock); + val = readl(jz_clock_base + reg); + val &= ~mask; + writel(val, jz_clock_base + reg); + spin_unlock(&jz_clock_lock); +} + +static int jz_clk_enable_gating(struct clk *clk) +{ + if (clk->gate_bit == JZ4740_CLK_NOT_GATED) + return -EINVAL; + + jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, clk->gate_bit); + return 0; +} + +static int jz_clk_disable_gating(struct clk *clk) +{ + if (clk->gate_bit == JZ4740_CLK_NOT_GATED) + return -EINVAL; + + jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, clk->gate_bit); + return 0; +} + +static int jz_clk_is_enabled_gating(struct clk *clk) +{ + if (clk->gate_bit == JZ4740_CLK_NOT_GATED) + return 1; + + return !(jz_clk_reg_read(JZ_REG_CLOCK_GATE) & clk->gate_bit); +} + +static unsigned long jz_clk_static_get_rate(struct clk *clk) +{ + return ((struct static_clk *)clk)->rate; +} + +static int jz_clk_ko_enable(struct clk *clk) +{ + jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE); + return 0; +} + +static int jz_clk_ko_disable(struct clk *clk) +{ + jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE); + return 0; +} + +static int jz_clk_ko_is_enabled(struct clk *clk) +{ + return !!(jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_KO_ENABLE); +} + +static const int pllno[] = {1, 2, 2, 4}; + +static unsigned long jz_clk_pll_get_rate(struct clk *clk) +{ + uint32_t val; + int m; + int n; + int od; + + val = jz_clk_reg_read(JZ_REG_CLOCK_PLL); + + if (val & JZ_CLOCK_PLL_BYPASS) + return clk_get_rate(clk->parent); + + m = ((val >> 23) & 0x1ff) + 2; + n = ((val >> 18) & 0x1f) + 2; + od = (val >> 16) & 0x3; + + return ((clk_get_rate(clk->parent) / n) * m) / pllno[od]; +} + +static unsigned long jz_clk_pll_half_get_rate(struct clk *clk) +{ + uint32_t reg; + + reg = jz_clk_reg_read(JZ_REG_CLOCK_CTRL); + if (reg & JZ_CLOCK_CTRL_PLL_HALF) + return jz_clk_pll_get_rate(clk->parent); + return jz_clk_pll_get_rate(clk->parent) >> 1; +} + +static const int jz_clk_main_divs[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; + +static unsigned long jz_clk_main_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent); + int div; + + div = parent_rate / rate; + if (div > 32) + return parent_rate / 32; + else if (div < 1) + return parent_rate; + + div &= (0x3 << (ffs(div) - 1)); + + return parent_rate / div; +} + +static unsigned long jz_clk_main_get_rate(struct clk *clk) +{ + struct main_clk *mclk = (struct main_clk *)clk; + uint32_t div; + + div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL); + + div >>= mclk->div_offset; + div &= 0xf; + + if (div >= ARRAY_SIZE(jz_clk_main_divs)) + div = ARRAY_SIZE(jz_clk_main_divs) - 1; + + return jz_clk_pll_get_rate(clk->parent) / jz_clk_main_divs[div]; +} + +static int jz_clk_main_set_rate(struct clk *clk, unsigned long rate) +{ + struct main_clk *mclk = (struct main_clk *)clk; + int i; + int div; + unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent); + + rate = jz_clk_main_round_rate(clk, rate); + + div = parent_rate / rate; + + i = (ffs(div) - 1) << 1; + if (i > 0 && !(div & BIT(i-1))) + i -= 1; + + jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, i << mclk->div_offset, + 0xf << mclk->div_offset); + + return 0; +} + +static struct clk_ops jz_clk_static_ops = { + .get_rate = jz_clk_static_get_rate, + .enable = jz_clk_enable_gating, + .disable = jz_clk_disable_gating, + .is_enabled = jz_clk_is_enabled_gating, +}; + +static struct static_clk jz_clk_ext = { + .clk = { + .name = "ext", + .gate_bit = JZ4740_CLK_NOT_GATED, + .ops = &jz_clk_static_ops, + }, +}; + +static struct clk_ops jz_clk_pll_ops = { + .get_rate = jz_clk_pll_get_rate, +}; + +static struct clk jz_clk_pll = { + .name = "pll", + .parent = &jz_clk_ext.clk, + .ops = &jz_clk_pll_ops, +}; + +static struct clk_ops jz_clk_pll_half_ops = { + .get_rate = jz_clk_pll_half_get_rate, +}; + +static struct clk jz_clk_pll_half = { + .name = "pll half", + .parent = &jz_clk_pll, + .ops = &jz_clk_pll_half_ops, +}; + +static const struct clk_ops jz_clk_main_ops = { + .get_rate = jz_clk_main_get_rate, + .set_rate = jz_clk_main_set_rate, + .round_rate = jz_clk_main_round_rate, +}; + +static struct main_clk jz_clk_cpu = { + .clk = { + .name = "cclk", + .parent = &jz_clk_pll, + .ops = &jz_clk_main_ops, + }, + .div_offset = JZ_CLOCK_CTRL_CDIV_OFFSET, +}; + +static struct main_clk jz_clk_memory = { + .clk = { + .name = "mclk", + .parent = &jz_clk_pll, + .ops = &jz_clk_main_ops, + }, + .div_offset = JZ_CLOCK_CTRL_MDIV_OFFSET, +}; + +static struct main_clk jz_clk_high_speed_peripheral = { + .clk = { + .name = "hclk", + .parent = &jz_clk_pll, + .ops = &jz_clk_main_ops, + }, + .div_offset = JZ_CLOCK_CTRL_HDIV_OFFSET, +}; + + +static struct main_clk jz_clk_low_speed_peripheral = { + .clk = { + .name = "pclk", + .parent = &jz_clk_pll, + .ops = &jz_clk_main_ops, + }, + .div_offset = JZ_CLOCK_CTRL_PDIV_OFFSET, +}; + +static const struct clk_ops jz_clk_ko_ops = { + .enable = jz_clk_ko_enable, + .disable = jz_clk_ko_disable, + .is_enabled = jz_clk_ko_is_enabled, +}; + +static struct clk jz_clk_ko = { + .name = "cko", + .parent = &jz_clk_memory.clk, + .ops = &jz_clk_ko_ops, +}; + +static int jz_clk_spi_set_parent(struct clk *clk, struct clk *parent) +{ + if (parent == &jz_clk_pll) + jz_clk_reg_set_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI); + else if (parent == &jz_clk_ext.clk) + jz_clk_reg_clear_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI); + else + return -EINVAL; + + clk->parent = parent; + + return 0; +} + +static int jz_clk_i2s_set_parent(struct clk *clk, struct clk *parent) +{ + if (parent == &jz_clk_pll_half) + jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL); + else if (parent == &jz_clk_ext.clk) + jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL); + else + return -EINVAL; + + clk->parent = parent; + + return 0; +} + +static int jz_clk_udc_enable(struct clk *clk) +{ + jz_clk_reg_set_bits(JZ_REG_CLOCK_SLEEP_CTRL, + JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC); + + return 0; +} + +static int jz_clk_udc_disable(struct clk *clk) +{ + jz_clk_reg_clear_bits(JZ_REG_CLOCK_SLEEP_CTRL, + JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC); + + return 0; +} + +static int jz_clk_udc_is_enabled(struct clk *clk) +{ + return !!(jz_clk_reg_read(JZ_REG_CLOCK_SLEEP_CTRL) & + JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC); +} + +static int jz_clk_udc_set_parent(struct clk *clk, struct clk *parent) +{ + if (parent == &jz_clk_pll_half) + jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL); + else if (parent == &jz_clk_ext.clk) + jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL); + else + return -EINVAL; + + clk->parent = parent; + + return 0; +} + +static int jz_clk_udc_set_rate(struct clk *clk, unsigned long rate) +{ + int div; + + if (clk->parent == &jz_clk_ext.clk) + return -EINVAL; + + div = clk_get_rate(clk->parent) / rate - 1; + + if (div < 0) + div = 0; + else if (div > 63) + div = 63; + + jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_UDIV_OFFSET, + JZ_CLOCK_CTRL_UDIV_MASK); + return 0; +} + +static unsigned long jz_clk_udc_get_rate(struct clk *clk) +{ + int div; + + if (clk->parent == &jz_clk_ext.clk) + return clk_get_rate(clk->parent); + + div = (jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_UDIV_MASK); + div >>= JZ_CLOCK_CTRL_UDIV_OFFSET; + div += 1; + + return clk_get_rate(clk->parent) / div; +} + +static unsigned long jz_clk_divided_get_rate(struct clk *clk) +{ + struct divided_clk *dclk = (struct divided_clk *)clk; + int div; + + if (clk->parent == &jz_clk_ext.clk) + return clk_get_rate(clk->parent); + + div = (jz_clk_reg_read(dclk->reg) & dclk->mask) + 1; + + return clk_get_rate(clk->parent) / div; +} + +static int jz_clk_divided_set_rate(struct clk *clk, unsigned long rate) +{ + struct divided_clk *dclk = (struct divided_clk *)clk; + int div; + + if (clk->parent == &jz_clk_ext.clk) + return -EINVAL; + + div = clk_get_rate(clk->parent) / rate - 1; + + if (div < 0) + div = 0; + else if (div > dclk->mask) + div = dclk->mask; + + jz_clk_reg_write_mask(dclk->reg, div, dclk->mask); + + return 0; +} + +static unsigned long jz_clk_ldclk_round_rate(struct clk *clk, unsigned long rate) +{ + int div; + unsigned long parent_rate = jz_clk_pll_half_get_rate(clk->parent); + + if (rate > 150000000) + return 150000000; + + div = parent_rate / rate; + if (div < 1) + div = 1; + else if (div > 32) + div = 32; + + return parent_rate / div; +} + +static int jz_clk_ldclk_set_rate(struct clk *clk, unsigned long rate) +{ + int div; + + if (rate > 150000000) + return -EINVAL; + + div = jz_clk_pll_half_get_rate(clk->parent) / rate - 1; + if (div < 0) + div = 0; + else if (div > 31) + div = 31; + + jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_LDIV_OFFSET, + JZ_CLOCK_CTRL_LDIV_MASK); + + return 0; +} + +static unsigned long jz_clk_ldclk_get_rate(struct clk *clk) +{ + int div; + + div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_LDIV_MASK; + div >>= JZ_CLOCK_CTRL_LDIV_OFFSET; + + return jz_clk_pll_half_get_rate(clk->parent) / (div + 1); +} + +static const struct clk_ops jz_clk_ops_ld = { + .set_rate = jz_clk_ldclk_set_rate, + .get_rate = jz_clk_ldclk_get_rate, + .round_rate = jz_clk_ldclk_round_rate, + .enable = jz_clk_enable_gating, + .disable = jz_clk_disable_gating, + .is_enabled = jz_clk_is_enabled_gating, +}; + +static struct clk jz_clk_ld = { + .name = "lcd", + .gate_bit = JZ_CLOCK_GATE_LCD, + .parent = &jz_clk_pll_half, + .ops = &jz_clk_ops_ld, +}; + +static const struct clk_ops jz_clk_i2s_ops = { + .set_rate = jz_clk_divided_set_rate, + .get_rate = jz_clk_divided_get_rate, + .enable = jz_clk_enable_gating, + .disable = jz_clk_disable_gating, + .is_enabled = jz_clk_is_enabled_gating, + .set_parent = jz_clk_i2s_set_parent, +}; + +static const struct clk_ops jz_clk_spi_ops = { + .set_rate = jz_clk_divided_set_rate, + .get_rate = jz_clk_divided_get_rate, + .enable = jz_clk_enable_gating, + .disable = jz_clk_disable_gating, + .is_enabled = jz_clk_is_enabled_gating, + .set_parent = jz_clk_spi_set_parent, +}; + +static const struct clk_ops jz_clk_divided_ops = { + .set_rate = jz_clk_divided_set_rate, + .get_rate = jz_clk_divided_get_rate, + .enable = jz_clk_enable_gating, + .disable = jz_clk_disable_gating, + .is_enabled = jz_clk_is_enabled_gating, +}; + +static struct divided_clk jz4740_clock_divided_clks[] = { + [0] = { + .clk = { + .name = "i2s", + .parent = &jz_clk_ext.clk, + .gate_bit = JZ_CLOCK_GATE_I2S, + .ops = &jz_clk_i2s_ops, + }, + .reg = JZ_REG_CLOCK_I2S, + .mask = JZ_CLOCK_I2S_DIV_MASK, + }, + [1] = { + .clk = { + .name = "spi", + .parent = &jz_clk_ext.clk, + .gate_bit = JZ_CLOCK_GATE_SPI, + .ops = &jz_clk_spi_ops, + }, + .reg = JZ_REG_CLOCK_SPI, + .mask = JZ_CLOCK_SPI_DIV_MASK, + }, + [2] = { + .clk = { + .name = "lcd_pclk", + .parent = &jz_clk_pll_half, + .gate_bit = JZ4740_CLK_NOT_GATED, + .ops = &jz_clk_divided_ops, + }, + .reg = JZ_REG_CLOCK_LCD, + .mask = JZ_CLOCK_LCD_DIV_MASK, + }, + [3] = { + .clk = { + .name = "mmc", + .parent = &jz_clk_pll_half, + .gate_bit = JZ_CLOCK_GATE_MMC, + .ops = &jz_clk_divided_ops, + }, + .reg = JZ_REG_CLOCK_MMC, + .mask = JZ_CLOCK_MMC_DIV_MASK, + }, + [4] = { + .clk = { + .name = "uhc", + .parent = &jz_clk_pll_half, + .gate_bit = JZ_CLOCK_GATE_UHC, + .ops = &jz_clk_divided_ops, + }, + .reg = JZ_REG_CLOCK_UHC, + .mask = JZ_CLOCK_UHC_DIV_MASK, + }, +}; + +static const struct clk_ops jz_clk_udc_ops = { + .set_parent = jz_clk_udc_set_parent, + .set_rate = jz_clk_udc_set_rate, + .get_rate = jz_clk_udc_get_rate, + .enable = jz_clk_udc_enable, + .disable = jz_clk_udc_disable, + .is_enabled = jz_clk_udc_is_enabled, +}; + +static const struct clk_ops jz_clk_simple_ops = { + .enable = jz_clk_enable_gating, + .disable = jz_clk_disable_gating, + .is_enabled = jz_clk_is_enabled_gating, +}; + +static struct clk jz4740_clock_simple_clks[] = { + [0] = { + .name = "udc", + .parent = &jz_clk_ext.clk, + .ops = &jz_clk_udc_ops, + }, + [1] = { + .name = "uart0", + .parent = &jz_clk_ext.clk, + .gate_bit = JZ_CLOCK_GATE_UART0, + .ops = &jz_clk_simple_ops, + }, + [2] = { + .name = "uart1", + .parent = &jz_clk_ext.clk, + .gate_bit = JZ_CLOCK_GATE_UART1, + .ops = &jz_clk_simple_ops, + }, + [3] = { + .name = "dma", + .parent = &jz_clk_high_speed_peripheral.clk, + .gate_bit = JZ_CLOCK_GATE_DMAC, + .ops = &jz_clk_simple_ops, + }, + [4] = { + .name = "ipu", + .parent = &jz_clk_high_speed_peripheral.clk, + .gate_bit = JZ_CLOCK_GATE_IPU, + .ops = &jz_clk_simple_ops, + }, + [5] = { + .name = "adc", + .parent = &jz_clk_ext.clk, + .gate_bit = JZ_CLOCK_GATE_ADC, + .ops = &jz_clk_simple_ops, + }, + [6] = { + .name = "i2c", + .parent = &jz_clk_ext.clk, + .gate_bit = JZ_CLOCK_GATE_I2C, + .ops = &jz_clk_simple_ops, + }, + [7] = { + .name = "aic", + .parent = &jz_clk_ext.clk, + .gate_bit = JZ_CLOCK_GATE_AIC, + .ops = &jz_clk_simple_ops, + }, +}; + +static struct static_clk jz_clk_rtc = { + .clk = { + .name = "rtc", + .gate_bit = JZ_CLOCK_GATE_RTC, + .ops = &jz_clk_static_ops, + }, + .rate = 32768, +}; + +int clk_enable(struct clk *clk) +{ + if (!clk->ops->enable) + return -EINVAL; + + return clk->ops->enable(clk); +} +EXPORT_SYMBOL_GPL(clk_enable); + +void clk_disable(struct clk *clk) +{ + if (clk->ops->disable) + clk->ops->disable(clk); +} +EXPORT_SYMBOL_GPL(clk_disable); + +int clk_is_enabled(struct clk *clk) +{ + if (clk->ops->is_enabled) + return clk->ops->is_enabled(clk); + + return 1; +} + +unsigned long clk_get_rate(struct clk *clk) +{ + if (clk->ops->get_rate) + return clk->ops->get_rate(clk); + if (clk->parent) + return clk_get_rate(clk->parent); + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(clk_get_rate); + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + if (!clk->ops->set_rate) + return -EINVAL; + return clk->ops->set_rate(clk, rate); +} +EXPORT_SYMBOL_GPL(clk_set_rate); + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + if (clk->ops->round_rate) + return clk->ops->round_rate(clk, rate); + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(clk_round_rate); + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + int ret; + int enabled; + + if (!clk->ops->set_parent) + return -EINVAL; + + enabled = clk_is_enabled(clk); + if (enabled) + clk_disable(clk); + ret = clk->ops->set_parent(clk, parent); + if (enabled) + clk_enable(clk); + + jz4740_clock_debugfs_update_parent(clk); + + return ret; +} +EXPORT_SYMBOL_GPL(clk_set_parent); + +struct clk *clk_get(struct device *dev, const char *name) +{ + struct clk *clk; + + list_for_each_entry(clk, &jz_clocks, list) { + if (strcmp(clk->name, name) == 0) + return clk; + } + return ERR_PTR(-ENXIO); +} +EXPORT_SYMBOL_GPL(clk_get); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL_GPL(clk_put); + +static inline void clk_add(struct clk *clk) +{ + list_add_tail(&clk->list, &jz_clocks); + + jz4740_clock_debugfs_add_clk(clk); +} + +static void clk_register_clks(void) +{ + size_t i; + + clk_add(&jz_clk_ext.clk); + clk_add(&jz_clk_pll); + clk_add(&jz_clk_pll_half); + clk_add(&jz_clk_cpu.clk); + clk_add(&jz_clk_high_speed_peripheral.clk); + clk_add(&jz_clk_low_speed_peripheral.clk); + clk_add(&jz_clk_ko); + clk_add(&jz_clk_ld); + clk_add(&jz_clk_rtc.clk); + + for (i = 0; i < ARRAY_SIZE(jz4740_clock_divided_clks); ++i) + clk_add(&jz4740_clock_divided_clks[i].clk); + + for (i = 0; i < ARRAY_SIZE(jz4740_clock_simple_clks); ++i) + clk_add(&jz4740_clock_simple_clks[i]); +} + +void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode) +{ + switch (mode) { + case JZ4740_WAIT_MODE_IDLE: + jz_clk_reg_clear_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP); + break; + case JZ4740_WAIT_MODE_SLEEP: + jz_clk_reg_set_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP); + break; + } +} + +void jz4740_clock_udc_disable_auto_suspend(void) +{ + jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC); +} +EXPORT_SYMBOL_GPL(jz4740_clock_udc_disable_auto_suspend); + +void jz4740_clock_udc_enable_auto_suspend(void) +{ + jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC); +} +EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend); + +void jz4740_clock_suspend(void) +{ + jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, + JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0); + + jz_clk_reg_clear_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED); +} + +void jz4740_clock_resume(void) +{ + uint32_t pll; + + jz_clk_reg_set_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED); + + do { + pll = jz_clk_reg_read(JZ_REG_CLOCK_PLL); + } while (!(pll & JZ_CLOCK_PLL_STABLE)); + + jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, + JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0); +} + +static int jz4740_clock_init(void) +{ + uint32_t val; + + jz_clock_base = ioremap(JZ4740_CPM_BASE_ADDR, 0x100); + if (!jz_clock_base) + return -EBUSY; + + spin_lock_init(&jz_clock_lock); + + jz_clk_ext.rate = jz4740_clock_bdata.ext_rate; + jz_clk_rtc.rate = jz4740_clock_bdata.rtc_rate; + + val = jz_clk_reg_read(JZ_REG_CLOCK_SPI); + + if (val & JZ_CLOCK_SPI_SRC_PLL) + jz4740_clock_divided_clks[1].clk.parent = &jz_clk_pll_half; + + val = jz_clk_reg_read(JZ_REG_CLOCK_CTRL); + + if (val & JZ_CLOCK_CTRL_I2S_SRC_PLL) + jz4740_clock_divided_clks[0].clk.parent = &jz_clk_pll_half; + + if (val & JZ_CLOCK_CTRL_UDC_SRC_PLL) + jz4740_clock_simple_clks[0].parent = &jz_clk_pll_half; + + jz4740_clock_debugfs_init(); + + clk_register_clks(); + + return 0; +} +arch_initcall(jz4740_clock_init); diff --git a/kernel/arch/mips/jz4740/clock.h b/kernel/arch/mips/jz4740/clock.h new file mode 100644 index 000000000..5d07499d7 --- /dev/null +++ b/kernel/arch/mips/jz4740/clock.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> + * JZ4740 SoC clock support + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __MIPS_JZ4740_CLOCK_H__ +#define __MIPS_JZ4740_CLOCK_H__ + +#include <linux/list.h> + +struct jz4740_clock_board_data { + unsigned long ext_rate; + unsigned long rtc_rate; +}; + +extern struct jz4740_clock_board_data jz4740_clock_bdata; + +void jz4740_clock_suspend(void); +void jz4740_clock_resume(void); + +struct clk; + +struct clk_ops { + unsigned long (*get_rate)(struct clk *clk); + unsigned long (*round_rate)(struct clk *clk, unsigned long rate); + int (*set_rate)(struct clk *clk, unsigned long rate); + int (*enable)(struct clk *clk); + int (*disable)(struct clk *clk); + int (*is_enabled)(struct clk *clk); + + int (*set_parent)(struct clk *clk, struct clk *parent); + +}; + +struct clk { + const char *name; + struct clk *parent; + + uint32_t gate_bit; + + const struct clk_ops *ops; + + struct list_head list; + +#ifdef CONFIG_DEBUG_FS + struct dentry *debugfs_entry; + struct dentry *debugfs_parent_entry; +#endif + +}; + +#define JZ4740_CLK_NOT_GATED ((uint32_t)-1) + +int clk_is_enabled(struct clk *clk); + +#ifdef CONFIG_DEBUG_FS +void jz4740_clock_debugfs_init(void); +void jz4740_clock_debugfs_add_clk(struct clk *clk); +void jz4740_clock_debugfs_update_parent(struct clk *clk); +#else +static inline void jz4740_clock_debugfs_init(void) {}; +static inline void jz4740_clock_debugfs_add_clk(struct clk *clk) {}; +static inline void jz4740_clock_debugfs_update_parent(struct clk *clk) {}; +#endif + +#endif diff --git a/kernel/arch/mips/jz4740/gpio.c b/kernel/arch/mips/jz4740/gpio.c new file mode 100644 index 000000000..00b798d2f --- /dev/null +++ b/kernel/arch/mips/jz4740/gpio.c @@ -0,0 +1,521 @@ +/* + * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> + * JZ4740 platform GPIO support + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> + +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/bitops.h> + +#include <linux/debugfs.h> +#include <linux/seq_file.h> + +#include <asm/mach-jz4740/base.h> + +#include "irq.h" + +#define JZ4740_GPIO_BASE_A (32*0) +#define JZ4740_GPIO_BASE_B (32*1) +#define JZ4740_GPIO_BASE_C (32*2) +#define JZ4740_GPIO_BASE_D (32*3) + +#define JZ4740_GPIO_NUM_A 32 +#define JZ4740_GPIO_NUM_B 32 +#define JZ4740_GPIO_NUM_C 31 +#define JZ4740_GPIO_NUM_D 32 + +#define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A) +#define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B) +#define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C) +#define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D) + +#define JZ_REG_GPIO_PIN 0x00 +#define JZ_REG_GPIO_DATA 0x10 +#define JZ_REG_GPIO_DATA_SET 0x14 +#define JZ_REG_GPIO_DATA_CLEAR 0x18 +#define JZ_REG_GPIO_MASK 0x20 +#define JZ_REG_GPIO_MASK_SET 0x24 +#define JZ_REG_GPIO_MASK_CLEAR 0x28 +#define JZ_REG_GPIO_PULL 0x30 +#define JZ_REG_GPIO_PULL_SET 0x34 +#define JZ_REG_GPIO_PULL_CLEAR 0x38 +#define JZ_REG_GPIO_FUNC 0x40 +#define JZ_REG_GPIO_FUNC_SET 0x44 +#define JZ_REG_GPIO_FUNC_CLEAR 0x48 +#define JZ_REG_GPIO_SELECT 0x50 +#define JZ_REG_GPIO_SELECT_SET 0x54 +#define JZ_REG_GPIO_SELECT_CLEAR 0x58 +#define JZ_REG_GPIO_DIRECTION 0x60 +#define JZ_REG_GPIO_DIRECTION_SET 0x64 +#define JZ_REG_GPIO_DIRECTION_CLEAR 0x68 +#define JZ_REG_GPIO_TRIGGER 0x70 +#define JZ_REG_GPIO_TRIGGER_SET 0x74 +#define JZ_REG_GPIO_TRIGGER_CLEAR 0x78 +#define JZ_REG_GPIO_FLAG 0x80 +#define JZ_REG_GPIO_FLAG_CLEAR 0x14 + +#define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f) +#define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg)) +#define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg)) + +struct jz_gpio_chip { + unsigned int irq; + unsigned int irq_base; + uint32_t edge_trigger_both; + + void __iomem *base; + + struct gpio_chip gpio_chip; +}; + +static struct jz_gpio_chip jz4740_gpio_chips[]; + +static inline struct jz_gpio_chip *gpio_to_jz_gpio_chip(unsigned int gpio) +{ + return &jz4740_gpio_chips[gpio >> 5]; +} + +static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *gpio_chip) +{ + return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip); +} + +static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(struct irq_data *data) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); + return gc->private; +} + +static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg) +{ + writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg)); +} + +int jz_gpio_set_function(int gpio, enum jz_gpio_function function) +{ + if (function == JZ_GPIO_FUNC_NONE) { + jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR); + jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR); + jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR); + } else { + jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET); + jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR); + switch (function) { + case JZ_GPIO_FUNC1: + jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR); + break; + case JZ_GPIO_FUNC3: + jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET); + case JZ_GPIO_FUNC2: /* Falltrough */ + jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET); + break; + default: + BUG(); + break; + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(jz_gpio_set_function); + +int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num) +{ + size_t i; + int ret; + + for (i = 0; i < num; ++i, ++request) { + ret = gpio_request(request->gpio, request->name); + if (ret) + goto err; + jz_gpio_set_function(request->gpio, request->function); + } + + return 0; + +err: + for (--request; i > 0; --i, --request) { + gpio_free(request->gpio); + jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE); + } + + return ret; +} +EXPORT_SYMBOL_GPL(jz_gpio_bulk_request); + +void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num) +{ + size_t i; + + for (i = 0; i < num; ++i, ++request) { + gpio_free(request->gpio); + jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE); + } + +} +EXPORT_SYMBOL_GPL(jz_gpio_bulk_free); + +void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num) +{ + size_t i; + + for (i = 0; i < num; ++i, ++request) { + jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE); + jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR); + jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET); + } +} +EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend); + +void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num) +{ + size_t i; + + for (i = 0; i < num; ++i, ++request) + jz_gpio_set_function(request->gpio, request->function); +} +EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume); + +void jz_gpio_enable_pullup(unsigned gpio) +{ + jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR); +} +EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup); + +void jz_gpio_disable_pullup(unsigned gpio) +{ + jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET); +} +EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup); + +static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio) +{ + return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio)); +} + +static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value) +{ + uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET); + reg += !value; + writel(BIT(gpio), reg); +} + +static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, + int value) +{ + writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET)); + jz_gpio_set_value(chip, gpio, value); + + return 0; +} + +static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) +{ + writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR)); + + return 0; +} + +int jz_gpio_port_direction_input(int port, uint32_t mask) +{ + writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR)); + + return 0; +} +EXPORT_SYMBOL(jz_gpio_port_direction_input); + +int jz_gpio_port_direction_output(int port, uint32_t mask) +{ + writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET)); + + return 0; +} +EXPORT_SYMBOL(jz_gpio_port_direction_output); + +void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask) +{ + writel(~value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR)); + writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET)); +} +EXPORT_SYMBOL(jz_gpio_port_set_value); + +uint32_t jz_gpio_port_get_value(int port, uint32_t mask) +{ + uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN)); + + return value & mask; +} +EXPORT_SYMBOL(jz_gpio_port_get_value); + +int gpio_to_irq(unsigned gpio) +{ + return JZ4740_IRQ_GPIO(0) + gpio; +} +EXPORT_SYMBOL_GPL(gpio_to_irq); + +int irq_to_gpio(unsigned irq) +{ + return irq - JZ4740_IRQ_GPIO(0); +} +EXPORT_SYMBOL_GPL(irq_to_gpio); + +#define IRQ_TO_BIT(irq) BIT(irq_to_gpio(irq) & 0x1f) + +static void jz_gpio_check_trigger_both(struct jz_gpio_chip *chip, unsigned int irq) +{ + uint32_t value; + void __iomem *reg; + uint32_t mask = IRQ_TO_BIT(irq); + + if (!(chip->edge_trigger_both & mask)) + return; + + reg = chip->base; + + value = readl(chip->base + JZ_REG_GPIO_PIN); + if (value & mask) + reg += JZ_REG_GPIO_DIRECTION_CLEAR; + else + reg += JZ_REG_GPIO_DIRECTION_SET; + + writel(mask, reg); +} + +static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc) +{ + uint32_t flag; + unsigned int gpio_irq; + struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc); + + flag = readl(chip->base + JZ_REG_GPIO_FLAG); + if (!flag) + return; + + gpio_irq = chip->irq_base + __fls(flag); + + jz_gpio_check_trigger_both(chip, gpio_irq); + + generic_handle_irq(gpio_irq); +}; + +static inline void jz_gpio_set_irq_bit(struct irq_data *data, unsigned int reg) +{ + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); + writel(IRQ_TO_BIT(data->irq), chip->base + reg); +} + +static void jz_gpio_irq_unmask(struct irq_data *data) +{ + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); + + jz_gpio_check_trigger_both(chip, data->irq); + irq_gc_unmask_enable_reg(data); +}; + +/* TODO: Check if function is gpio */ +static unsigned int jz_gpio_irq_startup(struct irq_data *data) +{ + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_SET); + jz_gpio_irq_unmask(data); + return 0; +} + +static void jz_gpio_irq_shutdown(struct irq_data *data) +{ + irq_gc_mask_disable_reg(data); + + /* Set direction to input */ + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_CLEAR); +} + +static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type) +{ + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); + unsigned int irq = data->irq; + + if (flow_type == IRQ_TYPE_EDGE_BOTH) { + uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN); + if (value & IRQ_TO_BIT(irq)) + flow_type = IRQ_TYPE_EDGE_FALLING; + else + flow_type = IRQ_TYPE_EDGE_RISING; + chip->edge_trigger_both |= IRQ_TO_BIT(irq); + } else { + chip->edge_trigger_both &= ~IRQ_TO_BIT(irq); + } + + switch (flow_type) { + case IRQ_TYPE_EDGE_RISING: + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET); + break; + case IRQ_TYPE_EDGE_FALLING: + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET); + break; + case IRQ_TYPE_LEVEL_HIGH: + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR); + break; + case IRQ_TYPE_LEVEL_LOW: + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR); + jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on) +{ + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); + + irq_gc_set_wake(data, on); + irq_set_irq_wake(chip->irq, on); + + return 0; +} + +#define JZ4740_GPIO_CHIP(_bank) { \ + .irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \ + .gpio_chip = { \ + .label = "Bank " # _bank, \ + .owner = THIS_MODULE, \ + .set = jz_gpio_set_value, \ + .get = jz_gpio_get_value, \ + .direction_output = jz_gpio_direction_output, \ + .direction_input = jz_gpio_direction_input, \ + .base = JZ4740_GPIO_BASE_ ## _bank, \ + .ngpio = JZ4740_GPIO_NUM_ ## _bank, \ + }, \ +} + +static struct jz_gpio_chip jz4740_gpio_chips[] = { + JZ4740_GPIO_CHIP(A), + JZ4740_GPIO_CHIP(B), + JZ4740_GPIO_CHIP(C), + JZ4740_GPIO_CHIP(D), +}; + +static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id) +{ + struct irq_chip_generic *gc; + struct irq_chip_type *ct; + + chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100); + + chip->irq = JZ4740_IRQ_INTC_GPIO(id); + irq_set_handler_data(chip->irq, chip); + irq_set_chained_handler(chip->irq, jz_gpio_irq_demux_handler); + + gc = irq_alloc_generic_chip(chip->gpio_chip.label, 1, chip->irq_base, + chip->base, handle_level_irq); + + gc->wake_enabled = IRQ_MSK(chip->gpio_chip.ngpio); + gc->private = chip; + + ct = gc->chip_types; + ct->regs.enable = JZ_REG_GPIO_MASK_CLEAR; + ct->regs.disable = JZ_REG_GPIO_MASK_SET; + ct->regs.ack = JZ_REG_GPIO_FLAG_CLEAR; + + ct->chip.name = "GPIO"; + ct->chip.irq_mask = irq_gc_mask_disable_reg; + ct->chip.irq_unmask = jz_gpio_irq_unmask; + ct->chip.irq_ack = irq_gc_ack_set_bit; + ct->chip.irq_suspend = jz4740_irq_suspend; + ct->chip.irq_resume = jz4740_irq_resume; + ct->chip.irq_startup = jz_gpio_irq_startup; + ct->chip.irq_shutdown = jz_gpio_irq_shutdown; + ct->chip.irq_set_type = jz_gpio_irq_set_type; + ct->chip.irq_set_wake = jz_gpio_irq_set_wake; + ct->chip.flags = IRQCHIP_SET_TYPE_MASKED; + + irq_setup_generic_chip(gc, IRQ_MSK(chip->gpio_chip.ngpio), + IRQ_GC_INIT_NESTED_LOCK, 0, IRQ_NOPROBE | IRQ_LEVEL); + + gpiochip_add(&chip->gpio_chip); +} + +static int __init jz4740_gpio_init(void) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i) + jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i); + + printk(KERN_INFO "JZ4740 GPIO initialized\n"); + + return 0; +} +arch_initcall(jz4740_gpio_init); + +#ifdef CONFIG_DEBUG_FS + +static inline void gpio_seq_reg(struct seq_file *s, struct jz_gpio_chip *chip, + const char *name, unsigned int reg) +{ + seq_printf(s, "\t%s: %08x\n", name, readl(chip->base + reg)); +} + +static int gpio_regs_show(struct seq_file *s, void *unused) +{ + struct jz_gpio_chip *chip = jz4740_gpio_chips; + int i; + + for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i, ++chip) { + seq_printf(s, "==GPIO %d==\n", i); + gpio_seq_reg(s, chip, "Pin", JZ_REG_GPIO_PIN); + gpio_seq_reg(s, chip, "Data", JZ_REG_GPIO_DATA); + gpio_seq_reg(s, chip, "Mask", JZ_REG_GPIO_MASK); + gpio_seq_reg(s, chip, "Pull", JZ_REG_GPIO_PULL); + gpio_seq_reg(s, chip, "Func", JZ_REG_GPIO_FUNC); + gpio_seq_reg(s, chip, "Select", JZ_REG_GPIO_SELECT); + gpio_seq_reg(s, chip, "Direction", JZ_REG_GPIO_DIRECTION); + gpio_seq_reg(s, chip, "Trigger", JZ_REG_GPIO_TRIGGER); + gpio_seq_reg(s, chip, "Flag", JZ_REG_GPIO_FLAG); + } + + return 0; +} + +static int gpio_regs_open(struct inode *inode, struct file *file) +{ + return single_open(file, gpio_regs_show, NULL); +} + +static const struct file_operations gpio_regs_operations = { + .open = gpio_regs_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init gpio_debugfs_init(void) +{ + (void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO, + NULL, NULL, &gpio_regs_operations); + return 0; +} +subsys_initcall(gpio_debugfs_init); + +#endif diff --git a/kernel/arch/mips/jz4740/irq.c b/kernel/arch/mips/jz4740/irq.c new file mode 100644 index 000000000..97206b3de --- /dev/null +++ b/kernel/arch/mips/jz4740/irq.c @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> + * JZ4740 platform IRQ support + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/timex.h> +#include <linux/slab.h> +#include <linux/delay.h> + +#include <linux/debugfs.h> +#include <linux/seq_file.h> + +#include <asm/io.h> +#include <asm/mipsregs.h> +#include <asm/irq_cpu.h> + +#include <asm/mach-jz4740/base.h> +#include <asm/mach-jz4740/irq.h> + +#include "irq.h" + +static void __iomem *jz_intc_base; + +#define JZ_REG_INTC_STATUS 0x00 +#define JZ_REG_INTC_MASK 0x04 +#define JZ_REG_INTC_SET_MASK 0x08 +#define JZ_REG_INTC_CLEAR_MASK 0x0c +#define JZ_REG_INTC_PENDING 0x10 + +static irqreturn_t jz4740_cascade(int irq, void *data) +{ + uint32_t irq_reg; + + irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING); + + if (irq_reg) + generic_handle_irq(__fls(irq_reg) + JZ4740_IRQ_BASE); + + return IRQ_HANDLED; +} + +static void jz4740_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask) +{ + struct irq_chip_regs *regs = &gc->chip_types->regs; + + writel(mask, gc->reg_base + regs->enable); + writel(~mask, gc->reg_base + regs->disable); +} + +void jz4740_irq_suspend(struct irq_data *data) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); + jz4740_irq_set_mask(gc, gc->wake_active); +} + +void jz4740_irq_resume(struct irq_data *data) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); + jz4740_irq_set_mask(gc, gc->mask_cache); +} + +static struct irqaction jz4740_cascade_action = { + .handler = jz4740_cascade, + .name = "JZ4740 cascade interrupt", +}; + +void __init arch_init_irq(void) +{ + struct irq_chip_generic *gc; + struct irq_chip_type *ct; + + mips_cpu_irq_init(); + + jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14); + + /* Mask all irqs */ + writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK); + + gc = irq_alloc_generic_chip("INTC", 1, JZ4740_IRQ_BASE, jz_intc_base, + handle_level_irq); + + gc->wake_enabled = IRQ_MSK(32); + + ct = gc->chip_types; + ct->regs.enable = JZ_REG_INTC_CLEAR_MASK; + ct->regs.disable = JZ_REG_INTC_SET_MASK; + ct->chip.irq_unmask = irq_gc_unmask_enable_reg; + ct->chip.irq_mask = irq_gc_mask_disable_reg; + ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; + ct->chip.irq_set_wake = irq_gc_set_wake; + ct->chip.irq_suspend = jz4740_irq_suspend; + ct->chip.irq_resume = jz4740_irq_resume; + + irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0, IRQ_NOPROBE | IRQ_LEVEL); + + setup_irq(2, &jz4740_cascade_action); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; + if (pending & STATUSF_IP2) + do_IRQ(2); + else if (pending & STATUSF_IP3) + do_IRQ(3); + else + spurious_interrupt(); +} + +#ifdef CONFIG_DEBUG_FS + +static inline void intc_seq_reg(struct seq_file *s, const char *name, + unsigned int reg) +{ + seq_printf(s, "%s:\t\t%08x\n", name, readl(jz_intc_base + reg)); +} + +static int intc_regs_show(struct seq_file *s, void *unused) +{ + intc_seq_reg(s, "Status", JZ_REG_INTC_STATUS); + intc_seq_reg(s, "Mask", JZ_REG_INTC_MASK); + intc_seq_reg(s, "Pending", JZ_REG_INTC_PENDING); + + return 0; +} + +static int intc_regs_open(struct inode *inode, struct file *file) +{ + return single_open(file, intc_regs_show, NULL); +} + +static const struct file_operations intc_regs_operations = { + .open = intc_regs_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init intc_debugfs_init(void) +{ + (void) debugfs_create_file("jz_regs_intc", S_IFREG | S_IRUGO, + NULL, NULL, &intc_regs_operations); + return 0; +} +subsys_initcall(intc_debugfs_init); + +#endif diff --git a/kernel/arch/mips/jz4740/irq.h b/kernel/arch/mips/jz4740/irq.h new file mode 100644 index 000000000..0f48720b5 --- /dev/null +++ b/kernel/arch/mips/jz4740/irq.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __MIPS_JZ4740_IRQ_H__ +#define __MIPS_JZ4740_IRQ_H__ + +#include <linux/irq.h> + +extern void jz4740_irq_suspend(struct irq_data *data); +extern void jz4740_irq_resume(struct irq_data *data); + +#endif diff --git a/kernel/arch/mips/jz4740/platform.c b/kernel/arch/mips/jz4740/platform.c new file mode 100644 index 000000000..0b12f273c --- /dev/null +++ b/kernel/arch/mips/jz4740/platform.c @@ -0,0 +1,359 @@ +/* + * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> + * JZ4740 platform devices + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/resource.h> + +#include <linux/dma-mapping.h> + +#include <linux/usb/musb.h> + +#include <asm/mach-jz4740/platform.h> +#include <asm/mach-jz4740/base.h> +#include <asm/mach-jz4740/irq.h> + +#include <linux/serial_core.h> +#include <linux/serial_8250.h> + +#include "serial.h" +#include "clock.h" + +/* OHCI controller */ +static struct resource jz4740_usb_ohci_resources[] = { + { + .start = JZ4740_UHC_BASE_ADDR, + .end = JZ4740_UHC_BASE_ADDR + 0x1000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = JZ4740_IRQ_UHC, + .end = JZ4740_IRQ_UHC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device jz4740_usb_ohci_device = { + .name = "jz4740-ohci", + .id = -1, + .dev = { + .dma_mask = &jz4740_usb_ohci_device.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(jz4740_usb_ohci_resources), + .resource = jz4740_usb_ohci_resources, +}; + +/* USB Device Controller */ +struct platform_device jz4740_udc_xceiv_device = { + .name = "usb_phy_generic", + .id = 0, +}; + +static struct resource jz4740_udc_resources[] = { + [0] = { + .start = JZ4740_UDC_BASE_ADDR, + .end = JZ4740_UDC_BASE_ADDR + 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = JZ4740_IRQ_UDC, + .end = JZ4740_IRQ_UDC, + .flags = IORESOURCE_IRQ, + .name = "mc", + }, +}; + +struct platform_device jz4740_udc_device = { + .name = "musb-jz4740", + .id = -1, + .dev = { + .dma_mask = &jz4740_udc_device.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(jz4740_udc_resources), + .resource = jz4740_udc_resources, +}; + +/* MMC/SD controller */ +static struct resource jz4740_mmc_resources[] = { + { + .start = JZ4740_MSC_BASE_ADDR, + .end = JZ4740_MSC_BASE_ADDR + 0x1000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = JZ4740_IRQ_MSC, + .end = JZ4740_IRQ_MSC, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device jz4740_mmc_device = { + .name = "jz4740-mmc", + .id = 0, + .dev = { + .dma_mask = &jz4740_mmc_device.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(jz4740_mmc_resources), + .resource = jz4740_mmc_resources, +}; + +/* RTC controller */ +static struct resource jz4740_rtc_resources[] = { + { + .start = JZ4740_RTC_BASE_ADDR, + .end = JZ4740_RTC_BASE_ADDR + 0x38 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = JZ4740_IRQ_RTC, + .end = JZ4740_IRQ_RTC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device jz4740_rtc_device = { + .name = "jz4740-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(jz4740_rtc_resources), + .resource = jz4740_rtc_resources, +}; + +/* I2C controller */ +static struct resource jz4740_i2c_resources[] = { + { + .start = JZ4740_I2C_BASE_ADDR, + .end = JZ4740_I2C_BASE_ADDR + 0x1000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = JZ4740_IRQ_I2C, + .end = JZ4740_IRQ_I2C, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device jz4740_i2c_device = { + .name = "jz4740-i2c", + .id = 0, + .num_resources = ARRAY_SIZE(jz4740_i2c_resources), + .resource = jz4740_i2c_resources, +}; + +/* NAND controller */ +static struct resource jz4740_nand_resources[] = { + { + .name = "mmio", + .start = JZ4740_EMC_BASE_ADDR, + .end = JZ4740_EMC_BASE_ADDR + 0x1000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "bank1", + .start = 0x18000000, + .end = 0x180C0000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "bank2", + .start = 0x14000000, + .end = 0x140C0000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "bank3", + .start = 0x0C000000, + .end = 0x0C0C0000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "bank4", + .start = 0x08000000, + .end = 0x080C0000 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device jz4740_nand_device = { + .name = "jz4740-nand", + .num_resources = ARRAY_SIZE(jz4740_nand_resources), + .resource = jz4740_nand_resources, +}; + +/* LCD controller */ +static struct resource jz4740_framebuffer_resources[] = { + { + .start = JZ4740_LCD_BASE_ADDR, + .end = JZ4740_LCD_BASE_ADDR + 0x1000 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device jz4740_framebuffer_device = { + .name = "jz4740-fb", + .id = -1, + .num_resources = ARRAY_SIZE(jz4740_framebuffer_resources), + .resource = jz4740_framebuffer_resources, + .dev = { + .dma_mask = &jz4740_framebuffer_device.dev.coherent_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +/* I2S controller */ +static struct resource jz4740_i2s_resources[] = { + { + .start = JZ4740_AIC_BASE_ADDR, + .end = JZ4740_AIC_BASE_ADDR + 0x38 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device jz4740_i2s_device = { + .name = "jz4740-i2s", + .id = -1, + .num_resources = ARRAY_SIZE(jz4740_i2s_resources), + .resource = jz4740_i2s_resources, +}; + +/* PCM */ +struct platform_device jz4740_pcm_device = { + .name = "jz4740-pcm-audio", + .id = -1, +}; + +/* Codec */ +static struct resource jz4740_codec_resources[] = { + { + .start = JZ4740_AIC_BASE_ADDR + 0x80, + .end = JZ4740_AIC_BASE_ADDR + 0x88 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device jz4740_codec_device = { + .name = "jz4740-codec", + .id = -1, + .num_resources = ARRAY_SIZE(jz4740_codec_resources), + .resource = jz4740_codec_resources, +}; + +/* ADC controller */ +static struct resource jz4740_adc_resources[] = { + { + .start = JZ4740_SADC_BASE_ADDR, + .end = JZ4740_SADC_BASE_ADDR + 0x30, + .flags = IORESOURCE_MEM, + }, + { + .start = JZ4740_IRQ_SADC, + .end = JZ4740_IRQ_SADC, + .flags = IORESOURCE_IRQ, + }, + { + .start = JZ4740_IRQ_ADC_BASE, + .end = JZ4740_IRQ_ADC_BASE, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device jz4740_adc_device = { + .name = "jz4740-adc", + .id = -1, + .num_resources = ARRAY_SIZE(jz4740_adc_resources), + .resource = jz4740_adc_resources, +}; + +/* Serial */ +#define JZ4740_UART_DATA(_id) \ + { \ + .flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE, \ + .iotype = UPIO_MEM, \ + .regshift = 2, \ + .serial_out = jz4740_serial_out, \ + .type = PORT_16550, \ + .mapbase = JZ4740_UART ## _id ## _BASE_ADDR, \ + .irq = JZ4740_IRQ_UART ## _id, \ + } + +static struct plat_serial8250_port jz4740_uart_data[] = { + JZ4740_UART_DATA(0), + JZ4740_UART_DATA(1), + {}, +}; + +static struct platform_device jz4740_uart_device = { + .name = "serial8250", + .id = 0, + .dev = { + .platform_data = jz4740_uart_data, + }, +}; + +void jz4740_serial_device_register(void) +{ + struct plat_serial8250_port *p; + + for (p = jz4740_uart_data; p->flags != 0; ++p) + p->uartclk = jz4740_clock_bdata.ext_rate; + + platform_device_register(&jz4740_uart_device); +} + +/* Watchdog */ +static struct resource jz4740_wdt_resources[] = { + { + .start = JZ4740_WDT_BASE_ADDR, + .end = JZ4740_WDT_BASE_ADDR + 0x10 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device jz4740_wdt_device = { + .name = "jz4740-wdt", + .id = -1, + .num_resources = ARRAY_SIZE(jz4740_wdt_resources), + .resource = jz4740_wdt_resources, +}; + +/* PWM */ +struct platform_device jz4740_pwm_device = { + .name = "jz4740-pwm", + .id = -1, +}; + +/* DMA */ +static struct resource jz4740_dma_resources[] = { + { + .start = JZ4740_DMAC_BASE_ADDR, + .end = JZ4740_DMAC_BASE_ADDR + 0x400 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = JZ4740_IRQ_DMAC, + .end = JZ4740_IRQ_DMAC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device jz4740_dma_device = { + .name = "jz4740-dma", + .id = -1, + .num_resources = ARRAY_SIZE(jz4740_dma_resources), + .resource = jz4740_dma_resources, +}; diff --git a/kernel/arch/mips/jz4740/pm.c b/kernel/arch/mips/jz4740/pm.c new file mode 100644 index 000000000..d8e213010 --- /dev/null +++ b/kernel/arch/mips/jz4740/pm.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> + * JZ4740 SoC power management support + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include <linux/init.h> +#include <linux/pm.h> +#include <linux/delay.h> +#include <linux/suspend.h> + +#include <asm/mach-jz4740/clock.h> + +#include "clock.h" + +static int jz4740_pm_enter(suspend_state_t state) +{ + jz4740_clock_suspend(); + + jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_SLEEP); + + __asm__(".set\tmips3\n\t" + "wait\n\t" + ".set\tmips0"); + + jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_IDLE); + + jz4740_clock_resume(); + + return 0; +} + +static const struct platform_suspend_ops jz4740_pm_ops = { + .valid = suspend_valid_only_mem, + .enter = jz4740_pm_enter, +}; + +static int __init jz4740_pm_init(void) +{ + suspend_set_ops(&jz4740_pm_ops); + return 0; + +} +late_initcall(jz4740_pm_init); diff --git a/kernel/arch/mips/jz4740/prom.c b/kernel/arch/mips/jz4740/prom.c new file mode 100644 index 000000000..5a93f3815 --- /dev/null +++ b/kernel/arch/mips/jz4740/prom.c @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> + * JZ4740 SoC prom code + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/string.h> + +#include <linux/serial_reg.h> + +#include <asm/bootinfo.h> +#include <asm/mach-jz4740/base.h> + +static __init void jz4740_init_cmdline(int argc, char *argv[]) +{ + unsigned int count = COMMAND_LINE_SIZE - 1; + int i; + char *dst = &(arcs_cmdline[0]); + char *src; + + for (i = 1; i < argc && count; ++i) { + src = argv[i]; + while (*src && count) { + *dst++ = *src++; + --count; + } + *dst++ = ' '; + } + if (i > 1) + --dst; + + *dst = 0; +} + +void __init prom_init(void) +{ + jz4740_init_cmdline((int)fw_arg0, (char **)fw_arg1); + mips_machtype = MACH_INGENIC_JZ4740; +} + +void __init prom_free_prom_memory(void) +{ +} + +#define UART_REG(_reg) ((void __iomem *)CKSEG1ADDR(JZ4740_UART0_BASE_ADDR + (_reg << 2))) + +void prom_putchar(char c) +{ + uint8_t lsr; + + do { + lsr = readb(UART_REG(UART_LSR)); + } while ((lsr & UART_LSR_TEMT) == 0); + + writeb(c, UART_REG(UART_TX)); +} diff --git a/kernel/arch/mips/jz4740/reset.c b/kernel/arch/mips/jz4740/reset.c new file mode 100644 index 000000000..b6c6343d2 --- /dev/null +++ b/kernel/arch/mips/jz4740/reset.c @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/pm.h> + +#include <asm/reboot.h> + +#include <asm/mach-jz4740/base.h> +#include <asm/mach-jz4740/timer.h> + +#include "reset.h" +#include "clock.h" + +static void jz4740_halt(void) +{ + while (1) { + __asm__(".set push;\n" + ".set mips3;\n" + "wait;\n" + ".set pop;\n" + ); + } +} + +#define JZ_REG_WDT_DATA 0x00 +#define JZ_REG_WDT_COUNTER_ENABLE 0x04 +#define JZ_REG_WDT_COUNTER 0x08 +#define JZ_REG_WDT_CTRL 0x0c + +static void jz4740_restart(char *command) +{ + void __iomem *wdt_base = ioremap(JZ4740_WDT_BASE_ADDR, 0x0f); + + jz4740_timer_enable_watchdog(); + + writeb(0, wdt_base + JZ_REG_WDT_COUNTER_ENABLE); + + writew(0, wdt_base + JZ_REG_WDT_COUNTER); + writew(0, wdt_base + JZ_REG_WDT_DATA); + writew(BIT(2), wdt_base + JZ_REG_WDT_CTRL); + + writeb(1, wdt_base + JZ_REG_WDT_COUNTER_ENABLE); + jz4740_halt(); +} + +#define JZ_REG_RTC_CTRL 0x00 +#define JZ_REG_RTC_HIBERNATE 0x20 +#define JZ_REG_RTC_WAKEUP_FILTER 0x24 +#define JZ_REG_RTC_RESET_COUNTER 0x28 + +#define JZ_RTC_CTRL_WRDY BIT(7) +#define JZ_RTC_WAKEUP_FILTER_MASK 0x0000FFE0 +#define JZ_RTC_RESET_COUNTER_MASK 0x00000FE0 + +static inline void jz4740_rtc_wait_ready(void __iomem *rtc_base) +{ + uint32_t ctrl; + + do { + ctrl = readl(rtc_base + JZ_REG_RTC_CTRL); + } while (!(ctrl & JZ_RTC_CTRL_WRDY)); +} + +static void jz4740_power_off(void) +{ + void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x38); + unsigned long wakeup_filter_ticks; + unsigned long reset_counter_ticks; + + /* + * Set minimum wakeup pin assertion time: 100 ms. + * Range is 0 to 2 sec if RTC is clocked at 32 kHz. + */ + wakeup_filter_ticks = (100 * jz4740_clock_bdata.rtc_rate) / 1000; + if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK) + wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK; + else + wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK; + jz4740_rtc_wait_ready(rtc_base); + writel(wakeup_filter_ticks, rtc_base + JZ_REG_RTC_WAKEUP_FILTER); + + /* + * Set reset pin low-level assertion time after wakeup: 60 ms. + * Range is 0 to 125 ms if RTC is clocked at 32 kHz. + */ + reset_counter_ticks = (60 * jz4740_clock_bdata.rtc_rate) / 1000; + if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK) + reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK; + else + reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK; + jz4740_rtc_wait_ready(rtc_base); + writel(reset_counter_ticks, rtc_base + JZ_REG_RTC_RESET_COUNTER); + + jz4740_rtc_wait_ready(rtc_base); + writel(1, rtc_base + JZ_REG_RTC_HIBERNATE); + + jz4740_halt(); +} + +void jz4740_reset_init(void) +{ + _machine_restart = jz4740_restart; + _machine_halt = jz4740_halt; + pm_power_off = jz4740_power_off; +} diff --git a/kernel/arch/mips/jz4740/reset.h b/kernel/arch/mips/jz4740/reset.h new file mode 100644 index 000000000..5202ab4ad --- /dev/null +++ b/kernel/arch/mips/jz4740/reset.h @@ -0,0 +1,6 @@ +#ifndef __MIPS_JZ4740_RESET_H__ +#define __MIPS_JZ4740_RESET_H__ + +extern void jz4740_reset_init(void); + +#endif diff --git a/kernel/arch/mips/jz4740/serial.c b/kernel/arch/mips/jz4740/serial.c new file mode 100644 index 000000000..d23de4582 --- /dev/null +++ b/kernel/arch/mips/jz4740/serial.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> + * JZ4740 serial support + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include <linux/io.h> +#include <linux/serial_core.h> +#include <linux/serial_reg.h> + +void jz4740_serial_out(struct uart_port *p, int offset, int value) +{ + switch (offset) { + case UART_FCR: + value |= 0x10; /* Enable uart module */ + break; + case UART_IER: + value |= (value & 0x4) << 2; + break; + default: + break; + } + writeb(value, p->membase + (offset << p->regshift)); +} diff --git a/kernel/arch/mips/jz4740/serial.h b/kernel/arch/mips/jz4740/serial.h new file mode 100644 index 000000000..8eb715bb1 --- /dev/null +++ b/kernel/arch/mips/jz4740/serial.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> + * JZ4740 serial support + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __MIPS_JZ4740_SERIAL_H__ +#define __MIPS_JZ4740_SERIAL_H__ + +struct uart_port; + +void jz4740_serial_out(struct uart_port *p, int offset, int value); + +#endif diff --git a/kernel/arch/mips/jz4740/setup.c b/kernel/arch/mips/jz4740/setup.c new file mode 100644 index 000000000..ef796f97b --- /dev/null +++ b/kernel/arch/mips/jz4740/setup.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> + * Copyright (C) 2011, Maarten ter Huurne <maarten@treewalker.org> + * JZ4740 setup code + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> + +#include <asm/bootinfo.h> + +#include <asm/mach-jz4740/base.h> + +#include "reset.h" + + +#define JZ4740_EMC_SDRAM_CTRL 0x80 + + +static void __init jz4740_detect_mem(void) +{ + void __iomem *jz_emc_base; + u32 ctrl, bus, bank, rows, cols; + phys_addr_t size; + + jz_emc_base = ioremap(JZ4740_EMC_BASE_ADDR, 0x100); + ctrl = readl(jz_emc_base + JZ4740_EMC_SDRAM_CTRL); + bus = 2 - ((ctrl >> 31) & 1); + bank = 1 + ((ctrl >> 19) & 1); + cols = 8 + ((ctrl >> 26) & 7); + rows = 11 + ((ctrl >> 20) & 3); + printk(KERN_DEBUG + "SDRAM preconfigured: bus:%u bank:%u rows:%u cols:%u\n", + bus, bank, rows, cols); + iounmap(jz_emc_base); + + size = 1 << (bus + bank + cols + rows); + add_memory_region(0, size, BOOT_MEM_RAM); +} + +void __init plat_mem_setup(void) +{ + jz4740_reset_init(); + jz4740_detect_mem(); +} + +const char *get_system_type(void) +{ + return "JZ4740"; +} diff --git a/kernel/arch/mips/jz4740/time.c b/kernel/arch/mips/jz4740/time.c new file mode 100644 index 000000000..72b0cecbc --- /dev/null +++ b/kernel/arch/mips/jz4740/time.c @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> + * JZ4740 platform time support + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/time.h> + +#include <linux/clockchips.h> +#include <linux/sched_clock.h> + +#include <asm/mach-jz4740/irq.h> +#include <asm/mach-jz4740/timer.h> +#include <asm/time.h> + +#include "clock.h" + +#define TIMER_CLOCKEVENT 0 +#define TIMER_CLOCKSOURCE 1 + +static uint16_t jz4740_jiffies_per_tick; + +static cycle_t jz4740_clocksource_read(struct clocksource *cs) +{ + return jz4740_timer_get_count(TIMER_CLOCKSOURCE); +} + +static struct clocksource jz4740_clocksource = { + .name = "jz4740-timer", + .rating = 200, + .read = jz4740_clocksource_read, + .mask = CLOCKSOURCE_MASK(16), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static u64 notrace jz4740_read_sched_clock(void) +{ + return jz4740_timer_get_count(TIMER_CLOCKSOURCE); +} + +static irqreturn_t jz4740_clockevent_irq(int irq, void *devid) +{ + struct clock_event_device *cd = devid; + + jz4740_timer_ack_full(TIMER_CLOCKEVENT); + + if (cd->mode != CLOCK_EVT_MODE_PERIODIC) + jz4740_timer_disable(TIMER_CLOCKEVENT); + + cd->event_handler(cd); + + return IRQ_HANDLED; +} + +static void jz4740_clockevent_set_mode(enum clock_event_mode mode, + struct clock_event_device *cd) +{ + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + jz4740_timer_set_count(TIMER_CLOCKEVENT, 0); + jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick); + case CLOCK_EVT_MODE_RESUME: + jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT); + jz4740_timer_enable(TIMER_CLOCKEVENT); + break; + case CLOCK_EVT_MODE_ONESHOT: + case CLOCK_EVT_MODE_SHUTDOWN: + jz4740_timer_disable(TIMER_CLOCKEVENT); + break; + default: + break; + } +} + +static int jz4740_clockevent_set_next(unsigned long evt, + struct clock_event_device *cd) +{ + jz4740_timer_set_count(TIMER_CLOCKEVENT, 0); + jz4740_timer_set_period(TIMER_CLOCKEVENT, evt); + jz4740_timer_enable(TIMER_CLOCKEVENT); + + return 0; +} + +static struct clock_event_device jz4740_clockevent = { + .name = "jz4740-timer", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_next_event = jz4740_clockevent_set_next, + .set_mode = jz4740_clockevent_set_mode, + .rating = 200, + .irq = JZ4740_IRQ_TCU0, +}; + +static struct irqaction timer_irqaction = { + .handler = jz4740_clockevent_irq, + .flags = IRQF_PERCPU | IRQF_TIMER, + .name = "jz4740-timerirq", + .dev_id = &jz4740_clockevent, +}; + +void __init plat_time_init(void) +{ + int ret; + uint32_t clk_rate; + uint16_t ctrl; + + jz4740_timer_init(); + + clk_rate = jz4740_clock_bdata.ext_rate >> 4; + jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ); + + clockevent_set_clock(&jz4740_clockevent, clk_rate); + jz4740_clockevent.min_delta_ns = clockevent_delta2ns(100, &jz4740_clockevent); + jz4740_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &jz4740_clockevent); + jz4740_clockevent.cpumask = cpumask_of(0); + + clockevents_register_device(&jz4740_clockevent); + + ret = clocksource_register_hz(&jz4740_clocksource, clk_rate); + + if (ret) + printk(KERN_ERR "Failed to register clocksource: %d\n", ret); + + sched_clock_register(jz4740_read_sched_clock, 16, clk_rate); + + setup_irq(JZ4740_IRQ_TCU0, &timer_irqaction); + + ctrl = JZ_TIMER_CTRL_PRESCALE_16 | JZ_TIMER_CTRL_SRC_EXT; + + jz4740_timer_set_ctrl(TIMER_CLOCKEVENT, ctrl); + jz4740_timer_set_ctrl(TIMER_CLOCKSOURCE, ctrl); + + jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick); + jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT); + + jz4740_timer_set_period(TIMER_CLOCKSOURCE, 0xffff); + + jz4740_timer_enable(TIMER_CLOCKEVENT); + jz4740_timer_enable(TIMER_CLOCKSOURCE); +} diff --git a/kernel/arch/mips/jz4740/timer.c b/kernel/arch/mips/jz4740/timer.c new file mode 100644 index 000000000..499246178 --- /dev/null +++ b/kernel/arch/mips/jz4740/timer.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> + * JZ4740 platform timer support + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> + +#include <asm/mach-jz4740/base.h> +#include <asm/mach-jz4740/timer.h> + +void __iomem *jz4740_timer_base; +EXPORT_SYMBOL_GPL(jz4740_timer_base); + +void jz4740_timer_enable_watchdog(void) +{ + writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); +} +EXPORT_SYMBOL_GPL(jz4740_timer_enable_watchdog); + +void jz4740_timer_disable_watchdog(void) +{ + writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); +} +EXPORT_SYMBOL_GPL(jz4740_timer_disable_watchdog); + +void __init jz4740_timer_init(void) +{ + jz4740_timer_base = ioremap(JZ4740_TCU_BASE_ADDR, 0x100); + + if (!jz4740_timer_base) + panic("Failed to ioremap timer registers"); + + /* Disable all timer clocks except for those used as system timers */ + writel(0x000100fc, jz4740_timer_base + JZ_REG_TIMER_STOP_SET); + + /* Timer irqs are unmasked by default, mask them */ + writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET); +} |