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-rw-r--r--kernel/arch/ia64/include/asm/sn/acpi.h15
-rw-r--r--kernel/arch/ia64/include/asm/sn/addrs.h299
-rw-r--r--kernel/arch/ia64/include/asm/sn/arch.h86
-rw-r--r--kernel/arch/ia64/include/asm/sn/bte.h234
-rw-r--r--kernel/arch/ia64/include/asm/sn/clksupport.h28
-rw-r--r--kernel/arch/ia64/include/asm/sn/geo.h132
-rw-r--r--kernel/arch/ia64/include/asm/sn/intr.h68
-rw-r--r--kernel/arch/ia64/include/asm/sn/io.h274
-rw-r--r--kernel/arch/ia64/include/asm/sn/ioc3.h241
-rw-r--r--kernel/arch/ia64/include/asm/sn/klconfig.h246
-rw-r--r--kernel/arch/ia64/include/asm/sn/l1.h51
-rw-r--r--kernel/arch/ia64/include/asm/sn/leds.h33
-rw-r--r--kernel/arch/ia64/include/asm/sn/module.h127
-rw-r--r--kernel/arch/ia64/include/asm/sn/mspec.h59
-rw-r--r--kernel/arch/ia64/include/asm/sn/nodepda.h82
-rw-r--r--kernel/arch/ia64/include/asm/sn/pcibr_provider.h150
-rw-r--r--kernel/arch/ia64/include/asm/sn/pcibus_provider_defs.h68
-rw-r--r--kernel/arch/ia64/include/asm/sn/pcidev.h85
-rw-r--r--kernel/arch/ia64/include/asm/sn/pda.h68
-rw-r--r--kernel/arch/ia64/include/asm/sn/pic.h261
-rw-r--r--kernel/arch/ia64/include/asm/sn/rw_mmr.h28
-rw-r--r--kernel/arch/ia64/include/asm/sn/shub_mmr.h502
-rw-r--r--kernel/arch/ia64/include/asm/sn/shubio.h3358
-rw-r--r--kernel/arch/ia64/include/asm/sn/simulator.h25
-rw-r--r--kernel/arch/ia64/include/asm/sn/sn2/sn_hwperf.h242
-rw-r--r--kernel/arch/ia64/include/asm/sn/sn_cpuid.h132
-rw-r--r--kernel/arch/ia64/include/asm/sn/sn_feature_sets.h58
-rw-r--r--kernel/arch/ia64/include/asm/sn/sn_sal.h1233
-rw-r--r--kernel/arch/ia64/include/asm/sn/tioca.h596
-rw-r--r--kernel/arch/ia64/include/asm/sn/tioca_provider.h207
-rw-r--r--kernel/arch/ia64/include/asm/sn/tioce.h760
-rw-r--r--kernel/arch/ia64/include/asm/sn/tioce_provider.h63
-rw-r--r--kernel/arch/ia64/include/asm/sn/tiocp.h257
-rw-r--r--kernel/arch/ia64/include/asm/sn/tiocx.h72
-rw-r--r--kernel/arch/ia64/include/asm/sn/types.h26
35 files changed, 10166 insertions, 0 deletions
diff --git a/kernel/arch/ia64/include/asm/sn/acpi.h b/kernel/arch/ia64/include/asm/sn/acpi.h
new file mode 100644
index 000000000..fd480db25
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/acpi.h
@@ -0,0 +1,15 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_ACPI_H
+#define _ASM_IA64_SN_ACPI_H
+
+extern int sn_acpi_rev;
+#define SN_ACPI_BASE_SUPPORT() (sn_acpi_rev >= 0x20101)
+
+#endif /* _ASM_IA64_SN_ACPI_H */
diff --git a/kernel/arch/ia64/include/asm/sn/addrs.h b/kernel/arch/ia64/include/asm/sn/addrs.h
new file mode 100644
index 000000000..e715c794b
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/addrs.h
@@ -0,0 +1,299 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1992-1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_ADDRS_H
+#define _ASM_IA64_SN_ADDRS_H
+
+#include <asm/percpu.h>
+#include <asm/sn/types.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/pda.h>
+
+/*
+ * Memory/SHUB Address Format:
+ * +-+---------+--+--------------+
+ * |0| NASID |AS| NodeOffset |
+ * +-+---------+--+--------------+
+ *
+ * NASID: (low NASID bit is 0) Memory and SHUB MMRs
+ * AS: 2-bit Address Space Identifier. Used only if low NASID bit is 0
+ * 00: Local Resources and MMR space
+ * Top bit of NodeOffset
+ * 0: Local resources space
+ * node id:
+ * 0: IA64/NT compatibility space
+ * 2: Local MMR Space
+ * 4: Local memory, regardless of local node id
+ * 1: Global MMR space
+ * 01: GET space.
+ * 10: AMO space.
+ * 11: Cacheable memory space.
+ *
+ * NodeOffset: byte offset
+ *
+ *
+ * TIO address format:
+ * +-+----------+--+--------------+
+ * |0| NASID |AS| Nodeoffset |
+ * +-+----------+--+--------------+
+ *
+ * NASID: (low NASID bit is 1) TIO
+ * AS: 2-bit Chiplet Identifier
+ * 00: TIO LB (Indicates TIO MMR access.)
+ * 01: TIO ICE (indicates coretalk space access.)
+ *
+ * NodeOffset: top bit must be set.
+ *
+ *
+ * Note that in both of the above address formats, the low
+ * NASID bit indicates if the reference is to the SHUB or TIO MMRs.
+ */
+
+
+/*
+ * Define basic shift & mask constants for manipulating NASIDs and AS values.
+ */
+#define NASID_BITMASK (sn_hub_info->nasid_bitmask)
+#define NASID_SHIFT (sn_hub_info->nasid_shift)
+#define AS_SHIFT (sn_hub_info->as_shift)
+#define AS_BITMASK 0x3UL
+
+#define NASID_MASK ((u64)NASID_BITMASK << NASID_SHIFT)
+#define AS_MASK ((u64)AS_BITMASK << AS_SHIFT)
+
+
+/*
+ * AS values. These are the same on both SHUB1 & SHUB2.
+ */
+#define AS_GET_VAL 1UL
+#define AS_AMO_VAL 2UL
+#define AS_CAC_VAL 3UL
+#define AS_GET_SPACE (AS_GET_VAL << AS_SHIFT)
+#define AS_AMO_SPACE (AS_AMO_VAL << AS_SHIFT)
+#define AS_CAC_SPACE (AS_CAC_VAL << AS_SHIFT)
+
+
+/*
+ * Virtual Mode Local & Global MMR space.
+ */
+#define SH1_LOCAL_MMR_OFFSET 0x8000000000UL
+#define SH2_LOCAL_MMR_OFFSET 0x0200000000UL
+#define LOCAL_MMR_OFFSET (is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET)
+#define LOCAL_MMR_SPACE (__IA64_UNCACHED_OFFSET | LOCAL_MMR_OFFSET)
+#define LOCAL_PHYS_MMR_SPACE (RGN_BASE(RGN_HPAGE) | LOCAL_MMR_OFFSET)
+
+#define SH1_GLOBAL_MMR_OFFSET 0x0800000000UL
+#define SH2_GLOBAL_MMR_OFFSET 0x0300000000UL
+#define GLOBAL_MMR_OFFSET (is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET)
+#define GLOBAL_MMR_SPACE (__IA64_UNCACHED_OFFSET | GLOBAL_MMR_OFFSET)
+
+/*
+ * Physical mode addresses
+ */
+#define GLOBAL_PHYS_MMR_SPACE (RGN_BASE(RGN_HPAGE) | GLOBAL_MMR_OFFSET)
+
+
+/*
+ * Clear region & AS bits.
+ */
+#define TO_PHYS_MASK (~(RGN_BITS | AS_MASK))
+
+
+/*
+ * Misc NASID manipulation.
+ */
+#define NASID_SPACE(n) ((u64)(n) << NASID_SHIFT)
+#define REMOTE_ADDR(n,a) (NASID_SPACE(n) | (a))
+#define NODE_OFFSET(x) ((x) & (NODE_ADDRSPACE_SIZE - 1))
+#define NODE_ADDRSPACE_SIZE (1UL << AS_SHIFT)
+#define NASID_GET(x) (int) (((u64) (x) >> NASID_SHIFT) & NASID_BITMASK)
+#define LOCAL_MMR_ADDR(a) (LOCAL_MMR_SPACE | (a))
+#define GLOBAL_MMR_ADDR(n,a) (GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a))
+#define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
+#define GLOBAL_CAC_ADDR(n,a) (CAC_BASE | REMOTE_ADDR(n,a))
+#define CHANGE_NASID(n,x) ((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n)))
+#define IS_TIO_NASID(n) ((n) & 1)
+
+
+/* non-II mmr's start at top of big window space (4G) */
+#define BWIN_TOP 0x0000000100000000UL
+
+/*
+ * general address defines
+ */
+#define CAC_BASE (PAGE_OFFSET | AS_CAC_SPACE)
+#define AMO_BASE (__IA64_UNCACHED_OFFSET | AS_AMO_SPACE)
+#define AMO_PHYS_BASE (RGN_BASE(RGN_HPAGE) | AS_AMO_SPACE)
+#define GET_BASE (PAGE_OFFSET | AS_GET_SPACE)
+
+/*
+ * Convert Memory addresses between various addressing modes.
+ */
+#define TO_PHYS(x) (TO_PHYS_MASK & (x))
+#define TO_CAC(x) (CAC_BASE | TO_PHYS(x))
+#ifdef CONFIG_SGI_SN
+#define TO_AMO(x) (AMO_BASE | TO_PHYS(x))
+#define TO_GET(x) (GET_BASE | TO_PHYS(x))
+#else
+#define TO_AMO(x) ({ BUG(); x; })
+#define TO_GET(x) ({ BUG(); x; })
+#endif
+
+/*
+ * Covert from processor physical address to II/TIO physical address:
+ * II - squeeze out the AS bits
+ * TIO- requires a chiplet id in bits 38-39. For DMA to memory,
+ * the chiplet id is zero. If we implement TIO-TIO dma, we might need
+ * to insert a chiplet id into this macro. However, it is our belief
+ * right now that this chiplet id will be ICE, which is also zero.
+ */
+#define SH1_TIO_PHYS_TO_DMA(x) \
+ ((((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
+
+#define SH2_NETWORK_BANK_OFFSET(x) \
+ ((u64)(x) & ((1UL << (sn_hub_info->nasid_shift - 4)) -1))
+
+#define SH2_NETWORK_BANK_SELECT(x) \
+ ((((u64)(x) & (0x3UL << (sn_hub_info->nasid_shift - 4))) \
+ >> (sn_hub_info->nasid_shift - 4)) << 36)
+
+#define SH2_NETWORK_ADDRESS(x) \
+ (SH2_NETWORK_BANK_OFFSET(x) | SH2_NETWORK_BANK_SELECT(x))
+
+#define SH2_TIO_PHYS_TO_DMA(x) \
+ (((u64)(NASID_GET(x)) << 40) | SH2_NETWORK_ADDRESS(x))
+
+#define PHYS_TO_TIODMA(x) \
+ (is_shub1() ? SH1_TIO_PHYS_TO_DMA(x) : SH2_TIO_PHYS_TO_DMA(x))
+
+#define PHYS_TO_DMA(x) \
+ ((((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
+
+
+/*
+ * Macros to test for address type.
+ */
+#define IS_AMO_ADDRESS(x) (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_BASE)
+#define IS_AMO_PHYS_ADDRESS(x) (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_PHYS_BASE)
+
+
+/*
+ * The following definitions pertain to the IO special address
+ * space. They define the location of the big and little windows
+ * of any given node.
+ */
+#define BWIN_SIZE_BITS 29 /* big window size: 512M */
+#define TIO_BWIN_SIZE_BITS 30 /* big window size: 1G */
+#define NODE_SWIN_BASE(n, w) ((w == 0) ? NODE_BWIN_BASE((n), SWIN0_BIGWIN) \
+ : RAW_NODE_SWIN_BASE(n, w))
+#define TIO_SWIN_BASE(n, w) (TIO_IO_BASE(n) + \
+ ((u64) (w) << TIO_SWIN_SIZE_BITS))
+#define NODE_IO_BASE(n) (GLOBAL_MMR_SPACE | NASID_SPACE(n))
+#define TIO_IO_BASE(n) (__IA64_UNCACHED_OFFSET | NASID_SPACE(n))
+#define BWIN_SIZE (1UL << BWIN_SIZE_BITS)
+#define NODE_BWIN_BASE0(n) (NODE_IO_BASE(n) + BWIN_SIZE)
+#define NODE_BWIN_BASE(n, w) (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))
+#define RAW_NODE_SWIN_BASE(n, w) (NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS))
+#define BWIN_WIDGET_MASK 0x7
+#define BWIN_WINDOWNUM(x) (((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
+#define SH1_IS_BIG_WINDOW_ADDR(x) ((x) & BWIN_TOP)
+
+#define TIO_BWIN_WINDOW_SELECT_MASK 0x7
+#define TIO_BWIN_WINDOWNUM(x) (((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)
+
+#define TIO_HWIN_SHIFT_BITS 33
+#define TIO_HWIN(x) (NODE_OFFSET(x) >> TIO_HWIN_SHIFT_BITS)
+
+/*
+ * The following definitions pertain to the IO special address
+ * space. They define the location of the big and little windows
+ * of any given node.
+ */
+
+#define SWIN_SIZE_BITS 24
+#define SWIN_WIDGET_MASK 0xF
+
+#define TIO_SWIN_SIZE_BITS 28
+#define TIO_SWIN_SIZE (1UL << TIO_SWIN_SIZE_BITS)
+#define TIO_SWIN_WIDGET_MASK 0x3
+
+/*
+ * Convert smallwindow address to xtalk address.
+ *
+ * 'addr' can be physical or virtual address, but will be converted
+ * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
+ */
+#define SWIN_WIDGETNUM(x) (((x) >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
+#define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
+
+
+/*
+ * The following macros produce the correct base virtual address for
+ * the hub registers. The REMOTE_HUB_* macro produce
+ * the address for the specified hub's registers. The intent is
+ * that the appropriate PI, MD, NI, or II register would be substituted
+ * for x.
+ *
+ * WARNING:
+ * When certain Hub chip workaround are defined, it's not sufficient
+ * to dereference the *_HUB_ADDR() macros. You should instead use
+ * HUB_L() and HUB_S() if you must deal with pointers to hub registers.
+ * Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
+ * They're always safe.
+ */
+/* Shub1 TIO & MMR addressing macros */
+#define SH1_TIO_IOSPACE_ADDR(n,x) \
+ GLOBAL_MMR_ADDR(n,x)
+
+#define SH1_REMOTE_BWIN_MMR(n,x) \
+ GLOBAL_MMR_ADDR(n,x)
+
+#define SH1_REMOTE_SWIN_MMR(n,x) \
+ (NODE_SWIN_BASE(n,1) + 0x800000UL + (x))
+
+#define SH1_REMOTE_MMR(n,x) \
+ (SH1_IS_BIG_WINDOW_ADDR(x) ? SH1_REMOTE_BWIN_MMR(n,x) : \
+ SH1_REMOTE_SWIN_MMR(n,x))
+
+/* Shub1 TIO & MMR addressing macros */
+#define SH2_TIO_IOSPACE_ADDR(n,x) \
+ ((__IA64_UNCACHED_OFFSET | REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2)))
+
+#define SH2_REMOTE_MMR(n,x) \
+ GLOBAL_MMR_ADDR(n,x)
+
+
+/* TIO & MMR addressing macros that work on both shub1 & shub2 */
+#define TIO_IOSPACE_ADDR(n,x) \
+ ((u64 *)(is_shub1() ? SH1_TIO_IOSPACE_ADDR(n,x) : \
+ SH2_TIO_IOSPACE_ADDR(n,x)))
+
+#define SH_REMOTE_MMR(n,x) \
+ (is_shub1() ? SH1_REMOTE_MMR(n,x) : SH2_REMOTE_MMR(n,x))
+
+#define REMOTE_HUB_ADDR(n,x) \
+ (IS_TIO_NASID(n) ? ((volatile u64*)TIO_IOSPACE_ADDR(n,x)) : \
+ ((volatile u64*)SH_REMOTE_MMR(n,x)))
+
+
+#define HUB_L(x) (*((volatile typeof(*x) *)x))
+#define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d))
+
+#define REMOTE_HUB_L(n, a) HUB_L(REMOTE_HUB_ADDR((n), (a)))
+#define REMOTE_HUB_S(n, a, d) HUB_S(REMOTE_HUB_ADDR((n), (a)), (d))
+
+/*
+ * Coretalk address breakdown
+ */
+#define CTALK_NASID_SHFT 40
+#define CTALK_NASID_MASK (0x3FFFULL << CTALK_NASID_SHFT)
+#define CTALK_CID_SHFT 38
+#define CTALK_CID_MASK (0x3ULL << CTALK_CID_SHFT)
+#define CTALK_NODE_OFFSET 0x3FFFFFFFFF
+
+#endif /* _ASM_IA64_SN_ADDRS_H */
diff --git a/kernel/arch/ia64/include/asm/sn/arch.h b/kernel/arch/ia64/include/asm/sn/arch.h
new file mode 100644
index 000000000..31eb78486
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/arch.h
@@ -0,0 +1,86 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SGI specific setup.
+ *
+ * Copyright (C) 1995-1997,1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_IA64_SN_ARCH_H
+#define _ASM_IA64_SN_ARCH_H
+
+#include <linux/numa.h>
+#include <asm/types.h>
+#include <asm/percpu.h>
+#include <asm/sn/types.h>
+#include <asm/sn/sn_cpuid.h>
+
+/*
+ * This is the maximum number of NUMALINK nodes that can be part of a single
+ * SSI kernel. This number includes C-brick, M-bricks, and TIOs. Nodes in
+ * remote partitions are NOT included in this number.
+ * The number of compact nodes cannot exceed size of a coherency domain.
+ * The purpose of this define is to specify a node count that includes
+ * all C/M/TIO nodes in an SSI system.
+ *
+ * SGI system can currently support up to 256 C/M nodes plus additional TIO nodes.
+ *
+ * Note: ACPI20 has an architectural limit of 256 nodes. When we upgrade
+ * to ACPI3.0, this limit will be removed. The notion of "compact nodes"
+ * should be deleted and TIOs should be included in MAX_NUMNODES.
+ */
+#define MAX_TIO_NODES MAX_NUMNODES
+#define MAX_COMPACT_NODES (MAX_NUMNODES + MAX_TIO_NODES)
+
+/*
+ * Maximum number of nodes in all partitions and in all coherency domains.
+ * This is the total number of nodes accessible in the numalink fabric. It
+ * includes all C & M bricks, plus all TIOs.
+ *
+ * This value is also the value of the maximum number of NASIDs in the numalink
+ * fabric.
+ */
+#define MAX_NUMALINK_NODES 16384
+
+/*
+ * The following defines attributes of the HUB chip. These attributes are
+ * frequently referenced. They are kept in the per-cpu data areas of each cpu.
+ * They are kept together in a struct to minimize cache misses.
+ */
+struct sn_hub_info_s {
+ u8 shub2;
+ u8 nasid_shift;
+ u8 as_shift;
+ u8 shub_1_1_found;
+ u16 nasid_bitmask;
+};
+DECLARE_PER_CPU(struct sn_hub_info_s, __sn_hub_info);
+#define sn_hub_info this_cpu_ptr(&__sn_hub_info)
+#define is_shub2() (sn_hub_info->shub2)
+#define is_shub1() (sn_hub_info->shub2 == 0)
+
+/*
+ * Use this macro to test if shub 1.1 wars should be enabled
+ */
+#define enable_shub_wars_1_1() (sn_hub_info->shub_1_1_found)
+
+
+/*
+ * Compact node ID to nasid mappings kept in the per-cpu data areas of each
+ * cpu.
+ */
+DECLARE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_COMPACT_NODES]);
+#define sn_cnodeid_to_nasid this_cpu_ptr(&__sn_cnodeid_to_nasid[0])
+
+
+extern u8 sn_partition_id;
+extern u8 sn_system_size;
+extern u8 sn_sharing_domain_size;
+extern u8 sn_region_size;
+
+extern void sn_flush_all_caches(long addr, long bytes);
+extern bool sn_cpu_disable_allowed(int cpu);
+
+#endif /* _ASM_IA64_SN_ARCH_H */
diff --git a/kernel/arch/ia64/include/asm/sn/bte.h b/kernel/arch/ia64/include/asm/sn/bte.h
new file mode 100644
index 000000000..cc6c4dbf5
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/bte.h
@@ -0,0 +1,234 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2000-2007 Silicon Graphics, Inc. All Rights Reserved.
+ */
+
+
+#ifndef _ASM_IA64_SN_BTE_H
+#define _ASM_IA64_SN_BTE_H
+
+#include <linux/timer.h>
+#include <linux/spinlock.h>
+#include <linux/cache.h>
+#include <asm/sn/pda.h>
+#include <asm/sn/types.h>
+#include <asm/sn/shub_mmr.h>
+
+#define IBCT_NOTIFY (0x1UL << 4)
+#define IBCT_ZFIL_MODE (0x1UL << 0)
+
+/* #define BTE_DEBUG */
+/* #define BTE_DEBUG_VERBOSE */
+
+#ifdef BTE_DEBUG
+# define BTE_PRINTK(x) printk x /* Terse */
+# ifdef BTE_DEBUG_VERBOSE
+# define BTE_PRINTKV(x) printk x /* Verbose */
+# else
+# define BTE_PRINTKV(x)
+# endif /* BTE_DEBUG_VERBOSE */
+#else
+# define BTE_PRINTK(x)
+# define BTE_PRINTKV(x)
+#endif /* BTE_DEBUG */
+
+
+/* BTE status register only supports 16 bits for length field */
+#define BTE_LEN_BITS (16)
+#define BTE_LEN_MASK ((1 << BTE_LEN_BITS) - 1)
+#define BTE_MAX_XFER (BTE_LEN_MASK << L1_CACHE_SHIFT)
+
+
+/* Define hardware */
+#define BTES_PER_NODE (is_shub2() ? 4 : 2)
+#define MAX_BTES_PER_NODE 4
+
+#define BTE2OFF_CTRL 0
+#define BTE2OFF_SRC (SH2_BT_ENG_SRC_ADDR_0 - SH2_BT_ENG_CSR_0)
+#define BTE2OFF_DEST (SH2_BT_ENG_DEST_ADDR_0 - SH2_BT_ENG_CSR_0)
+#define BTE2OFF_NOTIFY (SH2_BT_ENG_NOTIF_ADDR_0 - SH2_BT_ENG_CSR_0)
+
+#define BTE_BASE_ADDR(interface) \
+ (is_shub2() ? (interface == 0) ? SH2_BT_ENG_CSR_0 : \
+ (interface == 1) ? SH2_BT_ENG_CSR_1 : \
+ (interface == 2) ? SH2_BT_ENG_CSR_2 : \
+ SH2_BT_ENG_CSR_3 \
+ : (interface == 0) ? IIO_IBLS0 : IIO_IBLS1)
+
+#define BTE_SOURCE_ADDR(base) \
+ (is_shub2() ? base + (BTE2OFF_SRC/8) \
+ : base + (BTEOFF_SRC/8))
+
+#define BTE_DEST_ADDR(base) \
+ (is_shub2() ? base + (BTE2OFF_DEST/8) \
+ : base + (BTEOFF_DEST/8))
+
+#define BTE_CTRL_ADDR(base) \
+ (is_shub2() ? base + (BTE2OFF_CTRL/8) \
+ : base + (BTEOFF_CTRL/8))
+
+#define BTE_NOTIF_ADDR(base) \
+ (is_shub2() ? base + (BTE2OFF_NOTIFY/8) \
+ : base + (BTEOFF_NOTIFY/8))
+
+/* Define hardware modes */
+#define BTE_NOTIFY IBCT_NOTIFY
+#define BTE_NORMAL BTE_NOTIFY
+#define BTE_ZERO_FILL (BTE_NOTIFY | IBCT_ZFIL_MODE)
+/* Use a reserved bit to let the caller specify a wait for any BTE */
+#define BTE_WACQUIRE 0x4000
+/* Use the BTE on the node with the destination memory */
+#define BTE_USE_DEST (BTE_WACQUIRE << 1)
+/* Use any available BTE interface on any node for the transfer */
+#define BTE_USE_ANY (BTE_USE_DEST << 1)
+/* macro to force the IBCT0 value valid */
+#define BTE_VALID_MODE(x) ((x) & (IBCT_NOTIFY | IBCT_ZFIL_MODE))
+
+#define BTE_ACTIVE (IBLS_BUSY | IBLS_ERROR)
+#define BTE_WORD_AVAILABLE (IBLS_BUSY << 1)
+#define BTE_WORD_BUSY (~BTE_WORD_AVAILABLE)
+
+/*
+ * Some macros to simplify reading.
+ * Start with macros to locate the BTE control registers.
+ */
+#define BTE_LNSTAT_LOAD(_bte) \
+ HUB_L(_bte->bte_base_addr)
+#define BTE_LNSTAT_STORE(_bte, _x) \
+ HUB_S(_bte->bte_base_addr, (_x))
+#define BTE_SRC_STORE(_bte, _x) \
+({ \
+ u64 __addr = ((_x) & ~AS_MASK); \
+ if (is_shub2()) \
+ __addr = SH2_TIO_PHYS_TO_DMA(__addr); \
+ HUB_S(_bte->bte_source_addr, __addr); \
+})
+#define BTE_DEST_STORE(_bte, _x) \
+({ \
+ u64 __addr = ((_x) & ~AS_MASK); \
+ if (is_shub2()) \
+ __addr = SH2_TIO_PHYS_TO_DMA(__addr); \
+ HUB_S(_bte->bte_destination_addr, __addr); \
+})
+#define BTE_CTRL_STORE(_bte, _x) \
+ HUB_S(_bte->bte_control_addr, (_x))
+#define BTE_NOTIF_STORE(_bte, _x) \
+({ \
+ u64 __addr = ia64_tpa((_x) & ~AS_MASK); \
+ if (is_shub2()) \
+ __addr = SH2_TIO_PHYS_TO_DMA(__addr); \
+ HUB_S(_bte->bte_notify_addr, __addr); \
+})
+
+#define BTE_START_TRANSFER(_bte, _len, _mode) \
+ is_shub2() ? BTE_CTRL_STORE(_bte, IBLS_BUSY | (_mode << 24) | _len) \
+ : BTE_LNSTAT_STORE(_bte, _len); \
+ BTE_CTRL_STORE(_bte, _mode)
+
+/* Possible results from bte_copy and bte_unaligned_copy */
+/* The following error codes map into the BTE hardware codes
+ * IIO_ICRB_ECODE_* (in shubio.h). The hardware uses
+ * an error code of 0 (IIO_ICRB_ECODE_DERR), but we want zero
+ * to mean BTE_SUCCESS, so add one (BTEFAIL_OFFSET) to the error
+ * codes to give the following error codes.
+ */
+#define BTEFAIL_OFFSET 1
+
+typedef enum {
+ BTE_SUCCESS, /* 0 is success */
+ BTEFAIL_DIR, /* Directory error due to IIO access*/
+ BTEFAIL_POISON, /* poison error on IO access (write to poison page) */
+ BTEFAIL_WERR, /* Write error (ie WINV to a Read only line) */
+ BTEFAIL_ACCESS, /* access error (protection violation) */
+ BTEFAIL_PWERR, /* Partial Write Error */
+ BTEFAIL_PRERR, /* Partial Read Error */
+ BTEFAIL_TOUT, /* CRB Time out */
+ BTEFAIL_XTERR, /* Incoming xtalk pkt had error bit */
+ BTEFAIL_NOTAVAIL, /* BTE not available */
+} bte_result_t;
+
+#define BTEFAIL_SH2_RESP_SHORT 0x1 /* bit 000001 */
+#define BTEFAIL_SH2_RESP_LONG 0x2 /* bit 000010 */
+#define BTEFAIL_SH2_RESP_DSP 0x4 /* bit 000100 */
+#define BTEFAIL_SH2_RESP_ACCESS 0x8 /* bit 001000 */
+#define BTEFAIL_SH2_CRB_TO 0x10 /* bit 010000 */
+#define BTEFAIL_SH2_NACK_LIMIT 0x20 /* bit 100000 */
+#define BTEFAIL_SH2_ALL 0x3F /* bit 111111 */
+
+#define BTE_ERR_BITS 0x3FUL
+#define BTE_ERR_SHIFT 36
+#define BTE_ERR_MASK (BTE_ERR_BITS << BTE_ERR_SHIFT)
+
+#define BTE_ERROR_RETRY(value) \
+ (is_shub2() ? (value != BTEFAIL_SH2_CRB_TO) \
+ : (value != BTEFAIL_TOUT))
+
+/*
+ * On shub1 BTE_ERR_MASK will always be false, so no need for is_shub2()
+ */
+#define BTE_SHUB2_ERROR(_status) \
+ ((_status & BTE_ERR_MASK) \
+ ? (((_status >> BTE_ERR_SHIFT) & BTE_ERR_BITS) | IBLS_ERROR) \
+ : _status)
+
+#define BTE_GET_ERROR_STATUS(_status) \
+ (BTE_SHUB2_ERROR(_status) & ~IBLS_ERROR)
+
+#define BTE_VALID_SH2_ERROR(value) \
+ ((value >= BTEFAIL_SH2_RESP_SHORT) && (value <= BTEFAIL_SH2_ALL))
+
+/*
+ * Structure defining a bte. An instance of this
+ * structure is created in the nodepda for each
+ * bte on that node (as defined by BTES_PER_NODE)
+ * This structure contains everything necessary
+ * to work with a BTE.
+ */
+struct bteinfo_s {
+ volatile u64 notify ____cacheline_aligned;
+ u64 *bte_base_addr ____cacheline_aligned;
+ u64 *bte_source_addr;
+ u64 *bte_destination_addr;
+ u64 *bte_control_addr;
+ u64 *bte_notify_addr;
+ spinlock_t spinlock;
+ cnodeid_t bte_cnode; /* cnode */
+ int bte_error_count; /* Number of errors encountered */
+ int bte_num; /* 0 --> BTE0, 1 --> BTE1 */
+ int cleanup_active; /* Interface is locked for cleanup */
+ volatile bte_result_t bh_error; /* error while processing */
+ volatile u64 *most_rcnt_na;
+ struct bteinfo_s *btes_to_try[MAX_BTES_PER_NODE];
+};
+
+
+/*
+ * Function prototypes (functions defined in bte.c, used elsewhere)
+ */
+extern bte_result_t bte_copy(u64, u64, u64, u64, void *);
+extern bte_result_t bte_unaligned_copy(u64, u64, u64, u64);
+extern void bte_error_handler(unsigned long);
+
+#define bte_zero(dest, len, mode, notification) \
+ bte_copy(0, dest, len, ((mode) | BTE_ZERO_FILL), notification)
+
+/*
+ * The following is the preferred way of calling bte_unaligned_copy
+ * If the copy is fully cache line aligned, then bte_copy is
+ * used instead. Since bte_copy is inlined, this saves a call
+ * stack. NOTE: bte_copy is called synchronously and does block
+ * until the transfer is complete. In order to get the asynch
+ * version of bte_copy, you must perform this check yourself.
+ */
+#define BTE_UNALIGNED_COPY(src, dest, len, mode) \
+ (((len & (L1_CACHE_BYTES - 1)) || \
+ (src & (L1_CACHE_BYTES - 1)) || \
+ (dest & (L1_CACHE_BYTES - 1))) ? \
+ bte_unaligned_copy(src, dest, len, mode) : \
+ bte_copy(src, dest, len, mode, NULL))
+
+
+#endif /* _ASM_IA64_SN_BTE_H */
diff --git a/kernel/arch/ia64/include/asm/sn/clksupport.h b/kernel/arch/ia64/include/asm/sn/clksupport.h
new file mode 100644
index 000000000..d340c365a
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/clksupport.h
@@ -0,0 +1,28 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+
+/*
+ * This file contains definitions for accessing a platform supported high resolution
+ * clock. The clock is monitonically increasing and can be accessed from any node
+ * in the system. The clock is synchronized across nodes - all nodes see the
+ * same value.
+ *
+ * RTC_COUNTER_ADDR - contains the address of the counter
+ *
+ */
+
+#ifndef _ASM_IA64_SN_CLKSUPPORT_H
+#define _ASM_IA64_SN_CLKSUPPORT_H
+
+extern unsigned long sn_rtc_cycles_per_second;
+
+#define RTC_COUNTER_ADDR ((long *)LOCAL_MMR_ADDR(SH_RTC))
+
+#define rtc_time() (*RTC_COUNTER_ADDR)
+
+#endif /* _ASM_IA64_SN_CLKSUPPORT_H */
diff --git a/kernel/arch/ia64/include/asm/sn/geo.h b/kernel/arch/ia64/include/asm/sn/geo.h
new file mode 100644
index 000000000..f083c9434
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/geo.h
@@ -0,0 +1,132 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_GEO_H
+#define _ASM_IA64_SN_GEO_H
+
+/* The geoid_t implementation below is based loosely on the pcfg_t
+ implementation in sys/SN/promcfg.h. */
+
+/* Type declaractions */
+
+/* Size of a geoid_t structure (must be before decl. of geoid_u) */
+#define GEOID_SIZE 8 /* Would 16 be better? The size can
+ be different on different platforms. */
+
+#define MAX_SLOTS 0xf /* slots per module */
+#define MAX_SLABS 0xf /* slabs per slot */
+
+typedef unsigned char geo_type_t;
+
+/* Fields common to all substructures */
+typedef struct geo_common_s {
+ moduleid_t module; /* The module (box) this h/w lives in */
+ geo_type_t type; /* What type of h/w is named by this geoid_t */
+ slabid_t slab:4; /* slab (ASIC), 0 .. 15 within slot */
+ slotid_t slot:4; /* slot (Blade), 0 .. 15 within module */
+} geo_common_t;
+
+/* Additional fields for particular types of hardware */
+typedef struct geo_node_s {
+ geo_common_t common; /* No additional fields needed */
+} geo_node_t;
+
+typedef struct geo_rtr_s {
+ geo_common_t common; /* No additional fields needed */
+} geo_rtr_t;
+
+typedef struct geo_iocntl_s {
+ geo_common_t common; /* No additional fields needed */
+} geo_iocntl_t;
+
+typedef struct geo_pcicard_s {
+ geo_iocntl_t common;
+ char bus; /* Bus/widget number */
+ char slot; /* PCI slot number */
+} geo_pcicard_t;
+
+/* Subcomponents of a node */
+typedef struct geo_cpu_s {
+ geo_node_t node;
+ char slice; /* Which CPU on the node */
+} geo_cpu_t;
+
+typedef struct geo_mem_s {
+ geo_node_t node;
+ char membus; /* The memory bus on the node */
+ char memslot; /* The memory slot on the bus */
+} geo_mem_t;
+
+
+typedef union geoid_u {
+ geo_common_t common;
+ geo_node_t node;
+ geo_iocntl_t iocntl;
+ geo_pcicard_t pcicard;
+ geo_rtr_t rtr;
+ geo_cpu_t cpu;
+ geo_mem_t mem;
+ char padsize[GEOID_SIZE];
+} geoid_t;
+
+
+/* Preprocessor macros */
+
+#define GEO_MAX_LEN 48 /* max. formatted length, plus some pad:
+ module/001c07/slab/5/node/memory/2/slot/4 */
+
+/* Values for geo_type_t */
+#define GEO_TYPE_INVALID 0
+#define GEO_TYPE_MODULE 1
+#define GEO_TYPE_NODE 2
+#define GEO_TYPE_RTR 3
+#define GEO_TYPE_IOCNTL 4
+#define GEO_TYPE_IOCARD 5
+#define GEO_TYPE_CPU 6
+#define GEO_TYPE_MEM 7
+#define GEO_TYPE_MAX (GEO_TYPE_MEM+1)
+
+/* Parameter for hwcfg_format_geoid_compt() */
+#define GEO_COMPT_MODULE 1
+#define GEO_COMPT_SLAB 2
+#define GEO_COMPT_IOBUS 3
+#define GEO_COMPT_IOSLOT 4
+#define GEO_COMPT_CPU 5
+#define GEO_COMPT_MEMBUS 6
+#define GEO_COMPT_MEMSLOT 7
+
+#define GEO_INVALID_STR "<invalid>"
+
+#define INVALID_NASID ((nasid_t)-1)
+#define INVALID_CNODEID ((cnodeid_t)-1)
+#define INVALID_PNODEID ((pnodeid_t)-1)
+#define INVALID_SLAB (slabid_t)-1
+#define INVALID_SLOT (slotid_t)-1
+#define INVALID_MODULE ((moduleid_t)-1)
+
+static inline slabid_t geo_slab(geoid_t g)
+{
+ return (g.common.type == GEO_TYPE_INVALID) ?
+ INVALID_SLAB : g.common.slab;
+}
+
+static inline slotid_t geo_slot(geoid_t g)
+{
+ return (g.common.type == GEO_TYPE_INVALID) ?
+ INVALID_SLOT : g.common.slot;
+}
+
+static inline moduleid_t geo_module(geoid_t g)
+{
+ return (g.common.type == GEO_TYPE_INVALID) ?
+ INVALID_MODULE : g.common.module;
+}
+
+extern geoid_t cnodeid_get_geoid(cnodeid_t cnode);
+
+#endif /* _ASM_IA64_SN_GEO_H */
diff --git a/kernel/arch/ia64/include/asm/sn/intr.h b/kernel/arch/ia64/include/asm/sn/intr.h
new file mode 100644
index 000000000..e0487aa97
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/intr.h
@@ -0,0 +1,68 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2006 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_INTR_H
+#define _ASM_IA64_SN_INTR_H
+
+#include <linux/rcupdate.h>
+#include <asm/sn/types.h>
+
+#define SGI_UART_VECTOR 0xe9
+
+/* Reserved IRQs : Note, not to exceed IA64_SN2_FIRST_DEVICE_VECTOR */
+#define SGI_XPC_ACTIVATE 0x30
+#define SGI_II_ERROR 0x31
+#define SGI_XBOW_ERROR 0x32
+#define SGI_PCIASIC_ERROR 0x33
+#define SGI_ACPI_SCI_INT 0x34
+#define SGI_TIOCA_ERROR 0x35
+#define SGI_TIO_ERROR 0x36
+#define SGI_TIOCX_ERROR 0x37
+#define SGI_MMTIMER_VECTOR 0x38
+#define SGI_XPC_NOTIFY 0xe7
+
+#define IA64_SN2_FIRST_DEVICE_VECTOR 0x3c
+#define IA64_SN2_LAST_DEVICE_VECTOR 0xe6
+
+#define SN2_IRQ_RESERVED 0x1
+#define SN2_IRQ_CONNECTED 0x2
+#define SN2_IRQ_SHARED 0x4
+
+// The SN PROM irq struct
+struct sn_irq_info {
+ struct sn_irq_info *irq_next; /* deprecated DO NOT USE */
+ short irq_nasid; /* Nasid IRQ is assigned to */
+ int irq_slice; /* slice IRQ is assigned to */
+ int irq_cpuid; /* kernel logical cpuid */
+ int irq_irq; /* the IRQ number */
+ int irq_int_bit; /* Bridge interrupt pin */
+ /* <0 means MSI */
+ u64 irq_xtalkaddr; /* xtalkaddr IRQ is sent to */
+ int irq_bridge_type;/* pciio asic type (pciio.h) */
+ void *irq_bridge; /* bridge generating irq */
+ void *irq_pciioinfo; /* associated pciio_info_t */
+ int irq_last_intr; /* For Shub lb lost intr WAR */
+ int irq_cookie; /* unique cookie */
+ int irq_flags; /* flags */
+ int irq_share_cnt; /* num devices sharing IRQ */
+ struct list_head list; /* list of sn_irq_info structs */
+ struct rcu_head rcu; /* rcu callback list */
+};
+
+extern void sn_send_IPI_phys(int, long, int, int);
+extern u64 sn_intr_alloc(nasid_t, int,
+ struct sn_irq_info *,
+ int, nasid_t, int);
+extern void sn_intr_free(nasid_t, int, struct sn_irq_info *);
+extern struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *, nasid_t, int);
+extern void sn_set_err_irq_affinity(unsigned int);
+extern struct list_head **sn_irq_lh;
+
+#define CPU_VECTOR_TO_IRQ(cpuid,vector) (vector)
+
+#endif /* _ASM_IA64_SN_INTR_H */
diff --git a/kernel/arch/ia64/include/asm/sn/io.h b/kernel/arch/ia64/include/asm/sn/io.h
new file mode 100644
index 000000000..41c73a735
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/io.h
@@ -0,0 +1,274 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_SN_IO_H
+#define _ASM_SN_IO_H
+#include <linux/compiler.h>
+#include <asm/intrinsics.h>
+
+extern void * sn_io_addr(unsigned long port) __attribute_const__; /* Forward definition */
+extern void __sn_mmiowb(void); /* Forward definition */
+
+extern int num_cnodes;
+
+#define __sn_mf_a() ia64_mfa()
+
+extern void sn_dma_flush(unsigned long);
+
+#define __sn_inb ___sn_inb
+#define __sn_inw ___sn_inw
+#define __sn_inl ___sn_inl
+#define __sn_outb ___sn_outb
+#define __sn_outw ___sn_outw
+#define __sn_outl ___sn_outl
+#define __sn_readb ___sn_readb
+#define __sn_readw ___sn_readw
+#define __sn_readl ___sn_readl
+#define __sn_readq ___sn_readq
+#define __sn_readb_relaxed ___sn_readb_relaxed
+#define __sn_readw_relaxed ___sn_readw_relaxed
+#define __sn_readl_relaxed ___sn_readl_relaxed
+#define __sn_readq_relaxed ___sn_readq_relaxed
+
+/*
+ * Convenience macros for setting/clearing bits using the above accessors
+ */
+
+#define __sn_setq_relaxed(addr, val) \
+ writeq((__sn_readq_relaxed(addr) | (val)), (addr))
+#define __sn_clrq_relaxed(addr, val) \
+ writeq((__sn_readq_relaxed(addr) & ~(val)), (addr))
+
+/*
+ * The following routines are SN Platform specific, called when
+ * a reference is made to inX/outX set macros. SN Platform
+ * inX set of macros ensures that Posted DMA writes on the
+ * Bridge is flushed.
+ *
+ * The routines should be self explainatory.
+ */
+
+static inline unsigned int
+___sn_inb (unsigned long port)
+{
+ volatile unsigned char *addr;
+ unsigned char ret = -1;
+
+ if ((addr = sn_io_addr(port))) {
+ ret = *addr;
+ __sn_mf_a();
+ sn_dma_flush((unsigned long)addr);
+ }
+ return ret;
+}
+
+static inline unsigned int
+___sn_inw (unsigned long port)
+{
+ volatile unsigned short *addr;
+ unsigned short ret = -1;
+
+ if ((addr = sn_io_addr(port))) {
+ ret = *addr;
+ __sn_mf_a();
+ sn_dma_flush((unsigned long)addr);
+ }
+ return ret;
+}
+
+static inline unsigned int
+___sn_inl (unsigned long port)
+{
+ volatile unsigned int *addr;
+ unsigned int ret = -1;
+
+ if ((addr = sn_io_addr(port))) {
+ ret = *addr;
+ __sn_mf_a();
+ sn_dma_flush((unsigned long)addr);
+ }
+ return ret;
+}
+
+static inline void
+___sn_outb (unsigned char val, unsigned long port)
+{
+ volatile unsigned char *addr;
+
+ if ((addr = sn_io_addr(port))) {
+ *addr = val;
+ __sn_mmiowb();
+ }
+}
+
+static inline void
+___sn_outw (unsigned short val, unsigned long port)
+{
+ volatile unsigned short *addr;
+
+ if ((addr = sn_io_addr(port))) {
+ *addr = val;
+ __sn_mmiowb();
+ }
+}
+
+static inline void
+___sn_outl (unsigned int val, unsigned long port)
+{
+ volatile unsigned int *addr;
+
+ if ((addr = sn_io_addr(port))) {
+ *addr = val;
+ __sn_mmiowb();
+ }
+}
+
+/*
+ * The following routines are SN Platform specific, called when
+ * a reference is made to readX/writeX set macros. SN Platform
+ * readX set of macros ensures that Posted DMA writes on the
+ * Bridge is flushed.
+ *
+ * The routines should be self explainatory.
+ */
+
+static inline unsigned char
+___sn_readb (const volatile void __iomem *addr)
+{
+ unsigned char val;
+
+ val = *(volatile unsigned char __force *)addr;
+ __sn_mf_a();
+ sn_dma_flush((unsigned long)addr);
+ return val;
+}
+
+static inline unsigned short
+___sn_readw (const volatile void __iomem *addr)
+{
+ unsigned short val;
+
+ val = *(volatile unsigned short __force *)addr;
+ __sn_mf_a();
+ sn_dma_flush((unsigned long)addr);
+ return val;
+}
+
+static inline unsigned int
+___sn_readl (const volatile void __iomem *addr)
+{
+ unsigned int val;
+
+ val = *(volatile unsigned int __force *)addr;
+ __sn_mf_a();
+ sn_dma_flush((unsigned long)addr);
+ return val;
+}
+
+static inline unsigned long
+___sn_readq (const volatile void __iomem *addr)
+{
+ unsigned long val;
+
+ val = *(volatile unsigned long __force *)addr;
+ __sn_mf_a();
+ sn_dma_flush((unsigned long)addr);
+ return val;
+}
+
+/*
+ * For generic and SN2 kernels, we have a set of fast access
+ * PIO macros. These macros are provided on SN Platform
+ * because the normal inX and readX macros perform an
+ * additional task of flushing Post DMA request on the Bridge.
+ *
+ * These routines should be self explainatory.
+ */
+
+static inline unsigned int
+sn_inb_fast (unsigned long port)
+{
+ volatile unsigned char *addr = (unsigned char *)port;
+ unsigned char ret;
+
+ ret = *addr;
+ __sn_mf_a();
+ return ret;
+}
+
+static inline unsigned int
+sn_inw_fast (unsigned long port)
+{
+ volatile unsigned short *addr = (unsigned short *)port;
+ unsigned short ret;
+
+ ret = *addr;
+ __sn_mf_a();
+ return ret;
+}
+
+static inline unsigned int
+sn_inl_fast (unsigned long port)
+{
+ volatile unsigned int *addr = (unsigned int *)port;
+ unsigned int ret;
+
+ ret = *addr;
+ __sn_mf_a();
+ return ret;
+}
+
+static inline unsigned char
+___sn_readb_relaxed (const volatile void __iomem *addr)
+{
+ return *(volatile unsigned char __force *)addr;
+}
+
+static inline unsigned short
+___sn_readw_relaxed (const volatile void __iomem *addr)
+{
+ return *(volatile unsigned short __force *)addr;
+}
+
+static inline unsigned int
+___sn_readl_relaxed (const volatile void __iomem *addr)
+{
+ return *(volatile unsigned int __force *) addr;
+}
+
+static inline unsigned long
+___sn_readq_relaxed (const volatile void __iomem *addr)
+{
+ return *(volatile unsigned long __force *) addr;
+}
+
+struct pci_dev;
+
+static inline int
+sn_pci_set_vchan(struct pci_dev *pci_dev, unsigned long *addr, int vchan)
+{
+
+ if (vchan > 1) {
+ return -1;
+ }
+
+ if (!(*addr >> 32)) /* Using a mask here would be cleaner */
+ return 0; /* but this generates better code */
+
+ if (vchan == 1) {
+ /* Set Bit 57 */
+ *addr |= (1UL << 57);
+ } else {
+ /* Clear Bit 57 */
+ *addr &= ~(1UL << 57);
+ }
+
+ return 0;
+}
+
+#endif /* _ASM_SN_IO_H */
diff --git a/kernel/arch/ia64/include/asm/sn/ioc3.h b/kernel/arch/ia64/include/asm/sn/ioc3.h
new file mode 100644
index 000000000..95ed6cc83
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/ioc3.h
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2005 Silicon Graphics, Inc.
+ */
+#ifndef IA64_SN_IOC3_H
+#define IA64_SN_IOC3_H
+
+/* serial port register map */
+struct ioc3_serialregs {
+ uint32_t sscr;
+ uint32_t stpir;
+ uint32_t stcir;
+ uint32_t srpir;
+ uint32_t srcir;
+ uint32_t srtr;
+ uint32_t shadow;
+};
+
+/* SUPERIO uart register map */
+struct ioc3_uartregs {
+ char iu_lcr;
+ union {
+ char iir; /* read only */
+ char fcr; /* write only */
+ } u3;
+ union {
+ char ier; /* DLAB == 0 */
+ char dlm; /* DLAB == 1 */
+ } u2;
+ union {
+ char rbr; /* read only, DLAB == 0 */
+ char thr; /* write only, DLAB == 0 */
+ char dll; /* DLAB == 1 */
+ } u1;
+ char iu_scr;
+ char iu_msr;
+ char iu_lsr;
+ char iu_mcr;
+};
+
+#define iu_rbr u1.rbr
+#define iu_thr u1.thr
+#define iu_dll u1.dll
+#define iu_ier u2.ier
+#define iu_dlm u2.dlm
+#define iu_iir u3.iir
+#define iu_fcr u3.fcr
+
+struct ioc3_sioregs {
+ char fill[0x170];
+ struct ioc3_uartregs uartb;
+ struct ioc3_uartregs uarta;
+};
+
+/* PCI IO/mem space register map */
+struct ioc3 {
+ uint32_t pci_id;
+ uint32_t pci_scr;
+ uint32_t pci_rev;
+ uint32_t pci_lat;
+ uint32_t pci_addr;
+ uint32_t pci_err_addr_l;
+ uint32_t pci_err_addr_h;
+
+ uint32_t sio_ir;
+ /* these registers are read-only for general kernel code. To
+ * modify them use the functions in ioc3.c
+ */
+ uint32_t sio_ies;
+ uint32_t sio_iec;
+ uint32_t sio_cr;
+ uint32_t int_out;
+ uint32_t mcr;
+ uint32_t gpcr_s;
+ uint32_t gpcr_c;
+ uint32_t gpdr;
+ uint32_t gppr[9];
+ char fill[0x4c];
+
+ /* serial port registers */
+ uint32_t sbbr_h;
+ uint32_t sbbr_l;
+
+ struct ioc3_serialregs port_a;
+ struct ioc3_serialregs port_b;
+ char fill1[0x1ff10];
+ /* superio registers */
+ struct ioc3_sioregs sregs;
+};
+
+/* These don't exist on the ioc3 serial card... */
+#define eier fill1[8]
+#define eisr fill1[4]
+
+#define PCI_LAT 0xc /* Latency Timer */
+#define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */
+#define UARTA_BASE 0x178
+#define UARTB_BASE 0x170
+
+
+/* bitmasks for serial RX status byte */
+#define RXSB_OVERRUN 0x01 /* char(s) lost */
+#define RXSB_PAR_ERR 0x02 /* parity error */
+#define RXSB_FRAME_ERR 0x04 /* framing error */
+#define RXSB_BREAK 0x08 /* break character */
+#define RXSB_CTS 0x10 /* state of CTS */
+#define RXSB_DCD 0x20 /* state of DCD */
+#define RXSB_MODEM_VALID 0x40 /* DCD, CTS and OVERRUN are valid */
+#define RXSB_DATA_VALID 0x80 /* FRAME_ERR PAR_ERR & BREAK valid */
+
+/* bitmasks for serial TX control byte */
+#define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */
+#define TXCB_INVALID 0x00 /* byte is invalid */
+#define TXCB_VALID 0x40 /* byte is valid */
+#define TXCB_MCR 0x80 /* data<7:0> to modem cntrl register */
+#define TXCB_DELAY 0xc0 /* delay data<7:0> mSec */
+
+/* bitmasks for SBBR_L */
+#define SBBR_L_SIZE 0x00000001 /* 0 1KB rings, 1 4KB rings */
+
+/* bitmasks for SSCR_<A:B> */
+#define SSCR_RX_THRESHOLD 0x000001ff /* hiwater mark */
+#define SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
+#define SSCR_HFC_EN 0x00020000 /* h/w flow cntrl enabled */
+#define SSCR_RX_RING_DCD 0x00040000 /* postRX record on delta-DCD */
+#define SSCR_RX_RING_CTS 0x00080000 /* postRX record on delta-CTS */
+#define SSCR_HIGH_SPD 0x00100000 /* 4X speed */
+#define SSCR_DIAG 0x00200000 /* bypass clock divider */
+#define SSCR_RX_DRAIN 0x08000000 /* drain RX buffer to memory */
+#define SSCR_DMA_EN 0x10000000 /* enable ring buffer DMA */
+#define SSCR_DMA_PAUSE 0x20000000 /* pause DMA */
+#define SSCR_PAUSE_STATE 0x40000000 /* set when PAUSE takes effect*/
+#define SSCR_RESET 0x80000000 /* reset DMA channels */
+
+/* all producer/comsumer pointers are the same bitfield */
+#define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */
+#define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */
+#define PROD_CONS_PTR_OFF 3
+
+/* bitmasks for SRCIR_<A:B> */
+#define SRCIR_ARM 0x80000000 /* arm RX timer */
+
+/* bitmasks for SHADOW_<A:B> */
+#define SHADOW_DR 0x00000001 /* data ready */
+#define SHADOW_OE 0x00000002 /* overrun error */
+#define SHADOW_PE 0x00000004 /* parity error */
+#define SHADOW_FE 0x00000008 /* framing error */
+#define SHADOW_BI 0x00000010 /* break interrupt */
+#define SHADOW_THRE 0x00000020 /* transmit holding reg empty */
+#define SHADOW_TEMT 0x00000040 /* transmit shift reg empty */
+#define SHADOW_RFCE 0x00000080 /* char in RX fifo has error */
+#define SHADOW_DCTS 0x00010000 /* delta clear to send */
+#define SHADOW_DDCD 0x00080000 /* delta data carrier detect */
+#define SHADOW_CTS 0x00100000 /* clear to send */
+#define SHADOW_DCD 0x00800000 /* data carrier detect */
+#define SHADOW_DTR 0x01000000 /* data terminal ready */
+#define SHADOW_RTS 0x02000000 /* request to send */
+#define SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */
+#define SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */
+#define SHADOW_LOOP 0x10000000 /* loopback enabled */
+
+/* bitmasks for SRTR_<A:B> */
+#define SRTR_CNT 0x00000fff /* reload value for RX timer */
+#define SRTR_CNT_VAL 0x0fff0000 /* current value of RX timer */
+#define SRTR_CNT_VAL_SHIFT 16
+#define SRTR_HZ 16000 /* SRTR clock frequency */
+
+/* bitmasks for SIO_IR, SIO_IEC and SIO_IES */
+#define SIO_IR_SA_TX_MT 0x00000001 /* Serial port A TX empty */
+#define SIO_IR_SA_RX_FULL 0x00000002 /* port A RX buf full */
+#define SIO_IR_SA_RX_HIGH 0x00000004 /* port A RX hiwat */
+#define SIO_IR_SA_RX_TIMER 0x00000008 /* port A RX timeout */
+#define SIO_IR_SA_DELTA_DCD 0x00000010 /* port A delta DCD */
+#define SIO_IR_SA_DELTA_CTS 0x00000020 /* port A delta CTS */
+#define SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */
+#define SIO_IR_SA_TX_EXPLICIT 0x00000080 /* port A explicit TX thru */
+#define SIO_IR_SA_MEMERR 0x00000100 /* port A PCI error */
+#define SIO_IR_SB_TX_MT 0x00000200
+#define SIO_IR_SB_RX_FULL 0x00000400
+#define SIO_IR_SB_RX_HIGH 0x00000800
+#define SIO_IR_SB_RX_TIMER 0x00001000
+#define SIO_IR_SB_DELTA_DCD 0x00002000
+#define SIO_IR_SB_DELTA_CTS 0x00004000
+#define SIO_IR_SB_INT 0x00008000
+#define SIO_IR_SB_TX_EXPLICIT 0x00010000
+#define SIO_IR_SB_MEMERR 0x00020000
+#define SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */
+#define SIO_IR_PP_INTA 0x00080000 /* PP context A thru */
+#define SIO_IR_PP_INTB 0x00100000 /* PP context B thru */
+#define SIO_IR_PP_MEMERR 0x00200000 /* PP PCI error */
+#define SIO_IR_KBD_INT 0x00400000 /* kbd/mouse intr */
+#define SIO_IR_RT_INT 0x08000000 /* RT output pulse */
+#define SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */
+#define SIO_IR_GEN_INT_SHIFT 28
+
+/* per device interrupt masks */
+#define SIO_IR_SA (SIO_IR_SA_TX_MT | \
+ SIO_IR_SA_RX_FULL | \
+ SIO_IR_SA_RX_HIGH | \
+ SIO_IR_SA_RX_TIMER | \
+ SIO_IR_SA_DELTA_DCD | \
+ SIO_IR_SA_DELTA_CTS | \
+ SIO_IR_SA_INT | \
+ SIO_IR_SA_TX_EXPLICIT | \
+ SIO_IR_SA_MEMERR)
+
+#define SIO_IR_SB (SIO_IR_SB_TX_MT | \
+ SIO_IR_SB_RX_FULL | \
+ SIO_IR_SB_RX_HIGH | \
+ SIO_IR_SB_RX_TIMER | \
+ SIO_IR_SB_DELTA_DCD | \
+ SIO_IR_SB_DELTA_CTS | \
+ SIO_IR_SB_INT | \
+ SIO_IR_SB_TX_EXPLICIT | \
+ SIO_IR_SB_MEMERR)
+
+#define SIO_IR_PP (SIO_IR_PP_INT | SIO_IR_PP_INTA | \
+ SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)
+#define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
+
+/* bitmasks for SIO_CR */
+#define SIO_CR_CMD_PULSE_SHIFT 15
+#define SIO_CR_SER_A_BASE_SHIFT 1
+#define SIO_CR_SER_B_BASE_SHIFT 8
+#define SIO_CR_ARB_DIAG 0x00380000 /* cur !enet PCI requet (ro) */
+#define SIO_CR_ARB_DIAG_TXA 0x00000000
+#define SIO_CR_ARB_DIAG_RXA 0x00080000
+#define SIO_CR_ARB_DIAG_TXB 0x00100000
+#define SIO_CR_ARB_DIAG_RXB 0x00180000
+#define SIO_CR_ARB_DIAG_PP 0x00200000
+#define SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */
+
+/* defs for some of the generic I/O pins */
+#define GPCR_PHY_RESET 0x20 /* pin is output to PHY reset */
+#define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */
+#define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */
+
+#define GPPR_PHY_RESET_PIN 5 /* GIO pin controlling phy reset */
+#define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin cntrling uartb modeselect */
+#define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin cntrling uarta modeselect */
+
+#endif /* IA64_SN_IOC3_H */
diff --git a/kernel/arch/ia64/include/asm/sn/klconfig.h b/kernel/arch/ia64/include/asm/sn/klconfig.h
new file mode 100644
index 000000000..bcbf209d6
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/klconfig.h
@@ -0,0 +1,246 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/klconfig.h>.
+ *
+ * Copyright (C) 1992-1997,1999,2001-2004 Silicon Graphics, Inc. All Rights Reserved.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_IA64_SN_KLCONFIG_H
+#define _ASM_IA64_SN_KLCONFIG_H
+
+/*
+ * The KLCONFIG structures store info about the various BOARDs found
+ * during Hardware Discovery. In addition, it stores info about the
+ * components found on the BOARDs.
+ */
+
+typedef s32 klconf_off_t;
+
+
+/* Functions/macros needed to use this structure */
+
+typedef struct kl_config_hdr {
+ char pad[20];
+ klconf_off_t ch_board_info; /* the link list of boards */
+ char pad0[88];
+} kl_config_hdr_t;
+
+
+#define NODE_OFFSET_TO_LBOARD(nasid,off) (lboard_t*)(GLOBAL_CAC_ADDR((nasid), (off)))
+
+/*
+ * The KLCONFIG area is organized as a LINKED LIST of BOARDs. A BOARD
+ * can be either 'LOCAL' or 'REMOTE'. LOCAL means it is attached to
+ * the LOCAL/current NODE. REMOTE means it is attached to a different
+ * node.(TBD - Need a way to treat ROUTER boards.)
+ *
+ * There are 2 different structures to represent these boards -
+ * lboard - Local board, rboard - remote board. These 2 structures
+ * can be arbitrarily mixed in the LINKED LIST of BOARDs. (Refer
+ * Figure below). The first byte of the rboard or lboard structure
+ * is used to find out its type - no unions are used.
+ * If it is a lboard, then the config info of this board will be found
+ * on the local node. (LOCAL NODE BASE + offset value gives pointer to
+ * the structure.
+ * If it is a rboard, the local structure contains the node number
+ * and the offset of the beginning of the LINKED LIST on the remote node.
+ * The details of the hardware on a remote node can be built locally,
+ * if required, by reading the LINKED LIST on the remote node and
+ * ignoring all the rboards on that node.
+ *
+ * The local node uses the REMOTE NODE NUMBER + OFFSET to point to the
+ * First board info on the remote node. The remote node list is
+ * traversed as the local list, using the REMOTE BASE ADDRESS and not
+ * the local base address and ignoring all rboard values.
+ *
+ *
+ KLCONFIG
+
+ +------------+ +------------+ +------------+ +------------+
+ | lboard | +-->| lboard | +-->| rboard | +-->| lboard |
+ +------------+ | +------------+ | +------------+ | +------------+
+ | board info | | | board info | | |errinfo,bptr| | | board info |
+ +------------+ | +------------+ | +------------+ | +------------+
+ | offset |--+ | offset |--+ | offset |--+ |offset=NULL |
+ +------------+ +------------+ +------------+ +------------+
+
+
+ +------------+
+ | board info |
+ +------------+ +--------------------------------+
+ | compt 1 |------>| type, rev, diaginfo, size ... | (CPU)
+ +------------+ +--------------------------------+
+ | compt 2 |--+
+ +------------+ | +--------------------------------+
+ | ... | +--->| type, rev, diaginfo, size ... | (MEM_BANK)
+ +------------+ +--------------------------------+
+ | errinfo |--+
+ +------------+ | +--------------------------------+
+ +--->|r/l brd errinfo,compt err flags |
+ +--------------------------------+
+
+ *
+ * Each BOARD consists of COMPONENTs and the BOARD structure has
+ * pointers (offsets) to its COMPONENT structure.
+ * The COMPONENT structure has version info, size and speed info, revision,
+ * error info and the NIC info. This structure can accommodate any
+ * BOARD with arbitrary COMPONENT composition.
+ *
+ * The ERRORINFO part of each BOARD has error information
+ * that describes errors about the BOARD itself. It also has flags to
+ * indicate the COMPONENT(s) on the board that have errors. The error
+ * information specific to the COMPONENT is present in the respective
+ * COMPONENT structure.
+ *
+ * The ERRORINFO structure is also treated like a COMPONENT, ie. the
+ * BOARD has pointers(offset) to the ERRORINFO structure. The rboard
+ * structure also has a pointer to the ERRORINFO structure. This is
+ * the place to store ERRORINFO about a REMOTE NODE, if the HUB on
+ * that NODE is not working or if the REMOTE MEMORY is BAD. In cases where
+ * only the CPU of the REMOTE NODE is disabled, the ERRORINFO pointer can
+ * be a NODE NUMBER, REMOTE OFFSET combination, pointing to error info
+ * which is present on the REMOTE NODE.(TBD)
+ * REMOTE ERRINFO can be stored on any of the nearest nodes
+ * or on all the nearest nodes.(TBD)
+ * Like BOARD structures, REMOTE ERRINFO structures can be built locally
+ * using the rboard errinfo pointer.
+ *
+ * In order to get useful information from this Data organization, a set of
+ * interface routines are provided (TBD). The important thing to remember while
+ * manipulating the structures, is that, the NODE number information should
+ * be used. If the NODE is non-zero (remote) then each offset should
+ * be added to the REMOTE BASE ADDR else it should be added to the LOCAL BASE ADDR.
+ * This includes offsets for BOARDS, COMPONENTS and ERRORINFO.
+ *
+ * Note that these structures do not provide much info about connectivity.
+ * That info will be part of HWGRAPH, which is an extension of the cfg_t
+ * data structure. (ref IP27prom/cfg.h) It has to be extended to include
+ * the IO part of the Network(TBD).
+ *
+ * The data structures below define the above concepts.
+ */
+
+
+/*
+ * BOARD classes
+ */
+
+#define KLCLASS_MASK 0xf0
+#define KLCLASS_NONE 0x00
+#define KLCLASS_NODE 0x10 /* CPU, Memory and HUB board */
+#define KLCLASS_CPU KLCLASS_NODE
+#define KLCLASS_IO 0x20 /* BaseIO, 4 ch SCSI, ethernet, FDDI
+ and the non-graphics widget boards */
+#define KLCLASS_ROUTER 0x30 /* Router board */
+#define KLCLASS_MIDPLANE 0x40 /* We need to treat this as a board
+ so that we can record error info */
+#define KLCLASS_IOBRICK 0x70 /* IP35 iobrick */
+#define KLCLASS_MAX 8 /* Bump this if a new CLASS is added */
+
+#define KLCLASS(_x) ((_x) & KLCLASS_MASK)
+
+
+/*
+ * board types
+ */
+
+#define KLTYPE_MASK 0x0f
+#define KLTYPE(_x) ((_x) & KLTYPE_MASK)
+
+#define KLTYPE_SNIA (KLCLASS_CPU | 0x1)
+#define KLTYPE_TIO (KLCLASS_CPU | 0x2)
+
+#define KLTYPE_ROUTER (KLCLASS_ROUTER | 0x1)
+#define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3)
+#define KLTYPE_REPEATER_ROUTER (KLCLASS_ROUTER | 0x4)
+
+#define KLTYPE_IOBRICK_XBOW (KLCLASS_MIDPLANE | 0x2)
+
+#define KLTYPE_IOBRICK (KLCLASS_IOBRICK | 0x0)
+#define KLTYPE_NBRICK (KLCLASS_IOBRICK | 0x4)
+#define KLTYPE_PXBRICK (KLCLASS_IOBRICK | 0x6)
+#define KLTYPE_IXBRICK (KLCLASS_IOBRICK | 0x7)
+#define KLTYPE_CGBRICK (KLCLASS_IOBRICK | 0x8)
+#define KLTYPE_OPUSBRICK (KLCLASS_IOBRICK | 0x9)
+#define KLTYPE_SABRICK (KLCLASS_IOBRICK | 0xa)
+#define KLTYPE_IABRICK (KLCLASS_IOBRICK | 0xb)
+#define KLTYPE_PABRICK (KLCLASS_IOBRICK | 0xc)
+#define KLTYPE_GABRICK (KLCLASS_IOBRICK | 0xd)
+
+
+/*
+ * board structures
+ */
+
+#define MAX_COMPTS_PER_BRD 24
+
+typedef struct lboard_s {
+ klconf_off_t brd_next_any; /* Next BOARD */
+ unsigned char struct_type; /* type of structure, local or remote */
+ unsigned char brd_type; /* type+class */
+ unsigned char brd_sversion; /* version of this structure */
+ unsigned char brd_brevision; /* board revision */
+ unsigned char brd_promver; /* board prom version, if any */
+ unsigned char brd_flags; /* Enabled, Disabled etc */
+ unsigned char brd_slot; /* slot number */
+ unsigned short brd_debugsw; /* Debug switches */
+ geoid_t brd_geoid; /* geo id */
+ partid_t brd_partition; /* Partition number */
+ unsigned short brd_diagval; /* diagnostic value */
+ unsigned short brd_diagparm; /* diagnostic parameter */
+ unsigned char brd_inventory; /* inventory history */
+ unsigned char brd_numcompts; /* Number of components */
+ nic_t brd_nic; /* Number in CAN */
+ nasid_t brd_nasid; /* passed parameter */
+ klconf_off_t brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */
+ klconf_off_t brd_errinfo; /* Board's error information */
+ struct lboard_s *brd_parent; /* Logical parent for this brd */
+ char pad0[4];
+ unsigned char brd_confidence; /* confidence that the board is bad */
+ nasid_t brd_owner; /* who owns this board */
+ unsigned char brd_nic_flags; /* To handle 8 more NICs */
+ char pad1[24]; /* future expansion */
+ char brd_name[32];
+ nasid_t brd_next_same_host; /* host of next brd w/same nasid */
+ klconf_off_t brd_next_same; /* Next BOARD with same nasid */
+} lboard_t;
+
+/*
+ * Generic info structure. This stores common info about a
+ * component.
+ */
+
+typedef struct klinfo_s { /* Generic info */
+ unsigned char struct_type; /* type of this structure */
+ unsigned char struct_version; /* version of this structure */
+ unsigned char flags; /* Enabled, disabled etc */
+ unsigned char revision; /* component revision */
+ unsigned short diagval; /* result of diagnostics */
+ unsigned short diagparm; /* diagnostic parameter */
+ unsigned char inventory; /* previous inventory status */
+ unsigned short partid; /* widget part number */
+ nic_t nic; /* MUst be aligned properly */
+ unsigned char physid; /* physical id of component */
+ unsigned int virtid; /* virtual id as seen by system */
+ unsigned char widid; /* Widget id - if applicable */
+ nasid_t nasid; /* node number - from parent */
+ char pad1; /* pad out structure. */
+ char pad2; /* pad out structure. */
+ void *data;
+ klconf_off_t errinfo; /* component specific errors */
+ unsigned short pad3; /* pci fields have moved over to */
+ unsigned short pad4; /* klbri_t */
+} klinfo_t ;
+
+
+static inline lboard_t *find_lboard_next(lboard_t * brd)
+{
+ if (brd && brd->brd_next_any)
+ return NODE_OFFSET_TO_LBOARD(NASID_GET(brd), brd->brd_next_any);
+ return NULL;
+}
+
+#endif /* _ASM_IA64_SN_KLCONFIG_H */
diff --git a/kernel/arch/ia64/include/asm/sn/l1.h b/kernel/arch/ia64/include/asm/sn/l1.h
new file mode 100644
index 000000000..344bf44bb
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/l1.h
@@ -0,0 +1,51 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992-1997,2000-2004 Silicon Graphics, Inc. All Rights Reserved.
+ */
+
+#ifndef _ASM_IA64_SN_L1_H
+#define _ASM_IA64_SN_L1_H
+
+/* brick type response codes */
+#define L1_BRICKTYPE_PX 0x23 /* # */
+#define L1_BRICKTYPE_PE 0x25 /* % */
+#define L1_BRICKTYPE_N_p0 0x26 /* & */
+#define L1_BRICKTYPE_IP45 0x34 /* 4 */
+#define L1_BRICKTYPE_IP41 0x35 /* 5 */
+#define L1_BRICKTYPE_TWISTER 0x36 /* 6 */ /* IP53 & ROUTER */
+#define L1_BRICKTYPE_IX 0x3d /* = */
+#define L1_BRICKTYPE_IP34 0x61 /* a */
+#define L1_BRICKTYPE_GA 0x62 /* b */
+#define L1_BRICKTYPE_C 0x63 /* c */
+#define L1_BRICKTYPE_OPUS_TIO 0x66 /* f */
+#define L1_BRICKTYPE_I 0x69 /* i */
+#define L1_BRICKTYPE_N 0x6e /* n */
+#define L1_BRICKTYPE_OPUS 0x6f /* o */
+#define L1_BRICKTYPE_P 0x70 /* p */
+#define L1_BRICKTYPE_R 0x72 /* r */
+#define L1_BRICKTYPE_CHI_CG 0x76 /* v */
+#define L1_BRICKTYPE_X 0x78 /* x */
+#define L1_BRICKTYPE_X2 0x79 /* y */
+#define L1_BRICKTYPE_SA 0x5e /* ^ */
+#define L1_BRICKTYPE_PA 0x6a /* j */
+#define L1_BRICKTYPE_IA 0x6b /* k */
+#define L1_BRICKTYPE_ATHENA 0x2b /* + */
+#define L1_BRICKTYPE_DAYTONA 0x7a /* z */
+#define L1_BRICKTYPE_1932 0x2c /* . */
+#define L1_BRICKTYPE_191010 0x2e /* , */
+
+/* board type response codes */
+#define L1_BOARDTYPE_IP69 0x0100 /* CA */
+#define L1_BOARDTYPE_IP63 0x0200 /* CB */
+#define L1_BOARDTYPE_BASEIO 0x0300 /* IB */
+#define L1_BOARDTYPE_PCIE2SLOT 0x0400 /* IC */
+#define L1_BOARDTYPE_PCIX3SLOT 0x0500 /* ID */
+#define L1_BOARDTYPE_PCIXPCIE4SLOT 0x0600 /* IE */
+#define L1_BOARDTYPE_ABACUS 0x0700 /* AB */
+#define L1_BOARDTYPE_DAYTONA 0x0800 /* AD */
+#define L1_BOARDTYPE_INVAL (-1) /* invalid brick type */
+
+#endif /* _ASM_IA64_SN_L1_H */
diff --git a/kernel/arch/ia64/include/asm/sn/leds.h b/kernel/arch/ia64/include/asm/sn/leds.h
new file mode 100644
index 000000000..66cf8c4d9
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/leds.h
@@ -0,0 +1,33 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_LEDS_H
+#define _ASM_IA64_SN_LEDS_H
+
+#include <asm/sn/addrs.h>
+#include <asm/sn/pda.h>
+#include <asm/sn/shub_mmr.h>
+
+#define LED0 (LOCAL_MMR_ADDR(SH_REAL_JUNK_BUS_LED0))
+#define LED_CPU_SHIFT 16
+
+#define LED_CPU_HEARTBEAT 0x01
+#define LED_CPU_ACTIVITY 0x02
+#define LED_ALWAYS_SET 0x00
+
+/*
+ * Basic macros for flashing the LEDS on an SGI SN.
+ */
+
+static __inline__ void
+set_led_bits(u8 value, u8 mask)
+{
+ pda->led_state = (pda->led_state & ~mask) | (value & mask);
+ *pda->led_address = (short) pda->led_state;
+}
+
+#endif /* _ASM_IA64_SN_LEDS_H */
+
diff --git a/kernel/arch/ia64/include/asm/sn/module.h b/kernel/arch/ia64/include/asm/sn/module.h
new file mode 100644
index 000000000..734e980ec
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/module.h
@@ -0,0 +1,127 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_MODULE_H
+#define _ASM_IA64_SN_MODULE_H
+
+/* parameter for format_module_id() */
+#define MODULE_FORMAT_BRIEF 1
+#define MODULE_FORMAT_LONG 2
+#define MODULE_FORMAT_LCD 3
+
+/*
+ * Module id format
+ *
+ * 31-16 Rack ID (encoded class, group, number - 16-bit unsigned int)
+ * 15-8 Brick type (8-bit ascii character)
+ * 7-0 Bay (brick position in rack (0-63) - 8-bit unsigned int)
+ *
+ */
+
+/*
+ * Macros for getting the brick type
+ */
+#define MODULE_BTYPE_MASK 0xff00
+#define MODULE_BTYPE_SHFT 8
+#define MODULE_GET_BTYPE(_m) (((_m) & MODULE_BTYPE_MASK) >> MODULE_BTYPE_SHFT)
+#define MODULE_BT_TO_CHAR(_b) ((char)(_b))
+#define MODULE_GET_BTCHAR(_m) (MODULE_BT_TO_CHAR(MODULE_GET_BTYPE(_m)))
+
+/*
+ * Macros for getting the rack ID.
+ */
+#define MODULE_RACK_MASK 0xffff0000
+#define MODULE_RACK_SHFT 16
+#define MODULE_GET_RACK(_m) (((_m) & MODULE_RACK_MASK) >> MODULE_RACK_SHFT)
+
+/*
+ * Macros for getting the brick position
+ */
+#define MODULE_BPOS_MASK 0x00ff
+#define MODULE_BPOS_SHFT 0
+#define MODULE_GET_BPOS(_m) (((_m) & MODULE_BPOS_MASK) >> MODULE_BPOS_SHFT)
+
+/*
+ * Macros for encoding and decoding rack IDs
+ * A rack number consists of three parts:
+ * class (0==CPU/mixed, 1==I/O), group, number
+ *
+ * Rack number is stored just as it is displayed on the screen:
+ * a 3-decimal-digit number.
+ */
+#define RACK_CLASS_DVDR 100
+#define RACK_GROUP_DVDR 10
+#define RACK_NUM_DVDR 1
+
+#define RACK_CREATE_RACKID(_c, _g, _n) ((_c) * RACK_CLASS_DVDR + \
+ (_g) * RACK_GROUP_DVDR + (_n) * RACK_NUM_DVDR)
+
+#define RACK_GET_CLASS(_r) ((_r) / RACK_CLASS_DVDR)
+#define RACK_GET_GROUP(_r) (((_r) - RACK_GET_CLASS(_r) * \
+ RACK_CLASS_DVDR) / RACK_GROUP_DVDR)
+#define RACK_GET_NUM(_r) (((_r) - RACK_GET_CLASS(_r) * \
+ RACK_CLASS_DVDR - RACK_GET_GROUP(_r) * \
+ RACK_GROUP_DVDR) / RACK_NUM_DVDR)
+
+/*
+ * Macros for encoding and decoding rack IDs
+ * A rack number consists of three parts:
+ * class 1 bit, 0==CPU/mixed, 1==I/O
+ * group 2 bits for CPU/mixed, 3 bits for I/O
+ * number 3 bits for CPU/mixed, 2 bits for I/O (1 based)
+ */
+#define RACK_GROUP_BITS(_r) (RACK_GET_CLASS(_r) ? 3 : 2)
+#define RACK_NUM_BITS(_r) (RACK_GET_CLASS(_r) ? 2 : 3)
+
+#define RACK_CLASS_MASK(_r) 0x20
+#define RACK_CLASS_SHFT(_r) 5
+#define RACK_ADD_CLASS(_r, _c) \
+ ((_r) |= (_c) << RACK_CLASS_SHFT(_r) & RACK_CLASS_MASK(_r))
+
+#define RACK_GROUP_SHFT(_r) RACK_NUM_BITS(_r)
+#define RACK_GROUP_MASK(_r) \
+ ( (((unsigned)1<<RACK_GROUP_BITS(_r)) - 1) << RACK_GROUP_SHFT(_r) )
+#define RACK_ADD_GROUP(_r, _g) \
+ ((_r) |= (_g) << RACK_GROUP_SHFT(_r) & RACK_GROUP_MASK(_r))
+
+#define RACK_NUM_SHFT(_r) 0
+#define RACK_NUM_MASK(_r) \
+ ( (((unsigned)1<<RACK_NUM_BITS(_r)) - 1) << RACK_NUM_SHFT(_r) )
+#define RACK_ADD_NUM(_r, _n) \
+ ((_r) |= ((_n) - 1) << RACK_NUM_SHFT(_r) & RACK_NUM_MASK(_r))
+
+
+/*
+ * Brick type definitions
+ */
+#define MAX_BRICK_TYPES 256 /* brick type is stored as uchar */
+
+extern char brick_types[];
+
+#define MODULE_CBRICK 0
+#define MODULE_RBRICK 1
+#define MODULE_IBRICK 2
+#define MODULE_KBRICK 3
+#define MODULE_XBRICK 4
+#define MODULE_DBRICK 5
+#define MODULE_PBRICK 6
+#define MODULE_NBRICK 7
+#define MODULE_PEBRICK 8
+#define MODULE_PXBRICK 9
+#define MODULE_IXBRICK 10
+#define MODULE_CGBRICK 11
+#define MODULE_OPUSBRICK 12
+#define MODULE_SABRICK 13 /* TIO BringUp Brick */
+#define MODULE_IABRICK 14
+#define MODULE_PABRICK 15
+#define MODULE_GABRICK 16
+#define MODULE_OPUS_TIO 17 /* OPUS TIO Riser */
+
+extern char brick_types[];
+extern void format_module_id(char *, moduleid_t, int);
+
+#endif /* _ASM_IA64_SN_MODULE_H */
diff --git a/kernel/arch/ia64/include/asm/sn/mspec.h b/kernel/arch/ia64/include/asm/sn/mspec.h
new file mode 100644
index 000000000..c1d3c50c3
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/mspec.h
@@ -0,0 +1,59 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001-2008 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_MSPEC_H
+#define _ASM_IA64_SN_MSPEC_H
+
+#define FETCHOP_VAR_SIZE 64 /* 64 byte per fetchop variable */
+
+#define FETCHOP_LOAD 0
+#define FETCHOP_INCREMENT 8
+#define FETCHOP_DECREMENT 16
+#define FETCHOP_CLEAR 24
+
+#define FETCHOP_STORE 0
+#define FETCHOP_AND 24
+#define FETCHOP_OR 32
+
+#define FETCHOP_CLEAR_CACHE 56
+
+#define FETCHOP_LOAD_OP(addr, op) ( \
+ *(volatile long *)((char*) (addr) + (op)))
+
+#define FETCHOP_STORE_OP(addr, op, x) ( \
+ *(volatile long *)((char*) (addr) + (op)) = (long) (x))
+
+#ifdef __KERNEL__
+
+/*
+ * Each Atomic Memory Operation (amo, formerly known as fetchop)
+ * variable is 64 bytes long. The first 8 bytes are used. The
+ * remaining 56 bytes are unaddressable due to the operation taking
+ * that portion of the address.
+ *
+ * NOTE: The amo structure _MUST_ be placed in either the first or second
+ * half of the cache line. The cache line _MUST NOT_ be used for anything
+ * other than additional amo entries. This is because there are two
+ * addresses which reference the same physical cache line. One will
+ * be a cached entry with the memory type bits all set. This address
+ * may be loaded into processor cache. The amo will be referenced
+ * uncached via the memory special memory type. If any portion of the
+ * cached cache-line is modified, when that line is flushed, it will
+ * overwrite the uncached value in physical memory and lead to
+ * inconsistency.
+ */
+struct amo {
+ u64 variable;
+ u64 unused[7];
+};
+
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_IA64_SN_MSPEC_H */
diff --git a/kernel/arch/ia64/include/asm/sn/nodepda.h b/kernel/arch/ia64/include/asm/sn/nodepda.h
new file mode 100644
index 000000000..7c8b4710f
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/nodepda.h
@@ -0,0 +1,82 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_NODEPDA_H
+#define _ASM_IA64_SN_NODEPDA_H
+
+
+#include <asm/irq.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/bte.h>
+
+/*
+ * NUMA Node-Specific Data structures are defined in this file.
+ * In particular, this is the location of the node PDA.
+ * A pointer to the right node PDA is saved in each CPU PDA.
+ */
+
+/*
+ * Node-specific data structure.
+ *
+ * One of these structures is allocated on each node of a NUMA system.
+ *
+ * This structure provides a convenient way of keeping together
+ * all per-node data structures.
+ */
+struct phys_cpuid {
+ short nasid;
+ char subnode;
+ char slice;
+};
+
+struct nodepda_s {
+ void *pdinfo; /* Platform-dependent per-node info */
+
+ /*
+ * The BTEs on this node are shared by the local cpus
+ */
+ struct bteinfo_s bte_if[MAX_BTES_PER_NODE]; /* Virtual Interface */
+ struct timer_list bte_recovery_timer;
+ spinlock_t bte_recovery_lock;
+
+ /*
+ * Array of pointers to the nodepdas for each node.
+ */
+ struct nodepda_s *pernode_pdaindr[MAX_COMPACT_NODES];
+
+ /*
+ * Array of physical cpu identifiers. Indexed by cpuid.
+ */
+ struct phys_cpuid phys_cpuid[NR_CPUS];
+ spinlock_t ptc_lock ____cacheline_aligned_in_smp;
+};
+
+typedef struct nodepda_s nodepda_t;
+
+/*
+ * Access Functions for node PDA.
+ * Since there is one nodepda for each node, we need a convenient mechanism
+ * to access these nodepdas without cluttering code with #ifdefs.
+ * The next set of definitions provides this.
+ * Routines are expected to use
+ *
+ * sn_nodepda - to access node PDA for the node on which code is running
+ * NODEPDA(cnodeid) - to access node PDA for cnodeid
+ */
+
+DECLARE_PER_CPU(struct nodepda_s *, __sn_nodepda);
+#define sn_nodepda __this_cpu_read(__sn_nodepda)
+#define NODEPDA(cnodeid) (sn_nodepda->pernode_pdaindr[cnodeid])
+
+/*
+ * Check if given a compact node id the corresponding node has all the
+ * cpus disabled.
+ */
+#define is_headless_node(cnodeid) (nr_cpus_node(cnodeid) == 0)
+
+#endif /* _ASM_IA64_SN_NODEPDA_H */
diff --git a/kernel/arch/ia64/include/asm/sn/pcibr_provider.h b/kernel/arch/ia64/include/asm/sn/pcibr_provider.h
new file mode 100644
index 000000000..da205b7cd
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/pcibr_provider.h
@@ -0,0 +1,150 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992-1997,2000-2006 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
+#define _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
+
+#include <asm/sn/intr.h>
+#include <asm/sn/pcibus_provider_defs.h>
+
+/* Workarounds */
+#define PV907516 (1 << 1) /* TIOCP: Don't write the write buffer flush reg */
+
+#define BUSTYPE_MASK 0x1
+
+/* Macros given a pcibus structure */
+#define IS_PCIX(ps) ((ps)->pbi_bridge_mode & BUSTYPE_MASK)
+#define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \
+ asic == PCIIO_ASIC_TYPE_TIOCP)
+#define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
+#define IS_TIOCP_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_TIOCP)
+
+
+/*
+ * The different PCI Bridge types supported on the SGI Altix platforms
+ */
+#define PCIBR_BRIDGETYPE_UNKNOWN -1
+#define PCIBR_BRIDGETYPE_PIC 2
+#define PCIBR_BRIDGETYPE_TIOCP 3
+
+/*
+ * Bridge 64bit Direct Map Attributes
+ */
+#define PCI64_ATTR_PREF (1ull << 59)
+#define PCI64_ATTR_PREC (1ull << 58)
+#define PCI64_ATTR_VIRTUAL (1ull << 57)
+#define PCI64_ATTR_BAR (1ull << 56)
+#define PCI64_ATTR_SWAP (1ull << 55)
+#define PCI64_ATTR_VIRTUAL1 (1ull << 54)
+
+#define PCI32_LOCAL_BASE 0
+#define PCI32_MAPPED_BASE 0x40000000
+#define PCI32_DIRECT_BASE 0x80000000
+
+#define IS_PCI32_MAPPED(x) ((u64)(x) < PCI32_DIRECT_BASE && \
+ (u64)(x) >= PCI32_MAPPED_BASE)
+#define IS_PCI32_DIRECT(x) ((u64)(x) >= PCI32_MAPPED_BASE)
+
+
+/*
+ * Bridge PMU Address Transaltion Entry Attibutes
+ */
+#define PCI32_ATE_V (0x1 << 0)
+#define PCI32_ATE_CO (0x1 << 1) /* PIC ASIC ONLY */
+#define PCI32_ATE_PIO (0x1 << 1) /* TIOCP ASIC ONLY */
+#define PCI32_ATE_MSI (0x1 << 2)
+#define PCI32_ATE_PREF (0x1 << 3)
+#define PCI32_ATE_BAR (0x1 << 4)
+#define PCI32_ATE_ADDR_SHFT 12
+
+#define MINIMAL_ATES_REQUIRED(addr, size) \
+ (IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
+
+#define MINIMAL_ATE_FLAG(addr, size) \
+ (MINIMAL_ATES_REQUIRED((u64)addr, size) ? 1 : 0)
+
+/* bit 29 of the pci address is the SWAP bit */
+#define ATE_SWAPSHIFT 29
+#define ATE_SWAP_ON(x) ((x) |= (1 << ATE_SWAPSHIFT))
+#define ATE_SWAP_OFF(x) ((x) &= ~(1 << ATE_SWAPSHIFT))
+
+/*
+ * I/O page size
+ */
+#if PAGE_SIZE < 16384
+#define IOPFNSHIFT 12 /* 4K per mapped page */
+#else
+#define IOPFNSHIFT 14 /* 16K per mapped page */
+#endif
+
+#define IOPGSIZE (1 << IOPFNSHIFT)
+#define IOPG(x) ((x) >> IOPFNSHIFT)
+#define IOPGOFF(x) ((x) & (IOPGSIZE-1))
+
+#define PCIBR_DEV_SWAP_DIR (1ull << 19)
+#define PCIBR_CTRL_PAGE_SIZE (0x1 << 21)
+
+/*
+ * PMU resources.
+ */
+struct ate_resource{
+ u64 *ate;
+ u64 num_ate;
+ u64 lowest_free_index;
+};
+
+struct pcibus_info {
+ struct pcibus_bussoft pbi_buscommon; /* common header */
+ u32 pbi_moduleid;
+ short pbi_bridge_type;
+ short pbi_bridge_mode;
+
+ struct ate_resource pbi_int_ate_resource;
+ u64 pbi_int_ate_size;
+
+ u64 pbi_dir_xbase;
+ char pbi_hub_xid;
+
+ u64 pbi_devreg[8];
+
+ u32 pbi_valid_devices;
+ u32 pbi_enabled_devices;
+
+ spinlock_t pbi_lock;
+};
+
+extern int pcibr_init_provider(void);
+extern void *pcibr_bus_fixup(struct pcibus_bussoft *, struct pci_controller *);
+extern dma_addr_t pcibr_dma_map(struct pci_dev *, unsigned long, size_t, int type);
+extern dma_addr_t pcibr_dma_map_consistent(struct pci_dev *, unsigned long, size_t, int type);
+extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int);
+
+/*
+ * prototypes for the bridge asic register access routines in pcibr_reg.c
+ */
+extern void pcireg_control_bit_clr(struct pcibus_info *, u64);
+extern void pcireg_control_bit_set(struct pcibus_info *, u64);
+extern u64 pcireg_tflush_get(struct pcibus_info *);
+extern u64 pcireg_intr_status_get(struct pcibus_info *);
+extern void pcireg_intr_enable_bit_clr(struct pcibus_info *, u64);
+extern void pcireg_intr_enable_bit_set(struct pcibus_info *, u64);
+extern void pcireg_intr_addr_addr_set(struct pcibus_info *, int, u64);
+extern void pcireg_force_intr_set(struct pcibus_info *, int);
+extern u64 pcireg_wrb_flush_get(struct pcibus_info *, int);
+extern void pcireg_int_ate_set(struct pcibus_info *, int, u64);
+extern u64 __iomem * pcireg_int_ate_addr(struct pcibus_info *, int);
+extern void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
+extern void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
+extern int pcibr_ate_alloc(struct pcibus_info *, int);
+extern void pcibr_ate_free(struct pcibus_info *, int);
+extern void ate_write(struct pcibus_info *, int, int, u64);
+extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device,
+ void *resp, char **ssdt);
+extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device,
+ int action, void *resp);
+extern u16 sn_ioboard_to_pci_bus(struct pci_bus *pci_bus);
+#endif
diff --git a/kernel/arch/ia64/include/asm/sn/pcibus_provider_defs.h b/kernel/arch/ia64/include/asm/sn/pcibus_provider_defs.h
new file mode 100644
index 000000000..8f7c83d0f
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/pcibus_provider_defs.h
@@ -0,0 +1,68 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
+#define _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
+
+/*
+ * SN pci asic types. Do not ever renumber these or reuse values. The
+ * values must agree with what prom thinks they are.
+ */
+
+#define PCIIO_ASIC_TYPE_UNKNOWN 0
+#define PCIIO_ASIC_TYPE_PPB 1
+#define PCIIO_ASIC_TYPE_PIC 2
+#define PCIIO_ASIC_TYPE_TIOCP 3
+#define PCIIO_ASIC_TYPE_TIOCA 4
+#define PCIIO_ASIC_TYPE_TIOCE 5
+
+#define PCIIO_ASIC_MAX_TYPES 6
+
+/*
+ * Common pciio bus provider data. There should be one of these as the
+ * first field in any pciio based provider soft structure (e.g. pcibr_soft
+ * tioca_soft, etc).
+ */
+
+struct pcibus_bussoft {
+ u32 bs_asic_type; /* chipset type */
+ u32 bs_xid; /* xwidget id */
+ u32 bs_persist_busnum; /* Persistent Bus Number */
+ u32 bs_persist_segment; /* Segment Number */
+ u64 bs_legacy_io; /* legacy io pio addr */
+ u64 bs_legacy_mem; /* legacy mem pio addr */
+ u64 bs_base; /* widget base */
+ struct xwidget_info *bs_xwidget_info;
+};
+
+struct pci_controller;
+/*
+ * SN pci bus indirection
+ */
+
+struct sn_pcibus_provider {
+ dma_addr_t (*dma_map)(struct pci_dev *, unsigned long, size_t, int flags);
+ dma_addr_t (*dma_map_consistent)(struct pci_dev *, unsigned long, size_t, int flags);
+ void (*dma_unmap)(struct pci_dev *, dma_addr_t, int);
+ void * (*bus_fixup)(struct pcibus_bussoft *, struct pci_controller *);
+ void (*force_interrupt)(struct sn_irq_info *);
+ void (*target_interrupt)(struct sn_irq_info *);
+};
+
+/*
+ * Flags used by the map interfaces
+ * bits 3:0 specifies format of passed in address
+ * bit 4 specifies that address is to be used for MSI
+ */
+
+#define SN_DMA_ADDRTYPE(x) ((x) & 0xf)
+#define SN_DMA_ADDR_PHYS 1 /* address is an xio address. */
+#define SN_DMA_ADDR_XIO 2 /* address is phys memory */
+#define SN_DMA_MSI 0x10 /* Bus address is to be used for MSI */
+
+extern struct sn_pcibus_provider *sn_pci_provider[];
+#endif /* _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H */
diff --git a/kernel/arch/ia64/include/asm/sn/pcidev.h b/kernel/arch/ia64/include/asm/sn/pcidev.h
new file mode 100644
index 000000000..1c2382cea
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/pcidev.h
@@ -0,0 +1,85 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2006 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PCI_PCIDEV_H
+#define _ASM_IA64_SN_PCI_PCIDEV_H
+
+#include <linux/pci.h>
+
+/*
+ * In ia64, pci_dev->sysdata must be a *pci_controller. To provide access to
+ * the pcidev_info structs for all devices under a controller, we keep a
+ * list of pcidev_info under pci_controller->platform_data.
+ */
+struct sn_platform_data {
+ void *provider_soft;
+ struct list_head pcidev_info;
+};
+
+#define SN_PLATFORM_DATA(busdev) \
+ ((struct sn_platform_data *)(PCI_CONTROLLER(busdev)->platform_data))
+
+#define SN_PCIDEV_INFO(dev) sn_pcidev_info_get(dev)
+
+/*
+ * Given a pci_bus, return the sn pcibus_bussoft struct. Note that
+ * this only works for root busses, not for busses represented by PPB's.
+ */
+
+#define SN_PCIBUS_BUSSOFT(pci_bus) \
+ ((struct pcibus_bussoft *)(SN_PLATFORM_DATA(pci_bus)->provider_soft))
+
+#define SN_PCIBUS_BUSSOFT_INFO(pci_bus) \
+ ((struct pcibus_info *)(SN_PLATFORM_DATA(pci_bus)->provider_soft))
+/*
+ * Given a struct pci_dev, return the sn pcibus_bussoft struct. Note
+ * that this is not equivalent to SN_PCIBUS_BUSSOFT(pci_dev->bus) due
+ * due to possible PPB's in the path.
+ */
+
+#define SN_PCIDEV_BUSSOFT(pci_dev) \
+ (SN_PCIDEV_INFO(pci_dev)->pdi_host_pcidev_info->pdi_pcibus_info)
+
+#define SN_PCIDEV_BUSPROVIDER(pci_dev) \
+ (SN_PCIDEV_INFO(pci_dev)->pdi_provider)
+
+#define PCIIO_BUS_NONE 255 /* bus 255 reserved */
+#define PCIIO_SLOT_NONE 255
+#define PCIIO_FUNC_NONE 255
+#define PCIIO_VENDOR_ID_NONE (-1)
+
+struct pcidev_info {
+ u64 pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */
+ u64 pdi_slot_host_handle; /* Bus and devfn Host pci_dev */
+
+ struct pcibus_bussoft *pdi_pcibus_info; /* Kernel common bus soft */
+ struct pcidev_info *pdi_host_pcidev_info; /* Kernel Host pci_dev */
+ struct pci_dev *pdi_linux_pcidev; /* Kernel pci_dev */
+
+ struct sn_irq_info *pdi_sn_irq_info;
+ struct sn_pcibus_provider *pdi_provider; /* sn pci ops */
+ struct pci_dev *host_pci_dev; /* host bus link */
+ struct list_head pdi_list; /* List of pcidev_info */
+};
+
+extern void sn_irq_fixup(struct pci_dev *pci_dev,
+ struct sn_irq_info *sn_irq_info);
+extern void sn_irq_unfixup(struct pci_dev *pci_dev);
+extern struct pcidev_info * sn_pcidev_info_get(struct pci_dev *);
+extern void sn_bus_fixup(struct pci_bus *);
+extern void sn_acpi_bus_fixup(struct pci_bus *);
+extern void sn_common_bus_fixup(struct pci_bus *, struct pcibus_bussoft *);
+extern void sn_bus_store_sysdata(struct pci_dev *dev);
+extern void sn_bus_free_sysdata(void);
+extern void sn_generate_path(struct pci_bus *pci_bus, char *address);
+extern void sn_io_slot_fixup(struct pci_dev *);
+extern void sn_acpi_slot_fixup(struct pci_dev *);
+extern void sn_pci_fixup_slot(struct pci_dev *dev, struct pcidev_info *,
+ struct sn_irq_info *);
+extern void sn_pci_unfixup_slot(struct pci_dev *dev);
+extern void sn_irq_lh_init(void);
+#endif /* _ASM_IA64_SN_PCI_PCIDEV_H */
diff --git a/kernel/arch/ia64/include/asm/sn/pda.h b/kernel/arch/ia64/include/asm/sn/pda.h
new file mode 100644
index 000000000..22ae358c8
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/pda.h
@@ -0,0 +1,68 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PDA_H
+#define _ASM_IA64_SN_PDA_H
+
+#include <linux/cache.h>
+#include <asm/percpu.h>
+
+
+/*
+ * CPU-specific data structure.
+ *
+ * One of these structures is allocated for each cpu of a NUMA system.
+ *
+ * This structure provides a convenient way of keeping together
+ * all SN per-cpu data structures.
+ */
+
+typedef struct pda_s {
+
+ /*
+ * Support for SN LEDs
+ */
+ volatile short *led_address;
+ u8 led_state;
+ u8 hb_state; /* supports blinking heartbeat leds */
+ unsigned int hb_count;
+
+ unsigned int idle_flag;
+
+ volatile unsigned long *bedrock_rev_id;
+ volatile unsigned long *pio_write_status_addr;
+ unsigned long pio_write_status_val;
+ volatile unsigned long *pio_shub_war_cam_addr;
+
+ unsigned long sn_in_service_ivecs[4];
+ int sn_lb_int_war_ticks;
+ int sn_last_irq;
+ int sn_first_irq;
+} pda_t;
+
+
+#define CACHE_ALIGN(x) (((x) + SMP_CACHE_BYTES-1) & ~(SMP_CACHE_BYTES-1))
+
+/*
+ * PDA
+ * Per-cpu private data area for each cpu. The PDA is located immediately after
+ * the IA64 cpu_data area. A full page is allocated for the cp_data area for each
+ * cpu but only a small amout of the page is actually used. We put the SNIA PDA
+ * in the same page as the cpu_data area. Note that there is a check in the setup
+ * code to verify that we don't overflow the page.
+ *
+ * Seems like we should should cache-line align the pda so that any changes in the
+ * size of the cpu_data area don't change cache layout. Should we align to 32, 64, 128
+ * or 512 boundary. Each has merits. For now, pick 128 but should be revisited later.
+ */
+DECLARE_PER_CPU(struct pda_s, pda_percpu);
+
+#define pda (&__ia64_per_cpu_var(pda_percpu))
+
+#define pdacpu(cpu) (&per_cpu(pda_percpu, cpu))
+
+#endif /* _ASM_IA64_SN_PDA_H */
diff --git a/kernel/arch/ia64/include/asm/sn/pic.h b/kernel/arch/ia64/include/asm/sn/pic.h
new file mode 100644
index 000000000..5f9da5fd6
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/pic.h
@@ -0,0 +1,261 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PCI_PIC_H
+#define _ASM_IA64_SN_PCI_PIC_H
+
+/*
+ * PIC AS DEVICE ZERO
+ * ------------------
+ *
+ * PIC handles PCI/X busses. PCI/X requires that the 'bridge' (i.e. PIC)
+ * be designated as 'device 0'. That is a departure from earlier SGI
+ * PCI bridges. Because of that we use config space 1 to access the
+ * config space of the first actual PCI device on the bus.
+ * Here's what the PIC manual says:
+ *
+ * The current PCI-X bus specification now defines that the parent
+ * hosts bus bridge (PIC for example) must be device 0 on bus 0. PIC
+ * reduced the total number of devices from 8 to 4 and removed the
+ * device registers and windows, now only supporting devices 0,1,2, and
+ * 3. PIC did leave all 8 configuration space windows. The reason was
+ * there was nothing to gain by removing them. Here in lies the problem.
+ * The device numbering we do using 0 through 3 is unrelated to the device
+ * numbering which PCI-X requires in configuration space. In the past we
+ * correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc.
+ * PCI-X requires we start a 1, not 0 and currently the PX brick
+ * does associate our:
+ *
+ * device 0 with configuration space window 1,
+ * device 1 with configuration space window 2,
+ * device 2 with configuration space window 3,
+ * device 3 with configuration space window 4.
+ *
+ * The net effect is that all config space access are off-by-one with
+ * relation to other per-slot accesses on the PIC.
+ * Here is a table that shows some of that:
+ *
+ * Internal Slot#
+ * |
+ * | 0 1 2 3
+ * ----------|---------------------------------------
+ * config | 0x21000 0x22000 0x23000 0x24000
+ * |
+ * even rrb | 0[0] n/a 1[0] n/a [] == implied even/odd
+ * |
+ * odd rrb | n/a 0[1] n/a 1[1]
+ * |
+ * int dev | 00 01 10 11
+ * |
+ * ext slot# | 1 2 3 4
+ * ----------|---------------------------------------
+ */
+
+#define PIC_ATE_TARGETID_SHFT 8
+#define PIC_HOST_INTR_ADDR 0x0000FFFFFFFFFFFFUL
+#define PIC_PCI64_ATTR_TARG_SHFT 60
+
+
+/*****************************************************************************
+ *********************** PIC MMR structure mapping ***************************
+ *****************************************************************************/
+
+/* NOTE: PIC WAR. PV#854697. PIC does not allow writes just to [31:0]
+ * of a 64-bit register. When writing PIC registers, always write the
+ * entire 64 bits.
+ */
+
+struct pic {
+
+ /* 0x000000-0x00FFFF -- Local Registers */
+
+ /* 0x000000-0x000057 -- Standard Widget Configuration */
+ u64 p_wid_id; /* 0x000000 */
+ u64 p_wid_stat; /* 0x000008 */
+ u64 p_wid_err_upper; /* 0x000010 */
+ u64 p_wid_err_lower; /* 0x000018 */
+ #define p_wid_err p_wid_err_lower
+ u64 p_wid_control; /* 0x000020 */
+ u64 p_wid_req_timeout; /* 0x000028 */
+ u64 p_wid_int_upper; /* 0x000030 */
+ u64 p_wid_int_lower; /* 0x000038 */
+ #define p_wid_int p_wid_int_lower
+ u64 p_wid_err_cmdword; /* 0x000040 */
+ u64 p_wid_llp; /* 0x000048 */
+ u64 p_wid_tflush; /* 0x000050 */
+
+ /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
+ u64 p_wid_aux_err; /* 0x000058 */
+ u64 p_wid_resp_upper; /* 0x000060 */
+ u64 p_wid_resp_lower; /* 0x000068 */
+ #define p_wid_resp p_wid_resp_lower
+ u64 p_wid_tst_pin_ctrl; /* 0x000070 */
+ u64 p_wid_addr_lkerr; /* 0x000078 */
+
+ /* 0x000080-0x00008F -- PMU & MAP */
+ u64 p_dir_map; /* 0x000080 */
+ u64 _pad_000088; /* 0x000088 */
+
+ /* 0x000090-0x00009F -- SSRAM */
+ u64 p_map_fault; /* 0x000090 */
+ u64 _pad_000098; /* 0x000098 */
+
+ /* 0x0000A0-0x0000AF -- Arbitration */
+ u64 p_arb; /* 0x0000A0 */
+ u64 _pad_0000A8; /* 0x0000A8 */
+
+ /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
+ u64 p_ate_parity_err; /* 0x0000B0 */
+ u64 _pad_0000B8; /* 0x0000B8 */
+
+ /* 0x0000C0-0x0000FF -- PCI/GIO */
+ u64 p_bus_timeout; /* 0x0000C0 */
+ u64 p_pci_cfg; /* 0x0000C8 */
+ u64 p_pci_err_upper; /* 0x0000D0 */
+ u64 p_pci_err_lower; /* 0x0000D8 */
+ #define p_pci_err p_pci_err_lower
+ u64 _pad_0000E0[4]; /* 0x0000{E0..F8} */
+
+ /* 0x000100-0x0001FF -- Interrupt */
+ u64 p_int_status; /* 0x000100 */
+ u64 p_int_enable; /* 0x000108 */
+ u64 p_int_rst_stat; /* 0x000110 */
+ u64 p_int_mode; /* 0x000118 */
+ u64 p_int_device; /* 0x000120 */
+ u64 p_int_host_err; /* 0x000128 */
+ u64 p_int_addr[8]; /* 0x0001{30,,,68} */
+ u64 p_err_int_view; /* 0x000170 */
+ u64 p_mult_int; /* 0x000178 */
+ u64 p_force_always[8]; /* 0x0001{80,,,B8} */
+ u64 p_force_pin[8]; /* 0x0001{C0,,,F8} */
+
+ /* 0x000200-0x000298 -- Device */
+ u64 p_device[4]; /* 0x0002{00,,,18} */
+ u64 _pad_000220[4]; /* 0x0002{20,,,38} */
+ u64 p_wr_req_buf[4]; /* 0x0002{40,,,58} */
+ u64 _pad_000260[4]; /* 0x0002{60,,,78} */
+ u64 p_rrb_map[2]; /* 0x0002{80,,,88} */
+ #define p_even_resp p_rrb_map[0] /* 0x000280 */
+ #define p_odd_resp p_rrb_map[1] /* 0x000288 */
+ u64 p_resp_status; /* 0x000290 */
+ u64 p_resp_clear; /* 0x000298 */
+
+ u64 _pad_0002A0[12]; /* 0x0002{A0..F8} */
+
+ /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
+ struct {
+ u64 upper; /* 0x0003{00,,,F0} */
+ u64 lower; /* 0x0003{08,,,F8} */
+ } p_buf_addr_match[16];
+
+ /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
+ struct {
+ u64 flush_w_touch; /* 0x000{400,,,5C0} */
+ u64 flush_wo_touch; /* 0x000{408,,,5C8} */
+ u64 inflight; /* 0x000{410,,,5D0} */
+ u64 prefetch; /* 0x000{418,,,5D8} */
+ u64 total_pci_retry; /* 0x000{420,,,5E0} */
+ u64 max_pci_retry; /* 0x000{428,,,5E8} */
+ u64 max_latency; /* 0x000{430,,,5F0} */
+ u64 clear_all; /* 0x000{438,,,5F8} */
+ } p_buf_count[8];
+
+
+ /* 0x000600-0x0009FF -- PCI/X registers */
+ u64 p_pcix_bus_err_addr; /* 0x000600 */
+ u64 p_pcix_bus_err_attr; /* 0x000608 */
+ u64 p_pcix_bus_err_data; /* 0x000610 */
+ u64 p_pcix_pio_split_addr; /* 0x000618 */
+ u64 p_pcix_pio_split_attr; /* 0x000620 */
+ u64 p_pcix_dma_req_err_attr; /* 0x000628 */
+ u64 p_pcix_dma_req_err_addr; /* 0x000630 */
+ u64 p_pcix_timeout; /* 0x000638 */
+
+ u64 _pad_000640[120]; /* 0x000{640,,,9F8} */
+
+ /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
+ struct {
+ u64 p_buf_addr; /* 0x000{A00,,,AF0} */
+ u64 p_buf_attr; /* 0X000{A08,,,AF8} */
+ } p_pcix_read_buf_64[16];
+
+ struct {
+ u64 p_buf_addr; /* 0x000{B00,,,BE0} */
+ u64 p_buf_attr; /* 0x000{B08,,,BE8} */
+ u64 p_buf_valid; /* 0x000{B10,,,BF0} */
+ u64 __pad1; /* 0x000{B18,,,BF8} */
+ } p_pcix_write_buf_64[8];
+
+ /* End of Local Registers -- Start of Address Map space */
+
+ char _pad_000c00[0x010000 - 0x000c00];
+
+ /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */
+ u64 p_int_ate_ram[1024]; /* 0x010000-0x011fff */
+
+ /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */
+ u64 p_int_ate_ram_mp[1024]; /* 0x012000-0x013fff */
+
+ char _pad_014000[0x18000 - 0x014000];
+
+ /* 0x18000-0x197F8 -- PIC Write Request Ram */
+ u64 p_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
+ u64 p_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
+ u64 p_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
+
+ char _pad_019800[0x20000 - 0x019800];
+
+ /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
+ union {
+ u8 c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
+ u16 s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
+ u32 l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
+ u64 d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
+ union {
+ u8 c[0x100 / 1];
+ u16 s[0x100 / 2];
+ u32 l[0x100 / 4];
+ u64 d[0x100 / 8];
+ } f[8];
+ } p_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */
+
+ /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
+ union {
+ u8 c[0x1000 / 1]; /* 0x028000-0x029000 */
+ u16 s[0x1000 / 2]; /* 0x028000-0x029000 */
+ u32 l[0x1000 / 4]; /* 0x028000-0x029000 */
+ u64 d[0x1000 / 8]; /* 0x028000-0x029000 */
+ union {
+ u8 c[0x100 / 1];
+ u16 s[0x100 / 2];
+ u32 l[0x100 / 4];
+ u64 d[0x100 / 8];
+ } f[8];
+ } p_type1_cfg; /* 0x028000-0x029000 */
+
+ char _pad_029000[0x030000-0x029000];
+
+ /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
+ union {
+ u8 c[8 / 1];
+ u16 s[8 / 2];
+ u32 l[8 / 4];
+ u64 d[8 / 8];
+ } p_pci_iack; /* 0x030000-0x030007 */
+
+ char _pad_030007[0x040000-0x030008];
+
+ /* 0x040000-0x030007 -- PCIX Special Cycle */
+ union {
+ u8 c[8 / 1];
+ u16 s[8 / 2];
+ u32 l[8 / 4];
+ u64 d[8 / 8];
+ } p_pcix_cycle; /* 0x040000-0x040007 */
+};
+
+#endif /* _ASM_IA64_SN_PCI_PIC_H */
diff --git a/kernel/arch/ia64/include/asm/sn/rw_mmr.h b/kernel/arch/ia64/include/asm/sn/rw_mmr.h
new file mode 100644
index 000000000..2d78f4c5a
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/rw_mmr.h
@@ -0,0 +1,28 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002-2006 Silicon Graphics, Inc. All Rights Reserved.
+ */
+#ifndef _ASM_IA64_SN_RW_MMR_H
+#define _ASM_IA64_SN_RW_MMR_H
+
+
+/*
+ * This file that access MMRs via uncached physical addresses.
+ * pio_phys_read_mmr - read an MMR
+ * pio_phys_write_mmr - write an MMR
+ * pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0
+ * Second MMR will be skipped if address is NULL
+ *
+ * Addresses passed to these routines should be uncached physical addresses
+ * ie., 0x80000....
+ */
+
+
+extern long pio_phys_read_mmr(volatile long *mmr);
+extern void pio_phys_write_mmr(volatile long *mmr, long val);
+extern void pio_atomic_phys_write_mmrs(volatile long *mmr1, long val1, volatile long *mmr2, long val2);
+
+#endif /* _ASM_IA64_SN_RW_MMR_H */
diff --git a/kernel/arch/ia64/include/asm/sn/shub_mmr.h b/kernel/arch/ia64/include/asm/sn/shub_mmr.h
new file mode 100644
index 000000000..a84d870f4
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/shub_mmr.h
@@ -0,0 +1,502 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_SHUB_MMR_H
+#define _ASM_IA64_SN_SHUB_MMR_H
+
+/* ==================================================================== */
+/* Register "SH_IPI_INT" */
+/* SHub Inter-Processor Interrupt Registers */
+/* ==================================================================== */
+#define SH1_IPI_INT __IA64_UL_CONST(0x0000000110000380)
+#define SH2_IPI_INT __IA64_UL_CONST(0x0000000010000380)
+
+/* SH_IPI_INT_TYPE */
+/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
+#define SH_IPI_INT_TYPE_SHFT 0
+#define SH_IPI_INT_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
+
+/* SH_IPI_INT_AGT */
+/* Description: Agent, must be 0 for SHub */
+#define SH_IPI_INT_AGT_SHFT 3
+#define SH_IPI_INT_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
+
+/* SH_IPI_INT_PID */
+/* Description: Processor ID, same setting as on targeted McKinley */
+#define SH_IPI_INT_PID_SHFT 4
+#define SH_IPI_INT_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
+
+/* SH_IPI_INT_BASE */
+/* Description: Optional interrupt vector area, 2MB aligned */
+#define SH_IPI_INT_BASE_SHFT 21
+#define SH_IPI_INT_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
+
+/* SH_IPI_INT_IDX */
+/* Description: Targeted McKinley interrupt vector */
+#define SH_IPI_INT_IDX_SHFT 52
+#define SH_IPI_INT_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
+
+/* SH_IPI_INT_SEND */
+/* Description: Send Interrupt Message to PI, This generates a puls */
+#define SH_IPI_INT_SEND_SHFT 63
+#define SH_IPI_INT_SEND_MASK __IA64_UL_CONST(0x8000000000000000)
+
+/* ==================================================================== */
+/* Register "SH_EVENT_OCCURRED" */
+/* SHub Interrupt Event Occurred */
+/* ==================================================================== */
+#define SH1_EVENT_OCCURRED __IA64_UL_CONST(0x0000000110010000)
+#define SH1_EVENT_OCCURRED_ALIAS __IA64_UL_CONST(0x0000000110010008)
+#define SH2_EVENT_OCCURRED __IA64_UL_CONST(0x0000000010010000)
+#define SH2_EVENT_OCCURRED_ALIAS __IA64_UL_CONST(0x0000000010010008)
+
+/* ==================================================================== */
+/* Register "SH_PI_CAM_CONTROL" */
+/* CRB CAM MMR Access Control */
+/* ==================================================================== */
+#define SH1_PI_CAM_CONTROL __IA64_UL_CONST(0x0000000120050300)
+
+/* ==================================================================== */
+/* Register "SH_SHUB_ID" */
+/* SHub ID Number */
+/* ==================================================================== */
+#define SH1_SHUB_ID __IA64_UL_CONST(0x0000000110060580)
+#define SH1_SHUB_ID_REVISION_SHFT 28
+#define SH1_SHUB_ID_REVISION_MASK __IA64_UL_CONST(0x00000000f0000000)
+
+/* ==================================================================== */
+/* Register "SH_RTC" */
+/* Real-time Clock */
+/* ==================================================================== */
+#define SH1_RTC __IA64_UL_CONST(0x00000001101c0000)
+#define SH2_RTC __IA64_UL_CONST(0x00000002101c0000)
+#define SH_RTC_MASK __IA64_UL_CONST(0x007fffffffffffff)
+
+/* ==================================================================== */
+/* Register "SH_PIO_WRITE_STATUS_0|1" */
+/* PIO Write Status for CPU 0 & 1 */
+/* ==================================================================== */
+#define SH1_PIO_WRITE_STATUS_0 __IA64_UL_CONST(0x0000000120070200)
+#define SH1_PIO_WRITE_STATUS_1 __IA64_UL_CONST(0x0000000120070280)
+#define SH2_PIO_WRITE_STATUS_0 __IA64_UL_CONST(0x0000000020070200)
+#define SH2_PIO_WRITE_STATUS_1 __IA64_UL_CONST(0x0000000020070280)
+#define SH2_PIO_WRITE_STATUS_2 __IA64_UL_CONST(0x0000000020070300)
+#define SH2_PIO_WRITE_STATUS_3 __IA64_UL_CONST(0x0000000020070380)
+
+/* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */
+/* Description: Deadlock response detected */
+#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 1
+#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK \
+ __IA64_UL_CONST(0x0000000000000002)
+
+/* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */
+/* Description: Count of currently pending PIO writes */
+#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT 56
+#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK \
+ __IA64_UL_CONST(0x3f00000000000000)
+
+/* ==================================================================== */
+/* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */
+/* ==================================================================== */
+#define SH1_PIO_WRITE_STATUS_0_ALIAS __IA64_UL_CONST(0x0000000120070208)
+#define SH2_PIO_WRITE_STATUS_0_ALIAS __IA64_UL_CONST(0x0000000020070208)
+
+/* ==================================================================== */
+/* Register "SH_EVENT_OCCURRED" */
+/* SHub Interrupt Event Occurred */
+/* ==================================================================== */
+/* SH_EVENT_OCCURRED_UART_INT */
+/* Description: Pending Junk Bus UART Interrupt */
+#define SH_EVENT_OCCURRED_UART_INT_SHFT 20
+#define SH_EVENT_OCCURRED_UART_INT_MASK __IA64_UL_CONST(0x0000000000100000)
+
+/* SH_EVENT_OCCURRED_IPI_INT */
+/* Description: Pending IPI Interrupt */
+#define SH_EVENT_OCCURRED_IPI_INT_SHFT 28
+#define SH_EVENT_OCCURRED_IPI_INT_MASK __IA64_UL_CONST(0x0000000010000000)
+
+/* SH_EVENT_OCCURRED_II_INT0 */
+/* Description: Pending II 0 Interrupt */
+#define SH_EVENT_OCCURRED_II_INT0_SHFT 29
+#define SH_EVENT_OCCURRED_II_INT0_MASK __IA64_UL_CONST(0x0000000020000000)
+
+/* SH_EVENT_OCCURRED_II_INT1 */
+/* Description: Pending II 1 Interrupt */
+#define SH_EVENT_OCCURRED_II_INT1_SHFT 30
+#define SH_EVENT_OCCURRED_II_INT1_MASK __IA64_UL_CONST(0x0000000040000000)
+
+/* SH2_EVENT_OCCURRED_EXTIO_INT2 */
+/* Description: Pending SHUB 2 EXT IO INT2 */
+#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT 33
+#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK __IA64_UL_CONST(0x0000000200000000)
+
+/* SH2_EVENT_OCCURRED_EXTIO_INT3 */
+/* Description: Pending SHUB 2 EXT IO INT3 */
+#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT 34
+#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK __IA64_UL_CONST(0x0000000400000000)
+
+#define SH_ALL_INT_MASK \
+ (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \
+ SH_EVENT_OCCURRED_II_INT0_MASK | SH_EVENT_OCCURRED_II_INT1_MASK | \
+ SH_EVENT_OCCURRED_II_INT1_MASK | SH2_EVENT_OCCURRED_EXTIO_INT2_MASK | \
+ SH2_EVENT_OCCURRED_EXTIO_INT3_MASK)
+
+
+/* ==================================================================== */
+/* LEDS */
+/* ==================================================================== */
+#define SH1_REAL_JUNK_BUS_LED0 0x7fed00000UL
+#define SH1_REAL_JUNK_BUS_LED1 0x7fed10000UL
+#define SH1_REAL_JUNK_BUS_LED2 0x7fed20000UL
+#define SH1_REAL_JUNK_BUS_LED3 0x7fed30000UL
+
+#define SH2_REAL_JUNK_BUS_LED0 0xf0000000UL
+#define SH2_REAL_JUNK_BUS_LED1 0xf0010000UL
+#define SH2_REAL_JUNK_BUS_LED2 0xf0020000UL
+#define SH2_REAL_JUNK_BUS_LED3 0xf0030000UL
+
+/* ==================================================================== */
+/* Register "SH1_PTC_0" */
+/* Puge Translation Cache Message Configuration Information */
+/* ==================================================================== */
+#define SH1_PTC_0 __IA64_UL_CONST(0x00000001101a0000)
+
+/* SH1_PTC_0_A */
+/* Description: Type */
+#define SH1_PTC_0_A_SHFT 0
+
+/* SH1_PTC_0_PS */
+/* Description: Page Size */
+#define SH1_PTC_0_PS_SHFT 2
+
+/* SH1_PTC_0_RID */
+/* Description: Region ID */
+#define SH1_PTC_0_RID_SHFT 8
+
+/* SH1_PTC_0_START */
+/* Description: Start */
+#define SH1_PTC_0_START_SHFT 63
+
+/* ==================================================================== */
+/* Register "SH1_PTC_1" */
+/* Puge Translation Cache Message Configuration Information */
+/* ==================================================================== */
+#define SH1_PTC_1 __IA64_UL_CONST(0x00000001101a0080)
+
+/* SH1_PTC_1_START */
+/* Description: PTC_1 Start */
+#define SH1_PTC_1_START_SHFT 63
+
+/* ==================================================================== */
+/* Register "SH2_PTC" */
+/* Puge Translation Cache Message Configuration Information */
+/* ==================================================================== */
+#define SH2_PTC __IA64_UL_CONST(0x0000000170000000)
+
+/* SH2_PTC_A */
+/* Description: Type */
+#define SH2_PTC_A_SHFT 0
+
+/* SH2_PTC_PS */
+/* Description: Page Size */
+#define SH2_PTC_PS_SHFT 2
+
+/* SH2_PTC_RID */
+/* Description: Region ID */
+#define SH2_PTC_RID_SHFT 4
+
+/* SH2_PTC_START */
+/* Description: Start */
+#define SH2_PTC_START_SHFT 63
+
+/* SH2_PTC_ADDR_RID */
+/* Description: Region ID */
+#define SH2_PTC_ADDR_SHFT 4
+#define SH2_PTC_ADDR_MASK __IA64_UL_CONST(0x1ffffffffffff000)
+
+/* ==================================================================== */
+/* Register "SH_RTC1_INT_CONFIG" */
+/* SHub RTC 1 Interrupt Config Registers */
+/* ==================================================================== */
+
+#define SH1_RTC1_INT_CONFIG __IA64_UL_CONST(0x0000000110001480)
+#define SH2_RTC1_INT_CONFIG __IA64_UL_CONST(0x0000000010001480)
+#define SH_RTC1_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
+#define SH_RTC1_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
+
+/* SH_RTC1_INT_CONFIG_TYPE */
+/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
+#define SH_RTC1_INT_CONFIG_TYPE_SHFT 0
+#define SH_RTC1_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
+
+/* SH_RTC1_INT_CONFIG_AGT */
+/* Description: Agent, must be 0 for SHub */
+#define SH_RTC1_INT_CONFIG_AGT_SHFT 3
+#define SH_RTC1_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
+
+/* SH_RTC1_INT_CONFIG_PID */
+/* Description: Processor ID, same setting as on targeted McKinley */
+#define SH_RTC1_INT_CONFIG_PID_SHFT 4
+#define SH_RTC1_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
+
+/* SH_RTC1_INT_CONFIG_BASE */
+/* Description: Optional interrupt vector area, 2MB aligned */
+#define SH_RTC1_INT_CONFIG_BASE_SHFT 21
+#define SH_RTC1_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
+
+/* SH_RTC1_INT_CONFIG_IDX */
+/* Description: Targeted McKinley interrupt vector */
+#define SH_RTC1_INT_CONFIG_IDX_SHFT 52
+#define SH_RTC1_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
+
+/* ==================================================================== */
+/* Register "SH_RTC1_INT_ENABLE" */
+/* SHub RTC 1 Interrupt Enable Registers */
+/* ==================================================================== */
+
+#define SH1_RTC1_INT_ENABLE __IA64_UL_CONST(0x0000000110001500)
+#define SH2_RTC1_INT_ENABLE __IA64_UL_CONST(0x0000000010001500)
+#define SH_RTC1_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
+#define SH_RTC1_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
+
+/* SH_RTC1_INT_ENABLE_RTC1_ENABLE */
+/* Description: Enable RTC 1 Interrupt */
+#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT 0
+#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK \
+ __IA64_UL_CONST(0x0000000000000001)
+
+/* ==================================================================== */
+/* Register "SH_RTC2_INT_CONFIG" */
+/* SHub RTC 2 Interrupt Config Registers */
+/* ==================================================================== */
+
+#define SH1_RTC2_INT_CONFIG __IA64_UL_CONST(0x0000000110001580)
+#define SH2_RTC2_INT_CONFIG __IA64_UL_CONST(0x0000000010001580)
+#define SH_RTC2_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
+#define SH_RTC2_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
+
+/* SH_RTC2_INT_CONFIG_TYPE */
+/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
+#define SH_RTC2_INT_CONFIG_TYPE_SHFT 0
+#define SH_RTC2_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
+
+/* SH_RTC2_INT_CONFIG_AGT */
+/* Description: Agent, must be 0 for SHub */
+#define SH_RTC2_INT_CONFIG_AGT_SHFT 3
+#define SH_RTC2_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
+
+/* SH_RTC2_INT_CONFIG_PID */
+/* Description: Processor ID, same setting as on targeted McKinley */
+#define SH_RTC2_INT_CONFIG_PID_SHFT 4
+#define SH_RTC2_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
+
+/* SH_RTC2_INT_CONFIG_BASE */
+/* Description: Optional interrupt vector area, 2MB aligned */
+#define SH_RTC2_INT_CONFIG_BASE_SHFT 21
+#define SH_RTC2_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
+
+/* SH_RTC2_INT_CONFIG_IDX */
+/* Description: Targeted McKinley interrupt vector */
+#define SH_RTC2_INT_CONFIG_IDX_SHFT 52
+#define SH_RTC2_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
+
+/* ==================================================================== */
+/* Register "SH_RTC2_INT_ENABLE" */
+/* SHub RTC 2 Interrupt Enable Registers */
+/* ==================================================================== */
+
+#define SH1_RTC2_INT_ENABLE __IA64_UL_CONST(0x0000000110001600)
+#define SH2_RTC2_INT_ENABLE __IA64_UL_CONST(0x0000000010001600)
+#define SH_RTC2_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
+#define SH_RTC2_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
+
+/* SH_RTC2_INT_ENABLE_RTC2_ENABLE */
+/* Description: Enable RTC 2 Interrupt */
+#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT 0
+#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK \
+ __IA64_UL_CONST(0x0000000000000001)
+
+/* ==================================================================== */
+/* Register "SH_RTC3_INT_CONFIG" */
+/* SHub RTC 3 Interrupt Config Registers */
+/* ==================================================================== */
+
+#define SH1_RTC3_INT_CONFIG __IA64_UL_CONST(0x0000000110001680)
+#define SH2_RTC3_INT_CONFIG __IA64_UL_CONST(0x0000000010001680)
+#define SH_RTC3_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
+#define SH_RTC3_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
+
+/* SH_RTC3_INT_CONFIG_TYPE */
+/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
+#define SH_RTC3_INT_CONFIG_TYPE_SHFT 0
+#define SH_RTC3_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
+
+/* SH_RTC3_INT_CONFIG_AGT */
+/* Description: Agent, must be 0 for SHub */
+#define SH_RTC3_INT_CONFIG_AGT_SHFT 3
+#define SH_RTC3_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
+
+/* SH_RTC3_INT_CONFIG_PID */
+/* Description: Processor ID, same setting as on targeted McKinley */
+#define SH_RTC3_INT_CONFIG_PID_SHFT 4
+#define SH_RTC3_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
+
+/* SH_RTC3_INT_CONFIG_BASE */
+/* Description: Optional interrupt vector area, 2MB aligned */
+#define SH_RTC3_INT_CONFIG_BASE_SHFT 21
+#define SH_RTC3_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
+
+/* SH_RTC3_INT_CONFIG_IDX */
+/* Description: Targeted McKinley interrupt vector */
+#define SH_RTC3_INT_CONFIG_IDX_SHFT 52
+#define SH_RTC3_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
+
+/* ==================================================================== */
+/* Register "SH_RTC3_INT_ENABLE" */
+/* SHub RTC 3 Interrupt Enable Registers */
+/* ==================================================================== */
+
+#define SH1_RTC3_INT_ENABLE __IA64_UL_CONST(0x0000000110001700)
+#define SH2_RTC3_INT_ENABLE __IA64_UL_CONST(0x0000000010001700)
+#define SH_RTC3_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
+#define SH_RTC3_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
+
+/* SH_RTC3_INT_ENABLE_RTC3_ENABLE */
+/* Description: Enable RTC 3 Interrupt */
+#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT 0
+#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK \
+ __IA64_UL_CONST(0x0000000000000001)
+
+/* SH_EVENT_OCCURRED_RTC1_INT */
+/* Description: Pending RTC 1 Interrupt */
+#define SH_EVENT_OCCURRED_RTC1_INT_SHFT 24
+#define SH_EVENT_OCCURRED_RTC1_INT_MASK __IA64_UL_CONST(0x0000000001000000)
+
+/* SH_EVENT_OCCURRED_RTC2_INT */
+/* Description: Pending RTC 2 Interrupt */
+#define SH_EVENT_OCCURRED_RTC2_INT_SHFT 25
+#define SH_EVENT_OCCURRED_RTC2_INT_MASK __IA64_UL_CONST(0x0000000002000000)
+
+/* SH_EVENT_OCCURRED_RTC3_INT */
+/* Description: Pending RTC 3 Interrupt */
+#define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26
+#define SH_EVENT_OCCURRED_RTC3_INT_MASK __IA64_UL_CONST(0x0000000004000000)
+
+/* ==================================================================== */
+/* Register "SH_IPI_ACCESS" */
+/* CPU interrupt Access Permission Bits */
+/* ==================================================================== */
+
+#define SH1_IPI_ACCESS __IA64_UL_CONST(0x0000000110060480)
+#define SH2_IPI_ACCESS0 __IA64_UL_CONST(0x0000000010060c00)
+#define SH2_IPI_ACCESS1 __IA64_UL_CONST(0x0000000010060c80)
+#define SH2_IPI_ACCESS2 __IA64_UL_CONST(0x0000000010060d00)
+#define SH2_IPI_ACCESS3 __IA64_UL_CONST(0x0000000010060d80)
+
+/* ==================================================================== */
+/* Register "SH_INT_CMPB" */
+/* RTC Compare Value for Processor B */
+/* ==================================================================== */
+
+#define SH1_INT_CMPB __IA64_UL_CONST(0x00000001101b0080)
+#define SH2_INT_CMPB __IA64_UL_CONST(0x00000000101b0080)
+#define SH_INT_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff)
+#define SH_INT_CMPB_INIT __IA64_UL_CONST(0x0000000000000000)
+
+/* SH_INT_CMPB_REAL_TIME_CMPB */
+/* Description: Real Time Clock Compare */
+#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
+#define SH_INT_CMPB_REAL_TIME_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff)
+
+/* ==================================================================== */
+/* Register "SH_INT_CMPC" */
+/* RTC Compare Value for Processor C */
+/* ==================================================================== */
+
+#define SH1_INT_CMPC __IA64_UL_CONST(0x00000001101b0100)
+#define SH2_INT_CMPC __IA64_UL_CONST(0x00000000101b0100)
+#define SH_INT_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff)
+#define SH_INT_CMPC_INIT __IA64_UL_CONST(0x0000000000000000)
+
+/* SH_INT_CMPC_REAL_TIME_CMPC */
+/* Description: Real Time Clock Compare */
+#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
+#define SH_INT_CMPC_REAL_TIME_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff)
+
+/* ==================================================================== */
+/* Register "SH_INT_CMPD" */
+/* RTC Compare Value for Processor D */
+/* ==================================================================== */
+
+#define SH1_INT_CMPD __IA64_UL_CONST(0x00000001101b0180)
+#define SH2_INT_CMPD __IA64_UL_CONST(0x00000000101b0180)
+#define SH_INT_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff)
+#define SH_INT_CMPD_INIT __IA64_UL_CONST(0x0000000000000000)
+
+/* SH_INT_CMPD_REAL_TIME_CMPD */
+/* Description: Real Time Clock Compare */
+#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
+#define SH_INT_CMPD_REAL_TIME_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff)
+
+/* ==================================================================== */
+/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */
+/* privilege vector for acc=0 */
+/* ==================================================================== */
+#define SH1_MD_DQLP_MMR_DIR_PRIVEC0 __IA64_UL_CONST(0x0000000100030300)
+
+/* ==================================================================== */
+/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */
+/* privilege vector for acc=0 */
+/* ==================================================================== */
+#define SH1_MD_DQRP_MMR_DIR_PRIVEC0 __IA64_UL_CONST(0x0000000100050300)
+
+/* ==================================================================== */
+/* Some MMRs are functionally identical (or close enough) on both SHUB1 */
+/* and SHUB2 that it makes sense to define a geberic name for the MMR. */
+/* It is acceptable to use (for example) SH_IPI_INT to reference the */
+/* the IPI MMR. The value of SH_IPI_INT is determined at runtime based */
+/* on the type of the SHUB. Do not use these #defines in performance */
+/* critical code or loops - there is a small performance penalty. */
+/* ==================================================================== */
+#define shubmmr(a,b) (is_shub2() ? a##2_##b : a##1_##b)
+
+#define SH_REAL_JUNK_BUS_LED0 shubmmr(SH, REAL_JUNK_BUS_LED0)
+#define SH_IPI_INT shubmmr(SH, IPI_INT)
+#define SH_EVENT_OCCURRED shubmmr(SH, EVENT_OCCURRED)
+#define SH_EVENT_OCCURRED_ALIAS shubmmr(SH, EVENT_OCCURRED_ALIAS)
+#define SH_RTC shubmmr(SH, RTC)
+#define SH_RTC1_INT_CONFIG shubmmr(SH, RTC1_INT_CONFIG)
+#define SH_RTC1_INT_ENABLE shubmmr(SH, RTC1_INT_ENABLE)
+#define SH_RTC2_INT_CONFIG shubmmr(SH, RTC2_INT_CONFIG)
+#define SH_RTC2_INT_ENABLE shubmmr(SH, RTC2_INT_ENABLE)
+#define SH_RTC3_INT_CONFIG shubmmr(SH, RTC3_INT_CONFIG)
+#define SH_RTC3_INT_ENABLE shubmmr(SH, RTC3_INT_ENABLE)
+#define SH_INT_CMPB shubmmr(SH, INT_CMPB)
+#define SH_INT_CMPC shubmmr(SH, INT_CMPC)
+#define SH_INT_CMPD shubmmr(SH, INT_CMPD)
+
+/* ========================================================================== */
+/* Register "SH2_BT_ENG_CSR_0" */
+/* Engine 0 Control and Status Register */
+/* ========================================================================== */
+
+#define SH2_BT_ENG_CSR_0 __IA64_UL_CONST(0x0000000030040000)
+#define SH2_BT_ENG_SRC_ADDR_0 __IA64_UL_CONST(0x0000000030040080)
+#define SH2_BT_ENG_DEST_ADDR_0 __IA64_UL_CONST(0x0000000030040100)
+#define SH2_BT_ENG_NOTIF_ADDR_0 __IA64_UL_CONST(0x0000000030040180)
+
+/* ========================================================================== */
+/* BTE interfaces 1-3 */
+/* ========================================================================== */
+
+#define SH2_BT_ENG_CSR_1 __IA64_UL_CONST(0x0000000030050000)
+#define SH2_BT_ENG_CSR_2 __IA64_UL_CONST(0x0000000030060000)
+#define SH2_BT_ENG_CSR_3 __IA64_UL_CONST(0x0000000030070000)
+
+#endif /* _ASM_IA64_SN_SHUB_MMR_H */
diff --git a/kernel/arch/ia64/include/asm/sn/shubio.h b/kernel/arch/ia64/include/asm/sn/shubio.h
new file mode 100644
index 000000000..ecb8a4947
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/shubio.h
@@ -0,0 +1,3358 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_SHUBIO_H
+#define _ASM_IA64_SN_SHUBIO_H
+
+#define HUB_WIDGET_ID_MAX 0xf
+#define IIO_NUM_ITTES 7
+#define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1)
+
+#define IIO_WID 0x00400000 /* Crosstalk Widget Identification */
+ /* This register is also accessible from
+ * Crosstalk at address 0x0. */
+#define IIO_WSTAT 0x00400008 /* Crosstalk Widget Status */
+#define IIO_WCR 0x00400020 /* Crosstalk Widget Control Register */
+#define IIO_ILAPR 0x00400100 /* IO Local Access Protection Register */
+#define IIO_ILAPO 0x00400108 /* IO Local Access Protection Override */
+#define IIO_IOWA 0x00400110 /* IO Outbound Widget Access */
+#define IIO_IIWA 0x00400118 /* IO Inbound Widget Access */
+#define IIO_IIDEM 0x00400120 /* IO Inbound Device Error Mask */
+#define IIO_ILCSR 0x00400128 /* IO LLP Control and Status Register */
+#define IIO_ILLR 0x00400130 /* IO LLP Log Register */
+#define IIO_IIDSR 0x00400138 /* IO Interrupt Destination */
+
+#define IIO_IGFX0 0x00400140 /* IO Graphics Node-Widget Map 0 */
+#define IIO_IGFX1 0x00400148 /* IO Graphics Node-Widget Map 1 */
+
+#define IIO_ISCR0 0x00400150 /* IO Scratch Register 0 */
+#define IIO_ISCR1 0x00400158 /* IO Scratch Register 1 */
+
+#define IIO_ITTE1 0x00400160 /* IO Translation Table Entry 1 */
+#define IIO_ITTE2 0x00400168 /* IO Translation Table Entry 2 */
+#define IIO_ITTE3 0x00400170 /* IO Translation Table Entry 3 */
+#define IIO_ITTE4 0x00400178 /* IO Translation Table Entry 4 */
+#define IIO_ITTE5 0x00400180 /* IO Translation Table Entry 5 */
+#define IIO_ITTE6 0x00400188 /* IO Translation Table Entry 6 */
+#define IIO_ITTE7 0x00400190 /* IO Translation Table Entry 7 */
+
+#define IIO_IPRB0 0x00400198 /* IO PRB Entry 0 */
+#define IIO_IPRB8 0x004001A0 /* IO PRB Entry 8 */
+#define IIO_IPRB9 0x004001A8 /* IO PRB Entry 9 */
+#define IIO_IPRBA 0x004001B0 /* IO PRB Entry A */
+#define IIO_IPRBB 0x004001B8 /* IO PRB Entry B */
+#define IIO_IPRBC 0x004001C0 /* IO PRB Entry C */
+#define IIO_IPRBD 0x004001C8 /* IO PRB Entry D */
+#define IIO_IPRBE 0x004001D0 /* IO PRB Entry E */
+#define IIO_IPRBF 0x004001D8 /* IO PRB Entry F */
+
+#define IIO_IXCC 0x004001E0 /* IO Crosstalk Credit Count Timeout */
+#define IIO_IMEM 0x004001E8 /* IO Miscellaneous Error Mask */
+#define IIO_IXTT 0x004001F0 /* IO Crosstalk Timeout Threshold */
+#define IIO_IECLR 0x004001F8 /* IO Error Clear Register */
+#define IIO_IBCR 0x00400200 /* IO BTE Control Register */
+
+#define IIO_IXSM 0x00400208 /* IO Crosstalk Spurious Message */
+#define IIO_IXSS 0x00400210 /* IO Crosstalk Spurious Sideband */
+
+#define IIO_ILCT 0x00400218 /* IO LLP Channel Test */
+
+#define IIO_IIEPH1 0x00400220 /* IO Incoming Error Packet Header, Part 1 */
+#define IIO_IIEPH2 0x00400228 /* IO Incoming Error Packet Header, Part 2 */
+
+#define IIO_ISLAPR 0x00400230 /* IO SXB Local Access Protection Regster */
+#define IIO_ISLAPO 0x00400238 /* IO SXB Local Access Protection Override */
+
+#define IIO_IWI 0x00400240 /* IO Wrapper Interrupt Register */
+#define IIO_IWEL 0x00400248 /* IO Wrapper Error Log Register */
+#define IIO_IWC 0x00400250 /* IO Wrapper Control Register */
+#define IIO_IWS 0x00400258 /* IO Wrapper Status Register */
+#define IIO_IWEIM 0x00400260 /* IO Wrapper Error Interrupt Masking Register */
+
+#define IIO_IPCA 0x00400300 /* IO PRB Counter Adjust */
+
+#define IIO_IPRTE0_A 0x00400308 /* IO PIO Read Address Table Entry 0, Part A */
+#define IIO_IPRTE1_A 0x00400310 /* IO PIO Read Address Table Entry 1, Part A */
+#define IIO_IPRTE2_A 0x00400318 /* IO PIO Read Address Table Entry 2, Part A */
+#define IIO_IPRTE3_A 0x00400320 /* IO PIO Read Address Table Entry 3, Part A */
+#define IIO_IPRTE4_A 0x00400328 /* IO PIO Read Address Table Entry 4, Part A */
+#define IIO_IPRTE5_A 0x00400330 /* IO PIO Read Address Table Entry 5, Part A */
+#define IIO_IPRTE6_A 0x00400338 /* IO PIO Read Address Table Entry 6, Part A */
+#define IIO_IPRTE7_A 0x00400340 /* IO PIO Read Address Table Entry 7, Part A */
+
+#define IIO_IPRTE0_B 0x00400348 /* IO PIO Read Address Table Entry 0, Part B */
+#define IIO_IPRTE1_B 0x00400350 /* IO PIO Read Address Table Entry 1, Part B */
+#define IIO_IPRTE2_B 0x00400358 /* IO PIO Read Address Table Entry 2, Part B */
+#define IIO_IPRTE3_B 0x00400360 /* IO PIO Read Address Table Entry 3, Part B */
+#define IIO_IPRTE4_B 0x00400368 /* IO PIO Read Address Table Entry 4, Part B */
+#define IIO_IPRTE5_B 0x00400370 /* IO PIO Read Address Table Entry 5, Part B */
+#define IIO_IPRTE6_B 0x00400378 /* IO PIO Read Address Table Entry 6, Part B */
+#define IIO_IPRTE7_B 0x00400380 /* IO PIO Read Address Table Entry 7, Part B */
+
+#define IIO_IPDR 0x00400388 /* IO PIO Deallocation Register */
+#define IIO_ICDR 0x00400390 /* IO CRB Entry Deallocation Register */
+#define IIO_IFDR 0x00400398 /* IO IOQ FIFO Depth Register */
+#define IIO_IIAP 0x004003A0 /* IO IIQ Arbitration Parameters */
+#define IIO_ICMR 0x004003A8 /* IO CRB Management Register */
+#define IIO_ICCR 0x004003B0 /* IO CRB Control Register */
+#define IIO_ICTO 0x004003B8 /* IO CRB Timeout */
+#define IIO_ICTP 0x004003C0 /* IO CRB Timeout Prescalar */
+
+#define IIO_ICRB0_A 0x00400400 /* IO CRB Entry 0_A */
+#define IIO_ICRB0_B 0x00400408 /* IO CRB Entry 0_B */
+#define IIO_ICRB0_C 0x00400410 /* IO CRB Entry 0_C */
+#define IIO_ICRB0_D 0x00400418 /* IO CRB Entry 0_D */
+#define IIO_ICRB0_E 0x00400420 /* IO CRB Entry 0_E */
+
+#define IIO_ICRB1_A 0x00400430 /* IO CRB Entry 1_A */
+#define IIO_ICRB1_B 0x00400438 /* IO CRB Entry 1_B */
+#define IIO_ICRB1_C 0x00400440 /* IO CRB Entry 1_C */
+#define IIO_ICRB1_D 0x00400448 /* IO CRB Entry 1_D */
+#define IIO_ICRB1_E 0x00400450 /* IO CRB Entry 1_E */
+
+#define IIO_ICRB2_A 0x00400460 /* IO CRB Entry 2_A */
+#define IIO_ICRB2_B 0x00400468 /* IO CRB Entry 2_B */
+#define IIO_ICRB2_C 0x00400470 /* IO CRB Entry 2_C */
+#define IIO_ICRB2_D 0x00400478 /* IO CRB Entry 2_D */
+#define IIO_ICRB2_E 0x00400480 /* IO CRB Entry 2_E */
+
+#define IIO_ICRB3_A 0x00400490 /* IO CRB Entry 3_A */
+#define IIO_ICRB3_B 0x00400498 /* IO CRB Entry 3_B */
+#define IIO_ICRB3_C 0x004004a0 /* IO CRB Entry 3_C */
+#define IIO_ICRB3_D 0x004004a8 /* IO CRB Entry 3_D */
+#define IIO_ICRB3_E 0x004004b0 /* IO CRB Entry 3_E */
+
+#define IIO_ICRB4_A 0x004004c0 /* IO CRB Entry 4_A */
+#define IIO_ICRB4_B 0x004004c8 /* IO CRB Entry 4_B */
+#define IIO_ICRB4_C 0x004004d0 /* IO CRB Entry 4_C */
+#define IIO_ICRB4_D 0x004004d8 /* IO CRB Entry 4_D */
+#define IIO_ICRB4_E 0x004004e0 /* IO CRB Entry 4_E */
+
+#define IIO_ICRB5_A 0x004004f0 /* IO CRB Entry 5_A */
+#define IIO_ICRB5_B 0x004004f8 /* IO CRB Entry 5_B */
+#define IIO_ICRB5_C 0x00400500 /* IO CRB Entry 5_C */
+#define IIO_ICRB5_D 0x00400508 /* IO CRB Entry 5_D */
+#define IIO_ICRB5_E 0x00400510 /* IO CRB Entry 5_E */
+
+#define IIO_ICRB6_A 0x00400520 /* IO CRB Entry 6_A */
+#define IIO_ICRB6_B 0x00400528 /* IO CRB Entry 6_B */
+#define IIO_ICRB6_C 0x00400530 /* IO CRB Entry 6_C */
+#define IIO_ICRB6_D 0x00400538 /* IO CRB Entry 6_D */
+#define IIO_ICRB6_E 0x00400540 /* IO CRB Entry 6_E */
+
+#define IIO_ICRB7_A 0x00400550 /* IO CRB Entry 7_A */
+#define IIO_ICRB7_B 0x00400558 /* IO CRB Entry 7_B */
+#define IIO_ICRB7_C 0x00400560 /* IO CRB Entry 7_C */
+#define IIO_ICRB7_D 0x00400568 /* IO CRB Entry 7_D */
+#define IIO_ICRB7_E 0x00400570 /* IO CRB Entry 7_E */
+
+#define IIO_ICRB8_A 0x00400580 /* IO CRB Entry 8_A */
+#define IIO_ICRB8_B 0x00400588 /* IO CRB Entry 8_B */
+#define IIO_ICRB8_C 0x00400590 /* IO CRB Entry 8_C */
+#define IIO_ICRB8_D 0x00400598 /* IO CRB Entry 8_D */
+#define IIO_ICRB8_E 0x004005a0 /* IO CRB Entry 8_E */
+
+#define IIO_ICRB9_A 0x004005b0 /* IO CRB Entry 9_A */
+#define IIO_ICRB9_B 0x004005b8 /* IO CRB Entry 9_B */
+#define IIO_ICRB9_C 0x004005c0 /* IO CRB Entry 9_C */
+#define IIO_ICRB9_D 0x004005c8 /* IO CRB Entry 9_D */
+#define IIO_ICRB9_E 0x004005d0 /* IO CRB Entry 9_E */
+
+#define IIO_ICRBA_A 0x004005e0 /* IO CRB Entry A_A */
+#define IIO_ICRBA_B 0x004005e8 /* IO CRB Entry A_B */
+#define IIO_ICRBA_C 0x004005f0 /* IO CRB Entry A_C */
+#define IIO_ICRBA_D 0x004005f8 /* IO CRB Entry A_D */
+#define IIO_ICRBA_E 0x00400600 /* IO CRB Entry A_E */
+
+#define IIO_ICRBB_A 0x00400610 /* IO CRB Entry B_A */
+#define IIO_ICRBB_B 0x00400618 /* IO CRB Entry B_B */
+#define IIO_ICRBB_C 0x00400620 /* IO CRB Entry B_C */
+#define IIO_ICRBB_D 0x00400628 /* IO CRB Entry B_D */
+#define IIO_ICRBB_E 0x00400630 /* IO CRB Entry B_E */
+
+#define IIO_ICRBC_A 0x00400640 /* IO CRB Entry C_A */
+#define IIO_ICRBC_B 0x00400648 /* IO CRB Entry C_B */
+#define IIO_ICRBC_C 0x00400650 /* IO CRB Entry C_C */
+#define IIO_ICRBC_D 0x00400658 /* IO CRB Entry C_D */
+#define IIO_ICRBC_E 0x00400660 /* IO CRB Entry C_E */
+
+#define IIO_ICRBD_A 0x00400670 /* IO CRB Entry D_A */
+#define IIO_ICRBD_B 0x00400678 /* IO CRB Entry D_B */
+#define IIO_ICRBD_C 0x00400680 /* IO CRB Entry D_C */
+#define IIO_ICRBD_D 0x00400688 /* IO CRB Entry D_D */
+#define IIO_ICRBD_E 0x00400690 /* IO CRB Entry D_E */
+
+#define IIO_ICRBE_A 0x004006a0 /* IO CRB Entry E_A */
+#define IIO_ICRBE_B 0x004006a8 /* IO CRB Entry E_B */
+#define IIO_ICRBE_C 0x004006b0 /* IO CRB Entry E_C */
+#define IIO_ICRBE_D 0x004006b8 /* IO CRB Entry E_D */
+#define IIO_ICRBE_E 0x004006c0 /* IO CRB Entry E_E */
+
+#define IIO_ICSML 0x00400700 /* IO CRB Spurious Message Low */
+#define IIO_ICSMM 0x00400708 /* IO CRB Spurious Message Middle */
+#define IIO_ICSMH 0x00400710 /* IO CRB Spurious Message High */
+
+#define IIO_IDBSS 0x00400718 /* IO Debug Submenu Select */
+
+#define IIO_IBLS0 0x00410000 /* IO BTE Length Status 0 */
+#define IIO_IBSA0 0x00410008 /* IO BTE Source Address 0 */
+#define IIO_IBDA0 0x00410010 /* IO BTE Destination Address 0 */
+#define IIO_IBCT0 0x00410018 /* IO BTE Control Terminate 0 */
+#define IIO_IBNA0 0x00410020 /* IO BTE Notification Address 0 */
+#define IIO_IBIA0 0x00410028 /* IO BTE Interrupt Address 0 */
+#define IIO_IBLS1 0x00420000 /* IO BTE Length Status 1 */
+#define IIO_IBSA1 0x00420008 /* IO BTE Source Address 1 */
+#define IIO_IBDA1 0x00420010 /* IO BTE Destination Address 1 */
+#define IIO_IBCT1 0x00420018 /* IO BTE Control Terminate 1 */
+#define IIO_IBNA1 0x00420020 /* IO BTE Notification Address 1 */
+#define IIO_IBIA1 0x00420028 /* IO BTE Interrupt Address 1 */
+
+#define IIO_IPCR 0x00430000 /* IO Performance Control */
+#define IIO_IPPR 0x00430008 /* IO Performance Profiling */
+
+/************************************************************************
+ * *
+ * Description: This register echoes some information from the *
+ * LB_REV_ID register. It is available through Crosstalk as described *
+ * above. The REV_NUM and MFG_NUM fields receive their values from *
+ * the REVISION and MANUFACTURER fields in the LB_REV_ID register. *
+ * The PART_NUM field's value is the Crosstalk device ID number that *
+ * Steve Miller assigned to the SHub chip. *
+ * *
+ ************************************************************************/
+
+typedef union ii_wid_u {
+ u64 ii_wid_regval;
+ struct {
+ u64 w_rsvd_1:1;
+ u64 w_mfg_num:11;
+ u64 w_part_num:16;
+ u64 w_rev_num:4;
+ u64 w_rsvd:32;
+ } ii_wid_fld_s;
+} ii_wid_u_t;
+
+/************************************************************************
+ * *
+ * The fields in this register are set upon detection of an error *
+ * and cleared by various mechanisms, as explained in the *
+ * description. *
+ * *
+ ************************************************************************/
+
+typedef union ii_wstat_u {
+ u64 ii_wstat_regval;
+ struct {
+ u64 w_pending:4;
+ u64 w_xt_crd_to:1;
+ u64 w_xt_tail_to:1;
+ u64 w_rsvd_3:3;
+ u64 w_tx_mx_rty:1;
+ u64 w_rsvd_2:6;
+ u64 w_llp_tx_cnt:8;
+ u64 w_rsvd_1:8;
+ u64 w_crazy:1;
+ u64 w_rsvd:31;
+ } ii_wstat_fld_s;
+} ii_wstat_u_t;
+
+/************************************************************************
+ * *
+ * Description: This is a read-write enabled register. It controls *
+ * various aspects of the Crosstalk flow control. *
+ * *
+ ************************************************************************/
+
+typedef union ii_wcr_u {
+ u64 ii_wcr_regval;
+ struct {
+ u64 w_wid:4;
+ u64 w_tag:1;
+ u64 w_rsvd_1:8;
+ u64 w_dst_crd:3;
+ u64 w_f_bad_pkt:1;
+ u64 w_dir_con:1;
+ u64 w_e_thresh:5;
+ u64 w_rsvd:41;
+ } ii_wcr_fld_s;
+} ii_wcr_u_t;
+
+/************************************************************************
+ * *
+ * Description: This register's value is a bit vector that guards *
+ * access to local registers within the II as well as to external *
+ * Crosstalk widgets. Each bit in the register corresponds to a *
+ * particular region in the system; a region consists of one, two or *
+ * four nodes (depending on the value of the REGION_SIZE field in the *
+ * LB_REV_ID register, which is documented in Section 8.3.1.1). The *
+ * protection provided by this register applies to PIO read *
+ * operations as well as PIO write operations. The II will perform a *
+ * PIO read or write request only if the bit for the requestor's *
+ * region is set; otherwise, the II will not perform the requested *
+ * operation and will return an error response. When a PIO read or *
+ * write request targets an external Crosstalk widget, then not only *
+ * must the bit for the requestor's region be set in the ILAPR, but *
+ * also the target widget's bit in the IOWA register must be set in *
+ * order for the II to perform the requested operation; otherwise, *
+ * the II will return an error response. Hence, the protection *
+ * provided by the IOWA register supplements the protection provided *
+ * by the ILAPR for requests that target external Crosstalk widgets. *
+ * This register itself can be accessed only by the nodes whose *
+ * region ID bits are enabled in this same register. It can also be *
+ * accessed through the IAlias space by the local processors. *
+ * The reset value of this register allows access by all nodes. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ilapr_u {
+ u64 ii_ilapr_regval;
+ struct {
+ u64 i_region:64;
+ } ii_ilapr_fld_s;
+} ii_ilapr_u_t;
+
+/************************************************************************
+ * *
+ * Description: A write to this register of the 64-bit value *
+ * "SGIrules" in ASCII, will cause the bit in the ILAPR register *
+ * corresponding to the region of the requestor to be set (allow *
+ * access). A write of any other value will be ignored. Access *
+ * protection for this register is "SGIrules". *
+ * This register can also be accessed through the IAlias space. *
+ * However, this access will not change the access permissions in the *
+ * ILAPR. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ilapo_u {
+ u64 ii_ilapo_regval;
+ struct {
+ u64 i_io_ovrride:64;
+ } ii_ilapo_fld_s;
+} ii_ilapo_u_t;
+
+/************************************************************************
+ * *
+ * This register qualifies all the PIO and Graphics writes launched *
+ * from the SHUB towards a widget. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iowa_u {
+ u64 ii_iowa_regval;
+ struct {
+ u64 i_w0_oac:1;
+ u64 i_rsvd_1:7;
+ u64 i_wx_oac:8;
+ u64 i_rsvd:48;
+ } ii_iowa_fld_s;
+} ii_iowa_u_t;
+
+/************************************************************************
+ * *
+ * Description: This register qualifies all the requests launched *
+ * from a widget towards the Shub. This register is intended to be *
+ * used by software in case of misbehaving widgets. *
+ * *
+ * *
+ ************************************************************************/
+
+typedef union ii_iiwa_u {
+ u64 ii_iiwa_regval;
+ struct {
+ u64 i_w0_iac:1;
+ u64 i_rsvd_1:7;
+ u64 i_wx_iac:8;
+ u64 i_rsvd:48;
+ } ii_iiwa_fld_s;
+} ii_iiwa_u_t;
+
+/************************************************************************
+ * *
+ * Description: This register qualifies all the operations launched *
+ * from a widget towards the SHub. It allows individual access *
+ * control for up to 8 devices per widget. A device refers to *
+ * individual DMA master hosted by a widget. *
+ * The bits in each field of this register are cleared by the Shub *
+ * upon detection of an error which requires the device to be *
+ * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric *
+ * Crosstalk). Whether or not a device has access rights to this *
+ * Shub is determined by an AND of the device enable bit in the *
+ * appropriate field of this register and the corresponding bit in *
+ * the Wx_IAC field (for the widget which this device belongs to). *
+ * The bits in this field are set by writing a 1 to them. Incoming *
+ * replies from Crosstalk are not subject to this access control *
+ * mechanism. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iidem_u {
+ u64 ii_iidem_regval;
+ struct {
+ u64 i_w8_dxs:8;
+ u64 i_w9_dxs:8;
+ u64 i_wa_dxs:8;
+ u64 i_wb_dxs:8;
+ u64 i_wc_dxs:8;
+ u64 i_wd_dxs:8;
+ u64 i_we_dxs:8;
+ u64 i_wf_dxs:8;
+ } ii_iidem_fld_s;
+} ii_iidem_u_t;
+
+/************************************************************************
+ * *
+ * This register contains the various programmable fields necessary *
+ * for controlling and observing the LLP signals. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ilcsr_u {
+ u64 ii_ilcsr_regval;
+ struct {
+ u64 i_nullto:6;
+ u64 i_rsvd_4:2;
+ u64 i_wrmrst:1;
+ u64 i_rsvd_3:1;
+ u64 i_llp_en:1;
+ u64 i_bm8:1;
+ u64 i_llp_stat:2;
+ u64 i_remote_power:1;
+ u64 i_rsvd_2:1;
+ u64 i_maxrtry:10;
+ u64 i_d_avail_sel:2;
+ u64 i_rsvd_1:4;
+ u64 i_maxbrst:10;
+ u64 i_rsvd:22;
+
+ } ii_ilcsr_fld_s;
+} ii_ilcsr_u_t;
+
+/************************************************************************
+ * *
+ * This is simply a status registers that monitors the LLP error *
+ * rate. *
+ * *
+ ************************************************************************/
+
+typedef union ii_illr_u {
+ u64 ii_illr_regval;
+ struct {
+ u64 i_sn_cnt:16;
+ u64 i_cb_cnt:16;
+ u64 i_rsvd:32;
+ } ii_illr_fld_s;
+} ii_illr_u_t;
+
+/************************************************************************
+ * *
+ * Description: All II-detected non-BTE error interrupts are *
+ * specified via this register. *
+ * NOTE: The PI interrupt register address is hardcoded in the II. If *
+ * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI *
+ * packet) to address offset 0x0180_0090 within the local register *
+ * address space of PI0 on the node specified by the NODE field. If *
+ * PI_ID==1, then the II sends the interrupt request to address *
+ * offset 0x01A0_0090 within the local register address space of PI1 *
+ * on the node specified by the NODE field. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iidsr_u {
+ u64 ii_iidsr_regval;
+ struct {
+ u64 i_level:8;
+ u64 i_pi_id:1;
+ u64 i_node:11;
+ u64 i_rsvd_3:4;
+ u64 i_enable:1;
+ u64 i_rsvd_2:3;
+ u64 i_int_sent:2;
+ u64 i_rsvd_1:2;
+ u64 i_pi0_forward_int:1;
+ u64 i_pi1_forward_int:1;
+ u64 i_rsvd:30;
+ } ii_iidsr_fld_s;
+} ii_iidsr_u_t;
+
+/************************************************************************
+ * *
+ * There are two instances of this register. This register is used *
+ * for matching up the incoming responses from the graphics widget to *
+ * the processor that initiated the graphics operation. The *
+ * write-responses are converted to graphics credits and returned to *
+ * the processor so that the processor interface can manage the flow *
+ * control. *
+ * *
+ ************************************************************************/
+
+typedef union ii_igfx0_u {
+ u64 ii_igfx0_regval;
+ struct {
+ u64 i_w_num:4;
+ u64 i_pi_id:1;
+ u64 i_n_num:12;
+ u64 i_p_num:1;
+ u64 i_rsvd:46;
+ } ii_igfx0_fld_s;
+} ii_igfx0_u_t;
+
+/************************************************************************
+ * *
+ * There are two instances of this register. This register is used *
+ * for matching up the incoming responses from the graphics widget to *
+ * the processor that initiated the graphics operation. The *
+ * write-responses are converted to graphics credits and returned to *
+ * the processor so that the processor interface can manage the flow *
+ * control. *
+ * *
+ ************************************************************************/
+
+typedef union ii_igfx1_u {
+ u64 ii_igfx1_regval;
+ struct {
+ u64 i_w_num:4;
+ u64 i_pi_id:1;
+ u64 i_n_num:12;
+ u64 i_p_num:1;
+ u64 i_rsvd:46;
+ } ii_igfx1_fld_s;
+} ii_igfx1_u_t;
+
+/************************************************************************
+ * *
+ * There are two instances of this registers. These registers are *
+ * used as scratch registers for software use. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iscr0_u {
+ u64 ii_iscr0_regval;
+ struct {
+ u64 i_scratch:64;
+ } ii_iscr0_fld_s;
+} ii_iscr0_u_t;
+
+/************************************************************************
+ * *
+ * There are two instances of this registers. These registers are *
+ * used as scratch registers for software use. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iscr1_u {
+ u64 ii_iscr1_regval;
+ struct {
+ u64 i_scratch:64;
+ } ii_iscr1_fld_s;
+} ii_iscr1_u_t;
+
+/************************************************************************
+ * *
+ * Description: There are seven instances of translation table entry *
+ * registers. Each register maps a Shub Big Window to a 48-bit *
+ * address on Crosstalk. *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
+ * number) are used to select one of these 7 registers. The Widget *
+ * number field is then derived from the W_NUM field for synthesizing *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
+ * are padded with zeros. Although the maximum Crosstalk space *
+ * addressable by the SHub is thus the lower 16 GBytes per widget *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
+ * space can be accessed. *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
+ * Window number) are used to select one of these 7 registers. The *
+ * Widget number field is then derived from the W_NUM field for *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum *
+ * Crosstalk space addressable by the Shub is thus the lower *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
+ * of this space can be accessed. *
+ * *
+ ************************************************************************/
+
+typedef union ii_itte1_u {
+ u64 ii_itte1_regval;
+ struct {
+ u64 i_offset:5;
+ u64 i_rsvd_1:3;
+ u64 i_w_num:4;
+ u64 i_iosp:1;
+ u64 i_rsvd:51;
+ } ii_itte1_fld_s;
+} ii_itte1_u_t;
+
+/************************************************************************
+ * *
+ * Description: There are seven instances of translation table entry *
+ * registers. Each register maps a Shub Big Window to a 48-bit *
+ * address on Crosstalk. *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
+ * number) are used to select one of these 7 registers. The Widget *
+ * number field is then derived from the W_NUM field for synthesizing *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
+ * are padded with zeros. Although the maximum Crosstalk space *
+ * addressable by the Shub is thus the lower 16 GBytes per widget *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
+ * space can be accessed. *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
+ * Window number) are used to select one of these 7 registers. The *
+ * Widget number field is then derived from the W_NUM field for *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum *
+ * Crosstalk space addressable by the Shub is thus the lower *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
+ * of this space can be accessed. *
+ * *
+ ************************************************************************/
+
+typedef union ii_itte2_u {
+ u64 ii_itte2_regval;
+ struct {
+ u64 i_offset:5;
+ u64 i_rsvd_1:3;
+ u64 i_w_num:4;
+ u64 i_iosp:1;
+ u64 i_rsvd:51;
+ } ii_itte2_fld_s;
+} ii_itte2_u_t;
+
+/************************************************************************
+ * *
+ * Description: There are seven instances of translation table entry *
+ * registers. Each register maps a Shub Big Window to a 48-bit *
+ * address on Crosstalk. *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
+ * number) are used to select one of these 7 registers. The Widget *
+ * number field is then derived from the W_NUM field for synthesizing *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
+ * are padded with zeros. Although the maximum Crosstalk space *
+ * addressable by the Shub is thus the lower 16 GBytes per widget *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
+ * space can be accessed. *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
+ * Window number) are used to select one of these 7 registers. The *
+ * Widget number field is then derived from the W_NUM field for *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum *
+ * Crosstalk space addressable by the SHub is thus the lower *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
+ * of this space can be accessed. *
+ * *
+ ************************************************************************/
+
+typedef union ii_itte3_u {
+ u64 ii_itte3_regval;
+ struct {
+ u64 i_offset:5;
+ u64 i_rsvd_1:3;
+ u64 i_w_num:4;
+ u64 i_iosp:1;
+ u64 i_rsvd:51;
+ } ii_itte3_fld_s;
+} ii_itte3_u_t;
+
+/************************************************************************
+ * *
+ * Description: There are seven instances of translation table entry *
+ * registers. Each register maps a SHub Big Window to a 48-bit *
+ * address on Crosstalk. *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
+ * number) are used to select one of these 7 registers. The Widget *
+ * number field is then derived from the W_NUM field for synthesizing *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
+ * are padded with zeros. Although the maximum Crosstalk space *
+ * addressable by the SHub is thus the lower 16 GBytes per widget *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
+ * space can be accessed. *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
+ * Window number) are used to select one of these 7 registers. The *
+ * Widget number field is then derived from the W_NUM field for *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum *
+ * Crosstalk space addressable by the SHub is thus the lower *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
+ * of this space can be accessed. *
+ * *
+ ************************************************************************/
+
+typedef union ii_itte4_u {
+ u64 ii_itte4_regval;
+ struct {
+ u64 i_offset:5;
+ u64 i_rsvd_1:3;
+ u64 i_w_num:4;
+ u64 i_iosp:1;
+ u64 i_rsvd:51;
+ } ii_itte4_fld_s;
+} ii_itte4_u_t;
+
+/************************************************************************
+ * *
+ * Description: There are seven instances of translation table entry *
+ * registers. Each register maps a SHub Big Window to a 48-bit *
+ * address on Crosstalk. *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
+ * number) are used to select one of these 7 registers. The Widget *
+ * number field is then derived from the W_NUM field for synthesizing *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
+ * are padded with zeros. Although the maximum Crosstalk space *
+ * addressable by the Shub is thus the lower 16 GBytes per widget *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
+ * space can be accessed. *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
+ * Window number) are used to select one of these 7 registers. The *
+ * Widget number field is then derived from the W_NUM field for *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum *
+ * Crosstalk space addressable by the Shub is thus the lower *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
+ * of this space can be accessed. *
+ * *
+ ************************************************************************/
+
+typedef union ii_itte5_u {
+ u64 ii_itte5_regval;
+ struct {
+ u64 i_offset:5;
+ u64 i_rsvd_1:3;
+ u64 i_w_num:4;
+ u64 i_iosp:1;
+ u64 i_rsvd:51;
+ } ii_itte5_fld_s;
+} ii_itte5_u_t;
+
+/************************************************************************
+ * *
+ * Description: There are seven instances of translation table entry *
+ * registers. Each register maps a Shub Big Window to a 48-bit *
+ * address on Crosstalk. *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
+ * number) are used to select one of these 7 registers. The Widget *
+ * number field is then derived from the W_NUM field for synthesizing *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
+ * are padded with zeros. Although the maximum Crosstalk space *
+ * addressable by the Shub is thus the lower 16 GBytes per widget *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
+ * space can be accessed. *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
+ * Window number) are used to select one of these 7 registers. The *
+ * Widget number field is then derived from the W_NUM field for *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum *
+ * Crosstalk space addressable by the Shub is thus the lower *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
+ * of this space can be accessed. *
+ * *
+ ************************************************************************/
+
+typedef union ii_itte6_u {
+ u64 ii_itte6_regval;
+ struct {
+ u64 i_offset:5;
+ u64 i_rsvd_1:3;
+ u64 i_w_num:4;
+ u64 i_iosp:1;
+ u64 i_rsvd:51;
+ } ii_itte6_fld_s;
+} ii_itte6_u_t;
+
+/************************************************************************
+ * *
+ * Description: There are seven instances of translation table entry *
+ * registers. Each register maps a Shub Big Window to a 48-bit *
+ * address on Crosstalk. *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
+ * number) are used to select one of these 7 registers. The Widget *
+ * number field is then derived from the W_NUM field for synthesizing *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
+ * are padded with zeros. Although the maximum Crosstalk space *
+ * addressable by the Shub is thus the lower 16 GBytes per widget *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
+ * space can be accessed. *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
+ * Window number) are used to select one of these 7 registers. The *
+ * Widget number field is then derived from the W_NUM field for *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum *
+ * Crosstalk space addressable by the SHub is thus the lower *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
+ * of this space can be accessed. *
+ * *
+ ************************************************************************/
+
+typedef union ii_itte7_u {
+ u64 ii_itte7_regval;
+ struct {
+ u64 i_offset:5;
+ u64 i_rsvd_1:3;
+ u64 i_w_num:4;
+ u64 i_iosp:1;
+ u64 i_rsvd:51;
+ } ii_itte7_fld_s;
+} ii_itte7_u_t;
+
+/************************************************************************
+ * *
+ * Description: There are 9 instances of this register, one per *
+ * actual widget in this implementation of SHub and Crossbow. *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
+ * refers to Crossbow's internal space. *
+ * This register contains the state elements per widget that are *
+ * necessary to manage the PIO flow control on Crosstalk and on the *
+ * Router Network. See the PIO Flow Control chapter for a complete *
+ * description of this register *
+ * The SPUR_WR bit requires some explanation. When this register is *
+ * written, the new value of the C field is captured in an internal *
+ * register so the hardware can remember what the programmer wrote *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field *
+ * increments above this stored value, which indicates that there *
+ * have been more responses received than requests sent. The SPUR_WR *
+ * bit cannot be cleared until a value is written to the IPRBx *
+ * register; the write will correct the C field and capture its new *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
+ * . *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprb0_u {
+ u64 ii_iprb0_regval;
+ struct {
+ u64 i_c:8;
+ u64 i_na:14;
+ u64 i_rsvd_2:2;
+ u64 i_nb:14;
+ u64 i_rsvd_1:2;
+ u64 i_m:2;
+ u64 i_f:1;
+ u64 i_of_cnt:5;
+ u64 i_error:1;
+ u64 i_rd_to:1;
+ u64 i_spur_wr:1;
+ u64 i_spur_rd:1;
+ u64 i_rsvd:11;
+ u64 i_mult_err:1;
+ } ii_iprb0_fld_s;
+} ii_iprb0_u_t;
+
+/************************************************************************
+ * *
+ * Description: There are 9 instances of this register, one per *
+ * actual widget in this implementation of SHub and Crossbow. *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
+ * refers to Crossbow's internal space. *
+ * This register contains the state elements per widget that are *
+ * necessary to manage the PIO flow control on Crosstalk and on the *
+ * Router Network. See the PIO Flow Control chapter for a complete *
+ * description of this register *
+ * The SPUR_WR bit requires some explanation. When this register is *
+ * written, the new value of the C field is captured in an internal *
+ * register so the hardware can remember what the programmer wrote *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field *
+ * increments above this stored value, which indicates that there *
+ * have been more responses received than requests sent. The SPUR_WR *
+ * bit cannot be cleared until a value is written to the IPRBx *
+ * register; the write will correct the C field and capture its new *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
+ * . *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprb8_u {
+ u64 ii_iprb8_regval;
+ struct {
+ u64 i_c:8;
+ u64 i_na:14;
+ u64 i_rsvd_2:2;
+ u64 i_nb:14;
+ u64 i_rsvd_1:2;
+ u64 i_m:2;
+ u64 i_f:1;
+ u64 i_of_cnt:5;
+ u64 i_error:1;
+ u64 i_rd_to:1;
+ u64 i_spur_wr:1;
+ u64 i_spur_rd:1;
+ u64 i_rsvd:11;
+ u64 i_mult_err:1;
+ } ii_iprb8_fld_s;
+} ii_iprb8_u_t;
+
+/************************************************************************
+ * *
+ * Description: There are 9 instances of this register, one per *
+ * actual widget in this implementation of SHub and Crossbow. *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
+ * refers to Crossbow's internal space. *
+ * This register contains the state elements per widget that are *
+ * necessary to manage the PIO flow control on Crosstalk and on the *
+ * Router Network. See the PIO Flow Control chapter for a complete *
+ * description of this register *
+ * The SPUR_WR bit requires some explanation. When this register is *
+ * written, the new value of the C field is captured in an internal *
+ * register so the hardware can remember what the programmer wrote *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field *
+ * increments above this stored value, which indicates that there *
+ * have been more responses received than requests sent. The SPUR_WR *
+ * bit cannot be cleared until a value is written to the IPRBx *
+ * register; the write will correct the C field and capture its new *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
+ * . *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprb9_u {
+ u64 ii_iprb9_regval;
+ struct {
+ u64 i_c:8;
+ u64 i_na:14;
+ u64 i_rsvd_2:2;
+ u64 i_nb:14;
+ u64 i_rsvd_1:2;
+ u64 i_m:2;
+ u64 i_f:1;
+ u64 i_of_cnt:5;
+ u64 i_error:1;
+ u64 i_rd_to:1;
+ u64 i_spur_wr:1;
+ u64 i_spur_rd:1;
+ u64 i_rsvd:11;
+ u64 i_mult_err:1;
+ } ii_iprb9_fld_s;
+} ii_iprb9_u_t;
+
+/************************************************************************
+ * *
+ * Description: There are 9 instances of this register, one per *
+ * actual widget in this implementation of SHub and Crossbow. *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
+ * refers to Crossbow's internal space. *
+ * This register contains the state elements per widget that are *
+ * necessary to manage the PIO flow control on Crosstalk and on the *
+ * Router Network. See the PIO Flow Control chapter for a complete *
+ * description of this register *
+ * The SPUR_WR bit requires some explanation. When this register is *
+ * written, the new value of the C field is captured in an internal *
+ * register so the hardware can remember what the programmer wrote *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field *
+ * increments above this stored value, which indicates that there *
+ * have been more responses received than requests sent. The SPUR_WR *
+ * bit cannot be cleared until a value is written to the IPRBx *
+ * register; the write will correct the C field and capture its new *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
+ * *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprba_u {
+ u64 ii_iprba_regval;
+ struct {
+ u64 i_c:8;
+ u64 i_na:14;
+ u64 i_rsvd_2:2;
+ u64 i_nb:14;
+ u64 i_rsvd_1:2;
+ u64 i_m:2;
+ u64 i_f:1;
+ u64 i_of_cnt:5;
+ u64 i_error:1;
+ u64 i_rd_to:1;
+ u64 i_spur_wr:1;
+ u64 i_spur_rd:1;
+ u64 i_rsvd:11;
+ u64 i_mult_err:1;
+ } ii_iprba_fld_s;
+} ii_iprba_u_t;
+
+/************************************************************************
+ * *
+ * Description: There are 9 instances of this register, one per *
+ * actual widget in this implementation of SHub and Crossbow. *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
+ * refers to Crossbow's internal space. *
+ * This register contains the state elements per widget that are *
+ * necessary to manage the PIO flow control on Crosstalk and on the *
+ * Router Network. See the PIO Flow Control chapter for a complete *
+ * description of this register *
+ * The SPUR_WR bit requires some explanation. When this register is *
+ * written, the new value of the C field is captured in an internal *
+ * register so the hardware can remember what the programmer wrote *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field *
+ * increments above this stored value, which indicates that there *
+ * have been more responses received than requests sent. The SPUR_WR *
+ * bit cannot be cleared until a value is written to the IPRBx *
+ * register; the write will correct the C field and capture its new *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
+ * . *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprbb_u {
+ u64 ii_iprbb_regval;
+ struct {
+ u64 i_c:8;
+ u64 i_na:14;
+ u64 i_rsvd_2:2;
+ u64 i_nb:14;
+ u64 i_rsvd_1:2;
+ u64 i_m:2;
+ u64 i_f:1;
+ u64 i_of_cnt:5;
+ u64 i_error:1;
+ u64 i_rd_to:1;
+ u64 i_spur_wr:1;
+ u64 i_spur_rd:1;
+ u64 i_rsvd:11;
+ u64 i_mult_err:1;
+ } ii_iprbb_fld_s;
+} ii_iprbb_u_t;
+
+/************************************************************************
+ * *
+ * Description: There are 9 instances of this register, one per *
+ * actual widget in this implementation of SHub and Crossbow. *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
+ * refers to Crossbow's internal space. *
+ * This register contains the state elements per widget that are *
+ * necessary to manage the PIO flow control on Crosstalk and on the *
+ * Router Network. See the PIO Flow Control chapter for a complete *
+ * description of this register *
+ * The SPUR_WR bit requires some explanation. When this register is *
+ * written, the new value of the C field is captured in an internal *
+ * register so the hardware can remember what the programmer wrote *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field *
+ * increments above this stored value, which indicates that there *
+ * have been more responses received than requests sent. The SPUR_WR *
+ * bit cannot be cleared until a value is written to the IPRBx *
+ * register; the write will correct the C field and capture its new *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
+ * . *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprbc_u {
+ u64 ii_iprbc_regval;
+ struct {
+ u64 i_c:8;
+ u64 i_na:14;
+ u64 i_rsvd_2:2;
+ u64 i_nb:14;
+ u64 i_rsvd_1:2;
+ u64 i_m:2;
+ u64 i_f:1;
+ u64 i_of_cnt:5;
+ u64 i_error:1;
+ u64 i_rd_to:1;
+ u64 i_spur_wr:1;
+ u64 i_spur_rd:1;
+ u64 i_rsvd:11;
+ u64 i_mult_err:1;
+ } ii_iprbc_fld_s;
+} ii_iprbc_u_t;
+
+/************************************************************************
+ * *
+ * Description: There are 9 instances of this register, one per *
+ * actual widget in this implementation of SHub and Crossbow. *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
+ * refers to Crossbow's internal space. *
+ * This register contains the state elements per widget that are *
+ * necessary to manage the PIO flow control on Crosstalk and on the *
+ * Router Network. See the PIO Flow Control chapter for a complete *
+ * description of this register *
+ * The SPUR_WR bit requires some explanation. When this register is *
+ * written, the new value of the C field is captured in an internal *
+ * register so the hardware can remember what the programmer wrote *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field *
+ * increments above this stored value, which indicates that there *
+ * have been more responses received than requests sent. The SPUR_WR *
+ * bit cannot be cleared until a value is written to the IPRBx *
+ * register; the write will correct the C field and capture its new *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
+ * . *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprbd_u {
+ u64 ii_iprbd_regval;
+ struct {
+ u64 i_c:8;
+ u64 i_na:14;
+ u64 i_rsvd_2:2;
+ u64 i_nb:14;
+ u64 i_rsvd_1:2;
+ u64 i_m:2;
+ u64 i_f:1;
+ u64 i_of_cnt:5;
+ u64 i_error:1;
+ u64 i_rd_to:1;
+ u64 i_spur_wr:1;
+ u64 i_spur_rd:1;
+ u64 i_rsvd:11;
+ u64 i_mult_err:1;
+ } ii_iprbd_fld_s;
+} ii_iprbd_u_t;
+
+/************************************************************************
+ * *
+ * Description: There are 9 instances of this register, one per *
+ * actual widget in this implementation of SHub and Crossbow. *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
+ * refers to Crossbow's internal space. *
+ * This register contains the state elements per widget that are *
+ * necessary to manage the PIO flow control on Crosstalk and on the *
+ * Router Network. See the PIO Flow Control chapter for a complete *
+ * description of this register *
+ * The SPUR_WR bit requires some explanation. When this register is *
+ * written, the new value of the C field is captured in an internal *
+ * register so the hardware can remember what the programmer wrote *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field *
+ * increments above this stored value, which indicates that there *
+ * have been more responses received than requests sent. The SPUR_WR *
+ * bit cannot be cleared until a value is written to the IPRBx *
+ * register; the write will correct the C field and capture its new *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
+ * . *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprbe_u {
+ u64 ii_iprbe_regval;
+ struct {
+ u64 i_c:8;
+ u64 i_na:14;
+ u64 i_rsvd_2:2;
+ u64 i_nb:14;
+ u64 i_rsvd_1:2;
+ u64 i_m:2;
+ u64 i_f:1;
+ u64 i_of_cnt:5;
+ u64 i_error:1;
+ u64 i_rd_to:1;
+ u64 i_spur_wr:1;
+ u64 i_spur_rd:1;
+ u64 i_rsvd:11;
+ u64 i_mult_err:1;
+ } ii_iprbe_fld_s;
+} ii_iprbe_u_t;
+
+/************************************************************************
+ * *
+ * Description: There are 9 instances of this register, one per *
+ * actual widget in this implementation of Shub and Crossbow. *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
+ * refers to Crossbow's internal space. *
+ * This register contains the state elements per widget that are *
+ * necessary to manage the PIO flow control on Crosstalk and on the *
+ * Router Network. See the PIO Flow Control chapter for a complete *
+ * description of this register *
+ * The SPUR_WR bit requires some explanation. When this register is *
+ * written, the new value of the C field is captured in an internal *
+ * register so the hardware can remember what the programmer wrote *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field *
+ * increments above this stored value, which indicates that there *
+ * have been more responses received than requests sent. The SPUR_WR *
+ * bit cannot be cleared until a value is written to the IPRBx *
+ * register; the write will correct the C field and capture its new *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
+ * . *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprbf_u {
+ u64 ii_iprbf_regval;
+ struct {
+ u64 i_c:8;
+ u64 i_na:14;
+ u64 i_rsvd_2:2;
+ u64 i_nb:14;
+ u64 i_rsvd_1:2;
+ u64 i_m:2;
+ u64 i_f:1;
+ u64 i_of_cnt:5;
+ u64 i_error:1;
+ u64 i_rd_to:1;
+ u64 i_spur_wr:1;
+ u64 i_spur_rd:1;
+ u64 i_rsvd:11;
+ u64 i_mult_err:1;
+ } ii_iprbe_fld_s;
+} ii_iprbf_u_t;
+
+/************************************************************************
+ * *
+ * This register specifies the timeout value to use for monitoring *
+ * Crosstalk credits which are used outbound to Crosstalk. An *
+ * internal counter called the Crosstalk Credit Timeout Counter *
+ * increments every 128 II clocks. The counter starts counting *
+ * anytime the credit count drops below a threshold, and resets to *
+ * zero (stops counting) anytime the credit count is at or above the *
+ * threshold. The threshold is 1 credit in direct connect mode and 2 *
+ * in Crossbow connect mode. When the internal Crosstalk Credit *
+ * Timeout Counter reaches the value programmed in this register, a *
+ * Crosstalk Credit Timeout has occurred. The internal counter is not *
+ * readable from software, and stops counting at its maximum value, *
+ * so it cannot cause more than one interrupt. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ixcc_u {
+ u64 ii_ixcc_regval;
+ struct {
+ u64 i_time_out:26;
+ u64 i_rsvd:38;
+ } ii_ixcc_fld_s;
+} ii_ixcc_u_t;
+
+/************************************************************************
+ * *
+ * Description: This register qualifies all the PIO and DMA *
+ * operations launched from widget 0 towards the SHub. In *
+ * addition, it also qualifies accesses by the BTE streams. *
+ * The bits in each field of this register are cleared by the SHub *
+ * upon detection of an error which requires widget 0 or the BTE *
+ * streams to be terminated. Whether or not widget x has access *
+ * rights to this SHub is determined by an AND of the device *
+ * enable bit in the appropriate field of this register and bit 0 in *
+ * the Wx_IAC field. The bits in this field are set by writing a 1 to *
+ * them. Incoming replies from Crosstalk are not subject to this *
+ * access control mechanism. *
+ * *
+ ************************************************************************/
+
+typedef union ii_imem_u {
+ u64 ii_imem_regval;
+ struct {
+ u64 i_w0_esd:1;
+ u64 i_rsvd_3:3;
+ u64 i_b0_esd:1;
+ u64 i_rsvd_2:3;
+ u64 i_b1_esd:1;
+ u64 i_rsvd_1:3;
+ u64 i_clr_precise:1;
+ u64 i_rsvd:51;
+ } ii_imem_fld_s;
+} ii_imem_u_t;
+
+/************************************************************************
+ * *
+ * Description: This register specifies the timeout value to use for *
+ * monitoring Crosstalk tail flits coming into the Shub in the *
+ * TAIL_TO field. An internal counter associated with this register *
+ * is incremented every 128 II internal clocks (7 bits). The counter *
+ * starts counting anytime a header micropacket is received and stops *
+ * counting (and resets to zero) any time a micropacket with a Tail *
+ * bit is received. Once the counter reaches the threshold value *
+ * programmed in this register, it generates an interrupt to the *
+ * processor that is programmed into the IIDSR. The counter saturates *
+ * (does not roll over) at its maximum value, so it cannot cause *
+ * another interrupt until after it is cleared. *
+ * The register also contains the Read Response Timeout values. The *
+ * Prescalar is 23 bits, and counts II clocks. An internal counter *
+ * increments on every II clock and when it reaches the value in the *
+ * Prescalar field, all IPRTE registers with their valid bits set *
+ * have their Read Response timers bumped. Whenever any of them match *
+ * the value in the RRSP_TO field, a Read Response Timeout has *
+ * occurred, and error handling occurs as described in the Error *
+ * Handling section of this document. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ixtt_u {
+ u64 ii_ixtt_regval;
+ struct {
+ u64 i_tail_to:26;
+ u64 i_rsvd_1:6;
+ u64 i_rrsp_ps:23;
+ u64 i_rrsp_to:5;
+ u64 i_rsvd:4;
+ } ii_ixtt_fld_s;
+} ii_ixtt_u_t;
+
+/************************************************************************
+ * *
+ * Writing a 1 to the fields of this register clears the appropriate *
+ * error bits in other areas of SHub. Note that when the *
+ * E_PRB_x bits are used to clear error bits in PRB registers, *
+ * SPUR_RD and SPUR_WR may persist, because they require additional *
+ * action to clear them. See the IPRBx and IXSS Register *
+ * specifications. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ieclr_u {
+ u64 ii_ieclr_regval;
+ struct {
+ u64 i_e_prb_0:1;
+ u64 i_rsvd:7;
+ u64 i_e_prb_8:1;
+ u64 i_e_prb_9:1;
+ u64 i_e_prb_a:1;
+ u64 i_e_prb_b:1;
+ u64 i_e_prb_c:1;
+ u64 i_e_prb_d:1;
+ u64 i_e_prb_e:1;
+ u64 i_e_prb_f:1;
+ u64 i_e_crazy:1;
+ u64 i_e_bte_0:1;
+ u64 i_e_bte_1:1;
+ u64 i_reserved_1:10;
+ u64 i_spur_rd_hdr:1;
+ u64 i_cam_intr_to:1;
+ u64 i_cam_overflow:1;
+ u64 i_cam_read_miss:1;
+ u64 i_ioq_rep_underflow:1;
+ u64 i_ioq_req_underflow:1;
+ u64 i_ioq_rep_overflow:1;
+ u64 i_ioq_req_overflow:1;
+ u64 i_iiq_rep_overflow:1;
+ u64 i_iiq_req_overflow:1;
+ u64 i_ii_xn_rep_cred_overflow:1;
+ u64 i_ii_xn_req_cred_overflow:1;
+ u64 i_ii_xn_invalid_cmd:1;
+ u64 i_xn_ii_invalid_cmd:1;
+ u64 i_reserved_2:21;
+ } ii_ieclr_fld_s;
+} ii_ieclr_u_t;
+
+/************************************************************************
+ * *
+ * This register controls both BTEs. SOFT_RESET is intended for *
+ * recovery after an error. COUNT controls the total number of CRBs *
+ * that both BTEs (combined) can use, which affects total BTE *
+ * bandwidth. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ibcr_u {
+ u64 ii_ibcr_regval;
+ struct {
+ u64 i_count:4;
+ u64 i_rsvd_1:4;
+ u64 i_soft_reset:1;
+ u64 i_rsvd:55;
+ } ii_ibcr_fld_s;
+} ii_ibcr_u_t;
+
+/************************************************************************
+ * *
+ * This register contains the header of a spurious read response *
+ * received from Crosstalk. A spurious read response is defined as a *
+ * read response received by II from a widget for which (1) the SIDN *
+ * has a value between 1 and 7, inclusive (II never sends requests to *
+ * these widgets (2) there is no valid IPRTE register which *
+ * corresponds to the TNUM, or (3) the widget indicated in SIDN is *
+ * not the same as the widget recorded in the IPRTE register *
+ * referenced by the TNUM. If this condition is true, and if the *
+ * IXSS[VALID] bit is clear, then the header of the spurious read *
+ * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The *
+ * errant header is thereby captured, and no further spurious read *
+ * respones are captured until IXSS[VALID] is cleared by setting the *
+ * appropriate bit in IECLR. Every time a spurious read response is *
+ * detected, the SPUR_RD bit of the PRB corresponding to the incoming *
+ * message's SIDN field is set. This always happens, regarless of *
+ * whether a header is captured. The programmer should check *
+ * IXSM[SIDN] to determine which widget sent the spurious response, *
+ * because there may be more than one SPUR_RD bit set in the PRB *
+ * registers. The widget indicated by IXSM[SIDN] was the first *
+ * spurious read response to be received since the last time *
+ * IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB *
+ * will be set. Any SPUR_RD bits in any other PRB registers indicate *
+ * spurious messages from other widets which were detected after the *
+ * header was captured.. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ixsm_u {
+ u64 ii_ixsm_regval;
+ struct {
+ u64 i_byte_en:32;
+ u64 i_reserved:1;
+ u64 i_tag:3;
+ u64 i_alt_pactyp:4;
+ u64 i_bo:1;
+ u64 i_error:1;
+ u64 i_vbpm:1;
+ u64 i_gbr:1;
+ u64 i_ds:2;
+ u64 i_ct:1;
+ u64 i_tnum:5;
+ u64 i_pactyp:4;
+ u64 i_sidn:4;
+ u64 i_didn:4;
+ } ii_ixsm_fld_s;
+} ii_ixsm_u_t;
+
+/************************************************************************
+ * *
+ * This register contains the sideband bits of a spurious read *
+ * response received from Crosstalk. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ixss_u {
+ u64 ii_ixss_regval;
+ struct {
+ u64 i_sideband:8;
+ u64 i_rsvd:55;
+ u64 i_valid:1;
+ } ii_ixss_fld_s;
+} ii_ixss_u_t;
+
+/************************************************************************
+ * *
+ * This register enables software to access the II LLP's test port. *
+ * Refer to the LLP 2.5 documentation for an explanation of the test *
+ * port. Software can write to this register to program the values *
+ * for the control fields (TestErrCapture, TestClear, TestFlit, *
+ * TestMask and TestSeed). Similarly, software can read from this *
+ * register to obtain the values of the test port's status outputs *
+ * (TestCBerr, TestValid and TestData). *
+ * *
+ ************************************************************************/
+
+typedef union ii_ilct_u {
+ u64 ii_ilct_regval;
+ struct {
+ u64 i_test_seed:20;
+ u64 i_test_mask:8;
+ u64 i_test_data:20;
+ u64 i_test_valid:1;
+ u64 i_test_cberr:1;
+ u64 i_test_flit:3;
+ u64 i_test_clear:1;
+ u64 i_test_err_capture:1;
+ u64 i_rsvd:9;
+ } ii_ilct_fld_s;
+} ii_ilct_u_t;
+
+/************************************************************************
+ * *
+ * If the II detects an illegal incoming Duplonet packet (request or *
+ * reply) when VALID==0 in the IIEPH1 register, then it saves the *
+ * contents of the packet's header flit in the IIEPH1 and IIEPH2 *
+ * registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit, *
+ * and assigns a value to the ERR_TYPE field which indicates the *
+ * specific nature of the error. The II recognizes four different *
+ * types of errors: short request packets (ERR_TYPE==2), short reply *
+ * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long *
+ * reply packets (ERR_TYPE==5). The encodings for these types of *
+ * errors were chosen to be consistent with the same types of errors *
+ * indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in *
+ * the LB unit). If the II detects an illegal incoming Duplonet *
+ * packet when VALID==1 in the IIEPH1 register, then it merely sets *
+ * the OVERRUN bit to indicate that a subsequent error has happened, *
+ * and does nothing further. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iieph1_u {
+ u64 ii_iieph1_regval;
+ struct {
+ u64 i_command:7;
+ u64 i_rsvd_5:1;
+ u64 i_suppl:14;
+ u64 i_rsvd_4:1;
+ u64 i_source:14;
+ u64 i_rsvd_3:1;
+ u64 i_err_type:4;
+ u64 i_rsvd_2:4;
+ u64 i_overrun:1;
+ u64 i_rsvd_1:3;
+ u64 i_valid:1;
+ u64 i_rsvd:13;
+ } ii_iieph1_fld_s;
+} ii_iieph1_u_t;
+
+/************************************************************************
+ * *
+ * This register holds the Address field from the header flit of an *
+ * incoming erroneous Duplonet packet, along with the tail bit which *
+ * accompanied this header flit. This register is essentially an *
+ * extension of IIEPH1. Two registers were necessary because the 64 *
+ * bits available in only a single register were insufficient to *
+ * capture the entire header flit of an erroneous packet. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iieph2_u {
+ u64 ii_iieph2_regval;
+ struct {
+ u64 i_rsvd_0:3;
+ u64 i_address:47;
+ u64 i_rsvd_1:10;
+ u64 i_tail:1;
+ u64 i_rsvd:3;
+ } ii_iieph2_fld_s;
+} ii_iieph2_u_t;
+
+/******************************/
+
+/************************************************************************
+ * *
+ * This register's value is a bit vector that guards access from SXBs *
+ * to local registers within the II as well as to external Crosstalk *
+ * widgets *
+ * *
+ ************************************************************************/
+
+typedef union ii_islapr_u {
+ u64 ii_islapr_regval;
+ struct {
+ u64 i_region:64;
+ } ii_islapr_fld_s;
+} ii_islapr_u_t;
+
+/************************************************************************
+ * *
+ * A write to this register of the 56-bit value "Pup+Bun" will cause *
+ * the bit in the ISLAPR register corresponding to the region of the *
+ * requestor to be set (access allowed). (
+ * *
+ ************************************************************************/
+
+typedef union ii_islapo_u {
+ u64 ii_islapo_regval;
+ struct {
+ u64 i_io_sbx_ovrride:56;
+ u64 i_rsvd:8;
+ } ii_islapo_fld_s;
+} ii_islapo_u_t;
+
+/************************************************************************
+ * *
+ * Determines how long the wrapper will wait aftr an interrupt is *
+ * initially issued from the II before it times out the outstanding *
+ * interrupt and drops it from the interrupt queue. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iwi_u {
+ u64 ii_iwi_regval;
+ struct {
+ u64 i_prescale:24;
+ u64 i_rsvd:8;
+ u64 i_timeout:8;
+ u64 i_rsvd1:8;
+ u64 i_intrpt_retry_period:8;
+ u64 i_rsvd2:8;
+ } ii_iwi_fld_s;
+} ii_iwi_u_t;
+
+/************************************************************************
+ * *
+ * Log errors which have occurred in the II wrapper. The errors are *
+ * cleared by writing to the IECLR register. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iwel_u {
+ u64 ii_iwel_regval;
+ struct {
+ u64 i_intr_timed_out:1;
+ u64 i_rsvd:7;
+ u64 i_cam_overflow:1;
+ u64 i_cam_read_miss:1;
+ u64 i_rsvd1:2;
+ u64 i_ioq_rep_underflow:1;
+ u64 i_ioq_req_underflow:1;
+ u64 i_ioq_rep_overflow:1;
+ u64 i_ioq_req_overflow:1;
+ u64 i_iiq_rep_overflow:1;
+ u64 i_iiq_req_overflow:1;
+ u64 i_rsvd2:6;
+ u64 i_ii_xn_rep_cred_over_under:1;
+ u64 i_ii_xn_req_cred_over_under:1;
+ u64 i_rsvd3:6;
+ u64 i_ii_xn_invalid_cmd:1;
+ u64 i_xn_ii_invalid_cmd:1;
+ u64 i_rsvd4:30;
+ } ii_iwel_fld_s;
+} ii_iwel_u_t;
+
+/************************************************************************
+ * *
+ * Controls the II wrapper. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iwc_u {
+ u64 ii_iwc_regval;
+ struct {
+ u64 i_dma_byte_swap:1;
+ u64 i_rsvd:3;
+ u64 i_cam_read_lines_reset:1;
+ u64 i_rsvd1:3;
+ u64 i_ii_xn_cred_over_under_log:1;
+ u64 i_rsvd2:19;
+ u64 i_xn_rep_iq_depth:5;
+ u64 i_rsvd3:3;
+ u64 i_xn_req_iq_depth:5;
+ u64 i_rsvd4:3;
+ u64 i_iiq_depth:6;
+ u64 i_rsvd5:12;
+ u64 i_force_rep_cred:1;
+ u64 i_force_req_cred:1;
+ } ii_iwc_fld_s;
+} ii_iwc_u_t;
+
+/************************************************************************
+ * *
+ * Status in the II wrapper. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iws_u {
+ u64 ii_iws_regval;
+ struct {
+ u64 i_xn_rep_iq_credits:5;
+ u64 i_rsvd:3;
+ u64 i_xn_req_iq_credits:5;
+ u64 i_rsvd1:51;
+ } ii_iws_fld_s;
+} ii_iws_u_t;
+
+/************************************************************************
+ * *
+ * Masks errors in the IWEL register. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iweim_u {
+ u64 ii_iweim_regval;
+ struct {
+ u64 i_intr_timed_out:1;
+ u64 i_rsvd:7;
+ u64 i_cam_overflow:1;
+ u64 i_cam_read_miss:1;
+ u64 i_rsvd1:2;
+ u64 i_ioq_rep_underflow:1;
+ u64 i_ioq_req_underflow:1;
+ u64 i_ioq_rep_overflow:1;
+ u64 i_ioq_req_overflow:1;
+ u64 i_iiq_rep_overflow:1;
+ u64 i_iiq_req_overflow:1;
+ u64 i_rsvd2:6;
+ u64 i_ii_xn_rep_cred_overflow:1;
+ u64 i_ii_xn_req_cred_overflow:1;
+ u64 i_rsvd3:6;
+ u64 i_ii_xn_invalid_cmd:1;
+ u64 i_xn_ii_invalid_cmd:1;
+ u64 i_rsvd4:30;
+ } ii_iweim_fld_s;
+} ii_iweim_u_t;
+
+/************************************************************************
+ * *
+ * A write to this register causes a particular field in the *
+ * corresponding widget's PRB entry to be adjusted up or down by 1. *
+ * This counter should be used when recovering from error and reset *
+ * conditions. Note that software would be capable of causing *
+ * inadvertent overflow or underflow of these counters. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ipca_u {
+ u64 ii_ipca_regval;
+ struct {
+ u64 i_wid:4;
+ u64 i_adjust:1;
+ u64 i_rsvd_1:3;
+ u64 i_field:2;
+ u64 i_rsvd:54;
+ } ii_ipca_fld_s;
+} ii_ipca_u_t;
+
+/************************************************************************
+ * *
+ * There are 8 instances of this register. This register contains *
+ * the information that the II has to remember once it has launched a *
+ * PIO Read operation. The contents are used to form the correct *
+ * Router Network packet and direct the Crosstalk reply to the *
+ * appropriate processor. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprte0a_u {
+ u64 ii_iprte0a_regval;
+ struct {
+ u64 i_rsvd_1:54;
+ u64 i_widget:4;
+ u64 i_to_cnt:5;
+ u64 i_vld:1;
+ } ii_iprte0a_fld_s;
+} ii_iprte0a_u_t;
+
+/************************************************************************
+ * *
+ * There are 8 instances of this register. This register contains *
+ * the information that the II has to remember once it has launched a *
+ * PIO Read operation. The contents are used to form the correct *
+ * Router Network packet and direct the Crosstalk reply to the *
+ * appropriate processor. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprte1a_u {
+ u64 ii_iprte1a_regval;
+ struct {
+ u64 i_rsvd_1:54;
+ u64 i_widget:4;
+ u64 i_to_cnt:5;
+ u64 i_vld:1;
+ } ii_iprte1a_fld_s;
+} ii_iprte1a_u_t;
+
+/************************************************************************
+ * *
+ * There are 8 instances of this register. This register contains *
+ * the information that the II has to remember once it has launched a *
+ * PIO Read operation. The contents are used to form the correct *
+ * Router Network packet and direct the Crosstalk reply to the *
+ * appropriate processor. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprte2a_u {
+ u64 ii_iprte2a_regval;
+ struct {
+ u64 i_rsvd_1:54;
+ u64 i_widget:4;
+ u64 i_to_cnt:5;
+ u64 i_vld:1;
+ } ii_iprte2a_fld_s;
+} ii_iprte2a_u_t;
+
+/************************************************************************
+ * *
+ * There are 8 instances of this register. This register contains *
+ * the information that the II has to remember once it has launched a *
+ * PIO Read operation. The contents are used to form the correct *
+ * Router Network packet and direct the Crosstalk reply to the *
+ * appropriate processor. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprte3a_u {
+ u64 ii_iprte3a_regval;
+ struct {
+ u64 i_rsvd_1:54;
+ u64 i_widget:4;
+ u64 i_to_cnt:5;
+ u64 i_vld:1;
+ } ii_iprte3a_fld_s;
+} ii_iprte3a_u_t;
+
+/************************************************************************
+ * *
+ * There are 8 instances of this register. This register contains *
+ * the information that the II has to remember once it has launched a *
+ * PIO Read operation. The contents are used to form the correct *
+ * Router Network packet and direct the Crosstalk reply to the *
+ * appropriate processor. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprte4a_u {
+ u64 ii_iprte4a_regval;
+ struct {
+ u64 i_rsvd_1:54;
+ u64 i_widget:4;
+ u64 i_to_cnt:5;
+ u64 i_vld:1;
+ } ii_iprte4a_fld_s;
+} ii_iprte4a_u_t;
+
+/************************************************************************
+ * *
+ * There are 8 instances of this register. This register contains *
+ * the information that the II has to remember once it has launched a *
+ * PIO Read operation. The contents are used to form the correct *
+ * Router Network packet and direct the Crosstalk reply to the *
+ * appropriate processor. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprte5a_u {
+ u64 ii_iprte5a_regval;
+ struct {
+ u64 i_rsvd_1:54;
+ u64 i_widget:4;
+ u64 i_to_cnt:5;
+ u64 i_vld:1;
+ } ii_iprte5a_fld_s;
+} ii_iprte5a_u_t;
+
+/************************************************************************
+ * *
+ * There are 8 instances of this register. This register contains *
+ * the information that the II has to remember once it has launched a *
+ * PIO Read operation. The contents are used to form the correct *
+ * Router Network packet and direct the Crosstalk reply to the *
+ * appropriate processor. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprte6a_u {
+ u64 ii_iprte6a_regval;
+ struct {
+ u64 i_rsvd_1:54;
+ u64 i_widget:4;
+ u64 i_to_cnt:5;
+ u64 i_vld:1;
+ } ii_iprte6a_fld_s;
+} ii_iprte6a_u_t;
+
+/************************************************************************
+ * *
+ * There are 8 instances of this register. This register contains *
+ * the information that the II has to remember once it has launched a *
+ * PIO Read operation. The contents are used to form the correct *
+ * Router Network packet and direct the Crosstalk reply to the *
+ * appropriate processor. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprte7a_u {
+ u64 ii_iprte7a_regval;
+ struct {
+ u64 i_rsvd_1:54;
+ u64 i_widget:4;
+ u64 i_to_cnt:5;
+ u64 i_vld:1;
+ } ii_iprtea7_fld_s;
+} ii_iprte7a_u_t;
+
+/************************************************************************
+ * *
+ * There are 8 instances of this register. This register contains *
+ * the information that the II has to remember once it has launched a *
+ * PIO Read operation. The contents are used to form the correct *
+ * Router Network packet and direct the Crosstalk reply to the *
+ * appropriate processor. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprte0b_u {
+ u64 ii_iprte0b_regval;
+ struct {
+ u64 i_rsvd_1:3;
+ u64 i_address:47;
+ u64 i_init:3;
+ u64 i_source:11;
+ } ii_iprte0b_fld_s;
+} ii_iprte0b_u_t;
+
+/************************************************************************
+ * *
+ * There are 8 instances of this register. This register contains *
+ * the information that the II has to remember once it has launched a *
+ * PIO Read operation. The contents are used to form the correct *
+ * Router Network packet and direct the Crosstalk reply to the *
+ * appropriate processor. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprte1b_u {
+ u64 ii_iprte1b_regval;
+ struct {
+ u64 i_rsvd_1:3;
+ u64 i_address:47;
+ u64 i_init:3;
+ u64 i_source:11;
+ } ii_iprte1b_fld_s;
+} ii_iprte1b_u_t;
+
+/************************************************************************
+ * *
+ * There are 8 instances of this register. This register contains *
+ * the information that the II has to remember once it has launched a *
+ * PIO Read operation. The contents are used to form the correct *
+ * Router Network packet and direct the Crosstalk reply to the *
+ * appropriate processor. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprte2b_u {
+ u64 ii_iprte2b_regval;
+ struct {
+ u64 i_rsvd_1:3;
+ u64 i_address:47;
+ u64 i_init:3;
+ u64 i_source:11;
+ } ii_iprte2b_fld_s;
+} ii_iprte2b_u_t;
+
+/************************************************************************
+ * *
+ * There are 8 instances of this register. This register contains *
+ * the information that the II has to remember once it has launched a *
+ * PIO Read operation. The contents are used to form the correct *
+ * Router Network packet and direct the Crosstalk reply to the *
+ * appropriate processor. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprte3b_u {
+ u64 ii_iprte3b_regval;
+ struct {
+ u64 i_rsvd_1:3;
+ u64 i_address:47;
+ u64 i_init:3;
+ u64 i_source:11;
+ } ii_iprte3b_fld_s;
+} ii_iprte3b_u_t;
+
+/************************************************************************
+ * *
+ * There are 8 instances of this register. This register contains *
+ * the information that the II has to remember once it has launched a *
+ * PIO Read operation. The contents are used to form the correct *
+ * Router Network packet and direct the Crosstalk reply to the *
+ * appropriate processor. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprte4b_u {
+ u64 ii_iprte4b_regval;
+ struct {
+ u64 i_rsvd_1:3;
+ u64 i_address:47;
+ u64 i_init:3;
+ u64 i_source:11;
+ } ii_iprte4b_fld_s;
+} ii_iprte4b_u_t;
+
+/************************************************************************
+ * *
+ * There are 8 instances of this register. This register contains *
+ * the information that the II has to remember once it has launched a *
+ * PIO Read operation. The contents are used to form the correct *
+ * Router Network packet and direct the Crosstalk reply to the *
+ * appropriate processor. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprte5b_u {
+ u64 ii_iprte5b_regval;
+ struct {
+ u64 i_rsvd_1:3;
+ u64 i_address:47;
+ u64 i_init:3;
+ u64 i_source:11;
+ } ii_iprte5b_fld_s;
+} ii_iprte5b_u_t;
+
+/************************************************************************
+ * *
+ * There are 8 instances of this register. This register contains *
+ * the information that the II has to remember once it has launched a *
+ * PIO Read operation. The contents are used to form the correct *
+ * Router Network packet and direct the Crosstalk reply to the *
+ * appropriate processor. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprte6b_u {
+ u64 ii_iprte6b_regval;
+ struct {
+ u64 i_rsvd_1:3;
+ u64 i_address:47;
+ u64 i_init:3;
+ u64 i_source:11;
+
+ } ii_iprte6b_fld_s;
+} ii_iprte6b_u_t;
+
+/************************************************************************
+ * *
+ * There are 8 instances of this register. This register contains *
+ * the information that the II has to remember once it has launched a *
+ * PIO Read operation. The contents are used to form the correct *
+ * Router Network packet and direct the Crosstalk reply to the *
+ * appropriate processor. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iprte7b_u {
+ u64 ii_iprte7b_regval;
+ struct {
+ u64 i_rsvd_1:3;
+ u64 i_address:47;
+ u64 i_init:3;
+ u64 i_source:11;
+ } ii_iprte7b_fld_s;
+} ii_iprte7b_u_t;
+
+/************************************************************************
+ * *
+ * Description: SHub II contains a feature which did not exist in *
+ * the Hub which automatically cleans up after a Read Response *
+ * timeout, including deallocation of the IPRTE and recovery of IBuf *
+ * space. The inclusion of this register in SHub is for backward *
+ * compatibility *
+ * A write to this register causes an entry from the table of *
+ * outstanding PIO Read Requests to be freed and returned to the *
+ * stack of free entries. This register is used in handling the *
+ * timeout errors that result in a PIO Reply never returning from *
+ * Crosstalk. *
+ * Note that this register does not affect the contents of the IPRTE *
+ * registers. The Valid bits in those registers have to be *
+ * specifically turned off by software. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ipdr_u {
+ u64 ii_ipdr_regval;
+ struct {
+ u64 i_te:3;
+ u64 i_rsvd_1:1;
+ u64 i_pnd:1;
+ u64 i_init_rpcnt:1;
+ u64 i_rsvd:58;
+ } ii_ipdr_fld_s;
+} ii_ipdr_u_t;
+
+/************************************************************************
+ * *
+ * A write to this register causes a CRB entry to be returned to the *
+ * queue of free CRBs. The entry should have previously been cleared *
+ * (mark bit) via backdoor access to the pertinent CRB entry. This *
+ * register is used in the last step of handling the errors that are *
+ * captured and marked in CRB entries. Briefly: 1) first error for *
+ * DMA write from a particular device, and first error for a *
+ * particular BTE stream, lead to a marked CRB entry, and processor *
+ * interrupt, 2) software reads the error information captured in the *
+ * CRB entry, and presumably takes some corrective action, 3) *
+ * software clears the mark bit, and finally 4) software writes to *
+ * the ICDR register to return the CRB entry to the list of free CRB *
+ * entries. *
+ * *
+ ************************************************************************/
+
+typedef union ii_icdr_u {
+ u64 ii_icdr_regval;
+ struct {
+ u64 i_crb_num:4;
+ u64 i_pnd:1;
+ u64 i_rsvd:59;
+ } ii_icdr_fld_s;
+} ii_icdr_u_t;
+
+/************************************************************************
+ * *
+ * This register provides debug access to two FIFOs inside of II. *
+ * Both IOQ_MAX* fields of this register contain the instantaneous *
+ * depth (in units of the number of available entries) of the *
+ * associated IOQ FIFO. A read of this register will return the *
+ * number of free entries on each FIFO at the time of the read. So *
+ * when a FIFO is idle, the associated field contains the maximum *
+ * depth of the FIFO. This register is writable for debug reasons *
+ * and is intended to be written with the maximum desired FIFO depth *
+ * while the FIFO is idle. Software must assure that II is idle when *
+ * this register is written. If there are any active entries in any *
+ * of these FIFOs when this register is written, the results are *
+ * undefined. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ifdr_u {
+ u64 ii_ifdr_regval;
+ struct {
+ u64 i_ioq_max_rq:7;
+ u64 i_set_ioq_rq:1;
+ u64 i_ioq_max_rp:7;
+ u64 i_set_ioq_rp:1;
+ u64 i_rsvd:48;
+ } ii_ifdr_fld_s;
+} ii_ifdr_u_t;
+
+/************************************************************************
+ * *
+ * This register allows the II to become sluggish in removing *
+ * messages from its inbound queue (IIQ). This will cause messages to *
+ * back up in either virtual channel. Disabling the "molasses" mode *
+ * subsequently allows the II to be tested under stress. In the *
+ * sluggish ("Molasses") mode, the localized effects of congestion *
+ * can be observed. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iiap_u {
+ u64 ii_iiap_regval;
+ struct {
+ u64 i_rq_mls:6;
+ u64 i_rsvd_1:2;
+ u64 i_rp_mls:6;
+ u64 i_rsvd:50;
+ } ii_iiap_fld_s;
+} ii_iiap_u_t;
+
+/************************************************************************
+ * *
+ * This register allows several parameters of CRB operation to be *
+ * set. Note that writing to this register can have catastrophic side *
+ * effects, if the CRB is not quiescent, i.e. if the CRB is *
+ * processing protocol messages when the write occurs. *
+ * *
+ ************************************************************************/
+
+typedef union ii_icmr_u {
+ u64 ii_icmr_regval;
+ struct {
+ u64 i_sp_msg:1;
+ u64 i_rd_hdr:1;
+ u64 i_rsvd_4:2;
+ u64 i_c_cnt:4;
+ u64 i_rsvd_3:4;
+ u64 i_clr_rqpd:1;
+ u64 i_clr_rppd:1;
+ u64 i_rsvd_2:2;
+ u64 i_fc_cnt:4;
+ u64 i_crb_vld:15;
+ u64 i_crb_mark:15;
+ u64 i_rsvd_1:2;
+ u64 i_precise:1;
+ u64 i_rsvd:11;
+ } ii_icmr_fld_s;
+} ii_icmr_u_t;
+
+/************************************************************************
+ * *
+ * This register allows control of the table portion of the CRB *
+ * logic via software. Control operations from this register have *
+ * priority over all incoming Crosstalk or BTE requests. *
+ * *
+ ************************************************************************/
+
+typedef union ii_iccr_u {
+ u64 ii_iccr_regval;
+ struct {
+ u64 i_crb_num:4;
+ u64 i_rsvd_1:4;
+ u64 i_cmd:8;
+ u64 i_pending:1;
+ u64 i_rsvd:47;
+ } ii_iccr_fld_s;
+} ii_iccr_u_t;
+
+/************************************************************************
+ * *
+ * This register allows the maximum timeout value to be programmed. *
+ * *
+ ************************************************************************/
+
+typedef union ii_icto_u {
+ u64 ii_icto_regval;
+ struct {
+ u64 i_timeout:8;
+ u64 i_rsvd:56;
+ } ii_icto_fld_s;
+} ii_icto_u_t;
+
+/************************************************************************
+ * *
+ * This register allows the timeout prescalar to be programmed. An *
+ * internal counter is associated with this register. When the *
+ * internal counter reaches the value of the PRESCALE field, the *
+ * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT] *
+ * field). The internal counter resets to zero, and then continues *
+ * counting. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ictp_u {
+ u64 ii_ictp_regval;
+ struct {
+ u64 i_prescale:24;
+ u64 i_rsvd:40;
+ } ii_ictp_fld_s;
+} ii_ictp_u_t;
+
+/************************************************************************
+ * *
+ * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
+ * used for Crosstalk operations (both cacheline and partial *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five *
+ * registers (_A to _E) are required to read and write each entry. *
+ * The CRB Entry registers can be conceptualized as rows and columns *
+ * (illustrated in the table above). Each row contains the 4 *
+ * registers required for a single CRB Entry. The first doubleword *
+ * (column) for each entry is labeled A, and the second doubleword *
+ * (higher address) is labeled B, the third doubleword is labeled C, *
+ * the fourth doubleword is labeled D and the fifth doubleword is *
+ * labeled E. All CRB entries have their addresses on a quarter *
+ * cacheline aligned boundary. *
+ * Upon reset, only the following fields are initialized: valid *
+ * (VLD), priority count, timeout, timeout valid, and context valid. *
+ * All other bits should be cleared by software before use (after *
+ * recovering any potential error state from before the reset). *
+ * The following four tables summarize the format for the four *
+ * registers that are used for each ICRB# Entry. *
+ * *
+ ************************************************************************/
+
+typedef union ii_icrb0_a_u {
+ u64 ii_icrb0_a_regval;
+ struct {
+ u64 ia_iow:1;
+ u64 ia_vld:1;
+ u64 ia_addr:47;
+ u64 ia_tnum:5;
+ u64 ia_sidn:4;
+ u64 ia_rsvd:6;
+ } ii_icrb0_a_fld_s;
+} ii_icrb0_a_u_t;
+
+/************************************************************************
+ * *
+ * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
+ * used for Crosstalk operations (both cacheline and partial *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five *
+ * registers (_A to _E) are required to read and write each entry. *
+ * *
+ ************************************************************************/
+
+typedef union ii_icrb0_b_u {
+ u64 ii_icrb0_b_regval;
+ struct {
+ u64 ib_xt_err:1;
+ u64 ib_mark:1;
+ u64 ib_ln_uce:1;
+ u64 ib_errcode:3;
+ u64 ib_error:1;
+ u64 ib_stall__bte_1:1;
+ u64 ib_stall__bte_0:1;
+ u64 ib_stall__intr:1;
+ u64 ib_stall_ib:1;
+ u64 ib_intvn:1;
+ u64 ib_wb:1;
+ u64 ib_hold:1;
+ u64 ib_ack:1;
+ u64 ib_resp:1;
+ u64 ib_ack_cnt:11;
+ u64 ib_rsvd:7;
+ u64 ib_exc:5;
+ u64 ib_init:3;
+ u64 ib_imsg:8;
+ u64 ib_imsgtype:2;
+ u64 ib_use_old:1;
+ u64 ib_rsvd_1:11;
+ } ii_icrb0_b_fld_s;
+} ii_icrb0_b_u_t;
+
+/************************************************************************
+ * *
+ * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
+ * used for Crosstalk operations (both cacheline and partial *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five *
+ * registers (_A to _E) are required to read and write each entry. *
+ * *
+ ************************************************************************/
+
+typedef union ii_icrb0_c_u {
+ u64 ii_icrb0_c_regval;
+ struct {
+ u64 ic_source:15;
+ u64 ic_size:2;
+ u64 ic_ct:1;
+ u64 ic_bte_num:1;
+ u64 ic_gbr:1;
+ u64 ic_resprqd:1;
+ u64 ic_bo:1;
+ u64 ic_suppl:15;
+ u64 ic_rsvd:27;
+ } ii_icrb0_c_fld_s;
+} ii_icrb0_c_u_t;
+
+/************************************************************************
+ * *
+ * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
+ * used for Crosstalk operations (both cacheline and partial *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five *
+ * registers (_A to _E) are required to read and write each entry. *
+ * *
+ ************************************************************************/
+
+typedef union ii_icrb0_d_u {
+ u64 ii_icrb0_d_regval;
+ struct {
+ u64 id_pa_be:43;
+ u64 id_bte_op:1;
+ u64 id_pr_psc:4;
+ u64 id_pr_cnt:4;
+ u64 id_sleep:1;
+ u64 id_rsvd:11;
+ } ii_icrb0_d_fld_s;
+} ii_icrb0_d_u_t;
+
+/************************************************************************
+ * *
+ * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
+ * used for Crosstalk operations (both cacheline and partial *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five *
+ * registers (_A to _E) are required to read and write each entry. *
+ * *
+ ************************************************************************/
+
+typedef union ii_icrb0_e_u {
+ u64 ii_icrb0_e_regval;
+ struct {
+ u64 ie_timeout:8;
+ u64 ie_context:15;
+ u64 ie_rsvd:1;
+ u64 ie_tvld:1;
+ u64 ie_cvld:1;
+ u64 ie_rsvd_0:38;
+ } ii_icrb0_e_fld_s;
+} ii_icrb0_e_u_t;
+
+/************************************************************************
+ * *
+ * This register contains the lower 64 bits of the header of the *
+ * spurious message captured by II. Valid when the SP_MSG bit in ICMR *
+ * register is set. *
+ * *
+ ************************************************************************/
+
+typedef union ii_icsml_u {
+ u64 ii_icsml_regval;
+ struct {
+ u64 i_tt_addr:47;
+ u64 i_newsuppl_ex:14;
+ u64 i_reserved:2;
+ u64 i_overflow:1;
+ } ii_icsml_fld_s;
+} ii_icsml_u_t;
+
+/************************************************************************
+ * *
+ * This register contains the middle 64 bits of the header of the *
+ * spurious message captured by II. Valid when the SP_MSG bit in ICMR *
+ * register is set. *
+ * *
+ ************************************************************************/
+
+typedef union ii_icsmm_u {
+ u64 ii_icsmm_regval;
+ struct {
+ u64 i_tt_ack_cnt:11;
+ u64 i_reserved:53;
+ } ii_icsmm_fld_s;
+} ii_icsmm_u_t;
+
+/************************************************************************
+ * *
+ * This register contains the microscopic state, all the inputs to *
+ * the protocol table, captured with the spurious message. Valid when *
+ * the SP_MSG bit in the ICMR register is set. *
+ * *
+ ************************************************************************/
+
+typedef union ii_icsmh_u {
+ u64 ii_icsmh_regval;
+ struct {
+ u64 i_tt_vld:1;
+ u64 i_xerr:1;
+ u64 i_ft_cwact_o:1;
+ u64 i_ft_wact_o:1;
+ u64 i_ft_active_o:1;
+ u64 i_sync:1;
+ u64 i_mnusg:1;
+ u64 i_mnusz:1;
+ u64 i_plusz:1;
+ u64 i_plusg:1;
+ u64 i_tt_exc:5;
+ u64 i_tt_wb:1;
+ u64 i_tt_hold:1;
+ u64 i_tt_ack:1;
+ u64 i_tt_resp:1;
+ u64 i_tt_intvn:1;
+ u64 i_g_stall_bte1:1;
+ u64 i_g_stall_bte0:1;
+ u64 i_g_stall_il:1;
+ u64 i_g_stall_ib:1;
+ u64 i_tt_imsg:8;
+ u64 i_tt_imsgtype:2;
+ u64 i_tt_use_old:1;
+ u64 i_tt_respreqd:1;
+ u64 i_tt_bte_num:1;
+ u64 i_cbn:1;
+ u64 i_match:1;
+ u64 i_rpcnt_lt_34:1;
+ u64 i_rpcnt_ge_34:1;
+ u64 i_rpcnt_lt_18:1;
+ u64 i_rpcnt_ge_18:1;
+ u64 i_rpcnt_lt_2:1;
+ u64 i_rpcnt_ge_2:1;
+ u64 i_rqcnt_lt_18:1;
+ u64 i_rqcnt_ge_18:1;
+ u64 i_rqcnt_lt_2:1;
+ u64 i_rqcnt_ge_2:1;
+ u64 i_tt_device:7;
+ u64 i_tt_init:3;
+ u64 i_reserved:5;
+ } ii_icsmh_fld_s;
+} ii_icsmh_u_t;
+
+/************************************************************************
+ * *
+ * The Shub DEBUG unit provides a 3-bit selection signal to the *
+ * II core and a 3-bit selection signal to the fsbclk domain in the II *
+ * wrapper. *
+ * *
+ ************************************************************************/
+
+typedef union ii_idbss_u {
+ u64 ii_idbss_regval;
+ struct {
+ u64 i_iioclk_core_submenu:3;
+ u64 i_rsvd:5;
+ u64 i_fsbclk_wrapper_submenu:3;
+ u64 i_rsvd_1:5;
+ u64 i_iioclk_menu:5;
+ u64 i_rsvd_2:43;
+ } ii_idbss_fld_s;
+} ii_idbss_u_t;
+
+/************************************************************************
+ * *
+ * Description: This register is used to set up the length for a *
+ * transfer and then to monitor the progress of that transfer. This *
+ * register needs to be initialized before a transfer is started. A *
+ * legitimate write to this register will set the Busy bit, clear the *
+ * Error bit, and initialize the length to the value desired. *
+ * While the transfer is in progress, hardware will decrement the *
+ * length field with each successful block that is copied. Once the *
+ * transfer completes, hardware will clear the Busy bit. The length *
+ * field will also contain the number of cache lines left to be *
+ * transferred. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ibls0_u {
+ u64 ii_ibls0_regval;
+ struct {
+ u64 i_length:16;
+ u64 i_error:1;
+ u64 i_rsvd_1:3;
+ u64 i_busy:1;
+ u64 i_rsvd:43;
+ } ii_ibls0_fld_s;
+} ii_ibls0_u_t;
+
+/************************************************************************
+ * *
+ * This register should be loaded before a transfer is started. The *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
+ * address as described in Section 1.3, Figure2 and Figure3. Since *
+ * the bottom 7 bits of the address are always taken to be zero, BTE *
+ * transfers are always cacheline-aligned. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ibsa0_u {
+ u64 ii_ibsa0_regval;
+ struct {
+ u64 i_rsvd_1:7;
+ u64 i_addr:42;
+ u64 i_rsvd:15;
+ } ii_ibsa0_fld_s;
+} ii_ibsa0_u_t;
+
+/************************************************************************
+ * *
+ * This register should be loaded before a transfer is started. The *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
+ * address as described in Section 1.3, Figure2 and Figure3. Since *
+ * the bottom 7 bits of the address are always taken to be zero, BTE *
+ * transfers are always cacheline-aligned. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ibda0_u {
+ u64 ii_ibda0_regval;
+ struct {
+ u64 i_rsvd_1:7;
+ u64 i_addr:42;
+ u64 i_rsvd:15;
+ } ii_ibda0_fld_s;
+} ii_ibda0_u_t;
+
+/************************************************************************
+ * *
+ * Writing to this register sets up the attributes of the transfer *
+ * and initiates the transfer operation. Reading this register has *
+ * the side effect of terminating any transfer in progress. Note: *
+ * stopping a transfer midstream could have an adverse impact on the *
+ * other BTE. If a BTE stream has to be stopped (due to error *
+ * handling for example), both BTE streams should be stopped and *
+ * their transfers discarded. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ibct0_u {
+ u64 ii_ibct0_regval;
+ struct {
+ u64 i_zerofill:1;
+ u64 i_rsvd_2:3;
+ u64 i_notify:1;
+ u64 i_rsvd_1:3;
+ u64 i_poison:1;
+ u64 i_rsvd:55;
+ } ii_ibct0_fld_s;
+} ii_ibct0_u_t;
+
+/************************************************************************
+ * *
+ * This register contains the address to which the WINV is sent. *
+ * This address has to be cache line aligned. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ibna0_u {
+ u64 ii_ibna0_regval;
+ struct {
+ u64 i_rsvd_1:7;
+ u64 i_addr:42;
+ u64 i_rsvd:15;
+ } ii_ibna0_fld_s;
+} ii_ibna0_u_t;
+
+/************************************************************************
+ * *
+ * This register contains the programmable level as well as the node *
+ * ID and PI unit of the processor to which the interrupt will be *
+ * sent. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ibia0_u {
+ u64 ii_ibia0_regval;
+ struct {
+ u64 i_rsvd_2:1;
+ u64 i_node_id:11;
+ u64 i_rsvd_1:4;
+ u64 i_level:7;
+ u64 i_rsvd:41;
+ } ii_ibia0_fld_s;
+} ii_ibia0_u_t;
+
+/************************************************************************
+ * *
+ * Description: This register is used to set up the length for a *
+ * transfer and then to monitor the progress of that transfer. This *
+ * register needs to be initialized before a transfer is started. A *
+ * legitimate write to this register will set the Busy bit, clear the *
+ * Error bit, and initialize the length to the value desired. *
+ * While the transfer is in progress, hardware will decrement the *
+ * length field with each successful block that is copied. Once the *
+ * transfer completes, hardware will clear the Busy bit. The length *
+ * field will also contain the number of cache lines left to be *
+ * transferred. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ibls1_u {
+ u64 ii_ibls1_regval;
+ struct {
+ u64 i_length:16;
+ u64 i_error:1;
+ u64 i_rsvd_1:3;
+ u64 i_busy:1;
+ u64 i_rsvd:43;
+ } ii_ibls1_fld_s;
+} ii_ibls1_u_t;
+
+/************************************************************************
+ * *
+ * This register should be loaded before a transfer is started. The *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
+ * address as described in Section 1.3, Figure2 and Figure3. Since *
+ * the bottom 7 bits of the address are always taken to be zero, BTE *
+ * transfers are always cacheline-aligned. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ibsa1_u {
+ u64 ii_ibsa1_regval;
+ struct {
+ u64 i_rsvd_1:7;
+ u64 i_addr:33;
+ u64 i_rsvd:24;
+ } ii_ibsa1_fld_s;
+} ii_ibsa1_u_t;
+
+/************************************************************************
+ * *
+ * This register should be loaded before a transfer is started. The *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
+ * address as described in Section 1.3, Figure2 and Figure3. Since *
+ * the bottom 7 bits of the address are always taken to be zero, BTE *
+ * transfers are always cacheline-aligned. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ibda1_u {
+ u64 ii_ibda1_regval;
+ struct {
+ u64 i_rsvd_1:7;
+ u64 i_addr:33;
+ u64 i_rsvd:24;
+ } ii_ibda1_fld_s;
+} ii_ibda1_u_t;
+
+/************************************************************************
+ * *
+ * Writing to this register sets up the attributes of the transfer *
+ * and initiates the transfer operation. Reading this register has *
+ * the side effect of terminating any transfer in progress. Note: *
+ * stopping a transfer midstream could have an adverse impact on the *
+ * other BTE. If a BTE stream has to be stopped (due to error *
+ * handling for example), both BTE streams should be stopped and *
+ * their transfers discarded. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ibct1_u {
+ u64 ii_ibct1_regval;
+ struct {
+ u64 i_zerofill:1;
+ u64 i_rsvd_2:3;
+ u64 i_notify:1;
+ u64 i_rsvd_1:3;
+ u64 i_poison:1;
+ u64 i_rsvd:55;
+ } ii_ibct1_fld_s;
+} ii_ibct1_u_t;
+
+/************************************************************************
+ * *
+ * This register contains the address to which the WINV is sent. *
+ * This address has to be cache line aligned. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ibna1_u {
+ u64 ii_ibna1_regval;
+ struct {
+ u64 i_rsvd_1:7;
+ u64 i_addr:33;
+ u64 i_rsvd:24;
+ } ii_ibna1_fld_s;
+} ii_ibna1_u_t;
+
+/************************************************************************
+ * *
+ * This register contains the programmable level as well as the node *
+ * ID and PI unit of the processor to which the interrupt will be *
+ * sent. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ibia1_u {
+ u64 ii_ibia1_regval;
+ struct {
+ u64 i_pi_id:1;
+ u64 i_node_id:8;
+ u64 i_rsvd_1:7;
+ u64 i_level:7;
+ u64 i_rsvd:41;
+ } ii_ibia1_fld_s;
+} ii_ibia1_u_t;
+
+/************************************************************************
+ * *
+ * This register defines the resources that feed information into *
+ * the two performance counters located in the IO Performance *
+ * Profiling Register. There are 17 different quantities that can be *
+ * measured. Given these 17 different options, the two performance *
+ * counters have 15 of them in common; menu selections 0 through 0xE *
+ * are identical for each performance counter. As for the other two *
+ * options, one is available from one performance counter and the *
+ * other is available from the other performance counter. Hence, the *
+ * II supports all 17*16=272 possible combinations of quantities to *
+ * measure. *
+ * *
+ ************************************************************************/
+
+typedef union ii_ipcr_u {
+ u64 ii_ipcr_regval;
+ struct {
+ u64 i_ippr0_c:4;
+ u64 i_ippr1_c:4;
+ u64 i_icct:8;
+ u64 i_rsvd:48;
+ } ii_ipcr_fld_s;
+} ii_ipcr_u_t;
+
+/************************************************************************
+ * *
+ * *
+ * *
+ ************************************************************************/
+
+typedef union ii_ippr_u {
+ u64 ii_ippr_regval;
+ struct {
+ u64 i_ippr0:32;
+ u64 i_ippr1:32;
+ } ii_ippr_fld_s;
+} ii_ippr_u_t;
+
+/************************************************************************
+ * *
+ * The following defines which were not formed into structures are *
+ * probably identical to another register, and the name of the *
+ * register is provided against each of these registers. This *
+ * information needs to be checked carefully *
+ * *
+ * IIO_ICRB1_A IIO_ICRB0_A *
+ * IIO_ICRB1_B IIO_ICRB0_B *
+ * IIO_ICRB1_C IIO_ICRB0_C *
+ * IIO_ICRB1_D IIO_ICRB0_D *
+ * IIO_ICRB1_E IIO_ICRB0_E *
+ * IIO_ICRB2_A IIO_ICRB0_A *
+ * IIO_ICRB2_B IIO_ICRB0_B *
+ * IIO_ICRB2_C IIO_ICRB0_C *
+ * IIO_ICRB2_D IIO_ICRB0_D *
+ * IIO_ICRB2_E IIO_ICRB0_E *
+ * IIO_ICRB3_A IIO_ICRB0_A *
+ * IIO_ICRB3_B IIO_ICRB0_B *
+ * IIO_ICRB3_C IIO_ICRB0_C *
+ * IIO_ICRB3_D IIO_ICRB0_D *
+ * IIO_ICRB3_E IIO_ICRB0_E *
+ * IIO_ICRB4_A IIO_ICRB0_A *
+ * IIO_ICRB4_B IIO_ICRB0_B *
+ * IIO_ICRB4_C IIO_ICRB0_C *
+ * IIO_ICRB4_D IIO_ICRB0_D *
+ * IIO_ICRB4_E IIO_ICRB0_E *
+ * IIO_ICRB5_A IIO_ICRB0_A *
+ * IIO_ICRB5_B IIO_ICRB0_B *
+ * IIO_ICRB5_C IIO_ICRB0_C *
+ * IIO_ICRB5_D IIO_ICRB0_D *
+ * IIO_ICRB5_E IIO_ICRB0_E *
+ * IIO_ICRB6_A IIO_ICRB0_A *
+ * IIO_ICRB6_B IIO_ICRB0_B *
+ * IIO_ICRB6_C IIO_ICRB0_C *
+ * IIO_ICRB6_D IIO_ICRB0_D *
+ * IIO_ICRB6_E IIO_ICRB0_E *
+ * IIO_ICRB7_A IIO_ICRB0_A *
+ * IIO_ICRB7_B IIO_ICRB0_B *
+ * IIO_ICRB7_C IIO_ICRB0_C *
+ * IIO_ICRB7_D IIO_ICRB0_D *
+ * IIO_ICRB7_E IIO_ICRB0_E *
+ * IIO_ICRB8_A IIO_ICRB0_A *
+ * IIO_ICRB8_B IIO_ICRB0_B *
+ * IIO_ICRB8_C IIO_ICRB0_C *
+ * IIO_ICRB8_D IIO_ICRB0_D *
+ * IIO_ICRB8_E IIO_ICRB0_E *
+ * IIO_ICRB9_A IIO_ICRB0_A *
+ * IIO_ICRB9_B IIO_ICRB0_B *
+ * IIO_ICRB9_C IIO_ICRB0_C *
+ * IIO_ICRB9_D IIO_ICRB0_D *
+ * IIO_ICRB9_E IIO_ICRB0_E *
+ * IIO_ICRBA_A IIO_ICRB0_A *
+ * IIO_ICRBA_B IIO_ICRB0_B *
+ * IIO_ICRBA_C IIO_ICRB0_C *
+ * IIO_ICRBA_D IIO_ICRB0_D *
+ * IIO_ICRBA_E IIO_ICRB0_E *
+ * IIO_ICRBB_A IIO_ICRB0_A *
+ * IIO_ICRBB_B IIO_ICRB0_B *
+ * IIO_ICRBB_C IIO_ICRB0_C *
+ * IIO_ICRBB_D IIO_ICRB0_D *
+ * IIO_ICRBB_E IIO_ICRB0_E *
+ * IIO_ICRBC_A IIO_ICRB0_A *
+ * IIO_ICRBC_B IIO_ICRB0_B *
+ * IIO_ICRBC_C IIO_ICRB0_C *
+ * IIO_ICRBC_D IIO_ICRB0_D *
+ * IIO_ICRBC_E IIO_ICRB0_E *
+ * IIO_ICRBD_A IIO_ICRB0_A *
+ * IIO_ICRBD_B IIO_ICRB0_B *
+ * IIO_ICRBD_C IIO_ICRB0_C *
+ * IIO_ICRBD_D IIO_ICRB0_D *
+ * IIO_ICRBD_E IIO_ICRB0_E *
+ * IIO_ICRBE_A IIO_ICRB0_A *
+ * IIO_ICRBE_B IIO_ICRB0_B *
+ * IIO_ICRBE_C IIO_ICRB0_C *
+ * IIO_ICRBE_D IIO_ICRB0_D *
+ * IIO_ICRBE_E IIO_ICRB0_E *
+ * *
+ ************************************************************************/
+
+/*
+ * Slightly friendlier names for some common registers.
+ */
+#define IIO_WIDGET IIO_WID /* Widget identification */
+#define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */
+#define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */
+#define IIO_PROTECT IIO_ILAPR /* IO interface protection */
+#define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */
+#define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */
+#define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */
+#define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */
+#define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */
+#define IIO_LLP_LOG IIO_ILLR /* LLP log */
+#define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout */
+#define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */
+#define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */
+#define IIO_IGFX_0 IIO_IGFX0
+#define IIO_IGFX_1 IIO_IGFX1
+#define IIO_IBCT_0 IIO_IBCT0
+#define IIO_IBCT_1 IIO_IBCT1
+#define IIO_IBLS_0 IIO_IBLS0
+#define IIO_IBLS_1 IIO_IBLS1
+#define IIO_IBSA_0 IIO_IBSA0
+#define IIO_IBSA_1 IIO_IBSA1
+#define IIO_IBDA_0 IIO_IBDA0
+#define IIO_IBDA_1 IIO_IBDA1
+#define IIO_IBNA_0 IIO_IBNA0
+#define IIO_IBNA_1 IIO_IBNA1
+#define IIO_IBIA_0 IIO_IBIA0
+#define IIO_IBIA_1 IIO_IBIA1
+#define IIO_IOPRB_0 IIO_IPRB0
+
+#define IIO_PRTE_A(_x) (IIO_IPRTE0_A + (8 * (_x)))
+#define IIO_PRTE_B(_x) (IIO_IPRTE0_B + (8 * (_x)))
+#define IIO_NUM_PRTES 8 /* Total number of PRB table entries */
+#define IIO_WIDPRTE_A(x) IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */
+#define IIO_WIDPRTE_B(x) IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */
+
+#define IIO_NUM_IPRBS 9
+
+#define IIO_LLP_CSR_IS_UP 0x00002000
+#define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000
+#define IIO_LLP_CSR_LLP_STAT_SHFT 12
+
+#define IIO_LLP_CB_MAX 0xffff /* in ILLR CB_CNT, Max Check Bit errors */
+#define IIO_LLP_SN_MAX 0xffff /* in ILLR SN_CNT, Max Sequence Number errors */
+
+/* key to IIO_PROTECT_OVRRD */
+#define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */
+
+/* BTE register names */
+#define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */
+#define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */
+#define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */
+#define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */
+#define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */
+#define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */
+#define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */
+#define IIO_BTE_OFF_1 (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */
+
+/* BTE register offsets from base */
+#define BTEOFF_STAT 0
+#define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
+#define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
+#define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
+#define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
+#define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
+
+/* names used in shub diags */
+#define IIO_BASE_BTE0 IIO_IBLS_0
+#define IIO_BASE_BTE1 IIO_IBLS_1
+
+/*
+ * Macro which takes the widget number, and returns the
+ * IO PRB address of that widget.
+ * value _x is expected to be a widget number in the range
+ * 0, 8 - 0xF
+ */
+#define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
+ (_x) : \
+ (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
+
+/* GFX Flow Control Node/Widget Register */
+#define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */
+#define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1)
+#define IIO_IGFX_W_NUM_SHIFT 0
+#define IIO_IGFX_PI_NUM_BITS 1 /* size of PI num field */
+#define IIO_IGFX_PI_NUM_MASK ((1<<IIO_IGFX_PI_NUM_BITS)-1)
+#define IIO_IGFX_PI_NUM_SHIFT 4
+#define IIO_IGFX_N_NUM_BITS 8 /* size of node num field */
+#define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1)
+#define IIO_IGFX_N_NUM_SHIFT 5
+#define IIO_IGFX_P_NUM_BITS 1 /* size of processor num field */
+#define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1)
+#define IIO_IGFX_P_NUM_SHIFT 16
+#define IIO_IGFX_INIT(widget, pi, node, cpu) (\
+ (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) | \
+ (((pi) & IIO_IGFX_PI_NUM_MASK)<< IIO_IGFX_PI_NUM_SHIFT)| \
+ (((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \
+ (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT))
+
+/* Scratch registers (all bits available) */
+#define IIO_SCRATCH_REG0 IIO_ISCR0
+#define IIO_SCRATCH_REG1 IIO_ISCR1
+#define IIO_SCRATCH_MASK 0xffffffffffffffffUL
+
+#define IIO_SCRATCH_BIT0_0 0x0000000000000001UL
+#define IIO_SCRATCH_BIT0_1 0x0000000000000002UL
+#define IIO_SCRATCH_BIT0_2 0x0000000000000004UL
+#define IIO_SCRATCH_BIT0_3 0x0000000000000008UL
+#define IIO_SCRATCH_BIT0_4 0x0000000000000010UL
+#define IIO_SCRATCH_BIT0_5 0x0000000000000020UL
+#define IIO_SCRATCH_BIT0_6 0x0000000000000040UL
+#define IIO_SCRATCH_BIT0_7 0x0000000000000080UL
+#define IIO_SCRATCH_BIT0_8 0x0000000000000100UL
+#define IIO_SCRATCH_BIT0_9 0x0000000000000200UL
+#define IIO_SCRATCH_BIT0_A 0x0000000000000400UL
+
+#define IIO_SCRATCH_BIT1_0 0x0000000000000001UL
+#define IIO_SCRATCH_BIT1_1 0x0000000000000002UL
+/* IO Translation Table Entries */
+#define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */
+ /* Hw manuals number them 1..7! */
+/*
+ * IIO_IMEM Register fields.
+ */
+#define IIO_IMEM_W0ESD 0x1UL /* Widget 0 shut down due to error */
+#define IIO_IMEM_B0ESD (1UL << 4) /* BTE 0 shut down due to error */
+#define IIO_IMEM_B1ESD (1UL << 8) /* BTE 1 Shut down due to error */
+
+/*
+ * As a permanent workaround for a bug in the PI side of the shub, we've
+ * redefined big window 7 as small window 0.
+ XXX does this still apply for SN1??
+ */
+#define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1)
+
+/*
+ * Use the top big window as a surrogate for the first small window
+ */
+#define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW
+
+#define ILCSR_WARM_RESET 0x100
+
+/*
+ * CRB manipulation macros
+ * The CRB macros are slightly complicated, since there are up to
+ * four registers associated with each CRB entry.
+ */
+#define IIO_NUM_CRBS 15 /* Number of CRBs */
+#define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */
+#define IIO_ICRB_OFFSET 8
+#define IIO_ICRB_0 IIO_ICRB0_A
+#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */
+/* XXX - This is now tuneable:
+ #define IIO_FIRST_PC_ENTRY 12
+ */
+
+#define IIO_ICRB_A(_x) ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x))))
+#define IIO_ICRB_B(_x) ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET))
+#define IIO_ICRB_C(_x) ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET))
+#define IIO_ICRB_D(_x) ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET))
+#define IIO_ICRB_E(_x) ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET))
+
+#define TNUM_TO_WIDGET_DEV(_tnum) (_tnum & 0x7)
+
+/*
+ * values for "ecode" field
+ */
+#define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */
+#define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */
+#define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access
+ * e.g. WINV to a Read only line. */
+#define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */
+#define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */
+#define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */
+#define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */
+#define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */
+
+/*
+ * Values for field imsgtype
+ */
+#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */
+#define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */
+#define IIO_ICRB_IMSGT_SN1NET 2 /* Incoming message from SN1 net */
+#define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */
+
+/*
+ * values for field initiator.
+ */
+#define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */
+#define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */
+#define IIO_ICRB_INIT_SN1NET 0x2 /* Message originated in SN1net */
+#define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */
+#define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */
+
+/*
+ * Number of credits Hub widget has while sending req/response to
+ * xbow.
+ * Value of 3 is required by Xbow 1.1
+ * We may be able to increase this to 4 with Xbow 1.2.
+ */
+#define HUBII_XBOW_CREDIT 3
+#define HUBII_XBOW_REV2_CREDIT 4
+
+/*
+ * Number of credits that xtalk devices should use when communicating
+ * with a SHub (depth of SHub's queue).
+ */
+#define HUB_CREDIT 4
+
+/*
+ * Some IIO_PRB fields
+ */
+#define IIO_PRB_MULTI_ERR (1LL << 63)
+#define IIO_PRB_SPUR_RD (1LL << 51)
+#define IIO_PRB_SPUR_WR (1LL << 50)
+#define IIO_PRB_RD_TO (1LL << 49)
+#define IIO_PRB_ERROR (1LL << 48)
+
+/*************************************************************************
+
+ Some of the IIO field masks and shifts are defined here.
+ This is in order to maintain compatibility in SN0 and SN1 code
+
+**************************************************************************/
+
+/*
+ * ICMR register fields
+ * (Note: the IIO_ICMR_P_CNT and IIO_ICMR_PC_VLD from Hub are not
+ * present in SHub)
+ */
+
+#define IIO_ICMR_CRB_VLD_SHFT 20
+#define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
+
+#define IIO_ICMR_FC_CNT_SHFT 16
+#define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT)
+
+#define IIO_ICMR_C_CNT_SHFT 4
+#define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT)
+
+#define IIO_ICMR_PRECISE (1UL << 52)
+#define IIO_ICMR_CLR_RPPD (1UL << 13)
+#define IIO_ICMR_CLR_RQPD (1UL << 12)
+
+/*
+ * IIO PIO Deallocation register field masks : (IIO_IPDR)
+ XXX present but not needed in bedrock? See the manual.
+ */
+#define IIO_IPDR_PND (1 << 4)
+
+/*
+ * IIO CRB deallocation register field masks: (IIO_ICDR)
+ */
+#define IIO_ICDR_PND (1 << 4)
+
+/*
+ * IO BTE Length/Status (IIO_IBLS) register bit field definitions
+ */
+#define IBLS_BUSY (0x1UL << 20)
+#define IBLS_ERROR_SHFT 16
+#define IBLS_ERROR (0x1UL << IBLS_ERROR_SHFT)
+#define IBLS_LENGTH_MASK 0xffff
+
+/*
+ * IO BTE Control/Terminate register (IBCT) register bit field definitions
+ */
+#define IBCT_POISON (0x1UL << 8)
+#define IBCT_NOTIFY (0x1UL << 4)
+#define IBCT_ZFIL_MODE (0x1UL << 0)
+
+/*
+ * IIO Incoming Error Packet Header (IIO_IIEPH1/IIO_IIEPH2)
+ */
+#define IIEPH1_VALID (1UL << 44)
+#define IIEPH1_OVERRUN (1UL << 40)
+#define IIEPH1_ERR_TYPE_SHFT 32
+#define IIEPH1_ERR_TYPE_MASK 0xf
+#define IIEPH1_SOURCE_SHFT 20
+#define IIEPH1_SOURCE_MASK 11
+#define IIEPH1_SUPPL_SHFT 8
+#define IIEPH1_SUPPL_MASK 11
+#define IIEPH1_CMD_SHFT 0
+#define IIEPH1_CMD_MASK 7
+
+#define IIEPH2_TAIL (1UL << 40)
+#define IIEPH2_ADDRESS_SHFT 0
+#define IIEPH2_ADDRESS_MASK 38
+
+#define IIEPH1_ERR_SHORT_REQ 2
+#define IIEPH1_ERR_SHORT_REPLY 3
+#define IIEPH1_ERR_LONG_REQ 4
+#define IIEPH1_ERR_LONG_REPLY 5
+
+/*
+ * IO Error Clear register bit field definitions
+ */
+#define IECLR_PI1_FWD_INT (1UL << 31) /* clear PI1_FORWARD_INT in iidsr */
+#define IECLR_PI0_FWD_INT (1UL << 30) /* clear PI0_FORWARD_INT in iidsr */
+#define IECLR_SPUR_RD_HDR (1UL << 29) /* clear valid bit in ixss reg */
+#define IECLR_BTE1 (1UL << 18) /* clear bte error 1 */
+#define IECLR_BTE0 (1UL << 17) /* clear bte error 0 */
+#define IECLR_CRAZY (1UL << 16) /* clear crazy bit in wstat reg */
+#define IECLR_PRB_F (1UL << 15) /* clear err bit in PRB_F reg */
+#define IECLR_PRB_E (1UL << 14) /* clear err bit in PRB_E reg */
+#define IECLR_PRB_D (1UL << 13) /* clear err bit in PRB_D reg */
+#define IECLR_PRB_C (1UL << 12) /* clear err bit in PRB_C reg */
+#define IECLR_PRB_B (1UL << 11) /* clear err bit in PRB_B reg */
+#define IECLR_PRB_A (1UL << 10) /* clear err bit in PRB_A reg */
+#define IECLR_PRB_9 (1UL << 9) /* clear err bit in PRB_9 reg */
+#define IECLR_PRB_8 (1UL << 8) /* clear err bit in PRB_8 reg */
+#define IECLR_PRB_0 (1UL << 0) /* clear err bit in PRB_0 reg */
+
+/*
+ * IIO CRB control register Fields: IIO_ICCR
+ */
+#define IIO_ICCR_PENDING 0x10000
+#define IIO_ICCR_CMD_MASK 0xFF
+#define IIO_ICCR_CMD_SHFT 7
+#define IIO_ICCR_CMD_NOP 0x0 /* No Op */
+#define IIO_ICCR_CMD_WAKE 0x100 /* Reactivate CRB entry and process */
+#define IIO_ICCR_CMD_TIMEOUT 0x200 /* Make CRB timeout & mark invalid */
+#define IIO_ICCR_CMD_EJECT 0x400 /* Contents of entry written to memory
+ * via a WB
+ */
+#define IIO_ICCR_CMD_FLUSH 0x800
+
+/*
+ *
+ * CRB Register description.
+ *
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ *
+ * Many of the fields in CRB are status bits used by hardware
+ * for implementation of the protocol. It's very dangerous to
+ * mess around with the CRB registers.
+ *
+ * It's OK to read the CRB registers and try to make sense out of the
+ * fields in CRB.
+ *
+ * Updating CRB requires all activities in Hub IIO to be quiesced.
+ * otherwise, a write to CRB could corrupt other CRB entries.
+ * CRBs are here only as a back door peek to shub IIO's status.
+ * Quiescing implies no dmas no PIOs
+ * either directly from the cpu or from sn0net.
+ * this is not something that can be done easily. So, AVOID updating
+ * CRBs.
+ */
+
+/*
+ * Easy access macros for CRBs, all 5 registers (A-E)
+ */
+typedef ii_icrb0_a_u_t icrba_t;
+#define a_sidn ii_icrb0_a_fld_s.ia_sidn
+#define a_tnum ii_icrb0_a_fld_s.ia_tnum
+#define a_addr ii_icrb0_a_fld_s.ia_addr
+#define a_valid ii_icrb0_a_fld_s.ia_vld
+#define a_iow ii_icrb0_a_fld_s.ia_iow
+#define a_regvalue ii_icrb0_a_regval
+
+typedef ii_icrb0_b_u_t icrbb_t;
+#define b_use_old ii_icrb0_b_fld_s.ib_use_old
+#define b_imsgtype ii_icrb0_b_fld_s.ib_imsgtype
+#define b_imsg ii_icrb0_b_fld_s.ib_imsg
+#define b_initiator ii_icrb0_b_fld_s.ib_init
+#define b_exc ii_icrb0_b_fld_s.ib_exc
+#define b_ackcnt ii_icrb0_b_fld_s.ib_ack_cnt
+#define b_resp ii_icrb0_b_fld_s.ib_resp
+#define b_ack ii_icrb0_b_fld_s.ib_ack
+#define b_hold ii_icrb0_b_fld_s.ib_hold
+#define b_wb ii_icrb0_b_fld_s.ib_wb
+#define b_intvn ii_icrb0_b_fld_s.ib_intvn
+#define b_stall_ib ii_icrb0_b_fld_s.ib_stall_ib
+#define b_stall_int ii_icrb0_b_fld_s.ib_stall__intr
+#define b_stall_bte_0 ii_icrb0_b_fld_s.ib_stall__bte_0
+#define b_stall_bte_1 ii_icrb0_b_fld_s.ib_stall__bte_1
+#define b_error ii_icrb0_b_fld_s.ib_error
+#define b_ecode ii_icrb0_b_fld_s.ib_errcode
+#define b_lnetuce ii_icrb0_b_fld_s.ib_ln_uce
+#define b_mark ii_icrb0_b_fld_s.ib_mark
+#define b_xerr ii_icrb0_b_fld_s.ib_xt_err
+#define b_regvalue ii_icrb0_b_regval
+
+typedef ii_icrb0_c_u_t icrbc_t;
+#define c_suppl ii_icrb0_c_fld_s.ic_suppl
+#define c_barrop ii_icrb0_c_fld_s.ic_bo
+#define c_doresp ii_icrb0_c_fld_s.ic_resprqd
+#define c_gbr ii_icrb0_c_fld_s.ic_gbr
+#define c_btenum ii_icrb0_c_fld_s.ic_bte_num
+#define c_cohtrans ii_icrb0_c_fld_s.ic_ct
+#define c_xtsize ii_icrb0_c_fld_s.ic_size
+#define c_source ii_icrb0_c_fld_s.ic_source
+#define c_regvalue ii_icrb0_c_regval
+
+typedef ii_icrb0_d_u_t icrbd_t;
+#define d_sleep ii_icrb0_d_fld_s.id_sleep
+#define d_pricnt ii_icrb0_d_fld_s.id_pr_cnt
+#define d_pripsc ii_icrb0_d_fld_s.id_pr_psc
+#define d_bteop ii_icrb0_d_fld_s.id_bte_op
+#define d_bteaddr ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names */
+#define d_benable ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names */
+#define d_regvalue ii_icrb0_d_regval
+
+typedef ii_icrb0_e_u_t icrbe_t;
+#define icrbe_ctxtvld ii_icrb0_e_fld_s.ie_cvld
+#define icrbe_toutvld ii_icrb0_e_fld_s.ie_tvld
+#define icrbe_context ii_icrb0_e_fld_s.ie_context
+#define icrbe_timeout ii_icrb0_e_fld_s.ie_timeout
+#define e_regvalue ii_icrb0_e_regval
+
+/* Number of widgets supported by shub */
+#define HUB_NUM_WIDGET 9
+#define HUB_WIDGET_ID_MIN 0x8
+#define HUB_WIDGET_ID_MAX 0xf
+
+#define HUB_WIDGET_PART_NUM 0xc120
+#define MAX_HUBS_PER_XBOW 2
+
+/* A few more #defines for backwards compatibility */
+#define iprb_t ii_iprb0_u_t
+#define iprb_regval ii_iprb0_regval
+#define iprb_mult_err ii_iprb0_fld_s.i_mult_err
+#define iprb_spur_rd ii_iprb0_fld_s.i_spur_rd
+#define iprb_spur_wr ii_iprb0_fld_s.i_spur_wr
+#define iprb_rd_to ii_iprb0_fld_s.i_rd_to
+#define iprb_ovflow ii_iprb0_fld_s.i_of_cnt
+#define iprb_error ii_iprb0_fld_s.i_error
+#define iprb_ff ii_iprb0_fld_s.i_f
+#define iprb_mode ii_iprb0_fld_s.i_m
+#define iprb_bnakctr ii_iprb0_fld_s.i_nb
+#define iprb_anakctr ii_iprb0_fld_s.i_na
+#define iprb_xtalkctr ii_iprb0_fld_s.i_c
+
+#define LNK_STAT_WORKING 0x2 /* LLP is working */
+
+#define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */
+#define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */
+#define IIO_WSTAT_TXRETRY_MASK 0x7F /* should be 0xFF?? */
+#define IIO_WSTAT_TXRETRY_SHFT 16
+#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
+ IIO_WSTAT_TXRETRY_MASK)
+
+/* Number of II perf. counters we can multiplex at once */
+
+#define IO_PERF_SETS 32
+
+/* Bit for the widget in inbound access register */
+#define IIO_IIWA_WIDGET(_w) ((u64)(1ULL << _w))
+/* Bit for the widget in outbound access register */
+#define IIO_IOWA_WIDGET(_w) ((u64)(1ULL << _w))
+
+/* NOTE: The following define assumes that we are going to get
+ * widget numbers from 8 thru F and the device numbers within
+ * widget from 0 thru 7.
+ */
+#define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((u64)(1ULL << (8 * ((w) - 8) + (d))))
+
+/* IO Interrupt Destination Register */
+#define IIO_IIDSR_SENT_SHIFT 28
+#define IIO_IIDSR_SENT_MASK 0x30000000
+#define IIO_IIDSR_ENB_SHIFT 24
+#define IIO_IIDSR_ENB_MASK 0x01000000
+#define IIO_IIDSR_NODE_SHIFT 9
+#define IIO_IIDSR_NODE_MASK 0x000ff700
+#define IIO_IIDSR_PI_ID_SHIFT 8
+#define IIO_IIDSR_PI_ID_MASK 0x00000100
+#define IIO_IIDSR_LVL_SHIFT 0
+#define IIO_IIDSR_LVL_MASK 0x000000ff
+
+/* Xtalk timeout threshold register (IIO_IXTT) */
+#define IXTT_RRSP_TO_SHFT 55 /* read response timeout */
+#define IXTT_RRSP_TO_MASK (0x1FULL << IXTT_RRSP_TO_SHFT)
+#define IXTT_RRSP_PS_SHFT 32 /* read responsed TO prescalar */
+#define IXTT_RRSP_PS_MASK (0x7FFFFFULL << IXTT_RRSP_PS_SHFT)
+#define IXTT_TAIL_TO_SHFT 0 /* tail timeout counter threshold */
+#define IXTT_TAIL_TO_MASK (0x3FFFFFFULL << IXTT_TAIL_TO_SHFT)
+
+/*
+ * The IO LLP control status register and widget control register
+ */
+
+typedef union hubii_wcr_u {
+ u64 wcr_reg_value;
+ struct {
+ u64 wcr_widget_id:4, /* LLP crossbar credit */
+ wcr_tag_mode:1, /* Tag mode */
+ wcr_rsvd1:8, /* Reserved */
+ wcr_xbar_crd:3, /* LLP crossbar credit */
+ wcr_f_bad_pkt:1, /* Force bad llp pkt enable */
+ wcr_dir_con:1, /* widget direct connect */
+ wcr_e_thresh:5, /* elasticity threshold */
+ wcr_rsvd:41; /* unused */
+ } wcr_fields_s;
+} hubii_wcr_t;
+
+#define iwcr_dir_con wcr_fields_s.wcr_dir_con
+
+/* The structures below are defined to extract and modify the ii
+performance registers */
+
+/* io_perf_sel allows the caller to specify what tests will be
+ performed */
+
+typedef union io_perf_sel {
+ u64 perf_sel_reg;
+ struct {
+ u64 perf_ippr0:4, perf_ippr1:4, perf_icct:8, perf_rsvd:48;
+ } perf_sel_bits;
+} io_perf_sel_t;
+
+/* io_perf_cnt is to extract the count from the shub registers. Due to
+ hardware problems there is only one counter, not two. */
+
+typedef union io_perf_cnt {
+ u64 perf_cnt;
+ struct {
+ u64 perf_cnt:20, perf_rsvd2:12, perf_rsvd1:32;
+ } perf_cnt_bits;
+
+} io_perf_cnt_t;
+
+typedef union iprte_a {
+ u64 entry;
+ struct {
+ u64 i_rsvd_1:3;
+ u64 i_addr:38;
+ u64 i_init:3;
+ u64 i_source:8;
+ u64 i_rsvd:2;
+ u64 i_widget:4;
+ u64 i_to_cnt:5;
+ u64 i_vld:1;
+ } iprte_fields;
+} iprte_a_t;
+
+#endif /* _ASM_IA64_SN_SHUBIO_H */
diff --git a/kernel/arch/ia64/include/asm/sn/simulator.h b/kernel/arch/ia64/include/asm/sn/simulator.h
new file mode 100644
index 000000000..c2611f6cf
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/simulator.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_SIMULATOR_H
+#define _ASM_IA64_SN_SIMULATOR_H
+
+#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2) || defined(CONFIG_IA64_SGI_UV)
+#define SNMAGIC 0xaeeeeeee8badbeefL
+#define IS_MEDUSA() ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;})
+
+#define SIMULATOR_SLEEP() asm("nop.i 0x8beef")
+#define IS_RUNNING_ON_SIMULATOR() (sn_prom_type)
+#define IS_RUNNING_ON_FAKE_PROM() (sn_prom_type == 2)
+extern int sn_prom_type; /* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */
+#else
+#define IS_MEDUSA() 0
+#define SIMULATOR_SLEEP()
+#define IS_RUNNING_ON_SIMULATOR() 0
+#endif
+
+#endif /* _ASM_IA64_SN_SIMULATOR_H */
diff --git a/kernel/arch/ia64/include/asm/sn/sn2/sn_hwperf.h b/kernel/arch/ia64/include/asm/sn/sn2/sn_hwperf.h
new file mode 100644
index 000000000..e61ebac38
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/sn2/sn_hwperf.h
@@ -0,0 +1,242 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved.
+ *
+ * Data types used by the SN_SAL_HWPERF_OP SAL call for monitoring
+ * SGI Altix node and router hardware
+ *
+ * Mark Goodwin <markgw@sgi.com> Mon Aug 30 12:23:46 EST 2004
+ */
+
+#ifndef SN_HWPERF_H
+#define SN_HWPERF_H
+
+/*
+ * object structure. SN_HWPERF_ENUM_OBJECTS and SN_HWPERF_GET_CPU_INFO
+ * return an array of these. Do not change this without also
+ * changing the corresponding SAL code.
+ */
+#define SN_HWPERF_MAXSTRING 128
+struct sn_hwperf_object_info {
+ u32 id;
+ union {
+ struct {
+ u64 this_part:1;
+ u64 is_shared:1;
+ } fields;
+ struct {
+ u64 flags;
+ u64 reserved;
+ } b;
+ } f;
+ char name[SN_HWPERF_MAXSTRING];
+ char location[SN_HWPERF_MAXSTRING];
+ u32 ports;
+};
+
+#define sn_hwp_this_part f.fields.this_part
+#define sn_hwp_is_shared f.fields.is_shared
+#define sn_hwp_flags f.b.flags
+
+/* macros for object classification */
+#define SN_HWPERF_IS_NODE(x) ((x) && strstr((x)->name, "SHub"))
+#define SN_HWPERF_IS_NODE_SHUB2(x) ((x) && strstr((x)->name, "SHub 2."))
+#define SN_HWPERF_IS_IONODE(x) ((x) && strstr((x)->name, "TIO"))
+#define SN_HWPERF_IS_NL3ROUTER(x) ((x) && strstr((x)->name, "NL3Router"))
+#define SN_HWPERF_IS_NL4ROUTER(x) ((x) && strstr((x)->name, "NL4Router"))
+#define SN_HWPERF_IS_OLDROUTER(x) ((x) && strstr((x)->name, "Router"))
+#define SN_HWPERF_IS_ROUTER(x) (SN_HWPERF_IS_NL3ROUTER(x) || \
+ SN_HWPERF_IS_NL4ROUTER(x) || \
+ SN_HWPERF_IS_OLDROUTER(x))
+#define SN_HWPERF_FOREIGN(x) ((x) && !(x)->sn_hwp_this_part && !(x)->sn_hwp_is_shared)
+#define SN_HWPERF_SAME_OBJTYPE(x,y) ((SN_HWPERF_IS_NODE(x) && SN_HWPERF_IS_NODE(y)) ||\
+ (SN_HWPERF_IS_IONODE(x) && SN_HWPERF_IS_IONODE(y)) ||\
+ (SN_HWPERF_IS_ROUTER(x) && SN_HWPERF_IS_ROUTER(y)))
+
+/* numa port structure, SN_HWPERF_ENUM_PORTS returns an array of these */
+struct sn_hwperf_port_info {
+ u32 port;
+ u32 conn_id;
+ u32 conn_port;
+};
+
+/* for HWPERF_{GET,SET}_MMRS */
+struct sn_hwperf_data {
+ u64 addr;
+ u64 data;
+};
+
+/* user ioctl() argument, see below */
+struct sn_hwperf_ioctl_args {
+ u64 arg; /* argument, usually an object id */
+ u64 sz; /* size of transfer */
+ void *ptr; /* pointer to source/target */
+ u32 v0; /* second return value */
+};
+
+/*
+ * For SN_HWPERF_{GET,SET}_MMRS and SN_HWPERF_OBJECT_DISTANCE,
+ * sn_hwperf_ioctl_args.arg can be used to specify a CPU on which
+ * to call SAL, and whether to use an interprocessor interrupt
+ * or task migration in order to do so. If the CPU specified is
+ * SN_HWPERF_ARG_ANY_CPU, then the current CPU will be used.
+ */
+#define SN_HWPERF_ARG_ANY_CPU 0x7fffffffUL
+#define SN_HWPERF_ARG_CPU_MASK 0x7fffffff00000000ULL
+#define SN_HWPERF_ARG_USE_IPI_MASK 0x8000000000000000ULL
+#define SN_HWPERF_ARG_OBJID_MASK 0x00000000ffffffffULL
+
+/*
+ * ioctl requests on the "sn_hwperf" misc device that call SAL.
+ */
+#define SN_HWPERF_OP_MEM_COPYIN 0x1000
+#define SN_HWPERF_OP_MEM_COPYOUT 0x2000
+#define SN_HWPERF_OP_MASK 0x0fff
+
+/*
+ * Determine mem requirement.
+ * arg don't care
+ * sz 8
+ * p pointer to u64 integer
+ */
+#define SN_HWPERF_GET_HEAPSIZE 1
+
+/*
+ * Install mem for SAL drvr
+ * arg don't care
+ * sz sizeof buffer pointed to by p
+ * p pointer to buffer for scratch area
+ */
+#define SN_HWPERF_INSTALL_HEAP 2
+
+/*
+ * Determine number of objects
+ * arg don't care
+ * sz 8
+ * p pointer to u64 integer
+ */
+#define SN_HWPERF_OBJECT_COUNT (10|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Determine object "distance", relative to a cpu. This operation can
+ * execute on a designated logical cpu number, using either an IPI or
+ * via task migration. If the cpu number is SN_HWPERF_ANY_CPU, then
+ * the current CPU is used. See the SN_HWPERF_ARG_* macros above.
+ *
+ * arg bitmap of IPI flag, cpu number and object id
+ * sz 8
+ * p pointer to u64 integer
+ */
+#define SN_HWPERF_OBJECT_DISTANCE (11|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Enumerate objects. Special case if sz == 8, returns the required
+ * buffer size.
+ * arg don't care
+ * sz sizeof buffer pointed to by p
+ * p pointer to array of struct sn_hwperf_object_info
+ */
+#define SN_HWPERF_ENUM_OBJECTS (12|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Enumerate NumaLink ports for an object. Special case if sz == 8,
+ * returns the required buffer size.
+ * arg object id
+ * sz sizeof buffer pointed to by p
+ * p pointer to array of struct sn_hwperf_port_info
+ */
+#define SN_HWPERF_ENUM_PORTS (13|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * SET/GET memory mapped registers. These operations can execute
+ * on a designated logical cpu number, using either an IPI or via
+ * task migration. If the cpu number is SN_HWPERF_ANY_CPU, then
+ * the current CPU is used. See the SN_HWPERF_ARG_* macros above.
+ *
+ * arg bitmap of ipi flag, cpu number and object id
+ * sz sizeof buffer pointed to by p
+ * p pointer to array of struct sn_hwperf_data
+ */
+#define SN_HWPERF_SET_MMRS (14|SN_HWPERF_OP_MEM_COPYIN)
+#define SN_HWPERF_GET_MMRS (15|SN_HWPERF_OP_MEM_COPYOUT| \
+ SN_HWPERF_OP_MEM_COPYIN)
+/*
+ * Lock a shared object
+ * arg object id
+ * sz don't care
+ * p don't care
+ */
+#define SN_HWPERF_ACQUIRE 16
+
+/*
+ * Unlock a shared object
+ * arg object id
+ * sz don't care
+ * p don't care
+ */
+#define SN_HWPERF_RELEASE 17
+
+/*
+ * Break a lock on a shared object
+ * arg object id
+ * sz don't care
+ * p don't care
+ */
+#define SN_HWPERF_FORCE_RELEASE 18
+
+/*
+ * ioctl requests on "sn_hwperf" that do not call SAL
+ */
+
+/*
+ * get cpu info as an array of hwperf_object_info_t.
+ * id is logical CPU number, name is description, location
+ * is geoid (e.g. 001c04#1c). Special case if sz == 8,
+ * returns the required buffer size.
+ *
+ * arg don't care
+ * sz sizeof buffer pointed to by p
+ * p pointer to array of struct sn_hwperf_object_info
+ */
+#define SN_HWPERF_GET_CPU_INFO (100|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Given an object id, return it's node number (aka cnode).
+ * arg object id
+ * sz 8
+ * p pointer to u64 integer
+ */
+#define SN_HWPERF_GET_OBJ_NODE (101|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Given a node number (cnode), return it's nasid.
+ * arg ordinal node number (aka cnodeid)
+ * sz 8
+ * p pointer to u64 integer
+ */
+#define SN_HWPERF_GET_NODE_NASID (102|SN_HWPERF_OP_MEM_COPYOUT)
+
+/*
+ * Given a node id, determine the id of the nearest node with CPUs
+ * and the id of the nearest node that has memory. The argument
+ * node would normally be a "headless" node, e.g. an "IO node".
+ * Return 0 on success.
+ */
+extern int sn_hwperf_get_nearest_node(cnodeid_t node,
+ cnodeid_t *near_mem, cnodeid_t *near_cpu);
+
+/* return codes */
+#define SN_HWPERF_OP_OK 0
+#define SN_HWPERF_OP_NOMEM 1
+#define SN_HWPERF_OP_NO_PERM 2
+#define SN_HWPERF_OP_IO_ERROR 3
+#define SN_HWPERF_OP_BUSY 4
+#define SN_HWPERF_OP_RECONFIGURE 253
+#define SN_HWPERF_OP_INVAL 254
+
+int sn_topology_open(struct inode *inode, struct file *file);
+int sn_topology_release(struct inode *inode, struct file *file);
+#endif /* SN_HWPERF_H */
diff --git a/kernel/arch/ia64/include/asm/sn/sn_cpuid.h b/kernel/arch/ia64/include/asm/sn/sn_cpuid.h
new file mode 100644
index 000000000..a676dd9ac
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/sn_cpuid.h
@@ -0,0 +1,132 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+#ifndef _ASM_IA64_SN_SN_CPUID_H
+#define _ASM_IA64_SN_SN_CPUID_H
+
+#include <linux/smp.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/pda.h>
+#include <asm/intrinsics.h>
+
+
+/*
+ * Functions for converting between cpuids, nodeids and NASIDs.
+ *
+ * These are for SGI platforms only.
+ *
+ */
+
+
+
+
+/*
+ * Definitions of terms (these definitions are for IA64 ONLY. Other architectures
+ * use cpuid/cpunum quite defferently):
+ *
+ * CPUID - a number in range of 0..NR_CPUS-1 that uniquely identifies
+ * the cpu. The value cpuid has no significance on IA64 other than
+ * the boot cpu is 0.
+ * smp_processor_id() returns the cpuid of the current cpu.
+ *
+ * CPU_PHYSICAL_ID (also known as HARD_PROCESSOR_ID)
+ * This is the same as 31:24 of the processor LID register
+ * hard_smp_processor_id()- cpu_physical_id of current processor
+ * cpu_physical_id(cpuid) - convert a <cpuid> to a <physical_cpuid>
+ * cpu_logical_id(phy_id) - convert a <physical_cpuid> to a <cpuid>
+ * * not real efficient - don't use in perf critical code
+ *
+ * SLICE - a number in the range of 0 - 3 (typically) that represents the
+ * cpu number on a brick.
+ *
+ * SUBNODE - (almost obsolete) the number of the FSB that a cpu is
+ * connected to. This is also the same as the PI number. Usually 0 or 1.
+ *
+ * NOTE!!!: the value of the bits in the cpu physical id (SAPICid or LID) of a cpu has no
+ * significance. The SAPIC id (LID) is a 16-bit cookie that has meaning only to the PROM.
+ *
+ *
+ * The macros convert between cpu physical ids & slice/nasid/cnodeid.
+ * These terms are described below:
+ *
+ *
+ * Brick
+ * ----- ----- ----- ----- CPU
+ * | 0 | | 1 | | 0 | | 1 | SLICE
+ * ----- ----- ----- -----
+ * | | | |
+ * | | | |
+ * 0 | | 2 0 | | 2 FSB SLOT
+ * ------- -------
+ * | |
+ * | |
+ * | |
+ * ------------ -------------
+ * | | | |
+ * | SHUB | | SHUB | NASID (0..MAX_NASIDS)
+ * | |----- | | CNODEID (0..num_compact_nodes-1)
+ * | | | |
+ * | | | |
+ * ------------ -------------
+ * | |
+ *
+ *
+ */
+
+#define get_node_number(addr) NASID_GET(addr)
+
+/*
+ * NOTE: on non-MP systems, only cpuid 0 exists
+ */
+
+extern short physical_node_map[]; /* indexed by nasid to get cnode */
+
+/*
+ * Macros for retrieving info about current cpu
+ */
+#define get_nasid() (sn_nodepda->phys_cpuid[smp_processor_id()].nasid)
+#define get_subnode() (sn_nodepda->phys_cpuid[smp_processor_id()].subnode)
+#define get_slice() (sn_nodepda->phys_cpuid[smp_processor_id()].slice)
+#define get_cnode() (sn_nodepda->phys_cpuid[smp_processor_id()].cnode)
+#define get_sapicid() ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff)
+
+/*
+ * Macros for retrieving info about an arbitrary cpu
+ * cpuid - logical cpu id
+ */
+#define cpuid_to_nasid(cpuid) (sn_nodepda->phys_cpuid[cpuid].nasid)
+#define cpuid_to_subnode(cpuid) (sn_nodepda->phys_cpuid[cpuid].subnode)
+#define cpuid_to_slice(cpuid) (sn_nodepda->phys_cpuid[cpuid].slice)
+
+
+/*
+ * Dont use the following in performance critical code. They require scans
+ * of potentially large tables.
+ */
+extern int nasid_slice_to_cpuid(int, int);
+
+/*
+ * cnodeid_to_nasid - convert a cnodeid to a NASID
+ */
+#define cnodeid_to_nasid(cnodeid) (sn_cnodeid_to_nasid[cnodeid])
+
+/*
+ * nasid_to_cnodeid - convert a NASID to a cnodeid
+ */
+#define nasid_to_cnodeid(nasid) (physical_node_map[nasid])
+
+/*
+ * partition_coherence_id - get the coherence ID of the current partition
+ */
+extern u8 sn_coherency_id;
+#define partition_coherence_id() (sn_coherency_id)
+
+#endif /* _ASM_IA64_SN_SN_CPUID_H */
+
diff --git a/kernel/arch/ia64/include/asm/sn/sn_feature_sets.h b/kernel/arch/ia64/include/asm/sn/sn_feature_sets.h
new file mode 100644
index 000000000..8e83ac117
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/sn_feature_sets.h
@@ -0,0 +1,58 @@
+#ifndef _ASM_IA64_SN_FEATURE_SETS_H
+#define _ASM_IA64_SN_FEATURE_SETS_H
+
+/*
+ * SN PROM Features
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2005-2006 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+/* --------------------- PROM Features -----------------------------*/
+extern int sn_prom_feature_available(int id);
+
+#define MAX_PROM_FEATURE_SETS 2
+
+/*
+ * The following defines features that may or may not be supported by the
+ * current PROM. The OS uses sn_prom_feature_available(feature) to test for
+ * the presence of a PROM feature. Down rev (old) PROMs will always test
+ * "false" for new features.
+ *
+ * Use:
+ * if (sn_prom_feature_available(PRF_XXX))
+ * ...
+ */
+
+#define PRF_PAL_CACHE_FLUSH_SAFE 0
+#define PRF_DEVICE_FLUSH_LIST 1
+#define PRF_HOTPLUG_SUPPORT 2
+#define PRF_CPU_DISABLE_SUPPORT 3
+
+/* --------------------- OS Features -------------------------------*/
+
+/*
+ * The following defines OS features that are optionally present in
+ * the operating system.
+ * During boot, PROM is notified of these features via a series of calls:
+ *
+ * ia64_sn_set_os_feature(feature1);
+ *
+ * Once enabled, a feature cannot be disabled.
+ *
+ * By default, features are disabled unless explicitly enabled.
+ *
+ * These defines must be kept in sync with the corresponding
+ * PROM definitions in feature_sets.h.
+ */
+#define OSF_MCA_SLV_TO_OS_INIT_SLV 0
+#define OSF_FEAT_LOG_SBES 1
+#define OSF_ACPI_ENABLE 2
+#define OSF_PCISEGMENT_ENABLE 3
+
+
+#endif /* _ASM_IA64_SN_FEATURE_SETS_H */
diff --git a/kernel/arch/ia64/include/asm/sn/sn_sal.h b/kernel/arch/ia64/include/asm/sn/sn_sal.h
new file mode 100644
index 000000000..1f5ff470a
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/sn_sal.h
@@ -0,0 +1,1233 @@
+#ifndef _ASM_IA64_SN_SN_SAL_H
+#define _ASM_IA64_SN_SN_SAL_H
+
+/*
+ * System Abstraction Layer definitions for IA64
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2000-2006 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+#include <asm/sal.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/geo.h>
+#include <asm/sn/nodepda.h>
+#include <asm/sn/shub_mmr.h>
+
+// SGI Specific Calls
+#define SN_SAL_POD_MODE 0x02000001
+#define SN_SAL_SYSTEM_RESET 0x02000002
+#define SN_SAL_PROBE 0x02000003
+#define SN_SAL_GET_MASTER_NASID 0x02000004
+#define SN_SAL_GET_KLCONFIG_ADDR 0x02000005
+#define SN_SAL_LOG_CE 0x02000006
+#define SN_SAL_REGISTER_CE 0x02000007
+#define SN_SAL_GET_PARTITION_ADDR 0x02000009
+#define SN_SAL_XP_ADDR_REGION 0x0200000f
+#define SN_SAL_NO_FAULT_ZONE_VIRTUAL 0x02000010
+#define SN_SAL_NO_FAULT_ZONE_PHYSICAL 0x02000011
+#define SN_SAL_PRINT_ERROR 0x02000012
+#define SN_SAL_REGISTER_PMI_HANDLER 0x02000014
+#define SN_SAL_SET_ERROR_HANDLING_FEATURES 0x0200001a // reentrant
+#define SN_SAL_GET_FIT_COMPT 0x0200001b // reentrant
+#define SN_SAL_GET_SAPIC_INFO 0x0200001d
+#define SN_SAL_GET_SN_INFO 0x0200001e
+#define SN_SAL_CONSOLE_PUTC 0x02000021
+#define SN_SAL_CONSOLE_GETC 0x02000022
+#define SN_SAL_CONSOLE_PUTS 0x02000023
+#define SN_SAL_CONSOLE_GETS 0x02000024
+#define SN_SAL_CONSOLE_GETS_TIMEOUT 0x02000025
+#define SN_SAL_CONSOLE_POLL 0x02000026
+#define SN_SAL_CONSOLE_INTR 0x02000027
+#define SN_SAL_CONSOLE_PUTB 0x02000028
+#define SN_SAL_CONSOLE_XMIT_CHARS 0x0200002a
+#define SN_SAL_CONSOLE_READC 0x0200002b
+#define SN_SAL_SYSCTL_OP 0x02000030
+#define SN_SAL_SYSCTL_MODID_GET 0x02000031
+#define SN_SAL_SYSCTL_GET 0x02000032
+#define SN_SAL_SYSCTL_IOBRICK_MODULE_GET 0x02000033
+#define SN_SAL_SYSCTL_IO_PORTSPEED_GET 0x02000035
+#define SN_SAL_SYSCTL_SLAB_GET 0x02000036
+#define SN_SAL_BUS_CONFIG 0x02000037
+#define SN_SAL_SYS_SERIAL_GET 0x02000038
+#define SN_SAL_PARTITION_SERIAL_GET 0x02000039
+#define SN_SAL_SYSCTL_PARTITION_GET 0x0200003a
+#define SN_SAL_SYSTEM_POWER_DOWN 0x0200003b
+#define SN_SAL_GET_MASTER_BASEIO_NASID 0x0200003c
+#define SN_SAL_COHERENCE 0x0200003d
+#define SN_SAL_MEMPROTECT 0x0200003e
+#define SN_SAL_SYSCTL_FRU_CAPTURE 0x0200003f
+
+#define SN_SAL_SYSCTL_IOBRICK_PCI_OP 0x02000042 // reentrant
+#define SN_SAL_IROUTER_OP 0x02000043
+#define SN_SAL_SYSCTL_EVENT 0x02000044
+#define SN_SAL_IOIF_INTERRUPT 0x0200004a
+#define SN_SAL_HWPERF_OP 0x02000050 // lock
+#define SN_SAL_IOIF_ERROR_INTERRUPT 0x02000051
+#define SN_SAL_IOIF_PCI_SAFE 0x02000052
+#define SN_SAL_IOIF_SLOT_ENABLE 0x02000053
+#define SN_SAL_IOIF_SLOT_DISABLE 0x02000054
+#define SN_SAL_IOIF_GET_HUBDEV_INFO 0x02000055
+#define SN_SAL_IOIF_GET_PCIBUS_INFO 0x02000056
+#define SN_SAL_IOIF_GET_PCIDEV_INFO 0x02000057
+#define SN_SAL_IOIF_GET_WIDGET_DMAFLUSH_LIST 0x02000058 // deprecated
+#define SN_SAL_IOIF_GET_DEVICE_DMAFLUSH_LIST 0x0200005a
+
+#define SN_SAL_IOIF_INIT 0x0200005f
+#define SN_SAL_HUB_ERROR_INTERRUPT 0x02000060
+#define SN_SAL_BTE_RECOVER 0x02000061
+#define SN_SAL_RESERVED_DO_NOT_USE 0x02000062
+#define SN_SAL_IOIF_GET_PCI_TOPOLOGY 0x02000064
+
+#define SN_SAL_GET_PROM_FEATURE_SET 0x02000065
+#define SN_SAL_SET_OS_FEATURE_SET 0x02000066
+#define SN_SAL_INJECT_ERROR 0x02000067
+#define SN_SAL_SET_CPU_NUMBER 0x02000068
+
+#define SN_SAL_KERNEL_LAUNCH_EVENT 0x02000069
+#define SN_SAL_WATCHLIST_ALLOC 0x02000070
+#define SN_SAL_WATCHLIST_FREE 0x02000071
+
+/*
+ * Service-specific constants
+ */
+
+/* Console interrupt manipulation */
+ /* action codes */
+#define SAL_CONSOLE_INTR_OFF 0 /* turn the interrupt off */
+#define SAL_CONSOLE_INTR_ON 1 /* turn the interrupt on */
+#define SAL_CONSOLE_INTR_STATUS 2 /* retrieve the interrupt status */
+ /* interrupt specification & status return codes */
+#define SAL_CONSOLE_INTR_XMIT 1 /* output interrupt */
+#define SAL_CONSOLE_INTR_RECV 2 /* input interrupt */
+
+/* interrupt handling */
+#define SAL_INTR_ALLOC 1
+#define SAL_INTR_FREE 2
+#define SAL_INTR_REDIRECT 3
+
+/*
+ * operations available on the generic SN_SAL_SYSCTL_OP
+ * runtime service
+ */
+#define SAL_SYSCTL_OP_IOBOARD 0x0001 /* retrieve board type */
+#define SAL_SYSCTL_OP_TIO_JLCK_RST 0x0002 /* issue TIO clock reset */
+
+/*
+ * IRouter (i.e. generalized system controller) operations
+ */
+#define SAL_IROUTER_OPEN 0 /* open a subchannel */
+#define SAL_IROUTER_CLOSE 1 /* close a subchannel */
+#define SAL_IROUTER_SEND 2 /* send part of an IRouter packet */
+#define SAL_IROUTER_RECV 3 /* receive part of an IRouter packet */
+#define SAL_IROUTER_INTR_STATUS 4 /* check the interrupt status for
+ * an open subchannel
+ */
+#define SAL_IROUTER_INTR_ON 5 /* enable an interrupt */
+#define SAL_IROUTER_INTR_OFF 6 /* disable an interrupt */
+#define SAL_IROUTER_INIT 7 /* initialize IRouter driver */
+
+/* IRouter interrupt mask bits */
+#define SAL_IROUTER_INTR_XMIT SAL_CONSOLE_INTR_XMIT
+#define SAL_IROUTER_INTR_RECV SAL_CONSOLE_INTR_RECV
+
+/*
+ * Error Handling Features
+ */
+#define SAL_ERR_FEAT_MCA_SLV_TO_OS_INIT_SLV 0x1 // obsolete
+#define SAL_ERR_FEAT_LOG_SBES 0x2 // obsolete
+#define SAL_ERR_FEAT_MFR_OVERRIDE 0x4
+#define SAL_ERR_FEAT_SBE_THRESHOLD 0xffff0000
+
+/*
+ * SAL Error Codes
+ */
+#define SALRET_MORE_PASSES 1
+#define SALRET_OK 0
+#define SALRET_NOT_IMPLEMENTED (-1)
+#define SALRET_INVALID_ARG (-2)
+#define SALRET_ERROR (-3)
+
+#define SN_SAL_FAKE_PROM 0x02009999
+
+/**
+ * sn_sal_revision - get the SGI SAL revision number
+ *
+ * The SGI PROM stores its version in the sal_[ab]_rev_(major|minor).
+ * This routine simply extracts the major and minor values and
+ * presents them in a u32 format.
+ *
+ * For example, version 4.05 would be represented at 0x0405.
+ */
+static inline u32
+sn_sal_rev(void)
+{
+ struct ia64_sal_systab *systab = __va(efi.sal_systab);
+
+ return (u32)(systab->sal_b_rev_major << 8 | systab->sal_b_rev_minor);
+}
+
+/*
+ * Returns the master console nasid, if the call fails, return an illegal
+ * value.
+ */
+static inline u64
+ia64_sn_get_console_nasid(void)
+{
+ struct ia64_sal_retval ret_stuff;
+
+ ret_stuff.status = 0;
+ ret_stuff.v0 = 0;
+ ret_stuff.v1 = 0;
+ ret_stuff.v2 = 0;
+ SAL_CALL(ret_stuff, SN_SAL_GET_MASTER_NASID, 0, 0, 0, 0, 0, 0, 0);
+
+ if (ret_stuff.status < 0)
+ return ret_stuff.status;
+
+ /* Master console nasid is in 'v0' */
+ return ret_stuff.v0;
+}
+
+/*
+ * Returns the master baseio nasid, if the call fails, return an illegal
+ * value.
+ */
+static inline u64
+ia64_sn_get_master_baseio_nasid(void)
+{
+ struct ia64_sal_retval ret_stuff;
+
+ ret_stuff.status = 0;
+ ret_stuff.v0 = 0;
+ ret_stuff.v1 = 0;
+ ret_stuff.v2 = 0;
+ SAL_CALL(ret_stuff, SN_SAL_GET_MASTER_BASEIO_NASID, 0, 0, 0, 0, 0, 0, 0);
+
+ if (ret_stuff.status < 0)
+ return ret_stuff.status;
+
+ /* Master baseio nasid is in 'v0' */
+ return ret_stuff.v0;
+}
+
+static inline void *
+ia64_sn_get_klconfig_addr(nasid_t nasid)
+{
+ struct ia64_sal_retval ret_stuff;
+
+ ret_stuff.status = 0;
+ ret_stuff.v0 = 0;
+ ret_stuff.v1 = 0;
+ ret_stuff.v2 = 0;
+ SAL_CALL(ret_stuff, SN_SAL_GET_KLCONFIG_ADDR, (u64)nasid, 0, 0, 0, 0, 0, 0);
+ return ret_stuff.v0 ? __va(ret_stuff.v0) : NULL;
+}
+
+/*
+ * Returns the next console character.
+ */
+static inline u64
+ia64_sn_console_getc(int *ch)
+{
+ struct ia64_sal_retval ret_stuff;
+
+ ret_stuff.status = 0;
+ ret_stuff.v0 = 0;
+ ret_stuff.v1 = 0;
+ ret_stuff.v2 = 0;
+ SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_GETC, 0, 0, 0, 0, 0, 0, 0);
+
+ /* character is in 'v0' */
+ *ch = (int)ret_stuff.v0;
+
+ return ret_stuff.status;
+}
+
+/*
+ * Read a character from the SAL console device, after a previous interrupt
+ * or poll operation has given us to know that a character is available
+ * to be read.
+ */
+static inline u64
+ia64_sn_console_readc(void)
+{
+ struct ia64_sal_retval ret_stuff;
+
+ ret_stuff.status = 0;
+ ret_stuff.v0 = 0;
+ ret_stuff.v1 = 0;
+ ret_stuff.v2 = 0;
+ SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_READC, 0, 0, 0, 0, 0, 0, 0);
+
+ /* character is in 'v0' */
+ return ret_stuff.v0;
+}
+
+/*
+ * Sends the given character to the console.
+ */
+static inline u64
+ia64_sn_console_putc(char ch)
+{
+ struct ia64_sal_retval ret_stuff;
+
+ ret_stuff.status = 0;
+ ret_stuff.v0 = 0;
+ ret_stuff.v1 = 0;
+ ret_stuff.v2 = 0;
+ SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTC, (u64)ch, 0, 0, 0, 0, 0, 0);
+
+ return ret_stuff.status;
+}
+
+/*
+ * Sends the given buffer to the console.
+ */
+static inline u64
+ia64_sn_console_putb(const char *buf, int len)
+{
+ struct ia64_sal_retval ret_stuff;
+
+ ret_stuff.status = 0;
+ ret_stuff.v0 = 0;
+ ret_stuff.v1 = 0;
+ ret_stuff.v2 = 0;
+ SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTB, (u64)buf, (u64)len, 0, 0, 0, 0, 0);
+
+ if ( ret_stuff.status == 0 ) {
+ return ret_stuff.v0;
+ }
+ return (u64)0;
+}
+
+/*
+ * Print a platform error record
+ */
+static inline u64
+ia64_sn_plat_specific_err_print(int (*hook)(const char*, ...), char *rec)
+{
+ struct ia64_sal_retval ret_stuff;
+
+ ret_stuff.status = 0;
+ ret_stuff.v0 = 0;
+ ret_stuff.v1 = 0;
+ ret_stuff.v2 = 0;
+ SAL_CALL_REENTRANT(ret_stuff, SN_SAL_PRINT_ERROR, (u64)hook, (u64)rec, 0, 0, 0, 0, 0);
+
+ return ret_stuff.status;
+}
+
+/*
+ * Check for Platform errors
+ */
+static inline u64
+ia64_sn_plat_cpei_handler(void)
+{
+ struct ia64_sal_retval ret_stuff;
+
+ ret_stuff.status = 0;
+ ret_stuff.v0 = 0;
+ ret_stuff.v1 = 0;
+ ret_stuff.v2 = 0;
+ SAL_CALL_NOLOCK(ret_stuff, SN_SAL_LOG_CE, 0, 0, 0, 0, 0, 0, 0);
+
+ return ret_stuff.status;
+}
+
+/*
+ * Set Error Handling Features (Obsolete)
+ */
+static inline u64
+ia64_sn_plat_set_error_handling_features(void)
+{
+ struct ia64_sal_retval ret_stuff;
+
+ ret_stuff.status = 0;
+ ret_stuff.v0 = 0;
+ ret_stuff.v1 = 0;
+ ret_stuff.v2 = 0;
+ SAL_CALL_REENTRANT(ret_stuff, SN_SAL_SET_ERROR_HANDLING_FEATURES,
+ SAL_ERR_FEAT_LOG_SBES,
+ 0, 0, 0, 0, 0, 0);
+
+ return ret_stuff.status;
+}
+
+/*
+ * Checks for console input.
+ */
+static inline u64
+ia64_sn_console_check(int *result)
+{
+ struct ia64_sal_retval ret_stuff;
+
+ ret_stuff.status = 0;
+ ret_stuff.v0 = 0;
+ ret_stuff.v1 = 0;
+ ret_stuff.v2 = 0;
+ SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_POLL, 0, 0, 0, 0, 0, 0, 0);
+
+ /* result is in 'v0' */
+ *result = (int)ret_stuff.v0;
+
+ return ret_stuff.status;
+}
+
+/*
+ * Checks console interrupt status
+ */
+static inline u64
+ia64_sn_console_intr_status(void)
+{
+ struct ia64_sal_retval ret_stuff;
+
+ ret_stuff.status = 0;
+ ret_stuff.v0 = 0;
+ ret_stuff.v1 = 0;
+ ret_stuff.v2 = 0;
+ SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR,
+ 0, SAL_CONSOLE_INTR_STATUS,
+ 0, 0, 0, 0, 0);
+
+ if (ret_stuff.status == 0) {
+ return ret_stuff.v0;
+ }
+
+ return 0;
+}
+
+/*
+ * Enable an interrupt on the SAL console device.
+ */
+static inline void
+ia64_sn_console_intr_enable(u64 intr)
+{
+ struct ia64_sal_retval ret_stuff;
+
+ ret_stuff.status = 0;
+ ret_stuff.v0 = 0;
+ ret_stuff.v1 = 0;
+ ret_stuff.v2 = 0;
+ SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR,
+ intr, SAL_CONSOLE_INTR_ON,
+ 0, 0, 0, 0, 0);
+}
+
+/*
+ * Disable an interrupt on the SAL console device.
+ */
+static inline void
+ia64_sn_console_intr_disable(u64 intr)
+{
+ struct ia64_sal_retval ret_stuff;
+
+ ret_stuff.status = 0;
+ ret_stuff.v0 = 0;
+ ret_stuff.v1 = 0;
+ ret_stuff.v2 = 0;
+ SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR,
+ intr, SAL_CONSOLE_INTR_OFF,
+ 0, 0, 0, 0, 0);
+}
+
+/*
+ * Sends a character buffer to the console asynchronously.
+ */
+static inline u64
+ia64_sn_console_xmit_chars(char *buf, int len)
+{
+ struct ia64_sal_retval ret_stuff;
+
+ ret_stuff.status = 0;
+ ret_stuff.v0 = 0;
+ ret_stuff.v1 = 0;
+ ret_stuff.v2 = 0;
+ SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_XMIT_CHARS,
+ (u64)buf, (u64)len,
+ 0, 0, 0, 0, 0);
+
+ if (ret_stuff.status == 0) {
+ return ret_stuff.v0;
+ }
+
+ return 0;
+}
+
+/*
+ * Returns the iobrick module Id
+ */
+static inline u64
+ia64_sn_sysctl_iobrick_module_get(nasid_t nasid, int *result)
+{
+ struct ia64_sal_retval ret_stuff;
+
+ ret_stuff.status = 0;
+ ret_stuff.v0 = 0;
+ ret_stuff.v1 = 0;
+ ret_stuff.v2 = 0;
+ SAL_CALL_NOLOCK(ret_stuff, SN_SAL_SYSCTL_IOBRICK_MODULE_GET, nasid, 0, 0, 0, 0, 0, 0);
+
+ /* result is in 'v0' */
+ *result = (int)ret_stuff.v0;
+
+ return ret_stuff.status;
+}
+
+/**
+ * ia64_sn_pod_mode - call the SN_SAL_POD_MODE function
+ *
+ * SN_SAL_POD_MODE actually takes an argument, but it's always
+ * 0 when we call it from the kernel, so we don't have to expose
+ * it to the caller.
+ */
+static inline u64
+ia64_sn_pod_mode(void)
+{
+ struct ia64_sal_retval isrv;
+ SAL_CALL_REENTRANT(isrv, SN_SAL_POD_MODE, 0, 0, 0, 0, 0, 0, 0);
+ if (isrv.status)
+ return 0;
+ return isrv.v0;
+}
+
+/**
+ * ia64_sn_probe_mem - read from memory safely
+ * @addr: address to probe
+ * @size: number bytes to read (1,2,4,8)
+ * @data_ptr: address to store value read by probe (-1 returned if probe fails)
+ *
+ * Call into the SAL to do a memory read. If the read generates a machine
+ * check, this routine will recover gracefully and return -1 to the caller.
+ * @addr is usually a kernel virtual address in uncached space (i.e. the
+ * address starts with 0xc), but if called in physical mode, @addr should
+ * be a physical address.
+ *
+ * Return values:
+ * 0 - probe successful
+ * 1 - probe failed (generated MCA)
+ * 2 - Bad arg
+ * <0 - PAL error
+ */
+static inline u64
+ia64_sn_probe_mem(long addr, long size, void *data_ptr)
+{
+ struct ia64_sal_retval isrv;
+
+ SAL_CALL(isrv, SN_SAL_PROBE, addr, size, 0, 0, 0, 0, 0);
+
+ if (data_ptr) {
+ switch (size) {
+ case 1:
+ *((u8*)data_ptr) = (u8)isrv.v0;
+ break;
+ case 2:
+ *((u16*)data_ptr) = (u16)isrv.v0;
+ break;
+ case 4:
+ *((u32*)data_ptr) = (u32)isrv.v0;
+ break;
+ case 8:
+ *((u64*)data_ptr) = (u64)isrv.v0;
+ break;
+ default:
+ isrv.status = 2;
+ }
+ }
+ return isrv.status;
+}
+
+/*
+ * Retrieve the system serial number as an ASCII string.
+ */
+static inline u64
+ia64_sn_sys_serial_get(char *buf)
+{
+ struct ia64_sal_retval ret_stuff;
+ SAL_CALL_NOLOCK(ret_stuff, SN_SAL_SYS_SERIAL_GET, buf, 0, 0, 0, 0, 0, 0);
+ return ret_stuff.status;
+}
+
+extern char sn_system_serial_number_string[];
+extern u64 sn_partition_serial_number;
+
+static inline char *
+sn_system_serial_number(void) {
+ if (sn_system_serial_number_string[0]) {
+ return(sn_system_serial_number_string);
+ } else {
+ ia64_sn_sys_serial_get(sn_system_serial_number_string);
+ return(sn_system_serial_number_string);
+ }
+}
+
+
+/*
+ * Returns a unique id number for this system and partition (suitable for
+ * use with license managers), based in part on the system serial number.
+ */
+static inline u64
+ia64_sn_partition_serial_get(void)
+{
+ struct ia64_sal_retval ret_stuff;
+ ia64_sal_oemcall_reentrant(&ret_stuff, SN_SAL_PARTITION_SERIAL_GET, 0,
+ 0, 0, 0, 0, 0, 0);
+ if (ret_stuff.status != 0)
+ return 0;
+ return ret_stuff.v0;
+}
+
+static inline u64
+sn_partition_serial_number_val(void) {
+ if (unlikely(sn_partition_serial_number == 0)) {
+ sn_partition_serial_number = ia64_sn_partition_serial_get();
+ }
+ return sn_partition_serial_number;
+}
+
+/*
+ * Returns the partition id of the nasid passed in as an argument,
+ * or INVALID_PARTID if the partition id cannot be retrieved.
+ */
+static inline partid_t
+ia64_sn_sysctl_partition_get(nasid_t nasid)
+{
+ struct ia64_sal_retval ret_stuff;
+ SAL_CALL(ret_stuff, SN_SAL_SYSCTL_PARTITION_GET, nasid,
+ 0, 0, 0, 0, 0, 0);
+ if (ret_stuff.status != 0)
+ return -1;
+ return ((partid_t)ret_stuff.v0);
+}
+
+/*
+ * Returns the physical address of the partition's reserved page through
+ * an iterative number of calls.
+ *
+ * On first call, 'cookie' and 'len' should be set to 0, and 'addr'
+ * set to the nasid of the partition whose reserved page's address is
+ * being sought.
+ * On subsequent calls, pass the values, that were passed back on the
+ * previous call.
+ *
+ * While the return status equals SALRET_MORE_PASSES, keep calling
+ * this function after first copying 'len' bytes starting at 'addr'
+ * into 'buf'. Once the return status equals SALRET_OK, 'addr' will
+ * be the physical address of the partition's reserved page. If the
+ * return status equals neither of these, an error as occurred.
+ */
+static inline s64
+sn_partition_reserved_page_pa(u64 buf, u64 *cookie, u64 *addr, u64 *len)
+{
+ struct ia64_sal_retval rv;
+ ia64_sal_oemcall_reentrant(&rv, SN_SAL_GET_PARTITION_ADDR, *cookie,
+ *addr, buf, *len, 0, 0, 0);
+ *cookie = rv.v0;
+ *addr = rv.v1;
+ *len = rv.v2;
+ return rv.status;
+}
+
+/*
+ * Register or unregister a physical address range being referenced across
+ * a partition boundary for which certain SAL errors should be scanned for,
+ * cleaned up and ignored. This is of value for kernel partitioning code only.
+ * Values for the operation argument:
+ * 1 = register this address range with SAL
+ * 0 = unregister this address range with SAL
+ *
+ * SAL maintains a reference count on an address range in case it is registered
+ * multiple times.
+ *
+ * On success, returns the reference count of the address range after the SAL
+ * call has performed the current registration/unregistration. Returns a
+ * negative value if an error occurred.
+ */
+static inline int
+sn_register_xp_addr_region(u64 paddr, u64 len, int operation)
+{
+ struct ia64_sal_retval ret_stuff;
+ ia64_sal_oemcall(&ret_stuff, SN_SAL_XP_ADDR_REGION, paddr, len,
+ (u64)operation, 0, 0, 0, 0);
+ return ret_stuff.status;
+}
+
+/*
+ * Register or unregister an instruction range for which SAL errors should
+ * be ignored. If an error occurs while in the registered range, SAL jumps
+ * to return_addr after ignoring the error. Values for the operation argument:
+ * 1 = register this instruction range with SAL
+ * 0 = unregister this instruction range with SAL
+ *
+ * Returns 0 on success, or a negative value if an error occurred.
+ */
+static inline int
+sn_register_nofault_code(u64 start_addr, u64 end_addr, u64 return_addr,
+ int virtual, int operation)
+{
+ struct ia64_sal_retval ret_stuff;
+ u64 call;
+ if (virtual) {
+ call = SN_SAL_NO_FAULT_ZONE_VIRTUAL;
+ } else {
+ call = SN_SAL_NO_FAULT_ZONE_PHYSICAL;
+ }
+ ia64_sal_oemcall(&ret_stuff, call, start_addr, end_addr, return_addr,
+ (u64)1, 0, 0, 0);
+ return ret_stuff.status;
+}
+
+/*
+ * Register or unregister a function to handle a PMI received by a CPU.
+ * Before calling the registered handler, SAL sets r1 to the value that
+ * was passed in as the global_pointer.
+ *
+ * If the handler pointer is NULL, then the currently registered handler
+ * will be unregistered.
+ *
+ * Returns 0 on success, or a negative value if an error occurred.
+ */
+static inline int
+sn_register_pmi_handler(u64 handler, u64 global_pointer)
+{
+ struct ia64_sal_retval ret_stuff;
+ ia64_sal_oemcall(&ret_stuff, SN_SAL_REGISTER_PMI_HANDLER, handler,
+ global_pointer, 0, 0, 0, 0, 0);
+ return ret_stuff.status;
+}
+
+/*
+ * Change or query the coherence domain for this partition. Each cpu-based
+ * nasid is represented by a bit in an array of 64-bit words:
+ * 0 = not in this partition's coherency domain
+ * 1 = in this partition's coherency domain
+ *
+ * It is not possible for the local system's nasids to be removed from
+ * the coherency domain. Purpose of the domain arguments:
+ * new_domain = set the coherence domain to the given nasids
+ * old_domain = return the current coherence domain
+ *
+ * Returns 0 on success, or a negative value if an error occurred.
+ */
+static inline int
+sn_change_coherence(u64 *new_domain, u64 *old_domain)
+{
+ struct ia64_sal_retval ret_stuff;
+ ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_COHERENCE, (u64)new_domain,
+ (u64)old_domain, 0, 0, 0, 0, 0);
+ return ret_stuff.status;
+}
+
+/*
+ * Change memory access protections for a physical address range.
+ * nasid_array is not used on Altix, but may be in future architectures.
+ * Available memory protection access classes are defined after the function.
+ */
+static inline int
+sn_change_memprotect(u64 paddr, u64 len, u64 perms, u64 *nasid_array)
+{
+ struct ia64_sal_retval ret_stuff;
+
+ ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_MEMPROTECT, paddr, len,
+ (u64)nasid_array, perms, 0, 0, 0);
+ return ret_stuff.status;
+}
+#define SN_MEMPROT_ACCESS_CLASS_0 0x14a080
+#define SN_MEMPROT_ACCESS_CLASS_1 0x2520c2
+#define SN_MEMPROT_ACCESS_CLASS_2 0x14a1ca
+#define SN_MEMPROT_ACCESS_CLASS_3 0x14a290
+#define SN_MEMPROT_ACCESS_CLASS_6 0x084080
+#define SN_MEMPROT_ACCESS_CLASS_7 0x021080
+
+/*
+ * Turns off system power.
+ */
+static inline void
+ia64_sn_power_down(void)
+{
+ struct ia64_sal_retval ret_stuff;
+ SAL_CALL(ret_stuff, SN_SAL_SYSTEM_POWER_DOWN, 0, 0, 0, 0, 0, 0, 0);
+ while(1)
+ cpu_relax();
+ /* never returns */
+}
+
+/**
+ * ia64_sn_fru_capture - tell the system controller to capture hw state
+ *
+ * This routine will call the SAL which will tell the system controller(s)
+ * to capture hw mmr information from each SHub in the system.
+ */
+static inline u64
+ia64_sn_fru_capture(void)
+{
+ struct ia64_sal_retval isrv;
+ SAL_CALL(isrv, SN_SAL_SYSCTL_FRU_CAPTURE, 0, 0, 0, 0, 0, 0, 0);
+ if (isrv.status)
+ return 0;
+ return isrv.v0;
+}
+
+/*
+ * Performs an operation on a PCI bus or slot -- power up, power down
+ * or reset.
+ */
+static inline u64
+ia64_sn_sysctl_iobrick_pci_op(nasid_t n, u64 connection_type,
+ u64 bus, char slot,
+ u64 action)
+{
+ struct ia64_sal_retval rv = {0, 0, 0, 0};
+
+ SAL_CALL_NOLOCK(rv, SN_SAL_SYSCTL_IOBRICK_PCI_OP, connection_type, n, action,
+ bus, (u64) slot, 0, 0);
+ if (rv.status)
+ return rv.v0;
+ return 0;
+}
+
+
+/*
+ * Open a subchannel for sending arbitrary data to the system
+ * controller network via the system controller device associated with
+ * 'nasid'. Return the subchannel number or a negative error code.
+ */
+static inline int
+ia64_sn_irtr_open(nasid_t nasid)
+{
+ struct ia64_sal_retval rv;
+ SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_OPEN, nasid,
+ 0, 0, 0, 0, 0);
+ return (int) rv.v0;
+}
+
+/*
+ * Close system controller subchannel 'subch' previously opened on 'nasid'.
+ */
+static inline int
+ia64_sn_irtr_close(nasid_t nasid, int subch)
+{
+ struct ia64_sal_retval rv;
+ SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_CLOSE,
+ (u64) nasid, (u64) subch, 0, 0, 0, 0);
+ return (int) rv.status;
+}
+
+/*
+ * Read data from system controller associated with 'nasid' on
+ * subchannel 'subch'. The buffer to be filled is pointed to by
+ * 'buf', and its capacity is in the integer pointed to by 'len'. The
+ * referent of 'len' is set to the number of bytes read by the SAL
+ * call. The return value is either SALRET_OK (for bytes read) or
+ * SALRET_ERROR (for error or "no data available").
+ */
+static inline int
+ia64_sn_irtr_recv(nasid_t nasid, int subch, char *buf, int *len)
+{
+ struct ia64_sal_retval rv;
+ SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_RECV,
+ (u64) nasid, (u64) subch, (u64) buf, (u64) len,
+ 0, 0);
+ return (int) rv.status;
+}
+
+/*
+ * Write data to the system controller network via the system
+ * controller associated with 'nasid' on suchannel 'subch'. The
+ * buffer to be written out is pointed to by 'buf', and 'len' is the
+ * number of bytes to be written. The return value is either the
+ * number of bytes written (which could be zero) or a negative error
+ * code.
+ */
+static inline int
+ia64_sn_irtr_send(nasid_t nasid, int subch, char *buf, int len)
+{
+ struct ia64_sal_retval rv;
+ SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_SEND,
+ (u64) nasid, (u64) subch, (u64) buf, (u64) len,
+ 0, 0);
+ return (int) rv.v0;
+}
+
+/*
+ * Check whether any interrupts are pending for the system controller
+ * associated with 'nasid' and its subchannel 'subch'. The return
+ * value is a mask of pending interrupts (SAL_IROUTER_INTR_XMIT and/or
+ * SAL_IROUTER_INTR_RECV).
+ */
+static inline int
+ia64_sn_irtr_intr(nasid_t nasid, int subch)
+{
+ struct ia64_sal_retval rv;
+ SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INTR_STATUS,
+ (u64) nasid, (u64) subch, 0, 0, 0, 0);
+ return (int) rv.v0;
+}
+
+/*
+ * Enable the interrupt indicated by the intr parameter (either
+ * SAL_IROUTER_INTR_XMIT or SAL_IROUTER_INTR_RECV).
+ */
+static inline int
+ia64_sn_irtr_intr_enable(nasid_t nasid, int subch, u64 intr)
+{
+ struct ia64_sal_retval rv;
+ SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INTR_ON,
+ (u64) nasid, (u64) subch, intr, 0, 0, 0);
+ return (int) rv.v0;
+}
+
+/*
+ * Disable the interrupt indicated by the intr parameter (either
+ * SAL_IROUTER_INTR_XMIT or SAL_IROUTER_INTR_RECV).
+ */
+static inline int
+ia64_sn_irtr_intr_disable(nasid_t nasid, int subch, u64 intr)
+{
+ struct ia64_sal_retval rv;
+ SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INTR_OFF,
+ (u64) nasid, (u64) subch, intr, 0, 0, 0);
+ return (int) rv.v0;
+}
+
+/*
+ * Set up a node as the point of contact for system controller
+ * environmental event delivery.
+ */
+static inline int
+ia64_sn_sysctl_event_init(nasid_t nasid)
+{
+ struct ia64_sal_retval rv;
+ SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_EVENT, (u64) nasid,
+ 0, 0, 0, 0, 0, 0);
+ return (int) rv.v0;
+}
+
+/*
+ * Ask the system controller on the specified nasid to reset
+ * the CX corelet clock. Only valid on TIO nodes.
+ */
+static inline int
+ia64_sn_sysctl_tio_clock_reset(nasid_t nasid)
+{
+ struct ia64_sal_retval rv;
+ SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_OP, SAL_SYSCTL_OP_TIO_JLCK_RST,
+ nasid, 0, 0, 0, 0, 0);
+ if (rv.status != 0)
+ return (int)rv.status;
+ if (rv.v0 != 0)
+ return (int)rv.v0;
+
+ return 0;
+}
+
+/*
+ * Get the associated ioboard type for a given nasid.
+ */
+static inline long
+ia64_sn_sysctl_ioboard_get(nasid_t nasid, u16 *ioboard)
+{
+ struct ia64_sal_retval isrv;
+ SAL_CALL_REENTRANT(isrv, SN_SAL_SYSCTL_OP, SAL_SYSCTL_OP_IOBOARD,
+ nasid, 0, 0, 0, 0, 0);
+ if (isrv.v0 != 0) {
+ *ioboard = isrv.v0;
+ return isrv.status;
+ }
+ if (isrv.v1 != 0) {
+ *ioboard = isrv.v1;
+ return isrv.status;
+ }
+
+ return isrv.status;
+}
+
+/**
+ * ia64_sn_get_fit_compt - read a FIT entry from the PROM header
+ * @nasid: NASID of node to read
+ * @index: FIT entry index to be retrieved (0..n)
+ * @fitentry: 16 byte buffer where FIT entry will be stored.
+ * @banbuf: optional buffer for retrieving banner
+ * @banlen: length of banner buffer
+ *
+ * Access to the physical PROM chips needs to be serialized since reads and
+ * writes can't occur at the same time, so we need to call into the SAL when
+ * we want to look at the FIT entries on the chips.
+ *
+ * Returns:
+ * %SALRET_OK if ok
+ * %SALRET_INVALID_ARG if index too big
+ * %SALRET_NOT_IMPLEMENTED if running on older PROM
+ * ??? if nasid invalid OR banner buffer not large enough
+ */
+static inline int
+ia64_sn_get_fit_compt(u64 nasid, u64 index, void *fitentry, void *banbuf,
+ u64 banlen)
+{
+ struct ia64_sal_retval rv;
+ SAL_CALL_NOLOCK(rv, SN_SAL_GET_FIT_COMPT, nasid, index, fitentry,
+ banbuf, banlen, 0, 0);
+ return (int) rv.status;
+}
+
+/*
+ * Initialize the SAL components of the system controller
+ * communication driver; specifically pass in a sizable buffer that
+ * can be used for allocation of subchannel queues as new subchannels
+ * are opened. "buf" points to the buffer, and "len" specifies its
+ * length.
+ */
+static inline int
+ia64_sn_irtr_init(nasid_t nasid, void *buf, int len)
+{
+ struct ia64_sal_retval rv;
+ SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INIT,
+ (u64) nasid, (u64) buf, (u64) len, 0, 0, 0);
+ return (int) rv.status;
+}
+
+/*
+ * Returns the nasid, subnode & slice corresponding to a SAPIC ID
+ *
+ * In:
+ * arg0 - SN_SAL_GET_SAPIC_INFO
+ * arg1 - sapicid (lid >> 16)
+ * Out:
+ * v0 - nasid
+ * v1 - subnode
+ * v2 - slice
+ */
+static inline u64
+ia64_sn_get_sapic_info(int sapicid, int *nasid, int *subnode, int *slice)
+{
+ struct ia64_sal_retval ret_stuff;
+
+ ret_stuff.status = 0;
+ ret_stuff.v0 = 0;
+ ret_stuff.v1 = 0;
+ ret_stuff.v2 = 0;
+ SAL_CALL_NOLOCK(ret_stuff, SN_SAL_GET_SAPIC_INFO, sapicid, 0, 0, 0, 0, 0, 0);
+
+/***** BEGIN HACK - temp til old proms no longer supported ********/
+ if (ret_stuff.status == SALRET_NOT_IMPLEMENTED) {
+ if (nasid) *nasid = sapicid & 0xfff;
+ if (subnode) *subnode = (sapicid >> 13) & 1;
+ if (slice) *slice = (sapicid >> 12) & 3;
+ return 0;
+ }
+/***** END HACK *******/
+
+ if (ret_stuff.status < 0)
+ return ret_stuff.status;
+
+ if (nasid) *nasid = (int) ret_stuff.v0;
+ if (subnode) *subnode = (int) ret_stuff.v1;
+ if (slice) *slice = (int) ret_stuff.v2;
+ return 0;
+}
+
+/*
+ * Returns information about the HUB/SHUB.
+ * In:
+ * arg0 - SN_SAL_GET_SN_INFO
+ * arg1 - 0 (other values reserved for future use)
+ * Out:
+ * v0
+ * [7:0] - shub type (0=shub1, 1=shub2)
+ * [15:8] - Log2 max number of nodes in entire system (includes
+ * C-bricks, I-bricks, etc)
+ * [23:16] - Log2 of nodes per sharing domain
+ * [31:24] - partition ID
+ * [39:32] - coherency_id
+ * [47:40] - regionsize
+ * v1
+ * [15:0] - nasid mask (ex., 0x7ff for 11 bit nasid)
+ * [23:15] - bit position of low nasid bit
+ */
+static inline u64
+ia64_sn_get_sn_info(int fc, u8 *shubtype, u16 *nasid_bitmask, u8 *nasid_shift,
+ u8 *systemsize, u8 *sharing_domain_size, u8 *partid, u8 *coher, u8 *reg)
+{
+ struct ia64_sal_retval ret_stuff;
+
+ ret_stuff.status = 0;
+ ret_stuff.v0 = 0;
+ ret_stuff.v1 = 0;
+ ret_stuff.v2 = 0;
+ SAL_CALL_NOLOCK(ret_stuff, SN_SAL_GET_SN_INFO, fc, 0, 0, 0, 0, 0, 0);
+
+/***** BEGIN HACK - temp til old proms no longer supported ********/
+ if (ret_stuff.status == SALRET_NOT_IMPLEMENTED) {
+ int nasid = get_sapicid() & 0xfff;
+#define SH_SHUB_ID_NODES_PER_BIT_MASK 0x001f000000000000UL
+#define SH_SHUB_ID_NODES_PER_BIT_SHFT 48
+ if (shubtype) *shubtype = 0;
+ if (nasid_bitmask) *nasid_bitmask = 0x7ff;
+ if (nasid_shift) *nasid_shift = 38;
+ if (systemsize) *systemsize = 10;
+ if (sharing_domain_size) *sharing_domain_size = 8;
+ if (partid) *partid = ia64_sn_sysctl_partition_get(nasid);
+ if (coher) *coher = nasid >> 9;
+ if (reg) *reg = (HUB_L((u64 *) LOCAL_MMR_ADDR(SH1_SHUB_ID)) & SH_SHUB_ID_NODES_PER_BIT_MASK) >>
+ SH_SHUB_ID_NODES_PER_BIT_SHFT;
+ return 0;
+ }
+/***** END HACK *******/
+
+ if (ret_stuff.status < 0)
+ return ret_stuff.status;
+
+ if (shubtype) *shubtype = ret_stuff.v0 & 0xff;
+ if (systemsize) *systemsize = (ret_stuff.v0 >> 8) & 0xff;
+ if (sharing_domain_size) *sharing_domain_size = (ret_stuff.v0 >> 16) & 0xff;
+ if (partid) *partid = (ret_stuff.v0 >> 24) & 0xff;
+ if (coher) *coher = (ret_stuff.v0 >> 32) & 0xff;
+ if (reg) *reg = (ret_stuff.v0 >> 40) & 0xff;
+ if (nasid_bitmask) *nasid_bitmask = (ret_stuff.v1 & 0xffff);
+ if (nasid_shift) *nasid_shift = (ret_stuff.v1 >> 16) & 0xff;
+ return 0;
+}
+
+/*
+ * This is the access point to the Altix PROM hardware performance
+ * and status monitoring interface. For info on using this, see
+ * arch/ia64/include/asm/sn/sn2/sn_hwperf.h
+ */
+static inline int
+ia64_sn_hwperf_op(nasid_t nasid, u64 opcode, u64 a0, u64 a1, u64 a2,
+ u64 a3, u64 a4, int *v0)
+{
+ struct ia64_sal_retval rv;
+ SAL_CALL_NOLOCK(rv, SN_SAL_HWPERF_OP, (u64)nasid,
+ opcode, a0, a1, a2, a3, a4);
+ if (v0)
+ *v0 = (int) rv.v0;
+ return (int) rv.status;
+}
+
+static inline int
+ia64_sn_ioif_get_pci_topology(u64 buf, u64 len)
+{
+ struct ia64_sal_retval rv;
+ SAL_CALL_NOLOCK(rv, SN_SAL_IOIF_GET_PCI_TOPOLOGY, buf, len, 0, 0, 0, 0, 0);
+ return (int) rv.status;
+}
+
+/*
+ * BTE error recovery is implemented in SAL
+ */
+static inline int
+ia64_sn_bte_recovery(nasid_t nasid)
+{
+ struct ia64_sal_retval rv;
+
+ rv.status = 0;
+ SAL_CALL_NOLOCK(rv, SN_SAL_BTE_RECOVER, (u64)nasid, 0, 0, 0, 0, 0, 0);
+ if (rv.status == SALRET_NOT_IMPLEMENTED)
+ return 0;
+ return (int) rv.status;
+}
+
+static inline int
+ia64_sn_is_fake_prom(void)
+{
+ struct ia64_sal_retval rv;
+ SAL_CALL_NOLOCK(rv, SN_SAL_FAKE_PROM, 0, 0, 0, 0, 0, 0, 0);
+ return (rv.status == 0);
+}
+
+static inline int
+ia64_sn_get_prom_feature_set(int set, unsigned long *feature_set)
+{
+ struct ia64_sal_retval rv;
+
+ SAL_CALL_NOLOCK(rv, SN_SAL_GET_PROM_FEATURE_SET, set, 0, 0, 0, 0, 0, 0);
+ if (rv.status != 0)
+ return rv.status;
+ *feature_set = rv.v0;
+ return 0;
+}
+
+static inline int
+ia64_sn_set_os_feature(int feature)
+{
+ struct ia64_sal_retval rv;
+
+ SAL_CALL_NOLOCK(rv, SN_SAL_SET_OS_FEATURE_SET, feature, 0, 0, 0, 0, 0, 0);
+ return rv.status;
+}
+
+static inline int
+sn_inject_error(u64 paddr, u64 *data, u64 *ecc)
+{
+ struct ia64_sal_retval ret_stuff;
+
+ ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_INJECT_ERROR, paddr, (u64)data,
+ (u64)ecc, 0, 0, 0, 0);
+ return ret_stuff.status;
+}
+
+static inline int
+ia64_sn_set_cpu_number(int cpu)
+{
+ struct ia64_sal_retval rv;
+
+ SAL_CALL_NOLOCK(rv, SN_SAL_SET_CPU_NUMBER, cpu, 0, 0, 0, 0, 0, 0);
+ return rv.status;
+}
+static inline int
+ia64_sn_kernel_launch_event(void)
+{
+ struct ia64_sal_retval rv;
+ SAL_CALL_NOLOCK(rv, SN_SAL_KERNEL_LAUNCH_EVENT, 0, 0, 0, 0, 0, 0, 0);
+ return rv.status;
+}
+
+union sn_watchlist_u {
+ u64 val;
+ struct {
+ u64 blade : 16,
+ size : 32,
+ filler : 16;
+ };
+};
+
+static inline int
+sn_mq_watchlist_alloc(int blade, void *mq, unsigned int mq_size,
+ unsigned long *intr_mmr_offset)
+{
+ struct ia64_sal_retval rv;
+ unsigned long addr;
+ union sn_watchlist_u size_blade;
+ int watchlist;
+
+ addr = (unsigned long)mq;
+ size_blade.size = mq_size;
+ size_blade.blade = blade;
+
+ /*
+ * bios returns watchlist number or negative error number.
+ */
+ ia64_sal_oemcall_nolock(&rv, SN_SAL_WATCHLIST_ALLOC, addr,
+ size_blade.val, (u64)intr_mmr_offset,
+ (u64)&watchlist, 0, 0, 0);
+ if (rv.status < 0)
+ return rv.status;
+
+ return watchlist;
+}
+
+static inline int
+sn_mq_watchlist_free(int blade, int watchlist_num)
+{
+ struct ia64_sal_retval rv;
+ ia64_sal_oemcall_nolock(&rv, SN_SAL_WATCHLIST_FREE, blade,
+ watchlist_num, 0, 0, 0, 0, 0);
+ return rv.status;
+}
+#endif /* _ASM_IA64_SN_SN_SAL_H */
diff --git a/kernel/arch/ia64/include/asm/sn/tioca.h b/kernel/arch/ia64/include/asm/sn/tioca.h
new file mode 100644
index 000000000..666222d7f
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/tioca.h
@@ -0,0 +1,596 @@
+#ifndef _ASM_IA64_SN_TIO_TIOCA_H
+#define _ASM_IA64_SN_TIO_TIOCA_H
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+#define TIOCA_PART_NUM 0xE020
+#define TIOCA_MFGR_NUM 0x24
+#define TIOCA_REV_A 0x1
+
+/*
+ * Register layout for TIO:CA. See below for bitmasks for each register.
+ */
+
+struct tioca {
+ u64 ca_id; /* 0x000000 */
+ u64 ca_control1; /* 0x000008 */
+ u64 ca_control2; /* 0x000010 */
+ u64 ca_status1; /* 0x000018 */
+ u64 ca_status2; /* 0x000020 */
+ u64 ca_gart_aperature; /* 0x000028 */
+ u64 ca_gfx_detach; /* 0x000030 */
+ u64 ca_inta_dest_addr; /* 0x000038 */
+ u64 ca_intb_dest_addr; /* 0x000040 */
+ u64 ca_err_int_dest_addr; /* 0x000048 */
+ u64 ca_int_status; /* 0x000050 */
+ u64 ca_int_status_alias; /* 0x000058 */
+ u64 ca_mult_error; /* 0x000060 */
+ u64 ca_mult_error_alias; /* 0x000068 */
+ u64 ca_first_error; /* 0x000070 */
+ u64 ca_int_mask; /* 0x000078 */
+ u64 ca_crm_pkterr_type; /* 0x000080 */
+ u64 ca_crm_pkterr_type_alias; /* 0x000088 */
+ u64 ca_crm_ct_error_detail_1; /* 0x000090 */
+ u64 ca_crm_ct_error_detail_2; /* 0x000098 */
+ u64 ca_crm_tnumto; /* 0x0000A0 */
+ u64 ca_gart_err; /* 0x0000A8 */
+ u64 ca_pcierr_type; /* 0x0000B0 */
+ u64 ca_pcierr_addr; /* 0x0000B8 */
+
+ u64 ca_pad_0000C0[3]; /* 0x0000{C0..D0} */
+
+ u64 ca_pci_rd_buf_flush; /* 0x0000D8 */
+ u64 ca_pci_dma_addr_extn; /* 0x0000E0 */
+ u64 ca_agp_dma_addr_extn; /* 0x0000E8 */
+ u64 ca_force_inta; /* 0x0000F0 */
+ u64 ca_force_intb; /* 0x0000F8 */
+ u64 ca_debug_vector_sel; /* 0x000100 */
+ u64 ca_debug_mux_core_sel; /* 0x000108 */
+ u64 ca_debug_mux_pci_sel; /* 0x000110 */
+ u64 ca_debug_domain_sel; /* 0x000118 */
+
+ u64 ca_pad_000120[28]; /* 0x0001{20..F8} */
+
+ u64 ca_gart_ptr_table; /* 0x200 */
+ u64 ca_gart_tlb_addr[8]; /* 0x2{08..40} */
+};
+
+/*
+ * Mask/shift definitions for TIO:CA registers. The convention here is
+ * to mainly use the names as they appear in the "TIO AEGIS Programmers'
+ * Reference" with a CA_ prefix added. Some exceptions were made to fix
+ * duplicate field names or to generalize fields that are common to
+ * different registers (ca_debug_mux_core_sel and ca_debug_mux_pci_sel for
+ * example).
+ *
+ * Fields consisting of a single bit have a single #define have a single
+ * macro declaration to mask the bit. Fields consisting of multiple bits
+ * have two declarations: one to mask the proper bits in a register, and
+ * a second with the suffix "_SHFT" to identify how far the mask needs to
+ * be shifted right to get its base value.
+ */
+
+/* ==== ca_control1 */
+#define CA_SYS_BIG_END (1ull << 0)
+#define CA_DMA_AGP_SWAP (1ull << 1)
+#define CA_DMA_PCI_SWAP (1ull << 2)
+#define CA_PIO_IO_SWAP (1ull << 3)
+#define CA_PIO_MEM_SWAP (1ull << 4)
+#define CA_GFX_WR_SWAP (1ull << 5)
+#define CA_AGP_FW_ENABLE (1ull << 6)
+#define CA_AGP_CAL_CYCLE (0x7ull << 7)
+#define CA_AGP_CAL_CYCLE_SHFT 7
+#define CA_AGP_CAL_PRSCL_BYP (1ull << 10)
+#define CA_AGP_INIT_CAL_ENB (1ull << 11)
+#define CA_INJ_ADDR_PERR (1ull << 12)
+#define CA_INJ_DATA_PERR (1ull << 13)
+ /* bits 15:14 unused */
+#define CA_PCIM_IO_NBE_AD (0x7ull << 16)
+#define CA_PCIM_IO_NBE_AD_SHFT 16
+#define CA_PCIM_FAST_BTB_ENB (1ull << 19)
+ /* bits 23:20 unused */
+#define CA_PIO_ADDR_OFFSET (0xffull << 24)
+#define CA_PIO_ADDR_OFFSET_SHFT 24
+ /* bits 35:32 unused */
+#define CA_AGPDMA_OP_COMBDELAY (0x1full << 36)
+#define CA_AGPDMA_OP_COMBDELAY_SHFT 36
+ /* bit 41 unused */
+#define CA_AGPDMA_OP_ENB_COMBDELAY (1ull << 42)
+#define CA_PCI_INT_LPCNT (0xffull << 44)
+#define CA_PCI_INT_LPCNT_SHFT 44
+ /* bits 63:52 unused */
+
+/* ==== ca_control2 */
+#define CA_AGP_LATENCY_TO (0xffull << 0)
+#define CA_AGP_LATENCY_TO_SHFT 0
+#define CA_PCI_LATENCY_TO (0xffull << 8)
+#define CA_PCI_LATENCY_TO_SHFT 8
+#define CA_PCI_MAX_RETRY (0x3ffull << 16)
+#define CA_PCI_MAX_RETRY_SHFT 16
+ /* bits 27:26 unused */
+#define CA_RT_INT_EN (0x3ull << 28)
+#define CA_RT_INT_EN_SHFT 28
+#define CA_MSI_INT_ENB (1ull << 30)
+#define CA_PCI_ARB_ERR_ENB (1ull << 31)
+#define CA_GART_MEM_PARAM (0x3ull << 32)
+#define CA_GART_MEM_PARAM_SHFT 32
+#define CA_GART_RD_PREFETCH_ENB (1ull << 34)
+#define CA_GART_WR_PREFETCH_ENB (1ull << 35)
+#define CA_GART_FLUSH_TLB (1ull << 36)
+ /* bits 39:37 unused */
+#define CA_CRM_TNUMTO_PERIOD (0x1fffull << 40)
+#define CA_CRM_TNUMTO_PERIOD_SHFT 40
+ /* bits 55:53 unused */
+#define CA_CRM_TNUMTO_ENB (1ull << 56)
+#define CA_CRM_PRESCALER_BYP (1ull << 57)
+ /* bits 59:58 unused */
+#define CA_CRM_MAX_CREDIT (0x7ull << 60)
+#define CA_CRM_MAX_CREDIT_SHFT 60
+ /* bit 63 unused */
+
+/* ==== ca_status1 */
+#define CA_CORELET_ID (0x3ull << 0)
+#define CA_CORELET_ID_SHFT 0
+#define CA_INTA_N (1ull << 2)
+#define CA_INTB_N (1ull << 3)
+#define CA_CRM_CREDIT_AVAIL (0x7ull << 4)
+#define CA_CRM_CREDIT_AVAIL_SHFT 4
+ /* bit 7 unused */
+#define CA_CRM_SPACE_AVAIL (0x7full << 8)
+#define CA_CRM_SPACE_AVAIL_SHFT 8
+ /* bit 15 unused */
+#define CA_GART_TLB_VAL (0xffull << 16)
+#define CA_GART_TLB_VAL_SHFT 16
+ /* bits 63:24 unused */
+
+/* ==== ca_status2 */
+#define CA_GFX_CREDIT_AVAIL (0xffull << 0)
+#define CA_GFX_CREDIT_AVAIL_SHFT 0
+#define CA_GFX_OPQ_AVAIL (0xffull << 8)
+#define CA_GFX_OPQ_AVAIL_SHFT 8
+#define CA_GFX_WRBUFF_AVAIL (0xffull << 16)
+#define CA_GFX_WRBUFF_AVAIL_SHFT 16
+#define CA_ADMA_OPQ_AVAIL (0xffull << 24)
+#define CA_ADMA_OPQ_AVAIL_SHFT 24
+#define CA_ADMA_WRBUFF_AVAIL (0xffull << 32)
+#define CA_ADMA_WRBUFF_AVAIL_SHFT 32
+#define CA_ADMA_RDBUFF_AVAIL (0x7full << 40)
+#define CA_ADMA_RDBUFF_AVAIL_SHFT 40
+#define CA_PCI_PIO_OP_STAT (1ull << 47)
+#define CA_PDMA_OPQ_AVAIL (0xfull << 48)
+#define CA_PDMA_OPQ_AVAIL_SHFT 48
+#define CA_PDMA_WRBUFF_AVAIL (0xfull << 52)
+#define CA_PDMA_WRBUFF_AVAIL_SHFT 52
+#define CA_PDMA_RDBUFF_AVAIL (0x3ull << 56)
+#define CA_PDMA_RDBUFF_AVAIL_SHFT 56
+ /* bits 63:58 unused */
+
+/* ==== ca_gart_aperature */
+#define CA_GART_AP_ENB_AGP (1ull << 0)
+#define CA_GART_PAGE_SIZE (1ull << 1)
+#define CA_GART_AP_ENB_PCI (1ull << 2)
+ /* bits 11:3 unused */
+#define CA_GART_AP_SIZE (0x3ffull << 12)
+#define CA_GART_AP_SIZE_SHFT 12
+#define CA_GART_AP_BASE (0x3ffffffffffull << 22)
+#define CA_GART_AP_BASE_SHFT 22
+
+/* ==== ca_inta_dest_addr
+ ==== ca_intb_dest_addr
+ ==== ca_err_int_dest_addr */
+ /* bits 2:0 unused */
+#define CA_INT_DEST_ADDR (0x7ffffffffffffull << 3)
+#define CA_INT_DEST_ADDR_SHFT 3
+ /* bits 55:54 unused */
+#define CA_INT_DEST_VECT (0xffull << 56)
+#define CA_INT_DEST_VECT_SHFT 56
+
+/* ==== ca_int_status */
+/* ==== ca_int_status_alias */
+/* ==== ca_mult_error */
+/* ==== ca_mult_error_alias */
+/* ==== ca_first_error */
+/* ==== ca_int_mask */
+#define CA_PCI_ERR (1ull << 0)
+ /* bits 3:1 unused */
+#define CA_GART_FETCH_ERR (1ull << 4)
+#define CA_GFX_WR_OVFLW (1ull << 5)
+#define CA_PIO_REQ_OVFLW (1ull << 6)
+#define CA_CRM_PKTERR (1ull << 7)
+#define CA_CRM_DVERR (1ull << 8)
+#define CA_TNUMTO (1ull << 9)
+#define CA_CXM_RSP_CRED_OVFLW (1ull << 10)
+#define CA_CXM_REQ_CRED_OVFLW (1ull << 11)
+#define CA_PIO_INVALID_ADDR (1ull << 12)
+#define CA_PCI_ARB_TO (1ull << 13)
+#define CA_AGP_REQ_OFLOW (1ull << 14)
+#define CA_SBA_TYPE1_ERR (1ull << 15)
+ /* bit 16 unused */
+#define CA_INTA (1ull << 17)
+#define CA_INTB (1ull << 18)
+#define CA_MULT_INTA (1ull << 19)
+#define CA_MULT_INTB (1ull << 20)
+#define CA_GFX_CREDIT_OVFLW (1ull << 21)
+ /* bits 63:22 unused */
+
+/* ==== ca_crm_pkterr_type */
+/* ==== ca_crm_pkterr_type_alias */
+#define CA_CRM_PKTERR_SBERR_HDR (1ull << 0)
+#define CA_CRM_PKTERR_DIDN (1ull << 1)
+#define CA_CRM_PKTERR_PACTYPE (1ull << 2)
+#define CA_CRM_PKTERR_INV_TNUM (1ull << 3)
+#define CA_CRM_PKTERR_ADDR_RNG (1ull << 4)
+#define CA_CRM_PKTERR_ADDR_ALGN (1ull << 5)
+#define CA_CRM_PKTERR_HDR_PARAM (1ull << 6)
+#define CA_CRM_PKTERR_CW_ERR (1ull << 7)
+#define CA_CRM_PKTERR_SBERR_NH (1ull << 8)
+#define CA_CRM_PKTERR_EARLY_TERM (1ull << 9)
+#define CA_CRM_PKTERR_EARLY_TAIL (1ull << 10)
+#define CA_CRM_PKTERR_MSSNG_TAIL (1ull << 11)
+#define CA_CRM_PKTERR_MSSNG_HDR (1ull << 12)
+ /* bits 15:13 unused */
+#define CA_FIRST_CRM_PKTERR_SBERR_HDR (1ull << 16)
+#define CA_FIRST_CRM_PKTERR_DIDN (1ull << 17)
+#define CA_FIRST_CRM_PKTERR_PACTYPE (1ull << 18)
+#define CA_FIRST_CRM_PKTERR_INV_TNUM (1ull << 19)
+#define CA_FIRST_CRM_PKTERR_ADDR_RNG (1ull << 20)
+#define CA_FIRST_CRM_PKTERR_ADDR_ALGN (1ull << 21)
+#define CA_FIRST_CRM_PKTERR_HDR_PARAM (1ull << 22)
+#define CA_FIRST_CRM_PKTERR_CW_ERR (1ull << 23)
+#define CA_FIRST_CRM_PKTERR_SBERR_NH (1ull << 24)
+#define CA_FIRST_CRM_PKTERR_EARLY_TERM (1ull << 25)
+#define CA_FIRST_CRM_PKTERR_EARLY_TAIL (1ull << 26)
+#define CA_FIRST_CRM_PKTERR_MSSNG_TAIL (1ull << 27)
+#define CA_FIRST_CRM_PKTERR_MSSNG_HDR (1ull << 28)
+ /* bits 63:29 unused */
+
+/* ==== ca_crm_ct_error_detail_1 */
+#define CA_PKT_TYPE (0xfull << 0)
+#define CA_PKT_TYPE_SHFT 0
+#define CA_SRC_ID (0x3ull << 4)
+#define CA_SRC_ID_SHFT 4
+#define CA_DATA_SZ (0x3ull << 6)
+#define CA_DATA_SZ_SHFT 6
+#define CA_TNUM (0xffull << 8)
+#define CA_TNUM_SHFT 8
+#define CA_DW_DATA_EN (0xffull << 16)
+#define CA_DW_DATA_EN_SHFT 16
+#define CA_GFX_CRED (0xffull << 24)
+#define CA_GFX_CRED_SHFT 24
+#define CA_MEM_RD_PARAM (0x3ull << 32)
+#define CA_MEM_RD_PARAM_SHFT 32
+#define CA_PIO_OP (1ull << 34)
+#define CA_CW_ERR (1ull << 35)
+ /* bits 62:36 unused */
+#define CA_VALID (1ull << 63)
+
+/* ==== ca_crm_ct_error_detail_2 */
+ /* bits 2:0 unused */
+#define CA_PKT_ADDR (0x1fffffffffffffull << 3)
+#define CA_PKT_ADDR_SHFT 3
+ /* bits 63:56 unused */
+
+/* ==== ca_crm_tnumto */
+#define CA_CRM_TNUMTO_VAL (0xffull << 0)
+#define CA_CRM_TNUMTO_VAL_SHFT 0
+#define CA_CRM_TNUMTO_WR (1ull << 8)
+ /* bits 63:9 unused */
+
+/* ==== ca_gart_err */
+#define CA_GART_ERR_SOURCE (0x3ull << 0)
+#define CA_GART_ERR_SOURCE_SHFT 0
+ /* bits 3:2 unused */
+#define CA_GART_ERR_ADDR (0xfffffffffull << 4)
+#define CA_GART_ERR_ADDR_SHFT 4
+ /* bits 63:40 unused */
+
+/* ==== ca_pcierr_type */
+#define CA_PCIERR_DATA (0xffffffffull << 0)
+#define CA_PCIERR_DATA_SHFT 0
+#define CA_PCIERR_ENB (0xfull << 32)
+#define CA_PCIERR_ENB_SHFT 32
+#define CA_PCIERR_CMD (0xfull << 36)
+#define CA_PCIERR_CMD_SHFT 36
+#define CA_PCIERR_A64 (1ull << 40)
+#define CA_PCIERR_SLV_SERR (1ull << 41)
+#define CA_PCIERR_SLV_WR_PERR (1ull << 42)
+#define CA_PCIERR_SLV_RD_PERR (1ull << 43)
+#define CA_PCIERR_MST_SERR (1ull << 44)
+#define CA_PCIERR_MST_WR_PERR (1ull << 45)
+#define CA_PCIERR_MST_RD_PERR (1ull << 46)
+#define CA_PCIERR_MST_MABT (1ull << 47)
+#define CA_PCIERR_MST_TABT (1ull << 48)
+#define CA_PCIERR_MST_RETRY_TOUT (1ull << 49)
+
+#define CA_PCIERR_TYPES \
+ (CA_PCIERR_A64|CA_PCIERR_SLV_SERR| \
+ CA_PCIERR_SLV_WR_PERR|CA_PCIERR_SLV_RD_PERR| \
+ CA_PCIERR_MST_SERR|CA_PCIERR_MST_WR_PERR|CA_PCIERR_MST_RD_PERR| \
+ CA_PCIERR_MST_MABT|CA_PCIERR_MST_TABT|CA_PCIERR_MST_RETRY_TOUT)
+
+ /* bits 63:50 unused */
+
+/* ==== ca_pci_dma_addr_extn */
+#define CA_UPPER_NODE_OFFSET (0x3full << 0)
+#define CA_UPPER_NODE_OFFSET_SHFT 0
+ /* bits 7:6 unused */
+#define CA_CHIPLET_ID (0x3ull << 8)
+#define CA_CHIPLET_ID_SHFT 8
+ /* bits 11:10 unused */
+#define CA_PCI_DMA_NODE_ID (0xffffull << 12)
+#define CA_PCI_DMA_NODE_ID_SHFT 12
+ /* bits 27:26 unused */
+#define CA_PCI_DMA_PIO_MEM_TYPE (1ull << 28)
+ /* bits 63:29 unused */
+
+
+/* ==== ca_agp_dma_addr_extn */
+ /* bits 19:0 unused */
+#define CA_AGP_DMA_NODE_ID (0xffffull << 20)
+#define CA_AGP_DMA_NODE_ID_SHFT 20
+ /* bits 27:26 unused */
+#define CA_AGP_DMA_PIO_MEM_TYPE (1ull << 28)
+ /* bits 63:29 unused */
+
+/* ==== ca_debug_vector_sel */
+#define CA_DEBUG_MN_VSEL (0xfull << 0)
+#define CA_DEBUG_MN_VSEL_SHFT 0
+#define CA_DEBUG_PP_VSEL (0xfull << 4)
+#define CA_DEBUG_PP_VSEL_SHFT 4
+#define CA_DEBUG_GW_VSEL (0xfull << 8)
+#define CA_DEBUG_GW_VSEL_SHFT 8
+#define CA_DEBUG_GT_VSEL (0xfull << 12)
+#define CA_DEBUG_GT_VSEL_SHFT 12
+#define CA_DEBUG_PD_VSEL (0xfull << 16)
+#define CA_DEBUG_PD_VSEL_SHFT 16
+#define CA_DEBUG_AD_VSEL (0xfull << 20)
+#define CA_DEBUG_AD_VSEL_SHFT 20
+#define CA_DEBUG_CX_VSEL (0xfull << 24)
+#define CA_DEBUG_CX_VSEL_SHFT 24
+#define CA_DEBUG_CR_VSEL (0xfull << 28)
+#define CA_DEBUG_CR_VSEL_SHFT 28
+#define CA_DEBUG_BA_VSEL (0xfull << 32)
+#define CA_DEBUG_BA_VSEL_SHFT 32
+#define CA_DEBUG_PE_VSEL (0xfull << 36)
+#define CA_DEBUG_PE_VSEL_SHFT 36
+#define CA_DEBUG_BO_VSEL (0xfull << 40)
+#define CA_DEBUG_BO_VSEL_SHFT 40
+#define CA_DEBUG_BI_VSEL (0xfull << 44)
+#define CA_DEBUG_BI_VSEL_SHFT 44
+#define CA_DEBUG_AS_VSEL (0xfull << 48)
+#define CA_DEBUG_AS_VSEL_SHFT 48
+#define CA_DEBUG_PS_VSEL (0xfull << 52)
+#define CA_DEBUG_PS_VSEL_SHFT 52
+#define CA_DEBUG_PM_VSEL (0xfull << 56)
+#define CA_DEBUG_PM_VSEL_SHFT 56
+ /* bits 63:60 unused */
+
+/* ==== ca_debug_mux_core_sel */
+/* ==== ca_debug_mux_pci_sel */
+#define CA_DEBUG_MSEL0 (0x7ull << 0)
+#define CA_DEBUG_MSEL0_SHFT 0
+ /* bit 3 unused */
+#define CA_DEBUG_NSEL0 (0x7ull << 4)
+#define CA_DEBUG_NSEL0_SHFT 4
+ /* bit 7 unused */
+#define CA_DEBUG_MSEL1 (0x7ull << 8)
+#define CA_DEBUG_MSEL1_SHFT 8
+ /* bit 11 unused */
+#define CA_DEBUG_NSEL1 (0x7ull << 12)
+#define CA_DEBUG_NSEL1_SHFT 12
+ /* bit 15 unused */
+#define CA_DEBUG_MSEL2 (0x7ull << 16)
+#define CA_DEBUG_MSEL2_SHFT 16
+ /* bit 19 unused */
+#define CA_DEBUG_NSEL2 (0x7ull << 20)
+#define CA_DEBUG_NSEL2_SHFT 20
+ /* bit 23 unused */
+#define CA_DEBUG_MSEL3 (0x7ull << 24)
+#define CA_DEBUG_MSEL3_SHFT 24
+ /* bit 27 unused */
+#define CA_DEBUG_NSEL3 (0x7ull << 28)
+#define CA_DEBUG_NSEL3_SHFT 28
+ /* bit 31 unused */
+#define CA_DEBUG_MSEL4 (0x7ull << 32)
+#define CA_DEBUG_MSEL4_SHFT 32
+ /* bit 35 unused */
+#define CA_DEBUG_NSEL4 (0x7ull << 36)
+#define CA_DEBUG_NSEL4_SHFT 36
+ /* bit 39 unused */
+#define CA_DEBUG_MSEL5 (0x7ull << 40)
+#define CA_DEBUG_MSEL5_SHFT 40
+ /* bit 43 unused */
+#define CA_DEBUG_NSEL5 (0x7ull << 44)
+#define CA_DEBUG_NSEL5_SHFT 44
+ /* bit 47 unused */
+#define CA_DEBUG_MSEL6 (0x7ull << 48)
+#define CA_DEBUG_MSEL6_SHFT 48
+ /* bit 51 unused */
+#define CA_DEBUG_NSEL6 (0x7ull << 52)
+#define CA_DEBUG_NSEL6_SHFT 52
+ /* bit 55 unused */
+#define CA_DEBUG_MSEL7 (0x7ull << 56)
+#define CA_DEBUG_MSEL7_SHFT 56
+ /* bit 59 unused */
+#define CA_DEBUG_NSEL7 (0x7ull << 60)
+#define CA_DEBUG_NSEL7_SHFT 60
+ /* bit 63 unused */
+
+
+/* ==== ca_debug_domain_sel */
+#define CA_DEBUG_DOMAIN_L (1ull << 0)
+#define CA_DEBUG_DOMAIN_H (1ull << 1)
+ /* bits 63:2 unused */
+
+/* ==== ca_gart_ptr_table */
+#define CA_GART_PTR_VAL (1ull << 0)
+ /* bits 11:1 unused */
+#define CA_GART_PTR_ADDR (0xfffffffffffull << 12)
+#define CA_GART_PTR_ADDR_SHFT 12
+ /* bits 63:56 unused */
+
+/* ==== ca_gart_tlb_addr[0-7] */
+#define CA_GART_TLB_ADDR (0xffffffffffffffull << 0)
+#define CA_GART_TLB_ADDR_SHFT 0
+ /* bits 62:56 unused */
+#define CA_GART_TLB_ENTRY_VAL (1ull << 63)
+
+/*
+ * PIO address space ranges for TIO:CA
+ */
+
+/* CA internal registers */
+#define CA_PIO_ADMIN 0x00000000
+#define CA_PIO_ADMIN_LEN 0x00010000
+
+/* GFX Write Buffer - Diagnostics */
+#define CA_PIO_GFX 0x00010000
+#define CA_PIO_GFX_LEN 0x00010000
+
+/* AGP DMA Write Buffer - Diagnostics */
+#define CA_PIO_AGP_DMAWRITE 0x00020000
+#define CA_PIO_AGP_DMAWRITE_LEN 0x00010000
+
+/* AGP DMA READ Buffer - Diagnostics */
+#define CA_PIO_AGP_DMAREAD 0x00030000
+#define CA_PIO_AGP_DMAREAD_LEN 0x00010000
+
+/* PCI Config Type 0 */
+#define CA_PIO_PCI_TYPE0_CONFIG 0x01000000
+#define CA_PIO_PCI_TYPE0_CONFIG_LEN 0x01000000
+
+/* PCI Config Type 1 */
+#define CA_PIO_PCI_TYPE1_CONFIG 0x02000000
+#define CA_PIO_PCI_TYPE1_CONFIG_LEN 0x01000000
+
+/* PCI I/O Cycles - mapped to PCI Address 0x00000000-0x04ffffff */
+#define CA_PIO_PCI_IO 0x03000000
+#define CA_PIO_PCI_IO_LEN 0x05000000
+
+/* PCI MEM Cycles - mapped to PCI with CA_PIO_ADDR_OFFSET of ca_control1 */
+/* use Fast Write if enabled and coretalk packet type is a GFX request */
+#define CA_PIO_PCI_MEM_OFFSET 0x08000000
+#define CA_PIO_PCI_MEM_OFFSET_LEN 0x08000000
+
+/* PCI MEM Cycles - mapped to PCI Address 0x00000000-0xbfffffff */
+/* use Fast Write if enabled and coretalk packet type is a GFX request */
+#define CA_PIO_PCI_MEM 0x40000000
+#define CA_PIO_PCI_MEM_LEN 0xc0000000
+
+/*
+ * DMA space
+ *
+ * The CA aperature (ie. bus address range) mapped by the GART is segmented into
+ * two parts. The lower portion of the aperature is used for mapping 32 bit
+ * PCI addresses which are managed by the dma interfaces in this file. The
+ * upper poprtion of the aperature is used for mapping 48 bit AGP addresses.
+ * The AGP portion of the aperature is managed by the agpgart_be.c driver
+ * in drivers/linux/agp. There are ca-specific hooks in that driver to
+ * manipulate the gart, but management of the AGP portion of the aperature
+ * is the responsibility of that driver.
+ *
+ * CA allows three main types of DMA mapping:
+ *
+ * PCI 64-bit Managed by this driver
+ * PCI 32-bit Managed by this driver
+ * AGP 48-bit Managed by hooks in the /dev/agpgart driver
+ *
+ * All of the above can optionally be remapped through the GART. The following
+ * table lists the combinations of addressing types and GART remapping that
+ * is currently supported by the driver (h/w supports all, s/w limits this):
+ *
+ * PCI64 PCI32 AGP48
+ * GART no yes yes
+ * Direct yes yes no
+ *
+ * GART remapping of PCI64 is not done because there is no need to. The
+ * 64 bit PCI address holds all of the information necessary to target any
+ * memory in the system.
+ *
+ * AGP48 is always mapped through the GART. Management of the AGP48 portion
+ * of the aperature is the responsibility of code in the agpgart_be driver.
+ *
+ * The non-64 bit bus address space will currently be partitioned like this:
+ *
+ * 0xffff_ffff_ffff +--------
+ * | AGP48 direct
+ * | Space managed by this driver
+ * CA_AGP_DIRECT_BASE +--------
+ * | AGP GART mapped (gfx aperature)
+ * | Space managed by /dev/agpgart driver
+ * | This range is exposed to the agpgart
+ * | driver as the "graphics aperature"
+ * CA_AGP_MAPPED_BASE +-----
+ * | PCI GART mapped
+ * | Space managed by this driver
+ * CA_PCI32_MAPPED_BASE +----
+ * | PCI32 direct
+ * | Space managed by this driver
+ * 0xC000_0000 +--------
+ * (CA_PCI32_DIRECT_BASE)
+ *
+ * The bus address range CA_PCI32_MAPPED_BASE through CA_AGP_DIRECT_BASE
+ * is what we call the CA aperature. Addresses falling in this range will
+ * be remapped using the GART.
+ *
+ * The bus address range CA_AGP_MAPPED_BASE through CA_AGP_DIRECT_BASE
+ * is what we call the graphics aperature. This is a subset of the CA
+ * aperature and is under the control of the agpgart_be driver.
+ *
+ * CA_PCI32_MAPPED_BASE, CA_AGP_MAPPED_BASE, and CA_AGP_DIRECT_BASE are
+ * somewhat arbitrary values. The known constraints on choosing these is:
+ *
+ * 1) CA_AGP_DIRECT_BASE-CA_PCI32_MAPPED_BASE+1 (the CA aperature size)
+ * must be one of the values supported by the ca_gart_aperature register.
+ * Currently valid values are: 4MB through 4096MB in powers of 2 increments
+ *
+ * 2) CA_AGP_DIRECT_BASE-CA_AGP_MAPPED_BASE+1 (the gfx aperature size)
+ * must be in MB units since that's what the agpgart driver assumes.
+ */
+
+/*
+ * Define Bus DMA ranges. These are configurable (see constraints above)
+ * and will probably need tuning based on experience.
+ */
+
+
+/*
+ * 11/24/03
+ * CA has an addressing glitch w.r.t. PCI direct 32 bit DMA that makes it
+ * generally unusable. The problem is that for PCI direct 32
+ * DMA's, all 32 bits of the bus address are used to form the lower 32 bits
+ * of the coretalk address, and coretalk bits 38:32 come from a register.
+ * Since only PCI bus addresses 0xC0000000-0xFFFFFFFF (1GB) are available
+ * for DMA (the rest is allocated to PIO), host node addresses need to be
+ * such that their lower 32 bits fall in the 0xC0000000-0xffffffff range
+ * as well. So there can be no PCI32 direct DMA below 3GB!! For this
+ * reason we set the CA_PCI32_DIRECT_SIZE to 0 which essentially makes
+ * tioca_dma_direct32() a noop but preserves the code flow should this issue
+ * be fixed in a respin.
+ *
+ * For now, all PCI32 DMA's must be mapped through the GART.
+ */
+
+#define CA_PCI32_DIRECT_BASE 0xC0000000UL /* BASE not configurable */
+#define CA_PCI32_DIRECT_SIZE 0x00000000UL /* 0 MB */
+
+#define CA_PCI32_MAPPED_BASE 0xC0000000UL
+#define CA_PCI32_MAPPED_SIZE 0x40000000UL /* 2GB */
+
+#define CA_AGP_MAPPED_BASE 0x80000000UL
+#define CA_AGP_MAPPED_SIZE 0x40000000UL /* 2GB */
+
+#define CA_AGP_DIRECT_BASE 0x40000000UL /* 2GB */
+#define CA_AGP_DIRECT_SIZE 0x40000000UL
+
+#define CA_APERATURE_BASE (CA_AGP_MAPPED_BASE)
+#define CA_APERATURE_SIZE (CA_AGP_MAPPED_SIZE+CA_PCI32_MAPPED_SIZE)
+
+#endif /* _ASM_IA64_SN_TIO_TIOCA_H */
diff --git a/kernel/arch/ia64/include/asm/sn/tioca_provider.h b/kernel/arch/ia64/include/asm/sn/tioca_provider.h
new file mode 100644
index 000000000..9a820ac61
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/tioca_provider.h
@@ -0,0 +1,207 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H
+#define _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H
+
+#include <asm/sn/tioca.h>
+
+/*
+ * WAR enables
+ * Defines for individual WARs. Each is a bitmask of applicable
+ * part revision numbers. (1 << 1) == rev A, (1 << 2) == rev B,
+ * (3 << 1) == (rev A or rev B), etc
+ */
+
+#define TIOCA_WAR_ENABLED(pv, tioca_common) \
+ ((1 << tioca_common->ca_rev) & pv)
+
+ /* TIO:ICE:FRZ:Freezer loses a PIO data ucred on PIO RD RSP with CW error */
+#define PV907908 (1 << 1)
+ /* ATI config space problems after BIOS execution starts */
+#define PV908234 (1 << 1)
+ /* CA:AGPDMA write request data mismatch with ABC1CL merge */
+#define PV895469 (1 << 1)
+ /* TIO:CA TLB invalidate of written GART entries possibly not occurring in CA*/
+#define PV910244 (1 << 1)
+
+struct tioca_dmamap{
+ struct list_head cad_list; /* headed by ca_list */
+
+ dma_addr_t cad_dma_addr; /* Linux dma handle */
+ uint cad_gart_entry; /* start entry in ca_gart_pagemap */
+ uint cad_gart_size; /* #entries for this map */
+};
+
+/*
+ * Kernel only fields. Prom may look at this stuff for debugging only.
+ * Access this structure through the ca_kernel_private ptr.
+ */
+
+struct tioca_common ;
+
+struct tioca_kernel {
+ struct tioca_common *ca_common; /* tioca this belongs to */
+ struct list_head ca_list; /* list of all ca's */
+ struct list_head ca_dmamaps;
+ spinlock_t ca_lock; /* Kernel lock */
+ cnodeid_t ca_closest_node;
+ struct list_head *ca_devices; /* bus->devices */
+
+ /*
+ * General GART stuff
+ */
+ u64 ca_ap_size; /* size of aperature in bytes */
+ u32 ca_gart_entries; /* # u64 entries in gart */
+ u32 ca_ap_pagesize; /* aperature page size in bytes */
+ u64 ca_ap_bus_base; /* bus address of CA aperature */
+ u64 ca_gart_size; /* gart size in bytes */
+ u64 *ca_gart; /* gart table vaddr */
+ u64 ca_gart_coretalk_addr; /* gart coretalk addr */
+ u8 ca_gart_iscoherent; /* used in tioca_tlbflush */
+
+ /* PCI GART convenience values */
+ u64 ca_pciap_base; /* pci aperature bus base address */
+ u64 ca_pciap_size; /* pci aperature size (bytes) */
+ u64 ca_pcigart_base; /* gfx GART bus base address */
+ u64 *ca_pcigart; /* gfx GART vm address */
+ u32 ca_pcigart_entries;
+ u32 ca_pcigart_start; /* PCI start index in ca_gart */
+ void *ca_pcigart_pagemap;
+
+ /* AGP GART convenience values */
+ u64 ca_gfxap_base; /* gfx aperature bus base address */
+ u64 ca_gfxap_size; /* gfx aperature size (bytes) */
+ u64 ca_gfxgart_base; /* gfx GART bus base address */
+ u64 *ca_gfxgart; /* gfx GART vm address */
+ u32 ca_gfxgart_entries;
+ u32 ca_gfxgart_start; /* agpgart start index in ca_gart */
+};
+
+/*
+ * Common tioca info shared between kernel and prom
+ *
+ * DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES
+ * TO THE PROM VERSION.
+ */
+
+struct tioca_common {
+ struct pcibus_bussoft ca_common; /* common pciio header */
+
+ u32 ca_rev;
+ u32 ca_closest_nasid;
+
+ u64 ca_prom_private;
+ u64 ca_kernel_private;
+};
+
+/**
+ * tioca_paddr_to_gart - Convert an SGI coretalk address to a CA GART entry
+ * @paddr: page address to convert
+ *
+ * Convert a system [coretalk] address to a GART entry. GART entries are
+ * formed using the following:
+ *
+ * data = ( (1<<63) | ( (REMAP_NODE_ID << 40) | (MD_CHIPLET_ID << 38) |
+ * (REMAP_SYS_ADDR) ) >> 12 )
+ *
+ * DATA written to 1 GART TABLE Entry in system memory is remapped system
+ * addr for 1 page
+ *
+ * The data is for coretalk address format right shifted 12 bits with a
+ * valid bit.
+ *
+ * GART_TABLE_ENTRY [ 25:0 ] -- REMAP_SYS_ADDRESS[37:12].
+ * GART_TABLE_ENTRY [ 27:26 ] -- SHUB MD chiplet id.
+ * GART_TABLE_ENTRY [ 41:28 ] -- REMAP_NODE_ID.
+ * GART_TABLE_ENTRY [ 63 ] -- Valid Bit
+ */
+static inline u64
+tioca_paddr_to_gart(unsigned long paddr)
+{
+ /*
+ * We are assuming right now that paddr already has the correct
+ * format since the address from xtalk_dmaXXX should already have
+ * NODE_ID, CHIPLET_ID, and SYS_ADDR in the correct locations.
+ */
+
+ return ((paddr) >> 12) | (1UL << 63);
+}
+
+/**
+ * tioca_physpage_to_gart - Map a host physical page for SGI CA based DMA
+ * @page_addr: system page address to map
+ */
+
+static inline unsigned long
+tioca_physpage_to_gart(u64 page_addr)
+{
+ u64 coretalk_addr;
+
+ coretalk_addr = PHYS_TO_TIODMA(page_addr);
+ if (!coretalk_addr) {
+ return 0;
+ }
+
+ return tioca_paddr_to_gart(coretalk_addr);
+}
+
+/**
+ * tioca_tlbflush - invalidate cached SGI CA GART TLB entries
+ * @tioca_kernel: CA context
+ *
+ * Invalidate tlb entries for a given CA GART. Main complexity is to account
+ * for revA bug.
+ */
+static inline void
+tioca_tlbflush(struct tioca_kernel *tioca_kernel)
+{
+ volatile u64 tmp;
+ volatile struct tioca __iomem *ca_base;
+ struct tioca_common *tioca_common;
+
+ tioca_common = tioca_kernel->ca_common;
+ ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base;
+
+ /*
+ * Explicit flushes not needed if GART is in cached mode
+ */
+ if (tioca_kernel->ca_gart_iscoherent) {
+ if (TIOCA_WAR_ENABLED(PV910244, tioca_common)) {
+ /*
+ * PV910244: RevA CA needs explicit flushes.
+ * Need to put GART into uncached mode before
+ * flushing otherwise the explicit flush is ignored.
+ *
+ * Alternate WAR would be to leave GART cached and
+ * touch every CL aligned GART entry.
+ */
+
+ __sn_clrq_relaxed(&ca_base->ca_control2, CA_GART_MEM_PARAM);
+ __sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB);
+ __sn_setq_relaxed(&ca_base->ca_control2,
+ (0x2ull << CA_GART_MEM_PARAM_SHFT));
+ tmp = __sn_readq_relaxed(&ca_base->ca_control2);
+ }
+
+ return;
+ }
+
+ /*
+ * Gart in uncached mode ... need an explicit flush.
+ */
+
+ __sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB);
+ tmp = __sn_readq_relaxed(&ca_base->ca_control2);
+}
+
+extern u32 tioca_gart_found;
+extern struct list_head tioca_list;
+extern int tioca_init_provider(void);
+extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern);
+#endif /* _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H */
diff --git a/kernel/arch/ia64/include/asm/sn/tioce.h b/kernel/arch/ia64/include/asm/sn/tioce.h
new file mode 100644
index 000000000..6eae8ada9
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/tioce.h
@@ -0,0 +1,760 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_IA64_SN_TIOCE_H__
+#define __ASM_IA64_SN_TIOCE_H__
+
+/* CE ASIC part & mfgr information */
+#define TIOCE_PART_NUM 0xCE00
+#define TIOCE_SRC_ID 0x01
+#define TIOCE_REV_A 0x1
+
+/* CE Virtual PPB Vendor/Device IDs */
+#define CE_VIRT_PPB_VENDOR_ID 0x10a9
+#define CE_VIRT_PPB_DEVICE_ID 0x4002
+
+/* CE Host Bridge Vendor/Device IDs */
+#define CE_HOST_BRIDGE_VENDOR_ID 0x10a9
+#define CE_HOST_BRIDGE_DEVICE_ID 0x4001
+
+
+#define TIOCE_NUM_M40_ATES 4096
+#define TIOCE_NUM_M3240_ATES 2048
+#define TIOCE_NUM_PORTS 2
+
+/*
+ * Register layout for TIOCE. MMR offsets are shown at the far right of the
+ * structure definition.
+ */
+typedef volatile struct tioce {
+ /*
+ * ADMIN : Administration Registers
+ */
+ u64 ce_adm_id; /* 0x000000 */
+ u64 ce_pad_000008; /* 0x000008 */
+ u64 ce_adm_dyn_credit_status; /* 0x000010 */
+ u64 ce_adm_last_credit_status; /* 0x000018 */
+ u64 ce_adm_credit_limit; /* 0x000020 */
+ u64 ce_adm_force_credit; /* 0x000028 */
+ u64 ce_adm_control; /* 0x000030 */
+ u64 ce_adm_mmr_chn_timeout; /* 0x000038 */
+ u64 ce_adm_ssp_ure_timeout; /* 0x000040 */
+ u64 ce_adm_ssp_dre_timeout; /* 0x000048 */
+ u64 ce_adm_ssp_debug_sel; /* 0x000050 */
+ u64 ce_adm_int_status; /* 0x000058 */
+ u64 ce_adm_int_status_alias; /* 0x000060 */
+ u64 ce_adm_int_mask; /* 0x000068 */
+ u64 ce_adm_int_pending; /* 0x000070 */
+ u64 ce_adm_force_int; /* 0x000078 */
+ u64 ce_adm_ure_ups_buf_barrier_flush; /* 0x000080 */
+ u64 ce_adm_int_dest[15]; /* 0x000088 -- 0x0000F8 */
+ u64 ce_adm_error_summary; /* 0x000100 */
+ u64 ce_adm_error_summary_alias; /* 0x000108 */
+ u64 ce_adm_error_mask; /* 0x000110 */
+ u64 ce_adm_first_error; /* 0x000118 */
+ u64 ce_adm_error_overflow; /* 0x000120 */
+ u64 ce_adm_error_overflow_alias; /* 0x000128 */
+ u64 ce_pad_000130[2]; /* 0x000130 -- 0x000138 */
+ u64 ce_adm_tnum_error; /* 0x000140 */
+ u64 ce_adm_mmr_err_detail; /* 0x000148 */
+ u64 ce_adm_msg_sram_perr_detail; /* 0x000150 */
+ u64 ce_adm_bap_sram_perr_detail; /* 0x000158 */
+ u64 ce_adm_ce_sram_perr_detail; /* 0x000160 */
+ u64 ce_adm_ce_credit_oflow_detail; /* 0x000168 */
+ u64 ce_adm_tx_link_idle_max_timer; /* 0x000170 */
+ u64 ce_adm_pcie_debug_sel; /* 0x000178 */
+ u64 ce_pad_000180[16]; /* 0x000180 -- 0x0001F8 */
+
+ u64 ce_adm_pcie_debug_sel_top; /* 0x000200 */
+ u64 ce_adm_pcie_debug_lat_sel_lo_top; /* 0x000208 */
+ u64 ce_adm_pcie_debug_lat_sel_hi_top; /* 0x000210 */
+ u64 ce_adm_pcie_debug_trig_sel_top; /* 0x000218 */
+ u64 ce_adm_pcie_debug_trig_lat_sel_lo_top; /* 0x000220 */
+ u64 ce_adm_pcie_debug_trig_lat_sel_hi_top; /* 0x000228 */
+ u64 ce_adm_pcie_trig_compare_top; /* 0x000230 */
+ u64 ce_adm_pcie_trig_compare_en_top; /* 0x000238 */
+ u64 ce_adm_ssp_debug_sel_top; /* 0x000240 */
+ u64 ce_adm_ssp_debug_lat_sel_lo_top; /* 0x000248 */
+ u64 ce_adm_ssp_debug_lat_sel_hi_top; /* 0x000250 */
+ u64 ce_adm_ssp_debug_trig_sel_top; /* 0x000258 */
+ u64 ce_adm_ssp_debug_trig_lat_sel_lo_top; /* 0x000260 */
+ u64 ce_adm_ssp_debug_trig_lat_sel_hi_top; /* 0x000268 */
+ u64 ce_adm_ssp_trig_compare_top; /* 0x000270 */
+ u64 ce_adm_ssp_trig_compare_en_top; /* 0x000278 */
+ u64 ce_pad_000280[48]; /* 0x000280 -- 0x0003F8 */
+
+ u64 ce_adm_bap_ctrl; /* 0x000400 */
+ u64 ce_pad_000408[127]; /* 0x000408 -- 0x0007F8 */
+
+ u64 ce_msg_buf_data63_0[35]; /* 0x000800 -- 0x000918 */
+ u64 ce_pad_000920[29]; /* 0x000920 -- 0x0009F8 */
+
+ u64 ce_msg_buf_data127_64[35]; /* 0x000A00 -- 0x000B18 */
+ u64 ce_pad_000B20[29]; /* 0x000B20 -- 0x000BF8 */
+
+ u64 ce_msg_buf_parity[35]; /* 0x000C00 -- 0x000D18 */
+ u64 ce_pad_000D20[29]; /* 0x000D20 -- 0x000DF8 */
+
+ u64 ce_pad_000E00[576]; /* 0x000E00 -- 0x001FF8 */
+
+ /*
+ * LSI : LSI's PCI Express Link Registers (Link#1 and Link#2)
+ * Link#1 MMRs at start at 0x002000, Link#2 MMRs at 0x003000
+ * NOTE: the comment offsets at far right: let 'z' = {2 or 3}
+ */
+ #define ce_lsi(link_num) ce_lsi[link_num-1]
+ struct ce_lsi_reg {
+ u64 ce_lsi_lpu_id; /* 0x00z000 */
+ u64 ce_lsi_rst; /* 0x00z008 */
+ u64 ce_lsi_dbg_stat; /* 0x00z010 */
+ u64 ce_lsi_dbg_cfg; /* 0x00z018 */
+ u64 ce_lsi_ltssm_ctrl; /* 0x00z020 */
+ u64 ce_lsi_lk_stat; /* 0x00z028 */
+ u64 ce_pad_00z030[2]; /* 0x00z030 -- 0x00z038 */
+ u64 ce_lsi_int_and_stat; /* 0x00z040 */
+ u64 ce_lsi_int_mask; /* 0x00z048 */
+ u64 ce_pad_00z050[22]; /* 0x00z050 -- 0x00z0F8 */
+ u64 ce_lsi_lk_perf_cnt_sel; /* 0x00z100 */
+ u64 ce_pad_00z108; /* 0x00z108 */
+ u64 ce_lsi_lk_perf_cnt_ctrl; /* 0x00z110 */
+ u64 ce_pad_00z118; /* 0x00z118 */
+ u64 ce_lsi_lk_perf_cnt1; /* 0x00z120 */
+ u64 ce_lsi_lk_perf_cnt1_test; /* 0x00z128 */
+ u64 ce_lsi_lk_perf_cnt2; /* 0x00z130 */
+ u64 ce_lsi_lk_perf_cnt2_test; /* 0x00z138 */
+ u64 ce_pad_00z140[24]; /* 0x00z140 -- 0x00z1F8 */
+ u64 ce_lsi_lk_lyr_cfg; /* 0x00z200 */
+ u64 ce_lsi_lk_lyr_status; /* 0x00z208 */
+ u64 ce_lsi_lk_lyr_int_stat; /* 0x00z210 */
+ u64 ce_lsi_lk_ly_int_stat_test; /* 0x00z218 */
+ u64 ce_lsi_lk_ly_int_stat_mask; /* 0x00z220 */
+ u64 ce_pad_00z228[3]; /* 0x00z228 -- 0x00z238 */
+ u64 ce_lsi_fc_upd_ctl; /* 0x00z240 */
+ u64 ce_pad_00z248[3]; /* 0x00z248 -- 0x00z258 */
+ u64 ce_lsi_flw_ctl_upd_to_timer; /* 0x00z260 */
+ u64 ce_lsi_flw_ctl_upd_timer0; /* 0x00z268 */
+ u64 ce_lsi_flw_ctl_upd_timer1; /* 0x00z270 */
+ u64 ce_pad_00z278[49]; /* 0x00z278 -- 0x00z3F8 */
+ u64 ce_lsi_freq_nak_lat_thrsh; /* 0x00z400 */
+ u64 ce_lsi_ack_nak_lat_tmr; /* 0x00z408 */
+ u64 ce_lsi_rply_tmr_thr; /* 0x00z410 */
+ u64 ce_lsi_rply_tmr; /* 0x00z418 */
+ u64 ce_lsi_rply_num_stat; /* 0x00z420 */
+ u64 ce_lsi_rty_buf_max_addr; /* 0x00z428 */
+ u64 ce_lsi_rty_fifo_ptr; /* 0x00z430 */
+ u64 ce_lsi_rty_fifo_rd_wr_ptr; /* 0x00z438 */
+ u64 ce_lsi_rty_fifo_cred; /* 0x00z440 */
+ u64 ce_lsi_seq_cnt; /* 0x00z448 */
+ u64 ce_lsi_ack_sent_seq_num; /* 0x00z450 */
+ u64 ce_lsi_seq_cnt_fifo_max_addr; /* 0x00z458 */
+ u64 ce_lsi_seq_cnt_fifo_ptr; /* 0x00z460 */
+ u64 ce_lsi_seq_cnt_rd_wr_ptr; /* 0x00z468 */
+ u64 ce_lsi_tx_lk_ts_ctl; /* 0x00z470 */
+ u64 ce_pad_00z478; /* 0x00z478 */
+ u64 ce_lsi_mem_addr_ctl; /* 0x00z480 */
+ u64 ce_lsi_mem_d_ld0; /* 0x00z488 */
+ u64 ce_lsi_mem_d_ld1; /* 0x00z490 */
+ u64 ce_lsi_mem_d_ld2; /* 0x00z498 */
+ u64 ce_lsi_mem_d_ld3; /* 0x00z4A0 */
+ u64 ce_lsi_mem_d_ld4; /* 0x00z4A8 */
+ u64 ce_pad_00z4B0[2]; /* 0x00z4B0 -- 0x00z4B8 */
+ u64 ce_lsi_rty_d_cnt; /* 0x00z4C0 */
+ u64 ce_lsi_seq_buf_cnt; /* 0x00z4C8 */
+ u64 ce_lsi_seq_buf_bt_d; /* 0x00z4D0 */
+ u64 ce_pad_00z4D8; /* 0x00z4D8 */
+ u64 ce_lsi_ack_lat_thr; /* 0x00z4E0 */
+ u64 ce_pad_00z4E8[3]; /* 0x00z4E8 -- 0x00z4F8 */
+ u64 ce_lsi_nxt_rcv_seq_1_cntr; /* 0x00z500 */
+ u64 ce_lsi_unsp_dllp_rcvd; /* 0x00z508 */
+ u64 ce_lsi_rcv_lk_ts_ctl; /* 0x00z510 */
+ u64 ce_pad_00z518[29]; /* 0x00z518 -- 0x00z5F8 */
+ u64 ce_lsi_phy_lyr_cfg; /* 0x00z600 */
+ u64 ce_pad_00z608; /* 0x00z608 */
+ u64 ce_lsi_phy_lyr_int_stat; /* 0x00z610 */
+ u64 ce_lsi_phy_lyr_int_stat_test; /* 0x00z618 */
+ u64 ce_lsi_phy_lyr_int_mask; /* 0x00z620 */
+ u64 ce_pad_00z628[11]; /* 0x00z628 -- 0x00z678 */
+ u64 ce_lsi_rcv_phy_cfg; /* 0x00z680 */
+ u64 ce_lsi_rcv_phy_stat1; /* 0x00z688 */
+ u64 ce_lsi_rcv_phy_stat2; /* 0x00z690 */
+ u64 ce_lsi_rcv_phy_stat3; /* 0x00z698 */
+ u64 ce_lsi_rcv_phy_int_stat; /* 0x00z6A0 */
+ u64 ce_lsi_rcv_phy_int_stat_test; /* 0x00z6A8 */
+ u64 ce_lsi_rcv_phy_int_mask; /* 0x00z6B0 */
+ u64 ce_pad_00z6B8[9]; /* 0x00z6B8 -- 0x00z6F8 */
+ u64 ce_lsi_tx_phy_cfg; /* 0x00z700 */
+ u64 ce_lsi_tx_phy_stat; /* 0x00z708 */
+ u64 ce_lsi_tx_phy_int_stat; /* 0x00z710 */
+ u64 ce_lsi_tx_phy_int_stat_test; /* 0x00z718 */
+ u64 ce_lsi_tx_phy_int_mask; /* 0x00z720 */
+ u64 ce_lsi_tx_phy_stat2; /* 0x00z728 */
+ u64 ce_pad_00z730[10]; /* 0x00z730 -- 0x00z77F */
+ u64 ce_lsi_ltssm_cfg1; /* 0x00z780 */
+ u64 ce_lsi_ltssm_cfg2; /* 0x00z788 */
+ u64 ce_lsi_ltssm_cfg3; /* 0x00z790 */
+ u64 ce_lsi_ltssm_cfg4; /* 0x00z798 */
+ u64 ce_lsi_ltssm_cfg5; /* 0x00z7A0 */
+ u64 ce_lsi_ltssm_stat1; /* 0x00z7A8 */
+ u64 ce_lsi_ltssm_stat2; /* 0x00z7B0 */
+ u64 ce_lsi_ltssm_int_stat; /* 0x00z7B8 */
+ u64 ce_lsi_ltssm_int_stat_test; /* 0x00z7C0 */
+ u64 ce_lsi_ltssm_int_mask; /* 0x00z7C8 */
+ u64 ce_lsi_ltssm_stat_wr_en; /* 0x00z7D0 */
+ u64 ce_pad_00z7D8[5]; /* 0x00z7D8 -- 0x00z7F8 */
+ u64 ce_lsi_gb_cfg1; /* 0x00z800 */
+ u64 ce_lsi_gb_cfg2; /* 0x00z808 */
+ u64 ce_lsi_gb_cfg3; /* 0x00z810 */
+ u64 ce_lsi_gb_cfg4; /* 0x00z818 */
+ u64 ce_lsi_gb_stat; /* 0x00z820 */
+ u64 ce_lsi_gb_int_stat; /* 0x00z828 */
+ u64 ce_lsi_gb_int_stat_test; /* 0x00z830 */
+ u64 ce_lsi_gb_int_mask; /* 0x00z838 */
+ u64 ce_lsi_gb_pwr_dn1; /* 0x00z840 */
+ u64 ce_lsi_gb_pwr_dn2; /* 0x00z848 */
+ u64 ce_pad_00z850[246]; /* 0x00z850 -- 0x00zFF8 */
+ } ce_lsi[2];
+
+ u64 ce_pad_004000[10]; /* 0x004000 -- 0x004048 */
+
+ /*
+ * CRM: Coretalk Receive Module Registers
+ */
+ u64 ce_crm_debug_mux; /* 0x004050 */
+ u64 ce_pad_004058; /* 0x004058 */
+ u64 ce_crm_ssp_err_cmd_wrd; /* 0x004060 */
+ u64 ce_crm_ssp_err_addr; /* 0x004068 */
+ u64 ce_crm_ssp_err_syn; /* 0x004070 */
+
+ u64 ce_pad_004078[499]; /* 0x004078 -- 0x005008 */
+
+ /*
+ * CXM: Coretalk Xmit Module Registers
+ */
+ u64 ce_cxm_dyn_credit_status; /* 0x005010 */
+ u64 ce_cxm_last_credit_status; /* 0x005018 */
+ u64 ce_cxm_credit_limit; /* 0x005020 */
+ u64 ce_cxm_force_credit; /* 0x005028 */
+ u64 ce_cxm_disable_bypass; /* 0x005030 */
+ u64 ce_pad_005038[3]; /* 0x005038 -- 0x005048 */
+ u64 ce_cxm_debug_mux; /* 0x005050 */
+
+ u64 ce_pad_005058[501]; /* 0x005058 -- 0x005FF8 */
+
+ /*
+ * DTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
+ * DTL: Link#1 MMRs at start at 0x006000, Link#2 MMRs at 0x008000
+ * DTL: the comment offsets at far right: let 'y' = {6 or 8}
+ *
+ * UTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
+ * UTL: Link#1 MMRs at start at 0x007000, Link#2 MMRs at 0x009000
+ * UTL: the comment offsets at far right: let 'z' = {7 or 9}
+ */
+ #define ce_dtl(link_num) ce_dtl_utl[link_num-1]
+ #define ce_utl(link_num) ce_dtl_utl[link_num-1]
+ struct ce_dtl_utl_reg {
+ /* DTL */
+ u64 ce_dtl_dtdr_credit_limit; /* 0x00y000 */
+ u64 ce_dtl_dtdr_credit_force; /* 0x00y008 */
+ u64 ce_dtl_dyn_credit_status; /* 0x00y010 */
+ u64 ce_dtl_dtl_last_credit_stat; /* 0x00y018 */
+ u64 ce_dtl_dtl_ctrl; /* 0x00y020 */
+ u64 ce_pad_00y028[5]; /* 0x00y028 -- 0x00y048 */
+ u64 ce_dtl_debug_sel; /* 0x00y050 */
+ u64 ce_pad_00y058[501]; /* 0x00y058 -- 0x00yFF8 */
+
+ /* UTL */
+ u64 ce_utl_utl_ctrl; /* 0x00z000 */
+ u64 ce_utl_debug_sel; /* 0x00z008 */
+ u64 ce_pad_00z010[510]; /* 0x00z010 -- 0x00zFF8 */
+ } ce_dtl_utl[2];
+
+ u64 ce_pad_00A000[514]; /* 0x00A000 -- 0x00B008 */
+
+ /*
+ * URE: Upstream Request Engine
+ */
+ u64 ce_ure_dyn_credit_status; /* 0x00B010 */
+ u64 ce_ure_last_credit_status; /* 0x00B018 */
+ u64 ce_ure_credit_limit; /* 0x00B020 */
+ u64 ce_pad_00B028; /* 0x00B028 */
+ u64 ce_ure_control; /* 0x00B030 */
+ u64 ce_ure_status; /* 0x00B038 */
+ u64 ce_pad_00B040[2]; /* 0x00B040 -- 0x00B048 */
+ u64 ce_ure_debug_sel; /* 0x00B050 */
+ u64 ce_ure_pcie_debug_sel; /* 0x00B058 */
+ u64 ce_ure_ssp_err_cmd_wrd; /* 0x00B060 */
+ u64 ce_ure_ssp_err_addr; /* 0x00B068 */
+ u64 ce_ure_page_map; /* 0x00B070 */
+ u64 ce_ure_dir_map[TIOCE_NUM_PORTS]; /* 0x00B078 */
+ u64 ce_ure_pipe_sel1; /* 0x00B088 */
+ u64 ce_ure_pipe_mask1; /* 0x00B090 */
+ u64 ce_ure_pipe_sel2; /* 0x00B098 */
+ u64 ce_ure_pipe_mask2; /* 0x00B0A0 */
+ u64 ce_ure_pcie1_credits_sent; /* 0x00B0A8 */
+ u64 ce_ure_pcie1_credits_used; /* 0x00B0B0 */
+ u64 ce_ure_pcie1_credit_limit; /* 0x00B0B8 */
+ u64 ce_ure_pcie2_credits_sent; /* 0x00B0C0 */
+ u64 ce_ure_pcie2_credits_used; /* 0x00B0C8 */
+ u64 ce_ure_pcie2_credit_limit; /* 0x00B0D0 */
+ u64 ce_ure_pcie_force_credit; /* 0x00B0D8 */
+ u64 ce_ure_rd_tnum_val; /* 0x00B0E0 */
+ u64 ce_ure_rd_tnum_rsp_rcvd; /* 0x00B0E8 */
+ u64 ce_ure_rd_tnum_esent_timer; /* 0x00B0F0 */
+ u64 ce_ure_rd_tnum_error; /* 0x00B0F8 */
+ u64 ce_ure_rd_tnum_first_cl; /* 0x00B100 */
+ u64 ce_ure_rd_tnum_link_buf; /* 0x00B108 */
+ u64 ce_ure_wr_tnum_val; /* 0x00B110 */
+ u64 ce_ure_sram_err_addr0; /* 0x00B118 */
+ u64 ce_ure_sram_err_addr1; /* 0x00B120 */
+ u64 ce_ure_sram_err_addr2; /* 0x00B128 */
+ u64 ce_ure_sram_rd_addr0; /* 0x00B130 */
+ u64 ce_ure_sram_rd_addr1; /* 0x00B138 */
+ u64 ce_ure_sram_rd_addr2; /* 0x00B140 */
+ u64 ce_ure_sram_wr_addr0; /* 0x00B148 */
+ u64 ce_ure_sram_wr_addr1; /* 0x00B150 */
+ u64 ce_ure_sram_wr_addr2; /* 0x00B158 */
+ u64 ce_ure_buf_flush10; /* 0x00B160 */
+ u64 ce_ure_buf_flush11; /* 0x00B168 */
+ u64 ce_ure_buf_flush12; /* 0x00B170 */
+ u64 ce_ure_buf_flush13; /* 0x00B178 */
+ u64 ce_ure_buf_flush20; /* 0x00B180 */
+ u64 ce_ure_buf_flush21; /* 0x00B188 */
+ u64 ce_ure_buf_flush22; /* 0x00B190 */
+ u64 ce_ure_buf_flush23; /* 0x00B198 */
+ u64 ce_ure_pcie_control1; /* 0x00B1A0 */
+ u64 ce_ure_pcie_control2; /* 0x00B1A8 */
+
+ u64 ce_pad_00B1B0[458]; /* 0x00B1B0 -- 0x00BFF8 */
+
+ /* Upstream Data Buffer, Port1 */
+ struct ce_ure_maint_ups_dat1_data {
+ u64 data63_0[512]; /* 0x00C000 -- 0x00CFF8 */
+ u64 data127_64[512]; /* 0x00D000 -- 0x00DFF8 */
+ u64 parity[512]; /* 0x00E000 -- 0x00EFF8 */
+ } ce_ure_maint_ups_dat1;
+
+ /* Upstream Header Buffer, Port1 */
+ struct ce_ure_maint_ups_hdr1_data {
+ u64 data63_0[512]; /* 0x00F000 -- 0x00FFF8 */
+ u64 data127_64[512]; /* 0x010000 -- 0x010FF8 */
+ u64 parity[512]; /* 0x011000 -- 0x011FF8 */
+ } ce_ure_maint_ups_hdr1;
+
+ /* Upstream Data Buffer, Port2 */
+ struct ce_ure_maint_ups_dat2_data {
+ u64 data63_0[512]; /* 0x012000 -- 0x012FF8 */
+ u64 data127_64[512]; /* 0x013000 -- 0x013FF8 */
+ u64 parity[512]; /* 0x014000 -- 0x014FF8 */
+ } ce_ure_maint_ups_dat2;
+
+ /* Upstream Header Buffer, Port2 */
+ struct ce_ure_maint_ups_hdr2_data {
+ u64 data63_0[512]; /* 0x015000 -- 0x015FF8 */
+ u64 data127_64[512]; /* 0x016000 -- 0x016FF8 */
+ u64 parity[512]; /* 0x017000 -- 0x017FF8 */
+ } ce_ure_maint_ups_hdr2;
+
+ /* Downstream Data Buffer */
+ struct ce_ure_maint_dns_dat_data {
+ u64 data63_0[512]; /* 0x018000 -- 0x018FF8 */
+ u64 data127_64[512]; /* 0x019000 -- 0x019FF8 */
+ u64 parity[512]; /* 0x01A000 -- 0x01AFF8 */
+ } ce_ure_maint_dns_dat;
+
+ /* Downstream Header Buffer */
+ struct ce_ure_maint_dns_hdr_data {
+ u64 data31_0[64]; /* 0x01B000 -- 0x01B1F8 */
+ u64 data95_32[64]; /* 0x01B200 -- 0x01B3F8 */
+ u64 parity[64]; /* 0x01B400 -- 0x01B5F8 */
+ } ce_ure_maint_dns_hdr;
+
+ /* RCI Buffer Data */
+ struct ce_ure_maint_rci_data {
+ u64 data41_0[64]; /* 0x01B600 -- 0x01B7F8 */
+ u64 data69_42[64]; /* 0x01B800 -- 0x01B9F8 */
+ } ce_ure_maint_rci;
+
+ /* Response Queue */
+ u64 ce_ure_maint_rspq[64]; /* 0x01BA00 -- 0x01BBF8 */
+
+ u64 ce_pad_01C000[4224]; /* 0x01BC00 -- 0x023FF8 */
+
+ /* Admin Build-a-Packet Buffer */
+ struct ce_adm_maint_bap_buf_data {
+ u64 data63_0[258]; /* 0x024000 -- 0x024808 */
+ u64 data127_64[258]; /* 0x024810 -- 0x025018 */
+ u64 parity[258]; /* 0x025020 -- 0x025828 */
+ } ce_adm_maint_bap_buf;
+
+ u64 ce_pad_025830[5370]; /* 0x025830 -- 0x02FFF8 */
+
+ /* URE: 40bit PMU ATE Buffer */ /* 0x030000 -- 0x037FF8 */
+ u64 ce_ure_ate40[TIOCE_NUM_M40_ATES];
+
+ /* URE: 32/40bit PMU ATE Buffer */ /* 0x038000 -- 0x03BFF8 */
+ u64 ce_ure_ate3240[TIOCE_NUM_M3240_ATES];
+
+ u64 ce_pad_03C000[2050]; /* 0x03C000 -- 0x040008 */
+
+ /*
+ * DRE: Down Stream Request Engine
+ */
+ u64 ce_dre_dyn_credit_status1; /* 0x040010 */
+ u64 ce_dre_dyn_credit_status2; /* 0x040018 */
+ u64 ce_dre_last_credit_status1; /* 0x040020 */
+ u64 ce_dre_last_credit_status2; /* 0x040028 */
+ u64 ce_dre_credit_limit1; /* 0x040030 */
+ u64 ce_dre_credit_limit2; /* 0x040038 */
+ u64 ce_dre_force_credit1; /* 0x040040 */
+ u64 ce_dre_force_credit2; /* 0x040048 */
+ u64 ce_dre_debug_mux1; /* 0x040050 */
+ u64 ce_dre_debug_mux2; /* 0x040058 */
+ u64 ce_dre_ssp_err_cmd_wrd; /* 0x040060 */
+ u64 ce_dre_ssp_err_addr; /* 0x040068 */
+ u64 ce_dre_comp_err_cmd_wrd; /* 0x040070 */
+ u64 ce_dre_comp_err_addr; /* 0x040078 */
+ u64 ce_dre_req_status; /* 0x040080 */
+ u64 ce_dre_config1; /* 0x040088 */
+ u64 ce_dre_config2; /* 0x040090 */
+ u64 ce_dre_config_req_status; /* 0x040098 */
+ u64 ce_pad_0400A0[12]; /* 0x0400A0 -- 0x0400F8 */
+ u64 ce_dre_dyn_fifo; /* 0x040100 */
+ u64 ce_pad_040108[3]; /* 0x040108 -- 0x040118 */
+ u64 ce_dre_last_fifo; /* 0x040120 */
+
+ u64 ce_pad_040128[27]; /* 0x040128 -- 0x0401F8 */
+
+ /* DRE Downstream Head Queue */
+ struct ce_dre_maint_ds_head_queue {
+ u64 data63_0[32]; /* 0x040200 -- 0x0402F8 */
+ u64 data127_64[32]; /* 0x040300 -- 0x0403F8 */
+ u64 parity[32]; /* 0x040400 -- 0x0404F8 */
+ } ce_dre_maint_ds_head_q;
+
+ u64 ce_pad_040500[352]; /* 0x040500 -- 0x040FF8 */
+
+ /* DRE Downstream Data Queue */
+ struct ce_dre_maint_ds_data_queue {
+ u64 data63_0[256]; /* 0x041000 -- 0x0417F8 */
+ u64 ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */
+ u64 data127_64[256]; /* 0x042000 -- 0x0427F8 */
+ u64 ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */
+ u64 parity[256]; /* 0x043000 -- 0x0437F8 */
+ u64 ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */
+ } ce_dre_maint_ds_data_q;
+
+ /* DRE URE Upstream Response Queue */
+ struct ce_dre_maint_ure_us_rsp_queue {
+ u64 data63_0[8]; /* 0x044000 -- 0x044038 */
+ u64 ce_pad_044040[24]; /* 0x044040 -- 0x0440F8 */
+ u64 data127_64[8]; /* 0x044100 -- 0x044138 */
+ u64 ce_pad_044140[24]; /* 0x044140 -- 0x0441F8 */
+ u64 parity[8]; /* 0x044200 -- 0x044238 */
+ u64 ce_pad_044240[24]; /* 0x044240 -- 0x0442F8 */
+ } ce_dre_maint_ure_us_rsp_q;
+
+ u64 ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */
+
+ u64 ce_end_of_struct; /* 0x044400 */
+} tioce_t;
+
+/* ce_lsiX_gb_cfg1 register bit masks & shifts */
+#define CE_LSI_GB_CFG1_RXL0S_THS_SHFT 0
+#define CE_LSI_GB_CFG1_RXL0S_THS_MASK (0xffULL << 0)
+#define CE_LSI_GB_CFG1_RXL0S_SMP_SHFT 8
+#define CE_LSI_GB_CFG1_RXL0S_SMP_MASK (0xfULL << 8)
+#define CE_LSI_GB_CFG1_RXL0S_ADJ_SHFT 12
+#define CE_LSI_GB_CFG1_RXL0S_ADJ_MASK (0x7ULL << 12)
+#define CE_LSI_GB_CFG1_RXL0S_FLT_SHFT 15
+#define CE_LSI_GB_CFG1_RXL0S_FLT_MASK (0x1ULL << 15)
+#define CE_LSI_GB_CFG1_LPBK_SEL_SHFT 16
+#define CE_LSI_GB_CFG1_LPBK_SEL_MASK (0x3ULL << 16)
+#define CE_LSI_GB_CFG1_LPBK_EN_SHFT 18
+#define CE_LSI_GB_CFG1_LPBK_EN_MASK (0x1ULL << 18)
+#define CE_LSI_GB_CFG1_RVRS_LB_SHFT 19
+#define CE_LSI_GB_CFG1_RVRS_LB_MASK (0x1ULL << 19)
+#define CE_LSI_GB_CFG1_RVRS_CLK_SHFT 20
+#define CE_LSI_GB_CFG1_RVRS_CLK_MASK (0x3ULL << 20)
+#define CE_LSI_GB_CFG1_SLF_TS_SHFT 24
+#define CE_LSI_GB_CFG1_SLF_TS_MASK (0xfULL << 24)
+
+/* ce_adm_int_mask/ce_adm_int_status register bit defines */
+#define CE_ADM_INT_CE_ERROR_SHFT 0
+#define CE_ADM_INT_LSI1_IP_ERROR_SHFT 1
+#define CE_ADM_INT_LSI2_IP_ERROR_SHFT 2
+#define CE_ADM_INT_PCIE_ERROR_SHFT 3
+#define CE_ADM_INT_PORT1_HOTPLUG_EVENT_SHFT 4
+#define CE_ADM_INT_PORT2_HOTPLUG_EVENT_SHFT 5
+#define CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT 6
+#define CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT 7
+#define CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT 8
+#define CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT 9
+#define CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT 10
+#define CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT 11
+#define CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT 12
+#define CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT 13
+#define CE_ADM_INT_PCIE_MSG_SHFT 14 /*see int_dest_14*/
+#define CE_ADM_INT_PCIE_MSG_SLOT_0_SHFT 14
+#define CE_ADM_INT_PCIE_MSG_SLOT_1_SHFT 15
+#define CE_ADM_INT_PCIE_MSG_SLOT_2_SHFT 16
+#define CE_ADM_INT_PCIE_MSG_SLOT_3_SHFT 17
+#define CE_ADM_INT_PORT1_PM_PME_MSG_SHFT 22
+#define CE_ADM_INT_PORT2_PM_PME_MSG_SHFT 23
+
+/* ce_adm_force_int register bit defines */
+#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT 0
+#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT 1
+#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT 2
+#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT 3
+#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT 4
+#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT 5
+#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT 6
+#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT 7
+#define CE_ADM_FORCE_INT_ALWAYS_SHFT 8
+
+/* ce_adm_int_dest register bit masks & shifts */
+#define INTR_VECTOR_SHFT 56
+
+/* ce_adm_error_mask and ce_adm_error_summary register bit masks */
+#define CE_ADM_ERR_CRM_SSP_REQ_INVALID (0x1ULL << 0)
+#define CE_ADM_ERR_SSP_REQ_HEADER (0x1ULL << 1)
+#define CE_ADM_ERR_SSP_RSP_HEADER (0x1ULL << 2)
+#define CE_ADM_ERR_SSP_PROTOCOL_ERROR (0x1ULL << 3)
+#define CE_ADM_ERR_SSP_SBE (0x1ULL << 4)
+#define CE_ADM_ERR_SSP_MBE (0x1ULL << 5)
+#define CE_ADM_ERR_CXM_CREDIT_OFLOW (0x1ULL << 6)
+#define CE_ADM_ERR_DRE_SSP_REQ_INVAL (0x1ULL << 7)
+#define CE_ADM_ERR_SSP_REQ_LONG (0x1ULL << 8)
+#define CE_ADM_ERR_SSP_REQ_OFLOW (0x1ULL << 9)
+#define CE_ADM_ERR_SSP_REQ_SHORT (0x1ULL << 10)
+#define CE_ADM_ERR_SSP_REQ_SIDEBAND (0x1ULL << 11)
+#define CE_ADM_ERR_SSP_REQ_ADDR_ERR (0x1ULL << 12)
+#define CE_ADM_ERR_SSP_REQ_BAD_BE (0x1ULL << 13)
+#define CE_ADM_ERR_PCIE_COMPL_TIMEOUT (0x1ULL << 14)
+#define CE_ADM_ERR_PCIE_UNEXP_COMPL (0x1ULL << 15)
+#define CE_ADM_ERR_PCIE_ERR_COMPL (0x1ULL << 16)
+#define CE_ADM_ERR_DRE_CREDIT_OFLOW (0x1ULL << 17)
+#define CE_ADM_ERR_DRE_SRAM_PE (0x1ULL << 18)
+#define CE_ADM_ERR_SSP_RSP_INVALID (0x1ULL << 19)
+#define CE_ADM_ERR_SSP_RSP_LONG (0x1ULL << 20)
+#define CE_ADM_ERR_SSP_RSP_SHORT (0x1ULL << 21)
+#define CE_ADM_ERR_SSP_RSP_SIDEBAND (0x1ULL << 22)
+#define CE_ADM_ERR_URE_SSP_RSP_UNEXP (0x1ULL << 23)
+#define CE_ADM_ERR_URE_SSP_WR_REQ_TIMEOUT (0x1ULL << 24)
+#define CE_ADM_ERR_URE_SSP_RD_REQ_TIMEOUT (0x1ULL << 25)
+#define CE_ADM_ERR_URE_ATE3240_PAGE_FAULT (0x1ULL << 26)
+#define CE_ADM_ERR_URE_ATE40_PAGE_FAULT (0x1ULL << 27)
+#define CE_ADM_ERR_URE_CREDIT_OFLOW (0x1ULL << 28)
+#define CE_ADM_ERR_URE_SRAM_PE (0x1ULL << 29)
+#define CE_ADM_ERR_ADM_SSP_RSP_UNEXP (0x1ULL << 30)
+#define CE_ADM_ERR_ADM_SSP_REQ_TIMEOUT (0x1ULL << 31)
+#define CE_ADM_ERR_MMR_ACCESS_ERROR (0x1ULL << 32)
+#define CE_ADM_ERR_MMR_ADDR_ERROR (0x1ULL << 33)
+#define CE_ADM_ERR_ADM_CREDIT_OFLOW (0x1ULL << 34)
+#define CE_ADM_ERR_ADM_SRAM_PE (0x1ULL << 35)
+#define CE_ADM_ERR_DTL1_MIN_PDATA_CREDIT_ERR (0x1ULL << 36)
+#define CE_ADM_ERR_DTL1_INF_COMPL_CRED_UPDT_ERR (0x1ULL << 37)
+#define CE_ADM_ERR_DTL1_INF_POSTED_CRED_UPDT_ERR (0x1ULL << 38)
+#define CE_ADM_ERR_DTL1_INF_NPOSTED_CRED_UPDT_ERR (0x1ULL << 39)
+#define CE_ADM_ERR_DTL1_COMP_HD_CRED_MAX_ERR (0x1ULL << 40)
+#define CE_ADM_ERR_DTL1_COMP_D_CRED_MAX_ERR (0x1ULL << 41)
+#define CE_ADM_ERR_DTL1_NPOSTED_HD_CRED_MAX_ERR (0x1ULL << 42)
+#define CE_ADM_ERR_DTL1_NPOSTED_D_CRED_MAX_ERR (0x1ULL << 43)
+#define CE_ADM_ERR_DTL1_POSTED_HD_CRED_MAX_ERR (0x1ULL << 44)
+#define CE_ADM_ERR_DTL1_POSTED_D_CRED_MAX_ERR (0x1ULL << 45)
+#define CE_ADM_ERR_DTL2_MIN_PDATA_CREDIT_ERR (0x1ULL << 46)
+#define CE_ADM_ERR_DTL2_INF_COMPL_CRED_UPDT_ERR (0x1ULL << 47)
+#define CE_ADM_ERR_DTL2_INF_POSTED_CRED_UPDT_ERR (0x1ULL << 48)
+#define CE_ADM_ERR_DTL2_INF_NPOSTED_CRED_UPDT_ERR (0x1ULL << 49)
+#define CE_ADM_ERR_DTL2_COMP_HD_CRED_MAX_ERR (0x1ULL << 50)
+#define CE_ADM_ERR_DTL2_COMP_D_CRED_MAX_ERR (0x1ULL << 51)
+#define CE_ADM_ERR_DTL2_NPOSTED_HD_CRED_MAX_ERR (0x1ULL << 52)
+#define CE_ADM_ERR_DTL2_NPOSTED_D_CRED_MAX_ERR (0x1ULL << 53)
+#define CE_ADM_ERR_DTL2_POSTED_HD_CRED_MAX_ERR (0x1ULL << 54)
+#define CE_ADM_ERR_DTL2_POSTED_D_CRED_MAX_ERR (0x1ULL << 55)
+#define CE_ADM_ERR_PORT1_PCIE_COR_ERR (0x1ULL << 56)
+#define CE_ADM_ERR_PORT1_PCIE_NFAT_ERR (0x1ULL << 57)
+#define CE_ADM_ERR_PORT1_PCIE_FAT_ERR (0x1ULL << 58)
+#define CE_ADM_ERR_PORT2_PCIE_COR_ERR (0x1ULL << 59)
+#define CE_ADM_ERR_PORT2_PCIE_NFAT_ERR (0x1ULL << 60)
+#define CE_ADM_ERR_PORT2_PCIE_FAT_ERR (0x1ULL << 61)
+
+/* ce_adm_ure_ups_buf_barrier_flush register bit masks and shifts */
+#define FLUSH_SEL_PORT1_PIPE0_SHFT 0
+#define FLUSH_SEL_PORT1_PIPE1_SHFT 4
+#define FLUSH_SEL_PORT1_PIPE2_SHFT 8
+#define FLUSH_SEL_PORT1_PIPE3_SHFT 12
+#define FLUSH_SEL_PORT2_PIPE0_SHFT 16
+#define FLUSH_SEL_PORT2_PIPE1_SHFT 20
+#define FLUSH_SEL_PORT2_PIPE2_SHFT 24
+#define FLUSH_SEL_PORT2_PIPE3_SHFT 28
+
+/* ce_dre_config1 register bit masks and shifts */
+#define CE_DRE_RO_ENABLE (0x1ULL << 0)
+#define CE_DRE_DYN_RO_ENABLE (0x1ULL << 1)
+#define CE_DRE_SUP_CONFIG_COMP_ERROR (0x1ULL << 2)
+#define CE_DRE_SUP_IO_COMP_ERROR (0x1ULL << 3)
+#define CE_DRE_ADDR_MODE_SHFT 4
+
+/* ce_dre_config_req_status register bit masks */
+#define CE_DRE_LAST_CONFIG_COMPLETION (0x7ULL << 0)
+#define CE_DRE_DOWNSTREAM_CONFIG_ERROR (0x1ULL << 3)
+#define CE_DRE_CONFIG_COMPLETION_VALID (0x1ULL << 4)
+#define CE_DRE_CONFIG_REQUEST_ACTIVE (0x1ULL << 5)
+
+/* ce_ure_control register bit masks & shifts */
+#define CE_URE_RD_MRG_ENABLE (0x1ULL << 0)
+#define CE_URE_WRT_MRG_ENABLE1 (0x1ULL << 4)
+#define CE_URE_WRT_MRG_ENABLE2 (0x1ULL << 5)
+#define CE_URE_WRT_MRG_TIMER_SHFT 12
+#define CE_URE_WRT_MRG_TIMER_MASK (0x7FFULL << CE_URE_WRT_MRG_TIMER_SHFT)
+#define CE_URE_WRT_MRG_TIMER(x) (((u64)(x) << \
+ CE_URE_WRT_MRG_TIMER_SHFT) & \
+ CE_URE_WRT_MRG_TIMER_MASK)
+#define CE_URE_RSPQ_BYPASS_DISABLE (0x1ULL << 24)
+#define CE_URE_UPS_DAT1_PAR_DISABLE (0x1ULL << 32)
+#define CE_URE_UPS_HDR1_PAR_DISABLE (0x1ULL << 33)
+#define CE_URE_UPS_DAT2_PAR_DISABLE (0x1ULL << 34)
+#define CE_URE_UPS_HDR2_PAR_DISABLE (0x1ULL << 35)
+#define CE_URE_ATE_PAR_DISABLE (0x1ULL << 36)
+#define CE_URE_RCI_PAR_DISABLE (0x1ULL << 37)
+#define CE_URE_RSPQ_PAR_DISABLE (0x1ULL << 38)
+#define CE_URE_DNS_DAT_PAR_DISABLE (0x1ULL << 39)
+#define CE_URE_DNS_HDR_PAR_DISABLE (0x1ULL << 40)
+#define CE_URE_MALFORM_DISABLE (0x1ULL << 44)
+#define CE_URE_UNSUP_DISABLE (0x1ULL << 45)
+
+/* ce_ure_page_map register bit masks & shifts */
+#define CE_URE_ATE3240_ENABLE (0x1ULL << 0)
+#define CE_URE_ATE40_ENABLE (0x1ULL << 1)
+#define CE_URE_PAGESIZE_SHFT 4
+#define CE_URE_PAGESIZE_MASK (0x7ULL << CE_URE_PAGESIZE_SHFT)
+#define CE_URE_4K_PAGESIZE (0x0ULL << CE_URE_PAGESIZE_SHFT)
+#define CE_URE_16K_PAGESIZE (0x1ULL << CE_URE_PAGESIZE_SHFT)
+#define CE_URE_64K_PAGESIZE (0x2ULL << CE_URE_PAGESIZE_SHFT)
+#define CE_URE_128K_PAGESIZE (0x3ULL << CE_URE_PAGESIZE_SHFT)
+#define CE_URE_256K_PAGESIZE (0x4ULL << CE_URE_PAGESIZE_SHFT)
+
+/* ce_ure_pipe_sel register bit masks & shifts */
+#define PKT_TRAFIC_SHRT 16
+#define BUS_SRC_ID_SHFT 8
+#define DEV_SRC_ID_SHFT 3
+#define FNC_SRC_ID_SHFT 0
+#define CE_URE_TC_MASK (0x07ULL << PKT_TRAFIC_SHRT)
+#define CE_URE_BUS_MASK (0xFFULL << BUS_SRC_ID_SHFT)
+#define CE_URE_DEV_MASK (0x1FULL << DEV_SRC_ID_SHFT)
+#define CE_URE_FNC_MASK (0x07ULL << FNC_SRC_ID_SHFT)
+#define CE_URE_PIPE_BUS(b) (((u64)(b) << BUS_SRC_ID_SHFT) & \
+ CE_URE_BUS_MASK)
+#define CE_URE_PIPE_DEV(d) (((u64)(d) << DEV_SRC_ID_SHFT) & \
+ CE_URE_DEV_MASK)
+#define CE_URE_PIPE_FNC(f) (((u64)(f) << FNC_SRC_ID_SHFT) & \
+ CE_URE_FNC_MASK)
+
+#define CE_URE_SEL1_SHFT 0
+#define CE_URE_SEL2_SHFT 20
+#define CE_URE_SEL3_SHFT 40
+#define CE_URE_SEL1_MASK (0x7FFFFULL << CE_URE_SEL1_SHFT)
+#define CE_URE_SEL2_MASK (0x7FFFFULL << CE_URE_SEL2_SHFT)
+#define CE_URE_SEL3_MASK (0x7FFFFULL << CE_URE_SEL3_SHFT)
+
+
+/* ce_ure_pipe_mask register bit masks & shifts */
+#define CE_URE_MASK1_SHFT 0
+#define CE_URE_MASK2_SHFT 20
+#define CE_URE_MASK3_SHFT 40
+#define CE_URE_MASK1_MASK (0x7FFFFULL << CE_URE_MASK1_SHFT)
+#define CE_URE_MASK2_MASK (0x7FFFFULL << CE_URE_MASK2_SHFT)
+#define CE_URE_MASK3_MASK (0x7FFFFULL << CE_URE_MASK3_SHFT)
+
+
+/* ce_ure_pcie_control1 register bit masks & shifts */
+#define CE_URE_SI (0x1ULL << 0)
+#define CE_URE_ELAL_SHFT 4
+#define CE_URE_ELAL_MASK (0x7ULL << CE_URE_ELAL_SHFT)
+#define CE_URE_ELAL_SET(n) (((u64)(n) << CE_URE_ELAL_SHFT) & \
+ CE_URE_ELAL_MASK)
+#define CE_URE_ELAL1_SHFT 8
+#define CE_URE_ELAL1_MASK (0x7ULL << CE_URE_ELAL1_SHFT)
+#define CE_URE_ELAL1_SET(n) (((u64)(n) << CE_URE_ELAL1_SHFT) & \
+ CE_URE_ELAL1_MASK)
+#define CE_URE_SCC (0x1ULL << 12)
+#define CE_URE_PN1_SHFT 16
+#define CE_URE_PN1_MASK (0xFFULL << CE_URE_PN1_SHFT)
+#define CE_URE_PN2_SHFT 24
+#define CE_URE_PN2_MASK (0xFFULL << CE_URE_PN2_SHFT)
+#define CE_URE_PN1_SET(n) (((u64)(n) << CE_URE_PN1_SHFT) & \
+ CE_URE_PN1_MASK)
+#define CE_URE_PN2_SET(n) (((u64)(n) << CE_URE_PN2_SHFT) & \
+ CE_URE_PN2_MASK)
+
+/* ce_ure_pcie_control2 register bit masks & shifts */
+#define CE_URE_ABP (0x1ULL << 0)
+#define CE_URE_PCP (0x1ULL << 1)
+#define CE_URE_MSP (0x1ULL << 2)
+#define CE_URE_AIP (0x1ULL << 3)
+#define CE_URE_PIP (0x1ULL << 4)
+#define CE_URE_HPS (0x1ULL << 5)
+#define CE_URE_HPC (0x1ULL << 6)
+#define CE_URE_SPLV_SHFT 7
+#define CE_URE_SPLV_MASK (0xFFULL << CE_URE_SPLV_SHFT)
+#define CE_URE_SPLV_SET(n) (((u64)(n) << CE_URE_SPLV_SHFT) & \
+ CE_URE_SPLV_MASK)
+#define CE_URE_SPLS_SHFT 15
+#define CE_URE_SPLS_MASK (0x3ULL << CE_URE_SPLS_SHFT)
+#define CE_URE_SPLS_SET(n) (((u64)(n) << CE_URE_SPLS_SHFT) & \
+ CE_URE_SPLS_MASK)
+#define CE_URE_PSN1_SHFT 19
+#define CE_URE_PSN1_MASK (0x1FFFULL << CE_URE_PSN1_SHFT)
+#define CE_URE_PSN2_SHFT 32
+#define CE_URE_PSN2_MASK (0x1FFFULL << CE_URE_PSN2_SHFT)
+#define CE_URE_PSN1_SET(n) (((u64)(n) << CE_URE_PSN1_SHFT) & \
+ CE_URE_PSN1_MASK)
+#define CE_URE_PSN2_SET(n) (((u64)(n) << CE_URE_PSN2_SHFT) & \
+ CE_URE_PSN2_MASK)
+
+/*
+ * PIO address space ranges for CE
+ */
+
+/* Local CE Registers Space */
+#define CE_PIO_MMR 0x00000000
+#define CE_PIO_MMR_LEN 0x04000000
+
+/* PCI Compatible Config Space */
+#define CE_PIO_CONFIG_SPACE 0x04000000
+#define CE_PIO_CONFIG_SPACE_LEN 0x04000000
+
+/* PCI I/O Space Alias */
+#define CE_PIO_IO_SPACE_ALIAS 0x08000000
+#define CE_PIO_IO_SPACE_ALIAS_LEN 0x08000000
+
+/* PCI Enhanced Config Space */
+#define CE_PIO_E_CONFIG_SPACE 0x10000000
+#define CE_PIO_E_CONFIG_SPACE_LEN 0x10000000
+
+/* PCI I/O Space */
+#define CE_PIO_IO_SPACE 0x100000000
+#define CE_PIO_IO_SPACE_LEN 0x100000000
+
+/* PCI MEM Space */
+#define CE_PIO_MEM_SPACE 0x200000000
+#define CE_PIO_MEM_SPACE_LEN TIO_HWIN_SIZE
+
+
+/*
+ * CE PCI Enhanced Config Space shifts & masks
+ */
+#define CE_E_CONFIG_BUS_SHFT 20
+#define CE_E_CONFIG_BUS_MASK (0xFF << CE_E_CONFIG_BUS_SHFT)
+#define CE_E_CONFIG_DEVICE_SHFT 15
+#define CE_E_CONFIG_DEVICE_MASK (0x1F << CE_E_CONFIG_DEVICE_SHFT)
+#define CE_E_CONFIG_FUNC_SHFT 12
+#define CE_E_CONFIG_FUNC_MASK (0x7 << CE_E_CONFIG_FUNC_SHFT)
+
+#endif /* __ASM_IA64_SN_TIOCE_H__ */
diff --git a/kernel/arch/ia64/include/asm/sn/tioce_provider.h b/kernel/arch/ia64/include/asm/sn/tioce_provider.h
new file mode 100644
index 000000000..32c32f30b
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/tioce_provider.h
@@ -0,0 +1,63 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_CE_PROVIDER_H
+#define _ASM_IA64_SN_CE_PROVIDER_H
+
+#include <asm/sn/pcibus_provider_defs.h>
+#include <asm/sn/tioce.h>
+
+/*
+ * Common TIOCE structure shared between the prom and kernel
+ *
+ * DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES TO THE
+ * PROM VERSION.
+ */
+struct tioce_common {
+ struct pcibus_bussoft ce_pcibus; /* common pciio header */
+
+ u32 ce_rev;
+ u64 ce_kernel_private;
+ u64 ce_prom_private;
+};
+
+struct tioce_kernel {
+ struct tioce_common *ce_common;
+ spinlock_t ce_lock;
+ struct list_head ce_dmamap_list;
+
+ u64 ce_ate40_shadow[TIOCE_NUM_M40_ATES];
+ u64 ce_ate3240_shadow[TIOCE_NUM_M3240_ATES];
+ u32 ce_ate3240_pagesize;
+
+ u8 ce_port1_secondary;
+
+ /* per-port resources */
+ struct {
+ int dirmap_refcnt;
+ u64 dirmap_shadow;
+ } ce_port[TIOCE_NUM_PORTS];
+};
+
+struct tioce_dmamap {
+ struct list_head ce_dmamap_list; /* headed by tioce_kernel */
+ u32 refcnt;
+
+ u64 nbytes; /* # bytes mapped */
+
+ u64 ct_start; /* coretalk start address */
+ u64 pci_start; /* bus start address */
+
+ u64 __iomem *ate_hw;/* hw ptr of first ate in map */
+ u64 *ate_shadow; /* shadow ptr of firat ate */
+ u16 ate_count; /* # ate's in the map */
+};
+
+extern int tioce_init_provider(void);
+
+#endif /* __ASM_IA64_SN_CE_PROVIDER_H */
diff --git a/kernel/arch/ia64/include/asm/sn/tiocp.h b/kernel/arch/ia64/include/asm/sn/tiocp.h
new file mode 100644
index 000000000..e8ad0bb5b
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/tiocp.h
@@ -0,0 +1,257 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003-2005 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PCI_TIOCP_H
+#define _ASM_IA64_SN_PCI_TIOCP_H
+
+#define TIOCP_HOST_INTR_ADDR 0x003FFFFFFFFFFFFFUL
+#define TIOCP_PCI64_CMDTYPE_MEM (0x1ull << 60)
+#define TIOCP_PCI64_CMDTYPE_MSI (0x3ull << 60)
+
+
+/*****************************************************************************
+ *********************** TIOCP MMR structure mapping ***************************
+ *****************************************************************************/
+
+struct tiocp{
+
+ /* 0x000000-0x00FFFF -- Local Registers */
+
+ /* 0x000000-0x000057 -- (Legacy Widget Space) Configuration */
+ u64 cp_id; /* 0x000000 */
+ u64 cp_stat; /* 0x000008 */
+ u64 cp_err_upper; /* 0x000010 */
+ u64 cp_err_lower; /* 0x000018 */
+ #define cp_err cp_err_lower
+ u64 cp_control; /* 0x000020 */
+ u64 cp_req_timeout; /* 0x000028 */
+ u64 cp_intr_upper; /* 0x000030 */
+ u64 cp_intr_lower; /* 0x000038 */
+ #define cp_intr cp_intr_lower
+ u64 cp_err_cmdword; /* 0x000040 */
+ u64 _pad_000048; /* 0x000048 */
+ u64 cp_tflush; /* 0x000050 */
+
+ /* 0x000058-0x00007F -- Bridge-specific Configuration */
+ u64 cp_aux_err; /* 0x000058 */
+ u64 cp_resp_upper; /* 0x000060 */
+ u64 cp_resp_lower; /* 0x000068 */
+ #define cp_resp cp_resp_lower
+ u64 cp_tst_pin_ctrl; /* 0x000070 */
+ u64 cp_addr_lkerr; /* 0x000078 */
+
+ /* 0x000080-0x00008F -- PMU & MAP */
+ u64 cp_dir_map; /* 0x000080 */
+ u64 _pad_000088; /* 0x000088 */
+
+ /* 0x000090-0x00009F -- SSRAM */
+ u64 cp_map_fault; /* 0x000090 */
+ u64 _pad_000098; /* 0x000098 */
+
+ /* 0x0000A0-0x0000AF -- Arbitration */
+ u64 cp_arb; /* 0x0000A0 */
+ u64 _pad_0000A8; /* 0x0000A8 */
+
+ /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
+ u64 cp_ate_parity_err; /* 0x0000B0 */
+ u64 _pad_0000B8; /* 0x0000B8 */
+
+ /* 0x0000C0-0x0000FF -- PCI/GIO */
+ u64 cp_bus_timeout; /* 0x0000C0 */
+ u64 cp_pci_cfg; /* 0x0000C8 */
+ u64 cp_pci_err_upper; /* 0x0000D0 */
+ u64 cp_pci_err_lower; /* 0x0000D8 */
+ #define cp_pci_err cp_pci_err_lower
+ u64 _pad_0000E0[4]; /* 0x0000{E0..F8} */
+
+ /* 0x000100-0x0001FF -- Interrupt */
+ u64 cp_int_status; /* 0x000100 */
+ u64 cp_int_enable; /* 0x000108 */
+ u64 cp_int_rst_stat; /* 0x000110 */
+ u64 cp_int_mode; /* 0x000118 */
+ u64 cp_int_device; /* 0x000120 */
+ u64 cp_int_host_err; /* 0x000128 */
+ u64 cp_int_addr[8]; /* 0x0001{30,,,68} */
+ u64 cp_err_int_view; /* 0x000170 */
+ u64 cp_mult_int; /* 0x000178 */
+ u64 cp_force_always[8]; /* 0x0001{80,,,B8} */
+ u64 cp_force_pin[8]; /* 0x0001{C0,,,F8} */
+
+ /* 0x000200-0x000298 -- Device */
+ u64 cp_device[4]; /* 0x0002{00,,,18} */
+ u64 _pad_000220[4]; /* 0x0002{20,,,38} */
+ u64 cp_wr_req_buf[4]; /* 0x0002{40,,,58} */
+ u64 _pad_000260[4]; /* 0x0002{60,,,78} */
+ u64 cp_rrb_map[2]; /* 0x0002{80,,,88} */
+ #define cp_even_resp cp_rrb_map[0] /* 0x000280 */
+ #define cp_odd_resp cp_rrb_map[1] /* 0x000288 */
+ u64 cp_resp_status; /* 0x000290 */
+ u64 cp_resp_clear; /* 0x000298 */
+
+ u64 _pad_0002A0[12]; /* 0x0002{A0..F8} */
+
+ /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
+ struct {
+ u64 upper; /* 0x0003{00,,,F0} */
+ u64 lower; /* 0x0003{08,,,F8} */
+ } cp_buf_addr_match[16];
+
+ /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
+ struct {
+ u64 flush_w_touch; /* 0x000{400,,,5C0} */
+ u64 flush_wo_touch; /* 0x000{408,,,5C8} */
+ u64 inflight; /* 0x000{410,,,5D0} */
+ u64 prefetch; /* 0x000{418,,,5D8} */
+ u64 total_pci_retry; /* 0x000{420,,,5E0} */
+ u64 max_pci_retry; /* 0x000{428,,,5E8} */
+ u64 max_latency; /* 0x000{430,,,5F0} */
+ u64 clear_all; /* 0x000{438,,,5F8} */
+ } cp_buf_count[8];
+
+
+ /* 0x000600-0x0009FF -- PCI/X registers */
+ u64 cp_pcix_bus_err_addr; /* 0x000600 */
+ u64 cp_pcix_bus_err_attr; /* 0x000608 */
+ u64 cp_pcix_bus_err_data; /* 0x000610 */
+ u64 cp_pcix_pio_split_addr; /* 0x000618 */
+ u64 cp_pcix_pio_split_attr; /* 0x000620 */
+ u64 cp_pcix_dma_req_err_attr; /* 0x000628 */
+ u64 cp_pcix_dma_req_err_addr; /* 0x000630 */
+ u64 cp_pcix_timeout; /* 0x000638 */
+
+ u64 _pad_000640[24]; /* 0x000{640,,,6F8} */
+
+ /* 0x000700-0x000737 -- Debug Registers */
+ u64 cp_ct_debug_ctl; /* 0x000700 */
+ u64 cp_br_debug_ctl; /* 0x000708 */
+ u64 cp_mux3_debug_ctl; /* 0x000710 */
+ u64 cp_mux4_debug_ctl; /* 0x000718 */
+ u64 cp_mux5_debug_ctl; /* 0x000720 */
+ u64 cp_mux6_debug_ctl; /* 0x000728 */
+ u64 cp_mux7_debug_ctl; /* 0x000730 */
+
+ u64 _pad_000738[89]; /* 0x000{738,,,9F8} */
+
+ /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
+ struct {
+ u64 cp_buf_addr; /* 0x000{A00,,,AF0} */
+ u64 cp_buf_attr; /* 0X000{A08,,,AF8} */
+ } cp_pcix_read_buf_64[16];
+
+ struct {
+ u64 cp_buf_addr; /* 0x000{B00,,,BE0} */
+ u64 cp_buf_attr; /* 0x000{B08,,,BE8} */
+ u64 cp_buf_valid; /* 0x000{B10,,,BF0} */
+ u64 __pad1; /* 0x000{B18,,,BF8} */
+ } cp_pcix_write_buf_64[8];
+
+ /* End of Local Registers -- Start of Address Map space */
+
+ char _pad_000c00[0x010000 - 0x000c00];
+
+ /* 0x010000-0x011FF8 -- Internal ATE RAM (Auto Parity Generation) */
+ u64 cp_int_ate_ram[1024]; /* 0x010000-0x011FF8 */
+
+ char _pad_012000[0x14000 - 0x012000];
+
+ /* 0x014000-0x015FF8 -- Internal ATE RAM (Manual Parity Generation) */
+ u64 cp_int_ate_ram_mp[1024]; /* 0x014000-0x015FF8 */
+
+ char _pad_016000[0x18000 - 0x016000];
+
+ /* 0x18000-0x197F8 -- TIOCP Write Request Ram */
+ u64 cp_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
+ u64 cp_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
+ u64 cp_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
+
+ char _pad_019800[0x1C000 - 0x019800];
+
+ /* 0x1C000-0x1EFF8 -- TIOCP Read Response Ram */
+ u64 cp_rd_resp_lower[512]; /* 0x1C000 - 0x1CFF8 */
+ u64 cp_rd_resp_upper[512]; /* 0x1D000 - 0x1DFF8 */
+ u64 cp_rd_resp_parity[512]; /* 0x1E000 - 0x1EFF8 */
+
+ char _pad_01F000[0x20000 - 0x01F000];
+
+ /* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used) */
+ char _pad_020000[0x021000 - 0x20000];
+
+ /* 0x021000-0x027FFF -- PCI Device Configuration Spaces */
+ union {
+ u8 c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
+ u16 s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
+ u32 l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
+ u64 d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
+ union {
+ u8 c[0x100 / 1];
+ u16 s[0x100 / 2];
+ u32 l[0x100 / 4];
+ u64 d[0x100 / 8];
+ } f[8];
+ } cp_type0_cfg_dev[7]; /* 0x02{1000,,,7FFF} */
+
+ /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
+ union {
+ u8 c[0x1000 / 1]; /* 0x028000-0x029000 */
+ u16 s[0x1000 / 2]; /* 0x028000-0x029000 */
+ u32 l[0x1000 / 4]; /* 0x028000-0x029000 */
+ u64 d[0x1000 / 8]; /* 0x028000-0x029000 */
+ union {
+ u8 c[0x100 / 1];
+ u16 s[0x100 / 2];
+ u32 l[0x100 / 4];
+ u64 d[0x100 / 8];
+ } f[8];
+ } cp_type1_cfg; /* 0x028000-0x029000 */
+
+ char _pad_029000[0x030000-0x029000];
+
+ /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
+ union {
+ u8 c[8 / 1];
+ u16 s[8 / 2];
+ u32 l[8 / 4];
+ u64 d[8 / 8];
+ } cp_pci_iack; /* 0x030000-0x030007 */
+
+ char _pad_030007[0x040000-0x030008];
+
+ /* 0x040000-0x040007 -- PCIX Special Cycle */
+ union {
+ u8 c[8 / 1];
+ u16 s[8 / 2];
+ u32 l[8 / 4];
+ u64 d[8 / 8];
+ } cp_pcix_cycle; /* 0x040000-0x040007 */
+
+ char _pad_040007[0x200000-0x040008];
+
+ /* 0x200000-0x7FFFFF -- PCI/GIO Device Spaces */
+ union {
+ u8 c[0x100000 / 1];
+ u16 s[0x100000 / 2];
+ u32 l[0x100000 / 4];
+ u64 d[0x100000 / 8];
+ } cp_devio_raw[6]; /* 0x200000-0x7FFFFF */
+
+ #define cp_devio(n) cp_devio_raw[((n)<2)?(n*2):(n+2)]
+
+ char _pad_800000[0xA00000-0x800000];
+
+ /* 0xA00000-0xBFFFFF -- PCI/GIO Device Spaces w/flush */
+ union {
+ u8 c[0x100000 / 1];
+ u16 s[0x100000 / 2];
+ u32 l[0x100000 / 4];
+ u64 d[0x100000 / 8];
+ } cp_devio_raw_flush[6]; /* 0xA00000-0xBFFFFF */
+
+ #define cp_devio_flush(n) cp_devio_raw_flush[((n)<2)?(n*2):(n+2)]
+
+};
+
+#endif /* _ASM_IA64_SN_PCI_TIOCP_H */
diff --git a/kernel/arch/ia64/include/asm/sn/tiocx.h b/kernel/arch/ia64/include/asm/sn/tiocx.h
new file mode 100644
index 000000000..d29728492
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/tiocx.h
@@ -0,0 +1,72 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2005 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_TIO_TIOCX_H
+#define _ASM_IA64_SN_TIO_TIOCX_H
+
+#ifdef __KERNEL__
+
+struct cx_id_s {
+ unsigned int part_num;
+ unsigned int mfg_num;
+ int nasid;
+};
+
+struct cx_dev {
+ struct cx_id_s cx_id;
+ int bt; /* board/blade type */
+ void *soft; /* driver specific */
+ struct hubdev_info *hubdev;
+ struct device dev;
+ struct cx_drv *driver;
+};
+
+struct cx_device_id {
+ unsigned int part_num;
+ unsigned int mfg_num;
+};
+
+struct cx_drv {
+ char *name;
+ const struct cx_device_id *id_table;
+ struct device_driver driver;
+ int (*probe) (struct cx_dev * dev, const struct cx_device_id * id);
+ int (*remove) (struct cx_dev * dev);
+};
+
+/* create DMA address by stripping AS bits */
+#define TIOCX_DMA_ADDR(a) (u64)((u64)(a) & 0xffffcfffffffffUL)
+
+#define TIOCX_TO_TIOCX_DMA_ADDR(a) (u64)(((u64)(a) & 0xfffffffff) | \
+ ((((u64)(a)) & 0xffffc000000000UL) <<2))
+
+#define TIO_CE_ASIC_PARTNUM 0xce00
+#define TIOCX_CORELET 3
+
+/* These are taken from tio_mmr_as.h */
+#define TIO_ICE_FRZ_CFG TIO_MMR_ADDR_MOD(0x00000000b0008100UL)
+#define TIO_ICE_PMI_TX_CFG TIO_MMR_ADDR_MOD(0x00000000b000b100UL)
+#define TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3 TIO_MMR_ADDR_MOD(0x00000000b000be18UL)
+#define TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3_CREDIT_CNT_MASK 0x000000000000000fUL
+
+#define to_cx_dev(n) container_of(n, struct cx_dev, dev)
+#define to_cx_driver(drv) container_of(drv, struct cx_drv, driver)
+
+extern struct sn_irq_info *tiocx_irq_alloc(nasid_t, int, int, nasid_t, int);
+extern void tiocx_irq_free(struct sn_irq_info *);
+extern int cx_device_unregister(struct cx_dev *);
+extern int cx_device_register(nasid_t, int, int, struct hubdev_info *, int);
+extern int cx_driver_unregister(struct cx_drv *);
+extern int cx_driver_register(struct cx_drv *);
+extern u64 tiocx_dma_addr(u64 addr);
+extern u64 tiocx_swin_base(int nasid);
+extern void tiocx_mmr_store(int nasid, u64 offset, u64 value);
+extern u64 tiocx_mmr_load(int nasid, u64 offset);
+
+#endif // __KERNEL__
+#endif // _ASM_IA64_SN_TIO_TIOCX__
diff --git a/kernel/arch/ia64/include/asm/sn/types.h b/kernel/arch/ia64/include/asm/sn/types.h
new file mode 100644
index 000000000..8e04ee211
--- /dev/null
+++ b/kernel/arch/ia64/include/asm/sn/types.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1999,2001-2003 Silicon Graphics, Inc. All Rights Reserved.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_IA64_SN_TYPES_H
+#define _ASM_IA64_SN_TYPES_H
+
+#include <linux/types.h>
+
+typedef unsigned long cpuid_t;
+typedef signed short nasid_t; /* node id in numa-as-id space */
+typedef signed char partid_t; /* partition ID type */
+typedef unsigned int moduleid_t; /* user-visible module number type */
+typedef unsigned int cmoduleid_t; /* kernel compact module id type */
+typedef unsigned char slotid_t; /* slot (blade) within module */
+typedef unsigned char slabid_t; /* slab (asic) within slot */
+typedef u64 nic_t;
+typedef unsigned long iopaddr_t;
+typedef unsigned long paddr_t;
+typedef short cnodeid_t;
+
+#endif /* _ASM_IA64_SN_TYPES_H */