diff options
Diffstat (limited to 'kernel/arch/arm/mach-dove')
| -rw-r--r-- | kernel/arch/arm/mach-dove/Kconfig | 25 | ||||
| -rw-r--r-- | kernel/arch/arm/mach-dove/Makefile | 5 | ||||
| -rw-r--r-- | kernel/arch/arm/mach-dove/Makefile.boot | 3 | ||||
| -rw-r--r-- | kernel/arch/arm/mach-dove/cm-a510.c | 97 | ||||
| -rw-r--r-- | kernel/arch/arm/mach-dove/common.c | 411 | ||||
| -rw-r--r-- | kernel/arch/arm/mach-dove/common.h | 49 | ||||
| -rw-r--r-- | kernel/arch/arm/mach-dove/dove-db-setup.c | 103 | ||||
| -rw-r--r-- | kernel/arch/arm/mach-dove/include/mach/bridge-regs.h | 57 | ||||
| -rw-r--r-- | kernel/arch/arm/mach-dove/include/mach/dove.h | 190 | ||||
| -rw-r--r-- | kernel/arch/arm/mach-dove/include/mach/entry-macro.S | 33 | ||||
| -rw-r--r-- | kernel/arch/arm/mach-dove/include/mach/hardware.h | 19 | ||||
| -rw-r--r-- | kernel/arch/arm/mach-dove/include/mach/irqs.h | 96 | ||||
| -rw-r--r-- | kernel/arch/arm/mach-dove/include/mach/pm.h | 72 | ||||
| -rw-r--r-- | kernel/arch/arm/mach-dove/include/mach/uncompress.h | 36 | ||||
| -rw-r--r-- | kernel/arch/arm/mach-dove/irq.c | 178 | ||||
| -rw-r--r-- | kernel/arch/arm/mach-dove/mpp.c | 162 | ||||
| -rw-r--r-- | kernel/arch/arm/mach-dove/mpp.h | 196 | ||||
| -rw-r--r-- | kernel/arch/arm/mach-dove/pcie.c | 216 |
18 files changed, 1948 insertions, 0 deletions
diff --git a/kernel/arch/arm/mach-dove/Kconfig b/kernel/arch/arm/mach-dove/Kconfig new file mode 100644 index 000000000..d8c439c89 --- /dev/null +++ b/kernel/arch/arm/mach-dove/Kconfig @@ -0,0 +1,25 @@ +if ARCH_DOVE + +menu "Marvell Dove Implementations" + +config DOVE_LEGACY + bool + +config MACH_DOVE_DB + bool "Marvell DB-MV88AP510 Development Board" + select DOVE_LEGACY + select I2C_BOARDINFO + help + Say 'Y' here if you want your kernel to support the + Marvell DB-MV88AP510 Development Board. + +config MACH_CM_A510 + bool "CompuLab CM-A510 Board" + select DOVE_LEGACY + help + Say 'Y' here if you want your kernel to support the + CompuLab CM-A510 Board. + +endmenu + +endif diff --git a/kernel/arch/arm/mach-dove/Makefile b/kernel/arch/arm/mach-dove/Makefile new file mode 100644 index 000000000..b608a2191 --- /dev/null +++ b/kernel/arch/arm/mach-dove/Makefile @@ -0,0 +1,5 @@ +obj-y += common.o +obj-$(CONFIG_DOVE_LEGACY) += irq.o mpp.o +obj-$(CONFIG_PCI) += pcie.o +obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o +obj-$(CONFIG_MACH_CM_A510) += cm-a510.o diff --git a/kernel/arch/arm/mach-dove/Makefile.boot b/kernel/arch/arm/mach-dove/Makefile.boot new file mode 100644 index 000000000..760a0efe7 --- /dev/null +++ b/kernel/arch/arm/mach-dove/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y += 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/kernel/arch/arm/mach-dove/cm-a510.c b/kernel/arch/arm/mach-dove/cm-a510.c new file mode 100644 index 000000000..0dc39cf30 --- /dev/null +++ b/kernel/arch/arm/mach-dove/cm-a510.c @@ -0,0 +1,97 @@ +/* + * arch/arm/mach-dove/cm-a510.c + * + * Copyright (C) 2010 CompuLab, Ltd. + * Konstantin Sinyuk <kostyas@compulab.co.il> + * + * Based on Marvell DB-MV88AP510-BP Development Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/ata_platform.h> +#include <linux/mv643xx_eth.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/dove.h> + +#include "common.h" + +static struct mv643xx_eth_platform_data cm_a510_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT, +}; + +static struct mv_sata_platform_data cm_a510_sata_data = { + .n_ports = 1, +}; + +/* + * SPI Devices: + * SPI0: 1M Flash Winbond w25q32bv + */ +static const struct flash_platform_data cm_a510_spi_flash_data = { + .type = "w25q32bv", +}; + +static struct spi_board_info __initdata cm_a510_spi_flash_info[] = { + { + .modalias = "m25p80", + .platform_data = &cm_a510_spi_flash_data, + .irq = -1, + .max_speed_hz = 20000000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +static int __init cm_a510_pci_init(void) +{ + if (machine_is_cm_a510()) + dove_pcie_init(1, 1); + + return 0; +} + +subsys_initcall(cm_a510_pci_init); + +/* Board Init */ +static void __init cm_a510_init(void) +{ + /* + * Basic Dove setup. Needs to be called early. + */ + dove_init(); + + dove_ge00_init(&cm_a510_ge00_data); + dove_ehci0_init(); + dove_ehci1_init(); + dove_sata_init(&cm_a510_sata_data); + dove_sdio0_init(); + dove_sdio1_init(); + dove_spi0_init(); + dove_spi1_init(); + dove_uart0_init(); + dove_uart1_init(); + dove_i2c_init(); + spi_register_board_info(cm_a510_spi_flash_info, + ARRAY_SIZE(cm_a510_spi_flash_info)); +} + +MACHINE_START(CM_A510, "Compulab CM-A510 Board") + .atag_offset = 0x100, + .init_machine = cm_a510_init, + .map_io = dove_map_io, + .init_early = dove_init_early, + .init_irq = dove_init_irq, + .init_time = dove_timer_init, + .restart = dove_restart, +MACHINE_END diff --git a/kernel/arch/arm/mach-dove/common.c b/kernel/arch/arm/mach-dove/common.c new file mode 100644 index 000000000..0d1a89298 --- /dev/null +++ b/kernel/arch/arm/mach-dove/common.c @@ -0,0 +1,411 @@ +/* + * arch/arm/mach-dove/common.c + * + * Core functions for Marvell Dove 88AP510 System On Chip + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/clk-provider.h> +#include <linux/dma-mapping.h> +#include <linux/init.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/platform_data/dma-mv_xor.h> +#include <linux/platform_data/usb-ehci-orion.h> +#include <linux/platform_device.h> +#include <asm/hardware/cache-tauros2.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/time.h> +#include <mach/bridge-regs.h> +#include <mach/pm.h> +#include <plat/common.h> +#include <plat/irq.h> +#include <plat/time.h> +#include "common.h" + +/* These can go away once Dove uses the mvebu-mbus DT binding */ +#define DOVE_MBUS_PCIE0_MEM_TARGET 0x4 +#define DOVE_MBUS_PCIE0_MEM_ATTR 0xe8 +#define DOVE_MBUS_PCIE0_IO_TARGET 0x4 +#define DOVE_MBUS_PCIE0_IO_ATTR 0xe0 +#define DOVE_MBUS_PCIE1_MEM_TARGET 0x8 +#define DOVE_MBUS_PCIE1_MEM_ATTR 0xe8 +#define DOVE_MBUS_PCIE1_IO_TARGET 0x8 +#define DOVE_MBUS_PCIE1_IO_ATTR 0xe0 +#define DOVE_MBUS_CESA_TARGET 0x3 +#define DOVE_MBUS_CESA_ATTR 0x1 +#define DOVE_MBUS_BOOTROM_TARGET 0x1 +#define DOVE_MBUS_BOOTROM_ATTR 0xfd +#define DOVE_MBUS_SCRATCHPAD_TARGET 0xd +#define DOVE_MBUS_SCRATCHPAD_ATTR 0x0 + +/***************************************************************************** + * I/O Address Mapping + ****************************************************************************/ +static struct map_desc dove_io_desc[] __initdata = { + { + .virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE, + .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE), + .length = DOVE_SB_REGS_SIZE, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE, + .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), + .length = DOVE_NB_REGS_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init dove_map_io(void) +{ + iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc)); +} + +/***************************************************************************** + * CLK tree + ****************************************************************************/ +static int dove_tclk; + +static DEFINE_SPINLOCK(gating_lock); +static struct clk *tclk; + +static struct clk __init *dove_register_gate(const char *name, + const char *parent, u8 bit_idx) +{ + return clk_register_gate(NULL, name, parent, 0, + (void __iomem *)CLOCK_GATING_CONTROL, + bit_idx, 0, &gating_lock); +} + +static void __init dove_clk_init(void) +{ + struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1; + struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma; + struct clk *xor0, *xor1, *ge, *gephy; + + tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, + dove_tclk); + + usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0); + usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1); + sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA); + pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0); + pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1); + sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0); + sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1); + nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND); + camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA); + i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0); + i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1); + crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO); + ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97); + pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA); + xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0); + xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1); + gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY); + ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE); + + orion_clkdev_add(NULL, "orion_spi.0", tclk); + orion_clkdev_add(NULL, "orion_spi.1", tclk); + orion_clkdev_add(NULL, "orion_wdt", tclk); + orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk); + + orion_clkdev_add(NULL, "orion-ehci.0", usb0); + orion_clkdev_add(NULL, "orion-ehci.1", usb1); + orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge); + orion_clkdev_add(NULL, "sata_mv.0", sata); + orion_clkdev_add("0", "pcie", pex0); + orion_clkdev_add("1", "pcie", pex1); + orion_clkdev_add(NULL, "sdhci-dove.0", sdio0); + orion_clkdev_add(NULL, "sdhci-dove.1", sdio1); + orion_clkdev_add(NULL, "orion_nand", nand); + orion_clkdev_add(NULL, "cafe1000-ccic.0", camera); + orion_clkdev_add(NULL, "mvebu-audio.0", i2s0); + orion_clkdev_add(NULL, "mvebu-audio.1", i2s1); + orion_clkdev_add(NULL, "mv_crypto", crypto); + orion_clkdev_add(NULL, "dove-ac97", ac97); + orion_clkdev_add(NULL, "dove-pdma", pdma); + orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0); + orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1); +} + +/***************************************************************************** + * EHCI0 + ****************************************************************************/ +void __init dove_ehci0_init(void) +{ + orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA); +} + +/***************************************************************************** + * EHCI1 + ****************************************************************************/ +void __init dove_ehci1_init(void) +{ + orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1); +} + +/***************************************************************************** + * GE00 + ****************************************************************************/ +void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) +{ + orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE, + IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR, + 1600); +} + +/***************************************************************************** + * SoC RTC + ****************************************************************************/ +static void __init dove_rtc_init(void) +{ + orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC); +} + +/***************************************************************************** + * SATA + ****************************************************************************/ +void __init dove_sata_init(struct mv_sata_platform_data *sata_data) +{ + orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA); + +} + +/***************************************************************************** + * UART0 + ****************************************************************************/ +void __init dove_uart0_init(void) +{ + orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE, + IRQ_DOVE_UART_0, tclk); +} + +/***************************************************************************** + * UART1 + ****************************************************************************/ +void __init dove_uart1_init(void) +{ + orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE, + IRQ_DOVE_UART_1, tclk); +} + +/***************************************************************************** + * UART2 + ****************************************************************************/ +void __init dove_uart2_init(void) +{ + orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE, + IRQ_DOVE_UART_2, tclk); +} + +/***************************************************************************** + * UART3 + ****************************************************************************/ +void __init dove_uart3_init(void) +{ + orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE, + IRQ_DOVE_UART_3, tclk); +} + +/***************************************************************************** + * SPI + ****************************************************************************/ +void __init dove_spi0_init(void) +{ + orion_spi_init(DOVE_SPI0_PHYS_BASE); +} + +void __init dove_spi1_init(void) +{ + orion_spi_1_init(DOVE_SPI1_PHYS_BASE); +} + +/***************************************************************************** + * I2C + ****************************************************************************/ +void __init dove_i2c_init(void) +{ + orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10); +} + +/***************************************************************************** + * Time handling + ****************************************************************************/ +void __init dove_init_early(void) +{ + orion_time_set_base(TIMER_VIRT_BASE); + mvebu_mbus_init("marvell,dove-mbus", + BRIDGE_WINS_BASE, BRIDGE_WINS_SZ, + DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ); +} + +static int __init dove_find_tclk(void) +{ + return 166666667; +} + +void __init dove_timer_init(void) +{ + dove_tclk = dove_find_tclk(); + orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, + IRQ_DOVE_BRIDGE, dove_tclk); +} + +/***************************************************************************** + * XOR 0 + ****************************************************************************/ +static void __init dove_xor0_init(void) +{ + orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, + IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); +} + +/***************************************************************************** + * XOR 1 + ****************************************************************************/ +static void __init dove_xor1_init(void) +{ + orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE, + IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11); +} + +/***************************************************************************** + * SDIO + ****************************************************************************/ +static u64 sdio_dmamask = DMA_BIT_MASK(32); + +static struct resource dove_sdio0_resources[] = { + { + .start = DOVE_SDIO0_PHYS_BASE, + .end = DOVE_SDIO0_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_SDIO0, + .end = IRQ_DOVE_SDIO0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_sdio0 = { + .name = "sdhci-dove", + .id = 0, + .dev = { + .dma_mask = &sdio_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = dove_sdio0_resources, + .num_resources = ARRAY_SIZE(dove_sdio0_resources), +}; + +void __init dove_sdio0_init(void) +{ + platform_device_register(&dove_sdio0); +} + +static struct resource dove_sdio1_resources[] = { + { + .start = DOVE_SDIO1_PHYS_BASE, + .end = DOVE_SDIO1_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_SDIO1, + .end = IRQ_DOVE_SDIO1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_sdio1 = { + .name = "sdhci-dove", + .id = 1, + .dev = { + .dma_mask = &sdio_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = dove_sdio1_resources, + .num_resources = ARRAY_SIZE(dove_sdio1_resources), +}; + +void __init dove_sdio1_init(void) +{ + platform_device_register(&dove_sdio1); +} + +void __init dove_setup_cpu_wins(void) +{ + /* + * The PCIe windows will no longer be statically allocated + * here once Dove is migrated to the pci-mvebu driver. The + * non-PCIe windows will no longer be created here once Dove + * fully moves to DT. + */ + mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET, + DOVE_MBUS_PCIE0_IO_ATTR, + DOVE_PCIE0_IO_PHYS_BASE, + DOVE_PCIE0_IO_SIZE, + DOVE_PCIE0_IO_BUS_BASE); + mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET, + DOVE_MBUS_PCIE1_IO_ATTR, + DOVE_PCIE1_IO_PHYS_BASE, + DOVE_PCIE1_IO_SIZE, + DOVE_PCIE1_IO_BUS_BASE); + mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET, + DOVE_MBUS_PCIE0_MEM_ATTR, + DOVE_PCIE0_MEM_PHYS_BASE, + DOVE_PCIE0_MEM_SIZE); + mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET, + DOVE_MBUS_PCIE1_MEM_ATTR, + DOVE_PCIE1_MEM_PHYS_BASE, + DOVE_PCIE1_MEM_SIZE); + mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET, + DOVE_MBUS_CESA_ATTR, + DOVE_CESA_PHYS_BASE, + DOVE_CESA_SIZE); + mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET, + DOVE_MBUS_BOOTROM_ATTR, + DOVE_BOOTROM_PHYS_BASE, + DOVE_BOOTROM_SIZE); + mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET, + DOVE_MBUS_SCRATCHPAD_ATTR, + DOVE_SCRATCHPAD_PHYS_BASE, + DOVE_SCRATCHPAD_SIZE); +} + +void __init dove_init(void) +{ + pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", + (dove_tclk + 499999) / 1000000); + +#ifdef CONFIG_CACHE_TAUROS2 + tauros2_init(0); +#endif + dove_setup_cpu_wins(); + + /* Setup root of clk tree */ + dove_clk_init(); + + /* internal devices that every board has */ + dove_rtc_init(); + dove_xor0_init(); + dove_xor1_init(); +} + +void dove_restart(enum reboot_mode mode, const char *cmd) +{ + /* + * Enable soft reset to assert RSTOUTn. + */ + writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); + + /* + * Assert soft reset. + */ + writel(SOFT_RESET, SYSTEM_SOFT_RESET); + + while (1) + ; +} diff --git a/kernel/arch/arm/mach-dove/common.h b/kernel/arch/arm/mach-dove/common.h new file mode 100644 index 000000000..1d725224d --- /dev/null +++ b/kernel/arch/arm/mach-dove/common.h @@ -0,0 +1,49 @@ +/* + * arch/arm/mach-dove/common.h + * + * Core functions for Marvell Dove 88AP510 System On Chip + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ARCH_DOVE_COMMON_H +#define __ARCH_DOVE_COMMON_H + +#include <linux/reboot.h> + +struct mv643xx_eth_platform_data; +struct mv_sata_platform_data; + +extern void dove_timer_init(void); + +/* + * Basic Dove init functions used early by machine-setup. + */ +void dove_map_io(void); +void dove_init(void); +void dove_init_early(void); +void dove_init_irq(void); +void dove_setup_cpu_wins(void); +void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data); +void dove_sata_init(struct mv_sata_platform_data *sata_data); +#ifdef CONFIG_PCI +void dove_pcie_init(int init_port0, int init_port1); +#else +static inline void dove_pcie_init(int init_port0, int init_port1) { } +#endif +void dove_ehci0_init(void); +void dove_ehci1_init(void); +void dove_uart0_init(void); +void dove_uart1_init(void); +void dove_uart2_init(void); +void dove_uart3_init(void); +void dove_spi0_init(void); +void dove_spi1_init(void); +void dove_i2c_init(void); +void dove_sdio0_init(void); +void dove_sdio1_init(void); +void dove_restart(enum reboot_mode, const char *); + +#endif diff --git a/kernel/arch/arm/mach-dove/dove-db-setup.c b/kernel/arch/arm/mach-dove/dove-db-setup.c new file mode 100644 index 000000000..76e26f949 --- /dev/null +++ b/kernel/arch/arm/mach-dove/dove-db-setup.c @@ -0,0 +1,103 @@ +/* + * arch/arm/mach-dove/dove-db-setup.c + * + * Marvell DB-MV88AP510-BP Development Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/irq.h> +#include <linux/mtd/physmap.h> +#include <linux/mtd/nand.h> +#include <linux/timer.h> +#include <linux/ata_platform.h> +#include <linux/mv643xx_eth.h> +#include <linux/i2c.h> +#include <linux/pci.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> +#include <linux/gpio.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <mach/dove.h> +#include "common.h" + +static struct mv643xx_eth_platform_data dove_db_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT, +}; + +static struct mv_sata_platform_data dove_db_sata_data = { + .n_ports = 1, +}; + +/***************************************************************************** + * SPI Devices: + * SPI0: 4M Flash ST-M25P32-VMF6P + ****************************************************************************/ +static const struct flash_platform_data dove_db_spi_flash_data = { + .type = "m25p64", +}; + +static struct spi_board_info __initdata dove_db_spi_flash_info[] = { + { + .modalias = "m25p80", + .platform_data = &dove_db_spi_flash_data, + .irq = -1, + .max_speed_hz = 20000000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +/***************************************************************************** + * PCI + ****************************************************************************/ +static int __init dove_db_pci_init(void) +{ + if (machine_is_dove_db()) + dove_pcie_init(1, 1); + + return 0; +} + +subsys_initcall(dove_db_pci_init); + +/***************************************************************************** + * Board Init + ****************************************************************************/ +static void __init dove_db_init(void) +{ + /* + * Basic Dove setup. Needs to be called early. + */ + dove_init(); + + dove_ge00_init(&dove_db_ge00_data); + dove_ehci0_init(); + dove_ehci1_init(); + dove_sata_init(&dove_db_sata_data); + dove_sdio0_init(); + dove_sdio1_init(); + dove_spi0_init(); + dove_spi1_init(); + dove_uart0_init(); + dove_uart1_init(); + dove_i2c_init(); + spi_register_board_info(dove_db_spi_flash_info, + ARRAY_SIZE(dove_db_spi_flash_info)); +} + +MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board") + .atag_offset = 0x100, + .init_machine = dove_db_init, + .map_io = dove_map_io, + .init_early = dove_init_early, + .init_irq = dove_init_irq, + .init_time = dove_timer_init, + .restart = dove_restart, +MACHINE_END diff --git a/kernel/arch/arm/mach-dove/include/mach/bridge-regs.h b/kernel/arch/arm/mach-dove/include/mach/bridge-regs.h new file mode 100644 index 000000000..f4a5b3448 --- /dev/null +++ b/kernel/arch/arm/mach-dove/include/mach/bridge-regs.h @@ -0,0 +1,57 @@ +/* + * arch/arm/mach-dove/include/mach/bridge-regs.h + * + * Mbus-L to Mbus Bridge Registers + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_BRIDGE_REGS_H +#define __ASM_ARCH_BRIDGE_REGS_H + +#include <mach/dove.h> + +#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000) + +#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) +#define CPU_CTRL_PCIE0_LINK 0x00000001 +#define CPU_RESET 0x00000002 +#define CPU_CTRL_PCIE1_LINK 0x00000008 + +#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) +#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108) +#define SOFT_RESET_OUT_EN 0x00000004 + +#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) +#define SOFT_RESET 0x00000001 + +#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110) +#define BRIDGE_INT_TIMER1_CLR (~0x0004) + +#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) +#define IRQ_CAUSE_LOW_OFF 0x0000 +#define IRQ_MASK_LOW_OFF 0x0004 +#define FIQ_MASK_LOW_OFF 0x0008 +#define ENDPOINT_MASK_LOW_OFF 0x000c +#define IRQ_CAUSE_HIGH_OFF 0x0010 +#define IRQ_MASK_HIGH_OFF 0x0014 +#define FIQ_MASK_HIGH_OFF 0x0018 +#define ENDPOINT_MASK_HIGH_OFF 0x001c +#define PCIE_INTERRUPT_MASK_OFF 0x0020 + +#define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF) +#define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF) +#define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF) +#define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF) +#define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF) +#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF) +#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF) + +#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c) + +#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) +#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) + +#endif diff --git a/kernel/arch/arm/mach-dove/include/mach/dove.h b/kernel/arch/arm/mach-dove/include/mach/dove.h new file mode 100644 index 000000000..0c4b35f4e --- /dev/null +++ b/kernel/arch/arm/mach-dove/include/mach/dove.h @@ -0,0 +1,190 @@ +/* + * arch/arm/mach-dove/include/mach/dove.h + * + * Generic definitions for Marvell Dove 88AP510 SoC + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_DOVE_H +#define __ASM_ARCH_DOVE_H + +/* + * Marvell Dove address maps. + * + * phys virt size + * c8000000 fdb00000 1M Cryptographic SRAM + * e0000000 @runtime 128M PCIe-0 Memory space + * e8000000 @runtime 128M PCIe-1 Memory space + * f1000000 fde00000 8M on-chip south-bridge registers + * f1800000 fe600000 8M on-chip north-bridge registers + * f2000000 fee00000 1M PCIe-0 I/O space + * f2100000 fef00000 1M PCIe-1 I/O space + */ + +#define DOVE_CESA_PHYS_BASE 0xc8000000 +#define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000) +#define DOVE_CESA_SIZE SZ_1M + +#define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000 +#define DOVE_PCIE0_MEM_SIZE SZ_128M + +#define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000 +#define DOVE_PCIE1_MEM_SIZE SZ_128M + +#define DOVE_BOOTROM_PHYS_BASE 0xf8000000 +#define DOVE_BOOTROM_SIZE SZ_128M + +#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000 +#define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000) +#define DOVE_SCRATCHPAD_SIZE SZ_1M + +#define DOVE_SB_REGS_PHYS_BASE 0xf1000000 +#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) +#define DOVE_SB_REGS_SIZE SZ_8M + +#define DOVE_NB_REGS_PHYS_BASE 0xf1800000 +#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe600000) +#define DOVE_NB_REGS_SIZE SZ_8M + +#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 +#define DOVE_PCIE0_IO_BUS_BASE 0x00000000 +#define DOVE_PCIE0_IO_SIZE SZ_64K + +#define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000 +#define DOVE_PCIE1_IO_BUS_BASE 0x00010000 +#define DOVE_PCIE1_IO_SIZE SZ_64K + +/* + * Dove Core Registers Map + */ + +/* SPI, I2C, UART */ +#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x11000) +#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12000) +#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12000) +#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12100) +#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12100) +#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12200) +#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12200) +#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12300) +#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12300) +#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x10600) +#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x14600) + +/* North-South Bridge */ +#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000) +#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000) +#define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE) +#define BRIDGE_WINS_SZ (0x80) + +/* Cryptographic Engine */ +#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000) + +/* PCIe 0 */ +#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x40000) + +/* USB */ +#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x50000) +#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x51000) + +/* XOR 0 Engine */ +#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60800) +#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60800) +#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60A00) +#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60A00) + +/* XOR 1 Engine */ +#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60900) +#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60900) +#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60B00) +#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60B00) + +/* Gigabit Ethernet */ +#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x70000) + +/* PCIe 1 */ +#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x80000) + +/* CAFE */ +#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x92000) +#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x90000) +#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x94000) +#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000) + +/* SATA */ +#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xa0000) + +/* I2S/SPDIF */ +#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb0000) +#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb4000) + +/* NAND Flash Controller */ +#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xc0000) + +/* MPP, GPIO, Reset Sampling */ +#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) +#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) +#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE + 0x014) +#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE + 0x018) +#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) +#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0420) +#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe8400) +#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) +#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) +#define DOVE_NAND_GPIO_EN (1 << 0) +#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) +#define DOVE_SPI_GPIO_SEL (1 << 5) +#define DOVE_UART1_GPIO_SEL (1 << 4) +#define DOVE_AU1_GPIO_SEL (1 << 3) +#define DOVE_CAM_GPIO_SEL (1 << 2) +#define DOVE_SD1_GPIO_SEL (1 << 1) +#define DOVE_SD0_GPIO_SEL (1 << 0) + +/* Power Management */ +#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0000) +#define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c) + +/* Real Time Clock */ +#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xd8500) + +/* AC97 */ +#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe0000) +#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe0000) + +/* Peripheral DMA */ +#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe4000) +#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe4000) + +#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) +#define DOVE_TWSI_ENABLE_OPTION1 (1 << 7) +#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) +#define DOVE_TWSI_ENABLE_OPTION2 (1 << 20) +#define DOVE_TWSI_ENABLE_OPTION3 (1 << 21) +#define DOVE_TWSI_OPTION3_GPIO (1 << 22) +#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xec000) +#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) +#define DOVE_SSP_ON_AU1 (1 << 0) +#define DOVE_SSP_CLOCK_ENABLE (1 << 1) +#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11) +/* Memory Controller */ +#define DOVE_MC_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x00000) +#define DOVE_MC_WINS_BASE (DOVE_MC_PHYS_BASE + 0x100) +#define DOVE_MC_WINS_SZ (0x8) +#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000) + +/* LCD Controller */ +#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000) +#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x20000) +#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000) +#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000) + +/* Graphic Engine */ +#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x40000) + +/* Video Engine */ +#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x400000) + +#endif diff --git a/kernel/arch/arm/mach-dove/include/mach/entry-macro.S b/kernel/arch/arm/mach-dove/include/mach/entry-macro.S new file mode 100644 index 000000000..72d622baa --- /dev/null +++ b/kernel/arch/arm/mach-dove/include/mach/entry-macro.S @@ -0,0 +1,33 @@ +/* + * arch/arm/mach-dove/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for Marvell Dove platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <mach/bridge-regs.h> + + .macro get_irqnr_preamble, base, tmp + ldr \base, =IRQ_VIRT_BASE + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + @ check low interrupts + ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF] + ldr \tmp, [\base, #IRQ_MASK_LOW_OFF] + mov \irqnr, #31 + ands \irqstat, \irqstat, \tmp + + @ if no low interrupts set, check high interrupts + ldreq \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF] + ldreq \tmp, [\base, #IRQ_MASK_HIGH_OFF] + moveq \irqnr, #63 + andeqs \irqstat, \irqstat, \tmp + + @ find first active interrupt source + clzne \irqstat, \irqstat + subne \irqnr, \irqnr, \irqstat + .endm diff --git a/kernel/arch/arm/mach-dove/include/mach/hardware.h b/kernel/arch/arm/mach-dove/include/mach/hardware.h new file mode 100644 index 000000000..f1368b9a8 --- /dev/null +++ b/kernel/arch/arm/mach-dove/include/mach/hardware.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-dove/include/mach/hardware.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include "dove.h" + +/* Macros below are required for compatibility with PXA AC'97 driver. */ +#define __REG(x) (*((volatile u32 *)((x) - DOVE_SB_REGS_PHYS_BASE + \ + DOVE_SB_REGS_VIRT_BASE))) +#define __PREG(x) (((u32)&(x)) - DOVE_SB_REGS_VIRT_BASE + \ + DOVE_SB_REGS_PHYS_BASE) +#endif diff --git a/kernel/arch/arm/mach-dove/include/mach/irqs.h b/kernel/arch/arm/mach-dove/include/mach/irqs.h new file mode 100644 index 000000000..03d401d20 --- /dev/null +++ b/kernel/arch/arm/mach-dove/include/mach/irqs.h @@ -0,0 +1,96 @@ +/* + * arch/arm/mach-dove/include/mach/irqs.h + * + * IRQ definitions for Marvell Dove 88AP510 SoC + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +/* + * Dove Low Interrupt Controller + */ +#define IRQ_DOVE_BRIDGE 0 +#define IRQ_DOVE_H2C 1 +#define IRQ_DOVE_C2H 2 +#define IRQ_DOVE_NAND 3 +#define IRQ_DOVE_PDMA 4 +#define IRQ_DOVE_SPI1 5 +#define IRQ_DOVE_SPI0 6 +#define IRQ_DOVE_UART_0 7 +#define IRQ_DOVE_UART_1 8 +#define IRQ_DOVE_UART_2 9 +#define IRQ_DOVE_UART_3 10 +#define IRQ_DOVE_I2C 11 +#define IRQ_DOVE_GPIO_0_7 12 +#define IRQ_DOVE_GPIO_8_15 13 +#define IRQ_DOVE_GPIO_16_23 14 +#define IRQ_DOVE_PCIE0_ERR 15 +#define IRQ_DOVE_PCIE0 16 +#define IRQ_DOVE_PCIE1_ERR 17 +#define IRQ_DOVE_PCIE1 18 +#define IRQ_DOVE_I2S0 19 +#define IRQ_DOVE_I2S0_ERR 20 +#define IRQ_DOVE_I2S1 21 +#define IRQ_DOVE_I2S1_ERR 22 +#define IRQ_DOVE_USB_ERR 23 +#define IRQ_DOVE_USB0 24 +#define IRQ_DOVE_USB1 25 +#define IRQ_DOVE_GE00_RX 26 +#define IRQ_DOVE_GE00_TX 27 +#define IRQ_DOVE_GE00_MISC 28 +#define IRQ_DOVE_GE00_SUM 29 +#define IRQ_DOVE_GE00_ERR 30 +#define IRQ_DOVE_CRYPTO 31 + +/* + * Dove High Interrupt Controller + */ +#define IRQ_DOVE_AC97 32 +#define IRQ_DOVE_PMU 33 +#define IRQ_DOVE_CAM 34 +#define IRQ_DOVE_SDIO0 35 +#define IRQ_DOVE_SDIO1 36 +#define IRQ_DOVE_SDIO0_WAKEUP 37 +#define IRQ_DOVE_SDIO1_WAKEUP 38 +#define IRQ_DOVE_XOR_00 39 +#define IRQ_DOVE_XOR_01 40 +#define IRQ_DOVE_XOR0_ERR 41 +#define IRQ_DOVE_XOR_10 42 +#define IRQ_DOVE_XOR_11 43 +#define IRQ_DOVE_XOR1_ERR 44 +#define IRQ_DOVE_LCD_DCON 45 +#define IRQ_DOVE_LCD1 46 +#define IRQ_DOVE_LCD0 47 +#define IRQ_DOVE_GPU 48 +#define IRQ_DOVE_PERFORM_MNTR 49 +#define IRQ_DOVE_VPRO_DMA1 51 +#define IRQ_DOVE_SSP_TIMER 54 +#define IRQ_DOVE_SSP 55 +#define IRQ_DOVE_MC_L2_ERR 56 +#define IRQ_DOVE_CRYPTO_ERR 59 +#define IRQ_DOVE_GPIO_24_31 60 +#define IRQ_DOVE_HIGH_GPIO 61 +#define IRQ_DOVE_SATA 62 + +/* + * DOVE General Purpose Pins + */ +#define IRQ_DOVE_GPIO_START 64 +#define NR_GPIO_IRQS 64 + +/* + * PMU interrupts + */ +#define IRQ_DOVE_PMU_START (IRQ_DOVE_GPIO_START + NR_GPIO_IRQS) +#define NR_PMU_IRQS 7 +#define IRQ_DOVE_RTC (IRQ_DOVE_PMU_START + 5) + +#define NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS) + + +#endif diff --git a/kernel/arch/arm/mach-dove/include/mach/pm.h b/kernel/arch/arm/mach-dove/include/mach/pm.h new file mode 100644 index 000000000..b47f75038 --- /dev/null +++ b/kernel/arch/arm/mach-dove/include/mach/pm.h @@ -0,0 +1,72 @@ +/* + * arch/arm/mach-dove/include/mach/pm.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_PM_H +#define __ASM_ARCH_PM_H + +#include <asm/errno.h> +#include <mach/irqs.h> + +#define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38) +#define CLOCK_GATING_BIT_USB0 0 +#define CLOCK_GATING_BIT_USB1 1 +#define CLOCK_GATING_BIT_GBE 2 +#define CLOCK_GATING_BIT_SATA 3 +#define CLOCK_GATING_BIT_PCIE0 4 +#define CLOCK_GATING_BIT_PCIE1 5 +#define CLOCK_GATING_BIT_SDIO0 8 +#define CLOCK_GATING_BIT_SDIO1 9 +#define CLOCK_GATING_BIT_NAND 10 +#define CLOCK_GATING_BIT_CAMERA 11 +#define CLOCK_GATING_BIT_I2S0 12 +#define CLOCK_GATING_BIT_I2S1 13 +#define CLOCK_GATING_BIT_CRYPTO 15 +#define CLOCK_GATING_BIT_AC97 21 +#define CLOCK_GATING_BIT_PDMA 22 +#define CLOCK_GATING_BIT_XOR0 23 +#define CLOCK_GATING_BIT_XOR1 24 +#define CLOCK_GATING_BIT_GIGA_PHY 30 +#define CLOCK_GATING_USB0_MASK (1 << CLOCK_GATING_BIT_USB0) +#define CLOCK_GATING_USB1_MASK (1 << CLOCK_GATING_BIT_USB1) +#define CLOCK_GATING_GBE_MASK (1 << CLOCK_GATING_BIT_GBE) +#define CLOCK_GATING_SATA_MASK (1 << CLOCK_GATING_BIT_SATA) +#define CLOCK_GATING_PCIE0_MASK (1 << CLOCK_GATING_BIT_PCIE0) +#define CLOCK_GATING_PCIE1_MASK (1 << CLOCK_GATING_BIT_PCIE1) +#define CLOCK_GATING_SDIO0_MASK (1 << CLOCK_GATING_BIT_SDIO0) +#define CLOCK_GATING_SDIO1_MASK (1 << CLOCK_GATING_BIT_SDIO1) +#define CLOCK_GATING_NAND_MASK (1 << CLOCK_GATING_BIT_NAND) +#define CLOCK_GATING_CAMERA_MASK (1 << CLOCK_GATING_BIT_CAMERA) +#define CLOCK_GATING_I2S0_MASK (1 << CLOCK_GATING_BIT_I2S0) +#define CLOCK_GATING_I2S1_MASK (1 << CLOCK_GATING_BIT_I2S1) +#define CLOCK_GATING_CRYPTO_MASK (1 << CLOCK_GATING_BIT_CRYPTO) +#define CLOCK_GATING_AC97_MASK (1 << CLOCK_GATING_BIT_AC97) +#define CLOCK_GATING_PDMA_MASK (1 << CLOCK_GATING_BIT_PDMA) +#define CLOCK_GATING_XOR0_MASK (1 << CLOCK_GATING_BIT_XOR0) +#define CLOCK_GATING_XOR1_MASK (1 << CLOCK_GATING_BIT_XOR1) +#define CLOCK_GATING_GIGA_PHY_MASK (1 << CLOCK_GATING_BIT_GIGA_PHY) + +#define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50) +#define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54) + +static inline int pmu_to_irq(int pin) +{ + if (pin < NR_PMU_IRQS) + return pin + IRQ_DOVE_PMU_START; + + return -EINVAL; +} + +static inline int irq_to_pmu(int irq) +{ + if (IRQ_DOVE_PMU_START <= irq && irq < NR_IRQS) + return irq - IRQ_DOVE_PMU_START; + + return -EINVAL; +} + +#endif diff --git a/kernel/arch/arm/mach-dove/include/mach/uncompress.h b/kernel/arch/arm/mach-dove/include/mach/uncompress.h new file mode 100644 index 000000000..5c8ae9b9d --- /dev/null +++ b/kernel/arch/arm/mach-dove/include/mach/uncompress.h @@ -0,0 +1,36 @@ +/* + * arch/arm/mach-dove/include/mach/uncompress.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <mach/dove.h> + +#define UART_THR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x0)) +#define UART_LSR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x14)) + +#define LSR_THRE 0x20 + +static void putc(const char c) +{ + int i; + + for (i = 0; i < 0x1000; i++) { + /* Transmit fifo not full? */ + if (*UART_LSR & LSR_THRE) + break; + } + + *UART_THR = c; +} + +static void flush(void) +{ +} + +/* + * nothing to do + */ +#define arch_decomp_setup() diff --git a/kernel/arch/arm/mach-dove/irq.c b/kernel/arch/arm/mach-dove/irq.c new file mode 100644 index 000000000..4a5a7aedc --- /dev/null +++ b/kernel/arch/arm/mach-dove/irq.c @@ -0,0 +1,178 @@ +/* + * arch/arm/mach-dove/irq.c + * + * Dove IRQ handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/gpio.h> +#include <linux/io.h> +#include <asm/mach/arch.h> +#include <plat/irq.h> +#include <asm/mach/irq.h> +#include <mach/pm.h> +#include <mach/bridge-regs.h> +#include <plat/orion-gpio.h> +#include "common.h" + +static void pmu_irq_mask(struct irq_data *d) +{ + int pin = irq_to_pmu(d->irq); + u32 u; + + u = readl(PMU_INTERRUPT_MASK); + u &= ~(1 << (pin & 31)); + writel(u, PMU_INTERRUPT_MASK); +} + +static void pmu_irq_unmask(struct irq_data *d) +{ + int pin = irq_to_pmu(d->irq); + u32 u; + + u = readl(PMU_INTERRUPT_MASK); + u |= 1 << (pin & 31); + writel(u, PMU_INTERRUPT_MASK); +} + +static void pmu_irq_ack(struct irq_data *d) +{ + int pin = irq_to_pmu(d->irq); + u32 u; + + /* + * The PMU mask register is not RW0C: it is RW. This means that + * the bits take whatever value is written to them; if you write + * a '1', you will set the interrupt. + * + * Unfortunately this means there is NO race free way to clear + * these interrupts. + * + * So, let's structure the code so that the window is as small as + * possible. + */ + u = ~(1 << (pin & 31)); + u &= readl_relaxed(PMU_INTERRUPT_CAUSE); + writel_relaxed(u, PMU_INTERRUPT_CAUSE); +} + +static struct irq_chip pmu_irq_chip = { + .name = "pmu_irq", + .irq_mask = pmu_irq_mask, + .irq_unmask = pmu_irq_unmask, + .irq_ack = pmu_irq_ack, +}; + +static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + unsigned long cause = readl(PMU_INTERRUPT_CAUSE); + + cause &= readl(PMU_INTERRUPT_MASK); + if (cause == 0) { + do_bad_IRQ(irq, desc); + return; + } + + for (irq = 0; irq < NR_PMU_IRQS; irq++) { + if (!(cause & (1 << irq))) + continue; + irq = pmu_to_irq(irq); + generic_handle_irq(irq); + } +} + +static int __initdata gpio0_irqs[4] = { + IRQ_DOVE_GPIO_0_7, + IRQ_DOVE_GPIO_8_15, + IRQ_DOVE_GPIO_16_23, + IRQ_DOVE_GPIO_24_31, +}; + +static int __initdata gpio1_irqs[4] = { + IRQ_DOVE_HIGH_GPIO, + 0, + 0, + 0, +}; + +static int __initdata gpio2_irqs[4] = { + 0, + 0, + 0, + 0, +}; + +#ifdef CONFIG_MULTI_IRQ_HANDLER +/* + * Compiling with both non-DT and DT support enabled, will + * break asm irq handler used by non-DT boards. Therefore, + * we provide a C-style irq handler even for non-DT boards, + * if MULTI_IRQ_HANDLER is set. + */ + +static void __iomem *dove_irq_base = IRQ_VIRT_BASE; + +static asmlinkage void +__exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs) +{ + u32 stat; + + stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF); + stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF); + if (stat) { + unsigned int hwirq = __fls(stat); + handle_IRQ(hwirq, regs); + return; + } + stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF); + stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF); + if (stat) { + unsigned int hwirq = 32 + __fls(stat); + handle_IRQ(hwirq, regs); + return; + } +} +#endif + +void __init dove_init_irq(void) +{ + int i; + + orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); + orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); + +#ifdef CONFIG_MULTI_IRQ_HANDLER + set_handle_irq(dove_legacy_handle_irq); +#endif + + /* + * Initialize gpiolib for GPIOs 0-71. + */ + orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, + IRQ_DOVE_GPIO_START, gpio0_irqs); + + orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, + IRQ_DOVE_GPIO_START + 32, gpio1_irqs); + + orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0, + IRQ_DOVE_GPIO_START + 64, gpio2_irqs); + + /* + * Mask and clear PMU interrupts + */ + writel(0, PMU_INTERRUPT_MASK); + writel(0, PMU_INTERRUPT_CAUSE); + + for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { + irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq); + irq_set_status_flags(i, IRQ_LEVEL); + set_irq_flags(i, IRQF_VALID); + } + irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); +} diff --git a/kernel/arch/arm/mach-dove/mpp.c b/kernel/arch/arm/mach-dove/mpp.c new file mode 100644 index 000000000..8a433a512 --- /dev/null +++ b/kernel/arch/arm/mach-dove/mpp.c @@ -0,0 +1,162 @@ +/* + * arch/arm/mach-dove/mpp.c + * + * MPP functions for Marvell Dove SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/gpio.h> +#include <linux/io.h> +#include <plat/mpp.h> +#include <mach/dove.h> +#include <plat/orion-gpio.h> +#include "mpp.h" + +struct dove_mpp_grp { + int start; + int end; +}; + +/* Map a group to a range of GPIO pins in that group */ +static const struct dove_mpp_grp dove_mpp_grp[] = { + [MPP_24_39] = { + .start = 24, + .end = 39, + }, + [MPP_40_45] = { + .start = 40, + .end = 45, + }, + [MPP_46_51] = { + .start = 46, + .end = 51, + }, + [MPP_58_61] = { + .start = 58, + .end = 61, + }, + [MPP_62_63] = { + .start = 62, + .end = 63, + }, +}; + +/* Enable gpio for a range of pins. mode should be a combination of + GPIO_OUTPUT_OK | GPIO_INPUT_OK */ +static void __init dove_mpp_gpio_mode(int start, int end, int gpio_mode) +{ + int i; + + for (i = start; i <= end; i++) + orion_gpio_set_valid(i, gpio_mode); +} + +/* Dump all the extra MPP registers. The platform code will dump the + registers for pins 0-23. */ +static void __init dove_mpp_dump_regs(void) +{ + pr_debug("PMU_CTRL4_CTRL: %08x\n", + readl(DOVE_MPP_CTRL4_VIRT_BASE)); + + pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", + readl(DOVE_PMU_MPP_GENERAL_CTRL)); + + pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE)); +} + +static void __init dove_mpp_cfg_nfc(int sel) +{ + u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE); + + mpp_gen_cfg &= ~0x1; + mpp_gen_cfg |= sel; + writel(mpp_gen_cfg, DOVE_MPP_GENERAL_VIRT_BASE); + + dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK); +} + +static void __init dove_mpp_cfg_au1(int sel) +{ + u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); + u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1); + u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE); + u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2); + + mpp_ctrl4 &= ~(DOVE_AU1_GPIO_SEL); + ssp_ctrl1 &= ~(DOVE_SSP_ON_AU1); + mpp_gen_ctrl &= ~(DOVE_AU1_SPDIFO_GPIO_EN); + global_cfg_2 &= ~(DOVE_TWSI_OPTION3_GPIO); + + if (!sel || sel == 0x2) + dove_mpp_gpio_mode(52, 57, 0); + else + dove_mpp_gpio_mode(52, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK); + + if (sel & 0x1) { + global_cfg_2 |= DOVE_TWSI_OPTION3_GPIO; + dove_mpp_gpio_mode(56, 57, 0); + } + if (sel & 0x2) { + mpp_gen_ctrl |= DOVE_AU1_SPDIFO_GPIO_EN; + dove_mpp_gpio_mode(57, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK); + } + if (sel & 0x4) { + ssp_ctrl1 |= DOVE_SSP_ON_AU1; + dove_mpp_gpio_mode(52, 55, 0); + } + if (sel & 0x8) + mpp_ctrl4 |= DOVE_AU1_GPIO_SEL; + + writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE); + writel(ssp_ctrl1, DOVE_SSP_CTRL_STATUS_1); + writel(mpp_gen_ctrl, DOVE_MPP_GENERAL_VIRT_BASE); + writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2); +} + +/* Configure the group registers, enabling GPIO if sel indicates the + pin is to be used for GPIO */ +static void __init dove_mpp_conf_grp(unsigned int *mpp_grp_list) +{ + u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); + int gpio_mode; + + for ( ; *mpp_grp_list; mpp_grp_list++) { + unsigned int num = MPP_NUM(*mpp_grp_list); + unsigned int sel = MPP_SEL(*mpp_grp_list); + + if (num > MPP_GRP_MAX) { + pr_err("dove: invalid MPP GRP number (%u)\n", num); + continue; + } + + mpp_ctrl4 &= ~(0x1 << num); + mpp_ctrl4 |= sel << num; + + gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0; + dove_mpp_gpio_mode(dove_mpp_grp[num].start, + dove_mpp_grp[num].end, gpio_mode); + } + writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE); +} + +/* Configure the various MPP pins on Dove */ +void __init dove_mpp_conf(unsigned int *mpp_list, + unsigned int *mpp_grp_list, + unsigned int grp_au1_52_57, + unsigned int grp_nfc_64_71) +{ + dove_mpp_dump_regs(); + + /* Use platform code for pins 0-23 */ + orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE); + + dove_mpp_conf_grp(mpp_grp_list); + dove_mpp_cfg_au1(grp_au1_52_57); + dove_mpp_cfg_nfc(grp_nfc_64_71); + + dove_mpp_dump_regs(); +} diff --git a/kernel/arch/arm/mach-dove/mpp.h b/kernel/arch/arm/mach-dove/mpp.h new file mode 100644 index 000000000..fbec7c52b --- /dev/null +++ b/kernel/arch/arm/mach-dove/mpp.h @@ -0,0 +1,196 @@ +#ifndef __ARCH_DOVE_MPP_CODED_H +#define __ARCH_DOVE_MPP_CODED_H + +#define MPP(_num, _sel, _in, _out) ( \ + /* MPP number */ ((_num) & 0xff) | \ + /* MPP select value */ (((_sel) & 0xf) << 8) | \ + /* may be input signal */ ((!!(_in)) << 12) | \ + /* may be output signal */ ((!!(_out)) << 13)) + +#define MPP0_GPIO0 MPP(0, 0x0, 1, 1) +#define MPP0_UA2_RTSn MPP(0, 0x2, 0, 0) +#define MPP0_SDIO0_CD MPP(0, 0x3, 0, 0) +#define MPP0_LCD0_PWM MPP(0, 0xf, 0, 0) + +#define MPP1_GPIO1 MPP(1, 0x0, 1, 1) +#define MPP1_UA2_CTSn MPP(1, 0x2, 0, 0) +#define MPP1_SDIO0_WP MPP(1, 0x3, 0, 0) +#define MPP1_LCD1_PWM MPP(1, 0xf, 0, 0) + +#define MPP2_GPIO2 MPP(2, 0x0, 1, 1) +#define MPP2_SATA_PRESENT MPP(2, 0x1, 0, 0) +#define MPP2_UA2_TXD MPP(2, 0x2, 0, 0) +#define MPP2_SDIO0_BUS_POWER MPP(2, 0x3, 0, 0) +#define MPP2_UA_RTSn1 MPP(2, 0x4, 0, 0) + +#define MPP3_GPIO3 MPP(3, 0x0, 1, 1) +#define MPP3_SATA_ACT MPP(3, 0x1, 0, 0) +#define MPP3_UA2_RXD MPP(3, 0x2, 0, 0) +#define MPP3_SDIO0_LED_CTRL MPP(3, 0x3, 0, 0) +#define MPP3_UA_CTSn1 MPP(3, 0x4, 0, 0) +#define MPP3_SPI_LCD_CS1 MPP(3, 0xf, 0, 0) + +#define MPP4_GPIO4 MPP(4, 0x0, 1, 1) +#define MPP4_UA3_RTSn MPP(4, 0x2, 0, 0) +#define MPP4_SDIO1_CD MPP(4, 0x3, 0, 0) +#define MPP4_SPI_1_MISO MPP(4, 0x4, 0, 0) + +#define MPP5_GPIO5 MPP(5, 0x0, 1, 1) +#define MPP5_UA3_CTSn MPP(5, 0x2, 0, 0) +#define MPP5_SDIO1_WP MPP(5, 0x3, 0, 0) +#define MPP5_SPI_1_CS MPP(5, 0x4, 0, 0) + +#define MPP6_GPIO6 MPP(6, 0x0, 1, 1) +#define MPP6_UA3_TXD MPP(6, 0x2, 0, 0) +#define MPP6_SDIO1_BUS_POWER MPP(6, 0x3, 0, 0) +#define MPP6_SPI_1_MOSI MPP(6, 0x4, 0, 0) + +#define MPP7_GPIO7 MPP(7, 0x0, 1, 1) +#define MPP7_UA3_RXD MPP(7, 0x2, 0, 0) +#define MPP7_SDIO1_LED_CTRL MPP(7, 0x3, 0, 0) +#define MPP7_SPI_1_SCK MPP(7, 0x4, 0, 0) + +#define MPP8_GPIO8 MPP(8, 0x0, 1, 1) +#define MPP8_WD_RST_OUT MPP(8, 0x1, 0, 0) + +#define MPP9_GPIO9 MPP(9, 0x0, 1, 1) +#define MPP9_PEX1_CLKREQn MPP(9, 0x5, 0, 0) + +#define MPP10_GPIO10 MPP(10, 0x0, 1, 1) +#define MPP10_SSP_SCLK MPP(10, 0x5, 0, 0) + +#define MPP11_GPIO11 MPP(11, 0x0, 1, 1) +#define MPP11_SATA_PRESENT MPP(11, 0x1, 0, 0) +#define MPP11_SATA_ACT MPP(11, 0x2, 0, 0) +#define MPP11_SDIO0_LED_CTRL MPP(11, 0x3, 0, 0) +#define MPP11_SDIO1_LED_CTRL MPP(11, 0x4, 0, 0) +#define MPP11_PEX0_CLKREQn MPP(11, 0x5, 0, 0) + +#define MPP12_GPIO12 MPP(12, 0x0, 1, 1) +#define MPP12_SATA_ACT MPP(12, 0x1, 0, 0) +#define MPP12_UA2_RTSn MPP(12, 0x2, 0, 0) +#define MPP12_AD0_I2S_EXT_MCLK MPP(12, 0x3, 0, 0) +#define MPP12_SDIO1_CD MPP(12, 0x4, 0, 0) + +#define MPP13_GPIO13 MPP(13, 0x0, 1, 1) +#define MPP13_UA2_CTSn MPP(13, 0x2, 0, 0) +#define MPP13_AD1_I2S_EXT_MCLK MPP(13, 0x3, 0, 0) +#define MPP13_SDIO1WP MPP(13, 0x4, 0, 0) +#define MPP13_SSP_EXTCLK MPP(13, 0x5, 0, 0) + +#define MPP14_GPIO14 MPP(14, 0x0, 1, 1) +#define MPP14_UA2_TXD MPP(14, 0x2, 0, 0) +#define MPP14_SDIO1_BUS_POWER MPP(14, 0x4, 0, 0) +#define MPP14_SSP_RXD MPP(14, 0x5, 0, 0) + +#define MPP15_GPIO15 MPP(15, 0x0, 1, 1) +#define MPP15_UA2_RXD MPP(15, 0x2, 0, 0) +#define MPP15_SDIO1_LED_CTRL MPP(15, 0x4, 0, 0) +#define MPP15_SSP_SFRM MPP(15, 0x5, 0, 0) + +#define MPP16_GPIO16 MPP(16, 0x0, 1, 1) +#define MPP16_UA3_RTSn MPP(16, 0x2, 0, 0) +#define MPP16_SDIO0_CD MPP(16, 0x3, 0, 0) +#define MPP16_SPI_LCD_CS1 MPP(16, 0x4, 0, 0) +#define MPP16_AC97_SDATA_IN1 MPP(16, 0x5, 0, 0) + +#define MPP17_GPIO17 MPP(17, 0x0, 1, 1) +#define MPP17_AC97_SYSCLK_OUT MPP(17, 0x1, 0, 0) +#define MPP17_UA3_CTSn MPP(17, 0x2, 0, 0) +#define MPP17_SDIO0_WP MPP(17, 0x3, 0, 0) +#define MPP17_TW_SDA2 MPP(17, 0x4, 0, 0) +#define MPP17_AC97_SDATA_IN2 MPP(17, 0x5, 0, 0) + +#define MPP18_GPIO18 MPP(18, 0x0, 1, 1) +#define MPP18_UA3_TXD MPP(18, 0x2, 0, 0) +#define MPP18_SDIO0_BUS_POWER MPP(18, 0x3, 0, 0) +#define MPP18_LCD0_PWM MPP(18, 0x4, 0, 0) +#define MPP18_AC_SDATA_IN3 MPP(18, 0x5, 0, 0) + +#define MPP19_GPIO19 MPP(19, 0x0, 1, 1) +#define MPP19_UA3_RXD MPP(19, 0x2, 0, 0) +#define MPP19_SDIO0_LED_CTRL MPP(19, 0x3, 0, 0) +#define MPP19_TW_SCK2 MPP(19, 0x4, 0, 0) + +#define MPP20_GPIO20 MPP(20, 0x0, 1, 1) +#define MPP20_AC97_SYSCLK_OUT MPP(20, 0x1, 0, 0) +#define MPP20_SPI_LCD_MISO MPP(20, 0x2, 0, 0) +#define MPP20_SDIO1_CD MPP(20, 0x3, 0, 0) +#define MPP20_SDIO0_CD MPP(20, 0x5, 0, 0) +#define MPP20_SPI_1_MISO MPP(20, 0x6, 0, 0) + +#define MPP21_GPIO21 MPP(21, 0x0, 1, 1) +#define MPP21_UA1_RTSn MPP(21, 0x1, 0, 0) +#define MPP21_SPI_LCD_CS0 MPP(21, 0x2, 0, 0) +#define MPP21_SDIO1_WP MPP(21, 0x3, 0, 0) +#define MPP21_SSP_SFRM MPP(21, 0x4, 0, 0) +#define MPP21_SDIO0_WP MPP(21, 0x5, 0, 0) +#define MPP21_SPI_1_CS MPP(21, 0x6, 0, 0) + +#define MPP22_GPIO22 MPP(22, 0x0, 1, 1) +#define MPP22_UA1_CTSn MPP(22, 0x1, 0, 0) +#define MPP22_SPI_LCD_MOSI MPP(22, 0x2, 0, 0) +#define MPP22_SDIO1_BUS_POWER MPP(22, 0x3, 0, 0) +#define MPP22_SSP_TXD MPP(22, 0x4, 0, 0) +#define MPP22_SDIO0_BUS_POWER MPP(22, 0x5, 0, 0) +#define MPP22_SPI_1_MOSI MPP(22, 0x6, 0, 0) + +#define MPP23_GPIO23 MPP(23, 0x0, 1, 1) +#define MPP23_SPI_LCD_SCK MPP(23, 0x2, 0, 0) +#define MPP23_SDIO1_LED_CTRL MPP(23, 0x3, 0, 0) +#define MPP23_SSP_SCLK MPP(23, 0x4, 0, 0) +#define MPP23_SDIO0_LED_CTRL MPP(23, 0x5, 0, 0) +#define MPP23_SPI_1_SCK MPP(23, 0x6, 0, 0) + +#define MPP_MAX 23 + +#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 0) + +/* for MPP groups _num is a group index */ +enum dove_mpp_grp_idx { + MPP_24_39 = 2, + MPP_40_45 = 0, + MPP_46_51 = 1, + MPP_58_61 = 5, + MPP_62_63 = 4, + MPP_GRP_MAX = 5, +}; + +#define MPP_GRP_24_39_GPIO MPP_GRP(MPP_24_39, 0x1) +#define MPP_GRP_24_39_CAM MPP_GRP(MPP_24_39, 0x0) + +#define MPP_GRP_40_45_GPIO MPP_GRP(MPP_40_45, 0x1) +#define MPP_GRP_40_45_SD0 MPP_GRP(MPP_40_45, 0x0) + +#define MPP_GRP_46_51_GPIO MPP_GRP(MPP_46_51, 0x1) +#define MPP_GRP_46_51_SD1 MPP_GRP(MPP_46_51, 0x0) + +#define MPP_GRP_58_61_GPIO MPP_GRP(MPP_58_61, 0x1) +#define MPP_GRP_58_61_SPI MPP_GRP(MPP_58_61, 0x0) + +#define MPP_GRP_62_63_GPIO MPP_GRP(MPP_62_63, 0x1) +#define MPP_GRP_62_63_UA1 MPP_GRP(MPP_62_63, 0x0) + +/* The MPP[64:71] control differs from other groups */ +#define MPP_GRP_NFC_64_71_GPO 0x1 +#define MPP_GRP_NFC_64_71_NFC 0x0 + +/* + * The MPP[52:57] functionality is encoded by 4 bits in different + * registers. The _num field in this case encodes those bits in + * correspodence with Table 135 of 88AP510 Functional specification + */ +#define MPP_GRP_AU1_52_57_AU1 0x0 +#define MPP_GRP_AU1_52_57_AU1_GPIO57 0x2 +#define MPP_GRP_AU1_52_57_GPIO 0xa +#define MPP_GRP_AU1_52_57_TW_GPIO 0xb +#define MPP_GRP_AU1_52_57_AU1_SSP 0xc +#define MPP_GRP_AU1_52_57_SSP_GPIO 0xe +#define MPP_GRP_AU1_52_57_SSP_TW 0xf + +void dove_mpp_conf(unsigned int *mpp_list, + unsigned int *mpp_grp_list, + unsigned int grp_au1_52_57, + unsigned int grp_nfc_64_71); + +#endif /* __ARCH_DOVE_MPP_CODED_H */ diff --git a/kernel/arch/arm/mach-dove/pcie.c b/kernel/arch/arm/mach-dove/pcie.c new file mode 100644 index 000000000..91fe97144 --- /dev/null +++ b/kernel/arch/arm/mach-dove/pcie.c @@ -0,0 +1,216 @@ +/* + * arch/arm/mach-dove/pcie.c + * + * PCIe functions for Marvell Dove 88AP510 SoC + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/clk.h> +#include <video/vga.h> +#include <asm/mach/pci.h> +#include <asm/mach/arch.h> +#include <asm/setup.h> +#include <asm/delay.h> +#include <plat/pcie.h> +#include <mach/irqs.h> +#include <mach/bridge-regs.h> +#include <plat/addr-map.h> +#include "common.h" + +struct pcie_port { + u8 index; + u8 root_bus_nr; + void __iomem *base; + spinlock_t conf_lock; + char mem_space_name[16]; + struct resource res; +}; + +static struct pcie_port pcie_port[2]; +static int num_pcie_ports; + + +static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) +{ + struct pcie_port *pp; + + if (nr >= num_pcie_ports) + return 0; + + pp = &pcie_port[nr]; + sys->private_data = pp; + pp->root_bus_nr = sys->busnr; + + /* + * Generic PCIe unit setup. + */ + orion_pcie_set_local_bus_nr(pp->base, sys->busnr); + + orion_pcie_setup(pp->base); + + if (pp->index == 0) + pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE); + else + pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE); + + /* + * IORESOURCE_MEM + */ + snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), + "PCIe %d MEM", pp->index); + pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; + pp->res.name = pp->mem_space_name; + if (pp->index == 0) { + pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE; + pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1; + } else { + pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE; + pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1; + } + pp->res.flags = IORESOURCE_MEM; + if (request_resource(&iomem_resource, &pp->res)) + panic("Request PCIe Memory resource failed\n"); + pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); + + return 1; +} + +static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) +{ + /* + * Don't go out when trying to access nonexisting devices + * on the local bus. + */ + if (bus == pp->root_bus_nr && dev > 1) + return 0; + + return 1; +} + +static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, + int size, u32 *val) +{ + struct pci_sys_data *sys = bus->sysdata; + struct pcie_port *pp = sys->private_data; + unsigned long flags; + int ret; + + if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + spin_lock_irqsave(&pp->conf_lock, flags); + ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val); + spin_unlock_irqrestore(&pp->conf_lock, flags); + + return ret; +} + +static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, + int where, int size, u32 val) +{ + struct pci_sys_data *sys = bus->sysdata; + struct pcie_port *pp = sys->private_data; + unsigned long flags; + int ret; + + if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + spin_lock_irqsave(&pp->conf_lock, flags); + ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val); + spin_unlock_irqrestore(&pp->conf_lock, flags); + + return ret; +} + +static struct pci_ops pcie_ops = { + .read = pcie_rd_conf, + .write = pcie_wr_conf, +}; + +static void rc_pci_fixup(struct pci_dev *dev) +{ + /* + * Prevent enumeration of root complex. + */ + if (dev->bus->parent == NULL && dev->devfn == 0) { + int i; + + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { + dev->resource[i].start = 0; + dev->resource[i].end = 0; + dev->resource[i].flags = 0; + } + } +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); + +static struct pci_bus __init * +dove_pcie_scan_bus(int nr, struct pci_sys_data *sys) +{ + if (nr >= num_pcie_ports) { + BUG(); + return NULL; + } + + return pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, + &sys->resources); +} + +static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + struct pci_sys_data *sys = dev->sysdata; + struct pcie_port *pp = sys->private_data; + + return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0; +} + +static struct hw_pci dove_pci __initdata = { + .nr_controllers = 2, + .setup = dove_pcie_setup, + .scan = dove_pcie_scan_bus, + .map_irq = dove_pcie_map_irq, +}; + +static void __init add_pcie_port(int index, void __iomem *base) +{ + printk(KERN_INFO "Dove PCIe port %d: ", index); + + if (orion_pcie_link_up(base)) { + struct pcie_port *pp = &pcie_port[num_pcie_ports++]; + struct clk *clk = clk_get_sys("pcie", (index ? "1" : "0")); + + if (!IS_ERR(clk)) + clk_prepare_enable(clk); + + printk(KERN_INFO "link up\n"); + + pp->index = index; + pp->root_bus_nr = -1; + pp->base = base; + spin_lock_init(&pp->conf_lock); + memset(&pp->res, 0, sizeof(pp->res)); + } else { + printk(KERN_INFO "link down, ignoring\n"); + } +} + +void __init dove_pcie_init(int init_port0, int init_port1) +{ + vga_base = DOVE_PCIE0_MEM_PHYS_BASE; + + if (init_port0) + add_pcie_port(0, DOVE_PCIE0_VIRT_BASE); + + if (init_port1) + add_pcie_port(1, DOVE_PCIE1_VIRT_BASE); + + pci_common_init(&dove_pci); +} |