diff options
Diffstat (limited to 'kernel/arch/arm/mach-davinci/include/mach')
18 files changed, 2417 insertions, 0 deletions
diff --git a/kernel/arch/arm/mach-davinci/include/mach/clock.h b/kernel/arch/arm/mach-davinci/include/mach/clock.h new file mode 100644 index 000000000..3e8af6a0b --- /dev/null +++ b/kernel/arch/arm/mach-davinci/include/mach/clock.h @@ -0,0 +1,24 @@ +/* + * arch/arm/mach-davinci/include/mach/clock.h + * + * Clock control driver for DaVinci - header file + * + * Authors: Vladimir Barinov <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_DAVINCI_CLOCK_H +#define __ASM_ARCH_DAVINCI_CLOCK_H + +struct clk; + +extern int clk_register(struct clk *clk); +extern void clk_unregister(struct clk *clk); + +int davinci_clk_reset_assert(struct clk *c); +int davinci_clk_reset_deassert(struct clk *c); + +#endif diff --git a/kernel/arch/arm/mach-davinci/include/mach/common.h b/kernel/arch/arm/mach-davinci/include/mach/common.h new file mode 100644 index 000000000..0b3c16975 --- /dev/null +++ b/kernel/arch/arm/mach-davinci/include/mach/common.h @@ -0,0 +1,107 @@ +/* + * Header for code common to all DaVinci machines. + * + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H +#define __ARCH_ARM_MACH_DAVINCI_COMMON_H + +#include <linux/compiler.h> +#include <linux/types.h> +#include <linux/reboot.h> + +extern void davinci_timer_init(void); + +extern void davinci_irq_init(void); +extern void __iomem *davinci_intc_base; +extern int davinci_intc_type; + +struct davinci_timer_instance { + u32 base; + u32 bottom_irq; + u32 top_irq; + unsigned long cmp_off; + unsigned int cmp_irq; +}; + +struct davinci_timer_info { + struct davinci_timer_instance *timers; + unsigned int clockevent_id; + unsigned int clocksource_id; +}; + +struct davinci_gpio_controller; + +/* + * SoC info passed into common davinci modules. + * + * Base addresses in this structure should be physical and not virtual. + * Modules that take such base addresses, should internally ioremap() them to + * use. + */ +struct davinci_soc_info { + struct map_desc *io_desc; + unsigned long io_desc_num; + u32 cpu_id; + u32 jtag_id; + u32 jtag_id_reg; + struct davinci_id *ids; + unsigned long ids_num; + struct clk_lookup *cpu_clks; + u32 *psc_bases; + unsigned long psc_bases_num; + u32 pinmux_base; + const struct mux_config *pinmux_pins; + unsigned long pinmux_pins_num; + u32 intc_base; + int intc_type; + u8 *intc_irq_prios; + unsigned long intc_irq_num; + u32 *intc_host_map; + struct davinci_timer_info *timer_info; + int gpio_type; + u32 gpio_base; + unsigned gpio_num; + unsigned gpio_irq; + unsigned gpio_unbanked; + struct davinci_gpio_controller *gpio_ctlrs; + int gpio_ctlrs_num; + struct emac_platform_data *emac_pdata; + dma_addr_t sram_dma; + unsigned sram_len; +}; + +extern struct davinci_soc_info davinci_soc_info; + +extern void davinci_common_init(struct davinci_soc_info *soc_info); +extern void davinci_init_ide(void); +void davinci_restart(enum reboot_mode mode, const char *cmd); +void davinci_init_late(void); + +#ifdef CONFIG_DAVINCI_RESET_CLOCKS +int davinci_clk_disable_unused(void); +#else +static inline int davinci_clk_disable_unused(void) { return 0; } +#endif + +#ifdef CONFIG_CPU_FREQ +int davinci_cpufreq_init(void); +#else +static inline int davinci_cpufreq_init(void) { return 0; } +#endif + +#ifdef CONFIG_SUSPEND +int davinci_pm_init(void); +#else +static inline int davinci_pm_init(void) { return 0; } +#endif + +#define SRAM_SIZE SZ_128K + +#endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */ diff --git a/kernel/arch/arm/mach-davinci/include/mach/cp_intc.h b/kernel/arch/arm/mach-davinci/include/mach/cp_intc.h new file mode 100644 index 000000000..827bbe9ba --- /dev/null +++ b/kernel/arch/arm/mach-davinci/include/mach/cp_intc.h @@ -0,0 +1,57 @@ +/* + * TI Common Platform Interrupt Controller (cp_intc) definitions + * + * Author: Steve Chen <schen@mvista.com> + * Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com> + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ +#ifndef __ASM_HARDWARE_CP_INTC_H +#define __ASM_HARDWARE_CP_INTC_H + +#define CP_INTC_REV 0x00 +#define CP_INTC_CTRL 0x04 +#define CP_INTC_HOST_CTRL 0x0C +#define CP_INTC_GLOBAL_ENABLE 0x10 +#define CP_INTC_GLOBAL_NESTING_LEVEL 0x1C +#define CP_INTC_SYS_STAT_IDX_SET 0x20 +#define CP_INTC_SYS_STAT_IDX_CLR 0x24 +#define CP_INTC_SYS_ENABLE_IDX_SET 0x28 +#define CP_INTC_SYS_ENABLE_IDX_CLR 0x2C +#define CP_INTC_GLOBAL_WAKEUP_ENABLE 0x30 +#define CP_INTC_HOST_ENABLE_IDX_SET 0x34 +#define CP_INTC_HOST_ENABLE_IDX_CLR 0x38 +#define CP_INTC_PACING_PRESCALE 0x40 +#define CP_INTC_VECTOR_BASE 0x50 +#define CP_INTC_VECTOR_SIZE 0x54 +#define CP_INTC_VECTOR_NULL 0x58 +#define CP_INTC_PRIO_IDX 0x80 +#define CP_INTC_PRIO_VECTOR 0x84 +#define CP_INTC_SECURE_ENABLE 0x90 +#define CP_INTC_SECURE_PRIO_IDX 0x94 +#define CP_INTC_PACING_PARAM(n) (0x0100 + (n << 4)) +#define CP_INTC_PACING_DEC(n) (0x0104 + (n << 4)) +#define CP_INTC_PACING_MAP(n) (0x0108 + (n << 4)) +#define CP_INTC_SYS_RAW_STAT(n) (0x0200 + (n << 2)) +#define CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2)) +#define CP_INTC_SYS_ENABLE_SET(n) (0x0300 + (n << 2)) +#define CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2)) +#define CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2)) +#define CP_INTC_HOST_MAP(n) (0x0800 + (n << 2)) +#define CP_INTC_HOST_PRIO_IDX(n) (0x0900 + (n << 2)) +#define CP_INTC_SYS_POLARITY(n) (0x0D00 + (n << 2)) +#define CP_INTC_SYS_TYPE(n) (0x0D80 + (n << 2)) +#define CP_INTC_WAKEUP_ENABLE(n) (0x0E00 + (n << 2)) +#define CP_INTC_DEBUG_SELECT(n) (0x0F00 + (n << 2)) +#define CP_INTC_SYS_SECURE_ENABLE(n) (0x1000 + (n << 2)) +#define CP_INTC_HOST_NESTING_LEVEL(n) (0x1100 + (n << 2)) +#define CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2)) +#define CP_INTC_HOST_PRIO_VECTOR(n) (0x1600 + (n << 2)) +#define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2)) + +void cp_intc_init(void); +int cp_intc_of_init(struct device_node *, struct device_node *); + +#endif /* __ASM_HARDWARE_CP_INTC_H */ diff --git a/kernel/arch/arm/mach-davinci/include/mach/cpufreq.h b/kernel/arch/arm/mach-davinci/include/mach/cpufreq.h new file mode 100644 index 000000000..3c089cfb6 --- /dev/null +++ b/kernel/arch/arm/mach-davinci/include/mach/cpufreq.h @@ -0,0 +1,26 @@ +/* + * TI DaVinci CPUFreq platform support. + * + * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef _MACH_DAVINCI_CPUFREQ_H +#define _MACH_DAVINCI_CPUFREQ_H + +#include <linux/cpufreq.h> + +struct davinci_cpufreq_config { + struct cpufreq_frequency_table *freq_table; + int (*set_voltage) (unsigned int index); + int (*init) (void); +}; + +#endif diff --git a/kernel/arch/arm/mach-davinci/include/mach/cpuidle.h b/kernel/arch/arm/mach-davinci/include/mach/cpuidle.h new file mode 100644 index 000000000..74f088b0e --- /dev/null +++ b/kernel/arch/arm/mach-davinci/include/mach/cpuidle.h @@ -0,0 +1,18 @@ +/* + * TI DaVinci cpuidle platform support + * + * 2009 (C) Texas Instruments, Inc. http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ +#ifndef _MACH_DAVINCI_CPUIDLE_H +#define _MACH_DAVINCI_CPUIDLE_H + +struct davinci_cpuidle_config { + u32 ddr2_pdown; + void __iomem *ddr2_ctlr_base; +}; + +#endif diff --git a/kernel/arch/arm/mach-davinci/include/mach/cputype.h b/kernel/arch/arm/mach-davinci/include/mach/cputype.h new file mode 100644 index 000000000..1fc84e216 --- /dev/null +++ b/kernel/arch/arm/mach-davinci/include/mach/cputype.h @@ -0,0 +1,86 @@ +/* + * DaVinci CPU type detection + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * Defines the cpu_is_*() macros for runtime detection of DaVinci + * device type. In addition, if support for a given device is not + * compiled in to the kernel, the macros return 0 so that + * resulting code can be optimized out. + * + * 2009 (c) Deep Root Systems, LLC. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef _ASM_ARCH_CPU_H +#define _ASM_ARCH_CPU_H + +#include <mach/common.h> + +struct davinci_id { + u8 variant; /* JTAG ID bits 31:28 */ + u16 part_no; /* JTAG ID bits 27:12 */ + u16 manufacturer; /* JTAG ID bits 11:1 */ + u32 cpu_id; + char *name; +}; + +/* Can use lower 16 bits of cpu id for a variant when required */ +#define DAVINCI_CPU_ID_DM6446 0x64460000 +#define DAVINCI_CPU_ID_DM6467 0x64670000 +#define DAVINCI_CPU_ID_DM355 0x03550000 +#define DAVINCI_CPU_ID_DM365 0x03650000 +#define DAVINCI_CPU_ID_DA830 0x08300000 +#define DAVINCI_CPU_ID_DA850 0x08500000 + +#define IS_DAVINCI_CPU(type, id) \ +static inline int is_davinci_ ##type(void) \ +{ \ + return (davinci_soc_info.cpu_id == (id)); \ +} + +IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446) +IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467) +IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) +IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365) +IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830) +IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850) + +#ifdef CONFIG_ARCH_DAVINCI_DM644x +#define cpu_is_davinci_dm644x() is_davinci_dm644x() +#else +#define cpu_is_davinci_dm644x() 0 +#endif + +#ifdef CONFIG_ARCH_DAVINCI_DM646x +#define cpu_is_davinci_dm646x() is_davinci_dm646x() +#else +#define cpu_is_davinci_dm646x() 0 +#endif + +#ifdef CONFIG_ARCH_DAVINCI_DM355 +#define cpu_is_davinci_dm355() is_davinci_dm355() +#else +#define cpu_is_davinci_dm355() 0 +#endif + +#ifdef CONFIG_ARCH_DAVINCI_DM365 +#define cpu_is_davinci_dm365() is_davinci_dm365() +#else +#define cpu_is_davinci_dm365() 0 +#endif + +#ifdef CONFIG_ARCH_DAVINCI_DA830 +#define cpu_is_davinci_da830() is_davinci_da830() +#else +#define cpu_is_davinci_da830() 0 +#endif + +#ifdef CONFIG_ARCH_DAVINCI_DA850 +#define cpu_is_davinci_da850() is_davinci_da850() +#else +#define cpu_is_davinci_da850() 0 +#endif + +#endif diff --git a/kernel/arch/arm/mach-davinci/include/mach/da8xx.h b/kernel/arch/arm/mach-davinci/include/mach/da8xx.h new file mode 100644 index 000000000..39e58b48e --- /dev/null +++ b/kernel/arch/arm/mach-davinci/include/mach/da8xx.h @@ -0,0 +1,154 @@ +/* + * Chip specific defines for DA8XX/OMAP L1XX SoC + * + * Author: Mark A. Greer <mgreer@mvista.com> + * + * 2007, 2009-2010 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_DAVINCI_DA8XX_H +#define __ASM_ARCH_DAVINCI_DA8XX_H + +#include <video/da8xx-fb.h> + +#include <linux/platform_device.h> +#include <linux/davinci_emac.h> +#include <linux/spi/spi.h> +#include <linux/platform_data/davinci_asp.h> +#include <linux/reboot.h> +#include <linux/videodev2.h> + +#include <mach/serial.h> +#include <mach/pm.h> +#include <linux/platform_data/edma.h> +#include <linux/platform_data/i2c-davinci.h> +#include <linux/platform_data/mmc-davinci.h> +#include <linux/platform_data/usb-davinci.h> +#include <linux/platform_data/spi-davinci.h> +#include <linux/platform_data/uio_pruss.h> + +#include <media/davinci/vpif_types.h> + +extern void __iomem *da8xx_syscfg0_base; +extern void __iomem *da8xx_syscfg1_base; + +/* + * If the DA850/OMAP-L138/AM18x SoC on board is of a higher speed grade + * (than the regular 300Mhz variant), the board code should set this up + * with the supported speed before calling da850_register_cpufreq(). + */ +extern unsigned int da850_max_speed; + +/* + * The cp_intc interrupt controller for the da8xx isn't in the same + * chunk of physical memory space as the other registers (like it is + * on the davincis) so it needs to be mapped separately. It will be + * mapped early on when the I/O space is mapped and we'll put it just + * before the I/O space in the processor's virtual memory space. + */ +#define DA8XX_CP_INTC_BASE 0xfffee000 +#define DA8XX_CP_INTC_SIZE SZ_8K +#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K) + +#define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000) +#define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x)) +#define DA8XX_JTAG_ID_REG 0x18 +#define DA8XX_HOST1CFG_REG 0x44 +#define DA8XX_CHIPSIG_REG 0x174 +#define DA8XX_CFGCHIP0_REG 0x17c +#define DA8XX_CFGCHIP1_REG 0x180 +#define DA8XX_CFGCHIP2_REG 0x184 +#define DA8XX_CFGCHIP3_REG 0x188 + +#define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000) +#define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x)) +#define DA8XX_DEEPSLEEP_REG 0x8 +#define DA8XX_PWRDN_REG 0x18 + +#define DA8XX_PSC0_BASE 0x01c10000 +#define DA8XX_PLL0_BASE 0x01c11000 +#define DA8XX_TIMER64P0_BASE 0x01c20000 +#define DA8XX_TIMER64P1_BASE 0x01c21000 +#define DA8XX_VPIF_BASE 0x01e17000 +#define DA8XX_GPIO_BASE 0x01e26000 +#define DA8XX_PSC1_BASE 0x01e27000 +#define DA8XX_AEMIF_CS2_BASE 0x60000000 +#define DA8XX_AEMIF_CS3_BASE 0x62000000 +#define DA8XX_AEMIF_CTL_BASE 0x68000000 +#define DA8XX_SHARED_RAM_BASE 0x80000000 +#define DA8XX_ARM_RAM_BASE 0xffff0000 + +void da830_init(void); +void da850_init(void); + +int da830_register_edma(struct edma_rsv_info *rsv); +int da850_register_edma(struct edma_rsv_info *rsv[2]); +int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); +int da8xx_register_spi_bus(int instance, unsigned num_chipselect); +int da8xx_register_watchdog(void); +int da8xx_register_usb20(unsigned mA, unsigned potpgt); +int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata); +int da8xx_register_emac(void); +int da8xx_register_uio_pruss(void); +int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata); +int da8xx_register_mmcsd0(struct davinci_mmc_config *config); +int da850_register_mmcsd1(struct davinci_mmc_config *config); +void da8xx_register_mcasp(int id, struct snd_platform_data *pdata); +int da8xx_register_rtc(void); +int da8xx_register_gpio(void *pdata); +int da850_register_cpufreq(char *async_clk); +int da8xx_register_cpuidle(void); +void __iomem *da8xx_get_mem_ctlr(void); +int da850_register_pm(struct platform_device *pdev); +int da850_register_sata(unsigned long refclkpn); +int da850_register_vpif(void); +int da850_register_vpif_display + (struct vpif_display_config *display_config); +int da850_register_vpif_capture + (struct vpif_capture_config *capture_config); +void da8xx_restart(enum reboot_mode mode, const char *cmd); +void da8xx_rproc_reserve_cma(void); +int da8xx_register_rproc(void); +int da850_register_gpio(void); +int da830_register_gpio(void); + +extern struct platform_device da8xx_serial_device[]; +extern struct emac_platform_data da8xx_emac_pdata; +extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata; +extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata; + + +extern const short da830_emif25_pins[]; +extern const short da830_spi0_pins[]; +extern const short da830_spi1_pins[]; +extern const short da830_mmc_sd_pins[]; +extern const short da830_uart0_pins[]; +extern const short da830_uart1_pins[]; +extern const short da830_uart2_pins[]; +extern const short da830_usb20_pins[]; +extern const short da830_usb11_pins[]; +extern const short da830_uhpi_pins[]; +extern const short da830_cpgmac_pins[]; +extern const short da830_emif3c_pins[]; +extern const short da830_mcasp0_pins[]; +extern const short da830_mcasp1_pins[]; +extern const short da830_mcasp2_pins[]; +extern const short da830_i2c0_pins[]; +extern const short da830_i2c1_pins[]; +extern const short da830_lcdcntl_pins[]; +extern const short da830_pwm_pins[]; +extern const short da830_ecap0_pins[]; +extern const short da830_ecap1_pins[]; +extern const short da830_ecap2_pins[]; +extern const short da830_eqep0_pins[]; +extern const short da830_eqep1_pins[]; +extern const short da850_vpif_capture_pins[]; +extern const short da850_vpif_display_pins[]; + +extern const short da850_i2c0_pins[]; +extern const short da850_i2c1_pins[]; +extern const short da850_lcdcntl_pins[]; + +#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ diff --git a/kernel/arch/arm/mach-davinci/include/mach/ddr2.h b/kernel/arch/arm/mach-davinci/include/mach/ddr2.h new file mode 100644 index 000000000..c19e047d0 --- /dev/null +++ b/kernel/arch/arm/mach-davinci/include/mach/ddr2.h @@ -0,0 +1,4 @@ +#define DDR2_SDRCR_OFFSET 0xc +#define DDR2_SRPD_BIT (1 << 23) +#define DDR2_MCLKSTOPEN_BIT (1 << 30) +#define DDR2_LPMODEN_BIT (1 << 31) diff --git a/kernel/arch/arm/mach-davinci/include/mach/entry-macro.S b/kernel/arch/arm/mach-davinci/include/mach/entry-macro.S new file mode 100644 index 000000000..cf5f573eb --- /dev/null +++ b/kernel/arch/arm/mach-davinci/include/mach/entry-macro.S @@ -0,0 +1,39 @@ +/* + * Low-level IRQ helper macros for TI DaVinci-based platforms + * + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include <mach/irqs.h> + + .macro get_irqnr_preamble, base, tmp + ldr \base, =davinci_intc_base + ldr \base, [\base] + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp +#if defined(CONFIG_AINTC) && defined(CONFIG_CP_INTC) + ldr \tmp, =davinci_intc_type + ldr \tmp, [\tmp] + cmp \tmp, #DAVINCI_INTC_TYPE_CP_INTC + beq 1001f +#endif +#if defined(CONFIG_AINTC) + ldr \tmp, [\base, #0x14] + movs \tmp, \tmp, lsr #2 + sub \irqnr, \tmp, #1 + b 1002f +#endif +#if defined(CONFIG_CP_INTC) +1001: ldr \irqnr, [\base, #0x80] /* get irq number */ + mov \tmp, \irqnr, lsr #31 + and \irqnr, \irqnr, #0xff /* irq is in bits 0-9 */ + and \tmp, \tmp, #0x1 + cmp \tmp, #0x1 +#endif +1002: + .endm diff --git a/kernel/arch/arm/mach-davinci/include/mach/hardware.h b/kernel/arch/arm/mach-davinci/include/mach/hardware.h new file mode 100644 index 000000000..16bb42291 --- /dev/null +++ b/kernel/arch/arm/mach-davinci/include/mach/hardware.h @@ -0,0 +1,33 @@ +/* + * Hardware definitions common to all DaVinci family processors + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * 2007 (c) Deep Root Systems, LLC. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +/* + * Before you add anything to ths file: + * + * This header is for defines common to ALL DaVinci family chips. + * Anything that is chip specific should go in <chipname>.h, + * and the chip/board init code should then explicitly include + * <chipname>.h + */ +/* + * I/O mapping + */ +#define IO_PHYS UL(0x01c00000) +#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ +#define IO_SIZE 0x00400000 +#define IO_VIRT (IO_PHYS + IO_OFFSET) +#define io_v2p(va) ((va) - IO_OFFSET) +#define __IO_ADDRESS(x) ((x) + IO_OFFSET) +#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa)) + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/kernel/arch/arm/mach-davinci/include/mach/irqs.h b/kernel/arch/arm/mach-davinci/include/mach/irqs.h new file mode 100644 index 000000000..edb2ca623 --- /dev/null +++ b/kernel/arch/arm/mach-davinci/include/mach/irqs.h @@ -0,0 +1,409 @@ +/* + * DaVinci interrupt controller definitions + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +/* Base address */ +#define DAVINCI_ARM_INTC_BASE 0x01C48000 + +#define DAVINCI_INTC_TYPE_AINTC 0 +#define DAVINCI_INTC_TYPE_CP_INTC 1 + +/* Interrupt lines */ +#define IRQ_VDINT0 0 +#define IRQ_VDINT1 1 +#define IRQ_VDINT2 2 +#define IRQ_HISTINT 3 +#define IRQ_H3AINT 4 +#define IRQ_PRVUINT 5 +#define IRQ_RSZINT 6 +#define IRQ_VFOCINT 7 +#define IRQ_VENCINT 8 +#define IRQ_ASQINT 9 +#define IRQ_IMXINT 10 +#define IRQ_VLCDINT 11 +#define IRQ_USBINT 12 +#define IRQ_EMACINT 13 + +#define IRQ_CCINT0 16 +#define IRQ_CCERRINT 17 +#define IRQ_TCERRINT0 18 +#define IRQ_TCERRINT 19 +#define IRQ_PSCIN 20 + +#define IRQ_IDE 22 +#define IRQ_HPIINT 23 +#define IRQ_MBXINT 24 +#define IRQ_MBRINT 25 +#define IRQ_MMCINT 26 +#define IRQ_SDIOINT 27 +#define IRQ_MSINT 28 +#define IRQ_DDRINT 29 +#define IRQ_AEMIFINT 30 +#define IRQ_VLQINT 31 +#define IRQ_TINT0_TINT12 32 +#define IRQ_TINT0_TINT34 33 +#define IRQ_TINT1_TINT12 34 +#define IRQ_TINT1_TINT34 35 +#define IRQ_PWMINT0 36 +#define IRQ_PWMINT1 37 +#define IRQ_PWMINT2 38 +#define IRQ_I2C 39 +#define IRQ_UARTINT0 40 +#define IRQ_UARTINT1 41 +#define IRQ_UARTINT2 42 +#define IRQ_SPINT0 43 +#define IRQ_SPINT1 44 + +#define IRQ_DSP2ARM0 46 +#define IRQ_DSP2ARM1 47 +#define IRQ_GPIO0 48 +#define IRQ_GPIO1 49 +#define IRQ_GPIO2 50 +#define IRQ_GPIO3 51 +#define IRQ_GPIO4 52 +#define IRQ_GPIO5 53 +#define IRQ_GPIO6 54 +#define IRQ_GPIO7 55 +#define IRQ_GPIOBNK0 56 +#define IRQ_GPIOBNK1 57 +#define IRQ_GPIOBNK2 58 +#define IRQ_GPIOBNK3 59 +#define IRQ_GPIOBNK4 60 +#define IRQ_COMMTX 61 +#define IRQ_COMMRX 62 +#define IRQ_EMUINT 63 + +#define DAVINCI_N_AINTC_IRQ 64 + +#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 + +/* DaVinci DM6467-specific Interrupts */ +#define IRQ_DM646X_VP_VERTINT0 0 +#define IRQ_DM646X_VP_VERTINT1 1 +#define IRQ_DM646X_VP_VERTINT2 2 +#define IRQ_DM646X_VP_VERTINT3 3 +#define IRQ_DM646X_VP_ERRINT 4 +#define IRQ_DM646X_RESERVED_1 5 +#define IRQ_DM646X_RESERVED_2 6 +#define IRQ_DM646X_WDINT 7 +#define IRQ_DM646X_CRGENINT0 8 +#define IRQ_DM646X_CRGENINT1 9 +#define IRQ_DM646X_TSIFINT0 10 +#define IRQ_DM646X_TSIFINT1 11 +#define IRQ_DM646X_VDCEINT 12 +#define IRQ_DM646X_USBINT 13 +#define IRQ_DM646X_USBDMAINT 14 +#define IRQ_DM646X_PCIINT 15 +#define IRQ_DM646X_TCERRINT2 20 +#define IRQ_DM646X_TCERRINT3 21 +#define IRQ_DM646X_IDE 22 +#define IRQ_DM646X_HPIINT 23 +#define IRQ_DM646X_EMACRXTHINT 24 +#define IRQ_DM646X_EMACRXINT 25 +#define IRQ_DM646X_EMACTXINT 26 +#define IRQ_DM646X_EMACMISCINT 27 +#define IRQ_DM646X_MCASP0TXINT 28 +#define IRQ_DM646X_MCASP0RXINT 29 +#define IRQ_DM646X_MCASP1TXINT 30 +#define IRQ_DM646X_RESERVED_3 31 +#define IRQ_DM646X_VLQINT 38 +#define IRQ_DM646X_UARTINT2 42 +#define IRQ_DM646X_SPINT0 43 +#define IRQ_DM646X_SPINT1 44 +#define IRQ_DM646X_DSP2ARMINT 45 +#define IRQ_DM646X_RESERVED_4 46 +#define IRQ_DM646X_PSCINT 47 +#define IRQ_DM646X_GPIO0 48 +#define IRQ_DM646X_GPIO1 49 +#define IRQ_DM646X_GPIO2 50 +#define IRQ_DM646X_GPIO3 51 +#define IRQ_DM646X_GPIO4 52 +#define IRQ_DM646X_GPIO5 53 +#define IRQ_DM646X_GPIO6 54 +#define IRQ_DM646X_GPIO7 55 +#define IRQ_DM646X_GPIOBNK0 56 +#define IRQ_DM646X_GPIOBNK1 57 +#define IRQ_DM646X_GPIOBNK2 58 +#define IRQ_DM646X_DDRINT 59 +#define IRQ_DM646X_AEMIFINT 60 + +/* DaVinci DM355-specific Interrupts */ +#define IRQ_DM355_CCDC_VDINT0 0 +#define IRQ_DM355_CCDC_VDINT1 1 +#define IRQ_DM355_CCDC_VDINT2 2 +#define IRQ_DM355_IPIPE_HST 3 +#define IRQ_DM355_H3AINT 4 +#define IRQ_DM355_IPIPE_SDR 5 +#define IRQ_DM355_IPIPEIFINT 6 +#define IRQ_DM355_OSDINT 7 +#define IRQ_DM355_VENCINT 8 +#define IRQ_DM355_IMCOPINT 11 +#define IRQ_DM355_RTOINT 13 +#define IRQ_DM355_TINT4 13 +#define IRQ_DM355_TINT2_TINT12 13 +#define IRQ_DM355_UARTINT2 14 +#define IRQ_DM355_TINT5 14 +#define IRQ_DM355_TINT2_TINT34 14 +#define IRQ_DM355_TINT6 15 +#define IRQ_DM355_TINT3_TINT12 15 +#define IRQ_DM355_SPINT1_0 17 +#define IRQ_DM355_SPINT1_1 18 +#define IRQ_DM355_SPINT2_0 19 +#define IRQ_DM355_SPINT2_1 21 +#define IRQ_DM355_TINT7 22 +#define IRQ_DM355_TINT3_TINT34 22 +#define IRQ_DM355_SDIOINT0 23 +#define IRQ_DM355_MMCINT0 26 +#define IRQ_DM355_MSINT 26 +#define IRQ_DM355_MMCINT1 27 +#define IRQ_DM355_PWMINT3 28 +#define IRQ_DM355_SDIOINT1 31 +#define IRQ_DM355_SPINT0_0 42 +#define IRQ_DM355_SPINT0_1 43 +#define IRQ_DM355_GPIO0 44 +#define IRQ_DM355_GPIO1 45 +#define IRQ_DM355_GPIO2 46 +#define IRQ_DM355_GPIO3 47 +#define IRQ_DM355_GPIO4 48 +#define IRQ_DM355_GPIO5 49 +#define IRQ_DM355_GPIO6 50 +#define IRQ_DM355_GPIO7 51 +#define IRQ_DM355_GPIO8 52 +#define IRQ_DM355_GPIO9 53 +#define IRQ_DM355_GPIOBNK0 54 +#define IRQ_DM355_GPIOBNK1 55 +#define IRQ_DM355_GPIOBNK2 56 +#define IRQ_DM355_GPIOBNK3 57 +#define IRQ_DM355_GPIOBNK4 58 +#define IRQ_DM355_GPIOBNK5 59 +#define IRQ_DM355_GPIOBNK6 60 + +/* DaVinci DM365-specific Interrupts */ +#define IRQ_DM365_INSFINT 7 +#define IRQ_DM365_IMXINT1 8 +#define IRQ_DM365_IMXINT0 10 +#define IRQ_DM365_KLD_ARMINT 10 +#define IRQ_DM365_IMCOPINT 11 +#define IRQ_DM365_RTOINT 13 +#define IRQ_DM365_TINT5 14 +#define IRQ_DM365_TINT6 15 +#define IRQ_DM365_SPINT2_1 21 +#define IRQ_DM365_TINT7 22 +#define IRQ_DM365_SDIOINT0 23 +#define IRQ_DM365_MMCINT1 27 +#define IRQ_DM365_PWMINT3 28 +#define IRQ_DM365_RTCINT 29 +#define IRQ_DM365_SDIOINT1 31 +#define IRQ_DM365_SPIINT0_0 42 +#define IRQ_DM365_SPIINT3_0 43 +#define IRQ_DM365_GPIO0 44 +#define IRQ_DM365_GPIO1 45 +#define IRQ_DM365_GPIO2 46 +#define IRQ_DM365_GPIO3 47 +#define IRQ_DM365_GPIO4 48 +#define IRQ_DM365_GPIO5 49 +#define IRQ_DM365_GPIO6 50 +#define IRQ_DM365_GPIO7 51 +#define IRQ_DM365_EMAC_RXTHRESH 52 +#define IRQ_DM365_EMAC_RXPULSE 53 +#define IRQ_DM365_EMAC_TXPULSE 54 +#define IRQ_DM365_EMAC_MISCPULSE 55 +#define IRQ_DM365_GPIO12 56 +#define IRQ_DM365_GPIO13 57 +#define IRQ_DM365_GPIO14 58 +#define IRQ_DM365_GPIO15 59 +#define IRQ_DM365_ADCINT 59 +#define IRQ_DM365_KEYINT 60 +#define IRQ_DM365_TCERRINT2 61 +#define IRQ_DM365_TCERRINT3 62 +#define IRQ_DM365_EMUINT 63 + +/* DA8XX interrupts */ +#define IRQ_DA8XX_COMMTX 0 +#define IRQ_DA8XX_COMMRX 1 +#define IRQ_DA8XX_NINT 2 +#define IRQ_DA8XX_EVTOUT0 3 +#define IRQ_DA8XX_EVTOUT1 4 +#define IRQ_DA8XX_EVTOUT2 5 +#define IRQ_DA8XX_EVTOUT3 6 +#define IRQ_DA8XX_EVTOUT4 7 +#define IRQ_DA8XX_EVTOUT5 8 +#define IRQ_DA8XX_EVTOUT6 9 +#define IRQ_DA8XX_EVTOUT7 10 +#define IRQ_DA8XX_CCINT0 11 +#define IRQ_DA8XX_CCERRINT 12 +#define IRQ_DA8XX_TCERRINT0 13 +#define IRQ_DA8XX_AEMIFINT 14 +#define IRQ_DA8XX_I2CINT0 15 +#define IRQ_DA8XX_MMCSDINT0 16 +#define IRQ_DA8XX_MMCSDINT1 17 +#define IRQ_DA8XX_ALLINT0 18 +#define IRQ_DA8XX_RTC 19 +#define IRQ_DA8XX_SPINT0 20 +#define IRQ_DA8XX_TINT12_0 21 +#define IRQ_DA8XX_TINT34_0 22 +#define IRQ_DA8XX_TINT12_1 23 +#define IRQ_DA8XX_TINT34_1 24 +#define IRQ_DA8XX_UARTINT0 25 +#define IRQ_DA8XX_KEYMGRINT 26 +#define IRQ_DA8XX_SECINT 26 +#define IRQ_DA8XX_SECKEYERR 26 +#define IRQ_DA8XX_CHIPINT0 28 +#define IRQ_DA8XX_CHIPINT1 29 +#define IRQ_DA8XX_CHIPINT2 30 +#define IRQ_DA8XX_CHIPINT3 31 +#define IRQ_DA8XX_TCERRINT1 32 +#define IRQ_DA8XX_C0_RX_THRESH_PULSE 33 +#define IRQ_DA8XX_C0_RX_PULSE 34 +#define IRQ_DA8XX_C0_TX_PULSE 35 +#define IRQ_DA8XX_C0_MISC_PULSE 36 +#define IRQ_DA8XX_C1_RX_THRESH_PULSE 37 +#define IRQ_DA8XX_C1_RX_PULSE 38 +#define IRQ_DA8XX_C1_TX_PULSE 39 +#define IRQ_DA8XX_C1_MISC_PULSE 40 +#define IRQ_DA8XX_MEMERR 41 +#define IRQ_DA8XX_GPIO0 42 +#define IRQ_DA8XX_GPIO1 43 +#define IRQ_DA8XX_GPIO2 44 +#define IRQ_DA8XX_GPIO3 45 +#define IRQ_DA8XX_GPIO4 46 +#define IRQ_DA8XX_GPIO5 47 +#define IRQ_DA8XX_GPIO6 48 +#define IRQ_DA8XX_GPIO7 49 +#define IRQ_DA8XX_GPIO8 50 +#define IRQ_DA8XX_I2CINT1 51 +#define IRQ_DA8XX_LCDINT 52 +#define IRQ_DA8XX_UARTINT1 53 +#define IRQ_DA8XX_MCASPINT 54 +#define IRQ_DA8XX_ALLINT1 55 +#define IRQ_DA8XX_SPINT1 56 +#define IRQ_DA8XX_UHPI_INT1 57 +#define IRQ_DA8XX_USB_INT 58 +#define IRQ_DA8XX_IRQN 59 +#define IRQ_DA8XX_RWAKEUP 60 +#define IRQ_DA8XX_UARTINT2 61 +#define IRQ_DA8XX_DFTSSINT 62 +#define IRQ_DA8XX_EHRPWM0 63 +#define IRQ_DA8XX_EHRPWM0TZ 64 +#define IRQ_DA8XX_EHRPWM1 65 +#define IRQ_DA8XX_EHRPWM1TZ 66 +#define IRQ_DA8XX_ECAP0 69 +#define IRQ_DA8XX_ECAP1 70 +#define IRQ_DA8XX_ECAP2 71 +#define IRQ_DA8XX_ARMCLKSTOPREQ 90 + +/* DA830 specific interrupts */ +#define IRQ_DA830_MPUERR 27 +#define IRQ_DA830_IOPUERR 27 +#define IRQ_DA830_BOOTCFGERR 27 +#define IRQ_DA830_EHRPWM2 67 +#define IRQ_DA830_EHRPWM2TZ 68 +#define IRQ_DA830_EQEP0 72 +#define IRQ_DA830_EQEP1 73 +#define IRQ_DA830_T12CMPINT0_0 74 +#define IRQ_DA830_T12CMPINT1_0 75 +#define IRQ_DA830_T12CMPINT2_0 76 +#define IRQ_DA830_T12CMPINT3_0 77 +#define IRQ_DA830_T12CMPINT4_0 78 +#define IRQ_DA830_T12CMPINT5_0 79 +#define IRQ_DA830_T12CMPINT6_0 80 +#define IRQ_DA830_T12CMPINT7_0 81 +#define IRQ_DA830_T12CMPINT0_1 82 +#define IRQ_DA830_T12CMPINT1_1 83 +#define IRQ_DA830_T12CMPINT2_1 84 +#define IRQ_DA830_T12CMPINT3_1 85 +#define IRQ_DA830_T12CMPINT4_1 86 +#define IRQ_DA830_T12CMPINT5_1 87 +#define IRQ_DA830_T12CMPINT6_1 88 +#define IRQ_DA830_T12CMPINT7_1 89 + +#define DA830_N_CP_INTC_IRQ 96 + +/* DA850 speicific interrupts */ +#define IRQ_DA850_MPUADDRERR0 27 +#define IRQ_DA850_MPUPROTERR0 27 +#define IRQ_DA850_IOPUADDRERR0 27 +#define IRQ_DA850_IOPUPROTERR0 27 +#define IRQ_DA850_IOPUADDRERR1 27 +#define IRQ_DA850_IOPUPROTERR1 27 +#define IRQ_DA850_IOPUADDRERR2 27 +#define IRQ_DA850_IOPUPROTERR2 27 +#define IRQ_DA850_BOOTCFG_ADDR_ERR 27 +#define IRQ_DA850_BOOTCFG_PROT_ERR 27 +#define IRQ_DA850_MPUADDRERR1 27 +#define IRQ_DA850_MPUPROTERR1 27 +#define IRQ_DA850_IOPUADDRERR3 27 +#define IRQ_DA850_IOPUPROTERR3 27 +#define IRQ_DA850_IOPUADDRERR4 27 +#define IRQ_DA850_IOPUPROTERR4 27 +#define IRQ_DA850_IOPUADDRERR5 27 +#define IRQ_DA850_IOPUPROTERR5 27 +#define IRQ_DA850_MIOPU_BOOTCFG_ERR 27 +#define IRQ_DA850_SATAINT 67 +#define IRQ_DA850_TINT12_2 68 +#define IRQ_DA850_TINT34_2 68 +#define IRQ_DA850_TINTALL_2 68 +#define IRQ_DA850_MMCSDINT0_1 72 +#define IRQ_DA850_MMCSDINT1_1 73 +#define IRQ_DA850_T12CMPINT0_2 74 +#define IRQ_DA850_T12CMPINT1_2 75 +#define IRQ_DA850_T12CMPINT2_2 76 +#define IRQ_DA850_T12CMPINT3_2 77 +#define IRQ_DA850_T12CMPINT4_2 78 +#define IRQ_DA850_T12CMPINT5_2 79 +#define IRQ_DA850_T12CMPINT6_2 80 +#define IRQ_DA850_T12CMPINT7_2 81 +#define IRQ_DA850_T12CMPINT0_3 82 +#define IRQ_DA850_T12CMPINT1_3 83 +#define IRQ_DA850_T12CMPINT2_3 84 +#define IRQ_DA850_T12CMPINT3_3 85 +#define IRQ_DA850_T12CMPINT4_3 86 +#define IRQ_DA850_T12CMPINT5_3 87 +#define IRQ_DA850_T12CMPINT6_3 88 +#define IRQ_DA850_T12CMPINT7_3 89 +#define IRQ_DA850_RPIINT 91 +#define IRQ_DA850_VPIFINT 92 +#define IRQ_DA850_CCINT1 93 +#define IRQ_DA850_CCERRINT1 94 +#define IRQ_DA850_TCERRINT2 95 +#define IRQ_DA850_TINT12_3 96 +#define IRQ_DA850_TINT34_3 96 +#define IRQ_DA850_TINTALL_3 96 +#define IRQ_DA850_MCBSP0RINT 97 +#define IRQ_DA850_MCBSP0XINT 98 +#define IRQ_DA850_MCBSP1RINT 99 +#define IRQ_DA850_MCBSP1XINT 100 + +#define DA850_N_CP_INTC_IRQ 101 + +/* da850 currently has the most gpio pins (144) */ +#define DAVINCI_N_GPIO 144 +/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */ +#define NR_IRQS (DA850_N_CP_INTC_IRQ + DAVINCI_N_GPIO) + +#endif /* __ASM_ARCH_IRQS_H */ diff --git a/kernel/arch/arm/mach-davinci/include/mach/mux.h b/kernel/arch/arm/mach-davinci/include/mach/mux.h new file mode 100644 index 000000000..631655e68 --- /dev/null +++ b/kernel/arch/arm/mach-davinci/include/mach/mux.h @@ -0,0 +1,990 @@ +/* + * Table of the DAVINCI register configurations for the PINMUX combinations + * + * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> + * + * Based on linux/include/asm-arm/arch-omap/mux.h: + * Copyright (C) 2003 - 2005 Nokia Corporation + * + * Written by Tony Lindgren + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Copyright (C) 2008 Texas Instruments. + */ + +#ifndef __INC_MACH_MUX_H +#define __INC_MACH_MUX_H + +struct mux_config { + const char *name; + const char *mux_reg_name; + const unsigned char mux_reg; + const unsigned char mask_offset; + const unsigned char mask; + const unsigned char mode; + bool debug; +}; + +enum davinci_dm644x_index { + /* ATA and HDDIR functions */ + DM644X_HDIREN, + DM644X_ATAEN, + DM644X_ATAEN_DISABLE, + + /* HPI functions */ + DM644X_HPIEN_DISABLE, + + /* AEAW functions */ + DM644X_AEAW, + DM644X_AEAW0, + DM644X_AEAW1, + DM644X_AEAW2, + DM644X_AEAW3, + DM644X_AEAW4, + + /* Memory Stick */ + DM644X_MSTK, + + /* I2C */ + DM644X_I2C, + + /* ASP function */ + DM644X_MCBSP, + + /* UART1 */ + DM644X_UART1, + + /* UART2 */ + DM644X_UART2, + + /* PWM0 */ + DM644X_PWM0, + + /* PWM1 */ + DM644X_PWM1, + + /* PWM2 */ + DM644X_PWM2, + + /* VLYNQ function */ + DM644X_VLYNQEN, + DM644X_VLSCREN, + DM644X_VLYNQWD, + + /* EMAC and MDIO function */ + DM644X_EMACEN, + + /* GPIO3V[0:16] pins */ + DM644X_GPIO3V, + + /* GPIO pins */ + DM644X_GPIO0, + DM644X_GPIO3, + DM644X_GPIO43_44, + DM644X_GPIO46_47, + + /* VPBE */ + DM644X_RGB666, + + /* LCD */ + DM644X_LOEEN, + DM644X_LFLDEN, +}; + +enum davinci_dm646x_index { + /* ATA function */ + DM646X_ATAEN, + + /* AUDIO Clock */ + DM646X_AUDCK1, + DM646X_AUDCK0, + + /* CRGEN Control */ + DM646X_CRGMUX, + + /* VPIF Control */ + DM646X_STSOMUX_DISABLE, + DM646X_STSIMUX_DISABLE, + DM646X_PTSOMUX_DISABLE, + DM646X_PTSIMUX_DISABLE, + + /* TSIF Control */ + DM646X_STSOMUX, + DM646X_STSIMUX, + DM646X_PTSOMUX_PARALLEL, + DM646X_PTSIMUX_PARALLEL, + DM646X_PTSOMUX_SERIAL, + DM646X_PTSIMUX_SERIAL, +}; + +enum davinci_dm355_index { + /* MMC/SD 0 */ + DM355_MMCSD0, + + /* MMC/SD 1 */ + DM355_SD1_CLK, + DM355_SD1_CMD, + DM355_SD1_DATA3, + DM355_SD1_DATA2, + DM355_SD1_DATA1, + DM355_SD1_DATA0, + + /* I2C */ + DM355_I2C_SDA, + DM355_I2C_SCL, + + /* ASP0 function */ + DM355_MCBSP0_BDX, + DM355_MCBSP0_X, + DM355_MCBSP0_BFSX, + DM355_MCBSP0_BDR, + DM355_MCBSP0_R, + DM355_MCBSP0_BFSR, + + /* SPI0 */ + DM355_SPI0_SDI, + DM355_SPI0_SDENA0, + DM355_SPI0_SDENA1, + + /* IRQ muxing */ + DM355_INT_EDMA_CC, + DM355_INT_EDMA_TC0_ERR, + DM355_INT_EDMA_TC1_ERR, + + /* EDMA event muxing */ + DM355_EVT8_ASP1_TX, + DM355_EVT9_ASP1_RX, + DM355_EVT26_MMC0_RX, + + /* Video Out */ + DM355_VOUT_FIELD, + DM355_VOUT_FIELD_G70, + DM355_VOUT_HVSYNC, + DM355_VOUT_COUTL_EN, + DM355_VOUT_COUTH_EN, + + /* Video In Pin Mux */ + DM355_VIN_PCLK, + DM355_VIN_CAM_WEN, + DM355_VIN_CAM_VD, + DM355_VIN_CAM_HD, + DM355_VIN_YIN_EN, + DM355_VIN_CINL_EN, + DM355_VIN_CINH_EN, +}; + +enum davinci_dm365_index { + /* MMC/SD 0 */ + DM365_MMCSD0, + + /* MMC/SD 1 */ + DM365_SD1_CLK, + DM365_SD1_CMD, + DM365_SD1_DATA3, + DM365_SD1_DATA2, + DM365_SD1_DATA1, + DM365_SD1_DATA0, + + /* I2C */ + DM365_I2C_SDA, + DM365_I2C_SCL, + + /* AEMIF */ + DM365_AEMIF_AR_A14, + DM365_AEMIF_AR_BA0, + DM365_AEMIF_A3, + DM365_AEMIF_A7, + DM365_AEMIF_D15_8, + DM365_AEMIF_CE0, + DM365_AEMIF_CE1, + DM365_AEMIF_WE_OE, + + /* ASP0 function */ + DM365_MCBSP0_BDX, + DM365_MCBSP0_X, + DM365_MCBSP0_BFSX, + DM365_MCBSP0_BDR, + DM365_MCBSP0_R, + DM365_MCBSP0_BFSR, + + /* SPI0 */ + DM365_SPI0_SCLK, + DM365_SPI0_SDI, + DM365_SPI0_SDO, + DM365_SPI0_SDENA0, + DM365_SPI0_SDENA1, + + /* UART */ + DM365_UART0_RXD, + DM365_UART0_TXD, + DM365_UART1_RXD, + DM365_UART1_TXD, + DM365_UART1_RTS, + DM365_UART1_CTS, + + /* EMAC */ + DM365_EMAC_TX_EN, + DM365_EMAC_TX_CLK, + DM365_EMAC_COL, + DM365_EMAC_TXD3, + DM365_EMAC_TXD2, + DM365_EMAC_TXD1, + DM365_EMAC_TXD0, + DM365_EMAC_RXD3, + DM365_EMAC_RXD2, + DM365_EMAC_RXD1, + DM365_EMAC_RXD0, + DM365_EMAC_RX_CLK, + DM365_EMAC_RX_DV, + DM365_EMAC_RX_ER, + DM365_EMAC_CRS, + DM365_EMAC_MDIO, + DM365_EMAC_MDCLK, + + /* Key Scan */ + DM365_KEYSCAN, + + /* PWM */ + DM365_PWM0, + DM365_PWM0_G23, + DM365_PWM1, + DM365_PWM1_G25, + DM365_PWM2_G87, + DM365_PWM2_G88, + DM365_PWM2_G89, + DM365_PWM2_G90, + DM365_PWM3_G80, + DM365_PWM3_G81, + DM365_PWM3_G85, + DM365_PWM3_G86, + + /* SPI1 */ + DM365_SPI1_SCLK, + DM365_SPI1_SDO, + DM365_SPI1_SDI, + DM365_SPI1_SDENA0, + DM365_SPI1_SDENA1, + + /* SPI2 */ + DM365_SPI2_SCLK, + DM365_SPI2_SDO, + DM365_SPI2_SDI, + DM365_SPI2_SDENA0, + DM365_SPI2_SDENA1, + + /* SPI3 */ + DM365_SPI3_SCLK, + DM365_SPI3_SDO, + DM365_SPI3_SDI, + DM365_SPI3_SDENA0, + DM365_SPI3_SDENA1, + + /* SPI4 */ + DM365_SPI4_SCLK, + DM365_SPI4_SDO, + DM365_SPI4_SDI, + DM365_SPI4_SDENA0, + DM365_SPI4_SDENA1, + + /* Clock */ + DM365_CLKOUT0, + DM365_CLKOUT1, + DM365_CLKOUT2, + + /* GPIO */ + DM365_GPIO20, + DM365_GPIO30, + DM365_GPIO31, + DM365_GPIO32, + DM365_GPIO33, + DM365_GPIO40, + DM365_GPIO64_57, + + /* Video */ + DM365_VOUT_FIELD, + DM365_VOUT_FIELD_G81, + DM365_VOUT_HVSYNC, + DM365_VOUT_COUTL_EN, + DM365_VOUT_COUTH_EN, + DM365_VIN_CAM_WEN, + DM365_VIN_CAM_VD, + DM365_VIN_CAM_HD, + DM365_VIN_YIN4_7_EN, + DM365_VIN_YIN0_3_EN, + + /* IRQ muxing */ + DM365_INT_EDMA_CC, + DM365_INT_EDMA_TC0_ERR, + DM365_INT_EDMA_TC1_ERR, + DM365_INT_EDMA_TC2_ERR, + DM365_INT_EDMA_TC3_ERR, + DM365_INT_PRTCSS, + DM365_INT_EMAC_RXTHRESH, + DM365_INT_EMAC_RXPULSE, + DM365_INT_EMAC_TXPULSE, + DM365_INT_EMAC_MISCPULSE, + DM365_INT_IMX0_ENABLE, + DM365_INT_IMX0_DISABLE, + DM365_INT_HDVICP_ENABLE, + DM365_INT_HDVICP_DISABLE, + DM365_INT_IMX1_ENABLE, + DM365_INT_IMX1_DISABLE, + DM365_INT_NSF_ENABLE, + DM365_INT_NSF_DISABLE, + + /* EDMA event muxing */ + DM365_EVT2_ASP_TX, + DM365_EVT3_ASP_RX, + DM365_EVT2_VC_TX, + DM365_EVT3_VC_RX, + DM365_EVT26_MMC0_RX, +}; + +enum da830_index { + DA830_GPIO7_14, + DA830_RTCK, + DA830_GPIO7_15, + DA830_EMU_0, + DA830_EMB_SDCKE, + DA830_EMB_CLK_GLUE, + DA830_EMB_CLK, + DA830_NEMB_CS_0, + DA830_NEMB_CAS, + DA830_NEMB_RAS, + DA830_NEMB_WE, + DA830_EMB_BA_1, + DA830_EMB_BA_0, + DA830_EMB_A_0, + DA830_EMB_A_1, + DA830_EMB_A_2, + DA830_EMB_A_3, + DA830_EMB_A_4, + DA830_EMB_A_5, + DA830_GPIO7_0, + DA830_GPIO7_1, + DA830_GPIO7_2, + DA830_GPIO7_3, + DA830_GPIO7_4, + DA830_GPIO7_5, + DA830_GPIO7_6, + DA830_GPIO7_7, + DA830_EMB_A_6, + DA830_EMB_A_7, + DA830_EMB_A_8, + DA830_EMB_A_9, + DA830_EMB_A_10, + DA830_EMB_A_11, + DA830_EMB_A_12, + DA830_EMB_D_31, + DA830_GPIO7_8, + DA830_GPIO7_9, + DA830_GPIO7_10, + DA830_GPIO7_11, + DA830_GPIO7_12, + DA830_GPIO7_13, + DA830_GPIO3_13, + DA830_EMB_D_30, + DA830_EMB_D_29, + DA830_EMB_D_28, + DA830_EMB_D_27, + DA830_EMB_D_26, + DA830_EMB_D_25, + DA830_EMB_D_24, + DA830_EMB_D_23, + DA830_EMB_D_22, + DA830_EMB_D_21, + DA830_EMB_D_20, + DA830_EMB_D_19, + DA830_EMB_D_18, + DA830_EMB_D_17, + DA830_EMB_D_16, + DA830_NEMB_WE_DQM_3, + DA830_NEMB_WE_DQM_2, + DA830_EMB_D_0, + DA830_EMB_D_1, + DA830_EMB_D_2, + DA830_EMB_D_3, + DA830_EMB_D_4, + DA830_EMB_D_5, + DA830_EMB_D_6, + DA830_GPIO6_0, + DA830_GPIO6_1, + DA830_GPIO6_2, + DA830_GPIO6_3, + DA830_GPIO6_4, + DA830_GPIO6_5, + DA830_GPIO6_6, + DA830_EMB_D_7, + DA830_EMB_D_8, + DA830_EMB_D_9, + DA830_EMB_D_10, + DA830_EMB_D_11, + DA830_EMB_D_12, + DA830_EMB_D_13, + DA830_EMB_D_14, + DA830_GPIO6_7, + DA830_GPIO6_8, + DA830_GPIO6_9, + DA830_GPIO6_10, + DA830_GPIO6_11, + DA830_GPIO6_12, + DA830_GPIO6_13, + DA830_GPIO6_14, + DA830_EMB_D_15, + DA830_NEMB_WE_DQM_1, + DA830_NEMB_WE_DQM_0, + DA830_SPI0_SOMI_0, + DA830_SPI0_SIMO_0, + DA830_SPI0_CLK, + DA830_NSPI0_ENA, + DA830_NSPI0_SCS_0, + DA830_EQEP0I, + DA830_EQEP0S, + DA830_EQEP1I, + DA830_NUART0_CTS, + DA830_NUART0_RTS, + DA830_EQEP0A, + DA830_EQEP0B, + DA830_GPIO6_15, + DA830_GPIO5_14, + DA830_GPIO5_15, + DA830_GPIO5_0, + DA830_GPIO5_1, + DA830_GPIO5_2, + DA830_GPIO5_3, + DA830_GPIO5_4, + DA830_SPI1_SOMI_0, + DA830_SPI1_SIMO_0, + DA830_SPI1_CLK, + DA830_UART0_RXD, + DA830_UART0_TXD, + DA830_AXR1_10, + DA830_AXR1_11, + DA830_NSPI1_ENA, + DA830_I2C1_SCL, + DA830_I2C1_SDA, + DA830_EQEP1S, + DA830_I2C0_SDA, + DA830_I2C0_SCL, + DA830_UART2_RXD, + DA830_TM64P0_IN12, + DA830_TM64P0_OUT12, + DA830_GPIO5_5, + DA830_GPIO5_6, + DA830_GPIO5_7, + DA830_GPIO5_8, + DA830_GPIO5_9, + DA830_GPIO5_10, + DA830_GPIO5_11, + DA830_GPIO5_12, + DA830_NSPI1_SCS_0, + DA830_USB0_DRVVBUS, + DA830_AHCLKX0, + DA830_ACLKX0, + DA830_AFSX0, + DA830_AHCLKR0, + DA830_ACLKR0, + DA830_AFSR0, + DA830_UART2_TXD, + DA830_AHCLKX2, + DA830_ECAP0_APWM0, + DA830_RMII_MHZ_50_CLK, + DA830_ECAP1_APWM1, + DA830_USB_REFCLKIN, + DA830_GPIO5_13, + DA830_GPIO4_15, + DA830_GPIO2_11, + DA830_GPIO2_12, + DA830_GPIO2_13, + DA830_GPIO2_14, + DA830_GPIO2_15, + DA830_GPIO3_12, + DA830_AMUTE0, + DA830_AXR0_0, + DA830_AXR0_1, + DA830_AXR0_2, + DA830_AXR0_3, + DA830_AXR0_4, + DA830_AXR0_5, + DA830_AXR0_6, + DA830_RMII_TXD_0, + DA830_RMII_TXD_1, + DA830_RMII_TXEN, + DA830_RMII_CRS_DV, + DA830_RMII_RXD_0, + DA830_RMII_RXD_1, + DA830_RMII_RXER, + DA830_AFSR2, + DA830_ACLKX2, + DA830_AXR2_3, + DA830_AXR2_2, + DA830_AXR2_1, + DA830_AFSX2, + DA830_ACLKR2, + DA830_NRESETOUT, + DA830_GPIO3_0, + DA830_GPIO3_1, + DA830_GPIO3_2, + DA830_GPIO3_3, + DA830_GPIO3_4, + DA830_GPIO3_5, + DA830_GPIO3_6, + DA830_AXR0_7, + DA830_AXR0_8, + DA830_UART1_RXD, + DA830_UART1_TXD, + DA830_AXR0_11, + DA830_AHCLKX1, + DA830_ACLKX1, + DA830_AFSX1, + DA830_MDIO_CLK, + DA830_MDIO_D, + DA830_AXR0_9, + DA830_AXR0_10, + DA830_EPWM0B, + DA830_EPWM0A, + DA830_EPWMSYNCI, + DA830_AXR2_0, + DA830_EPWMSYNC0, + DA830_GPIO3_7, + DA830_GPIO3_8, + DA830_GPIO3_9, + DA830_GPIO3_10, + DA830_GPIO3_11, + DA830_GPIO3_14, + DA830_GPIO3_15, + DA830_GPIO4_10, + DA830_AHCLKR1, + DA830_ACLKR1, + DA830_AFSR1, + DA830_AMUTE1, + DA830_AXR1_0, + DA830_AXR1_1, + DA830_AXR1_2, + DA830_AXR1_3, + DA830_ECAP2_APWM2, + DA830_EHRPWMGLUETZ, + DA830_EQEP1A, + DA830_GPIO4_11, + DA830_GPIO4_12, + DA830_GPIO4_13, + DA830_GPIO4_14, + DA830_GPIO4_0, + DA830_GPIO4_1, + DA830_GPIO4_2, + DA830_GPIO4_3, + DA830_AXR1_4, + DA830_AXR1_5, + DA830_AXR1_6, + DA830_AXR1_7, + DA830_AXR1_8, + DA830_AXR1_9, + DA830_EMA_D_0, + DA830_EMA_D_1, + DA830_EQEP1B, + DA830_EPWM2B, + DA830_EPWM2A, + DA830_EPWM1B, + DA830_EPWM1A, + DA830_MMCSD_DAT_0, + DA830_MMCSD_DAT_1, + DA830_UHPI_HD_0, + DA830_UHPI_HD_1, + DA830_GPIO4_4, + DA830_GPIO4_5, + DA830_GPIO4_6, + DA830_GPIO4_7, + DA830_GPIO4_8, + DA830_GPIO4_9, + DA830_GPIO0_0, + DA830_GPIO0_1, + DA830_EMA_D_2, + DA830_EMA_D_3, + DA830_EMA_D_4, + DA830_EMA_D_5, + DA830_EMA_D_6, + DA830_EMA_D_7, + DA830_EMA_D_8, + DA830_EMA_D_9, + DA830_MMCSD_DAT_2, + DA830_MMCSD_DAT_3, + DA830_MMCSD_DAT_4, + DA830_MMCSD_DAT_5, + DA830_MMCSD_DAT_6, + DA830_MMCSD_DAT_7, + DA830_UHPI_HD_8, + DA830_UHPI_HD_9, + DA830_UHPI_HD_2, + DA830_UHPI_HD_3, + DA830_UHPI_HD_4, + DA830_UHPI_HD_5, + DA830_UHPI_HD_6, + DA830_UHPI_HD_7, + DA830_LCD_D_8, + DA830_LCD_D_9, + DA830_GPIO0_2, + DA830_GPIO0_3, + DA830_GPIO0_4, + DA830_GPIO0_5, + DA830_GPIO0_6, + DA830_GPIO0_7, + DA830_GPIO0_8, + DA830_GPIO0_9, + DA830_EMA_D_10, + DA830_EMA_D_11, + DA830_EMA_D_12, + DA830_EMA_D_13, + DA830_EMA_D_14, + DA830_EMA_D_15, + DA830_EMA_A_0, + DA830_EMA_A_1, + DA830_UHPI_HD_10, + DA830_UHPI_HD_11, + DA830_UHPI_HD_12, + DA830_UHPI_HD_13, + DA830_UHPI_HD_14, + DA830_UHPI_HD_15, + DA830_LCD_D_7, + DA830_MMCSD_CLK, + DA830_LCD_D_10, + DA830_LCD_D_11, + DA830_LCD_D_12, + DA830_LCD_D_13, + DA830_LCD_D_14, + DA830_LCD_D_15, + DA830_UHPI_HCNTL0, + DA830_GPIO0_10, + DA830_GPIO0_11, + DA830_GPIO0_12, + DA830_GPIO0_13, + DA830_GPIO0_14, + DA830_GPIO0_15, + DA830_GPIO1_0, + DA830_GPIO1_1, + DA830_EMA_A_2, + DA830_EMA_A_3, + DA830_EMA_A_4, + DA830_EMA_A_5, + DA830_EMA_A_6, + DA830_EMA_A_7, + DA830_EMA_A_8, + DA830_EMA_A_9, + DA830_MMCSD_CMD, + DA830_LCD_D_6, + DA830_LCD_D_3, + DA830_LCD_D_2, + DA830_LCD_D_1, + DA830_LCD_D_0, + DA830_LCD_PCLK, + DA830_LCD_HSYNC, + DA830_UHPI_HCNTL1, + DA830_GPIO1_2, + DA830_GPIO1_3, + DA830_GPIO1_4, + DA830_GPIO1_5, + DA830_GPIO1_6, + DA830_GPIO1_7, + DA830_GPIO1_8, + DA830_GPIO1_9, + DA830_EMA_A_10, + DA830_EMA_A_11, + DA830_EMA_A_12, + DA830_EMA_BA_1, + DA830_EMA_BA_0, + DA830_EMA_CLK, + DA830_EMA_SDCKE, + DA830_NEMA_CAS, + DA830_LCD_VSYNC, + DA830_NLCD_AC_ENB_CS, + DA830_LCD_MCLK, + DA830_LCD_D_5, + DA830_LCD_D_4, + DA830_OBSCLK, + DA830_NEMA_CS_4, + DA830_UHPI_HHWIL, + DA830_AHCLKR2, + DA830_GPIO1_10, + DA830_GPIO1_11, + DA830_GPIO1_12, + DA830_GPIO1_13, + DA830_GPIO1_14, + DA830_GPIO1_15, + DA830_GPIO2_0, + DA830_GPIO2_1, + DA830_NEMA_RAS, + DA830_NEMA_WE, + DA830_NEMA_CS_0, + DA830_NEMA_CS_2, + DA830_NEMA_CS_3, + DA830_NEMA_OE, + DA830_NEMA_WE_DQM_1, + DA830_NEMA_WE_DQM_0, + DA830_NEMA_CS_5, + DA830_UHPI_HRNW, + DA830_NUHPI_HAS, + DA830_NUHPI_HCS, + DA830_NUHPI_HDS1, + DA830_NUHPI_HDS2, + DA830_NUHPI_HINT, + DA830_AXR0_12, + DA830_AMUTE2, + DA830_AXR0_13, + DA830_AXR0_14, + DA830_AXR0_15, + DA830_GPIO2_2, + DA830_GPIO2_3, + DA830_GPIO2_4, + DA830_GPIO2_5, + DA830_GPIO2_6, + DA830_GPIO2_7, + DA830_GPIO2_8, + DA830_GPIO2_9, + DA830_EMA_WAIT_0, + DA830_NUHPI_HRDY, + DA830_GPIO2_10, +}; + +enum davinci_da850_index { + /* UART0 function */ + DA850_NUART0_CTS, + DA850_NUART0_RTS, + DA850_UART0_RXD, + DA850_UART0_TXD, + + /* UART1 function */ + DA850_NUART1_CTS, + DA850_NUART1_RTS, + DA850_UART1_RXD, + DA850_UART1_TXD, + + /* UART2 function */ + DA850_NUART2_CTS, + DA850_NUART2_RTS, + DA850_UART2_RXD, + DA850_UART2_TXD, + + /* I2C1 function */ + DA850_I2C1_SCL, + DA850_I2C1_SDA, + + /* I2C0 function */ + DA850_I2C0_SDA, + DA850_I2C0_SCL, + + /* EMAC function */ + DA850_MII_TXEN, + DA850_MII_TXCLK, + DA850_MII_COL, + DA850_MII_TXD_3, + DA850_MII_TXD_2, + DA850_MII_TXD_1, + DA850_MII_TXD_0, + DA850_MII_RXER, + DA850_MII_CRS, + DA850_MII_RXCLK, + DA850_MII_RXDV, + DA850_MII_RXD_3, + DA850_MII_RXD_2, + DA850_MII_RXD_1, + DA850_MII_RXD_0, + DA850_MDIO_CLK, + DA850_MDIO_D, + DA850_RMII_TXD_0, + DA850_RMII_TXD_1, + DA850_RMII_TXEN, + DA850_RMII_CRS_DV, + DA850_RMII_RXD_0, + DA850_RMII_RXD_1, + DA850_RMII_RXER, + DA850_RMII_MHZ_50_CLK, + + /* McASP function */ + DA850_ACLKR, + DA850_ACLKX, + DA850_AFSR, + DA850_AFSX, + DA850_AHCLKR, + DA850_AHCLKX, + DA850_AMUTE, + DA850_AXR_15, + DA850_AXR_14, + DA850_AXR_13, + DA850_AXR_12, + DA850_AXR_11, + DA850_AXR_10, + DA850_AXR_9, + DA850_AXR_8, + DA850_AXR_7, + DA850_AXR_6, + DA850_AXR_5, + DA850_AXR_4, + DA850_AXR_3, + DA850_AXR_2, + DA850_AXR_1, + DA850_AXR_0, + + /* LCD function */ + DA850_LCD_D_7, + DA850_LCD_D_6, + DA850_LCD_D_5, + DA850_LCD_D_4, + DA850_LCD_D_3, + DA850_LCD_D_2, + DA850_LCD_D_1, + DA850_LCD_D_0, + DA850_LCD_D_15, + DA850_LCD_D_14, + DA850_LCD_D_13, + DA850_LCD_D_12, + DA850_LCD_D_11, + DA850_LCD_D_10, + DA850_LCD_D_9, + DA850_LCD_D_8, + DA850_LCD_PCLK, + DA850_LCD_HSYNC, + DA850_LCD_VSYNC, + DA850_NLCD_AC_ENB_CS, + + /* MMC/SD0 function */ + DA850_MMCSD0_DAT_0, + DA850_MMCSD0_DAT_1, + DA850_MMCSD0_DAT_2, + DA850_MMCSD0_DAT_3, + DA850_MMCSD0_CLK, + DA850_MMCSD0_CMD, + + /* MMC/SD1 function */ + DA850_MMCSD1_DAT_0, + DA850_MMCSD1_DAT_1, + DA850_MMCSD1_DAT_2, + DA850_MMCSD1_DAT_3, + DA850_MMCSD1_CLK, + DA850_MMCSD1_CMD, + + /* EMIF2.5/EMIFA function */ + DA850_EMA_D_7, + DA850_EMA_D_6, + DA850_EMA_D_5, + DA850_EMA_D_4, + DA850_EMA_D_3, + DA850_EMA_D_2, + DA850_EMA_D_1, + DA850_EMA_D_0, + DA850_EMA_A_1, + DA850_EMA_A_2, + DA850_NEMA_CS_3, + DA850_NEMA_CS_4, + DA850_NEMA_WE, + DA850_NEMA_OE, + DA850_EMA_D_15, + DA850_EMA_D_14, + DA850_EMA_D_13, + DA850_EMA_D_12, + DA850_EMA_D_11, + DA850_EMA_D_10, + DA850_EMA_D_9, + DA850_EMA_D_8, + DA850_EMA_A_0, + DA850_EMA_A_3, + DA850_EMA_A_4, + DA850_EMA_A_5, + DA850_EMA_A_6, + DA850_EMA_A_7, + DA850_EMA_A_8, + DA850_EMA_A_9, + DA850_EMA_A_10, + DA850_EMA_A_11, + DA850_EMA_A_12, + DA850_EMA_A_13, + DA850_EMA_A_14, + DA850_EMA_A_15, + DA850_EMA_A_16, + DA850_EMA_A_17, + DA850_EMA_A_18, + DA850_EMA_A_19, + DA850_EMA_A_20, + DA850_EMA_A_21, + DA850_EMA_A_22, + DA850_EMA_A_23, + DA850_EMA_BA_1, + DA850_EMA_CLK, + DA850_EMA_WAIT_1, + DA850_NEMA_CS_2, + + /* GPIO function */ + DA850_GPIO2_4, + DA850_GPIO2_6, + DA850_GPIO2_8, + DA850_GPIO2_15, + DA850_GPIO3_12, + DA850_GPIO3_13, + DA850_GPIO4_0, + DA850_GPIO4_1, + DA850_GPIO6_9, + DA850_GPIO6_10, + DA850_GPIO6_13, + DA850_RTC_ALARM, + + /* VPIF Capture */ + DA850_VPIF_DIN0, + DA850_VPIF_DIN1, + DA850_VPIF_DIN2, + DA850_VPIF_DIN3, + DA850_VPIF_DIN4, + DA850_VPIF_DIN5, + DA850_VPIF_DIN6, + DA850_VPIF_DIN7, + DA850_VPIF_DIN8, + DA850_VPIF_DIN9, + DA850_VPIF_DIN10, + DA850_VPIF_DIN11, + DA850_VPIF_DIN12, + DA850_VPIF_DIN13, + DA850_VPIF_DIN14, + DA850_VPIF_DIN15, + DA850_VPIF_CLKIN0, + DA850_VPIF_CLKIN1, + DA850_VPIF_CLKIN2, + DA850_VPIF_CLKIN3, + + /* VPIF Display */ + DA850_VPIF_DOUT0, + DA850_VPIF_DOUT1, + DA850_VPIF_DOUT2, + DA850_VPIF_DOUT3, + DA850_VPIF_DOUT4, + DA850_VPIF_DOUT5, + DA850_VPIF_DOUT6, + DA850_VPIF_DOUT7, + DA850_VPIF_DOUT8, + DA850_VPIF_DOUT9, + DA850_VPIF_DOUT10, + DA850_VPIF_DOUT11, + DA850_VPIF_DOUT12, + DA850_VPIF_DOUT13, + DA850_VPIF_DOUT14, + DA850_VPIF_DOUT15, + DA850_VPIF_CLKO2, + DA850_VPIF_CLKO3, +}; + +#define PINMUX(x) (4 * (x)) + +#ifdef CONFIG_DAVINCI_MUX +/* setup pin muxing */ +extern int davinci_cfg_reg(unsigned long reg_cfg); +extern int davinci_cfg_reg_list(const short pins[]); +#else +/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */ +static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; } +static inline int davinci_cfg_reg_list(const short pins[]) +{ + return 0; +} +#endif + +#endif /* __INC_MACH_MUX_H */ diff --git a/kernel/arch/arm/mach-davinci/include/mach/pm.h b/kernel/arch/arm/mach-davinci/include/mach/pm.h new file mode 100644 index 000000000..37b19bf35 --- /dev/null +++ b/kernel/arch/arm/mach-davinci/include/mach/pm.h @@ -0,0 +1,54 @@ +/* + * TI DaVinci platform support for power management. + * + * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef _MACH_DAVINCI_PM_H +#define _MACH_DAVINCI_PM_H + +/* + * Caution: Assembly code in sleep.S makes assumtion on the order + * of the members of this structure. + */ +struct davinci_pm_config { + void __iomem *ddr2_ctlr_base; + void __iomem *ddrpsc_reg_base; + int ddrpsc_num; + void __iomem *ddrpll_reg_base; + void __iomem *deepsleep_reg; + void __iomem *cpupll_reg_base; + /* + * Note on SLEEPCOUNT: + * The SLEEPCOUNT feature is mainly intended for cases in which + * the internal oscillator is used. The internal oscillator is + * fully disabled in deep sleep mode. When you exist deep sleep + * mode, the oscillator will be turned on and will generate very + * small oscillations which will not be detected by the deep sleep + * counter. Eventually those oscillations will grow to an amplitude + * large enough to start incrementing the deep sleep counter. + * In this case recommendation from hardware engineers is that the + * SLEEPCOUNT be set to 4096. This means that 4096 valid clock cycles + * must be detected before the clock is passed to the rest of the + * system. + * In the case that the internal oscillator is not used and the + * clock is generated externally, the SLEEPCOUNT value can be very + * small since the clock input is assumed to be stable before SoC + * is taken out of deepsleep mode. A value of 128 would be more than + * adequate. + */ + int sleepcount; +}; + +extern unsigned int davinci_cpu_suspend_sz; +extern void davinci_cpu_suspend(struct davinci_pm_config *); + +#endif diff --git a/kernel/arch/arm/mach-davinci/include/mach/psc.h b/kernel/arch/arm/mach-davinci/include/mach/psc.h new file mode 100644 index 000000000..99d47cfa3 --- /dev/null +++ b/kernel/arch/arm/mach-davinci/include/mach/psc.h @@ -0,0 +1,217 @@ +/* + * DaVinci Power & Sleep Controller (PSC) defines + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#ifndef __ASM_ARCH_PSC_H +#define __ASM_ARCH_PSC_H + +#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000 + +/* Power and Sleep Controller (PSC) Domains */ +#define DAVINCI_GPSC_ARMDOMAIN 0 +#define DAVINCI_GPSC_DSPDOMAIN 1 + +#define DAVINCI_LPSC_VPSSMSTR 0 +#define DAVINCI_LPSC_VPSSSLV 1 +#define DAVINCI_LPSC_TPCC 2 +#define DAVINCI_LPSC_TPTC0 3 +#define DAVINCI_LPSC_TPTC1 4 +#define DAVINCI_LPSC_EMAC 5 +#define DAVINCI_LPSC_EMAC_WRAPPER 6 +#define DAVINCI_LPSC_USB 9 +#define DAVINCI_LPSC_ATA 10 +#define DAVINCI_LPSC_VLYNQ 11 +#define DAVINCI_LPSC_UHPI 12 +#define DAVINCI_LPSC_DDR_EMIF 13 +#define DAVINCI_LPSC_AEMIF 14 +#define DAVINCI_LPSC_MMC_SD 15 +#define DAVINCI_LPSC_McBSP 17 +#define DAVINCI_LPSC_I2C 18 +#define DAVINCI_LPSC_UART0 19 +#define DAVINCI_LPSC_UART1 20 +#define DAVINCI_LPSC_UART2 21 +#define DAVINCI_LPSC_SPI 22 +#define DAVINCI_LPSC_PWM0 23 +#define DAVINCI_LPSC_PWM1 24 +#define DAVINCI_LPSC_PWM2 25 +#define DAVINCI_LPSC_GPIO 26 +#define DAVINCI_LPSC_TIMER0 27 +#define DAVINCI_LPSC_TIMER1 28 +#define DAVINCI_LPSC_TIMER2 29 +#define DAVINCI_LPSC_SYSTEM_SUBSYS 30 +#define DAVINCI_LPSC_ARM 31 +#define DAVINCI_LPSC_SCR2 32 +#define DAVINCI_LPSC_SCR3 33 +#define DAVINCI_LPSC_SCR4 34 +#define DAVINCI_LPSC_CROSSBAR 35 +#define DAVINCI_LPSC_CFG27 36 +#define DAVINCI_LPSC_CFG3 37 +#define DAVINCI_LPSC_CFG5 38 +#define DAVINCI_LPSC_GEM 39 +#define DAVINCI_LPSC_IMCOP 40 + +#define DM355_LPSC_TIMER3 5 +#define DM355_LPSC_SPI1 6 +#define DM355_LPSC_MMC_SD1 7 +#define DM355_LPSC_McBSP1 8 +#define DM355_LPSC_PWM3 10 +#define DM355_LPSC_SPI2 11 +#define DM355_LPSC_RTO 12 +#define DM355_LPSC_VPSS_DAC 41 + +/* DM365 */ +#define DM365_LPSC_TIMER3 5 +#define DM365_LPSC_SPI1 6 +#define DM365_LPSC_MMC_SD1 7 +#define DM365_LPSC_McBSP1 8 +#define DM365_LPSC_PWM3 10 +#define DM365_LPSC_SPI2 11 +#define DM365_LPSC_RTO 12 +#define DM365_LPSC_TIMER4 17 +#define DM365_LPSC_SPI0 22 +#define DM365_LPSC_SPI3 38 +#define DM365_LPSC_SPI4 39 +#define DM365_LPSC_EMAC 40 +#define DM365_LPSC_VOICE_CODEC 44 +#define DM365_LPSC_DAC_CLK 46 +#define DM365_LPSC_VPSSMSTR 47 +#define DM365_LPSC_MJCP 50 + +/* + * LPSC Assignments + */ +#define DM646X_LPSC_ARM 0 +#define DM646X_LPSC_C64X_CPU 1 +#define DM646X_LPSC_HDVICP0 2 +#define DM646X_LPSC_HDVICP1 3 +#define DM646X_LPSC_TPCC 4 +#define DM646X_LPSC_TPTC0 5 +#define DM646X_LPSC_TPTC1 6 +#define DM646X_LPSC_TPTC2 7 +#define DM646X_LPSC_TPTC3 8 +#define DM646X_LPSC_PCI 13 +#define DM646X_LPSC_EMAC 14 +#define DM646X_LPSC_VDCE 15 +#define DM646X_LPSC_VPSSMSTR 16 +#define DM646X_LPSC_VPSSSLV 17 +#define DM646X_LPSC_TSIF0 18 +#define DM646X_LPSC_TSIF1 19 +#define DM646X_LPSC_DDR_EMIF 20 +#define DM646X_LPSC_AEMIF 21 +#define DM646X_LPSC_McASP0 22 +#define DM646X_LPSC_McASP1 23 +#define DM646X_LPSC_CRGEN0 24 +#define DM646X_LPSC_CRGEN1 25 +#define DM646X_LPSC_UART0 26 +#define DM646X_LPSC_UART1 27 +#define DM646X_LPSC_UART2 28 +#define DM646X_LPSC_PWM0 29 +#define DM646X_LPSC_PWM1 30 +#define DM646X_LPSC_I2C 31 +#define DM646X_LPSC_SPI 32 +#define DM646X_LPSC_GPIO 33 +#define DM646X_LPSC_TIMER0 34 +#define DM646X_LPSC_TIMER1 35 +#define DM646X_LPSC_ARM_INTC 45 + +/* PSC0 defines */ +#define DA8XX_LPSC0_TPCC 0 +#define DA8XX_LPSC0_TPTC0 1 +#define DA8XX_LPSC0_TPTC1 2 +#define DA8XX_LPSC0_EMIF25 3 +#define DA8XX_LPSC0_SPI0 4 +#define DA8XX_LPSC0_MMC_SD 5 +#define DA8XX_LPSC0_AINTC 6 +#define DA8XX_LPSC0_ARM_RAM_ROM 7 +#define DA8XX_LPSC0_SECU_MGR 8 +#define DA8XX_LPSC0_UART0 9 +#define DA8XX_LPSC0_SCR0_SS 10 +#define DA8XX_LPSC0_SCR1_SS 11 +#define DA8XX_LPSC0_SCR2_SS 12 +#define DA8XX_LPSC0_PRUSS 13 +#define DA8XX_LPSC0_ARM 14 +#define DA8XX_LPSC0_GEM 15 + +/* PSC1 defines */ +#define DA850_LPSC1_TPCC1 0 +#define DA8XX_LPSC1_USB20 1 +#define DA8XX_LPSC1_USB11 2 +#define DA8XX_LPSC1_GPIO 3 +#define DA8XX_LPSC1_UHPI 4 +#define DA8XX_LPSC1_CPGMAC 5 +#define DA8XX_LPSC1_EMIF3C 6 +#define DA8XX_LPSC1_McASP0 7 +#define DA830_LPSC1_McASP1 8 +#define DA850_LPSC1_SATA 8 +#define DA830_LPSC1_McASP2 9 +#define DA850_LPSC1_VPIF 9 +#define DA8XX_LPSC1_SPI1 10 +#define DA8XX_LPSC1_I2C 11 +#define DA8XX_LPSC1_UART1 12 +#define DA8XX_LPSC1_UART2 13 +#define DA8XX_LPSC1_LCDC 16 +#define DA8XX_LPSC1_PWM 17 +#define DA850_LPSC1_MMC_SD1 18 +#define DA8XX_LPSC1_ECAP 20 +#define DA830_LPSC1_EQEP 21 +#define DA850_LPSC1_TPTC2 21 +#define DA8XX_LPSC1_SCR_P0_SS 24 +#define DA8XX_LPSC1_SCR_P1_SS 25 +#define DA8XX_LPSC1_CR_P3_SS 26 +#define DA8XX_LPSC1_L3_CBA_RAM 31 + +/* PSC register offsets */ +#define EPCPR 0x070 +#define PTCMD 0x120 +#define PTSTAT 0x128 +#define PDSTAT 0x200 +#define PDCTL 0x300 +#define MDSTAT 0x800 +#define MDCTL 0xA00 + +/* PSC module states */ +#define PSC_STATE_SWRSTDISABLE 0 +#define PSC_STATE_SYNCRST 1 +#define PSC_STATE_DISABLE 2 +#define PSC_STATE_ENABLE 3 + +#define MDSTAT_STATE_MASK 0x3f +#define PDSTAT_STATE_MASK 0x1f +#define MDCTL_LRST BIT(8) +#define MDCTL_FORCE BIT(31) +#define PDCTL_NEXT BIT(0) +#define PDCTL_EPCGOOD BIT(8) + +#ifndef __ASSEMBLER__ + +extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); +extern void davinci_psc_reset(unsigned int ctlr, unsigned int id, + bool reset); +extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, + unsigned int id, bool enable, u32 flags); + +#endif + +#endif /* __ASM_ARCH_PSC_H */ diff --git a/kernel/arch/arm/mach-davinci/include/mach/serial.h b/kernel/arch/arm/mach-davinci/include/mach/serial.h new file mode 100644 index 000000000..d4b4aa879 --- /dev/null +++ b/kernel/arch/arm/mach-davinci/include/mach/serial.h @@ -0,0 +1,37 @@ +/* + * DaVinci serial device definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_SERIAL_H +#define __ASM_ARCH_SERIAL_H + +#include <asm/memory.h> + +#include <mach/hardware.h> + +#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) +#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) +#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) + +#define DA8XX_UART0_BASE (IO_PHYS + 0x042000) +#define DA8XX_UART1_BASE (IO_PHYS + 0x10c000) +#define DA8XX_UART2_BASE (IO_PHYS + 0x10d000) + +/* DaVinci UART register offsets */ +#define UART_DAVINCI_PWREMU 0x0c +#define UART_DM646X_SCR 0x10 +#define UART_DM646X_SCR_TX_WATERMARK 0x08 + +#ifndef __ASSEMBLY__ +#include <linux/platform_device.h> + +extern int davinci_serial_init(struct platform_device *); +#endif + +#endif /* __ASM_ARCH_SERIAL_H */ diff --git a/kernel/arch/arm/mach-davinci/include/mach/sram.h b/kernel/arch/arm/mach-davinci/include/mach/sram.h new file mode 100644 index 000000000..4e5db5621 --- /dev/null +++ b/kernel/arch/arm/mach-davinci/include/mach/sram.h @@ -0,0 +1,30 @@ +/* + * mach/sram.h - DaVinci simple SRAM allocator + * + * Copyright (C) 2009 David Brownell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __MACH_SRAM_H +#define __MACH_SRAM_H + +/* ARBITRARY: SRAM allocations are multiples of this 2^N size */ +#define SRAM_GRANULARITY 512 + +/* + * SRAM allocations return a CPU virtual address, or NULL on error. + * If a DMA address is requested and the SRAM supports DMA, its + * mapped address is also returned. + * + * Errors include SRAM memory not being available, and requesting + * DMA mapped SRAM on systems which don't allow that. + */ +extern void *sram_alloc(size_t len, dma_addr_t *dma); +extern void sram_free(void *addr, size_t len); + +/* Get the struct gen_pool * for use in platform data */ +extern struct gen_pool *sram_get_gen_pool(void); + +#endif /* __MACH_SRAM_H */ diff --git a/kernel/arch/arm/mach-davinci/include/mach/time.h b/kernel/arch/arm/mach-davinci/include/mach/time.h new file mode 100644 index 000000000..1c971d8d8 --- /dev/null +++ b/kernel/arch/arm/mach-davinci/include/mach/time.h @@ -0,0 +1,35 @@ +/* + * Local header file for DaVinci time code. + * + * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ARCH_ARM_MACH_DAVINCI_TIME_H +#define __ARCH_ARM_MACH_DAVINCI_TIME_H + +#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400) +#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800) +#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00) + +enum { + T0_BOT, + T0_TOP, + T1_BOT, + T1_TOP, + NUM_TIMERS +}; + +#define IS_TIMER1(id) (id & 0x2) +#define IS_TIMER0(id) (!IS_TIMER1(id)) +#define IS_TIMER_TOP(id) ((id & 0x1)) +#define IS_TIMER_BOT(id) (!IS_TIMER_TOP(id)) + +#define ID_TO_TIMER(id) (IS_TIMER1(id) != 0) + +extern struct davinci_timer_instance davinci_timer_instance[]; + +#endif /* __ARCH_ARM_MACH_DAVINCI_TIME_H */ diff --git a/kernel/arch/arm/mach-davinci/include/mach/uncompress.h b/kernel/arch/arm/mach-davinci/include/mach/uncompress.h new file mode 100644 index 000000000..8fb97b93b --- /dev/null +++ b/kernel/arch/arm/mach-davinci/include/mach/uncompress.h @@ -0,0 +1,97 @@ +/* + * Serial port stubs for kernel decompress status messages + * + * Initially based on: + * arch/arm/plat-omap/include/mach/uncompress.h + * + * Original copyrights follow. + * + * Copyright (C) 2000 RidgeRun, Inc. + * Author: Greg Lonnon <glonnon@ridgerun.com> + * + * Rewritten by: + * Author: <source@mvista.com> + * 2004 (c) MontaVista Software, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <linux/types.h> +#include <linux/serial_reg.h> + +#include <asm/mach-types.h> + +#include <mach/serial.h> + +#define IOMEM(x) ((void __force __iomem *)(x)) + +u32 *uart; + +/* PORT_16C550A, in polled non-fifo mode */ +static void putc(char c) +{ + if (!uart) + return; + + while (!(uart[UART_LSR] & UART_LSR_THRE)) + barrier(); + uart[UART_TX] = c; +} + +static inline void flush(void) +{ + if (!uart) + return; + + while (!(uart[UART_LSR] & UART_LSR_THRE)) + barrier(); +} + +static inline void set_uart_info(u32 phys) +{ + uart = (u32 *)phys; +} + +#define _DEBUG_LL_ENTRY(machine, phys) \ + { \ + if (machine_is_##machine()) { \ + set_uart_info(phys); \ + break; \ + } \ + } + +#define DEBUG_LL_DAVINCI(machine, port) \ + _DEBUG_LL_ENTRY(machine, DAVINCI_UART##port##_BASE) + +#define DEBUG_LL_DA8XX(machine, port) \ + _DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE) + +static inline void __arch_decomp_setup(unsigned long arch_id) +{ + /* + * Initialize the port based on the machine ID from the bootloader. + * Note that we're using macros here instead of switch statement + * as machine_is functions are optimized out for the boards that + * are not selected. + */ + do { + /* Davinci boards */ + DEBUG_LL_DAVINCI(davinci_evm, 0); + DEBUG_LL_DAVINCI(sffsdr, 0); + DEBUG_LL_DAVINCI(neuros_osd2, 0); + DEBUG_LL_DAVINCI(davinci_dm355_evm, 0); + DEBUG_LL_DAVINCI(dm355_leopard, 0); + DEBUG_LL_DAVINCI(davinci_dm6467_evm, 0); + DEBUG_LL_DAVINCI(davinci_dm365_evm, 0); + + /* DA8xx boards */ + DEBUG_LL_DA8XX(davinci_da830_evm, 2); + DEBUG_LL_DA8XX(davinci_da850_evm, 2); + DEBUG_LL_DA8XX(mityomapl138, 1); + DEBUG_LL_DA8XX(omapl138_hawkboard, 2); + } while (0); +} + +#define arch_decomp_setup() __arch_decomp_setup(arch_id) |