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-rw-r--r--kernel/Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt10
-rw-r--r--kernel/Documentation/devicetree/bindings/serial/atmel-usart.txt3
-rw-r--r--kernel/Documentation/devicetree/bindings/serial/axis,etraxfs-uart.txt6
-rw-r--r--kernel/Documentation/devicetree/bindings/serial/ingenic,uart.txt23
-rw-r--r--kernel/Documentation/devicetree/bindings/serial/mrvl,pxa-ssp.txt1
-rw-r--r--kernel/Documentation/devicetree/bindings/serial/mtk-uart.txt18
-rw-r--r--kernel/Documentation/devicetree/bindings/serial/nxp,lpc1850-uart.txt28
-rw-r--r--kernel/Documentation/devicetree/bindings/serial/nxp,sc16is7xx.txt37
-rw-r--r--kernel/Documentation/devicetree/bindings/serial/omap_serial.txt3
-rw-r--r--kernel/Documentation/devicetree/bindings/serial/pl011.txt4
-rw-r--r--kernel/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt6
-rw-r--r--kernel/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt10
-rw-r--r--kernel/Documentation/devicetree/bindings/serial/sirf-uart.txt15
-rw-r--r--kernel/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt3
-rw-r--r--kernel/Documentation/devicetree/bindings/serial/uniphier-uart.txt23
15 files changed, 168 insertions, 22 deletions
diff --git a/kernel/Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt b/kernel/Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt
new file mode 100644
index 000000000..4163e7eb7
--- /dev/null
+++ b/kernel/Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt
@@ -0,0 +1,10 @@
+* ARM SBSA defined generic UART
+This UART uses a subset of the PL011 registers and consequently lives
+in the PL011 driver. It's baudrate and other communication parameters
+cannot be adjusted at runtime, so it lacks a clock specifier here.
+
+Required properties:
+- compatible: must be "arm,sbsa-uart"
+- reg: exactly one register range
+- interrupts: exactly one interrupt specifier
+- current-speed: the (fixed) baud rate set by the firmware
diff --git a/kernel/Documentation/devicetree/bindings/serial/atmel-usart.txt b/kernel/Documentation/devicetree/bindings/serial/atmel-usart.txt
index 90787aa2e..e6e6142e3 100644
--- a/kernel/Documentation/devicetree/bindings/serial/atmel-usart.txt
+++ b/kernel/Documentation/devicetree/bindings/serial/atmel-usart.txt
@@ -22,6 +22,8 @@ Optional properties:
memory peripheral interface and USART DMA channel ID, FIFO configuration.
Refer to dma.txt and atmel-dma.txt for details.
- dma-names: "rx" for RX channel, "tx" for TX channel.
+- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
+ capable USARTs.
<chip> compatible description:
- at91rm9200: legacy USART support
@@ -57,4 +59,5 @@ Example:
dmas = <&dma0 2 0x3>,
<&dma0 2 0x204>;
dma-names = "tx", "rx";
+ atmel,fifo-size = <32>;
};
diff --git a/kernel/Documentation/devicetree/bindings/serial/axis,etraxfs-uart.txt b/kernel/Documentation/devicetree/bindings/serial/axis,etraxfs-uart.txt
index ebcbb62c0..51b3c9e80 100644
--- a/kernel/Documentation/devicetree/bindings/serial/axis,etraxfs-uart.txt
+++ b/kernel/Documentation/devicetree/bindings/serial/axis,etraxfs-uart.txt
@@ -6,7 +6,7 @@ Required properties:
- interrupts: device interrupt
Optional properties:
-- {dtr,dsr,ri,cd}-gpios: specify a GPIO for DTR/DSR/RI/CD
+- {dtr,dsr,rng,dcd}-gpios: specify a GPIO for DTR/DSR/RI/DCD
line respectively.
Example:
@@ -16,4 +16,8 @@ serial@b00260000 {
reg = <0xb0026000 0x1000>;
interrupts = <68>;
status = "disabled";
+ dtr-gpios = <&sysgpio 0 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&sysgpio 1 GPIO_ACTIVE_LOW>;
+ rng-gpios = <&sysgpio 2 GPIO_ACTIVE_LOW>;
+ dcd-gpios = <&sysgpio 3 GPIO_ACTIVE_LOW>;
};
diff --git a/kernel/Documentation/devicetree/bindings/serial/ingenic,uart.txt b/kernel/Documentation/devicetree/bindings/serial/ingenic,uart.txt
new file mode 100644
index 000000000..02cb7fe59
--- /dev/null
+++ b/kernel/Documentation/devicetree/bindings/serial/ingenic,uart.txt
@@ -0,0 +1,23 @@
+* Ingenic SoC UART
+
+Required properties:
+- compatible : "ingenic,jz4740-uart", "ingenic,jz4760-uart",
+ "ingenic,jz4775-uart" or "ingenic,jz4780-uart"
+- reg : offset and length of the register set for the device.
+- interrupts : should contain uart interrupt.
+- clocks : phandles to the module & baud clocks.
+- clock-names: tuple listing input clock names.
+ Required elements: "baud", "module"
+
+Example:
+
+uart0: serial@10030000 {
+ compatible = "ingenic,jz4740-uart";
+ reg = <0x10030000 0x100>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <9>;
+
+ clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
+ clock-names = "baud", "module";
+};
diff --git a/kernel/Documentation/devicetree/bindings/serial/mrvl,pxa-ssp.txt b/kernel/Documentation/devicetree/bindings/serial/mrvl,pxa-ssp.txt
index 669b8140d..d10cc06c0 100644
--- a/kernel/Documentation/devicetree/bindings/serial/mrvl,pxa-ssp.txt
+++ b/kernel/Documentation/devicetree/bindings/serial/mrvl,pxa-ssp.txt
@@ -10,7 +10,6 @@ Required properties:
mvrl,pxa168-ssp
mrvl,pxa910-ssp
mrvl,ce4100-ssp
- mrvl,lpss-ssp
- reg: The memory base
- dmas: Two dma phandles, one for rx, one for tx
diff --git a/kernel/Documentation/devicetree/bindings/serial/mtk-uart.txt b/kernel/Documentation/devicetree/bindings/serial/mtk-uart.txt
index 44152261e..2d47add34 100644
--- a/kernel/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/kernel/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -5,16 +5,25 @@ Required properties:
* "mediatek,mt8135-uart" for MT8135 compatible UARTS
* "mediatek,mt8127-uart" for MT8127 compatible UARTS
* "mediatek,mt8173-uart" for MT8173 compatible UARTS
+ * "mediatek,mt6795-uart" for MT6795 compatible UARTS
* "mediatek,mt6589-uart" for MT6589 compatible UARTS
* "mediatek,mt6582-uart" for MT6582 compatible UARTS
- * "mediatek,mt6577-uart" for all compatible UARTS (MT8173, MT6589, MT6582,
- MT6577)
+ * "mediatek,mt6580-uart" for MT6580 compatible UARTS
+ * "mediatek,mt6577-uart" for all compatible UARTS (MT8173, MT6795,
+ MT6589, MT6582, MT6580, MT6577)
- reg: The base address of the UART register bank.
- interrupts: A single interrupt specifier.
-- clocks: Clock driving the hardware.
+- clocks : Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+- clock-names:
+ - "baud": The clock the baudrate is derived from
+ - "bus": The bus clock for register accesses (optional)
+
+For compatibility with older device trees an unnamed clock is used for the
+baud clock if the baudclk does not exist. Do not use this for new designs.
Example:
@@ -22,5 +31,6 @@ Example:
compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart";
reg = <0x11006000 0x400>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&uart_clk>, <&bus_clk>;
+ clock-names = "baud", "bus";
};
diff --git a/kernel/Documentation/devicetree/bindings/serial/nxp,lpc1850-uart.txt b/kernel/Documentation/devicetree/bindings/serial/nxp,lpc1850-uart.txt
new file mode 100644
index 000000000..04e23e63e
--- /dev/null
+++ b/kernel/Documentation/devicetree/bindings/serial/nxp,lpc1850-uart.txt
@@ -0,0 +1,28 @@
+* NXP LPC1850 UART
+
+Required properties:
+- compatible : "nxp,lpc1850-uart", "ns16550a".
+- reg : offset and length of the register set for the device.
+- interrupts : should contain uart interrupt.
+- clocks : phandle to the input clocks.
+- clock-names : required elements: "uartclk", "reg".
+
+Optional properties:
+- dmas : Two or more DMA channel specifiers following the
+ convention outlined in bindings/dma/dma.txt
+- dma-names : Names for the dma channels, if present. There must
+ be at least one channel named "tx" for transmit
+ and named "rx" for receive.
+
+Since it's also possible to also use the of_serial.c driver all
+parameters from 8250.txt also apply but are optional.
+
+Example:
+uart0: serial@40081000 {
+ compatible = "nxp,lpc1850-uart", "ns16550a";
+ reg = <0x40081000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <24>;
+ clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
+ clock-names = "uartclk", "reg";
+};
diff --git a/kernel/Documentation/devicetree/bindings/serial/nxp,sc16is7xx.txt b/kernel/Documentation/devicetree/bindings/serial/nxp,sc16is7xx.txt
index 246c79566..fbfe53635 100644
--- a/kernel/Documentation/devicetree/bindings/serial/nxp,sc16is7xx.txt
+++ b/kernel/Documentation/devicetree/bindings/serial/nxp,sc16is7xx.txt
@@ -1,4 +1,5 @@
* NXP SC16IS7xx advanced Universal Asynchronous Receiver-Transmitter (UART)
+* i2c as bus
Required properties:
- compatible: Should be one of the following:
@@ -31,3 +32,39 @@ Example:
gpio-controller;
#gpio-cells = <2>;
};
+
+* spi as bus
+
+Required properties:
+- compatible: Should be one of the following:
+ - "nxp,sc16is740" for NXP SC16IS740,
+ - "nxp,sc16is741" for NXP SC16IS741,
+ - "nxp,sc16is750" for NXP SC16IS750,
+ - "nxp,sc16is752" for NXP SC16IS752,
+ - "nxp,sc16is760" for NXP SC16IS760,
+ - "nxp,sc16is762" for NXP SC16IS762.
+- reg: SPI chip select number.
+- interrupt-parent: The phandle for the interrupt controller that
+ services interrupts for this IC.
+- interrupts: Specifies the interrupt source of the parent interrupt
+ controller. The format of the interrupt specifier depends on the
+ parent interrupt controller.
+- clocks: phandle to the IC source clock.
+
+Optional properties:
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells: Should be two. The first cell is the GPIO number and
+ the second cell is used to specify the GPIO polarity:
+ 0 = active high,
+ 1 = active low.
+
+Example:
+ sc16is750: sc16is750@0 {
+ compatible = "nxp,sc16is750";
+ reg = <0>;
+ clocks = <&clk20m>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
diff --git a/kernel/Documentation/devicetree/bindings/serial/omap_serial.txt b/kernel/Documentation/devicetree/bindings/serial/omap_serial.txt
index 54c2a155c..7a71b5de7 100644
--- a/kernel/Documentation/devicetree/bindings/serial/omap_serial.txt
+++ b/kernel/Documentation/devicetree/bindings/serial/omap_serial.txt
@@ -4,6 +4,9 @@ Required properties:
- compatible : should be "ti,omap2-uart" for OMAP2 controllers
- compatible : should be "ti,omap3-uart" for OMAP3 controllers
- compatible : should be "ti,omap4-uart" for OMAP4 controllers
+- compatible : should be "ti,am4372-uart" for AM437x controllers
+- compatible : should be "ti,am3352-uart" for AM335x controllers
+- compatible : should be "ti,dra742-uart" for DRA7x controllers
- reg : address and length of the register space
- interrupts or interrupts-extended : Should contain the uart interrupt
specifier or both the interrupt
diff --git a/kernel/Documentation/devicetree/bindings/serial/pl011.txt b/kernel/Documentation/devicetree/bindings/serial/pl011.txt
index ba3ecb8cb..77863aefe 100644
--- a/kernel/Documentation/devicetree/bindings/serial/pl011.txt
+++ b/kernel/Documentation/devicetree/bindings/serial/pl011.txt
@@ -1,7 +1,7 @@
* ARM AMBA Primecell PL011 serial UART
Required properties:
-- compatible: must be "arm,primecell", "arm,pl011"
+- compatible: must be "arm,primecell", "arm,pl011", "zte,zx296702-uart"
- reg: exactly one register range with length 0x1000
- interrupts: exactly one interrupt specifier
@@ -19,7 +19,7 @@ Optional properties:
must correspond to the PCLK clocking the internal logic
of the block. Just listing one clock (the first one) is
deprecated.
-- clocks-names:
+- clock-names:
When present, the first clock listed must be named
"uartclk" and the second clock listed must be named
"apb_pclk"
diff --git a/kernel/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt b/kernel/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
index a2114c217..182777fac 100644
--- a/kernel/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
+++ b/kernel/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
@@ -26,6 +26,12 @@ Required properties:
Optional properties:
- dmas: Should contain dma specifiers for transmit and receive channels
- dma-names: Should contain "tx" for transmit and "rx" for receive channels
+- qcom,tx-crci: Identificator <u32> for Client Rate Control Interface to be
+ used with TX DMA channel. Required when using DMA for transmission
+ with UARTDM v1.3 and bellow.
+- qcom,rx-crci: Identificator <u32> for Client Rate Control Interface to be
+ used with RX DMA channel. Required when using DMA for reception
+ with UARTDM v1.3 and bellow.
Note: Aliases may be defined to ensure the correct ordering of the UARTs.
The alias serialN will result in the UART being assigned port N. If any
diff --git a/kernel/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/kernel/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
index ae73bb0e9..73f825e5e 100644
--- a/kernel/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+++ b/kernel/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -23,12 +23,15 @@ Required properties:
- "renesas,scifa-r8a7794" for R8A7794 (R-Car E2) SCIFA compatible UART.
- "renesas,scifb-r8a7794" for R8A7794 (R-Car E2) SCIFB compatible UART.
- "renesas,hscif-r8a7794" for R8A7794 (R-Car E2) HSCIF compatible UART.
+ - "renesas,scif-r8a7795" for R8A7795 (R-Car H3) SCIF compatible UART.
+ - "renesas,hscif-r8a7795" for R8A7795 (R-Car H3) HSCIF compatible UART.
- "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART.
- "renesas,scifb-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFB compatible UART.
- "renesas,scif" for generic SCIF compatible UART.
- "renesas,scifa" for generic SCIFA compatible UART.
- "renesas,scifb" for generic SCIFB compatible UART.
- "renesas,hscif" for generic HSCIF compatible UART.
+ - "renesas,sci" for generic SCI compatible UART.
When compatible with the generic version, nodes must list the
SoC-specific version corresponding to the platform first followed by the
@@ -44,6 +47,11 @@ Required properties:
Note: Each enabled SCIx UART should have an alias correctly numbered in the
"aliases" node.
+Optional properties:
+ - dmas: Must contain a list of two references to DMA specifiers, one for
+ transmission, and one for reception.
+ - dma-names: Must contain a list of two DMA names, "tx" and "rx".
+
Example:
aliases {
serial0 = &scifa0;
@@ -56,4 +64,6 @@ Example:
interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
clock-names = "sci_ick";
+ dmas = <&dmac0 0x21>, <&dmac0 0x22>;
+ dma-names = "tx", "rx";
};
diff --git a/kernel/Documentation/devicetree/bindings/serial/sirf-uart.txt b/kernel/Documentation/devicetree/bindings/serial/sirf-uart.txt
index f0c39261c..67e2a0aeb 100644
--- a/kernel/Documentation/devicetree/bindings/serial/sirf-uart.txt
+++ b/kernel/Documentation/devicetree/bindings/serial/sirf-uart.txt
@@ -2,8 +2,7 @@
Required properties:
- compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart",
- "sirf,atlas7-uart" or "sirf,atlas7-bt-uart" which means
- uart located in BT module and used for BT.
+ "sirf,atlas7-uart" or "sirf,atlas7-usp-uart".
- reg : Offset and length of the register set for the device
- interrupts : Should contain uart interrupt
- fifosize : Should define hardware rx/tx fifo size
@@ -33,15 +32,3 @@ usp@b0090000 {
rts-gpios = <&gpio 15 0>;
cts-gpios = <&gpio 46 0>;
};
-
-for uart use in BT module,
-uart6: uart@11000000 {
- cell-index = <6>;
- compatible = "sirf,atlas7-bt-uart", "sirf,atlas7-uart";
- reg = <0x11000000 0x1000>;
- interrupts = <0 100 0>;
- clocks = <&clks 138>, <&clks 140>, <&clks 141>;
- clock-names = "uart", "general", "noc";
- fifosize = <128>;
- status = "disabled";
-}
diff --git a/kernel/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt b/kernel/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt
index 289c40ed7..12bbe9f22 100644
--- a/kernel/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt
+++ b/kernel/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt
@@ -15,6 +15,9 @@ The supplying peripheral clock can also be handled, needing a second property
Required elements: "baudclk", "apb_pclk"
Optional properties:
+- snps,uart-16550-compatible : reflects the value of UART_16550_COMPATIBLE
+ configuration parameter. Define this if your UART does not implement the busy
+ functionality.
- resets : phandle to the parent reset controller.
- reg-shift : quantity to shift the register offsets by. If this property is
not present then the register offsets are not shifted.
diff --git a/kernel/Documentation/devicetree/bindings/serial/uniphier-uart.txt b/kernel/Documentation/devicetree/bindings/serial/uniphier-uart.txt
new file mode 100644
index 000000000..0b3892a7a
--- /dev/null
+++ b/kernel/Documentation/devicetree/bindings/serial/uniphier-uart.txt
@@ -0,0 +1,23 @@
+UniPhier UART controller
+
+Required properties:
+- compatible: should be "socionext,uniphier-uart".
+- reg: offset and length of the register set for the device.
+- interrupts: a single interrupt specifier.
+- clocks: phandle to the input clock.
+
+Optional properties:
+- fifo-size: the RX/TX FIFO size. Defaults to 64 if not specified.
+
+Example:
+ aliases {
+ serial0 = &serial0;
+ };
+
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ clocks = <&uart_clk>;
+ fifo-size = <64>;
+ };