summaryrefslogtreecommitdiffstats
path: root/kernel/Documentation/devicetree/bindings/reset/sirf,rstc.txt
diff options
context:
space:
mode:
Diffstat (limited to 'kernel/Documentation/devicetree/bindings/reset/sirf,rstc.txt')
-rw-r--r--kernel/Documentation/devicetree/bindings/reset/sirf,rstc.txt42
1 files changed, 42 insertions, 0 deletions
diff --git a/kernel/Documentation/devicetree/bindings/reset/sirf,rstc.txt b/kernel/Documentation/devicetree/bindings/reset/sirf,rstc.txt
new file mode 100644
index 000000000..0505de742
--- /dev/null
+++ b/kernel/Documentation/devicetree/bindings/reset/sirf,rstc.txt
@@ -0,0 +1,42 @@
+CSR SiRFSoC Reset Controller
+======================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: Should be "sirf,prima2-rstc" or "sirf,marco-rstc"
+- reg: should be register base and length as documented in the
+ datasheet
+- #reset-cells: 1, see below
+
+example:
+
+rstc: reset-controller@88010000 {
+ compatible = "sirf,prima2-rstc";
+ reg = <0x88010000 0x1000>;
+ #reset-cells = <1>;
+};
+
+Specifying reset lines connected to IP modules
+==============================================
+
+The reset controller(rstc) manages various reset sources. This module provides
+reset signals for most blocks in system. Those device nodes should specify the
+reset line on the rstc in their resets property, containing a phandle to the
+rstc device node and a RESET_INDEX specifying which module to reset, as described
+in reset.txt.
+
+For SiRFSoC, RESET_INDEX is just reset_bit defined in SW_RST0 and SW_RST1 registers.
+For modules whose rest_bit is in SW_RST0, its RESET_INDEX is 0~31. For modules whose
+rest_bit is in SW_RST1, its RESET_INDEX is 32~63.
+
+example:
+
+vpp@90020000 {
+ compatible = "sirf,prima2-vpp";
+ reg = <0x90020000 0x10000>;
+ interrupts = <31>;
+ clocks = <&clks 35>;
+ resets = <&rstc 6>;
+};