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Diffstat (limited to 'kernel/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt')
-rw-r--r-- | kernel/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/kernel/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/kernel/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt new file mode 100644 index 000000000..98d198396 --- /dev/null +++ b/kernel/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt @@ -0,0 +1,69 @@ +* Marvell PXA GPIO controller + +Required properties: +- compatible : Should be "intel,pxa25x-gpio", "intel,pxa26x-gpio", + "intel,pxa27x-gpio", "intel,pxa3xx-gpio", + "marvell,pxa93x-gpio", "marvell,mmp-gpio", + "marvell,mmp2-gpio" or marvell,pxa1928-gpio. +- reg : Address and length of the register set for the device +- interrupts : Should be the port interrupt shared by all gpio pins. + There're three gpio interrupts in arch-pxa, and they're gpio0, + gpio1 and gpio_mux. There're only one gpio interrupt in arch-mmp, + gpio_mux. +- interrupt-names : Should be the names of irq resources. Each interrupt + uses its own interrupt name, so there should be as many interrupt names + as referenced interrupts. +- interrupt-controller : Identifies the node as an interrupt controller. +- #interrupt-cells: Specifies the number of cells needed to encode an + interrupt source. +- gpio-controller : Marks the device node as a gpio controller. +- #gpio-cells : Should be one. It is the pin number. + +Example for a MMP platform: + + gpio: gpio@d4019000 { + compatible = "marvell,mmp-gpio"; + reg = <0xd4019000 0x1000>; + interrupts = <49>; + interrupt-names = "gpio_mux"; + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <1>; + }; + +Example for a PXA3xx platform: + + gpio: gpio@40e00000 { + compatible = "intel,pxa3xx-gpio"; + reg = <0x40e00000 0x10000>; + interrupt-names = "gpio0", "gpio1", "gpio_mux"; + interrupts = <8 9 10>; + gpio-controller; + #gpio-cells = <0x2>; + interrupt-controller; + #interrupt-cells = <0x2>; + }; + +* Marvell Orion GPIO Controller + +Required properties: +- compatible : Should be "marvell,orion-gpio" +- reg : Address and length of the register set for controller. +- gpio-controller : So we know this is a gpio controller. +- ngpio : How many gpios this controller has. +- interrupts : Up to 4 Interrupts for the controller. + +Optional properties: +- mask-offset : For SMP Orions, offset for Nth CPU + +Example: + + gpio0: gpio@10100 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x10100 0x40>; + ngpio = <32>; + interrupts = <35>, <36>, <37>, <38>; + }; |