diff options
Diffstat (limited to 'kernel/Documentation/devicetree/bindings/arm/pmu.txt')
| -rw-r--r-- | kernel/Documentation/devicetree/bindings/arm/pmu.txt | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/kernel/Documentation/devicetree/bindings/arm/pmu.txt b/kernel/Documentation/devicetree/bindings/arm/pmu.txt index 3b5f5d108..97ba45af0 100644 --- a/kernel/Documentation/devicetree/bindings/arm/pmu.txt +++ b/kernel/Documentation/devicetree/bindings/arm/pmu.txt @@ -7,7 +7,10 @@ representation in the device tree should be done as under:- Required properties: - compatible : should be one of + "apm,potenza-pmu" "arm,armv8-pmuv3" + "arm.cortex-a57-pmu" + "arm.cortex-a53-pmu" "arm,cortex-a17-pmu" "arm,cortex-a15-pmu" "arm,cortex-a12-pmu" @@ -26,13 +29,19 @@ Required properties: Optional properties: -- interrupt-affinity : Valid only when using SPIs, specifies a list of phandles - to CPU nodes corresponding directly to the affinity of +- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU + nodes corresponding directly to the affinity of the SPIs listed in the interrupts property. - This property should be present when there is more than + When using a PPI, specifies a list of phandles to CPU + nodes corresponding to the set of CPUs which have + a PMU of this type signalling the PPI listed in the + interrupts property. + + This property should be present when there is more than a single SPI. + - qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd events. |