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| author |   Yang Zhang <yang.z.zhang@intel.com> | 2015-08-28 09:58:54 +0800 |
|---|---|---|
| committer | Yang Zhang <yang.z.zhang@intel.com> | 2015-09-01 12:44:00 +0800 |
| commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
| tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/tests/tcg/xtensa/Makefile | |
| parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) | |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/tests/tcg/xtensa/Makefile')
| -rw-r--r-- | qemu/tests/tcg/xtensa/Makefile | 92 |
1 files changed, 92 insertions, 0 deletions
diff --git a/qemu/tests/tcg/xtensa/Makefile b/qemu/tests/tcg/xtensa/Makefile new file mode 100644 index 000000000..522a63e36 --- /dev/null +++ b/qemu/tests/tcg/xtensa/Makefile @@ -0,0 +1,92 @@ +-include ../../../config-host.mak + +CORE=dc232b +CROSS=xtensa-$(CORE)-elf- + +ifndef XT +SIM = ../../../xtensa-softmmu/qemu-system-xtensa +SIMFLAGS = -M sim -cpu $(CORE) -nographic -semihosting $(EXTFLAGS) -kernel +SIMDEBUG = -s -S +else +SIM = xt-run +SIMFLAGS = --xtensa-core=DC_B_232L --exit_with_target_code $(EXTFLAGS) +SIMDEBUG = --gdbserve=0 +endif + +HOST_CC = gcc +CC = $(CROSS)gcc +AS = $(CROSS)gcc -x assembler-with-cpp +LD = $(CROSS)ld + +XTENSA_SRC_PATH = $(SRC_PATH)/tests/tcg/xtensa +INCLUDE_DIRS = $(XTENSA_SRC_PATH) $(SRC_PATH)/target-xtensa/core-$(CORE) +XTENSA_INC = $(addprefix -I,$(INCLUDE_DIRS)) + +LDFLAGS = -Tlinker.ld + +CRT = crt.o vectors.o + +TESTCASES += test_b.tst +TESTCASES += test_bi.tst +#TESTCASES += test_boolean.tst +TESTCASES += test_break.tst +TESTCASES += test_bz.tst +TESTCASES += test_cache.tst +TESTCASES += test_clamps.tst +TESTCASES += test_extui.tst +TESTCASES += test_fail.tst +TESTCASES += test_interrupt.tst +TESTCASES += test_loop.tst +TESTCASES += test_mac16.tst +TESTCASES += test_max.tst +TESTCASES += test_min.tst +TESTCASES += test_mmu.tst +TESTCASES += test_mul16.tst +TESTCASES += test_mul32.tst +TESTCASES += test_nsa.tst +ifdef XT +TESTCASES += test_pipeline.tst +endif +TESTCASES += test_quo.tst +TESTCASES += test_rem.tst +TESTCASES += test_rst0.tst +TESTCASES += test_s32c1i.tst +TESTCASES += test_sar.tst +TESTCASES += test_sext.tst +TESTCASES += test_shift.tst +TESTCASES += test_sr.tst +TESTCASES += test_timer.tst +TESTCASES += test_windowed.tst + +all: build + +linker.ld: $(XTENSA_SRC_PATH)/linker.ld.S + $(HOST_CC) $(XTENSA_INC) -E -P $< -o $@ + +%.o: $(XTENSA_SRC_PATH)/%.c + $(CC) $(XTENSA_INC) $(CFLAGS) -c $< -o $@ + +%.o: $(XTENSA_SRC_PATH)/%.S + $(CC) $(XTENSA_INC) $(ASFLAGS) -c $< -o $@ + +%.tst: %.o linker.ld $(XTENSA_SRC_PATH)/macros.inc $(CRT) Makefile + $(LD) $(LDFLAGS) $(NOSTDFLAGS) $(CRT) $< -o $@ + +build: $(TESTCASES) + +check: $(addprefix run-, $(TESTCASES)) + +run-%.tst: %.tst + $(SIM) $(SIMFLAGS) ./$< + +run-test_fail.tst: test_fail.tst + ! $(SIM) $(SIMFLAGS) ./$< + +debug-%.tst: %.tst + $(SIM) $(SIMDEBUG) $(SIMFLAGS) ./$< + +host-debug-%.tst: %.tst + gdb --args $(SIM) $(SIMFLAGS) ./$< + +clean: + $(RM) -fr $(TESTCASES) $(CRT) linker.ld |