diff options
author | 2015-08-28 09:58:54 +0800 | |
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committer | 2015-09-01 12:44:00 +0800 | |
commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/tests/tcg/mips/mips64-dsp/precr_sra_r_qh_pw.c | |
parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/tests/tcg/mips/mips64-dsp/precr_sra_r_qh_pw.c')
-rw-r--r-- | qemu/tests/tcg/mips/mips64-dsp/precr_sra_r_qh_pw.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/qemu/tests/tcg/mips/mips64-dsp/precr_sra_r_qh_pw.c b/qemu/tests/tcg/mips/mips64-dsp/precr_sra_r_qh_pw.c new file mode 100644 index 000000000..734ac322e --- /dev/null +++ b/qemu/tests/tcg/mips/mips64-dsp/precr_sra_r_qh_pw.c @@ -0,0 +1,40 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt; + long long res; + + rt = 0x8765432187654321; + rs = 0x1234567812345678; + + res = 0x4321432156785678; + + __asm + ("precr_sra_r.qh.pw %0, %1, 0x0\n\t" + : "=r"(rt) + : "r"(rs) + ); + + if (rt != res) { + printf("precr_sra_r.qh.pw error\n"); + return -1; + } + + rt = 0x8765432187654321; + rs = 0x1234567812345678; + + res = 0x5432543245684568; + + __asm + ("precr_sra_r.qh.pw %0, %1, 0x4\n\t" + : "=r"(rt) + : "r"(rs) + ); + + if (rt != res) { + printf("precr_sra_r.qh.pw error\n"); + return -1; + } + return 0; +} |