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author | Yang Zhang <yang.z.zhang@intel.com> | 2015-08-28 09:58:54 +0800 |
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committer | Yang Zhang <yang.z.zhang@intel.com> | 2015-09-01 12:44:00 +0800 |
commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/tests/tcg/mips/mips64-dsp/head.S | |
parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/tests/tcg/mips/mips64-dsp/head.S')
-rw-r--r-- | qemu/tests/tcg/mips/mips64-dsp/head.S | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/qemu/tests/tcg/mips/mips64-dsp/head.S b/qemu/tests/tcg/mips/mips64-dsp/head.S new file mode 100644 index 000000000..9a099ae42 --- /dev/null +++ b/qemu/tests/tcg/mips/mips64-dsp/head.S @@ -0,0 +1,16 @@ +/* + * Startup Code for MIPS64 CPU-core + * + */ +.text +.globl _start +.align 4 +_start: + ori $2, $2, 0xffff + sll $2, $2, 16 + ori $2, $2, 0xffff + mtc0 $2, $12, 0 + jal main + +end: + b end |